1. General description
The TEA19161T is a fully digital controller for high-efficiency resonant power supplies.
Together with the TEA19162T PFC controller and the TEA1995T dual SR controller, a
complete resonant power supply can be built which is easy to design and has a very low
component count. This power supply meets the efficiency regulations of Energy Star, the
Department of Energy (DoE), the Eco-design directive of the European Union, the
European Code of Conduct, and other guidelines. So, any auxiliary low-power supply can
be omitted.
In contrast to traditional resonant topologies, the TEA19161T (LLC) shows a high
efficiency at low loads due to the newly introduced low-power mode. This mode operates
in the power region between continuous switching (also called high-power mode) and
burst mode.
Because the TEA19161T is regulated via the primary capacitor voltage, it has accurate
information about the power delivered to the output. The measured output power defines
the mode of operation (burst mode, low-power mode or high-power mode). A
configuration pin can easily set the transition levels of the operating modes.
The TEA19161T contains a low-voltage die with a fully digital contro ller for output power
control, start-up, initializations, and protections. These protections include OverCurrent
Protection (OCP), OverVoltage Protection (OVP), Open-Loop Protection (OLP), and
Capacitive Mode Regulation (CMR). It also contains a high-voltage Silicon-On-Insulator
(SOI) controller for high-voltage start-up, integrated drivers, level shifter, protections, and
circuitry assuring zero-voltage switching.
The TEA19161T is designed to cooperate with the TEA19162T Power Factor Control
(PFC) controller. For communications about start-up and protections, the TEA19161T
contains a digital control interface. The digital control enables a fast latch reset
mechanism. It maximizes the overall system efficiency at low output power levels by
setting the TEA19162T to operate in burst mode.
The TEA19161T/TEA19162T/TEA1995T combination gives an easy to design, highly
efficient and reliable power supply, providing 90 W to 500 W, with a minimum of external
components. The system provides a very low no-load input power (< 75 mW ; tot al system
including the TEA19161T/TEA19162T/TEA1995T combination) and high efficiency from
minimum to maximum load. So, any addition al low-power su pply can be o mitted, ensuring
a significant system cost saving and highly simplified power supply design.
TEA19161T
Digital controller for high-efficiency resonant power supply
Rev. 1 — 10 March 2016 Product data sheet
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 2 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
2. Features and benefits
2.1 Distinctive features
Complete functionality as a combination with TEA19162T
Integrated high-voltage start-up
Integrated high-voltage Level Shifter (LS)
Extremely fast start-up (< 500 ms at Vmains =100V(AC))
Continuously VSUPIC regulation via the SUPHV pin during start-up and protection,
allowing minimum SUPIC capacitor values
Operating frequencies are outside the audible area at all operating mode s
Integrated soft start
Power good function
Maximum 500 kHz half-bridge switching frequency
2.2 Green features
Extremely high efficiency from low load to high load
Compliant with Energy using Product directive (EuP) lot 6
Excellent no-load input power (< 75 mW for TEA19161T/TEA19162T/TEA1995T
combination)
Regulated low optocurrent, enabling low no-load power consumption
Very low supply current during non-switching state in burst mode
Transition between different operation modes (high-power/low-power/burst mode)
occur at integrated, externally adjustable power levels
Adaptive non-overlap time
2.3 Protection features
Supply UnderVoltage Protection (UVP)
OverPower Protection (OPP)
Integrated adjustable overpower time-out
Adjustable latch or restart fu nction for OverPower Protection
On-chip OverTemperature Protection (OTP)
Capacitive Mod e Regulation (CMR)
Accurate OverVoltage Protection (OVP)
Maximum on-time protection for low-side and high-side driver output
OverCurrent Protection (OCP)
Disable input
3. Applications
Desktop and all-in-one PCs
LCD television
Notebook adapter
Printers
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 3 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
4. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
TEA19161T SO16 plastic small outline package; 16 leads; body width 3.9 mm; body thickness
1.47 mm SOT109-3
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xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 4 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
5. Block diagram
Fig 1. Block diagram
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 5 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. TEA19161T pin configuration (SOT109-3)
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Table 2. Pin description
Symbol Pin Description
SUPIC 1 input supply voltage and output of intern al HV start-up source; externally connected to an auxiliary
winding of the LLC via a diode or to an external DC supply
SNSFB 2 output voltage regulation feedback sense input; externally connected to an optocoupler
SNSOUT 3 sense input for setting the burst frequency and monitoring the LLC output voltage; externally via a
resistive divider and a diode connected to the auxiliary winding
GND 4 ground
SUPREG 5 regulated SUPREG IC supply; internal regula tor output; input for drivers; externally connected to
SUPREG buffer capacitor
GATELS 6 LLC low-side MOSFET gate driver output
n.c. 7 not connected
SUPHV 8 internal HV start-up source high-voltage supply input; externall y connected to (PFC) boost voltage
GATEHS 9 LLC high-side MOSFET gate driver output
SUPHS 10 high-side driver supply input; externally connected to bootstrap capacitor (CSUPHS)
HB 11 low-level reference for high-side driver and input for half-bridge slope detection; externally connected to
half-bridge node HB between the LLC MOSFETs
n.c. 12 no t co nn e c te d
SNSSET 13 settings for transition levels high/low powe r mode and low-powe r /burst mode, overpower level,
overpower time-out, and restart or latched. Output of the power good signal.
SNSCUR 14 LLC current sense input; externally connected to the resonant current sense resistor
SNSCAP 15 LLC capacitor voltage sense input; externally connected to divider across LLC capacitor
SNSBOOST 16 sense input for boost voltage; output for PFC burst control; externally connected to resistive divided
boost voltage
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 6 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
7. Functional description
7.1 Supply voltages
The TEA19161T includes:
•A high-voltage supply pin for start-up (SUPHV)
•A general supply to be connected to an external auxiliary winding (SUPIC pin)
•An accurate regulated voltage (SUPREG pin)
•A floating supply for the high-side driver (SUPHS pin)
7.1.1 Start-up and supply voltage
Initially, the capacitors on the SUPIC and SUPREG pins are charged via the SUPHV pin.
The SUPHV pin is connected to the output voltage of a PFC via an external resistor.
Internally, a high-voltage series switch is located between the SUPHV and SUPIC pins.
From the SUPIC pin, the SUPREG pin is supplied using a line ar reg u lat or (see Figure 3).
Initially, when the voltage on the SUPIC pin is below the reset level VrstSUPIC) (3.5 V), the
SUPIC charge current is internally limited to Ilim(SUPHV) (0.75 mA). In this way, the
dissipation is limited when SUPIC is shorted to ground. When the voltage on the SUPIC
pin exceeds Vrst(SUPIC), the internal switch is closed.
To limit the IC power dissipation, an external resistor (RSUPHV) is required to reduce the
voltage drop between the SUPHV and SUPIC pins when charging the SUPIC cap acitor.
RSUPHV must be dimensioned such that the maximum current is limited to below limiting
value ISUPHV (20 mA) and it can handle the required power dissipation. The maximum
power dissipation of the external resistor can be reduced by using several resistors in
series.
Fig 3. TEA19161T HV start-up
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 7 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
When the SUPIC reaches the Vstart(SUPIC) level (19.1 V), it is continuously regulated to this
start level with a hysteresis (Vstart(hys)SUPIC; 0.7 V). It activates the switch between the
SUPHV and SUPIC pins when the SUPIC voltage drops to below
Vstart(SUPIC) +V
start(hys)SUPIC. It deactivates the switch when it exceeds Vstart(SUPIC). When
start-up is complete and the LLC controller is operating, the LLC transformer auxiliary
winding supplies the SUPIC pin. In this operational state, the HV start-up source is
disabled (see Figure 4).
When the system enters th e protection mode, the SUPIC pin is also regulate d to the start
level. During the non-switching period of the burst mode, the system also activates the
switch between the SUPHV and SUPIC pins when the SUPIC voltage drops below
Vlow(SUPIC). It regulates the voltage with a hysteresis of Vlow(hys)SUPIC. In this way, the
system avoids tha t th e SU PIC undervoltage protection (Vuvp(SUPIC)) is triggered because
of a long non-switching period in burst mode.
Fig 4. Start-up sequence and normal operation
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 8 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
7.1.2 Regulated supply (SUPREG pin)
The voltage range on the SUPIC pin exceeds that of the maximum external M OSFETs
gate-source voltage. So, the TEA19161T incorporates an integrated series stabilizer. The
series stabilizer creates an accurate regulated voltage (Vintregd(SUPREG) =11V) at the
buffer capacitor CSUPREG. The stabilized voltage is used to:
•Supply the internal low-side LLC driver
•Supply the internal high-side driver using external components
•As a reference voltage for optional external circuits
To ensure that the external MOSFETs receive sufficient gate drive, the voltage on the
SUPREG pin must reach Vuvp(SUPREG) before the system starts switching. If the SUPREG
voltage drops to below this undervoltage protection level, the system restarts .
7.1.3 High-side driver floating supply (SUPHS pin)
External bootstrap buffer capacitor CSUPHS supplies the high-side driver. The bootstrap
capacitor is connected between the high-side dr iver supply, the SUPHS pin, and the
half-bridge node, HB. CSUPHS is charged from the SUPREG pin using an external diode
DSUPHS (see Figure 27).
Careful selection of the appropriate diode minimizes the voltage dr op between the
SUPREG and SUPHS pins, especially when large MOSFETs and high switching
frequencies are used. A lar ge voltage drop across the diode reduces the gate drive of the
high-side MOSFET.
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 9 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
7.2 System start-up
Figure 5 shows the flow diagram corresponding with Figure 4.
When the SUPIC or SUPREG pins drop to below their stop le vels, the TEA19161 T enters
the no supply state. It r echarges the SUPIC an d SUPREG pin s to their start levels via the
SUPHV pin. When the st art levels are reached, measuring th e external resist ances on the
SNSSET, SNSOUT, and GATELS pins initializes the settings.
During the no supply and read out settings states, the SNSBOOST pin is pulled low,
disabling the TEA19162T PFC. When the settings have been defined, the SNSBOOST
pin is released and the PFC starts up. When the SNSBOOST reaches the minimum level
Vstart(SNSBOOST), the LLC s tarts switching.
When a small optocurrent is detected (ISNSFB <I
reg(SNSFB)), the output voltage is close to
its regulation level. As the SUPIC pin must then be supplied via the primary auxiliary
winding, charging via the SUPHV is disabled.
Fig 5. TEA19161T L LC co ntroller flow diagram
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 10 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
7.3 LLC system regulation
A typical resonant controller regulates the output power by adapting the operating
frequency.
If the power drops and so the voltage of the LLC converter exceeds the targeted
regulation level (12 V or 19.5 V typical), the optocurrent increases and the voltage at the
SNSFB decreases (see Figure 6). The resonant controller then increases the frequency
according to its internal frequency control curve. Because of the higher frequency, the
power to the output is reduced and the output voltage drops. If th e output voltage
becomes too low, the controller lowers the system frequ ency, increasing the outp ut power .
In this way, the system regulates the output power to the required leve l.
As a small change in frequency gives a significant change in output power, frequency
control has a high ga in of the control loop. To increase the efficiency at low loads, most
converters switch to burst mode as soon as the output power is below a minimum level.
The burst mode level is mostly derived from the voltage on the SNSFB pin. For a
frequency controlled resonant converter, it implies that the burst mode is entered at a
certain frequency instead of at a certain load. A small variation of the resonant
components then results in a significant variat ion in power level at which the burst mode is
activated.
In the TEA19161T, the control mechanism is different. The advantage is a constant gain
of the control loop and a burst mode which is derived from the output power. The
TEA19161T does not regulate the output power by adjusting the frequency but by the
voltage across the primary capacitor.
Fig 6. Resonant frequenc y controller
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 11 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
The input power (re la te d to the ou tp ut pow er ) of a re sona nt converter can be calcu la ted
with Equation 1:
(1)
Equation 1 shows that the input power has a linear relation ship with the cap a citor voltage
difference VCr.
Figure 7 shows an alternative explanation of the linear relationship between the input
power and the energy stored in the resonant capacitor.
When the high-side switch is on, a primary current is flowing through the transformer and
resonant capacitor Cr as indicated by the red line. Half the energy the input delivers is
transferre d to the ou tp ut . Th e ot he r ha lf cha r ge s res on a nt capacitor C r. The voltage
across the reso na nt capacito r increases.
When the high-side switch is off and the low-side switch is on, the energy which is stored
in resonant capacitor Cr is transferr ed to the output and it s voltage decreases. In this way,
the linear relationship between the increase of the resonant capacitor voltage and the
output power can be seen.
Although the TEA19161T uses the primary cap acitor voltage as a re gulation parameter,
all application values, like the resonant inductances, resonant capacitor, and primary
MOSFETs remain unchanged compared to a frequency controlled LLC converter. A
secondary TL431 circuitry in combination with an optocoupler connected to the primary
SNSFB pin continuous ly regu late s th e ou tp ut voltage.
Fig 7. Linear relationship between input power and energy stored in Cr
Pin Vboost Iboost
Vboost VCr Crfsw
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 12 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
7.3.1 Output power regulation loop
Figure 8 shows the output power regulation loop of Vcap control as use d by th e
TEA19161T. Figure 9 shows a corresponding timing diagram.
When the divided reso nant capacitor voltage (VSNSCAP) exceeds the capacitor voltage
high level (Vhs(SNSCAP)), the high-side MOSFET is switched off (see Figure 9 (t1). After a
short delay, the low-side MOSFET is switched on. Because of the resonant current, the
resonant capacitor voltage initially increases further but eventually drop s.
Fig 8. Regulation loop Vcap control
Fig 9. Timi ng dia gram of the regu la tio n loop
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 13 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
When the divided capacitor voltage (VSNSCAP) drops to below the capacitor voltage low
level (Vls(SNSCAP)), the low-side MOSFET is switched off (see Figure 9 (t2)). After a short
delay, the high-side MOSFET is switched on. Figure 9 shows that the switching fr equency
is a result of this switching behavior. In a frequency controlled system, the frequency is a
control p arameter and the ou tput power is a result. The TEA19161T regulates the power
and the frequency is a result.
The difference between the high and low capacitor voltage level is a measure of the
delivered output power. The value of the primary optocurrent, defined by the secondary
TL431 circuitry, determines the difference between the high and low capacitor voltages.
Figure 9 also shows the behavior at a transient. If the output load increases, the current
pulled out of the SNSFB pin decreases. The result is that the TEA19161T increases the
high-level capacitor voltage and lowers the low-level capacitor voltage. According to
Equation 1, the output power increases an d eventually the output voltage increases to its
regulation level.
To minimize no-load input power of the system, the primary curre nt into the optocou pler is
continuously regulated to 85 A (see Section 7.5).
7.3.2 Output voltage start-up
The system controls the output power by regulating the primary VCr (see Section 7.3).
When the system is in regulation and the output voltage is stabilized, a small change in
VCr corresponds to a small change in the output current (see Equation 2).
(2)
However, before start-up, when the output voltage is around zero, a small capacitor
voltage increase (VCr) corresponds to a substantial output current increase. So, at
start-up, the divided VCr voltage (VSNSCAP) is slowly increased from a minimum value to
the regulation level. As a result, the system starts up at a higher frequency. The GATELS
resistor sets the starting value of the VSNSCAP.
Pout Vout Iout Vboost Iboost
VCr Crfsw Vboost
==
Iout Crfsw
Vboost
VCr
Vout
-------------
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Product data sheet Rev. 1 — 10 March 2016 14 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
7.4 Modes of operation
Figure 10 shows the control curve between the output power and the voltage difference
between the high and low capacitor voltage levels.
When the output power (Pout) is at its maximum, the low capacitor voltage level
(Vls(SNSCAP)) is at its minimum and the high capacitor voltage (Vhs(SNSCAP)) is at its
maximum level. According to Equation 1, the maximum VSNSCAP
(Vhs(SNSCAP) Vls(SNSCAP)), which is the divided VCr voltage, cor responds to the
maximum output powe r.
When the output load decreases, the VSNSCAP voltage decreases. As a result, the output
power decrease s an d th e ou tp ut voltage is regula ted . Th is mo d e is called hig h- p owe r
mode.
When the output power drops to below the tr ansition level (Pt(lp)), the system enters the
low-power mo de. External components can set the applied Pt(lp) level (see Section 7.7.3).
Fig 10. TEA19161T control curve
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 15 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
To compensate for the hold period, VSNSCAP is initially increased at entering the
low-power mode (see Section 7.4.2). In low-power mode, the output power is initially
regulated by ada pt ing VSNSCAP, until it reaches a minimum. Then, the output power is
regulated by lowering the duty cycle of the low-power mode with a fixed VSNSCAP until
the period time of a low-power cycle reaches a maximum (1 / flp(min)). The system enters
the burst mode (see Section 7.4.3).
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 16 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
7.4.1 High-power mode
In high-power mo de , the syste m op er ates as described in Section 7.3.1. Figure 11 shows
a flow diagram of the high-power mode.
Fig 11. High-powe r mo de f low dia gra m
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 17 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
When the system is off, GATELS is on and GATEHS is off. The external bootstrap buffer
capacitor (CSUPHS) is charged via the SUPREG pin and an external diode. The system
remains in this state for at least the minimum on-time (ton(min)) of GATELS. Before entering
the next state, one of the following conditions must be fulfilled:
•The VSNSCAP voltage drops to below the minimum VSNSCAP voltage (Vls(SNSCAP))
•The measured current exceeds the OCP level (see Section 7.6.6)
•The system is close to capacitive mode (see Section 7.6.5)
•The maximum on-time (t on(max)), a protection that maximizes the time the high-side or
low-side MOSFET is kept on, is exceeded.
In the next state, to avoid fa lse detection of the HB peak volt age, the system waits until the
minimum non-overlap time (tno(min)) is exceeded. When it is exceeded, the system starts
to detect the end (= peak voltage) of the HB node. When it detects the peak of the HB
node and the measured resonant current is negative (or zero), it enters the next state.
If the system does not detect a peak at the HB node, it also enter s the next state when the
maximum non-over lap time (tno(max)) is exceeded under the condition of a negative (or
zero) resona nt curr e nt.
Finally, the third and fourth states (see Figure 11) describe the GATEHS and GATEHS to
GATELS transition criteria which are the inverse of the first two states.
7.4.2 Low-power mode
At low loads, the operating frequency of a resonant converter increases. As a result, the
magnetization and switching losses increase. For this reason, the ef ficien cy of a resonant
converter drops at low loads. A newly intro duced low-power mode ensure s high efficiency
at lower loads as well.
When the output power drops to below the Pt(lp) level, the system enters the low-power
mode (see Figure 10 and Figure 12). It continues switching for 3 half-cycles (low-side,
high-side, low-side) with a fixed duty cycle of 67 %. To ensure a constant output powe r
level, it increases the energy per cycle (Vhs(SNSCAP) Vls(SNSCAP)) at the same time. So
1/3 of the time the converter is in a "hold" period. The result is a 33 % magnetization and
switching losses reduction.
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 18 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
As the system continuously tracks the primary capacitor voltage, it knows exactly when to
enter the "hold" period. It can also continue again at exactly the correct voltage and
current levels of the resonant converter. In this way, a "hold" period can be introduced
which reduces the magnetizat ion and switching losses without any additional losses. The
currents ID1 and ID2 (see Figure 12) are the secondary current s through d iodes D1 and D2
(see Figure 27).
When in the low-power mode the ou tput power is further reduced, the amount of en ergy
per cycle (= VSNSCAP) is reduced and the duty cycle remains the same (see Figure 13).
Fig 12. Timing diagram transition high-power mode to low-power mode
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 19 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
When, in low-power mode, the minimum energy per cycle is reached, the duty cycle
regulates the outp ut power (see Figure 14). Increa sing the “hold” period lowers the duty
cycle.
To avoid audible noise, the system reduces the duty cycle until the frequency reaches
flp(min) (23 kHz). If the output power is lowered further, the system enters the burst mode.
Fig 13. Low-power mode, lowering the energy per cycle (VSNSCAP)
Fig 14. Low-power mode, lowering the duty cycle
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 20 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
7.4.3 Burst mode
In burst mode, the system alternates between operating in low-power mode and an
extended hold state (see Figure 15). Because of this additional extended hold period, the
magnetization and switching losses are further reduced. So, the ef ficiency of the system is
increased.
Figure 15 shows that all operating frequencies are outside the audible area. The minimum
low-power frequency is 23 kHz. Within a low-power period, the system is switching at the
resonant frequency of the converter, which is typically between 50 kHz and 200 kHz.
The burst frequency (1 / tburst) is continuously regulated to a predefined value, which can
be set externally to 200 Hz, 400 Hz, 800 Hz or 1600 Hz. Isec is the secondary current
flowing through either diode D1 or D2 (see Figure 27).
When the primary optocurrent (ISNSFB) drops to below 106 A, a new burst-on period is
started. The end of the burst-on period depends on the calculated number of low-power
cycles. The number of low-po wer cycles within a bur st-on is continuo usly adjusted so that
the burst period is at least the period defined by the setting (see Figure 16).
The system continuously measur es the burst period from the sta rt of the previous burst-on
period to a new burst-on period. At t1, the measured burst period (tburst) equals the
required Tburst. So, the next number of low-power cycles equals the number of previous
low-power cycles. At a constant output power, the system expects that when the next
burst-on period has the same number of low-power cycles as the previous burst-on
period, the burst period (tburst) remains constant.
Fig 15. Burst mode
Fig 16. Burst mode: Regulating the number of low-power cycles
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Product data sheet Rev. 1 — 10 March 2016 21 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
At a positive transient (t2), a new low-power cycle is started immediately to minimize the
drop in output voltage. The measured time period, at time t2, is below the targeted burst
period. The sys te m incr e as es th e nu m be r of burst cycles. At t3, it measures the burst
period again. In this example, the burst period is still below the targeted burst period. So,
the system increases the number of low-power cycles again a nd again until the me asured
burst period equ als th e target burst period, which occu rs at t4.
7.5 Optobias regulation
In a typical application, the output voltage is sensed using a TL431 and connected to the
SNSFB pin of the TEA19161T via an optocoupler (see Figure 27). Because of the
behavior of the TL431, the current through the optocoupler is at the maximum level when
the output power is at the minimum level. It is therefore one of the most critical parameters
to achieve the required no-load input power. To achieve maximum efficiency at
low load/no-load, the TEA19161T continuously regulates the optocurrent to a low level
that is independent of the output load.
A very low optocurrent reduces the transient re sponse of the system, because of the
parasitic capacitance at the optocoupler collector. So, the TEA19161T applies a fixed
voltage at the SNSFB pin. It measures the current through the optocoupler which defines
the required output power. Via an additional internal circuitry, which adds an offset to the
required outp ut power, the optocurrent is co ntinuously (slowly) re gulated to the Ireg(SNSFB)
level (= 85 A). This level is independent of the output power.
At a positive load transient, the optocurrent initially decreases (see Figure 9; ISNSFB). The
TEA19161T immediately increases the VSNSCAP which again incre ase s th e ou tp ut
power.
Figure 17 shows that when the optocurrent decreases, the internal voltage across the
12 k resistor drops to below the targeted level of 1020 mV (= 85 A12 k). The
TEA19161T then slowly increases a n additional offse t at the power level (P). It continues
to increase the additional offset until the optocurrent reaches the target of 85 A. At a
negative transient, the additional offset to the power level is decrease d. As a re su lt, the
output voltage increases which again increases th e optocurrent. In this way, the
optocurrent is continuously regulated to the Ireg(SNSFB) level (see Figure 9).
Fig 17. Opto bia s regula tio n
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 22 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
The behavior of the internal circuitry conn ected to the SNSFB pin is the same as the
behavior of the tra ditional circuitry. The fixed volt age at the SNSFB pin and the continuous
regulation of the optocurrent level does no t influence the regu lation level. The adva nt age,
however, is a reduction in no-load input power and an optimization of the transient
response.
When the system operates in low-power mode at the minimum energy per cycle and at
minimum duty cycle, it can no longer reduce the optocurrent level to the Ireg(SNSFB) target
(85 A). If the output power decreases further and the optocurrent increases to above
the level of Istart(burst) (106 A), the burst mode is triggered. When the outp ut power drops
to below this level again, a new burst cycle is started (see Figure 15 and Figure 16).
7.6 Protections
Table 3 gives an overview of the available protections.
[1] Can be longer due to the sharing of the internal ADC converter.
[2] Latched implies that the system only restarts after a mains disconnection.
[3] Can be set by external components.
When the system is in a latched or safe restart protection, the SUPIC voltage is regulated
to its start level via the SUPHV pin.
7.6.1 Undervoltage protection SUPIC/SUPREG
When the voltage on the SUPIC pin or the SUPREG pin is below its undervoltage level
Vuvp(SUPIC) /V
uvp(SUPREG), the LLC converter stops switching. The capacitors at the
SUPIC and SUPREG pins are recharged via the SUPHV pin (see Figure 5). The
SNSBOOST pin is pulled low, disabling the PFC. When the supply voltages exceed their
start levels, the system restarts.
Table 3. Protection s
Protection Description Action PFC
UVP
SUPIC/SUPREG undervoltage protection
SUPIC/SUPREG pins LLC = off; recharge via SUPHV;
restart when VSUPIC >V
start(SUPIC)
and VSUPREG >V
start(SUPREG)
off
UVP SUPHS undervoltage protection SUPHS
pin GATEHS = off
UVP SNSBOOST unde rvoltage protection boost LLC = off; restart when
VSNSBOOST >V
start(SNSBOOST)
OVP output overvoltage protection output latched after 5 consecutive
cycles[1][2] off
CMR capacitive mode regulation system ensures that mode of
operation is inductive
OCP overcurrent protection switch off cycle-by-cycle; Af ter 5
consecutive cycles, it follows the
OPP setting.[2]
off
OTP overtemperature protection latched[2] off
OPP overpower protection latched[2]/safe restart[3] off
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Product data sheet Rev. 1 — 10 March 2016 23 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
7.6.2 Undervoltage protection SUPHS
To ensure a minimum drive voltage at the high-side driver output (GATEHS), this driver is
kept off when its voltage is below the minimum level (VSUPHS <V
rst(SUPHS)).
7.6.3 Undervoltage protection boost
The PFC output volta ge is measure d via a r esistive divide r connected to the SNSBOOST
pin. The voltage at the SNSBOOST pin must exceed the start level
(VSNSBOOST >V
start(SNSBOOST)) before the system is allowed to start switching.
When the system is operating and the voltage at the SNSBOOST pin drops to below the
minimum level (VSNSBOOST <V
uvp(SNSBOOST)), the LLC converter stop s switch ing. When it
exceeds the start level, it restarts.
7.6.4 Overvoltage protection
When the volt age at the SNSOUT pin exceeds the V ovp(SNSOUT) level for at least 5
consecutive switching cycles, the OVP protection is triggere d. The voltage at th e
SNSOUT pin is internally measured via an ADC converter. As the same ADC converter
toggles between measuring the SNSOUT and SNSBOOST pins (see Figure 1), there is
an additional delay before the OVP is triggered. OVP is a latched protection. The PFC is
disabled via the SNSBOOST pin .
7.6.5 Capacitive Mode Regulation (CMR)
The TEA19161T h as a Capacitive Mode Re gulation (CMR) which ensures that the syste m
is always operating in inductive mode and avoids operation in capacitive mode.
At lower input voltage or higher output power and depending on the resonant design, the
resonant current can already approach zero before the capacitor voltage reaches the
regulation leve l.
When the resonant current has changed polarity before the switches are turned off and
the other switch is turned on, hard switching occurs. This event is called capacitive mo de.
To avoid that the system operates in capacitive mode, the system also switches off the
high-side/low-side switch when the resonant cur rent approaches zero.
Figure 18 shows the signals that occur when a resonant converter is switching in CMR
mode. At t1 (and also at t3), the low-side switch is on while the resonant current
approaches zero before VSNSCAP reaches Vls(SNSCAP). At t2, the resonant current is also
close to changing polarity while the divided capacitor voltage (VSNSCAP) has not reached
the Vhs(SNSCAP) level yet. To avoid a turn-of f of the high-side switch at a negative current or
the low-side at a positive current, the system also turns off the high-side/low-side switch
when the primary current approaches zero. So at t2, the high-side switch is turned off
because the primary current is close to zero. At t3 (and also at t1), the low-side switch is
turned off, although VSNSCAP did not reach the regulation level (Vls(SNSCAP)) yet. The
primary current is measured via an external sense resistor connected to the SNSCUR pin.
The capacitive mode prot ec tio n levels ar e V reg(capm) (100 mV and +100 mV,
respectively).
In this mode, the amount of output power is reduced and the output voltage decreases.
The TEA19161T does not enter a so-called "capacitive mode protection", but avoids this
mode of operation.
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Product data sheet Rev. 1 — 10 March 2016 24 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
7.6.6 Overcurrent protection
The system measures the primary curren t continuously via a sense resistor connected to
the SNSCUR pin. If the measured voltage exceeds the overcurrent level (Vocp), the
correspond ing switch (GATEL S/GAT EHS) is turn ed off, but the system con tin uou s
switching. In this way, the primary current is limited to the OCP level. If the OCP level is
exceeded for 5 consecutive cycles (GATELS and/or GATEHS), the system stops
switching and enters the latched OCP protection mode. The PFC is disabled via the
SNSBOOST pin.
7.6.7 Overtemperature protection
When the internal junction temperature exceeds the Totp level, the overtem p er a tur e
protection is triggered. OTP is a latched protection which also disables the PFC.
Fig 18. Near capacitive mode switching
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 25 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
7.6.8 Overpower protection
The external capacitive/resistive divider connected to the SNSCAP pin must be chosen
such that:
•The voltage difference between Vhs(SNSCAP) and Vls(SNSCAP) equals Vopp(SNSCAP)
•The voltage difference between Vhs(SNSCAP) and Vls(SNSCAP) occurs at 125 % of the
maximum output power or at 175 %, depending on the settings
When the VSNSCAP (Vhs(SNSCAP) Vls(SNSCAP)) exceeds the Vopp(SNSCAP) voltage
difference, an internal counter is started. When this counter exceeds td(opp)
(50 ms/200 ms), the system enters a latched/safe restart protection as defined by the
external settings.
The voltage difference between Vhs(SNSCAP) and Vls(SNSCAP) is also limited to
Vth(max)SNSCAP, which then corresponds to an output power of 150 % or 200 %,
depending on th e set tin gs (see Figure 19). If the output of the LLC converter requires
additional power, the output voltage drops as the po wer delivered by the LL C co nver te r is
limited to 150 % or 200 %.
An additional option is to disable the overpower counter, using the external se ttings. In this
way, the overpower rating can be used as an extension of the typical power level.
Fig 19. TEA19161T overpower
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 26 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
7.7 External settings
Before the system starts switching, it read s th e ext er n al set tings. Using specific resistor
values at the GATELS, SNSSET, and SNSOUT pins, several internal settings can be
defined.
7.7.1 Burst period
Figure 20 shows how the intern al r egulated bur st frequ ency can be set using th e externa l
resistor connected to the SNSOUT pin.
The absolute value of the resistor connected between the SNSOUT pin and ground
(RSNSOUT1) defines the burst frequency. An accurate resistor of 1 % according to Table 4
is required. The OVP level can be set using r esistor RSNSOUT2.
A low burst frequency is best for minimum audible noise . However, a high burst frequency
minimizes the output voltage ripple.
7.7.2 General settings
Variables on the OPP function can be set using resistor RSNSSET1 conn ec te d to the
SNSSET pin (see Figure 21).
Fig 20. External setting of the burst frequency
Table 4. External setting of the bu rst frequency
RSNSOUT1 Burst frequency
22 k200 Hz
15 k400 Hz
10 k800 Hz
6.8 k1600 Hz
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Product data sheet Rev. 1 — 10 March 2016 27 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
When the measured value of RSNSSET1 <10k, the system assumes a shorted pin to
ground and the st art-up is inhibited. At a value o f 46.4 K, the system can of cont inuously
delivering the maximum power of 20 0 %.
The output power level at which the overpower timer is started can be set to 125 % or
175 %. Two corresponding timer values can be selected, 50 ms or 200 ms. Finally, the
value of RSNSSET1 (see Table 5) can set the be ha vio r of the overpo we r fu nc tion (eit he r a
1 s restart or latched). During this protection period, the SUPIC is regulated at its
Vstart(SUPIC) level.
7.7.3 Low-power mode/burst mode transition levels
To ensure the best ef ficiency, the system must enter the low-power mode and the burst
mode at high power levels. However, to ensure the best output ripple, these modes must
be entered at low-power levels. To choose the optimum level for a specific application, the
power transition levels at which the system enters the low-power mode and the burst
mode can be set extern ally.
Resistor RSNSSET2 defines the power levels at which the system enters the low-power
mode and the bu r st mo de . Table 6 gives an overview.
Table 5. General settings
RSNSSET1 (k)Power capability
level (%) OPP timer level
(%) End of power
good timer (ms) OPP timer (ms) Protection
< 10 no start-up
46.4 200 infinite
53.6 200 175 190 200 1 s restart
61.9 200 175 45 50 1 s restart
71.5 150 125 190 200 1 s restart
82.5 150 125 45 50 1 s restart
95.3 200 175 190 200 latched
110 200 175 45 50 latched
127 150 125 190 200 latched
147 150 125 45 50 latched
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Product data sheet Rev. 1 — 10 March 2016 28 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
[1] The values in this table are including the additional shift due to the internal (tPD(SNSCAP)) delay and a typical
external delay of 150 ns and 300 ns, respectively. When an external R + C network compensates these
delays, the levels in Table 6 can be lowered.
The power level at which the system en ters the burst mode also depends on the defined
burst period. In this way, the optimum between ef ficiency and outpu t volta ge ripple can be
chosen.
7.8 Power good function
The TEA19161T provides a po wer good function via the SNSSET pi n. At initialization, the
TEA19161T measures the resistors connected to the SNSSET pin to set internal
variables. After that, the pin is used for the power good function.
After the system has read the external set tings (see Figure 5), the SNSSET output is
active high, enabling an external MOSFET. A secondary po wer good signal can be pulled
low using an external optocoupler.
When the system enters the operating state (see Figure 5), the SNSSET output i s pulled
low and the external power good signal becomes active high. Any required delay can be
achieved via an external R/C network.
Table 6. External setting of the high-power/low-power and low-power/burst transition
levels
RSNSSET2
(k)High-power => low-power
(%)[1] Burst mode[1]
200 Hz (%) 400 Hz (%) 800 Hz (%) 1600 Hz (%)
125 9 9 9 9
6.8 25 12 12 12 12
15 37.5 9 9 9 10
27 37.5 12 12 12 13
47 50 9 10 11 12
82 50 12 13 15 17
180 62.5 9 10 12 14
open 62.5 12 15 17.5 20
a. Primary side b. Secondary side
Fig 22. Power good function
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 29 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
At low power good, the SNSSET output becomes active high when:
•The voltage on the SNSBOOST pin drops to below Vdet(SNSBOOST) (1.95 V)
•The OPP counter is at a value indicated in Table 5.
In this way, the secondary power good signal is pulled low at 5 ms or 10 ms before the
output is disabled.
When the system enters protection mo de (OVP, OCP, UVP or OTP), it pulls low the
SNSSET pin and stops switching immediately.
7.9 PFC/LLC communication protocol
The TEA19161T is designed to cooperate with the TEA1916 2T (PFC) in one system. The
TEA19161T and TEA19162T can be seen as a combination, split up into two packages.
All required functionality betwe en the two contr ollers is arranged via the combined SUPIC
and SNSBOOST pins.
7.9.1 Start-up
To ensure that at start-up the TEA1916 1T and TEA19162T are enab led at the same time,
the TEA19161T (LLC) pulls down the SNSBOOST pin to below the SNSBOOST short
protection lev el of th e PFC. T h e TE A19161T disables the TEA19162T (PFC)
(see Figure 23) until the system enters the PFC start-up phase (see Figure 5 and
Figure 23).
The SUPIC start levels and stop levels of the TEA19162T (PFC) are below the SUPIC
start levels and stop levels of the TEA19161T (LLC). When the SUPIC exceeds the start
level of the TEA19161T, both controllers are enabled.
In this way, both controllers are enabled/disabled at th e same SUPIC star t and stop levels.
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Product data sheet Rev. 1 — 10 March 2016 30 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
When the LLC reaches a minimum supply voltage level (Vrst(SUPIC); t1), the LLC pulls
down the SNSBOOST pin to disable the PFC.
At t2, the SUPIC reaches the start level o f the PFC converter. However, as the LLC pulls
low the SNSBOOST voltage to < the PFC short protection level, the PFC is still off. When
at t3 the SUPIC reach es the start level of the LLC, af ter the LLC h as read ou t the exte rnal
settings, the SNSBOOST voltage is released. It increases because of the connected
resistive divider which is connected to the PFC boost voltage. To ensure that the
SNSBOOST voltage is a representative of the Vboost voltage before the system actually
starts to switch, an additional delay (until t4) is built into the PFC control ler before it starts.
When at t5 the SNSBOOST voltage reaches the start level of the LLC, the LLC converter
starts to switch. At t6, the SUPIC is supplied via the primary auxiliary winding.
Fig 23. Start-up of the PFC and LLC
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 31 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
7.9.2 Protection
When a protection is triggered in either the PFC or LLC, it may also disable the other
converter. For example, if an OVP is detected at the LLC, both converters are latched.
Also, at initial st art-up, the PFC disables the LLC converter until the mains volt age detect s
the brownin leve l.
The PFC can disable the LLC converter by pulling down the SNSBOOST pin to below the
Vuvp(SNSBOOST) level of the LLC converter. The LLC can disable the PFC converter by
pulling down the SNSBOOST pin to below the short protection level of the PFC converter
SNSBOOST pin.
Table 3 in Section 7.6 gives an overview of protections in the LLC converter. It shows
which protections also disable the PFC.
Fig 24. System protection
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 32 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
The start-up period up to t3 is identical in Figure 23 and Figure 24. At t3, the LLC
converter releases the pu ll-down of the SNSBOOST pin. However , as the mains volt age is
below the brownin level, the PFC converter pulls low the SNSBOOST pin. When the
mains voltage exceeds the brownin level (t4), the SNSBOOST pin is released and
increases because of the resistive divider con nected between th e PFC bo ost voltage and
the SNSBOOST pin. To allow some external capacitance on the SNSBOOST pin, the PFC
converter waits until the SNSBOOS T voltage is stabilized.
At t5, the PFC converter starts to switch. At t6, the LLC converter also starts to switch, as
the SNSBOOST voltage reac he s th e V start(SNSBOOST) of the LLC converter.
At t7, the primary auxiliary winding takes over the supply of the SUPIC pin.
At t8, the LLC detects an OVP at the SNSOUT pin. After at least 5 consecutive OVP
cycles (t9), the LLC stops switching and pulls down the SNSBOOST pin. As a result, the
PFC also stops switching.
When either the PFC or LLC is in protection , the SUPIC pin is regulated to the Vstart(SUPIC)
via the SUPHV pin as soon as it drops below the Vstart(SUPIC) level.
7.9.3 Fast latch reset
The SUPIC pin is regulate d to the Vstart(SUPIC) level when a (latched) protection is
triggered. So, it can remain in this protection mode until the capacitor at the PFC output,
which the SUPHV is connected to, is discharged. Hence, it may remain in protection mode
for a long time after the mains is disconnected.
When protection modes are tested at mass-pro duction, a long reset time is not accepta ble
in most cases. So, a fast latch reset function is built into the PFC and the LLC. When the
mains is initially disconnected and then reconnected, all protections the PFC or the LLC
initiated are released again.
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 33 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
Before t1, the LLC is in a (latched) protection and pulls down the SNSBOOST pin, which
also disables the PFC.
When the mains voltage drops to below the brownout level for a minimum period of
td(mains)bo, the PFC enters the brownout protection mode. When the mains voltage
increases again to > the brownin level (t2) in the brownout protection mode, the PFC pulls
up the SNSBOOST voltage until it reaches the Vuvp(SNSBOOST) level of the LLC co nverter.
The LLC converter th en releases all protecti on modes and wait s until the SNSBOOST pin
exceeds its start level (Vstart(SNSBOOST)). After a waiting time, the PFC converter start s (t3),
followed by a st art-up of the LLC converter (t 4).
7.9.4 PFC burst mode
When the LLC operates in bu rst mod e and the du ty cycle of the burst is below 5 0 % for at
least 8 consecutive burst periods, the TEA19161T (LLC) sets the TEA19162T (PFC) in
burst mode as well. T he correspo nding output power leve l is then 50 % of the power level
at which the LLC enters the burst mode (see Table 6).
When the output powe r exceeds 75 % of the power level at which the LLC enters the bu rst
mode (see Table 6), the PFC burst is disabled again.
When the PFC burst is enabled, an additional current out of the SNSBOOST pin stops the
PFC from switching via a soft stop, so the audible noise is minimized (see Figure 26).
Fig 25. Fast latch reset
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 34 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
At t1, the current out of the LLC SNSBOOST pin ( I off(burst)) is activated and the vo ltage on
the SNSBOOST pin increases. When an external 100 k resistor (RSNSBOOST) is used
between the SNSBOOST pin and GND pin (see Figure 27), the SNSBOOST vo ltage
increase is approximately 640 mV (= Ioff(burst) *R
SNSBOOST). Because of this increase, the
SNSBOOST voltage is between the Vdet(L)SNSBOOST and Vdet(H)SNSBOOST levels of the
PFC (t2), so the soft stop of the PFC converter is started. At the end of the soft stop, the
PFC enters the energy safe state and stops switching (t3). Because of the continuous
operation of the LLC converter, even when the PFC is stopped, the PFC output capacitor
is discharged.
When the PFC boost cap acitor is discharged so much that the voltage on the SNSBOOST
pin has dropped 7 5 mV (Voff(burst); t4), the internal curr en t so urce in the LLC co nverte r is
switched off. Because of the negative voltage drop at the SNSBOOST pin, the PFC st ar t s
switching again. When VSNSBOOST exceeds the LLC Von(burst)max level (2.37 V) again, the
internal current source is reactivated and the PFC stops switching again (t1).
a. Block diagram
b. Timing diagram
Fig 26. PFC burst mode
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 35 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
8. Limiting values
Table 7. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Voltages
VSUPHV voltage on pin SUPHV maximum during mains surge;
not repetitive 0.4 +700 V
VSUPHS voltage on pin SUPHS VHB VHB +14 V
VHB voltage on pin HB maximum during mains surge;
not repetitive 3 +700 V
t<1s14 - V
VSUPIC voltage on pin SUPIC 0.4 +36 V
VSUPREG voltage on pin
SUPREG 0.4 +12 V
VGATEHS voltage on pin
GATEHS VHB 0.4 VSUPHS +0.4 V
VGATELS voltage on pin GATELS 0.4 VSUPREG +0.4 V
VSNSFB voltage on pin SNSFB 0.4 +12 V
VSNSOUT voltage on pin
SNSOUT 0.4 +12 V
VSNSSET voltage on pin
SNSSET 0.4 +12 V
VSNSCUR voltage on pin
SNSCUR 0.4 +12 V
VSNSCAP voltage on pin
SNSCAP 0.4 +12 V
VSNSBOOST voltage on pin
SNSBOOST 0.4 +12 V
Currents
ISUPHV current on pin SUPHV - 20 mA
General
Ptot total power dissipation Tamb <75C-0.7W
Tstg storage temperature 55 +150 C
Tjjunction temperature 40 +150 C
Latch-up
Ilu latch-up current all pins; according to JEDEC: Standard
78D 100 +100 mA
ESD
VESD electrostatic discharge
voltage human body model
pins SUPHV, SUPHS, GATEHS, and
HB 1000 +1000 V
other pins 2000 +2000 V
charged device model; all pins 500 +500 V
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 36 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
9. Thermal characteristics
10. Characteristics
Table 8. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to
ambient In free air;
JEDEC test board 107 K/W
Rth(j-c) thermal resistance from junction to case In free air,
JEDEC test board 60 K/W
Table 9. Characteristics
Tamb =25
C; VSUPIC = 19.5 V; all voltages are measured with respect to GND; currents are positive when flowing into the IC;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
SUPHV pin
Ilim(SUPHV) current limit on pin SUPHV VSUPIC <V
rst(SUPIC) 0.5 0.75 1.0 mA
Ioff(SUPHV) off-state current on pin
SUPHV VSUPIC =15V - 0.5 0.9 A
VI(SUPHV-SUPIC) input voltage difference
between pin SUPHV and pin
SUPIC
ISUPHV =20mA - 7 - V
SUPIC pin
Vstart(SUPIC) st art volt age on pin SUPIC 18.3 19.1 19.8 V
Vstart(hys)SUPIC start voltage hysteresis on
pin SUPIC -0.7 - V
Vlow(hys)SUPIC low voltage hysteresis on
pin SUPIC -0.9-V
Vlow(SUPIC) low voltage on pin SUPIC Vuvp(SUPIC) = 13.3 V;
tracks with Vuvp(SUPIC)
- 14.0 - V
Vuvp(SUPIC) undervoltage protection
voltage on pin SUPIC 12.7 13.2 13.7 V
Vrst(SUPIC) reset voltage on pin SUPIC - 3.5 - V
ICC(SUPIC) supply current on pin SUPIC operating mode; fHB = 100 kHz;
GATEHS/GATELS open ;
ISNSFB =85 A;
ISNSCAP =100 A
-5.6-mA
latched protection; ISNSFB =0A;
ISNSCAP =100 A2.3 3.0 3.7 mA
burst mode; ISNSFB =106 A;
ISNSCAP =100 A-0.7-mA
SUPREG pin
Vintregd(SUPREG) internal regulated voltage on
pin SUPREG VSUPIC > 13.8 V;
ISUPREG =50mA 10.6 11.0 11.4 V
Vreg(acc)SUPREG regulator voltage accuracy
on pin SUPREG VSUPIC > 13.8 V;
10 A<I
SUPREG <20mA 150 100 50 mV
Ilim(SUPREG) current limit on pin SUPREG VSUPIC = 19.5 V 44 37 30 mA
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 37 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
Vuvp(SUPREG) undervoltage protection
voltage on pin SUPREG 8.6 9.0 9.4 V
SNSCAP pin
VAV(regd)SNSCAP regulated average voltage
on pin SNSCAP regulated average of Vhs(SNSCAP)
and Vls(SNSCAP)
-2.50-V
Ibias(max)SNSCAP maximum bias current on
pin SNSCAP 245 210 175 A
Vth(max)SNSCAP maximum threshold voltage
difference on pin SNSCAP Vhs(SNSCAP) Vls(SNSCAP);
Pout =200%; V
SNSBOOST =2.5V -1.92-V
Vhs(SNSCAP) Vls(SNSCAP);
Pout =200%; V
SNSBOOST <2.0V 2.85 3.00 3.15 V
Overpower protection
Vopp(SNSCAP) overpower protection
voltage difference on pin
SNSCAP
Vhs(SNSCAP) Vls(SNSCAP);
Pout = 150 %; VSNSBOOST =2.5V -1.44-V
Vhs(SNSCAP) Vls(SNSCAP);
Pout = 150 %; VSNSBOOST =2.1V -2.24-V
tPD(SNSCAP) propagation delay on pin
SNSCAP from crossing
Vls(SNSCAP)/Vhs(SNSCAP) level to
GATELS/GATEHS switch-off
-150-ns
td(opp) overpower protection delay
time See Table 5 for related RSNSSET1 40 50 60 ms
See Table 5 for related RSNSSET1 160 170 180 ms
td(restart) restart delay time 0.8 1.0 1.2 s
SNSCUR pin
Vbias(SNSCUR) bias voltage on pin
SNSCUR 2.4 2.5 2.6 V
RO(SNSCUR) output resistance on pin
SNSCUR -60-k
Vocp overcurrent protection
voltage positive level;
VSNSCUR Vbias(SNSCUR)
1.35 1.50 1.65 V
negative level;
VSNSCUR Vbias(SNSCUR)
1.65 1.50 1.35 V
Vreg(capm) capacitive mode regulation
voltage positive level;
VSNSCUR Vbias(SNSCUR)
85 100 115 mV
negative level;
VSNSCUR Vbias(SNSCUR)
115 100 85 mV
Vdet(zero) zero detection voltage detected as 0-13 - mV
detected as 0-13-mV
SNSBOOST pin
Vstart(SNSBOOST) start voltage on pin
SNSBOOST 2.2 2.3 2.4 V
Vuvp(SNSBOOST) undervoltage protection
voltage on pin SNSBOOST 1.5 1.6 1.7 V
Vdet(SNSBOOST) detection voltage on pin
SNSBOOST when below power good = LOW - 1.95 - V
Table 9. Characteristics …continued
Tamb =25
C; VSUPIC = 19.5 V; all voltages are measured with respect to GND; currents are positive when flowing into the IC;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 38 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
PFC burst mode controller
en(burst) burst mode enable duty
cycle enable of PFC burst mode;
duty cycle of LLC burst mode -50-%
Ncy(en)burst burst mode enable number
of cycles enable of PFC burst mode;
cycles of LLC burst mode -8-
dis(burst) burst mode disable duty
cycle disable of PFC burst mode;
duty cycle of LLC burst mode -75-%
Vpu(SNSBOOST) pull-up voltage on pin
SNSBOOST to enter PFC burst mode off-state - 2.95 - V
Ioff(burst) burst mode off-state current during PFC burst mode off-state 7.1 6.4 5.7 A
Voff(burst) burst mode off-st ate voltage
difference during PFC burst mode off-state;
between peak voltage and end of
off-state
-75 - mV
Von(burst)max maximum burst mode
on-state voltage during PFC burst mode on-state 2.29 2.37 2.45 V
tto(det)on(burst) burst mode on-state
detection time-out time during PFC burst mode on-state 3.7 4.0 4.3 ms
PFC protection controller
Rpd(SNSBOOST) pull-down resistance on pin
SNSBOOST at protection activation - 550 -
Ipd(SNSBOOST) pull-down current on pin
SNSBOOST during acti ve protection 94 110 127 A
Iprot(SNSBOOST) protection current on pin
SNSBOOST -60-nA
SNSOUT pin
Vovp(SNSOUT) overvoltage protection
voltage on pin SNSOUT 3.36 3.50 3.64 V
Iprot(SNSOUT) protection current on pin
SNSOUT for open pin - 60 - nA
SNSFB pin
Vbias(SNSFB) bias voltage on pin SNSFB ISNSFB =85 A2.22.52.8V
Optobias regulator
Ireg(SNSFB) regulation current on pin
SNSFB Istart(burst) = 106 A;
tracks with Istart(burst)
-85 - A
Ireg(max)SNSFB maximum regulation current
on pin SNSFB Istart(burst) = 106 A;
tracks with Istart(burst)
-310 - A
Ireg(min)SNSFB minimum regulation current
on pin SNSFB Istart(burst) = 106 A;
tracks with Istart(burst)
-63 - A
Burst mode regulator
Istart(burst) burst mode start current LLC burst mode 123 106 89 A
Istop(burst) burst mode stop current LLC burst mode - 200 - A
Table 9. Characteristics …continued
Tamb =25
C; VSUPIC = 19.5 V; all voltages are measured with respect to GND; currents are positive when flowing into the IC;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 39 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
GATELS and GATEHS pins
Isource(GATEHS) source current on pin
GATEHS VGATEHS VHB =4V - 340 - mA
Isource(GATELS) source current on pin
GATELS VGATELS VGND =4V - 340 - mA
Isink(GATEHS) sink current on pin GATEHS VGATEHS VHB = 2 V - 580 - mA
VGATEHS VHB =11V - 2 - A
Isink(GATELS) sink current on pin GATELS VGATELS VGND = 2 V - 580 - mA
VGATELS VGND =11 V - 2 - A
Vrst(SUPHS) reset voltage on pin SUPHS 6.4 7 7.6 V
Vrst(hys)SUPHS hysteresis of reset voltage
on pin SUPHS >V
rst(SUPHS) -0.6-V
ton(min) minimum on-time - 0.83 - s
ton(max) maximum on-time 14.8 17.4 20.0 s
tsweep sweep time frequency; at start-up 1 12 14 ms
Low-power mode regulator
flp(min) minimum low-power mode
frequency 20 23 26 kHz
Burst mode regulator
fburst(max) maximum burst mode
frequency RSNSOUT1 =22k170 200 230 Hz
RSNSOUT1 =15k340 400 460 Hz
RSNSOUT1 =10k680 800 920 Hz
RSNSOUT1 =6.8k1360 1600 1840 Hz
Power good characteristics (pin SNSSET)
VOH(SNSSET) HIGH-level output voltage
on pin SNSSET ISNSSET =100 A;
power good = LOW -4-V
IOH(SNSSET) HIGH-level output current
on pin SNSSET VSNSSET =3V;
power good = LOW 11 85mA
IOL(SNSSET) LOW-level output current on
pin SNSSET VSNSSET =0.5V;
power good = HIGH 81114mA
td(H)SNSSET HIGH-level delay time on
pin SNSSET See Table 5 for related RSNSSET1 35 45 55 ms
See Table 5 for related RSNSSET1 150 190 230 ms
Settings senso r (SNSOUT, SNSSET, and GATELS pins)
IO(SNSOUT) output current on pin
SNSOUT during RSNSOUT1 measurement - 171 - A
IO(SNSSET) output current on pin
SNSSET during RSNSSET measurement - 26.8 - A
VO(GATELS-SUPREG) output voltage difference
between pin GATELS and
pin SUPREG
during RGATELS measurement - 1.25 - V
Table 9. Characteristics …continued
Tamb =25
C; VSUPIC = 19.5 V; all voltages are measured with respect to GND; currents are positive when flowing into the IC;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 40 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
HB pin
(dV/dt)tno(min) minimum non-overlap time
rate of change of voltage --120V/s
tno(min) minimum non-overlap time - 200 - ns
tno(max) maximum non-overlap time - 1.1 - s
Overtemper ature protec ti on
Totp overtemperature protection
trip 130 140 150 C
Table 9. Characteristics …continued
Tamb =25
C; VSUPIC = 19.5 V; all voltages are measured with respect to GND; currents are positive when flowing into the IC;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 41 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
11. Application information
Fig 27. TEA19161T application diagram
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 42 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
12. Package outline
Fig 28. Package outline SOT109-3 (SO16)
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 43 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
13. Revision history
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
TEA19161T v.1 20160310 Product data sheet - -
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 44 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
14. Legal information
14.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The prod uct sta tus of device (s) descri bed in this d ocument may have change d since this d ocument was p ublished and may dif fer in case of multiple devices. The latest product st atus
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict wit h the short data sheet, th e
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for t he customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associated with t heir
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data fro m the objective specification fo r product development.
Preliminary [short] dat a sheet Qualification This document contains data from the pre liminary specification.
Product [short] data sheet Production This document contains the product specification.
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 45 of 46
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omotive use. It i s neither qua lified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in au tomotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such au tomotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y
liability, damages or failed product claims resulting f rom customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
GreenChip — is a trademark of NXP B.V.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors TEA19161T
Digital controller for high-efficiency resonant power supply
© NXP Semiconductors N.V. 2016. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 March 2016
Document identifier: TE A1 91 61 T
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
16. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2
2.1 Distinctive features. . . . . . . . . . . . . . . . . . . . . . 2
2.2 Green features . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.3 Protection features . . . . . . . . . . . . . . . . . . . . . . 2
3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Functional description . . . . . . . . . . . . . . . . . . . 6
7.1 Supply voltages . . . . . . . . . . . . . . . . . . . . . . . . 6
7.1.1 Start-up and supply voltage . . . . . . . . . . . . . . . 6
7.1.2 Regulated supply (SUPREG pin) . . . . . . . . . . . 8
7.1.3 High-side driver floating supply (SUPHS pin). . 8
7.2 System start-up. . . . . . . . . . . . . . . . . . . . . . . . . 9
7.3 LLC system regulation . . . . . . . . . . . . . . . . . . 10
7.3.1 Output power regulation loop . . . . . . . . . . . . . 12
7.3.2 Output voltage start-up. . . . . . . . . . . . . . . . . . 13
7.4 Modes of operation. . . . . . . . . . . . . . . . . . . . . 14
7.4.1 High-power mode . . . . . . . . . . . . . . . . . . . . . . 16
7.4.2 Low-power mode . . . . . . . . . . . . . . . . . . . . . . 17
7.4.3 Burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.5 Optobias regulation . . . . . . . . . . . . . . . . . . . . 21
7.6 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.6.1 Undervoltage protection SUPIC/SUPREG . . . 22
7.6.2 Undervoltage protection SUPHS . . . . . . . . . . 23
7.6.3 Undervoltage protection boost . . . . . . . . . . . . 23
7.6.4 Overvoltage protection . . . . . . . . . . . . . . . . . . 23
7.6.5 Capacitive Mode Regulation (CMR). . . . . . . . 23
7.6.6 Overcurrent protection . . . . . . . . . . . . . . . . . . 24
7.6.7 Overtemperature protection . . . . . . . . . . . . . . 24
7.6.8 Overpower protection. . . . . . . . . . . . . . . . . . . 25
7.7 External settings. . . . . . . . . . . . . . . . . . . . . . . 26
7.7.1 Burst period . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.7.2 General settings . . . . . . . . . . . . . . . . . . . . . . . 26
7.7.3 Low-power mode/burst mode transition levels 27
7.8 Power good function. . . . . . . . . . . . . . . . . . . . 28
7.9 PFC/LLC communication protocol . . . . . . . . . 29
7.9.1 Start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.9.2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.9.3 Fast latch reset. . . . . . . . . . . . . . . . . . . . . . . . 32
7.9.4 PFC burst mode . . . . . . . . . . . . . . . . . . . . . . . 33
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 35
9 Thermal characteristics . . . . . . . . . . . . . . . . . 36
10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
11 Application information . . . . . . . . . . . . . . . . . 41
12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 42
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . 43
14 Legal information . . . . . . . . . . . . . . . . . . . . . . 44
14.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 44
14.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
14.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 44
14.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 45
15 Contact information . . . . . . . . . . . . . . . . . . . . 45
16 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
