INCH-POUND MIL-M-38510/203E 18 September 2007 SUPERSEDING MIL-M-38510/203D 19 January 2006 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, 1024 BIT SCHOTTKY, BIPOLAR, PROGRAMMABLE READ-ONLY MEMORY (PROM), MONOLITHIC SILICON Inactive for new design after 24 July 1995 This specification is approved for use by all Departments and Agencies of the Department of Defense. The requirements for acquiring the product herein shall consist of this specification sheet and MIL-PRF 38535. 1. SCOPE * 1.1 Scope. This specification covers the detail requirements for monolithic silicon, programmable read-only memory (PROM) microcircuits which employ thin film nichrome (NiCr) resistors, tungsten (W), titanium tungsten (TiW), or zapped vertical emitter (ZVE) as the fusible link or programming element. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, (see 6.4). 1.2 Part or Identifying Number (PIN). The PIN is in accordance with MIL-PRF-38535, and as specified herein. 1.2.1 Device types. The device types are as follows: Device type 01, 03 02, 04 Circuit 256 word/4 bits per word PROM with uncommitted collector. 256 word/4 bits per word PROM with active pull-up and a third high impedance state output. 1.2.2 Device class. The device class is the product assurance level as defined in MIL-PRF-38535. 1.2.3 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter E F Descriptive designator GDIP1-T16 or CDIP2-T16 GDFP2-F16 or CDFP3-F16 Terminals Package style 16 16 Dual-in-line Flat pack Comments, suggestions, or questions on this document should be addressed to: Commander, Defense Supply Center Columbus, ATTN: DSCC-VAS, P. O. Box 3990, Columbus, OH 43218-3990, or emailed to mailto:memory@dscc.dla.mil . Since contact information can change, you may want to verify the currency of this address information using the ASSIST Online database at http://assist.daps.dla.mil AMSC N/A FSC 5962 MIL-M-38510/203E 1.3 Absolute maximum ratings. Supply voltage range .............................................................................. Input voltage range ................................................................................. Storage temperature range ..................................................................... Lead temperature (soldering, 10 seconds) .............................................. Thermal resistance, junction to case (JC) 1/ ........................................ Output supply voltage ............................................................................. Output sink current .................................................................................. Maximum power dissipation (PD) 2/ ......................................................... Maximum junction temperature (TJ)......................................................... -0.5 V dc to +7.0 V dc -1.5 V dc at -10 mA to +5.5 V dc -65 to +150C +300C See MIL-STD-1835 -0.5 C dc to +VCC +100 mA 739 mW dc +175C 3/ 1.4 Recommended operating conditions. Supply voltage (VCC) ............................................................................... +4.5 V dc minimum to +5.5 V dc maximum Minimum high-level input voltage (VIH) ................................................... 2.0 V dc Maximum low-level input voltage (VIL) .................................................... 0.8 V dc Fanout (each output) ............................................................................ 16 mA 4/ Case operating temperature range (TC)................................................... -55 C to +125 C 2. APPLICABLE DOCUMENTS 2.1 General. The documents listed in this section are specified in sections 3, 4, or 5 of this specification. This section does not include documents cited in other sections of this specification or recommended for additional information or as examples. While every effort has been made to ensure the completeness of this list, document users are cautioned that they must meet all specified requirements of documents cited in sections 3, 4, or 5 of this specification, whether or not they are listed. 2.2 Government documents. 2.2.1 Specifications and Standards. The following specifications and standards form a part of this specification to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIONS MIL-PRF-38535 - Integrated Circuits (Microcircuits) Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard for Microelectronics. Interface Standard Electronic Component Case Outline ______ 1/ Heat sinking is recommended to reduce the junction temperature. 2/ Must withstand the added PD due to short circuit test (e.g. IOS). 3/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions per MIL-PRF-38535. 4/ 12 mA for circuit B. 2 MIL-M-38510/203E (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.3 Order of precedence. In the event of a conflict between the text of this specification and the references cited herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Qualification. Microcircuits furnished under this specification shall be products that are manufactured by a manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturers list before contract award (see 4.3 and 6.3). 3.2 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.3 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein. 3.3.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.3.2 Truth table 3.3.2.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in groups A, B, or C (see 4.4), the devices shall be programmed by the manufacturer prior to test in a checkerboard pattern (a minimum of 50 percent of the total number of bits programmed) or to any altered item drawing pattern which includes at least 25 percent of the total number of bits programmed. 3.3.2.2 Programmed devices. The truth table for programmed devices shall be as specified by the altered item drawing. 3.3.3 Functional block diagram. The functional block diagram shall be as specified on figure 3. 3.3.4 Case outlines. The case outlines shall be as specified in 1.2.3. 3.4 Lead material and finish. The lead material and finish shall be in accordance with MIL-PRF-38535 (see 6.6). 3.5 Electrical performance characteristics. The electrical performance characteristics are as specified in table I, and apply over the full recommended case operating temperature range, unless otherwise specified. 3.6 Electrical test requirements. The electrical test requirements shall be as specified in table II, and where applicable, the altered item drawing. The electrical tests for each subgroup are described in table III. 3.7 Marking. Marking shall be in accordance with MIL-PRF-38535. For programmed devices, the altered item drawing number shall be added to the marking by the programming activity. 3 MIL-M-38510/203E TABLE I. Electrical performance characteristics. Characteristic Symbol High level output voltage VOH Low level output voltage VOL Input clamp voltage VIC Maximum collector cut-off current High impedance (off-state) output high current High impedance (off-state) output low current High level input current ICEX IIH1 High level input current IIH2 Low level input current IIL Short circuit output current Supply current IOS Propagation delay time high-to-low level logic, address to output Propagation delay time low-to-high level logic, address to output Propagation delay time high-to-low level logic, enable to output Propagation delay time low-to-high level logic, enable to output IOHZ IOLZ ICC tPHL1 Conditions 1/ -55C TC +125C VCC = 4.5 V; IOH = -2 mA, VIL = 0.8 V, VIH = 2.0 V VCC = 4.5 V; IOL = 16 mA 2/ VIL = 0.8 V, VIH = 2.0 V VCC = 4.5 V; IIN = -10 mA; TC = 25C VCC = 5.5 V; VO = 5.2 V VCC = 5.5 V; VO = 5.2 V VCC = 5.5 V; VO = .5 V VCC = 5.5 V; VIN = 5.5 V VCC = 5.5 V; VIN = 4.5 V; special program pin VCC = 5.5 V; VIN = 0.5 V VCC = 5.5 V; 3/ VO = 0.0 V VCC = 5.5 V; VIN = 0; outputs open VCC = 4.5 V and 5.5 V; CL = 30 pF minimum; see figure 5 tPLH1 tPHL2 tPLH2 Device type 02,04 Limits Unit Min Max 2.4 --V 01,02 03,04 --- 0.5 V 01,02 03,04 --- -1.5 V 01,03 --- 100 A 02,04 --- 100 A 02,04 --- -100 A 01,02 03,04 01,02 03,04 01,02 03,04 02,04 --- 50 A --- 100 A -1 -250 A -10 -100 mA 01,02 03,04 01, 02 --- 130 mA --- 75 ns 03, 04 --- 35 01, 02 --- 75 03, 04 --- 35 01, 02 --- 35 03, 04 --- 20 01, 02 --- 35 03, 04 --- 20 1/ Complete terminal conditions shall be specified in table III. 2/ IOL = 12 mA for circuit B. 3/ Not more than one output shall be grounded at one time. Output shall be at high logic level prior to test. 4 ns ns ns MIL-M-38510/203E TABLE II. Electrical test requirements. Subgroups (see table III) 1/, 2/, 3/ Class S Class B devices devices 1 1 MIL-PRF-38535 test requirements Interim electrical parameters Final electrical test parameters for unprogrammed devices Final electrical test parameters for programmed devices Group A test requirements Group B end-point electrical parameters when using the method 5005 QCI option Group C end-point electrical parameters Group D test requirements 1*, 2, 3, 7*, 8 1*, 2, 3, 7* 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8 1*, 2, 3, 7*, 8 1*, 2, 3, 7*, 8, 9 1, 2, 3, 7, 8 9, 10, 11 N/A 1, 2, 3, 7, 8 1, 2, 3, 7, 8 1/ * indicates PDA applies to subgroups 1 and 7. 2/ Any or all subgroups may be combined when using high-speed testers. 3/ Subgroups 7 and 8 shall consist of verifying the pattern specified. 3.8 Processing options. Since the PROM is an unprogrammed memory capable of being programmed by either the manufacturer or the user to result in a wide variety of PROM configurations, two processing options are provided for selection in the contract, using an altered item drawing. 3.8.1 Unprogrammed PROM delivered to the user. All testing shall be verified through group A testing as defined in 3.3.2.1, table II, and table III. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 3.8.2 Manufacturer-programmed PROM delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery. 3.9 Microcircuit group assignment. The devices covered by this specification shall be in microcircuit group number 14 (see Appendix A MIL-PRF-38535.) 5 MIL-M-38510/203E 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not effect the form, fit, or function as described herein. 4.2 Screening. Screening shall be in accordance with MIL-PRF-38535 and shall be conducted on all devices prior to qualification and quality conformance inspection. The following additional criteria shall apply: a. The burn-in test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document control by the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II, except interim electrical parameters test prior to burn-in is optional at the discretion of the manufacturer. c. Additional screening for space level product shall be as specified in MIL-PRF-38535, appendix B. d. Class B devices processed to an altered item drawing may be programmed either before or after burn-in at the manufacturer's discretion. The required electrical testing shall include, as a minimum, the final electrical tests for programmed devices as specified in table II herein. Class S devices processed by the manufacturer to an altered item drawing shall be programmed prior to burn-in. 4.3 Qualification inspection. Qualification inspection shall be in accordance with MIL-PRF-38535. 4.3.1 Qualification extension. When authorized by the qualifying activity, for qualification inspection, if a manufacturer qualifies to a faster device type which is manufactured identically to a slower device type on this specification, then the slower device type may be part I qualified by conducting only group A electrical tests and any electricals specified as additional group C subgroups and submitting data in accordance with MIL-PRF-38535 (i.e.,groups B, C, and D tests are not required). 4.4 Technology Conformance inspection (TCI). Technology conformance inspection shall be in accordance with MIL-PRF-38535 and as specified herein for groups A, B, C, and D inspections (see 4.4.1 through 4.4.4). 6 MIL-M-38510/203E 4.4.1 Group A inspection. Group A inspection shall be in accordance with table III of MIL-PRF-38535 and as follows: a. Electrical test requirements shall be as specified in table II herein. b. Subgroups 4, 5, and 6 shall be omitted. c. For unprogrammed devices, a sample shall be selected to satisfy programmability requirements prior to performing subgroups 9. 10, and 11. Twelve devices shall be submitted to programming (see 3.3.2.1). If more than 2 devices fail to program, the lot shall be rejected, At the manufacturer's option, the sample may be increased to 24 total devices with no more than 4 total device failures allowable. d. For unprogrammed devices, 10 devices from the programmability sample shall be submitted to the requirements of group A, subgroups 9, 10, and 11. If more than two total devices fail in all three subgroups, the lot shall be rejected. At the manufacturer's option, the sample may be increased to 20 total devices with no more than 4 total device failures allowable. 4.4.2 Group B inspection. Group B inspection shall be in accordance with table II MIL-PRF-38535. 4.4.3 Group C inspection. Group C inspection shall be in accordance with table IV of MIL-PRF-38535 and as follows: a. End-point electrical parameters shall be as specified in table II herein. b. The steady-state life test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document control by the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. c. For qualification, at least 50 percent of the sample selected for life testing shall be programmed (see 3.3.2). For quality conformance inspection, the programmability sample (see 4.4.1c) shall be included in the life test. 4.4.4 Group D inspection. Group D inspection shall be in accordance with table V of MIL-PRF-38535. End-point electrical parameters shall be as specified in table II herein. 4.5 Methods of inspection. Methods of inspection shall be as specified and as follows: 4.5.1 Voltage and current. All voltages given are referenced to the microcircuit ground terminal. Currents given are conventional and positive when flowing into the referenced terminal. 7 MIL-M-38510/203E Device type Case outline Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 13 All E and F Terminal symbol A6 A5 A4 A3 A0 A1 A2 GND O4 O3 O2 O1 CE 1 14 CE 2 15 16 A7 VCC FIGURE 1. Terminal connections. 8 MIL-M-38510/203E Word no. Enable Address A6 A5 A4 A3 A2 A1 A0 X X X X X X X X 5/ 5/ 5/ 5/ H X X X X X X X X OC OC OC OC H L X X X X X X X X OC OC OC OC H H X X X X X X X X OC OC OC OC CE 1 CE 2 NA L L NA L NA NA A7 Data 01 02 03 04 NOTES: 1. NA = Not applicable. 2. X = Input may be high level, low level, or open circuit. 3. OC = Open circuit (high resistance output). 4. Program readout can only be accomplished with both enable inputs at low level. 5. The outputs for an unprogrammed device shall be high for circuits A and B, and shall be low for circuit C and G. FIGURE 2. Truth table (unprogrammed). 9 MIL-M-38510/203E CIRCUIT A TEST ROW SELECT z 1 OF 32 DECODER z :c :::, :c :::, ..J 0 ..J 0 u I- A A A A "' u I- "' ILi I- ILi I- B B B Oz A = 32 x 8 Memory Array B = 1 of 8 Decoder FIGURE 3. Functional block diagram. 10 B MIL-M-38510/203E CIRCUIT B ADDRESS BUFFER X 1 OF 32 DECODER 32 DRIVER D 32 D 32 D 32 D Ao ADDRESS1-----------1 BUFFER l-----------1 E y Az ZENER DIODE CE 10-------+--\ CEz0--------1 Oz A = Enable buffer B = Output buffer C = Programming driver D = 256 bit memory, 32 x 8 matrix E = 1 of 8 Y decoder multiplexer FIGURE 3. Functional block diagram - Continued. 11 MIL-M-38510/203E CIRCUIT C A3 INPUT BUFFER 4 A4 A5 6 X DECODE 11*32) 32 8 X 32 ARRAY 8 X 32 ARRAY 8 X 32 ARRAY 8 X 32 ARRAY As A7 2 TESTRDW CE 1 0-----<1 CE2v----q FIGURE 3. Functional block diagram - Continued. 12 MIL-M-38510/203E CIRCUIT G 1024-BIT ARRAY 32 X 32 MEMORY MATRIX 1 OF 32 DECODER A2 A1 1 OF 8 MUX 1 OF 8 MUX 1 OF 8 MUX 1 OF 8 MUX BUFFER BUFFER BUFFER BUFFER 04 03 02 01 Ao CE 1 CE2 ENABLE GATE FIGURE 3. Functional block diagram - Continued 13 MIL-M-38510/203E Vee INPUT Ao A1 R1 Az A3 PULSE GENERATOR PRR ~ 1 MHz SEE TEST TABLE 01 A4 Oz A5 03 As 04 A7 CE1 Rz 3.0 INPUT-~Y-=-<-1_o_n_s~~-----Y-<-10-ns- Z.7 1.5 0.7 0 V - - - - < 500 n s - - - - ~ CL *0.1 V V V V *0.1 V VoH OUTPUT WAVEFORM A 1.5 V Vol l OUTPUT WAVEFORM _a_____~ \[ VoH - - - - - - - - - - - \~---_-_-_-_-_-_ 1.5 V Vol NOTES: 1. Test table for devices programmed in accordance with an altered item drawing may be replaced by the equivalent tests which apply to the specific program configuration for the resulting read-only memory 2. CL = 30 pF minimum, including jig and probe capacitance, R1 =330 25%, and R2 = 680 20%. 3. Outputs may be under load simultaneously. FIGURE 4. Switching time test circuit. 14 MIL-M-38510/203E NOTE: All other waveform characteristics shall be as specified in table IVA. FIGURE 5a. Typical programming voltage waveforms during programming for circuit A. 15 MIL-M-38510/203E ADDRESSES ~ - - - - - - - - - - - - - - - - - _/\_____----=:;:j"""i"-;::--;::=-------~ TTL PROGRAM p IN LI _ _ _ _ _ _t_JT=CH:... i-- :t=l tpp I HIGH TTL LOW .=.=.=.=.=::::::--:::--:::--:::--:::--:::--:::=- ~6/ 10% --j~:02 TTL LOW OUTPUT PIN /~7-0V 5.5 V --4.0 V TTL HIGH --TTL LOW STROBE CHECK NOTES: 1. Output load is 0.2 mA and 12 mA during 7.0 V and 4.0 V check respectively. 2. All other waveform characteristics shall be as specified in table IVB. FIGURE 5b. Typical programming voltage waveforms during programming for circuit B. 16 MIL-M-38510/203E A~~~5~s "~.t...1.J._ _ _ _ _ A_F_1R_s_1_ _ _ _ _ _LILI_ _ _A_L_A_s_1_ _ __,JI ::: 1::: ::: NOTE: All other waveform characteristics shall be as specified in table IVC. FIGURE 5c. Typical Programming voltage waveforms during programming for circuit C. 17 MIL-M-38510/203E 2.4 V TO 5.5 V ADDRESS ~k~ Vee OUTPUT ENABLE 0 V TO 0.5 V 1 ~.t I Veep 5.0 V Veev 1t51-- 1.ar JI --Jt4 II-- Vop VoH Vol 2.4 V TO 5.5 V I OVT00.5V ~PWE~ FIGURE 5d. Programming voltage waveforms during programming for circuit G. 18 MIL-M-38510/203E 4.6 Programming procedure identification. The programming procedure to be utilized shall be identified by the manufacturer's circuit designator. 4.7 Programming procedure for circuit A. The programming characteristics in table IVA and the following procedures shall be used for programming the device. a. Connect the device in the electrical configuration for programming. The waveforms on figure 5a and the programming characteristics in table IVA shall apply to these procedures. b. Address the PROM with the binary address of the word to be programmed. Address inputs are TTL compatible. An open circuit shall not be used to address the PROM. c. Apply VPL voltage to VCC. d. Bring the CE X inputs high and the CE X inputs low to disable the device. The chip enables are TTL compatible. An open circuit shall not be used to disable the devices. e. Disable the programming circuitry by applying a voltage of VOPD to the outputs of the PROM. f. Raise VCC to VPH with rise time less than or equal to tTLH. g. After a delay equal to or greater than tD1 apply only one pulse with amplitude of VOPE and duration of tp to the output selected for programming. Note that the PROM is supplied with fuses intact, which generates an output high. Programming a fuse will cause the output to go low. h. Lower VCC to VPL following a delay to tD2 from programming enable pulse applied to an output. i. Enable the PROM for verification by applying VIL to CE X and VIH to CE X . j. Apply VPHV to VCC and verify bit is programmed. k. Repeat steps a through j for all other bits to be programmed in the PROM. l. If any bit does not verify as programmed, it shall be considered a programming reject. 19 TABLE III. Group A inspection for device type 01, 03. Terminal conditions Outputs: Not designated are open or resistive coupled to GND or voltage Inputs: Not designated are high 2.0 V, low 0.8 V, or open. Subgroup Symbol 1 TC=+25C VIC MILCases STD-883 E,F method Test no. 1 A6 2 5 3 4 4 3 5 0 6 1 7 2 8 9 GND O4 See footnotes at end of device type 02. 11 12 13 3 2 1 CE O 14 1 CE 15 2 A7 " GND " " " " 5/ 5/ Outputs -10mA -10mA 0.8V 0.8V 2/ 2/ 2/ -10mA 4/ 1/ " " " 0.5V 0.5V 0.5V 5.5V 5.5V 5.2V 5.2V 5.2V 5.2V 5/ 5/ 5/ 5/ 4.5V 5.5V " " " GND 5.5V " " " GND 5/ 5/ 4.5V " " " " " " " " " " " " " 5.5V " " " " " " " " " " " " " " " " " " " Test limits Min CC V 2/ Measured terminal A6 A5 A4 A3 A0 A1 A2 CE1 CE2 A7 O4 O3 O2 O1 A6 A5 A4 A3 A0 A1 A2 CE1 CE2 A7 A6 A5 A4 A3 A0 A1 A2 A7 CE2 CE1 O4 O3 O2 O1 VCC O O 16 -1.0 " " " " " " " " " Unit Max -1.5 " " " " " " " " " 0.5 " " " -250 " " " " " " " " " 50 " " " " " " " " 100 100 " " " 130 5/ V " " " " " " " " " " " " " A " " " " " " " " " " " " " " " " " " " " " " " mA MIL-M-38510/203E 20 1 -10mA GND A A A A A A 2 -10mA " 3 -10mA " 4 -10mA " 5 -10mA " 6 -10mA " 7 -10mA " 8 " 9 " 10 " 3007 11 1/ 1/ VOL 1/ 1/ 1/ 3/ 1/ 1/ " " 12 " " " " " " " " " 13 " " " " " " " " " 14 " " " " " " " " IIL 3009 15 0.5V " " 16 0.5V " " 17 0.5V " " 18 0.5V " " 19 0.5V " " 20 0.5V " " 21 0.5V " " 22 " " 23 " " 24 " IIH1 3010 25 5.5V " " 26 5.5V " " 27 5.5V " " 28 5.5V " " 29 5.5V " " 30 5.5V " " 31 5.5V " " 32 " " 33 " IIH2 " 34 " 35 " ICEX 36 " 37 " 38 " ICC 3005 39 GND GND GND GND GND GND GND " 2 Same tests, terminal conditions, and limits as for subgroup 1, except TC = +125C and VIC tests are omitted. 3 Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55C and VIC tests are omitted. 7 Funct5/ 40 5/ 5/ 5/ 5/ 5/ 5/ 5/ GND ional TC=+25C test 10 . TABLE III. Group A inspection for device type 01, 03 - Continued. Terminal conditions Outputs: Not designated are open or resistive coupled to GND or voltage Inputs: Not designated are high 2.0 V, low 0.8 V, or open. Subgroup Symbol MILCases STD-883 E,F method Test no. 1 A6 2 5 3 4 4 3 5 0 6 1 8 Same tests, terminal conditions, and limits as subgroup 7, except TC = +125C and -55C. 8/ A 8/ A 8/ A 8/ A 8/ A 9 tPHL1 GALPAT 41 8/ A Fig. 4 TC=+25C 8/ 8/ 8/ 8/ 8/ 8/ tPLH1 GALPAT 42 Fig. 4 10/ 10/ 10/ 10/ 10/ Sequen43 10/ tPHL2 tial Fig. 4 10/ 10/ 10/ 10/ 44 10/ 10/ tPLH2 Sequential Fig. 4 10 Same tests, terminal conditions, and limits as subgroup 9, except TC = +125C. 11 Same tests, terminal conditions, and limits as subgroup 9, except TC = -55C. 7 8 9 2 GND O4 8/ GND 10 11 12 3 2 1 13 CE 1 14 15 CE A7 2 9/ O 9/ O 9/ O 9/ GND GND 8/ . 16 Measured terminal V Test limits Min CC 8/ Outputs 8/ " " " " " GND GND 8/ 8/ " 10/ " " " " " 10/ 10/ 10/ 10/ " 10/ " " " " " 10/ 10/ 10/ 10/ " Unit Max / 11 ns " " " " " " See footnotes at end of device type 02. 26 MIL-M-38510/203E 21 TABLE III. Group A inspection for device type 02, 04. Terminal conditions Outputs: Not designated are open or resistive coupled to GND or voltage Inputs: Not designated are high 2.0 V, low 0.8 V, or open. Subgroup Symbol 1 TC=+25C VIC VOL VOH 22 IIH1 IIH2 IOHZ 3007 " " " 3006 " " " 3009 " " " " " " " " " 3010 " " " " " " " " " IOLZ ICC IOS 3005 3011 " " " 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 A6 -10mA A 2 3 5 A -10mA 4 A -10mA 4 5 3 6 0 A 7 1 A 2 A -10mA -10mA -10mA -10mA 1/ " " " 1/ 6/ " " " 0.5V 1/ " " " 1/ 6/ " " " 1/ " " " 1/ 6/ " " " 1/ " " " 1/ 6/ " " " 1/ " " " 1/ 6/ " " " 3/ 1/ " " " 1/ 6/ " " " 1/ " " " 1/ 12/ 6/ " " " 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V GND 1/ 6/ " " " GND 1/ 6/ " " " GND 1/ 6/ " " " See footnotes at end of device type 02. GND 1/ 6/ " " " GND 1/ 6/ " " " GND 1/ 6/ " " " GND 1/ 12/ 6/ " " " 8 9 GND O4 GND " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " 10 11 12 13 3 2 1 CE O 14 1 CE 15 2 A7 -10mA -10mA 2/ 2/ 2/ 2/ -2mA -2mA -2mA -2mA 0.8V " " " " " " " 0.8V " " " " " " " -10mA 4/ 1/ " " " 6/ 1/ " " " 0.5V 0.5V 0.5V 5.5V 5.5V 5.2V 5.2V 5.2V 5.2V 0.5V 0.5V 0.5V 0.5V GND GND GND GND 4.5V 5.5V 7/ " " " " " " " GND 0.5V " " " 5.5V 7/ " " " " " " " GND 0.5V " " " Measured terminal " " GND 6/ 1/ " " " 4.5V " " " " " " " " " " " " " " " " " 5.5V " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " Test limits Min CC V O O 16 2 A CE1 CE2 A7 O4 O3 O2 O1 O4 O3 O2 O1 A6 A5 A4 A3 A0 A1 2 A CE1 CE2 A7 A6 A5 A4 A3 A0 A1 A2 A7 CE2 CE1 O4 O3 O2 O1 O4 O3 O2 O1 VCC O4 O3 O2 O1 Max -1.5 " " " " " " " " " A6 A5 A4 A3 A0 A1 0.5 2.4 " " " -1.0 " " " " " " " " " 50 100 -10 " " " Unit " " " " -250 " " " " " " " " " " " " " " " " " 100 " " " -100 " " " 130 -100 " " " V " " " " " " " " " " " " " " " " A " " " " " " " " " " " " " " " " " " " " " " " " " " " mA " " " " MIL-M-38510/203E IIL MILCases STD-883 E,F method Test no. . 28 TABLE III. Group A inspection for device type 02, 04. Terminal conditions Outputs: Not designated are open or resistive coupled to GND or voltage Inputs: Not designated are high 2.0 V, low 0.8 V, or open. Subgroup Symbol MILCases STD-883 E,F method Test no. 1 A6 2 5 3 4 4 3 5 0 6 1 7 2 8 9 GND O4 11 12 13 3 2 1 CE O 14 1 CE 15 2 A7 Measured terminal Test limits Min CC Unit Max V O O 16 5/ 5/ 5/ 5/ 5/ 5/ 5/ 5/ Outputs 9/ 9/ 9/ 9/ GND GND 8/ 8/ Outputs " " " " GND GND 8/ 8/ " " " " " 10/ 10/ 10/ 10/ " " " " " 10/ 10/ 10/ 10/ " 5/ / 11 ns " " " " " " 23 1/ For programmed devices, select an appropriate address to acquire the desired output state, VIL = 0.8 V, VIH = 2.0 V. 2/ 16 mA for circuits A, C and G. 12 mA for circuit B. 3/ For unprogrammed devices, apply 12.0 V on pin 6 (A1) for circuit B devices. 4/ For unprogrammed devices, apply 13 V on pins 1 (A6) and 2 (A5) for circuit A devices. 5/ The functional tests shall verify that no fuses are blown for unprogrammed devices or that the truth table specified in the altered item drawing exists for programmed devices (see 3.3.2). All bits shall be tested. Terminal conditions shall be as follows: a. Inputs: H = 3.0 V, L = GND b. Outputs: Output voltage shall be either: 1. H = 2.4 V minimum and L = 0.5 V maximum when using a high speed checker double comparator, or 2. H 1.0 V and L 1.0 V when using a high speed checker single comparator. c. The functional tests shall be performed with VCC = 4.5 V and VCC = 5.5 V. 6/ For unprogrammed 02 devices (82S129); apply 10.0 V on pin 15 (A7), apply 0.5 V on pin 2 (A5) and 5.0 V on all other address lines for circuit C devices. For unprogrammed 04 devices (82S129A) apply 10.0 V on pin 5 (A0) and 5.0 V on all other address pins for the circuit C devices. 7/ 2.4 V for circuit B devices. MIL-M-38510/203E 2 Same tests, terminal conditions, and limits as for subgroup 1, except TC = +125C and VIC tests are omitted. A and V Atests are omitted. A subgroup A 1, exceptA TC = -55C 3 Same tests, terminal conditions, and A limits as for IC 7 Funct5/ 52 5/ 5/ 5/ 5/ 5/ 5/ 5/ GND ional TC=+25C test 8 Same tests, terminal conditions, and limits as for subgroup 7, except TC = +125C and -55C. 8/ GND 8/ 8/ 8/ 9 8/ 8/ tPHL1 GALPAT 53 8/ Fig. 4 TC=+25C 8/ 8/ " 8/ 8/ 8/ tPLH1 8/ 8/ GALPAT 54 Fig. 4 10/ " 10/ 10/ 10/ 10/ 10/ tPHL2 Sequen55 10/ tial Fig. 4 " 10/ 10/ 10/ 10/ 10/ 10/ tPLH2 10/ Sequen56 tial Fig. 4 10 Same tests, terminal conditions, and limits as subgroup 9, except TC = +125C. 11 Same tests, terminal conditions, and limits as subgroup 9, except TC = -55C. 10 . MIL-M-38510/203E 8/ GALPAT (PROGRAMMED PROM) This program will test all bits in the array, the addressing and interaction between bits for ac performance, tPHL1, and tPLH1. Each bit in the pattern is fixed by being programmed with a "H" or "L". Description 1. Word 0 is read. 2. Word 1 is read 3. Word 0 is read 4. Word 2 is read 5. Word 0 is read 6. The reading procedure continues back and forth between word 0 and the next higher numbered word until word 255 is reached, then increments to the next word and reads back and forth as in steps 1 through 6 and shall include all words. 7. Pass execution time = (n2 + n) x cycle time. n = 256. 8. The GALPAT tests shall be performed with VCC = 4.5 V and 5.5 V. 9/ The outputs are loaded per figure 5. 10/ SEQUENTIAL TEST (PROGRAMMED PROM) This program will test all bits in the array for tPHL2 and tPLH2. Description 1. Each word in the pattern is tested from the enable lines to the output lines for recovery. 2. Word 0 is addressed. Enable line is pulled hi to lo and lo to hi. tPHL2 and tPLH2 are read. 3. Word 1 is addressed. Same enable sequence as above. 4. The reading procedure continues until word 255 is reached. 5. Pass execution time = 256 x cycle time. 6. The sequential tests shall be performed with VCC = 4.5 V and 5.5 V 11/ The limits shall be as follows: I Device 01,02 75 ns TPHL1 TPLH1 75 ns 35 ns TPHL2 35 ns TPLH2 I I Device 03,04 TPHL1 35 ns TPLH1 35 ns TPHL2 20 ns TPLH2 20 ns 12/ For unprogrammed circuit G devices; apply 11.0 V on pin 7 (A2). 24 I I MIL-M-38510/203E 4.8 Programming procedure for circuit B. The programming characteristics in table IVB and the following procedures shall be used for programming the device: a. Connect the device in the electrical configuration for programming. The waveforms on figure 5b and the programming characteristics of table IVB shall apply to these procedures. b. Raise VCC to 5.5 V. c. Address the PROM with the binary address of the selected word to be programmed. Address inputs are TTL compatible. d. Disable the chip by applying VIH to CE2 and CE1 inputs. CE1 and CE2 inputs are TTL compatible. e. Apply the VPP pulse to the programming pin ( CE1 ). In order to insure that the output transistor is off before increasing the voltage on the output pin, the program pin's voltage pulse shall precede the output pin's programming pulse by TD1 and leave after the output pins programming pulse by TD2 (see figure 5b). f. Apply the VOUT pulse with duration of tP to the output selected for programming (see table IVB). The outputs shall be programmed one output at a time, since internal decoding circuitry is capable of sinking only one unit of programming current at a time. Note that the PROM is supplied with fuses generating a high level logic output. Programming a fuse will cause the output to go to a low level logic in the verify mode. g. Other bits in the same word may be programmed sequentially by applying VOUT pulses to each output to be programmed. h. Repeat steps 4.8b through 4.8g for all other bits to be programmed. i. Enable the chip by applying VIL to the CE1 and CE2 and verify the program. Verification may check for a low output by requiring the device to sink 12 mA at VCC = 4.0 V and 0.2 mA at VCC = 7.0 V at TC = +25C. j. If any bit does not verify as programmed it shall be considered a programming reject. 4.9 Programming procedures for circuit C. The programming characteristics in table IVC and the following procedures shall be used for programming the device: a. Connect the device in the electrical configuration for programming. The waveforms on the figure 5c and the programming characteristics of table IVC shall apply to these procedures. b. Terminate all device outputs with a 10 k resistor to VCC. c. Address the PROM with the binary address of the selected word to be programmed. Raise VCC to VCCP = 8.75 0.25 V. d. After a tD delay (10s), apply VOUT = +17 1 V to the output to be programmed. Program one output at a time. e. After a tD delay (10s), pulse CE1 and CE2 inputs to logic "0" for a duration of tP (1 to 2 ms). f. After a tD delay (10s), remove the VOUT pulse from the programmed output. Programming a fuse will cause the output to go to a high-level logic in the verify mode. g. Other bits in the same word may be programmed sequentially while the VCC input is at the VCCP level by applying VOUT pulses to each output to be programmed allowing a delay of tD between pulses as shown on figure 5c. h. Repeat steps 4.9b through 4.9g for all other bits to be programmed. 25 MIL-M-38510/203E i. To verify programming, after tD (10 s) delay, lower VCC to VCCH = +5.5 0.2 V, and apply a logic "0" level to CE1 and CE2 inputs. The programmed output should remain in the "1" state. Again, lower VCC to VCCL = +4.5 0.2 V, and verify that the programmed output remains in the "1" state. j. If any bit does not verify as programmed it shall be considered a programming reject. 4.10 Programming procedure for circuit G. The programming characteristics on table IVD and the following procedures shall be used for programming. a. Connect the device in the electrical configuration of programming. The waveforms on figure 5d and the programming characteristics of table IVD shall apply to these procedures. b. Select the desired word by applying high or low levels to the appropriate address inputs. Disable the device by applying a high level to one or more `active low' chip Enable inputs. NOTE: Address and Enable inputs must be driven with TTL logic levels during programming and verification. c. Increase VCC from nominal to VCCP (10.5 0.5 V) with a slew rate limit of IRR (1.0 to 10.0 V/s). Since VCC is the source of the current required to program the fuse as well as the ICC for the device at the programming voltage, it must be capable of supplying 750 mA at 11.0 volts. d. Select the output where a logical high is desired by raising that output voltage to VOP (10.5 0.5 V). Limit the slew rate to IRR (1.0 to 10.0 V/s). This voltage change may occur simultaneously with the VCC increase to VCCP, but must not precede it. It is critical that only one output at a time be programmed since the internal circuits can only supply programming current to one bit at a time. Outputs not being programmed must be left open or connected to a high impedance source of 20 k minimum (remember that the outputs of the device are disabled at this time). e. Enable the device by taking the chip enable(s) to a low level. This is done with a pulse PWE for 10 s. The 10 s duration refers to 5.0 V (0.25). The time that the circuit (device) is enabled, normal input levels are used and rise and fall times are not critical. f. Verify that the bit has been programmed by first removing the programming voltage from the output and then reducing VCC to 5.0 V (0.25 V). The device must be Enabled to sense the state of the outputs. During verification, the loading of the output must be within specified IOL and IOH limits. g. If the device is not to be tested for VOH over the entire operating range subsequent to programming, the verification of step 4.10f is to be performed at a VCC level of 4.0 volt (0.2 V). VOH, during the 4 V verification, must be at least 2.0 V. The 4.0 V VCC verification assures minimum VOH levels over the entire operating range. h. Repeat steps 4.10b through 4.10f for each bit to be programmed to a high level. If the procedure is performed on an automatic programmer, the duty cycle of VCC at the programming voltage must be limited to a maximum of 25%. This is necessary to minimize device junction temperatures. After all selected bits are programmed; the entire contents of the memory should be verified. i. If any bit does not verify as programmed it shall be considered a programming reject. 26 MIL-M-38510/203E TABLE IVA. Programming characteristics for circuit A. Parameter Address input voltage 2/ Programming Voltage to VCC low Program verify Verify voltage Programming input low current at VPH Programming voltage(VCC) transition time Programming delay Programming pulse width Programming duty cycle Output voltage Enable Disable Symbol Limits 1/ Unit Min Rec Max VIH VIL VPH 3/ VPL VPHV VR 4/ IILP 2.4 0.0 10.75 0.0 --4.5 --- 5.0 0.4 11.0 0.0 5.5 ---300 5.0 0.5 11.25 1.5 --5.5 -600 tTLH tTHL tD1 tD2 tP 5/ PDC 1 1 10 1 90 --- 5 5 10 5 100 30 10 10 20 5 110 60 s " " VOPE 6/ VOPD 10.5 0.0 10.5 5.0 11.0 5.5 V V V V " " " " A " % During the programming the chip must be disabled for proper operation. 1/ TC = +25C. 2/ No inputs should be left open for VIH. 3/ VPH source must be capable of supplying one ampere. 4/ It is recommended that post programming dual verification be made at VR minimum and VR maximum. 5/ Note step j in programming procedure. 6/ VOPE source must be capable of supplying 10 mA minimum. 27 MIL-M-38510/203E TABLE IVB. Programming characteristics for circuit B. Parameter VCC required during programming Rise time of program pulse to data out or program pin Programming voltage on program pin Output programming voltage Programming pin pulse width ( CE ) Pulse width of programming voltage Required current limit of power supply feeding program pin and output during programming Required time delay between disabling memory output and application of output programming pulse Required time delay between removal of programming pulse and enabling memory output Output current during verification Address input voltage Symbol Unit Min Rec Max VCCP 5.4 5.5 5.6 V tTLH 0.34 0.40 0.46 V/s VPP 32.5 33 33.5 V VOUT 25.5 26 26.5 V tPP Chip disabled, VCC = 5.5 V ---- 100 180 s tP Chip disabled, VCC = 5.5 V 1 ---- 40 s IL VPP = 33 V, VOUT = 26 V, VCC = 5.5 V 240 ---- ---- mA TD1 Measured at 10% levels 70 80 90 s TD2 Measured at 10% levels 100 IOLV1 IOLV2 VIH Chip enabled, VCC = 4.0 V Chip enabled, VCC = 7.0 V 11 0.19 2.4 12 0.2 5.0 13 0.21 5.5 mA mA V 0.0 0.4 0.8 V 25 % VIL Maximum duty cycle during automatic programming of program pin and output pin Limits 1/ Conditions D. C. tP / t C 1/ TC = +25C. 28 ns MIL-M-38510/203E TABLE IVC. Programming characteristics for circuit C. Parameter Symbol Rec Max 8.5 8.75 9.0 V VCCH 5.3 5.5 5.7 V VCCL VS 2/ 4.3 1.4 4.5 1.5 4.7 1.6 V V 300 350 400 mA 5.5 V V A A V VCCP 1/ Verification upper limit Verification lower limit Verify threshold ICCP ICCP = 375 75 mA Transient or steady-state VCCP = +8.75 0.25 V 2.4 VIH VIL IIH IIL VOUT 3/ IOUT VIH = +5.5 V VIL = +0.4 V IOUT = 200 20 mA Transient or steady-state VOUT = +17 V 1 V 0 0.4 16 17 0.8 50 -500 18 180 200 220 mA 50 s 0.5 ms tTLH 10 CE programming pulse width tP 0.3 Pulse sequence delay tD 10 Programming time tPR VCC = VCCP Programming pause tPS VCC = 0 V Programming duty cycle Unit Min Programming voltage Programming supply current Input voltage high level "1" Input voltage low level "0" Input current Input current Output programming voltage Output programming current Output pulse transition Limits 1/ Conditions 0.4 s 2.5 s 6 tPR tPR + tPS 50 1/ Bypass VCC to GND with a 0.01 F capacitor to reduce voltage spikes. 2/ VS is the sensing threshold of the PROM output voltage for a programmed bit. It normally constitutes the reference voltage applied to a comparator circuit to verify a successful fusing attempt. 3/ Care should be taken to insure the 17 1 V output voltage is maintained during the entire fusing cycle. The recommended supply is a constant current source clamped at the specified voltage limit. 29 s % MIL-M-38510/203E TABLE IVD. Programming characteristics for circuit G. Parameter Symbol Required VCC for programming ICC during programming VCCP Required output voltage for programming Output current while programming Rate of voltage change of VCC or output Programming pulse width (Enabled) Required VCC for verification Maximum duty cycle for VCC at VCCP Address set-up time VOP ICCP IOP Limits 1/ Conditions Unit Min Rec Max 10.0 10.5 11.0 V 750 mA 11.0 V 20 mA 10.0 V/s VCC = 11 V 10.0 10.5 VOUT = 11 V IRR 1.0 PWE 9 10 11 s VCCV 3.8 4.0 4.2 V 25 25 % MDC t1 100 ns 5 ns VCCP set-up time t2 VCCP hold time t5 100 ns VOP set-up time t3 100 ns VOP hold time t4 100 ns 2/ 1/ TC = +25C 2/ VCCP set-up time may be greater than 0 if VCCP rises at the same rate or faster than VOP. 5. PACKAGING 5.1 Packaging requirements. For acquisition purposes, the packaging requirements shall be as specified in the contract or order (see 6.2). When packaging of materiel is to be performed by DoD or in-house contractor personnel, these personnel need to contact the responsible packaging activity to ascertain packaging requirements. Packaging requirements are maintained by the Inventory Control Point's packaging activity within the Military Service or Defense Agency, or within the military service's system command. Packaging data retrieval is available from the managing Military Department's or Defense Agency's automated packaging files, CD-ROM products, or by contacting the responsible packaging activity. 30 MIL-M-38510/203E 6. NOTES (This section contains information of a general or explanatory nature which may be helpful, but is not mandatory.) 6.1 Intended use. Microcircuits conforming to this specification are intended for logistic support of existing equipment. 6.2 Acquisition requirements. Acquisition documents should specify the following: a. Title, number, and date of the specification. b. PIN and compliance identifier, if applicable (see 1.2). c. Requirements for delivery of one copy of the conformance inspection data pertinent to the device inspection lot to be supplied with each shipment by the device manufacturer, if applicable. d. Requirements for certificate of compliance, if applicable. e. Requirements for notification of change of product or process to contracting activity in addition to notification to the qualifying activity, if applicable. f. Requirements for failure analysis (including required test condition of method 5003 of MIL-STD-883), corrective action, and reporting of results, if applicable. g. Requirements for product assurance options. h. Requirements for special carriers, lead lengths, or lead forming, if applicable. These requirements should not affect the part number. Unless otherwise specified, these requirements will not apply to direct purchase by or direct shipment to the Government. i. Requirement for programming the device, including processing option. The device may be programmed pre- or post-burn-in, if applicable. j. Requirements for "JAN" marking. k. Packaging Requirements (see 5.1) 6.3 Qualification. With respect to products requiring qualification, awards will be made only for products which are, at the time of award of contract, qualified for inclusion in Qualified Manufacturers List QML-38535 whether or not such products have actually been so listed by that date. The attention of the contractors is called to these requirements, and manufacturers are urged to arrange to have the products that they propose to offer to the Federal Government tested for qualification in order that they may be eligible to be awarded contracts or purchase orders for the products covered by this specification. Information pertaining to qualification of products may be obtained from DSCC-VQ, 3990 E. Broad Street, Columbus, Ohio 43218-3990. 6.4 Superseding information. The requirements of MIL-M-38510 have been superseded to take advantage of the available Qualified Manufacturer Listing (QML) system provided by MIL-PRF-38535. Previous references to MIL-M38510 in this document have been replaced by appropriate references to MIL-PRF-38535. All technical requirements now consist of this specification and MIL-PRF-38535. The MIL-M-38510 specification sheet number and PIN have been retained to avoid adversely impacting existing government logistics systems and contractor's parts lists. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535, MIL-HDBK-1331, and as follows: GND ............................................ Electrical ground (common terminal). VIN ............................................... Voltage level at an input terminal VIC ................................................ Input clamp voltage IIN ................................................. Current flowing into an input terminal 31 MIL-M-38510/203E 6.6 Logistic support. Lead materials and finishes (see 3.4) are interchangeable. Unless otherwise specified, microcircuits acquired for Government logistic support will be acquired to device class B (see 1.2.2), lead material and finish C (see 3.4). Longer length leads and lead forming should not affect the part number. It is intended that spare devices for logistic support be acquired in the unprogrammed condition (see 3.8.1) and programmed by the maintenance activity, except where use quantities for devices with a specific program or pattern justify stocking of preprogrammed devices. 6.7 Substitutability. The cross-reference information below is presented for the convenience of users. Microcircuits covered by this specification will functionally replace the listed generic-industry type. Generic-industry microcircuit types may not have equivalent operational performance characteristics across military temperature ranges or reliability factors equivalent to MIL-M-38510 device types and may have slight physical variations in relation to case size. The presence of this information should not be deemed as permitting substitution of generic-industry types for MIL-M-38510 types or as a waiver of any of the provisions of MIL-PRF-38535. * * * * * * Military device type 01 01 01, 03 01, 03 01 01 02 02 02 02 02 03 02, 04 02, 04 04 Generic-industry Type 7610/ Harris Semiconductor 5300-1/ Monolithic Memories 82S126A/ Signetics Corporation 82S126A/ QP Semiconductors 93417/ Fairchild Semiconductor SL82S126/ Lansdale SL82S129/ Lansdale 93427/ Fairchild Semiconductor 54S287/ National Semiconductor 7611/ Harris Semiconductor 5301-1/ Monolithic Memories SL82S126A/ Lansdale 82S129A/ Signetics Corporation 82S129A/ QP Semiconductors SL82S129A/ Lansdale Circuit Designator A B C C D C C D G A B C C C C Fusible Links NiCr NiCr NiCr ZVE NiCr NiCr NiCr NiCr TiW/W NiCr NiCr NiCr NiCr ZVE NiCr Symbol/ FSCM number CDWO/34371 CECD/50364 CDKB/18324 0C7V7 CFJ/07263 58625 58625 CFJ/07263 CCXP/27014 CDWO/34371 CECD/50364 58625 CDKB/18324 0C7V7 58625 6.8 Change from previous issue. Marginal notations are used in this revision to identify changes with respect to the previous issue. Custodians: Army - CR Navy - EC Air Force - 11 DLA - CC Preparing activity: DLA - CC Review activities: Army - SM, MI Navy - AS, CG, MC, SH TD Air Force - 03, 19, 99 (Project 5962-2007-006) NOTE: The activities listed above were interested in this document as of the date of this document. Since organization and responsibilities can change, you should verify the currency of the information above using the ASSIST Online database at http://assist.daps.dla.mil. 32