INCH-POUND
MIL-M-38510/203E
18 September 2007
SUPERSEDING
MIL-M-38510/203D
19 January 2006
MILITARY SPECIFICATION
MICROCIRCUITS, DIGITAL, 1024 BIT SCHOTTKY, BIPOLAR, PROGRAMMABLE READ-ONLY MEMORY (PROM),
MONOLITHIC SILICON
Inactive for new design after 24 July 1995
This specification is approv ed for use by all Departments
and Agencies of the Department of Defense.
The requirements for acquiring the prod uct herein shall consist of this specification sheet and MIL-PRF 385 35.
1. SCOPE
1.1 Scope. This specification covers the det ail requirements for monolithic silicon, programmable read-only memory
(PROM) microcircuits which employ thin film nichrome (NiCr) resistors, tungsten (W), titanium tungsten (TiW), or zapped
* vertical emitter (ZVE) as the fusible link or programmin g element. Two product assurance classes and a choice of case
outlines and lead finishes are provided and are reflected i n the comp lete part number. For this product, the requirements of
MIL-M-38510 have been supersede d by MIL-PRF-38535, (see 6.4).
1.2 Part or Identifying Number (PIN). The PIN is in accordance with MIL-PRF-38535, an d as specified herein.
1.2.1 Device types. The device types are as follows:
Device type Circuit
01, 03 256 word/4 bits per word PROM with uncommitted collector.
02, 04 256 word/4 bits per word PROM with active pull-up and a
third high impedance state output.
1.2.2 Device class. The device class is the product assur ance level as defined in MIL-PRF-38535.
1.2.3 Case outlines. The case outlines are as designated in MIL-STD-1835 and as foll ows:
Outline letter Descriptive designator Terminals Package style
E GDIP1-T16 or CDIP2-T16 16 Dual-in-line
F GDFP2-F16 or CDFP3-F16 16 Flat pack
Comments, suggestions, or questions on this document should be addressed to: Commander, Defense
Supply Center Columbus, ATTN: DSCC-VAS, P. O. Box 3990, Columbus, OH 43218-3990, or emailed to
mailto:memory@dscc.dla.mil . Since contact information can change, you may want to verify the currency of
this address information using the ASSIST Online databas e at http://assist.daps.dla.mil
AMSC N/A FSC 5962
______
MIL-M-38510/203E
1.3 Absolute maximum ratings.
Supply voltage range .............................................................................. -0.5 V dc to +7.0 V dc
Input voltage range ................................................................................. -1.5 V dc at -10 mA to +5.5 V dc
Storage temperature range ..................................................................... -65° to +150°C
Lead temperature (soldering, 10 seconds) .............................................. +300°C
Thermal resistance, junction to case (θJC) 1/ ........................................ See MIL-STD-1835
Output supply voltage ............................................................................. -0.5 C dc to +VCC
Output sink current .................................................................................. +100 mA
Maximum power dissipation (PD) 2/......................................................... 739 mW dc
Maximum junction temperature (TJ)......................................................... +175°C 3/
1.4 Recommended operating conditions.
Supply voltage (VCC) ............................................................................... +4.5 V dc minimum to
+5.5 V dc maximum
Minimum high-level input voltage (VIH) ................................................... 2.0 V dc
Maximum low-level input voltage (VIL) .................................................... 0.8 V dc
Fanout (each output) ............................................................................ 16 mA 4/
Case operating temperature rang e (TC)................................................... -55 °C to +125 °C
2. APPLICABLE DOCUMENTS
2.1 General. The documents listed in this section are specified in sections 3, 4, or 5 of this specification. This section
does not include documents cited in other sections of this specification or recommended for additional information or as
examples. While every effort has been mad e to ensure th e completeness of this list, document users are cautioned that
they must meet all specified requireme nts of docume nts cited in sections 3, 4, or 5 of this specification, whether or not
they are listed.
2.2 Government documents.
2.2.1 Specifications and Standards. The following specifications and standards form a part of this specification to the
extent specified herein. Unl ess otherwise specified, the issues of these documents are those cited in the solicitation or
contract.
DEPARTMENT OF DEFENSE SPECIFICATIONS
MIL-PRF-38535 - Integrated Circuits (Microcircu its) Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Method Standard for Microelectronics.
MIL-STD-1835 - Interface Standard Electronic Component Case Outline
1/ Heat sinking is recommended to reduce th e junction temperature.
2/ Must withstand the added PD due to short circuit test (e.g. IOS).
3/ Maximum junction temperature shall not b e exceeded except for allowable short duration burn-in scre ening conditions
per MIL-PRF-38535.
4/ 12 mA for circuit B.
2
MIL-M-38510/203E
(Copies of these documents ar e available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil
or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.3 Order of precedence. In the event of a conflict between the text of this specification and the references cited
herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable l aws and
regulations unless a specific exemption has been obtaine d.
3. REQUIREMENTS
3.1 Qualification. Microcircuits furnished un der this specification shall be products that are manufactured by a
manufacturer authorized by the qualifying activit y for listing on the applicable qualified ma nufacturers list before contract
award (see 4.3 and 6.3).
3.2 Item requirements. The individual item requ irements shall be in accordanc e with MIL-PRF-38535 and as
specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The modification in the QM
plan shall not affect the form, fit, or function as described herein.
3.3 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as
specified in MIL-PRF-38535 and herein.
3.3.1 Terminal connections. The terminal connections shall be as specified on figure 1.
3.3.2 Truth table
3.3.2.1 Unprogrammed devices. The truth table for unprogrammed devices for contrac t s involving no altered item
drawing shall be as specified on figure 2. When required in groups A, B, or C (see 4.4), the devices sh all be
programmed by the manufacturer prior to test in a checkerb oard pattern (a minimum of 50 percent of the total number of
bits programmed) or to any altered item drawing pattern which includes at least 25 percent of the total number of bits
programmed.
3.3.2.2 Programmed devices. The truth table for programmed devices shall be as specified by the altered item
drawing.
3.3.3 Functional block diagram. The functional block diagram shall be as specified on figure 3.
3.3.4 Case outlines. The case outlines shall be as specified in 1.2.3.
3.4 Lead material and finish. The lead material and finish shall be in accordance with MIL-PRF-38535 (see 6.6).
3.5 Electrical performance characteristics . The electrical performance characteristics are as specifi ed in table I, and
apply over the full recommended case operating temperat ure range, unless otherwise specified.
3.6 Electrical test requirements. The electrical test requirements shall be as specified in table II, and where
applicable, the altered item drawing. The electrical tests for each subgroup are descri bed in table III.
3.7 Marking. Marking shall be in accorda nce with MIL-PRF-38535. For programmed devices, the altered item
drawing number shall be added to the marking by the programming activity.
3
MIL-M-38510/203E
TABLE I. Electrical performance characterist ics.
Characteristic Symbol Conditions 1/
-55°C ≤ TC ≤ +125°C Device
type Limits Unit
Min Max
High level output voltage VOH VCC = 4.5 V;
IOH = -2 mA,
VIL = 0.8 V, VIH = 2.0 V
02,04 2.4 --- V
Low level output voltage VOL VCC = 4.5 V;
IOL = 16 mA 2/
VIL = 0.8 V, VIH = 2.0 V
01,02
03,04 --- 0.5 V
Input clamp voltage VIC VCC = 4.5 V;
IIN = -10 mA;
TC = 25°C
01,02
03,04 --- -1.5 V
Maximum collector cut-off
current ICEX VCC = 5.5 V;
VO = 5.2 V 01,03 --- 100
μA
High impedance (off-state)
output high current IOHZ VCC = 5.5 V;
VO = 5.2 V 02,04 --- 100
μA
High impedance (off-state)
output low current IOLZ VCC = 5.5 V;
VO = .5 V 02,04 --- -100
μA
High level input current IIH1 VCC = 5.5 V;
VIN = 5.5 V 01,02
03,04 --- 50 μA
High level input current IIH2 VCC = 5.5 V; VIN = 4.5 V;
special program pin 01,02
03,04 --- 100 μA
Low level input current IIL VCC = 5.5 V;
VIN = 0.5 V 01,02
03,04 -1 -250 μA
Short circuit output
current IOS VCC = 5.5 V; 3/
VO = 0.0 V 02,04 -10 -100 mA
Supply current ICC VCC = 5.5 V;
VIN = 0; outputs open 01,02
03,04 --- 130 mA
Propagation delay time
high-to-low level logic,
address to output
tPHL1 VCC = 4.5 V and 5.5 V;
CL = 30 pF minimum;
see figure 5
01, 02 --- 75 ns
03, 04 --- 35
Propagation delay time
low-to-high level logic,
address to output
tPLH1 01, 02 --- 75 ns
03, 04 --- 35
Propagation delay time
high-to-low level logic,
enable to output
tPHL2 01, 02 --- 35 ns
03, 04 --- 20
Propagation delay time
low-to-high level logic,
enable to output
tPLH2 01, 02 --- 35 ns
03, 04 --- 20
1/ Complete terminal conditions shall be specified in table III.
2/ IOL = 12 mA for circuit B.
3/ Not more than one outp ut shall be grounded at one time. Output shall be at high logic level prior
to test.
4
MIL-M-38510/203E
TABLE II. Electrical test requirements.
MIL-PRF-38535
test requirements
Subgroups (see table III)
1/, 2/, 3/
Class S
devices Class B
devices
Interim electrical parameters 1 1
Final electrical test parameters
for unprogrammed devices 1*, 2, 3, 7*,
8 1*, 2, 3,
7*, 8
Final electrical test parameters
for programmed devices 1*, 2, 3, 7*
8, 9, 10, 11 1*, 2, 3, 7*,
8, 9
Group A test requirements 1, 2, 3, 7, 8,
9, 10, 11 1, 2, 3, 7, 8
9, 10, 11
Group B end-point electrical parameters
when using the method 5005 QCI option 1, 2, 3, 7, 8,
9, 10, 11 N/A
Group C end-point electrical
parameters 1, 2, 3, 7, 8,
9, 10, 11 1, 2, 3, 7, 8
Group D test requirements 1, 2, 3, 7, 8 1, 2, 3, 7, 8
1/ * indicates PDA applies to subgroups 1 and 7.
2/ Any or all subgroups may be combined when using high-speed testers.
3/ Subgroups 7 and 8 shall consist of verifying the pattern specified.
3.8 Processing options. Since the PRO M is an unprogrammed memory capable of being programmed by either the
manufacturer or the user to result in a wide variety of PROM configurations, two processing options are provided for
selection in the contract, using an altered ite m drawing.
3.8.1 Unprogrammed PROM delivered to the user. All testing shall be verified throu gh group A testing as defined in
3.3.2.1, table II, and table III. It is recommended that users perform subgroups 7 and 9 after programming to verify the
specific program configuratio n.
3.8.2 Manufacturer-programmed PROM delivered to the user. All testing requirements and quality assurance
provisions herein, including th e requirements of the altered item drawing, shall be satisfied by the manufacturer prior to
delivery.
3.9 Microcircuit group assignment. The devices covered by this specification shall be in microcircuit group number
14 (see Appendix A MIL-PRF-38535.)
5
MIL-M-38510/203E
4. VERIFICATION
4.1 Sampling and inspection. Sampling and inspection procedures shall b e in accordance with MIL-PRF-38535 or
as modified in the device ma nufacturer's Quality Management (QM) plan. The modification in the QM pla n shall not
effect the form, fit, or function as described herein.
4.2 Screening. Screening shall be in accordance with MIL-PRF-38535 and shall be co nducted on all devices prior to
qualification and quality conformance inspecti on. The following additional criteria shall apply:
a. The burn-in test duration, test condition, and test temperature, or approved alternatives shall b e as specified
in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be
maintained under document control b y the device manufacturer's Technology Review Board (TRB) in
accordance with MIL-PRF-38535 and shall be made available to the acq uiring or preparing activity upon
request. The test circuit shall specif y the inputs, outputs, biases, and power dissipation, as applicable, in
accordance with the intent specified in test method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table II, except interim electrical
parameters test prior to burn-in is optional at the discretion of the manufacturer.
c. Additional screening for space level product shall be as specified in MIL-PRF-38535, appendix B.
d. Class B devices processed to an altered item drawing may be programmed either before or after
burn-in at the manufacturer’s discretion. T he required electrical testing sh all include, as a
minimum, the final electrical tests for programmed devices as specified in table II herein. Class S devices
processed by the manufacturer to an altered item drawing shall be programmed prior to
burn-in.
4.3 Qualification inspection. Qualification inspection shall be in accord ance with MIL-PRF-38535.
4.3.1 Qualification extensio n . When authorized by the qualifying activity, for qualification inspection, if a
manufacturer qualifies to a faster device type which is manufactured identically to a slower device type on this
specification, then the slower device type may be part I qualified by conducting only group A electrical tests and any
electricals specified as additional group C subgroups and submitting data in accordanc e wit h MIL-PRF - 38535
(i.e.,groups B, C, and D tests are not required).
4.4 Technology Conformance inspection (TCI). Technology conformance inspection shall be in accordance with
MIL-PRF-38535 and as specified herein for groups A, B, C, and D inspections (see 4.4.1 through 4.4.4).
6
MIL-M-38510/203E
4.4.1 Group A inspection. Group A inspection shall be in accordance with table III of MIL-PRF-38535 and as follows:
a. Electrical test requirements shall be as specified in table II herein.
b. Subgroups 4, 5, and 6 shall be omitted.
c. For unprogrammed devices, a sample shall be selected to satisfy programmability requirements prior to
performing subgroups 9. 10, and 11. Twelve devices shall be submitted to programming (see 3.3.2.1). If
more than 2 devices fail to program, the lot shall be rejected, At the manufacturer’s optio n, the sample may
be increased to 24 total devices with no mor e than 4 total d evice failures allowable.
d. For unprogrammed devices, 10 devices from the programmability sample shall be submitted to the
requirements of group A, subgroups 9, 10, and 11. If more than two total devices fail in all three subgroups,
the lot shall be rejected. At the manufacturer’s option, the sampl e ma y be increased to 20 total devices with
no more than 4 total device failures allowable.
4.4.2 Group B inspection. Group B inspection shall be in accordance with table II MIL-PRF-38535.
4.4.3 Group C inspection. Group C inspection shall be in accordance with table IV of MIL-PRF-38535 and as follows:
a. End-point electrical parameters shall be as specified in table II herein.
b. The steady-state life test duration, test condition, and test temperature, or approved alternatives shall be as
specified in the device manufacturer' s QM plan in accordance with MIL-PRF-38535. The burn-in test circuit
shall be maintained under document control by the device manufacturer's Technology Review Board (TRB) in
accordance with MIL-PRF-38535 and shall be made available to the acq uiring or preparing activity upon
request. The test circuit shall specif y the inputs, outputs, biases, and power dissipation, as applicable, in
accordance with the intent specified in test method 1005 of MIL-STD-883.
c. For qualification, at least 50 percent of the sample selected for life testing shall be programmed (see 3.3.2).
For quality conformance insp ection, the programmability sample (see 4.4.1c) shall be includ ed in the life test.
4.4.4 Group D inspection. Group D inspection shall be in accordance with table V of MIL-PRF-38535. End-point
electrical parameters shal l be as specified in table II herein.
4.5 Methods of inspection. Methods of inspection shall be a s specified and as follows:
4.5.1 Voltage and current. All voltages give n are referenced to the microcircuit ground terminal. Currents given are
conventional and positive when flowing into the referenced terminal.
7
MIL-M-38510/203E
Device type All
Case outline E and F
Terminal number Terminal symbol
1 A6
2 A5
3 A4
4 A3
5 A0
6 A1
7 A2
8 GND
9 O4
10 O3
11 O2
12 O1
13 CE 1
14 CE 2
15 A7
16 VCC
FIGURE 1. Terminal connections.
8
MIL-M-38510/203E
Word
no. Enable Address Data
CE 1 CE 2 A7 A6 A5 A4 A3 A2 A1 A0 01 02 03 04
NA L L X X X X X X X X 5/ 5/ 5/ 5/
NA L H X X X X X X X X OC OC OC OC
NA H L X X X X X X X X OC OC OC OC
NA H H X X X X X X X X OC OC OC OC
NOTES:
1. NA = Not applicable.
2. X = Input may be high level, low level, or open circuit.
3. OC = Open circuit (high resistance output).
4. Program readout can only be accomplished with both enable inputs at low level.
5. The outputs for an unprogrammed device shall be high for circuits A and B, and shall be low for circuit C and G.
FIGURE 2. Truth table (unprogrammed).
9
TEST
ROW
SELECT
1
OF
32
DECODER
z
:c
:::,
..J
0
u A
I-
"'
ILi
I-
B
CIRCUIT
A
z
:c
:::,
..J
0
A A A u
I-
"'
ILi
I-
B B B
Oz
MIL-M-38510/203E
A = 32 x 8 Memory Array
B = 1 of 8 Decoder
FIGURE 3. Functional block diagram.
10
Ao
Az
ADDRESS
BUFFER
X
1
OF
32
DECODER
32
DRIVER
ADDRESS1-----------1
BUFFER
l-----------1
y
ZENER
DIODE
CE
10-------+--\
CEz0--------1
CIRCUIT
B
D
32
D
32
D
32
D
E
Oz
MIL-M-38510/203E
A = Enable buffer
B = Output buffer
C = Programming driver
D = 256 bit memory, 32 x 8 matrix
E = 1 of 8 Y decoder multiplexer
FIGURE 3. Functional block diagram – Continued.
11
A3
INPUT
BUFFER
A4
A5
As
A7
CE
1
0-----<1
CE2v----q
4
X
DECODE
6
11•32)
2
TESTRDW
32
8 X
32
8 X
32
8 X
32
8 X
32
ARRAY ARRAY
ARRAY ARRAY
MIL-M-38510/203E
CIRCUIT C
FIGURE 3. Functional block diagram – Co ntinued.
12
Vee
INPUT
Ao
A1
Az
A3
01
PULSE
SEE
A4
Oz
GENERATOR
TEST
PRR
~
1
MHz
TABLE
A5
03
As
04
A7
CE1
INPUT-~Y-=-<-1_o_n_s~~-----Y-<-10-ns-
OUTPUT
WAVEFORM
A
----<
500
ns----~
OUTPUT
l
\[
WAVEFORM
_a
_____
~
-----------
\~---
_-
_-_
-_
-_-_
R1
Rz
CL
3.0
*0.1
V
Z.7
V
1.5
V
0.7
V
0 V
*0.1
V
VoH
1.5
V
Vol
VoH
1.5
V
Vol
MIL-M-38510/203E
NOTES:
1. Test table for devices programmed in acc ordance with an altered item drawing may be replaced by the equivalent tests
which apply to the specific program configuration for the resulting read-on ly memory
2. CL = 30 pF minimum, including jig and probe capacitance, R1 =330 Ω ±25%, and R2 = 680 Ω ±20%.
3. Outputs may be under load simultaneousl y.
FIGURE 4. Switching time test circuit.
14
MIL-M-38510/203E
NOTE: All other waveform characteristics shall be as spec ified in table IVA.
FIGURE 5a. Typical programming voltage waveforms during programming for circuit A.
15
ADDRESSES
~-----------------
_/\
_____
----=:;:j"""i"-;::--;::=-------~
TTL
HIGH
PROGRAM
LI
tpp
i--
TTL
LOW
p
IN
______
t_JT=CH:...
:t=l
.=.=.=.=.=::::::--:::--:::--:::--:::--:::--:::=-
~6/
OUTPUT
PIN
STROBE
I
10%
--j~:02
TTL
LOW
/~7-0V
5.5
V
--4.0
V
TTL
HIGH
--TTL
LOW
CHECK
MIL-M-38510/203E
NOTES:
1. Output load is 0.2 mA and 12 mA during 7.0 V and 4.0 V check respectively.
2. All other waveform characteristics shall b e as specified in table IVB.
FIGURE 5b. Typical programming voltage waveforms during programming for circuit B.
16
A~~~5~s
"~.t...1.J.
_____
A_F_1R_s_1
______
LI LI
___
A_L_A_s_1
__
__,JI
:::
1:::
:::
MIL-M-38510/203E
NOTE: All other waveform characteristics shall be as spec ified in table IVC.
FIGURE 5c. Typical Programming voltage waveforms during programming for circuit C.
17
MIL-M-38510/203E
4.6 Programming procedure identification. The programming procedure to be utilized shall be identified by the
manufacturer’s circuit designator.
4.7 Programming procedure for circuit A. T he programming characteristics in table IVA and the following
procedures shall be used for programmin g the device.
a. Connect the device in the electrical configuration for programming. The waveforms on figure 5a and the
programming characteristics in table IVA shall apply to these procedures.
b. Address the PROM with the binary address of the word to be programmed. Address inp uts are TTL compatible.
An open circuit shall not be used to address the PROM.
c. Apply VPL voltage to VCC.
d. Bring the CE X inputs high and the CE X inputs low to disable the device. The chip enables are T TL
compatible. An open circuit shall not be used to disable the devices.
e. Disable the programming circuitry by applying a voltage of VOPD to the outputs of the PROM.
f. Raise VCC to VPH with rise time less than or equal to tTLH.
g. After a delay equal to or greater than tD1 apply only one pulse with amp litude of VOPE and duration of tp to the
output selected for programming. Note that the PROM is supplied with fuses intact, which generates an output
high. Programming a fuse will cause the output to go low.
h. Lower VCC to VPL following a delay to tD2 from programming enable pulse applied to a n output.
i. Enable the PROM for verification by applying VIL to CE X and VIH to CE X .
j. Apply VPHV to VCC and verify bit is program med.
k. Repeat steps a through j for all other bits to be programmed in the PROM.
l. If any bit does not verify as programmed, it shall be considered a programming reject.
19
TABLE III. Group A inspection for device type 01, 03.
Terminal conditions Outputs: Not desi gnated are open or resistive coupled to GND or voltage .
Inputs: Not designated are high ≥ 2.0 V, low ≤ 0.8 V, or open.
MIL-M-38510/203E
20
Subgroup Symbol MIL-
STD-883
method
Cases
E,F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Measured
terminal Test limits Unit
Test no. A6
A
5
A
4
A
3
A
0
A
1
A
2 GND O4
O
3
O
2
O
1 CE 1 CE 2 A7
V
CC Min Max
1
TC=+25°C VIC 1
2
3
4
5
6
7
8
9
10
-10mA
-10mA -10mA -10mA -10mA -10mA -10mA
GND
“
“
“
“
“
“
“
“
“
-10mA -10mA -10mA
4.5V
“
“
“
“
“
“
“
“
“
A6
A5
A4
A3
A0
A1
A2
CE1
CE2
A7
-1.5
“
“
“
“
“
“
“
“
“
V
“
“
“
“
“
“
“
“
“
VOL 3007
“
“
“
11
12
13
14
1/
“
“
“
1/
“
“
“
1/
“
“
“
1/
“
“
“
1/
“
“
“
3/ 1/
“
“
“
1/
“
“
“
“
“
“
“
2/
2/ 2/ 2/
0.8V 0.8V 4/ 1/
“
“
“
“
“
“
“
O4
O3
O2
O1
0.5
“
“
“
“
“
“
“
IIL 3009
“
“
“
“
“
“
“
“
“
15
16
17
18
19
20
21
22
23
24
0.5V
0.5V 0.5V 0.5V 0.5V 0.5V 0.5V
“
“
“
“
“
“
“
“
“
“
0.5V 0.5V 0.5V
5.5V
“
“
“
“
“
“
“
“
“
A6
A5
A4
A3
A0
A1
A2
CE1
CE2
A7
-1.0
“
“
“
“
“
“
“
“
“
-250
“
“
“
“
“
“
“
“
“
μA
“
“
“
“
“
“
“
“
“
IIH1
IIH2
3010
“
“
“
“
“
“
“
“
“
25
26
27
28
29
30
31
32
33
34
5.5V
5.5V 5.5V 5.5V 5.5V 5.5V 5.5V
“
“
“
“
“
“
“
“
“
“ 4.5V 5.5V 5.5V
“
“
“
“
“
“
“
“
“
“
A6
A5
A4
A3
A0
A1
A2
A7
CE2
CE1
50
“
“
“
“
“
“
“
“
100
“
“
“
“
“
“
“
“
“
“
ICEX 35
36
37
38
“
“
“
“
5.2V
5.2V 5.2V 5.2V
5.5V
“
“
“
5.5V
“
“
“ “
“
“
“
O4
O3
O2
O1
100
“
“
“
“
“
“
“
ICC 3005 39 GND GND GND GND GND GND GND “ GND GND GND “ VCC 130 mA
2 Same tests, terminal conditions, and limits as for subgroup 1, except TC = +125°C and VIC tests are omitted.
3 Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55°C and VIC tests are omitted.
7
TC=+25°C Funct-
ional
test
5/ 40 5/ 5/ 5/ 5/ 5/ 5/ 5/ GND 5/ 5/ 5/ 5/ 5/ 5/ 5/ 5/ Outputs 5/
See footnotes at end of device type 02.
26
TABLE III. Group A inspection for device type 01, 03 – Continued.
Terminal conditions Outputs: Not desi gnated are open or resistive coupled to GND or voltage .
Inputs: Not designated are high ≥ 2.0 V, low ≤ 0.8 V, or open.
Subgroup Symbol MIL-
STD-883 Cases
E,F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Measured
terminal Test limits Unit
method Test no. A6
A
5
A
4
A
3
A
0
A
1
A
2 GND O4
O
3
O
2
O
1 CE 1 CE 2 A7
V
CC Min Max
8 Same tests, terminal conditions, and limits as subgroup 7, except TC = +125°C and -55°C.
9
TC=+25°C tPHL1
tPLH1
tPHL2
tPLH2
GALPAT
Fig. 4
GALPAT
Fig. 4
Sequen-
tial
Fig. 4
Sequen-
tial
Fig. 4
41
42
43
44
8/
8/
10/
10/
8/
8/
10/
10/
8/
8/
10/
10/
8/
8/
10/
10/
8/
8/
10/
10/
8/
8/
10/
10/
8/
8/
10/
10/
GND
“
“
“
9/
“
“
“
9/
“
“
“
9/
“
“
“
9/
“
“
“
GND
GND
10/
10/
GND
GND
10/
10/
8/
8/
10/
10/
8/
8/
10/
10/
Outputs
“
“
“
11
/
“
“
“
ns
“
“
“
10 Same tests, terminal conditions, and limits as subgroup 9, except TC = +125°C.
11 Same tests, terminal conditions, and limits as subgroup 9, except TC = -55°C.
See footnotes at end of device type 02.
MIL-M-38510/203E
21
28
TABLE III. Group A inspection for device type 02, 04.
Terminal conditions Outputs: Not desi gnated are open or resistive coupled to GND or voltage .
Inputs: Not designated are high ≥ 2.0 V, low ≤ 0.8 V, or open.
MIL-M-38510/203E
22
Subgroup Symbol MIL-
STD-883 Cases
E,F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Measured
terminal Test limits Unit
method Test no. A6
A
5
A
4
A
3
A
0
A
1
A
2 GND O4
O
3
O
2
O
1 CE 1 CE 2 A7
V
CC Min Max
1
TC=+25°C VIC 1
2
3
4
5
6
7
8
9
10
-10mA
-10mA -10mA -10mA -10mA -10mA -10mA
GND
“
“
“
“
“
“
“
“
“
-10mA -10mA -10mA
4.5V
“
“
“
“
“
“
“
“
“
A6
A5
A4
A3
A0
A1
A 2
CE1
CE2
A7
-1.5
“
“
“
“
“
“
“
“
“
V
“
“
“
“
“
“
“
“
“
VOL 3007 11 1/ 1/ 1/ 1/ 1/ 3/ 1/ 1/ “ 2/ 0.8V 0.8V 4/ 1/ “ O4
0.5
“
“ 12 “ “ “ “ “ “ “ “ 2/ “ “ “ “ O3 “ “
“ 13 “ “ “ “ “ “ “ “ 2/ “ “ “ “ O2 “ “
“ 14 “ “ “ “ “ “ “ “ 2/ “ “ “ “ O1“ “
VOH 3006 15 1/ 6/ 1/ 6/ 1/ 6/ 1/ 6/ 1/ 6/ 1/ 6/ 1/ 12/ 6/ “ -2mA “ “ 6/ 1/ “ O4 2.4
“
“ 16 “ “ “ “ “ “ “ “ -2mA “ “ “ “ O3 “ “
“ 17 “ “ “ “ “ “ “ “ -2mA “ “ “ “ O2 “ “
“ 18 “ “ “ “ “ “ “ “ -2mA “ “ “ “ O1 “ “
IIL 3009 19 0.5V “ 5.5V A6 -1.0 -250 μA
“ 20 0.5V “ “ A5 “ “ “
“ 21 0.5V “ “ A4 “ “ “
“ 22 0.5V “ “ A3 “ “ “
“ 23 0.5V “ “ A0 “ “ “
“ 24 0.5V “ “ A1“ “ “
“ 25 0.5V “ “ A2 “ “ “
“ 26 “ 0.5V “ CE1 “ “ “
“ 27 “ 0.5V “ CE2 “ “ “
“ 28 “ 0.5V “ A7 “ “ “
IIH1 3010 29 5.5V “ “ A6
50
“
“ 30 5.5V “ “ A5 “ “
“ 31 5.5V “ “ A4 “ “
“ 32 5.5V “ “ A3 “ “
“ 33 5.5V “ “ A0 “ “
“ 34 5.5V “ “ A1 “ “
“ 35 5.5V “ “ A2 “ “
“ 36 “ 5.5V “ A7 “ “
“ 37 “ 5.5V “ CE2 “ “
IIH2 “ 38 “ 4.5V “ CE1100 “
IOHZ 39 “ 5.2V 5.5V 7/ 5.5V 7/
“
O4
100
“
40 “ 5.2V “ “ “ O3 “ “
41 “ 5.2V “ “ “ O2 “ “
42 “ 5.2V “ “ “ O1“ “
IOLZ 43 “ 0.5V “ “
“
O4 -100 “
44 “ 0.5V “ “ “ O3 “ “
45 “ 0.5V “ “ “ O2 “ “
46 “ 0.5V “ “ “ O1“ “
ICC 3005 47 GND GND GND GND GND GND GND “ GND GND GND “ VCC 130 mA
IOS 3011 48 1/ 6/ 1/ 6/ 1/ 6/ 1/ 6/ 1/ 6/ 1/ 6/ 1/ 12/ 6/ “ GND 0.5V 0.5V 6/ 1/ “ O4 -10 -100 “
“ 49 “ “ “ “ “ “ “ “ GND “ “ “ “ O3 “ “ “
“ 50 “ “ “ “ “ “ “ “ GND “ “ “ “ O2 “ “ “
“ 51 “ “ “ “ “ “ “ “ GND “ “ “ “ O1 “ “ “
See footnotes at end of device type 02.
TABLE III. Group A inspection for device type 02, 04.
Terminal conditions Outputs: Not desi gnated are open or resistive coupled to GND or voltage .
Inputs: Not designated are high ≥ 2.0 V, low ≤ 0.8 V, or open.
MIL-M-38510/203E
23
Subgroup Symbol MIL-
STD-883
method
Cases
E,F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Measured
terminal Test limits Unit
Test no. A6
A
5
A
4
A
3
A
0
A
1
A
2 GND O4
O
3
O
2
O
1 CE 1 CE 2 A7
V
CC Min Max
2 Same tests, terminal conditions, and limits as for subgroup 1, except TC = +125°C and VIC tests are omitted.
3 Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55°C and VIC tests are omitted.
7
TC=+25°C Funct-
ional
test
5/ 52 5/ 5/ 5/ 5/ 5/ 5/ 5/ GND 5/ 5/ 5/ 5/ 5/ 5/ 5/ 5/ Outputs 5/
8 Same tests, terminal conditions, and limits as for subgroup 7, except TC = +125°C and -55°C.
9
TC=+25°C tPHL1
tPLH1
tPHL2
tPLH2
GALPAT
Fig. 4
GALPAT
Fig. 4
Sequen-
tial
Fig. 4
Sequen-
tial
Fig. 4
53
54
55
56
8/
8/
10/
10/
8/
8/
10/
10/
8/
8/
10/
10/
8/
8/
10/
10/
8/
8/
10/
10/
8/
8/
10/
10/
8/
8/
10/
10/
GND
“
“
“
9/
“
“
“
9/
“
“
“
9/
“
“
“
9/
“
“
“
GND
GND
10/
10/
GND
GND
10/
10/
8/
8/
10/
10/
8/
8/
10/
10/
Outputs
“
“
“
11
/
“
“
“
ns
“
“
“
10 Same tests, terminal conditions, and limits as subgroup 9, except TC = +125°C.
11 Same tests, terminal conditions, and limits as subgroup 9, except TC = -55°C.
1/ For programmed devices, select an appropriate address to acquire the desired output state, VIL = 0.8 V, VIH = 2.0 V.
2/ 16 mA for circuits A, C and G.
12 mA for circuit B.
3/ For unprogrammed devices, a pply 12.0 V on pin 6 (A1) for circuit B devices.
4/ For unprogrammed devices, a pply 13 V on pins 1 (A6) and 2 (A5) for circuit A devices.
5/ The functional tests shall verify that no fuses are bl own for unprogrammed devices or that the truth table specified in the a ltered item drawing exists for
programmed devices (see 3.3.2). All bits shall be tested. Terminal conditio ns shall be as follows:
a. Inputs: H = 3.0 V, L = GND
b. Outputs: Output voltage shall be either:
1. H = 2.4 V minimum and L = 0.5 V maxim um when using a high speed checker double comparator, or
2. H ≥ 1.0 V and L ≤ 1.0 V when using a high speed checker single comparator.
c. The functional tests shall be performe d with VCC = 4.5 V and VCC = 5.5 V.
6/ For unprogrammed 02 device s (82S129); apply 10.0 V on pin 15 (A7), apply 0.5 V on pin 2 (A5) and 5.0 V on all other address lines for circuit C devices. For
unprogrammed 04 devices (82S129A) apply 10.0 V on pin 5 (A0) and 5.0 V on all other address pins for the circuit C devices.
7/ 2.4 V for circuit B devices.
I I I I I
MIL-M-38510/203E
8/ GALPAT (PROGRAMMED PROM)
This program will test all bits in the array, the addressing and interaction between bits for ac performance, tPHL1, and
tPLH1. Each bit in the pattern is fixed by being programmed with a “H” or “L”.
Description
1. Word 0 is read.
2. Word 1 is read
3. Word 0 is read
4. Word 2 is read
5. Word 0 is read
6. The reading proced ure continues back and forth between word 0 and the next higher numbered word until word
255 is reached, then increments to the next word and reads back and forth as in steps 1 through 6 and shall
include all words.
7. Pass execution time = (n2 + n) x cycle time. n = 256.
8. The GALPAT tests shall be performed with VCC = 4.5 V and 5.5 V.
9/ The outputs are loaded per figure 5.
10
/ SEQUENTIAL TEST (PROGRAMMED PROM)
This program will test all bits in the array for tPHL2 and tPLH2.
Description
1. Each word in the pattern is tested from the enable lines to the output lines for recovery.
2. Word 0 is addressed. Enable line is pulle d hi to lo a nd lo to hi. tPHL2 and tPLH2 are read.
3. Word 1 is addressed. Same enable s eq uence as above.
4. The reading procedure continues until word 255 is reached.
5. Pass execution time = 256 x cycle time.
6. The sequential tests shall be performed with VCC = 4.5 V and 5.5 V
11/ The limits shall be as follows:
Device 01,02 Device 03,04
TPHL1 75 ns TPHL1 35 ns
TPLH1 75 ns TPLH1 35 ns
TPHL2 35 ns TPHL2 20 ns
TPLH2 35 ns TPLH2 20 ns
12/ F or unpro grammed circuit G devices; apply 11.0 V on pi n 7 (A2).
24
MIL-M-38510/203E
4.8 Programming procedure for circuit B. The programming characteristics in table IVB and the foll owing
procedures shall be used for programmin g the device:
a. Connect the device in the electrical configuration for programming. The waveforms on figure 5b and
the programming characteristics of table IVB shall apply to these procedures.
b. Raise VCC to 5.5 V.
c. Address the PROM with the binary address of the selected word to be programmed. Address inputs are
TTL compatible.
d. Disable the chip by applyi ng VIH to CE2 and CE1 inputs. CE1 and CE2 inputs are TTL compatible.
e. Apply the VPP pulse to the pr ogramming pin ( CE1 ). In order to insure that the output transistor is off before
increasing the voltage on the output pin, the program pin’s voltage pulse shall precede the output pin’s
programming pulse by TD1 and leave after the output pins programming pulse b y TD2 (see figure 5b).
f. Apply the VOUT pulse with duration of tP to the output selected for programming (see table IVB). T he
outputs shall be programmed one o utput at a time, since internal decoding circuitry is capabl e of sinking
only one unit of programming current at a time. Note that the PROM is supplied with fuses generating a
high level logic output. Programming a fuse will cause the output to go to a low level logic in the verify
mode.
g. Other bits in the same word may be programmed sequentially by applying VOUT pulses to each output to
be programmed.
h. Repeat steps 4.8b through 4.8g for all other bits to be progr ammed.
i. Enable the chip by applying VIL to the CE1 and CE2 and verify the program. Verification may check for a
low output by requiring the device to sink 12 mA at VCC = 4.0 V and 0.2 mA at VCC = 7.0 V at TC = +25°C.
j. If any bit does not verify as programmed it shall be consi dered a programming reject.
4.9 Programming proce dures for circuit C. The programming characteristics i n table IVC a nd the following
procedures shall be used for programmin g the device:
a. Connect the device in the electrical configuration for programming. The waveforms on the figure 5c and
the programming characteristi cs of table IVC shall apply to these procedures.
b. Terminate all device outputs with a 10 kΩ resistor to VCC.
c. Address the PROM with the binary address of the selected word to be programmed.
Raise VCC to VCCP = 8.75 ± 0.25 V.
d. After a tD delay (10μs), apply VOUT = +17 ± 1 V to the output to be programmed. Program one output at a
time.
e. After a tD delay (10μs), pulse CE1 and CE2 inputs to logic “0” for a duration of tP (1 to 2 ms).
f. After a tD delay (10μs), remove the VOUT pulse from the programmed output. Programming a fuse will
cause the output to go to a high-level logic in the verify mode.
g. Other bits in the same word may be programmed sequentially while the VCC input is at the VCCP level by
applying VOUT pulses to each output to be programmed allowing a delay of tD between pulses as shown on
figure 5c.
h. Repeat steps 4.9b through 4.9g for all other bits to be progr ammed.
25
MIL-M-38510/203E
i. To verify programming, after tD (10 μs) delay, lower VCC to VCCH = +5.5 ± 0.2 V, and apply a logic “0” level
to CE1 and CE2 inputs. The programmed output sh ould remain in the “1” state. Again, lower
VCC to VCCL = +4.5 ± 0.2 V, and verify that the programmed output remains in the “1” state.
j. If any bit does not verify as programmed it shall be consid ered a programming reject.
4.10 Programming procedure for circuit G. The programming characteristics on table IVD and the following
procedures shall be used for programming.
a. Connect the device in the electrical configuration of programming. The waveforms on figure 5d and the
programming characteristics of table IVD shall apply to these procedures.
b. Select the desired word by applying high or low levels to the appropriate address inputs. Disable the
device by applying a high level to one or more ‘active l ow’ chip Enable inputs. NOT E: Address and Enable
inputs must be driven with TTL logic levels during progr amming and verification.
c. Increase VCC from nominal to VCCP (10.5 ±0.5 V) with a slew rate limit of IRR (1.0 to 10.0 V/μs). Since VCC is
the source of the current required to program the fuse as well as the ICC for the device at the programming
voltage, it must be capable of supplying 750 mA at 11.0 volts.
d. Select the output where a logical high is desired by raising that output voltage to VOP (10.5 ±0.5 V). Limit
the slew rate to IRR (1.0 to 10.0 V/μs). This voltage change may occur simultaneously with the VCC
increase to VCCP, but must not precede it. It is critical that only one output at a time be programmed since
the internal circuits can only supply programming current to one bit at a time. Outputs not being
programmed must be left open or connected to a high impedance source of 20 kΩ minimum (remember
that the outputs of the device are disabled at this time).
e. Enable the device by taking the chip ena ble(s) to a low level. This is done with a pulse PWE for 10 μs.
The 10 μs duration refers to 5.0 V (±0.25). The time that the circuit (device) is enabled, normal input levels
are used and rise and fall times are not critical.
f. Verify that the bit has been programmed by first removing the programming voltage from the output and
then reducing VCC to 5.0 V (±0.25 V). The device must be Enabled to sense the state of the outputs.
During verification, the loading of the output must be within specified IOL and IOH limits.
g. If the device is not to be tested for VOH over the entire operating range subs equent to programming, the
verification of step 4.10f is to be performed at a VCC level of 4.0 volt (±0.2 V). VOH, during t he 4 V
verification, must be at least 2.0 V. The 4.0 V VCC verification assures minimum VOH levels over the entire
operating range.
h. Repeat steps 4.10b through 4.10f for each bit to be programmed to a high level. If the procedure is
performed on an automatic programmer, the dut y cycle of VCC at the programming voltage must be limited
to a maximum of 25%. This is necessary to minimize device junction temperatures. After all selected bits
are programmed; the entire contents of the memory should be verified.
i. If any bit does not verify as programmed it shall be considered a programming rej ect.
26
MIL-M-38510/203E
TABLE IVA. Programming characteristics for circuit A.
Parameter Symbol Limits 1/ Unit
Min Rec Max
Address input voltage 2/ VIH
VIL 2.4
0.0 5.0
0.4 5.0
0.5 V
V
Programming
Voltage to VCC low
Program verify
Verify voltage
VPH 3/
VPL
VPHV
VR 4/
10.75
0.0
---
4.5
11.0
0.0
5.5
---
11.25
1.5
---
5.5
“
“
“
“
Programming input low
current at VPH IILP --- -300 -600
μA
Programming voltage(VCC)
transition time tTLH
tTHL 1
1 5
5 10
10 μs
“
Programming delay tD1
tD2 10
1 10
5 20
5 “
Programming pulse width tP 5/ 90 100 110 “
Programming duty cycle PDC --- 30 60 %
Output voltage
Enable
Disable VOPE 6/
VOPD 10.5
0.0 10.5
5.0 11.0
5.5 V
V
During the programming the chip must be disabled for pro per operation.
1/ TC = +25°C.
2/ No inputs should be left open for VIH.
3/ VPH source must be capable of supplying o ne ampere.
4/ It is recommended that post programming dual verification b e made at VR minimum and VR maximum.
5/ Note step j in programming procedure.
6/ VOPE source must be capable of supplying 10 mA minimum.
27
MIL-M-38510/203E
TABLE IVB. Programming characteristics for circuit B.
Parameter Symbol Conditions Limits 1/ Unit
Min Rec Max
VCC required during
programming VCCP 5.4 5.5 5.6 V
Rise time of program
pulse to data out or
program pin
tTLH 0.34 0.40 0.46
V/μs
Programming voltage on
program pin VPP 32.5 33 33.5 V
Output programming
voltage VOUT 25.5 26 26.5 V
Programming pin pulse
width ( CE ) tPP Chip disabled, VCC = 5.5 V ---- 100 180 μs
Pulse width of
programming voltage tP Chip disabled, VCC = 5.5 V 1 ---- 40 μs
Required current limit of
power supply feeding
program pin and output
during programming
IL VPP = 33 V, VOUT = 26 V,
VCC = 5.5 V 240 ---- ---- mA
Required time delay
between disabling
memory output and
application of output
programming pulse
TD1 Measured at 10% levels 70 80 90 μs
Required time delay
between removal of
programming pulse and
enabling memory output
TD2 Measured at 10% levels 100 ns
Output current during
verification IOLV1 Chip enabled, VCC = 4.0 V 11 12 13 mA
IOLV2 Chip enabled, VCC = 7.0 V 0.19 0.2 0.21 mA
Address input voltage VIH 2.4 5.0 5.5 V
VIL 0.0 0.4 0.8 V
Maximum duty cycle
during automat ic
programming of program
pin and output pin
D. C. tP/ tC 25 %
1/ TC = +25°C.
28
MIL-M-38510/203E
TABLE IVC. Programming characteristics for circuit C.
Parameter Symbol Conditions Limits 1/ Unit
Min Rec Max
Programming voltage V CCP 1/ ICCP = 375 ±75 mA
Transient or steady-state 8.5 8.75 9.0 V
Verification upper limit VCCH 5.3 5.5 5.7 V
Verification lower limit VCCL 4.3 4.5 4.7 V
Verify threshold VS 2/ 1.4 1.5 1.6 V
Programming supply
current ICCP VCCP = +8.75 ± 0.25 V 300 350 400 mA
Input voltage high level
“1” VIH 2.4 5.5 V
Input voltage low level “0” VIL 0 0.4 0.8 V
Input current IIH VIH = +5.5 V 50 μA
Input current IIL VIL = +0.4 V -500 μA
Output programming
voltage VOUT 3/ IOUT = 200 ±20 mA
Transient or steady-state 16 17 18 V
Output programming
current IOUT VOUT = +17 V ± 1 V 180 200 220 mA
Output pulse transition tTLH 10 50
μs
CE programming pulse
width tP 0.3 0.4 0.5 ms
Pulse sequence delay t D 10 μs
Programming time tPR VCC = VCCP 2.5
μs
Programming pause tPS VCC = 0 V 6 μs
Programming duty cycle tPR
tPR + tPS 50 %
1/ Bypass VCC to GND with a 0.01 μF capacitor to reduce voltage spikes.
2/ VS is the sensing threshold of the PROM output voltage for a programmed bit. It normally constitutes the
reference voltage applied to a comparator ci rcuit to verify a successful fusing attempt.
3/ Care should be taken to insure the 17 ±1 V output voltage is maintained during the entire fusing cycle. The
recommended supply is a constant current source cl amped at the specified voltage limit.
29
MIL-M-38510/203E
TABLE IVD. Programming characteristics for circuit G.
Parameter Symbol Conditions Limits 1/ Unit
Min Rec Max
Required VCC for
programming VCCP 10.0 10.5 11.0 V
ICC during programming ICCP VCC = 11 V 750 mA
Required output voltage
for programming VOP 10.0 10.5 11.0 V
Output current while
programming IOP VOUT = 11 V 20 mA
Rate of voltage change of
VCC or output IRR 1.0 10.0
V/μs
Programming pulse width
(Enabled) PWE 9 10 11
μs
Required VCC for
verification VCCV 3.8 4.0 4.2 V
Maximum duty cycle for
VCC at VCCP MDC 25 25 %
Address set-up time t1 100 ns
VCCP set-up time t2 2/ 5 ns
VCCP hold time t5 100 ns
VOP set-up time t3 100 ns
VOP hold time t4 100 ns
1/ TC = +25°C
2/ VCCP set-up time may be greater than 0 if VCCP rises at the same rate or faster than VOP.
5. PACKAGING
5.1 Packaging requirements. For acquisition purposes, the packaging requirements shall be as specified in the
contract or order (see 6.2). When packaging of materiel is to be performed b y DoD or in-house contractor personnel,
these personnel need to contact the responsible packaging activity to ascertain packaging req uirements. Packaging
requirements are maintained by the Inventory Control Point's packaging activity within the Military Service or Defense
Agency, or within the military service's system command. Packaging data retrieval is availabl e from the managing
Military Department's or Defe nse Agency's automated packaging files, CD-ROM products, or by contacting the
responsible packaging activity.
30
MIL-M-38510/203E
6. NOTES
(This section contains information of a g eneral or explanatory nature which may be helpful, but is not
mandatory.)
6.1 Intended use. Microcircuits conforming to this specification are intended for log istic support of existing
equipment.
6.2 Acquisition requirements. Acquisition do c uments should specify the follo wing:
a. Title, number, and date of the specification.
b. PIN and compliance i dentifier, if applicable (see 1.2).
c. Requirements for delivery of o ne copy of the conformance inspection data pertinent to the device
inspection lot to be supplied with eac h shipment by the device manufacturer, if applicable.
d. Requirements for certificate of compliance, if applicable.
e. Requirements for notification of change of product or process to contracting activity in addition to
notification to the qualifying activity, if applicable.
f. Requirements for failure analysis (inclu ding required test condition of method 5003 of MIL-STD-883),
corrective action, and reporting of results, if applicable.
g. Requirements for prod uct assurance options.
h. Requirements for speci al carri ers, lead lengths, or lead forming, if applicable. These req uirements should
not affect the part number. Unless otherwise specified, these requirements will not apply to direct
purchase by or direct shipment to the Government.
i. Requirement for programming the device, including processing option. The device may be programmed
pre- or post-burn-in, if applicable.
j. Requirements for "JAN" marking.
k. Packaging Requirements (see 5.1)
6.3 Qualification. With respect to products requiring qualification, awards will be made only for products which
are, at the time of award of contract, qualified for inclusion in Qualified Manufacturers List QML-38535 whether or not
such products have actually been so listed b y that date. The attention of the contractors is called to these
requirements, and manufacturers are urged to arrange to have the products that they propose to offer to the Federal
Government tested for qualification in order that they may be eligible to be awarded contracts or purchase orders for
the products covered by this specification. Information pertaining to qual ification of products may be obtained from
DSCC-VQ, 3990 E. Broad Street, Columbus, Ohio 43218-3990.
6.4 Superseding information. The requirements of MIL-M-38510 have b e en superseded to take advantage of the
available Qualified Manufactur er Listing (QML) system provided by MIL-PRF-38535. Previous references to MIL-M-
38510 in this document have been replaced by appropriate references to MIL-PRF-38535. All technical requirements
now consist of this specification and MIL-PRF-385 35. The MIL-M-38510 specification sheet number and PIN have
been retained to avoid adversely impacting existing g overnment logistics systems and contractor's parts lists.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined
in MIL-PRF-38535, MIL-HDBK-1331, and as follows:
GND ............................................ Electrical ground (common terminal).
VIN ............................................... Voltage level at an input terminal
VIC................................................ Input clamp voltage
IIN ................................................. Current flowing into an input terminal
31
MIL-M-38510/203E
6.6 Logistic support. Lead materials and fini shes (see 3.4) are interchangeable. Unl ess otherwise specified,
microcircuits acquired for Government logistic support will be acquired to device class B (see 1.2.2), lead material
and finish C (see 3.4). Longer length l ea ds and lead forming should not affect the part number. It is intended that
spare devices for logistic support be acquired in the unprogrammed conditi on (see 3.8.1) and programmed b y the
maintenance activit y, except where use q ua ntities for devices with a specific program or pattern justify stocking of
preprogrammed devices.
6.7 Substitutability. T he cross-reference information below is presented for the convenience of users.
Microcircuits covered by this specification will functio nally replace the listed generic-industry type. Generic-industry
microcircuit types may not have equivalent op erational performance characteristics across military temperature
ranges or reliability factors equivalent to MIL-M-38510 device types and may have slight physical variations in relation
to case size. The presence of this information should not be deemed as permitting substitution of generic-industr y
types for MIL-M-38510 types or as a waiver of any of the provisio ns of MIL-PRF-38535.
*
*
*
*
*
Military
device type Generic-industry
Type Circuit
Designator Fusible
Links Symbol/
FSCM number
01 7610/ Harris Semiconductor A NiCr CDWO/3437 1
01 5300-1/ Monolithic Memories B NiCr CECD/50364
01, 03 82S126A/ Signetics Corporation C NiCr CDKB/18324
01, 03 82S126A/ QP Semiconductors C ZVE 0C7V7
01 93417/ Fairchild Semiconductor D NiCr CFJ/07263
01 SL82S126/ Lansdale C NiCr 58625
02 SL82S129/ Lansdale C NiCr 58625
02 93427/ Fairchild Semiconductor D NiCr CFJ/07263
02 54S287/ National Semiconductor G TiW/W CCXP/2701 4
02 7611/ Harris Semiconductor A NiCr CDWO/3437 1
02 5301-1/ Monolithic Memories B NiCr CECD/50364
03 SL82S126A/ Lansdale C NiCr 58625
02, 04 82S129A/ Signetics Corporation C NiCr CDKB/18324
02, 04 82S129A/ QP Semiconductors C ZVE 0C7V7
04 SL82S129A/ Lansdale C NiCr 58625
6.8 Change from previous issue. Marginal n otations are used in this revision to identify changes with respect to the
* previous issue.
Custodians:
Army - CR
Navy - EC
Air Force - 11
DLA - CC
Review activities:
Army – SM, MI
Navy - AS, CG, MC, SH TD
Air Force – 03, 19, 99
Preparing activity:
DLA - CC
(Project 5962-2007-006)
NOTE: The activities listed above were inte rested in this docume nt as of the date of this document. Since
organization and responsi bilities can change, you should verify the currency of the inform ation above using the
ASSIST Online database at http://assist.daps.dla.mil.
32
