©2000 Fairchild Semiconductor International
May 2000
Rev. A, May 2000
FQP13N10
QFET
QFETQFET
QFETTM
FQP13N10
100V N-Ch annel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for low voltage applications such as audio amplifier,
high efficiency switching DC/DC converters, and DC motor
control.
Features
12.8A, 100V, RDS(on) = 0.18 @VGS = 10 V
Low gate charge ( typical 12 nC)
Low Crss ( typical 20 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
175°C maximum junction temperature rating
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Thermal Characteristics
Symbol Parameter FQP13N10 Units
VDSS Drain-Source Voltage 100 V
IDDrain Current - Continuous (TC = 25°C) 12.8 A
- Continuous (TC = 100°C) 9.05 A
IDM Drain Current - Pulsed (Note 1) 51.2 A
VGSS Gate-Source Voltage ± 25 V
EAS Single Pulsed Avalanche Energy (Note 2) 95 mJ
IAR Avalanche Current (Note 1) 12.8 A
EAR Repetitive Avalanche Energy (Note 1) 6.5 mJ
dv/dt Peak Diode Recovery dv/dt (Note 3) 6.0 V/ns
PDPower Dissipation (TC = 25°C) 65 W
- Derate above 25°C 0.43 W/°C
TJ, TSTG Operating and Storage Temperature Range -55 to +175 °C
TLMaximum lead temperature for soldering purposes,
1/8" from case for 5 seconds 300 °C
Symbol Parameter Typ Max Units
RθJC Thermal Resistance, Junction-to-Case -- 2.31 °C/W
RθCS Thermal Resistance, Case-to-Sink 0.5 -- °C/W
RθJA Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W
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S
D
G
GS
D TO-220
FQP Series
©2000 Fairchild Semiconductor International
FQP13N10
(Note 4)
(Note 4, 5)
(Note 4, 5)
(Note 4)
Rev. A, May 2000
Electrical Characteristics TC = 25°C unless otherwise noted
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 0.87mH, IAS = 12.8A, VDD = 25V, RG = 25 Ω, Starting TJ = 25°C
3. ISD 12.8 A, di/dt 300A/µs, VDD BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width 300µs, Duty cycle 2%
5. Essentially independent of operating temperature
Symbol Parame ter Test Condit i ons Min Typ Max Units
Off Characteristics
BVDSS Drain-S ource Breakdown Voltage VGS = 0 V, I D = 250 µA100 -- -- V
BVDSS
/ TJ
Breakdown Voltage Temperature
Coefficient ID = 250 µA, Referenced to 25°C -- 0.09 -- V/°C
IDSS Zero Gate Voltage Drain Current VDS = 100 V, VGS = 0 V -- -- 1 µA
VDS = 80 V, TC = 150°C -- -- 10 µA
IGSSF Gate-Body Leakage Current, Forward VGS = 25 V, VDS = 0 V -- -- 100 nA
IGSSR Gate-Body Leakage Current, Reverse VGS = -25 V, VDS = 0 V -- -- -100 nA
On Characteri st ics
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA3.0 -- 5.0 V
RDS(on) Static Drain-Source
On-Resistance VGS = 10 V, ID = 6.4 A -- 0.142 0.18
gFS Forward Transconduct ance VDS = 40 V, ID = 6.4 A -- 6.8 -- S
Dynamic Characteristics
Ciss Input Capacitance VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
-- 345 450 pF
Coss Output Capacitance -- 100 130 pF
Crss Reverse Transfer Capacitance -- 20 25 pF
Switching Characteristics
td(on) Turn-On Delay Time VDD = 50 V, ID = 12.8 A,
RG = 25
-- 5 20 ns
trTurn-On Rise Time -- 55 120 ns
td(off) Turn-Off D e l a y Time -- 20 50 ns
tfTurn-Off F all Time -- 25 60 ns
QgTotal Gate Ch arge VDS = 80 V, ID = 12.8 A,
VGS = 10 V
-- 12 16 nC
Qgs Gate-Source Charge -- 2.5 -- nC
Qgd Gate-Drain Charge -- 5.1 -- nC
Drain-Source Diode Characteristics and Maximum Ratings
ISMaximum Continuous Drain-Source Diode Forward Current -- -- 12.8 A
ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 51.2 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 12.8 A -- -- 1.5 V
trr Reverse Recovery Time VGS = 0 V, I S = 12.8 A,
dIF / dt = 100 A/µs
-- 72 -- ns
Qrr Reverse Recovery Charge -- 0.17 -- µC
©2000 Fairchild Semiconductor International
FQP13N10
Rev. A, May 2000
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
10-1
100
101
175
Notes :
1. VGS = 0V
2. 250μ
s Pulse Test
25
IDR, Reverse Drain Current [A]
VSD, So u r c e - Dra i n volta g e [V ]
246810
10-1
100
101
No tes :
1 . VDS = 40V
2. 250μ
s Pu lse T est
-55
175
25
ID , Drain Current [A ]
VGS , Gate-Source Voltage [V]
0 10203040
0.0
0.2
0.4
0.6
0.8
VGS = 20V
VGS = 10V
N ote : T J = 25
RDS(ON) [Ω],
Drain-Source On-Resistance
ID, Drain Current [A]
10-1 100101
10-1
100
101
VGS
Top : 15.0 V
10.0 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom : 4.5 V
Notes :
1. 250μ
s Pulse Test
2. TC = 25
ID, Drain Current [A]
VDS, Drain-Source Voltage [V]
024681012
0
2
4
6
8
10
12
VDS = 50V
VDS = 80V
Note : ID = 12.8A
VGS, Gate-Source Voltage [V]
QG, T ota l Ga te Cha rg e [nC]
10-1 100101
0
150
300
450
600
750
900 Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
Notes :
1. VGS = 0 V
2. f = 1 MHz
Crss
Coss
Ciss
Capacitance [pF]
VDS, Drain-Source Voltage [V]
Typical Characteristics
Figure 5. C apacitanc e Ch aracterist i cs Figure 6. Ga te Ch arge Cha ra ct eri stics
Figu re 3. On-Resi stan ce Vari ation vs.
Drain Current and Gate Voltage Figure 4. Body Diode Fo rwa rd Voltage
Variation vs. Source Current
and Temperature
Figure 2. Transfer CharacteristicsFigure 1. On- R egi on Character i st ic s
©2000 Fairchild Semiconductor International
FQP13N10
Rev. A, May 2000
25 50 75 100 125 150 175
0
3
6
9
12
15
ID, Drain Current [A]
TC, Case Temperature [
]
100101102
10-1
100
101
102
DC
10 m s 1 ms
100 µs
Op era tion in Th is A r e a
is Limited by R DS(on)
Notes :
1. TC = 25 oC
2. TJ = 175 oC
3. Single Pulse
ID, D rain C urrent [A]
VDS, Drain-Source Voltage [V]
-100 -50 0 50 100 150 200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Notes :
1. VGS = 10 V
2. ID = 6.4 A
RDS(ON) , (Normalized)
Drain-Source On-Resistance
TJ, Junction Temperature [oC]
-100 -50 0 50 100 150 200
0.8
0.9
1.0
1.1
1.2
Notes :
1 . VGS = 0 V
2 . ID = 250 μ
A
BV DSS , (N ormaliz e d )
Drain-Source Breakdow n Voltage
TJ, Junction Tem perature [oC]
10-5 10-4 10-3 10-2 10-1 100101
10-2
10-1
100
No te s :
1 . ZθJC(t) = 2.31 /W Max .
2 . D u ty F a c to r, D = t1/t2
3 . TJM - T C = PDM * Z θJC(t)
single p ulse
D=0.5
0.02
0.2
0.05
0.1
0.01
ZθJC
(t), T herm al R esponse
t1, S quare W ave Pulse D uration [sec]
Typical Characteristics (Continued)
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
Figu re 7. Breakdown Voltage Variat i on
vs. Temperature Figure 8. On-Resistance Variation
vs. Temperature
Figure 11. Transient Thermal Res pons e Cur ve
t1
PDM
t2
©2000 Fairchild Semiconductor International
FQP13N10
Rev. A, May 2000
Charge
VGS
10V Qg
Qgs Qgd
3mA
VGS
DUT
VDS
300nF
50KΩ
200nF
12V
Same Type
as DUT
Charge
VGS
10V Qg
Qgs Qgd
3mA
VGS
DUT
VDS
300nF
50KΩ
200nF
12V
Same Type
as DUT
VGS
VDS
10%
90%
td(on) tr
ton toff
td(off) tf
VDD
10V
VDS RL
DUT
RG
VGS
VGS
VDS
10%
90%
td(on) tr
ton toff
td(off) tf
VDD
10V
VDS RL
DUT
RG
VGS
EAS =LI
AS2
----
2
1--------------------
BVDSS -V
DD
BVDSS
VDD
VDS
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
10V DUT
RG
L
ID
t p
EAS =LI
AS2
----
2
1
EAS =LI
AS2
----
2
1
----
2
1--------------------
BVDSS -V
DD
BVDSS
VDD
VDS
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
10V DUT
RG
LL
ID
ID
t p
Gate Charge Test Circuit & Waveform
Resist iv e Sw itc h ing Test Circ ui t & Waveform s
Unclamped Inductive Switching Test Circuit & Waveforms
©2000 Fairchild Semiconductor International
FQP13N10
Rev. A, May 2000
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
VDS
+
_
Driver
RGSame Type
as DUT
VGS dv/dt controlled by RG
•I
SD con troll e d by pul s e period
VDD
L
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
DUT
VDS
+
_
Driver
RGSame Type
as DUT
VGS dv/dt controlled by RG
•I
SD con troll e d by pul s e period
VDD
LL
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
©2000 Fairchild Semiconductor International
FQP13N10
Rev. A, May 2000
Package Dimensions
4.50 ±0.20
9.90 ±0.20
1.52 ±0.10
0.80 ±0.10 2.40 ±0.20
10.00 ±0.20
1.27 ±0.10
ø3.60 ±0.10
(8.70)
2.80 ±0.1015.90 ±0.20
10.08 ±0.30 18.95MAX.
(1.70)
(3.70)(3.00)
(1.46)
(1.00)
(45°)
9.20 ±0.2013.08 ±0.20
1.30 ±0.10
1.30 +0.10
–0.05
0.50 +0.10
–0.05
2.54TYP
[2.54 ±0.20]2.54TYP
[2.54 ±0.20]
TO-220
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This datasheet contains the design specifications for
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changes at any time without notice in order to improve
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