IRFR9120NPbF
IRFU9120NPbF
HEXFET® Power MOSFET
VDSS = -100V
RDS(on) = 0.48Ω
ID = -6.6A
12/14/04
Parameter Typ. Max. Units
RθJC Junction-to-Case 3.1
RθJA Junction-to-Ambient (PCB mount)** 50 °C/W
RθJA Junction-to-Ambient 110
Thermal Resistance
D-Pak
T
O-252AA I-Pak
TO-251AA
lUltra Low On-Resistance
lP-Channel
lSurface Mount (IRFR9120N)
lStraight Lead (IRFU9120N)
lAdvanced Process Technology
lFast Switching
lFully Avalanche Rated
Description
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ -10V -6.6
ID @ TC = 100°C Continuous Drain Current, VGS @ -10V -4.2 A
IDM Pulsed Drain Current -26
PD @TC = 25°C Power Dissipation 40 W
Linear Derating Factor 0.32 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy100 mJ
IAR Avalanche Current-6.6 A
EAR Repetitive Avalanche Energy4.0 mJ
dv/dt Peak Diode Recovery dv/dt -5.0 V/ns
TJOperating Junction and -55 to + 150
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
°C
Absolute Maximum Ratings
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
and reliable device for use in a wide variety of applications.
The D-Pak is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU series) is for through-hole mounting
applications. Power dissipation levels up to 1.5 watts are
possible in typical surface mount applications.
S
D
G
PD-95020A
lLead-Free
www.irf.com 1
IRFR/U9120NPbF
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) showing the
ISM Pulsed Source Current integral reverse
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage -1.6 V TJ = 25°C, IS = -3.9A, VGS = 0V
trr Reverse Recovery Time 100 150 ns TJ = 25°C, IF = -4.0A
Qrr Reverse Recovery Charge 420 630 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
-6.6
-26
A
Notes:
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
This is applied for I-PAK, LS of D-PAK is measured between
lead and center of die contact
Starting TJ = 25°C, L = 13mH
RG = 25Ω, IAS = -3.9A. (See Figure 12)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
ISD ≤ -4.0A, di/dt ≤ 300A/µs, VDD ≤ V
(BR)DSS,
TJ ≤ 150°C
Pulse width ≤ 300µs; duty cycle ≤ 2%.
S
D
G
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage -100 V VGS = 0V, ID = -250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient -0.11 V/°C Reference to 25°C, ID = -1mA
RDS(on) Static Drain-to-Source On-Resistance 0.48 ΩVGS = -10V, ID = -3.9A
VGS(th) Gate Threshold Voltage -2.0 -4.0 V VDS = VGS, ID = -250µA
gfs Forward Transconductance 1.4 S VDS = -50V, ID = -4.0A
-25 µA VDS = -100V, VGS = 0V
-250 VDS = -80V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage 100 VGS = 20V
Gate-to-Source Reverse Leakage -100 nA VGS = -20V
QgTotal Gate Charge 27 ID = -4.0A
Qgs Gate-to-Source Charge 5.0 nC VDS = -80V
Qgd Gate-to-Drain ("Miller") Charge 15 VGS = -10V, See Fig. 6 and 13
td(on) Turn-On Delay Time 14 VDD = -50V
trRise Time 47 ID = -4.0A
td(off) Turn-Off Delay Time 28 RG = 12 Ω
tfFall Time 31 RD =12 Ω, See Fig. 10
Between lead,
6mm (0.25in.)
from package
and center of die contact
Ciss Input Capacitance 350 VGS = 0V
Coss Output Capacitance 110 pF VDS = -25V
Crss Reverse Transfer Capacitance 70 = 1.0MHz, See Fig. 5
nH
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
LDInternal Drain Inductance
LSInternal Source Inductance
IGSS
ns
4.5
7.5
IDSS Drain-to-Source Leakage Current
S
D
G
Uses IRF9520N data and test conditions.
IRFR/U9120NPbF
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1
1
10
100
0.1 1 10 100
20µs PULS E WID TH
T = 25 C
J°
TOP
BOTTOM
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
-4.5V
-V , Drain-to-Source Voltage (V)
-I , Drain-to-Source Current (A)
DS
D
-4.5V
0.1
1
10
100
0.1 1 10 100
20µs PULS E WID TH
T = 150 C
J°
TOP
BOTTOM
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
-4.5V
-V , Drain-to-Source Voltage (V)
-I , D rai n-t o-Source Cur rent (A)
DS
D
-4.5V
0.1
1
10
100
45678910
V = -50V
20µs PULSE WIDTH
DS
-V , Gate-to-Source Voltage (V)
-I , Dr ain-to- Source Cur rent (A)
GS
D
T = 25 C
J°
T = 150 C
J°
-60 -40 -20 020 40 60 80 100 120 140 160
0.0
0.5
1.0
1.5
2.0
2.5
T , Junction Te mperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
-10V
-6.7A
IRFR/U9120NPbF
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
1 10 100
0
200
400
600
800
-V , Drain-to-Source Voltage (V )
C, Capacitance (pF)
DS
V
C
C
C
=
=
=
=
0V,
C
C
C
f = 1MHz
+ C
+ C
C SHORTED
GS
iss gs gd , ds
rss gd
oss ds gd
Ciss
Coss
Crss
0 5 10 15 20 25
0
4
8
12
16
20
Q , Total Gate Charge (nC)
-V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
-4.0 A
V =-20V
DS
V =-50V
DS
V =-80V
DS
0.1
1
10
100
0.2 0.8 1.4 2.0 2.6
-V ,Sou rce- to-Drain Voltage (V)
-I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 150 C
J°
0.1
1
10
100
1 10 100 1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
Single Pulse
T
T = 150 C
= 25 C
°°
J
C
-V , Drain-to-Source Voltage (V)
-I , Drain Current (A)I , Drain Current (A)
DS
D
10us
100us
1ms
10ms
IRFR/U9120NPbF
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10a. Switching Time Test Circuit
Fig 10b. Switching Time Waveforms
VDS
-10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
VDD
RG
D.U.T.
+
-
V
DS
9
0%
1
0%
V
GS
t
d(on)
t
r
t
d(off)
t
f
25 50 75 100 125 150
0.0
2.0
4.0
6.0
8.0
T , Case Temperature ( C)
-I , Drain Current (A)
°
C
D
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1 10
Notes:
1. Du ty factor D = t / t
2. Peak T =P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SIN GLE PULSE
(THER MAL RESPO NSE)
IRFR/U9120NPbF
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Q
G
Q
GS
Q
GD
V
G
Charge
-10V
D.U.T. VD
S
ID
IG
-3mA
VGS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tpV
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
V
DS
V
DD
DRIVER
A
15V
-20V
-
+VDD
25 50 75 100 125 150
0
50
100
150
200
250
Starting T , Junction Temperature ( C)
E , Single Pulse Avalanche Energy (mJ)
J
AS
°
ID
TOP
BOTTOM
-1.7A
-2.5A
-3.9A
IRFR/U9120NPbF
Peak Diode Recovery dv/dt Test Circuit
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
RG
VDD
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T*Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
* Reverse Polarity of D.U.T for P-Channel
VGS
[ ]
[ ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
[ ] ***
Fig 14. For P-Channel HEXFETS
IRFR/U9120NPbF
D-Pak (TO-252AA) Part Marking Information
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
12
IN THE ASSEMBLY LINE "A"
ASSEMBLED ON W W 16, 1999
EXAMPLE: WITH ASS EMBLY
THIS IS AN IRFR120
LOT C ODE 1234 YEAR 9 = 19 9
9
DATE CODE
WE EK 16
PART NUMBER
LOGO
INTERNATIONAL
RECTIFIER
AS S EMBLY
LOT CODE
916A
IRFU120
34
YEAR 9 = 1999
DA TE C ODE
OR
P = D ESIGN ATES LEAD -FREE
PRODUCT (OPTIONAL)
N ote: "P " in assembly line position
indicates "Lea d-Free"
12 34
WEEK 16
A = ASSEMBLY SITE CODE
PART NUMBER
IRFU120
LINE A
LOGO
LOT CODE
AS S E MB L Y
INTERNATIONAL
RECTIFIER
IRFR/U9120NPbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
AS S EMB LY
EXAMPLE: WIT H AS SEMBLY
THIS IS AN IRFU120
YEAR 9 = 199
9
DATE CODE
LINE A
WEEK 19
IN T HE ASSEMBLY LINE "A"
ASSEM BLED O N WW 19, 1999
LOT CODE 5678
PART NUMBER
56
IRFU120
INTERNATIONAL
LOGO
RECTIFIER
LOT CODE
919A
78
Note: "P" in assembly line
pos ition indicates "L ead-F ree"
OR
56 78
AS S E MB LY
LOT CODE
RECTIFIER
LOGO
INTERNATIONAL
IRFU120
PART NUMB ER
WEEK 19
DATE CODE
YEA R 9 = 1999
A = AS SE MB LY S IT E CODE
P = DE S IGNAT ES L EAD-FREE
PRODUCT (OPTIONAL)
IRFR/U9120NPbF
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 ) FEED DIRECTION FEED DIRECTION
16.3 ( .641
)
15.7 ( .619
)
TRR TRL
N
OTES :
1
. CONTROLLI NG DIM E NS I ON : MILLIM E TER.
2
. ALL DIMENSION S ARE SHOW N IN MILLIMETERS ( INCHES ).
3
. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
