General Description
The MAX16000–MAX16007 are low-voltage, quad/hex/
octal-voltage μP supervisors in small TQFN and TSSOP
packages. These devices provide supervisory functions
for complex multivoltage systems. The MAX16000/
MAX16001/MAX16002 monitor four voltages, the
MAX16003/MAX16004/MAX16005 monitor six voltages,
and the MAX16006/MAX16007 monitor eight voltages.
The MAX16000/MAX16001/MAX16003/MAX16004/
MAX16006 offer independent outputs for each
monitored voltage. The MAX16001/MAX16002/
MAX16004– MAX16007 offer a reset output that asserts
whenever any of the monitored voltages fall below their
respective thresholds or the manual reset input is asserted.
The reset output remains asserted for the reset timeout
after all voltages are above their respective thresholds
and the manual reset input is deasserted. The minimum
reset timeout is internally set to 140ms or can be adjusted
with an external capacitor.
All open-drain outputs have internal 30μA pullups that
eliminate the need for external pullup resistors. However,
each output can be driven with an external voltage up to
5.5V. Other features offered include a manual reset input,
a tolerance pin for selecting 5% or 10% input thresholds,
and a margin enable function for deasserting the outputs
during margin testing.
The MAX16001/MAX16002/MAX16004–MAX16007 offer
a watchdog timer that asserts RESET or an independent
watchdog output (MAX16005) when the watchdog timeout
period (1.6s typ) is exceeded. The watchdog timer can be
disabled by leaving the input open.
These devices are offered in 12, 16, 20, and 24-pin TQFN
and 16-pin TSSOP packages. These are fully specified
from -40°C to +125°C.
Applications
● Storage Equipment
● Servers
● Networking/Telecommunication Equipment
● Multivoltage ASICs
Benets and Features
● Fixed Thresholds for 5V, 3.3V, 3V, 2.5V, 1.8V, 1.5V,
1.2V, and 0.9V Systems
●Adjustable Thresholds Monitor Voltages Down to 0.4V
● Open-Drain Outputs with Internal Pullups Reduce the
Number of External Components
● Fixed 140ms (min) or Capacitor-Adjustable Reset
Timeout
● Manual Reset, Margin Enable, and Tolerance Select
Inputs
● Watchdog Timer
• 1.6s (typ) Timeout Period
• 54s Startup Delay After Reset (Except MAX16005)
● Independent Watchdog Output (MAX16005)
● RESET Output Indicates All Voltages Present
● Independent Voltage Monitors
● Guaranteed Correct Logic State Down to VCC = 1V
● Small (4mm x 4mm) TQFN Package
● TSSOP (5mm x 4.4mm) Package (MAX16005)
Selector Guide appears at end of data sheet.
Ordering Information continued at end of data sheet.
19-3870; Rev 7; 4/16
Note: The “_” is a placeholder for the input voltage threshold.
See Table 1.
+Denotes a lead(Pb)-free/RoHS-compliant package.
For tape-and-reel, add a “T” after the “+.” Tape-and-reel are
offered in 2.5k increments.
*EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE
MAX16000_TC+ -40°C to +125°C 12 TQFN-EP*
MAX16005
GND
P
TOL
VCC SRT
MR
IN1 MARGINVIN1
VIN2
VIN3
VIN4
VIN5
VIN6
RESET
WDI
WDO
RST
I/O
NMI
IN2
IN3
IN4
IN5
IN6
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
μP Supervisors
Typical Operating Circuit
Ordering Information
VCC, OUT_, IN_, RESET, WDO to GND ................-0.3V to +6V
TOL, MARGIN, MR, SRT, WDI, to GND ...... -0.3V to VCC + 0.3
Input/Output Current (RESET, MARGIN,
SRT, MR, TOL, OUT_, WDO, WDI) .............................±20mA
Continuous Power Dissipation (TA = +70°C)
12-Pin TQFN (derate 16.9mW/°C above +70°C) ......1349mW
16-Pin TQFN (derate 16.9mW/°C above +70°C) ......1349mW
20-Pin TQFN (derate 16.9mW/°C above +70°C) ......1355mW
24-Pin TQFN (derate 16.9mW/°C above +70°C) ......1666mW
16-Pin TSSOP (derate 9.4mW/°C above +70°C) ........754mW
Operating Temperature Range ......................... -40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
(VCC = 2.0V to 5.5V, TA = -40°C to +125°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Voltage Range VCC (Note 2) 1.0 5.5 V
Supply Current ICC
VCC = 3.3V, OUT_, RESET not asserted
(Note 3) 45 65 µA
VCC = 5V, OUT_, RESET not asserted 50 70
UVLO (Undervoltage Lockout) VUVLO VCC rising 1.62 1.8 1.98 V
IN_ (See Table 1)
Threshold Voltages (IN_ Falling) VTH
5V threshold, TOL = GND 4.50 4.625 4.75
V
5V threshold, TOL = VCC 4.25 4.375 4.50
3.3V threshold, TOL = GND 2.970 3.053 3.135
3.3V threshold, TOL = VCC 2.805 2.888 2.970
3.0V threshold, TOL = GND 2.70 2.775 2.85
3.0V threshold, TOL = VCC 2.55 2.625 2.70
2.5V threshold, TOL = GND 2.250 2.313 2.375
2.5V threshold, TOL = VCC 2.125 2.188 2.250
1.8V threshold, TOL = GND 1.62 1.665 1.71
1.8V threshold, TOL = VCC 1.53 1.575 1.62
1.5V threshold, TOL = GND 1.350 1.388 1.425
1.5V threshold, TOL = VCC 1.275 1.313 1.350
1.2V threshold, TOL = GND 1.08 1.11 1.14
1.2V threshold, TOL = VCC 1.02 1.05 1.08
0.9V threshold, TOL = GND 0.810 0.833 0.855
0.9V threshold, TOL = VCC 0.765 0.788 0.810
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
μP Supervisors
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Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VCC = 2.0V to 5.5V, TA = -40°C to +125°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Adjustable Threshold
(IN_ Falling) VTH
TOL = GND 0.388 0.394 0.400 V
TOL = VCC 0.366 0.372 0.378
IN_ Hysteresis VTH_HYS IN_ rising 0.5 % VTH
IN_ Input Current Fixed thresholds 3 16 µA
Adjustable thresholds -100 +100 nA
RESET
Reset Timeout tRP
SRT = VCC 140 200 280
msCSRT = 1500pF (Note 4) 2.43 3.09 3.92
CSRT = 100pF 0.206
CSRT = open 50 µs
SRT Ramp Current ISRT VSRT = 0V 460 600 740 nA
SRT Threshold 1.173 1.235 1.293 V
SRT Hysteresis 100 mV
IN_ to Reset Delay tRD IN_ falling 20 µs
RESET Output-Voltage Low VOL
VCC = 3.3V, ISINK = 10mA, RESET asserted 0.30
VVCC = 2.5V, ISINK = 6mA, RESET asserted 0.30
VCC = 1.2V, ISINK = 50µA, RESET asserted 0.30
RESET Output-Voltage High VOH VCC ≥ 2.0V, ISOURCE = 6µA, RESET
deasserted 0.8 x VCC V
MR Input-Voltage Low VIL 0.3 x VCC V
MR Input-Voltage High VIH 0.7 x VCC V
MR Minimum Pulse Width 1µs
MR Glitch Rejection 100 ns
MR to Reset Delay 200 ns
MR Pullup Resistance Pulled up to VCC 12 20 28 kΩ
OUTPUTS (OUT_ )
OUT_ Output-Voltage Low VOL
VCC = 3.3V, ISINK = 2mA 0.30 V
VCC = 2.5V, ISINK = 1.2mA 0.30
OUT_ Output-Voltage High VOH VCC R 2.0V, ISOURCE = 6µA 0.8 x VCC V
IN_ to OUT_ Propagation Delay tD(VTH + 100mV) to (VTH - 100mV) 20 µs
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
μP Supervisors
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Electrical Characteristics (continued)
(VCC = 2.0V to 5.5V, TA = -40°C to +125°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1)
Note 1: Devices are tested at TA = +25°C and guaranteed by design for TA = TMIN to TMAX.
Note 2: The outputs are guaranteed to be in the correct logic state down to VCC = 1V.
Note 3: Measured with WDI, MARGIN, and MR unconnected.
Note 4: The minimum and maximum specifications for this parameter are guaranteed by using the worst case of the SRT ramp cur-
rent and SRT threshold specifications.
Note 5: Guaranteed by design and not production tested.
Note 6: Amount of time required for logic to lock/unlock outputs from margin testing.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REFERENCE OUTPUT (MAX16005 Only)
Reference Short-Circuit Current Shorted to GND 0.8 mA
Reference Output Accuracy VREF No load 1.200 1.235 1.270 V
Line Regulation 0.005 % / V
Reference Load Regulation Sourcing, 0 ≤ IREF ≤ 40µA 10 Ω
WATCHDOG TIMER (MAX16001/MAX16002/MAX16004–MAX16007)
WDI Input-Voltage Low VIL 0.3 x VCC V
WDI Input-Voltage High VIH 0.7 x VCC V
WDI Pulse Width (Note 5) 50 ns
Watchdog Timeout Period tWDI 1.12 1.6 2.40 s
Watchdog Startup Period MAX16001/2/4/6/7 35 54 72 s
Watchdog Input Current VWDI = 0 to VCC (Note 5) -1 +1 µA
WDO Output-Voltage Low
(MAX16005 Only) VOL
VCC = 3.3V, ISINK = 2mA 0.30 V
VCC = 2.5V, ISINK = 1.2mA 0.30
WDO Output-Voltage High
(MAX16005 Only) VOH VCC ≥ 2.0V, ISOURCE = 6µA, WDO
deasserted 0.8 x VCC V
DIGITAL LOGIC
TOL Input-Voltage Low VIL 0.3 x VCC V
TOL Input-Voltage High VIH 0.7 x VCC V
TOL Input Current TOL = VCC 100 nA
MARGIN Input-Voltage Low VIL 0.3 x VCC V
MARGIN Input-Voltage High VIH 0.7 x VCC V
MARGIN Pullup Resistance Pulled up to VCC 12 20 28 kΩ
MARGIN Delay Time tMD Rising or falling (Note 6) 50 µs
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
μP Supervisors
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Electrical Characteristics (continued)
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
MAX16000 toc02
-40 -25 -10 5 20 35 50 65 80 95 110 125
30
35
40
45
50
55
60
WDI, MARGIN, AND MR UNCONNECTED
VCC = 2.5V
VCC = 3.3V
VCC = 5V
NORMALIZED THRESHOLD
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
NORMALIZED THRESHOLD
MAX16000 toc03
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.990
0.993
0.995
0.998
1.000
1.003
1.005
1.008
1.010
NORMALIZED THRESHOLD
vs. TEMPERATURE
TEMPERATURE (°C)
NORMALIZED THRESHOLD
MAX16000 toc04
-40 -25 -10 5 20 35 50 65 80 95 110 125
0.995
0.996
0.997
0.998
0.999
1.000
1.001
OUTPUT VOLTAGE vs. SINK CURRENT
SINK CURRENT (mA)
VOUT_ (mV)
MAX16000 toc05
012345678
0
25
50
75
100
OUT_ LOW
OUTPUT VOLTAGE vs. SOURCE CURRENT
SOURCE CURRENT (µA)
V
CC
- V
OUT_
(mV)
MAX16000 toc06
0 5 10 15 20 25 30
0
200
400
600
800
1000
OUT_ HIGH
1 10 100 1000
MAXIMUM TRANSIENT DURATION
vs. INPUT OVERDRIVE
MAX16000 toc07
INPUT OVERDRIVE (mV)
MAXIMUM TRANSIENT DURATION (s)
600
0
100
200
300
400
500
OUTPUT GOES LOW
ABOVE THIS LINE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
MAX16000 toc01
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
30
35
40
45
50
55
60
WDI, MARGIN, AND MR UNCONNECTED
RESET TIMEOUT PERIOD
vs. TEMPERATURE
TEMPERATURE (°C)
RESET TIMEOUT PERIOD (ms)
MAX16000 toc08
-40 -25 -10 5 20 35 50 65 80 95 110 125
190
191
192
193
194
195
196
197
198
RESET TIMEOUT DELAY
MAX16000 toc09
OUT1
2V/div
IN1
5V/div
40ms/div
RESET
2V/div
SRT = VCC
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
μP Supervisors
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Typical Operating Characteristics
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
TEMPERATURE (°C)
WATCHDOG TIMEOUT PERIOD (s)
MAX16000 toc11
-40 -25 -10 5 20 35 50 65 80 95 110 125
1.50
1.51
1.52
1.53
1.54
1.55
1.56
1.57
1.58
1.59
1.60
MARGIN ENABLE FUNCTION
MAX16000 toc12
OUT_
2V/div
MARGIN
2V/div
100µs/div
RESET
2V/div
OUT_ AND RESET ARE
BELOW RESPECTIVE
THRESHOLDS
MARGIN DISABLE FUNCTION
MAX16000 toc13
OUT_
2V/div
MARGIN
2V/div
100µs/div
RESET
2V/div
OUT_ AND RESET ARE BELOW RESPECTIVE
THRESHOLDS
REFERENCE VOLTAGE
vs. SOURCE CURRENT
SOURCE CURRENT (µA)
V
REF
(V)
MAX16000 toc14
0 100 200 300 400 500 600
1.220
1.225
1.230
1.235
1.240
1.245
1.250
1.255
1.260
MAX16005
REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
MAX16000 toc15
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
1.220
1.225
1.230
1.235
1.240
1.245
1.250
1.255
1.260
MAX16005
REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
MAX16000 toc16
-40 -25 -10 5 20 35 50 65 80 95 110 125
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
MAX16005
TRANSIENT DURATION
vs. VCC TRANSIENT MAGNITUDE
MAX16000 toc17
TRANSIENT MAGNITUDE (VCC - V) (mV)
MAXIMUM TRANSIENT DURATION (µs)
1
2
3
4
5
6
7
8
9
10
0
100 1000
RESET, OUT_ASSERT
ABOVE THIS LINE
1000
0.01 0.1 1 10 100 1000
100
10
1
0.1
0.01
RESET TIMEOUT PERIOD
vs. CSRT
MAX16000 toc10
CSRT (nF)
t
RP
(ms)
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
μP Supervisors
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Typical Operating Characteristics (continued)
PIN
NAME FUNCTION
MAX16000
MAX16001
MAX16002
1 1 1 IN3 Monitored Input Voltage 3. See Table 1 for the input voltage threshold.
2 2 2 IN4 Monitored Input Voltage 4. See Table 1 for the input voltage threshold.
3 4 4 GND Ground
4 5 5 VCC Unmonitored Power-Supply Input. Bypass VCC with a 0.1µF capacitor to ground. See Power
Supply Bypassing section for more detail.
5 6 — OUT3 Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the
voltage at IN3 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
6 7 — OUT4 Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the
voltage at IN4 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
7 10 8MARGIN Active-Low Manual Deassert Input. Pull MARGIN low to deassert all outputs (go into high state),
regardless of the voltage at any monitored input.
811 —OUT2 Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the
voltage at IN2 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
912 — OUT1 Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the
voltage at IN1 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
10 14 10 IN1 Monitored Input Voltage 1. See Table 1 for the input voltage threshold.
11 15 11 IN2 Monitored Input Voltage 2. See Table 1 for the input voltage threshold.
12 16 12 TOL Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL
to VCC to select 10% threshold tolerance.
— 3 3 WDI
Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period,
RESET is asserted. The timer clears whenever a reset is asserted or a rising or falling edge on
WDI is detected. The watchdog timer enters a startup period that allows 54s for the rst transition
to occur before a reset. Leave WDI unconnected to disable the watchdog timer. The WDI open-
state detector uses a small 400nA current. Therefore, do not connect WDI to anything that will
source or sink more than 200nA. Note that the leakage current specication for most three-state
drivers exceeds 200nA.
—86MR Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the
reset timeout period after MR is deasserted. MR is pulled up to VCC through a 20kΩ resistor.
—97SRT
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period.
The reset timeout period can be calculated as follows:
Reset Timeout (s) = 2.06 x 106 (Ω) x CSRT (F). For the internal timeout period of 140ms (min),
connect SRT to VCC.
— 13 9RESET
Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below
its respective threshold or MR is asserted. RESET remains asserted for the reset timeout period
after all monitored voltages exceed their respective thresholds and MR is deasserted. This open-
drain output has a 30µA internal pullup.
— — — EP
Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide
a low thermal resistance path from the IC junction to the PCB. Do not use as the electrical
connection to GND.
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
μP Supervisors
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Pin Description (MAX16000/MAX16001/MAX16002)
PIN
NAME FUNCTION
MAX16003
MAX16004
MAX16005
TSSOP
MAX16005
TQFN
1 1 3 1 IN4 Monitored Input Voltage 4. See Table 1 for the input voltage threshold.
2 2 4 2 IN5 Monitored Input Voltage 5. See Table 1 for the input voltage threshold.
3 3 5 3 IN6 Monitored Input Voltage 6. See Table 1 for the input voltage threshold.
4 5 7 5 GND Ground
5 6 86VCC Unmonitored Power-Supply Input. Bypass VCC with a 0.1µF capacitor to ground. See
Power Supply Bypassing section for more detail.
6 7 — — OUT4
Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low
until the voltage at IN4 exceeds its threshold. The open-drain output has a 30µA internal
pullup to VCC.
78— — OUT5
Output 5. When the voltage at IN5 falls below its threshold, OUT5 goes low and stays low
until the voltage at IN5 exceeds its threshold. The open-drain output has a 30µA internal
pullup to VCC.
8 9 — — OUT6
Output 6. When the voltage at IN6 falls below its threshold, OUT6 goes low and stays low
until the voltage at IN6 exceeds its threshold. The open-drain output has a 30µA internal
pullup to VCC.
912 13 11 MARGIN Manual Deassert Input. Pull MARGIN low to deassert all outputs (go into high state),
regardless of the voltage at any monitored input.
10 13 — — OUT3
Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low
until the voltage at IN3 exceeds its threshold. The open-drain output has a 30µA internal
pullup to VCC.
11 14 — — OUT2
Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low
until the voltage at IN2 exceeds its threshold. The open-drain output has a 30µA internal
pullup to VCC.
12 15 — — OUT1
Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low
until the voltage at IN1 exceeds its threshold. The open-drain output has a 30µA internal
pullup to VCC.
13 17 15 13 IN1 Monitored Input Voltage 1. See Table 1 for the input voltage threshold.
14 18 16 14 IN2 Monitored Input Voltage 2. See Table 1 for the input voltage threshold.
15 19 1 15 IN3 Monitored Input Voltage 3. See Table 1 for the input voltage threshold.
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
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Pin Description (MAX16003/MAX16004/MAX16005)
PIN
NAME FUNCTION
MAX16003
MAX16004
MAX16005
TSSOP
MAX16005
TQFN
16 20 2 16 TOL Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance.
Connect TOL to VCC to select 10% threshold tolerance.
— 4 6 4 WDI
Watchdog Timer Input.
MAX16004: If WDI remains low or high for longer than the watchdog timeout period,
RESET is asserted and the timer is cleared. The timer also clears whenever a reset is
asserted or a rising or falling edge on WDI is detected. The watchdog timer enters a
startup period that allows 54s for the rst transition to occur before a reset. Leave WDI
unconnected to disable the watchdog timer.
MAX16005: If WDI remains low or high for longer than the watchdog timeout period,
WDO is asserted. The timer clears whenever a rising or falling edge on WDI is detected.
Leave WDI unconnected to disable the watchdog timer. The MAX16005 does not have a
startup period.
MAX16004/MAX16005: The WDI open-state detector uses a small 100nA current.
Therefore, do not connect WDI to anything that will source or sink more than 50nA. Note
that the leakage current specication for most three-state drivers exceeds 50nA.
— 10 11 9MR
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low
for the reset timeout period after MR is deasserted. MR is pulled up to VCC through a
20kΩ resistor.
—11 12 10 SRT
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout
period. The reset timeout period can be calculated as follows:
Reset Timeout (s) = 2.06 x 106 (Ω) x CSRT (F). For the internal timeout period of 140ms
(min), connect SRT to VCC.
— 16 14 12 RESET
Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls
below its respective threshold or MR is asserted. RESET remains asserted for the reset
timeout period after all monitored voltages exceed their respective thresholds and MR is
deasserted. This open-drain output has a 30µA internal pullup.
— — 97REF Reference Output. The reference output voltage of 1.23V can source up to 40µA.
— — 10 8WDO
Active-Low Watchdog Output. WDO asserts and stays low whenever any of the IN_
inputs fall below their respective thresholds. WDO deasserts without a timeout delay
when all the IN_ inputs rise above their thresholds. When all the IN_ inputs rise above
their thresholds, WDO asserts low whenever the watchdog timer times out. WDO
deasserts after a valid WDI transition or if MR is pulled low. The watchdog timer begins
counting after the reset timeout period once MR goes high. Pull MARGIN low to deassert
WDO.
— — — — EP
Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to
provide a low thermal resistance path from the IC junction to the PCB. Do not use as the
electrical connection to GND.
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
μP Supervisors
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Pin Description (MAX16003/MAX16004/MAX16005) (continued)
PIN
NAME FUNCTION
MAX16006
MAX16007
1 1 IN5 Monitored Input Voltage 5. See Table 1 for the input voltage threshold.
2 2 IN6 Monitored Input Voltage 6. See Table 1 for the input voltage threshold.
3 3 IN7 Monitored Input Voltage 7. See Table 1 for the input voltage threshold.
4 4 IN8 Monitored Input Voltage 8. See Table 1 for the input voltage threshold.
5 5 WDI
Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period,
RESET is asserted and the timer is cleared. The timer also clears whenever a reset is asserted or a
rising or falling edge on WDI is detected. The watchdog timer enters a startup period that allows 54s
for the rst transition to occur before a reset. Leave WDI unconnected to disable the watchdog timer.
The WDI open-state detector uses a small 400nA current. Therefore, do not connect WDI to anything
that will source or sink more than 200nA. Note that the leakage current specication for most three-
state drivers exceeds 200nA.
6 6 GND Ground
7 7 VCC Unmonitored Power-Supply Input. Bypass VCC with a 0.1µF capacitor to ground. See Power Supply
Bypassing section for more detail.
8—OUT5 Output 5. When the voltage at IN5 falls below its threshold, OUT5 goes low and stays low until the
voltage at IN5 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
9—OUT6 Output 6. When the voltage at IN6 falls below its threshold, OUT6 goes low and stays low until the
voltage at IN6 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
10 — OUT7 Output 7. When the voltage at IN7 falls below its threshold, OUT7 goes low and stays low until the
voltage at IN7 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
11 —OUT8 Output 8. When the voltage at IN8 falls below its threshold, OUT8 goes low and stays low until the
voltage at IN8 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
12 10 MR Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset
timeout period after MR is deasserted. MR is pulled up to VCC through a 20kΩ resistor.
13 11 SRT
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The
reset timeout period can be calculated as follows:
Reset Timeout (s) = 2.06 x 106 (Ω) x CSRT (F). For the internal timeout period of 140ms (min),
connect SRT to VCC.
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
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Pin Description (MAX16006/MAX16007)
PIN
NAME FUNCTION
MAX16006
MAX16007
14 12 MARGIN Margin Disable Input. Pull MARGIN low to deassert all outputs (go into high state), regardless of the
voltage at any monitored input.
15 — OUT4 Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the
voltage at IN4 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
16 — OUT3 Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the
voltage at IN3 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
17 — OUT2 Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the
voltage at IN2 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
18 —OUT1 Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the
voltage at IN1 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.
19 15 RESET
Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its
respective threshold or MR is asserted. RESET remains asserted for the reset timeout period after all
monitored voltages exceed their respective thresholds and MR is deasserted. This open-drain output
has a 30µA internal pullup.
20 16 IN1 Monitored Input Voltage 1. See Table 1 for the input voltage threshold.
21 17 IN2 Monitored Input Voltage 2. See Table 1 for the input voltage threshold.
22 18 IN3 Monitored Input Voltage 3. See Table 1 for the input voltage threshold.
23 19 IN4 Monitored Input Voltage 4. See Table 1 for the input voltage threshold.
24 20 TOL Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to
VCC to select 10% threshold tolerance.
—8, 9,
13, 14 N.C. Not Internally Connected
— — EP Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low thermal
resistance path from the IC junction to the PCB. Do not use as the electrical connection to GND.
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
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Pin Description (MAX16006/MAX16007) (continued)
Table 1. Input-Voltage-Threshold Selector
Note: Other fixed thresholds may be available. Contact factory for availability.
PART IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8
MAX16000A 3.3 2.5 ADJ 1.8 ————
MAX16000B 3.3 ADJ ADJ 1.8 ————
MAX16000C ADJ 2.5 ADJ 1.8 ————
MAX16000D 3.3 2.5 ADJ ADJ ————
MAX16000E ADJ ADJ ADJ ADJ ————
MAX16001A 3.3 2.5 ADJ 1.8 ————
MAX16001B 3.3 ADJ ADJ 1.8 ————
MAX16001C ADJ 2.5 ADJ 1.8 ————
MAX16001D 3.3 2.5 ADJ ADJ ————
MAX16001E ADJ ADJ ADJ ADJ ————
MAX16002A 3.3 2.5 ADJ 1.8 ————
MAX16002B 3.3 ADJ ADJ 1.8 ————
MAX16002C ADJ 2.5 ADJ 1.8 ————
MAX16002D 3.3 2.5 ADJ ADJ ————
MAX16002E ADJ ADJ ADJ ADJ ————
MAX16003A 3.3 2.5 ADJ 1.8 ADJ ADJ — —
MAX16003B 3.3 ADJ ADJ 1.8 ADJ ADJ — —
MAX16003C 3.3 2.5 ADJ ADJ ADJ ADJ — —
MAX16003D ADJ 2.5 ADJ 1.8 ADJ ADJ — —
MAX16003E ADJ ADJ ADJ ADJ ADJ ADJ — —
MAX16004A 3.3 2.5 ADJ 1.8 ADJ ADJ — —
MAX16004B 3.3 ADJ ADJ 1.8 ADJ ADJ — —
MAX16004C 3.3 2.5 ADJ ADJ ADJ ADJ — —
MAX16004D ADJ 2.5 ADJ 1.8 ADJ ADJ — —
MAX16004E ADJ ADJ ADJ ADJ ADJ ADJ — —
MAX16005A 3.3 2.5 ADJ 1.8 ADJ ADJ — —
MAX16005B 3.3 ADJ ADJ 1.8 ADJ ADJ — —
MAX16005C 3.3 2.5 ADJ ADJ ADJ ADJ — —
MAX16005D ADJ 2.5 ADJ 1.8 ADJ ADJ — —
MAX16005E ADJ ADJ ADJ ADJ ADJ ADJ — —
MAX16006A 3.3 2.5 ADJ 1.8 ADJ ADJ ADJ ADJ
MAX16006B 3.3 ADJ ADJ 1.8 ADJ ADJ ADJ ADJ
MAX16006C 3.3 2.5 ADJ ADJ ADJ ADJ ADJ ADJ
MAX16006D ADJ 2.5 ADJ 1.8 ADJ ADJ ADJ ADJ
MAX16006E ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ
MAX16006F 5.0 3.3 3.0 2.5 1.8 1.5 1.2 0.9
MAX16007A 3.3 2.5 ADJ 1.8 ADJ ADJ ADJ ADJ
MAX16007B 3.3 ADJ ADJ 1.8 ADJ ADJ ADJ ADJ
MAX16007C 3.3 2.5 ADJ ADJ ADJ ADJ ADJ ADJ
MAX16007D ADJ 2.5 ADJ 1.8 ADJ ADJ ADJ ADJ
MAX16007E ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
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Figure 1. MAX16000D Functional Diagram
MAX16000
REFERENCE
UNDERVOLTAGE LOCKOUT
VCC
IN1
OUT1
OUT2
OUT3
OUT4
MARGIN
IN2
IN3
IN4
TOL
VCC
RESET
CIRCUIT
OUTPUT
DRIVER
EN
VCC
VCC
VCC
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
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Functional Diagrams
Figure 2. MAX16001D/MAX16002D Functional Diagram
MAX16001/
MAX16002
REFERENCE
UNDERVOLTAGE LOCKOUT
VCC
IN1
(OUT1)
RESET
(OUT2)
(OUT3)
(OUT4)
MARGIN
IN2
IN3
IN4
TOL
VCC
RESET CIRCUIT
WATCHDOG
TIMER CIRCUIT
OUTPUT
DRIVER
EN
MR SRTWDI
TIMING
VCC
VCC
VCC
( ) MAX16001 ONLY
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Functional Diagrams (continued)
Figure 3. MAX16003C/MAX16004C Functional Diagram
MAX16003/
MAX16004
REFERENCE
UNDERVOLTAGE LOCKOUT
VCC
IN1
OUT1
(RESET)
OUT2
OUT3
OUT6
MARGIN
( ) MAX16004 ONLY
IN2
IN3
IN4
TOL
VCC
RESET CIRCUIT
WATCHDOG
TIMER CIRCUIT
OUTPUT
DRIVER
EN
(MR) (SRT)(WDI)
TIMING
VCC
VCC
VCC
IN5
IN6
OUT4
OUT5
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
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Functional Diagrams (continued)
Figure 4. MAX16005C Functional Diagram
MAX16005
REFERENCE
UNDERVOLTAGE LOCKOUT
VCC
IN1
RESET
MARGINREF
IN2
IN3
IN4
TOL
VCC
RESET CIRCUIT
WATCHDOG
TIMER CIRCUIT
OUTPUT
DRIVER
EN
MR SRTWDIWDO
TIMING
VCC
VCC
VCC
IN5
IN6
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Functional Diagrams (continued)
Figure 5. MAX16006C/MAX16007C Functional Diagram
MAX16006/
MAX16007
REFERENCE
UNDERVOLTAGE LOCKOUT
VCC
IN1
MARGIN
( ) MAX16006 ONLY
IN2
IN3
IN4
TOL
VCC
RESET CIRCUIT
WATCHDOG
TIMER CIRCUIT
OUTPUT
DRIVER
EN
MR SRTWDI
TIMING
VCC
VCC
IN5
IN6
IN7
IN8
(OUT1)
RESET
(OUT2)
(OUT3)
OUT8
VCC
(OUT4)
(OUT5)
(OUT6)
(OUT7)
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
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Functional Diagrams (continued)
Detailed Description
The MAX16000–MAX16007 are low-voltage, quad/hex/
octal-voltage μP supervisors in small TQFN and TSSOP
packages. These devices provide supervisory functions
for complex multivoltage systems. The MAX16000/
MAX16001/MAX16002 monitor four voltages, the
MAX16003/MAX16004/MAX16005 monitor six voltages,
and the MAX16006/MAX16007 monitor eight voltages.
The MAX16000/MAX16001/MAX16003/MAX16004/
MAX16006 offer independent outputs for each
monitored voltage. The MAX16001/MAX16002/
MAX16004– MAX16007 offer a reset output that asserts
whenever any of the monitored voltages fall below their
respective thresholds or the manual reset input is asserted.
The reset output remains asserted for the reset timeout
after all voltages are above their respective thresholds
and the manual reset input is deasserted. The minimum
reset timeout is internally set to 140ms or can be adjusted
with an external capacitor.
All open-drain outputs have internal 30μA pullups that
eliminate the need for external pullup resistors. However,
each output can be driven with an external voltage up to
5.5V. Other features offered include a manual reset input,
a tolerance pin for selecting 5% or 10% input thresholds,
and a margin enable function for deasserting the outputs
during margin testing.
The MAX16001/MAX16002/MAX16004–MAX16007 offer
a watchdog timer that asserts RESET or an independent
watchdog output (MAX16005) when the watchdog timeout
period (1.6s typ) is exceeded. The watchdog timer can be
disabled by leaving input open.
Applications Information
Undervoltage-Detection Circuit
The open-drain outputs of the MAX16000–MAX16007 can
be configured to detect an undervoltage condition. Figure
6 shows a configuration where an LED turns on when
the comparator output is low, indicating an undervoltage
condition. These devices can also be used in applications
such as system supervisory monitoring, multivoltage level
detection, and VCC bar-graph monitoring (Figure 7).
Tolerance (TOL)
The MAX16000–MAX16007 feature a pin-selectable
threshold tolerance. Connect TOL to GND to select 5%
threshold tolerance. Connect TOL to VCC to select 10%
threshold tolerance.
Window Detection
A window detector circuit uses two auxiliary inputs in the
configuration shown in Figure 8. External resistors set
the two threshold voltages of the window detector circuit.
External logic gates create the OUT signal. The window
detection width is the difference between the threshold
voltages (Figure 9).
Figure 6. Quad Undervoltage Detector with LED Indicators
Figure 7. VCC Bar-Graph Monitoring
MAX16000
MAX16001
GND
VCC
IN1V1
5V
V2
V3
V4 OUT1
IN2
IN3
IN4
OUT2
OUT3
OUT4
MAX16000
MAX16001
GND
D2
VCC
IN1
VIN(5V)
5V
OUT1
IN2
IN3
IN4
OUT2
OUT3
OUT4
D1
D3
D4
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Adjustable Input
These devices offer several monitor options with adjustable
input thresholds (see Table 1). The threshold voltage at
each adjustable IN_ input is typically 0.394V (TOL = GND)
or 0.372 (TOL = VCC). To monitor a voltage VINTH,
connect a resistive-divider network to the circuit as shown
in Figure 10.
VINTH = VTH ((R1 / R2) + 1)
R1 = R2 ((VINTH / VTH) - 1)
Large resistors can be used to minimize current through
the external resistors. For greater accuracy, use lower-
value resistors.
Unused Inputs
Connect any unused IN_ inputs to a voltage above its
threshold.
OUT_ Outputs
(MAX16000/MAX16001/MAX16003/
MAX16004/MAX16006)
The OUT_ outputs go low when their respective IN_
inputs drop below their specified thresholds. The output
is open drain with a 30μA internal pullup to VCC. For
many applications, no external pullup resistor is required
to interface with other logic devices. An external pullup
resistor to any voltage from 0 to 5.5V overrides the
internal pullup if interfacing to different logic supply
voltages. Internal circuitry prevents reverse current flow
from the external pullup voltage to VCC (Figure 11).
Figure 8. Window Detection
Figure 10. Setting the Adjustable Input
Figure 9. Output Response of Window Detector Circuit
MAX16000
MAX16001
GND
VCC
IN1
5V
R2
INPUT
R1
OUT1
IN2
IN3
OUT
IN4
OUT2
OUT3
OUT4
R4
R3
VTH1 = (1 + R1) (VTH + VTH_HYS)
R2
VTH4 = (1 + R3) VTH
R4
R1
VINTH
VTH
R2
R1 = R2(VINTH )
VTH
- 1
V TH
V TH4
V TH1
OUT
OUT4
OUT1
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RESET Output (MAX16001/MAX16002/
MAX16004–MAX16007)
RESET asserts low when any of the monitored voltages
fall below their respective thresholds or MR is asserted.
RESET remains asserted for the reset timeout period
after all monitored voltages exceed their respective
thresholds and MR is deasserted (see Figure 12). This
open-drain output has a 30μA internal pullup. An external
pullup resistor to any voltage from 0 to 5.5V overrides the
internal pullup if interfacing to different logic supply
voltages. Internal circuitry prevents reverse current flow
from the external pullup voltage to VCC (Figure 11).
WDO (MAX16005 Only)
WDO asserts and stays low whenever any of the IN_
inputs fall below their respective thresholds. WDO deasserts
without a timeout delay when all the IN_inputs rise above
their thresholds. When all the IN_ inputs rise above their
thresholds, WDO asserts low whenever the watchdog
timer times out. WDO deasserts after a valid WDI transition
or if MR is pulled low. The watchdog timer begins counting
after the reset timeout period once MR goes high. Pull
MARGIN low to deassert WDO regardless of any other
condition. The watchdog timer continues to run when
MARGIN is low and if a timeout occurs. WDO will assert
MR after MARGIN is deasserted. This open-drain output
has a 30μA internal pullup. An external pullup resistor to
any voltage from 0 to 5.5V overrides the internal pullup
if interfacing to different logic supply voltages. Internal
circuitry prevents reverse current flow from the external
pullup voltage to VCC (Figure 11).
Figure 11. Interfacing to a Different Logic Supply Voltage Figure 12. Output Timing Diagram
MAX16001/
MAX16002/
MAX16004–MAX16007
GND
VCC
GND
RESET
VCC
5V
OUT_
VCC = 3.3V
100kΩ
IN_
10%
90%
10%
90%
RESET
OUT_
VTH_
tRP
tD
tD
tRD
VTH_
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Figure 13. WDO Timing Related to VTH and tRP
Figure 14. Margin Output Disable (MARGIN) Affect on RESET within tRP
RESET
WDO
WDI
t
RP
t<t
WD
t<t
WD
t<t
WD
t
WD
t
RP
V
TH
V
TH
+
V
TH_HYST
V
TH
+
V
TH_HYST
V
IN
MARGIN
RESET
INTERNAL
RESET
SIGNAL
t
RP
t
RP
t
WD
V
TH
V
TH
+
V
TH_HYST
V
TH
+
V
TH_HYST
V
IN
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Reset Timeout Capacitor
The reset timeout period can be adjusted to accommodate
a variety of μP applications from 50μs to 1.12s. Adjust
the reset timeout period (tRP) by connecting a capacitor
(CSRT) between SRT and GND. Calculate the reset timeout
capacitor as follows:
SRT
RP
SRT TH_SRT
t (s) x I
C (F) V
=
Connect SRT to VCC for a factory-programmed reset
timeout of 140ms (min).
Manual Reset Input (MR)
(MAX16001/MAX16002/
MAX16004–MAX16007)
Many μP-based products require manual reset capability,
allowing the operator, a test technician, or external logic
circuitry to initiate a reset. A logic-low on MR asserts
RESET low. RESET remains asserted while MR is low,
and during the reset timeout period (140ms min) after MR
returns high. The MR input has an internal 20kΩ pullup
resistor to VCC, so it can be left unconnected if not used.
MR can be driven with TTL or CMOS-logic levels, or with
open-drain/collector outputs. Connect a normally open
momentary switch from MR to GND to create a manual
reset function. External debounce circuitry is not required.
If MR is driven from long cables or if the device is used in
a noisy environment, connecting a 0.1μF capacitor from
MR to GND provides additional noise immunity.
Margin Output Disable (MARGIN)
MARGIN allows system-level testing while power supplies
are adjusted from their nominal voltages. Drive MARGIN
low to force RESET, WDO, and OUT_ high, regardless
of the voltage at any monitored input. The state of each
output does not change while MARGIN = GND. The
watchdog timer continues to run when MARGIN is low,
and if a timeout occurs, WDO/RESET will assert tMD after
MARGIN is deasserted.
The MARGIN input is internally pulled up to VCC. Leave
MARGIN unconnected or connect to VCC if unused.
Power-Supply Bypassing
The MAX16000–MAX16007 operate from a 2.0V to 5.5V
supply. An undervoltage lockout ensures that the outputs
are in the correct states when the UVLO is exceeded. In
noisy applications, bypass VCC to ground with a 0.1μF
capacitor as close to the device as possible. The additional
capacitor improves transient immunity. For VCC transients
with high slew rates, place an RC lowpass filter in front of
VCC, where R can be up to 100Ω.
Figure 15. Margin Output Disable (MARGIN) Affect on RESET Outside tRP
MARGIN
RESET
INTERNAL
RESET
SIGNAL
tRP tRP
VTH
VTH + VTH_HYST
VTH + VTH_HYST
VIN
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
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12
11
10
4
5
IN4
GND
6
IN3
OUT2
MARGIN
OUT1
1 2
IN2
3
9 8 7
TOL +
+
OUT4
OUT3
VCC
MAX16000
IN1
TQFN
(4mm x 4mm)
TOP VIEW
12
11
10
4
5
IN4
WDI
6
IN3
SRT
MARGIN
RESET
1 2
IN2
3
9 8 7
TOL +
MR
GND
VCC
MAX16002
IN1
TQFN
(4mm x 4mm)
TOP VIEW
15
16
14
13
6
5
7
IN4
GND
8
IN3
OUT2
SRT
OUT1
1 2
IN1
4
12 11 9
IN2
TOL
MR
OUT4
OUT3
VCC
MAX16001
WDI MARGIN
3
10
RESET
TQFN
(4mm x 4mm)
TOP VIEW
+
15
16
14
13
6
5
7
IN5
GND
8
IN4
OUT2
OUT1
1 2
IN2
4
12 11 9
IN3
TOL
OUT5
OUT4
VCC
MAX16003
IN6
MARGIN
3
10
IN1 OUT6
TQFN
(4mm x 4mm)
TOP VIEW
OUT3
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Pin Congurations
+
+ +
15
16
14
13
6
5
7
IN5
WDI
8
IN4
MARGIN
MR
RESET
1 2
IN2
4
12 11 9
IN3
TOL
WDO
REF
VCC
GND
MAX16005
IN6 SRT
3
10
IN1
TQFN
(4mm x 4mm)
TOP VIEW
19
20
18
17
7
6
8
IN5
WDI
GND
9
IN4
OUT2
MARGIN
SRT
OUT1
1 2
IN2
4 5
15 14 12 11
IN3
TOL
OUT6
OUT5
OUT4
VCC
MAX16004
IN6 OUT3
3
13
IN1
16 10 MR
RESET
TQFN
(4mm x 4mm)
TOP VIEW
MARGIN
SRT
+
19
20
18
17
7
6
8
IN6
IN8
WDI
9
IN5
N.C.
MARGIN
SRT
RESET
1 2
IN3
4 5
15 14 12 11
IN4
TOL
N.C.
N.C.
VCC
GND
MAX16007
IN7 N.C.
3
13
IN2
16 10 MR
IN1
TQFN
(4mm x 4mm)
TOP VIEW
23
24
22
21
8
7
9
IN6
IN8
WDI
GND
10
IN5
1 2
IN3
4 5 6
1718 16 14 13
IN4
TOL
OUT7
OUT6
OUT5
VCC
MAX16006
IN7
3
15
IN2
20 11 OUT8
IN1
19 12 MR
RESET
TQFN
(4mm x 4mm)
TOP VIEW
OUT2
OUT1
OUT3
OUT4
16
15
14
13
12
11
10
1
2
3
4
5
6
7
IN2
IN1
RESET
MARGININ5
IN4
TOL
IN3
TOP VIEW
MAX16005
SRT
MR
WDOGND
WDI
98 REFVCC
IN6
TSSOP
+
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Pin Congurations (continued)
Note: The “_” is a placeholder for the input voltage threshold.
See Table 1
+Denotes a lead(Pb)-free/RoHS-compliant package.
For tape-and-reel, add a “T” after the “+.” Tape-and-reel are
offered in 2.5k increments.
*EP = Exposed pad.
/V denotes an automotive qualified part.
PART TEMP RANGE PIN-PACKAGE
MAX16001_TE+ -40°C to +125°C 16 TQFN-EP*
MAX16001_TE/V -40°C to +125°C 16 TQFN-EP*
MAX16002_TC+ -40°C to +125°C 12 TQFN-EP*
MAX16003_TE+ -40°C to +125°C 16 TQFN-EP*
MAX16004_TP+ -40°C to +125°C 20 TQFN-EP*
MAX16005_TE+ -40°C to +125°C 16 TQFN-EP*
MAX16005_UE+ -40°C to +125°C 16 TSSOP
MAX16006_TG+ -40°C to +125°C 24 TQFN-EP*
MAX16007_TP+ -40°C to +125°C 20 TQFN-EP*
PART MONITORED
VOLTAGES
INDEPENDENT
OUTPUTS RESET WDI/WDO MR
ADJUSTABLE
RESET
TIMEOUT
MAX16000 4 4 — — — —
MAX16001 4 4 üWDI ü ü
MAX16002 4 — üWDI ü ü
MAX16003 6 6 — — — —
MAX16004 6 6 üWDI ü ü
MAX16005 6 — üWDI/WDO ü ü
MAX16006 8 8 üWDI ü ü
MAX16007 8—üWDI ü ü
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
12 TQFN-EP T1244+4 21-0139 90-0068
16 TSSOP U16+2 21-0066 90-0117
16 TQFN-EP T1644+4 21-0139 90-0070
20 TQFN-EP T2044+3 21-0139 90-0037
24 TQFN-EP T2444+4 21-0139 90-0022
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
μP Supervisors
www.maximintegrated.com Maxim Integrated
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25
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Ordering Information (continued)
Selector Guide
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 12/05 Initial release —
1 1/06 Released MAX16003 and MAX16004. 20, 21
2 7/06 Released MAX16005. Updated Pin Description and Detailed Description. 1, 4, 7, 9, 10, 20, 21
312/08 Added the MAX16005 TSSOP package. Modied the Detailed Description,
and added Figures 13, 14, and 15.
1, 2, 7, 8, 9, 10,
20–26
48/10 Revised the Absolute Maximum Ratings and the Power-Supply Bypassing
sections. 2, 22
5 10/10 Added new graph to the Typical Operating Characteristics.6
69/12 Added automotive qualied part to Ordering Information.25
7 4/16 Updated Pin Conguration table 7, 8, 10
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
MAX16000–MAX16007 Low-Voltage, Quad/Hex/Octal-Voltage
μP Supervisors
© 2016 Maxim Integrated Products, Inc.
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26
Revision History
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MAX16005ATE+ MAX16007ATP+ MAX16000ATC+ MAX16000ATC+T MAX16000BTC+ MAX16000BTC+T
MAX16000CTC+ MAX16000CTC+T MAX16000DTC+ MAX16000DTC+T MAX16000ETC+ MAX16000ETC+T
MAX16001ATE+ MAX16001ATE+T MAX16001BTE+ MAX16001BTE+T MAX16001CTE+ MAX16001CTE+T
MAX16001DTE+ MAX16001DTE+T MAX16001ETE+ MAX16001ETE+T MAX16002ATC+ MAX16002ATC+T
MAX16002BTC+ MAX16002BTC+T MAX16002CTC+ MAX16002CTC+T MAX16002DTC+ MAX16002DTC+T
MAX16002ETC+ MAX16002ETC+T MAX16003ATE+ MAX16003ATE+T MAX16003BTE+ MAX16003BTE+T
MAX16003CTE+ MAX16003CTE+T MAX16003DTE+ MAX16003DTE+T MAX16003ETE+ MAX16003ETE+T
MAX16004ATP+ MAX16004ATP+T MAX16004BTP+ MAX16004BTP+T MAX16004CTP+ MAX16004CTP+T
MAX16004DTP+ MAX16004DTP+T MAX16004ETP+ MAX16004ETP+T MAX16005ATE+T MAX16005BTE+
MAX16005BTE+T MAX16005CTE+ MAX16005CTE+T MAX16005DTE+ MAX16005DTE+T MAX16005ETE+
MAX16005ETE+T MAX16006ATG+ MAX16006ATG+T MAX16006BTG+ MAX16006BTG+T MAX16006CTG+
MAX16006CTG+T MAX16006DTG+ MAX16006DTG+T MAX16006ETG+ MAX16006ETG+T MAX16006FTG+
MAX16006FTG+T MAX16007ATP+T MAX16007BTP+ MAX16007BTP+T MAX16007CTP+ MAX16007CTP+T
MAX16007DTP+ MAX16007DTP+T MAX16007ETP+ MAX16007ETP+T