550BA1417M000DGR - Silicon Labs

VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)

10 MHZ TO 1.4 GHZ

Features

Applications

Description

The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL

circuitry to

provide a low-jitter clock at high frequencies. The Si550 is available with

any-rate output frequency from 10 to 945 MHz and selected frequencies to

1400 MHz. Unlike traditional VCXOs, where a different crystal is required for

each output frequency, the Si550 uses one fixed crystal to provide a wide

range of output frequencies. This IC-based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In

addition, DSPLL clock synthesis provides superior supply noise rejection,

simplifying the task of generating low-jitter clocks in noisy environments

typically found in communication systems. The Si550 IC-based VCXO is

factory-configurable for a wide variety of user specifications, including

frequency, supply voltage, output format, tuning slope, and temperature

stability. Specific configurations are factory programmed at time of shipment,

thereby eliminating the long lead times associated with custom oscillators.

Functional Block Diagram

Available with any-rate output

frequencies from 10 to 945 MHz

and selected frequencies to

1.4 GHz

3rd generation DSPLL® with

superior jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Lead-free/RoHS-compliant

SONET/SDH

xDSL

10 GbE LAN/WAN

Low-jitter clock generation

Optical modules

Clock and data recovery

Fixed

Frequency

Any-rate

10-1400 MHz

DSPLL®

Clock Synthesis

ADC

VDD CLK+CLK–

Vc OE GND

Ordering Information:

See page 8.

Pin Assignments:

See page 7.

(Top View)

Si5602

GND

VDD

CLK+

CLK–

Si550

REVISION D

Si550

2 Rev. 0.6

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Units

Supply Voltage1VDD 3.3 V option 2.97 3.3 3.63

V2.5 V option 2.25 2.5 2.75

1.8 V option 1.71 1.8 1.89

Supply Current IDD Output enabled

LVPECL

CML

LVDS

CMOS

—

120

108

130

117

108

tristate mode — 60 75

Output Enable (OE)2VIH 0.75 x VDD ——

VIL ——0.5

Operating Temperature Range TA–40 — 85 °C

Notes:

1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 8 for further details.

2. OE pin includes a 17 kΩ resistor to VDD.

Table 2. VC Control Voltage Input

Parameter Symbol Test Condition Min Typ Max Units

Control Voltage Tuning Slope1,2,3 KV10 to 90% of VDD —33

135

180

356

— ppm/V

Control Voltage Linearity4LVC BSL –5 ±1 +5 %

Incremental –10 ±5 +10

Modulation Bandwidth BW 9.3 10.0 10.7 kHz

VC Input Impedance ZVC 500 — — kΩ

Nominal Control Voltage VCNOM @ fO—V

DD/2 — V

Control Voltage Tuning Range VC0V

DD V

Notes:

1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 8.

2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.

3. KV variation is ±10% of typical values.

4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope

determined with VC ranging from 10 to 90% of VDD.

Si550

Rev. 0.6 3

Table 3. CLK± Output Frequency Characteristics

Parameter Symbol Test Condition Min Typ Max Units

Nominal Frequency1,2,3 fOLVDS/CML/LVPECL 10 — 945 MHz

CMOS 10 — 160

Temperature Stability1,4 TA= –40 to +85 ºC –20

–50

–100

—

+20

+50

+100

ppm

Absolute Pull Range1,4 APR ±25 — ±375 ppm

Aging Frequency drift over first year. — — ±3 ppm

Frequency drift over 15 year life. — — ±10

Power up Time5tOSC ——10ms

Notes:

1. See Section 3. "Ordering Information" on page 8 for further details.

2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.

3. Nominal output frequency set by VCNOM =V

DD/2.

4. Selectable parameter specified by part number.

5. Time from power up or tristate mode to fO.

Table 4. CLK± Output Levels and Symmetry

Parameter Symbol Test Condition Min Typ Max Units

LVPECL Output Option1VOmid-level VDD – 1.42 — VDD – 1.25 V

VOD swing (diff) 1.1 —1.9 VPP

VSE swing (single-ended) 0.55 —0.95 VPP

LVDS Output Option2VOmid-level 1.125 1.20 1.275 V

VOD swing (diff) 0.5 0.7 0.9 VPP

CML Output Option2VOmid-level — VDD – 0.75 — V

VOD swing (diff) 0.70 0.95 1.20 VPP

CMOS Output Option3VOH IOH =32mA 0.8 x VDD —VDD V

VOL IOL =32mA — — 0.4

Rise/Fall time (20/80%) tR, tFLVPECL/LVDS/CML — — 350 ps

CMOS with CL=15pF — 1 — ns

Symmetry (duty cycle) SYM LVPECL: VDD – 1.3 V (diff)

LVDS: 1.25 V (diff)

CMOS: VDD/2

45 — 55 %

Notes:

1. 50 Ω to VDD – 2.0 V.

2. Rterm = 100 Ω (differential).

3. CL = 15 pF

Si550

4 Rev. 0.6

Table 5. CLK± Output Phase Jitter

Parameter Symbol Test Condition Min Typ Max Units

Phase Jitter (RMS)1,2,3

for FOUT > 500 MHz

φJKv = 33 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.26

—

Kv = 45 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.27

0.26

—

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.32

0.26

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.40

0.27

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.49

0.28

—

Kv = 356 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.87

0.33

—

Notes:

1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.

2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.

3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply

rejection (PSR) advantage of Si55x versus SAW-based solutions.

Si550

Rev. 0.6 5

Phase Jitter (RMS)1,2,3

for FOUT of 125 to 500 MHz

φJKv = 33 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.37

0.33

—

Kv = 45 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.37

0.33

—

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.43

0.34

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.50

0.34

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.59

0.35

—

Kv = 356 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

1.00

0.39

—

Table 6. CLK± Output Period Jitter

Parameter Symbol Test Condition Min Typ Max Units

Period Jitter* JPER RMS — 2 — ps

Peak-to-Peak — 14 —

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.

Table 5. CLK± Output Phase Jitter (Continued)

Parameter Symbol Test Condition Min Typ Max Units

Notes:

1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.

2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.

3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply

rejection (PSR) advantage of Si55x versus SAW-based solutions.

Si550

6 Rev. 0.6

Table 7. CLK± Output Phase Noise (Typical)

Offset Frequency 74.25 MHz

90 ppm/V

LVPECL

491.52 MHz

45 ppm/V

LVPECL

622.08 MHz

135 ppm/V

LVPECL

Units

100 Hz

1kHz

10 kHz

100 kHz

1MHz

10 MHz

100 MHz

–87

–114

–132

–142

–148

–150

n/a

–75

–100

–116

–124

–135

–146

–147

–65

–90

–109

–121

–134

–146

–147

dBc/Hz

Table 8. Absolute Maximum Ratings1

Parameter Symbol Rating Units

Maximum Operating Temperature TAMAX 85 ºC

Supply Voltage VDD –0.5 to +3.8 Volts

Input Voltage VI–0.5 to VDD + 0.3 Volts

Storage Temperature TS–55 to +125 ºC

ESD Sensitivity (HBM, per JESD22-A114) ESD 2500 Volts

Soldering Temperature (Pb-free profile)2TPEAK 260 ºC

Soldering Temperature Time @ TPEAK (Pb-free profile)2tP20–40 seconds

Notes:

1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional

operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for

extended periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download from

www.silabs.com/VCXO for further information, including soldering profiles.

Table 9. Environmental Compliance

The Si550 meets the following qualification test requirements.

Parameter Conditions/Test Method

Mechanical Shock MIL-STD-883F, Method 2002.3 B

Mechanical Vibration MIL-STD-883F, Method 2007.3 A

Solderability MIL-STD-883F, Method 203.8

Gross & Fine Leak MIL-STD-883F, Method 1014.7

Resistance to Solvents MIL-STD-883F, Method 2016

Si550

Rev. 0.6 7

2. Pin Descriptions

Table 10. Si550 Pin Descriptions

Pin Name Type Function

1 VCAnalog Input Control Voltage

2OE* Input

Output Enable (Polarity = High):

0 = clock output disabled (outputs tri-stated)

1 = clock output enabled

3GND Ground Electrical and Case Ground

4CLK+ Output Oscillator Output

5CLK–

(N/A for CMOS)

Output Complementary Output

(N/C for CMOS)

6 VDD Power Power Supply Voltage

*Note: OE includes 17 kΩ pullup resistor to VDD. See Section 3. "Ordering Information" on page 8 for details on OE polarity

ordering options.

GND

VDD

CLK+

CLK–

(Top View)

Si550

8 Rev. 0.6

3. Ordering Information

The Si550 supports a variety of options including frequency, temperature stability, tuning slope, output format, and

VDD. Specific device configurations are programmed into the Si550 at time of shipment. Configurations are

specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part

number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool

and for further ordering instructions. The Si550 VCXO series is supplied in an industry-standard, RoHS compliant,

lead-free, 6-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.

Figure 1. Part Number Convention

R = Tape & Reel

Blank = Trays

Operating Temp Range (°C)

G –40 to +85 °C

Device Revision Letter

550 VCXO

Product Family

550 X X XXXMXXX D G R

1st Option Code

VDD Output Format Output Enable Polarity

A 3.3 LVPECL High

B 3.3 LVDS High

C 3.3 CMOS High

D3.3CML High

E 2.5 LVPECL High

F 2.5 LVDS High

G 2.5 CMOS High

H2.5CML High

J 1.8 CMOS High

K1.8CML High

M3.3LVPECL Low

N3.3LVDS Low

P3.3CMOS Low

Q3.3CML Low

R2.5LVPECL Low

S2.5LVDS Low

T2.5CMOS Low

U2.5CML Low

V1.8CMOS Low

W1.8CML Low

Note:

CMOS available to 160 MHz.

2nd Option Code

Temperature Tuning Slope Minimum APR

Stability Kv (±ppm) for VDD @

Code ± ppm (max) ppm/V (typ) 3.3 V 2.5 V 1.8 V

A 100 180 100 75 25

B 100 90 30 Note 6 Note 6

C 50 180 150 125 75

D50 90 803025

E 20 45 25 Note 6 Note 6

F50 135 1007550

G 20 356 375 300 235

H 20 180 185 145 105

J 20 135 130 104 70

K 100 356 295 220 155

M 20 33 12 Note 6 Note 6

Notes:

1. For best jitter and phase noise performance, always choose the smallest Kv that meets

the application’s minimum APR requirements. Unlike SAW-based solutions which

require higher higher Kv values to account for their higher temperature dependence,

the Si55x series provides lower Kv options to minimize noise coupling and jitter in real-

world PLL designs. See AN255 and AN266 for more information.

2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an

APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability over 15 years over all

operating conditions.

3. Nominal Pull range (±) = 0.5 x VDD x tuning slope.

4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging

= 0.5 x VDD x tuning slope – stability – 10 ppm

5. Minimum APR values noted above include worst case values for all parameters.

6. Combination not available.

Example Part Number: 550AF622M080DGR is a 5 x 7 mm VCXO in a 6 pad package. The nominal frequency is 622.080 MHz, with a 3.3 V supply,

LVPECL output, and Output Enable active high polarity. Temperature stability is specified as ±50 ppm and the tuning slope is 135 ppm/V. The part

is specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format.

Frequency (e.g. 622M080 is 622.080 MHz)

Available frequency range is 10 to 945 MHz, 970 to 1134, and 1213 to

1417 MHz. The position of “M” shifts to denote higher or lower

frequencies. If the frequency of interest requires greater than 6 digit

resolution, a six digit code will be assigned for the specific frequency.

Si550

Rev. 0.6 9

4. Si55x Mark Specification

Figure 2 illustrates the mark specification for the Si550. Table 11 lists the line information.

Figure 2. Mark Specification

Table 11. Si55x Top Mark Description

Line Position Description

1 1–10 “SiLabs”+ Part Family Number, 5xx (First 3 characters in part number)

2 1–10 Si550: Option1+Option2+Freq(7)+Temp

Si552, Si554, Si550 w/ 8-digit resolution: Option1+Option2+ConfigNum(6)+Temp

3 Trace Code

Position 1 Pin 1 orientation mark (dot)

Position 2 Product Revision (D)

Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions)

Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7)

Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site

Position 10 “+” to indicate Pb-Free and RoHS-compliant

SiLabs 123

123

R T T T T Y W W +

1 2 3 4 5 6 7 8 9 0

Si550

10 Rev. 0.6

5. Outline Diagram and Suggested Pad Layout

Figure 3 illustrates the package details for the Si550. Table 12 lists the values for the dimensions shown in the

illustration.

Figure 3. Si550 Outline Diagram

Table 12. Package Diagram Dimensions (mm)

Dimension Min Nom Max

A 1.45 1.65 1.85

b1.21.41.6

c0.60 TYP.

D 7.00 BSC.

D1 6.10 6.2 6.30

e 2.54 BSC.

E 5.00 BSC.

E1 4.30 4.40 4.50

L 1.07 1.27 1.47

S 1.815 BSC.

R 0.7 REF.

aaa — — 0.15

bbb — — 0.15

ccc — — 0.10

ddd — — 0.10

Si550

Rev. 0.6 11

6. 6-Pin PCB Land Pattern

Figure 4 illustrates the 6-pin PCB land pattern for the Si550. Table 13 lists the values for the dimensions shown in

the illustration.

Figure 4. Si550 PCB Land Pattern

Table 13. PCB Land Pattern Dimensions (mm)

Dimension Min Max

D2 5.08 REF

e 2.54 BSC

E2 4.15 REF

GD 0.84 —

GE 2.00 —

VD 8.20 REF

VE 7.30 REF

X1.70 TYP

Y2.15 REF

ZD — 6.78

ZE — 6.30

Notes:

1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.

2. Land pattern design based on IPC-7351 guidelines.

3. All dimensions shown are at maximum material condition (MMC).

4. Controlling dimension is in millimeters (mm).

Si550

12 Rev. 0.6

DOCUMENT CHANGE LIST

Revision 0.3 to Revision 0.4

Updated Table 1, “Recommended Operating

Conditions,” on page 2.

 Added maximum supply current specifications.

 Specified relationship between temperature at startup

and operation temperature.

Added Output Enable active polarity as an option in

Figure 1, “Part Number Convention,” on page 8.

Revision 0.4 to Revision 0.5

Updated Note 3 in Table 1, “Recommended

Operating Conditions,” on page 2.

Updated Figure 1, “Part Number Convention,” on

page 8.

Revision 0.5 to Revision 0.6

Updated Table 1, “Recommended Operating

Conditions,” on page 2.

 Device maintains stable operation over –40 to +85 ºC

operating temperature range.

 Supply current specifications updated for revision D.

Updated Table 4, “CLK± Output Levels and

Symmetry,” on page 3.

 Updated LVDS differential peak-peak swing

specifications.

Updated Table 5, “CLK± Output Phase Jitter,” on

page 4.

Updated Table 6, “CLK± Output Period Jitter,” on

page 5.

 Revised period jitter specifications.

Updated Table 8, “Absolute Maximum Ratings1,” on

page 6 to reflect the soldering temperature time at

260 ºC is 20–40 sec per JEDEC J-STD-020C.

Updated 3. "Ordering Information" on page 8.

 Changed ordering instructions to revision D.

Added 4. "Si55x Mark Specification" on page 9.

Si550

Rev. 0.6 13

NOTES:

Si550

14 Rev. 0.6

CONTACT INFORMATION

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Email: VCXOinfo@silabs.com

Internet: www.silabs.com

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