IS61WV12816DALL/DALS IS61WV12816DBLL/DBLS IS64WV12816DBLL/DBLS 128K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64WV12816DALL/DBLL) * High-speed access time: 8, 10, 12, 20 ns * Low Active Power: 135 mW (typical) * Low Standby Power: 12 W (typical) CMOS standby LOW POWER: (IS61/64WV12816DALS/DBLS) * High-speed access time: 25, 35 ns * Low Active Power: 55 mW (typical) * Low Standby Power: 12 W (typical) CMOS standby * Single power supply -- Vdd 1.65V to 2.2V (IS61WV12816DAxx) -- Vdd 2.4V to 3.6V (IS61/64WV12816DBxx) * Fully static operation: no clock or refresh required * Three state outputs * Data control for upper and lower bytes * Industrial and Automotive temperature support * Lead-free available JANUARY 2013 DESCRIPTION The ISSI IS61WV12816DAxx/DBxx and IS64WV12816D- Bxx are high-speed, 2,097,152-bit static RAMs organized as 131,072 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61WV12816DAxx/DBxx and IS64WV12816DBxx are packaged in the JEDEC standard 44-pin TSOP Type II and 48-pin Mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CE OE WE UB LB CONTROL CIRCUIT Copyright (c) 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 1 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS TRUTH TABLE I/O PIN Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 Not Selected X H X X X High-Z High-Z Output Disabled H L H X X High-Z High-Z X L X H H High-Z High-Z Read H L L L H Dout High-Z H L L H L High-Z Dout H L L L LDoutDout Write L L X L H Din High-Z L L X H L High-Z Din L L X L LDinDin PIN CONFIGURATION 44-Pin TSOP (Type II) (T) A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Vdd Current Isb1, Isb2 Icc Icc Icc PIN DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC A0-A16 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection Vdd Power GND Ground Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS PIN CONFIGURATION 48-Pin mini BGA (B) 1 2 3 4 5 6 A LB OE A0 A1 A2 NC B I/O8 UB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 NC A7 I/O3 VDD E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 PIN DESCRIPTIONS A0-A16 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection Vdd Power GND Ground 3 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 3.3V + 5% Symbol Voh Vol Vih Vil Ili Ilo Parameter Test Conditions Output HIGH Voltage Vdd = Min., Ioh = -4.0 mA Output LOW Voltage Vdd = Min., Iol = 8.0 mA Input HIGH Voltage Input LOW Voltage(1) Input Leakage GND Vin Vdd Output Leakage GND Vout Vdd, Outputs Disabled Min. 2.4 -- 2 -0.3 -1 -1 Max. -- 0.4 Vdd + 0.3 0.8 1 1 Unit V V V V A A Max. -- 0.4 Vdd + 0.3 0.8 1 1 Unit V V V V A A Note: 1. Vil (min.) = -0.3V DC; Vil (min.) = -2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.4V-3.6V Symbol Voh Vol Vih Vil Ili Ilo Parameter Test Conditions Output HIGH Voltage Vdd = Min., Ioh = -1.0 mA Output LOW Voltage Vdd = Min., Iol = 1.0 mA Input HIGH Voltage Input LOW Voltage(1) Input Leakage GND Vin Vdd Output Leakage GND Vout Vdd, Outputs Disabled Min. 1.8 -- 2.0 -0.3 -1 -1 Note: 1. Vil (min.) = -0.3V DC; Vil (min.) = -2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 1.65V-2.2V Symbol Voh Vol Vih Vil(1) Ili Ilo Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions Ioh = -0.1 mA Iol = 0.1 mA Vdd 1.65-2.2V 1.65-2.2V 1.65-2.2V 1.65-2.2V GND Vin Vdd GND Vout Vdd, Outputs Disabled Min. 1.4 -- 1.4 -0.2 -1 -1 Max. -- 0.2 Vdd + 0.2 0.4 1 1 Unit V V V V A A Note: 1. Vil (min.) = -0.3V DC; Vil (min.) = -2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. 4 Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load R1 ( ) R2 ( ) Vtm (V) Unit (2.4V-3.6V) 0.4V to Vdd - 0.3V 1V/ ns VDD /2 See Figures 1 and 2 1909 1105 3.0V Unit (3.3V + 5%) 0.4V to Vdd - 0.3V 1V/ ns VDD + 0.05 2 See Figures 1 and 2 317 351 3.3V Unit (1.65V-2.2V) 0.4V to Vdd - 0.3V 1V/ ns 0.9V See Figures 1 and 2 13500 10800 1.8V AC TEST LOADS R1 ZO = 50 VTM 50 VDD/2 OUTPUT 30 pF Including jig and scope Figure 1. Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 OUTPUT 5 pF Including jig and scope R2 Figure 2. 5 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS ABSOLUTE MAXIMUM RATINGS(1) Symbol Vterm Vdd Tstg Pt Parameter Terminal Voltage with Respect to GND Vdd Relates to GND Storage Temperature Power Dissipation Value -0.5 to Vdd + 0.5 -0.3 to 4.0 -65 to +150 1.0 Unit V V C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Cin CI/O Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25C, f = 1 MHz, Vdd = 3.3V. 6 Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS HIGH SPEED (IS61WV12816DALL/DBLL) OPERATING RANGE (Vdd) (IS61WV12816DALL) Range Ambient Temperature Commercial 0C to +70C Industrial -40C to +85C Vdd 1.65V-2.2V 1.65V-2.2V OPERATING RANGE (Vdd) (IS61WV12816DBLL)(1) Range Ambient Temperature Commercial 0C to +70C Industrial -40C to +85C Vdd (8 ns)1 3.3V + 5% 3.3V + 5% Speed 20ns 20ns Vdd (10 ns)1 2.4V-3.6V 2.4V-3.6V Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns. OPERATING RANGE (Vdd) (IS64WV12816DBLL)(2,3) Range Automotive Ambient Temperature -40C to +125C Vdd (10 ns)2 3.3V + 5% Vdd (12 ns)2 2.4V-3.6V Note: 2. When operated in the range of 2.4V-3.6V, the device meets 12ns. When operated in the range of 3.3V + 5%, the device meets 10ns. 3. If the device is operated in the temperature range of -40oC to +85oC, the device meets 10ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 -10 -12 -20 Symbol Parameter Test Conditions Min.Max. Min.Max. Min.Max. Min.Max. Unit Icc Vdd Dynamic Operating Vdd = Max., Com. -- 65 -- 60 -- 55 -- 40 mA Supply Current Iout = 0 mA, f = fmax Ind. -- 70 -- 65 -- 55 -- 45 CE = Vil Auto.(3) -- -- -- 75 -- 60 -- 50 Vin Vdd - 0.3V, or typ.(2) 45 45 Vin 0.4V Icc1 Operating Vdd = Max., Com. -- 2 -- 2 -- 2 -- 2 mA Supply Current Iout = 0 mA, f = 0 Ind. --2 --2 --2 --2 CE = Vil Auto. ---- -- 2 -- 2 -- 2 Vin Vdd - 0.3V, or Vin 0.4V Isb2 CMOS Standby Vdd = Max., Com. -- 50 -- 50 -- 50 -- 50 A Current (CMOS Inputs) CE Vdd - 0.2V, Ind. -- 70 -- 70 -- 70 -- 70 Vin Vdd - 0.2V, or Auto. ---- --100 -- 100 -- 100 Vin 0.2V, f = 0 typ.(2) 4 4 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. 3. For Automotive grade at 15ns, typ. Icc = 38mA, not 100% tested. Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 7 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS LOW POWER (IS61WV12816DALS/DBLS) OPERATING RANGE (Vdd) (IS61WV12816DALS) Range Ambient Temperature Commercial 0C to +70C Industrial -40C to +85C Vdd 1.65V-2.2V 1.65V-2.2V Speed 45ns 45ns OPERATING RANGE (Vdd) (IS61WV12816DBLS) Range Ambient Temperature Commercial 0C to +70C Industrial -40C to +85C Vdd (35 ns) 2.4V-3.6V 2.4V-3.6V OPERATING RANGE (Vdd) (IS64WV12816DBLS) Range Automotive Ambient Temperature -40C to +125C Vdd (35 ns) 2.4V-3.6V POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -25 -35 -45 Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit Icc Vdd Dynamic Operating Vdd = Max., Com. -- 20 -- 20 -- 18 mA Supply Current Iout = 0 mA, f = fmax Ind. -- 25 -- 25 -- 20 CE = Vil Auto. -- 40 -- 35 -- 30 Vin Vdd - 0.3V, or typ.(2) 18 Vin 0.4V Icc1 Operating Vdd = Max., Com. -- 2 -- 2 -- 2 mA Supply Current Iout = 0 mA, f = 0 Ind. -- 2 -- 2 -- 2 CE = Vil Auto. -- 2 -- 2 -- 2 Vin Vdd - 0.3V, or Vin 0.4V Isb2 CMOS Standby Vdd = Max., Com. -- 40 -- 40 -- 40 A Current (CMOS Inputs) CE Vdd - 0.2V, Ind. -- 50 -- 50 -- 50 Vin Vdd - 0.2V, or Auto. -- 75 -- 75 -- 75 Vin 0.2V, f = 0 typ.(2) 4 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. 8 Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -8 Symbol Parameter Min. Max. trc Read Cycle Time 8 -- taa Address Access Time -- 8 toha Output Hold Time 2.0 -- tace CE Access Time -- 8 tdoe OE Access Time -- 5.5 thzoe(2) OE to High-Z Output -- 3 tlzoe(2) OE to Low-Z Output 0 -- thzce(2 CE to High-Z Output 0 3 tlzce(2) CE to Low-Z Output 3 -- tba LB, UB Access Time -- 5.5 thzb(2) LB, UB to High-Z Output 0 5.5 (2) tlzb LB, UB to Low-Z Output 0 -- tpu Power Up Time 0 -- tpd Power Down Time -- 8 -10 Min. Max. 10 -- -- 10 2.0 -- -- 10 -- 6.0 -- 4 0 -- 0 4 3 -- -- 6.5 0 6.5 0 -- 0 -- -- 10 -12 Min. Max. 12 -- -- 12 3 -- -- 12 -- 6.0 -- 6 0 -- 0 6 3 -- -- 6.5 0 6.5 0 -- 0 -- -- 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 9 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol trc taa toha tace tdoe thzoe(2) tlzoe(2) thzce(2 tlzce(2) tba thzb tlzb -20 ns -25 ns -35 ns-45 ns Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output Min.Max. 20 -- -- 20 2.5 -- -- 20 -- 8 0 8 0 -- 0 8 3 -- Min. Max. 25 -- -- 25 6 -- -- 25 -- 12 0 8 0 -- 0 8 10 -- Min.Max. 35 -- -- 35 8 -- -- 35 -- 15 0 10 0 -- 0 10 10 -- Min. Max. 45 -- -- 45 10 -- -- 45 -- 20 0 15 0 -- 0 15 10 -- Unit ns ns ns ns ns ns ns ns ns LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output -- 8 0 8 0 -- -- 25 0 8 0 -- -- 35 0 10 0 -- -- 45 0 15 0 -- ns ns ns Notes: 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. 10 Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil, UB or LB = Vil) t RC ADDRESS t OHA DOUT t AA t OHA DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tHZOE tDOE tLZOE CE tACE tLZCE tHZCE LB, UB DOUT VDD Supply Current HIGH-Z tBA tLZB tHZB tRC DATA VALID tPU 50% tPD 50% ICC ISB UB_CEDR2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = Vil. 3. Address is valid prior to or coincident with CE LOW transition. Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 11 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 Symbol twc tsce taw tha tsa tpwb tpwe1 tpwe2 tsd thd thzwe(2) tlzwe(2) Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output Min. 8 6.5 6.5 Max. -- -- -- 0 0 6.5 6.5 8.0 5 0 -- 2 -- -- -- -- -- -- -- 3.5 -- -10 Min. Max. 10 -- 8 -- 8 -- 0 0 8 8 10 6 0 -- 2 -- -- -- -- -- -- -- 5 -- -12 Min. Max. 12 -- 9 -- 9 -- 0 0 9 9 11 9 0 -- 3 Unit ns ns ns -- ns -- ns -- ns -- ns -- ns -- ns --ns 6 ns -- ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development 12 Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) -20 ns-25 ns-35 ns -45ns Symbol ParameterMin.Max. Min.Max. Min.Max. Min.Max. twc Write Cycle Time 20 -- 25 -- 35 -- 45 -- tsce CE to Write End 12 -- 18 -- 25 -- 35 -- taw Address Setup Time 12 -- 15 -- 25 -- 35 -- to Write End tha Address Hold from Write End0-- 0-- 0 -- 0-- tsa Address Setup Time 0 -- 0 -- 0 -- 0 -- tpwb LB, UB Valid to End of Write 12 -- 18 -- 30 -- 35 -- tpwe1 WE Pulse Width (OE = HIGH) 12 -- 18 -- 30 -- 35 -- tpwe2 WE Pulse Width (OE = LOW) 17 -- 20 -- 30 -- 35 -- tsd Data Setup to Write End 9 -- 12 -- 15 -- 20 -- thd Data Hold from Write End0-- 0-- 0 -- 0-- thzwe(3) WE LOW to High-Z Output -- 9 -- 12 -- 20 -- 20 (3) tlzwe WE HIGH to Low-Z Output 3 -- 5 -- 5 -- 5 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 13 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t PBW UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR1.eps Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CEWR2.eps 14 Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS AC WAVEFORMS WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA t PBW UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR3.eps WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CE LOW t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t sa, t ha, t sd, and t hd timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 15 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS HIGH SPEED (IS61WV12816DALL/DBLL) DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) Symbol Parameter Vdd for Data Retention Data Retention Current Test Condition Options Min. Typ.(1) Vdr See Data Retention Waveform 2.0 -- Idr Vdd = 2.0V, CE Vdd - 0.2V Com. -- 10 Ind. -- -- Auto. tsdr Data Retention Setup Time See Data Retention Waveform 0 -- trdr Recovery Time See Data Retention Waveform trc -- Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested. Max. 3.6 50 70 100 -- -- Unit V A Max. 3.6 50 70 100 -- -- Unit V A ns ns o DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V) Symbol Parameter Vdd for Data Retention Data Retention Current Test Condition Options Vdr See Data Retention Waveform Idr Vdd = 1.2V, CE Vdd - 0.2V Com. Ind. Auto. tsdr Data Retention Setup Time See Data Retention Waveform trdr Recovery Time See Data Retention Waveform Note 1: Typical values are measured at Vdd = 1.8V, Ta = 25 C and not 100% tested. Min. 1.2 -- -- -- 0 trc Typ.(1) -- 10 -- -- -- -- ns ns o DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD VDR CE GND 16 CE VDD - 0.2V Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS LOW POWER (IS61WV12816DALS/DBLS) DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) Symbol Vdr Idr Parameter Vdd for Data Retention Data Retention Current Test Condition Options See Data Retention Waveform Vdd = 2.0V, CE Vdd - 0.2V Com. Ind. Auto. See Data Retention Waveform See Data Retention Waveform tsdr Data Retention Setup Time trdr Recovery Time Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested. Min. 2.0 -- -- Typ.(1) -- 20 -- 0 trc Unit V A -- -- Max. 3.6 40 50 75 -- -- Typ.(1) -- 20 -- -- -- -- Max. 3.6 40 50 75 -- -- Unit V A ns ns o DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V) Symbol Vdr Idr Parameter Vdd for Data Retention Data Retention Current Test Condition Options See Data Retention Waveform Vdd = 1.2V, CE Vdd - 0.2V Com. Ind. Auto. See Data Retention Waveform See Data Retention Waveform tsdr Data Retention Setup Time trdr Recovery Time Note 1: Typical values are measured at Vdd = 1.8V, Ta = 25 C and not 100% tested. Min. 1.2 -- -- -- 0 trc ns ns o DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD VDR CE GND Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 CE VDD - 0.2V 17 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS ORDERING INFORMATION (HIGH SPEED) Commercial Range: 0C to +70C Voltage Range: 2.4V to 3.6V Speed (ns) 10 (81) Order Part No. IS61WV12816DBLL-10TL Package TSOP (Type II), Lead-free Note: 1. Speed = 8ns for Vdd = 3.3V + 5%. Speed = 10ns for Vdd = 2.4V to 3.6V. Industrial Range: -40C to +85C Voltage Range: 2.4V to 3.6V Speed (ns) 10 (81) Order Part No. IS61WV12816DBLL-10BI IS61WV12816DBLL-10BLI IS61WV12816DBLL-10TI IS61WV12816DBLL-10TLI Package 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II) TSOP (Type II), Lead-free Note: 1. Speed = 8ns for Vdd = 3.3V + 5%. Speed = 10ns for Vdd = 2.4V to 3.6V. Industrial Range: -40C to +85C Voltage Range: 1.65V to 2.2V Speed (ns) 20 Order Part No. IS61WV12816DALL-20BI IS61WV12816DALL-20TI Package 48 mini BGA (6mm x 8mm) TSOP (Type II) Automotive Range: -40C to +125C Voltage Range: 2.4V to 3.6V Speed (ns) 12 (102,3) Order Part No. IS64WV12816DBLL-12BA3 IS64WV12816DBLL-12BLA3 IS64WV12816DBLL-12CTA3 IS64WV12816DBLL-12CTLA3 Package 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Copper Leadframe TSOP (Type II), Lead-free, Copper Leadframe Note: 2. Speed = 10ns for Vdd = 3.3V + 5%. Speed = 12ns for Vdd = 2.4V to 3.6V. 3. Speed = 10ns for Vdd = 2.4V to 3.6V and temperature = -40oC to +85oC. 18 Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS ORDERING INFORMATION (LOW POWER - IN EVALUATION) Industrial Range: -40C to +85C Voltage Range: 2.4V to 3.6V Speed (ns) 35 Order Part No. Package IS61WV12816DBLS-35TLI TSOP (Type II), Lead-free Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 19 20 08/12/2008 Package Outline 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 Integrated Silicon Solution, Inc. -- www.issi.com Rev. E 01/10/2013 Package Outline 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS, IS64WV12816DBLL/DBLS 21