Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. E
01/10/2013
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
IS61WV12816DALL/DALS
IS61WV12816DBLL/DBLS
IS64WV12816DBLL/DBLS
FEATURES
HIGH SPEED: (IS61/64WV12816DALL/DBLL)
• High-speedaccesstime:8,10,12,20ns
• LowActivePower:135mW(typical)
• LowStandbyPower:12µW(typical)
CMOS standby
LOW POWER: (IS61/64WV12816DALS/DBLS)
• High-speedaccesstime:25,35ns
• LowActivePower:55mW(typical)
• LowStandbyPower:12µW(typical)
CMOS standby
• Singlepowersupply
— Vdd1.65Vto2.2V(IS61WV12816DAxx)
— Vdd2.4Vto3.6V(IS61/64WV12816DBxx)
• Fullystaticoperation:noclockorrefresh
required
• Threestateoutputs
• Datacontrolforupperandlowerbytes
• IndustrialandAutomotivetemperaturesupport
• Lead-freeavailable
128K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM
DESCRIPTION
TheISSIIS61WV12816DAxx/DBxxandIS64WV12816D-
Bxxarehigh-speed,2,097,152-bitstaticRAMsorganized
as131,072wordsby16bits.ItisfabricatedusingISSI's
high-performanceCMOStechnology.Thishighlyreliable
process coupled with innovative circuit design techniques,
yields high-performance and low power consumption
devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be re-
duced down with CMOS input levels.
EasymemoryexpansionisprovidedbyusingChipEnable
andOutputEnableinputs,CEandOE.TheactiveLOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61WV12816DAxx/DBxx and IS64WV12816DBxx
arepackagedintheJEDECstandard44-pinTSOPType
IIand48-pinMiniBGA(6mmx8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A16
CE
OE
WE
128K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
JANUARY 2013
2 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
V
DD
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
V
DD
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
44-Pin TSOP (Type II) (T) PIN DESCRIPTIONS
A0-A16 Address Inputs
I/O0-I/O15 DataInputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byteControl(I/O0-I/O7)
UB Upper-byteControl(I/O8-I/O15)
NC No Connection
Vdd Power
GND Ground
TRUTH TABLE
I/O PIN
Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 VDD Current
Not Selected X H X X X High-Z High-Z Isb1, Isb2
Output Disabled H L H X X High-Z High-Z Icc
X L X H H High-Z High-Z
Read H L L L H dout High-Z Icc
H L L H L High-Z dout
H L L L L dout dout
Write L L X L H dIn High-Z Icc
L L X H L High-Z dIn
L L X L L dIn dIn
PIN CONFIGURATION
Integrated Silicon Solution, Inc. — www.issi.com 3
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
PIN DESCRIPTIONS
A0-A16 Address Inputs
I/O0-I/O15 DataInputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byteControl(I/O0-I/O7)
UB Upper-byteControl(I/O8-I/O15)
NC No Connection
Vdd Power
GND Ground
48-Pin mini BGA (B)
PIN CONFIGURATION
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB OE A0 A1 A2 NC
I/O8UB A3 A4 CE I/O0
I/O9I/O10 A5 A6 I/O1I/O2
GND I/O11 NC A7 I/O3VDD
VDD I/O12 NC A16 I/O4GND
I/O14 I/O13 A14 A15 I/O5I/O6
I/O15 NC A12 A13 WE I/O7
NC A8 A9 A10 A11 NC
4 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.4V-3.6V
Symbol Parameter Test Conditions Min. Max. Unit
VoH Output HIGH Voltage Vdd = Min., IoH = –1.0 mA 1.8 — V
VoL Output LOW Voltage Vdd = Min., IoL = 1.0 mA — 0.4 V
VIH Input HIGH Voltage 2.0 Vdd + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND ≤ VIn ≤ Vdd –1 1 µA
ILo Output Leakage GND ≤ Vout ≤ Vdd, OutputsDisabled –1 1 µA
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
VIH (max.)= Vdd + 0.3V dc; VIH (max.)= Vdd + 2.0V Ac (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 3.3V + 5%
Symbol Parameter Test Conditions Min. Max. Unit
VoH Output HIGH Voltage Vdd = Min., IoH = –4.0 mA 2.4 — V
VoL Output LOW Voltage Vdd = Min., IoL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2 Vdd + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND ≤ VIn ≤ Vdd –1 1 µA
ILo Output Leakage GND ≤ Vout ≤ Vdd, OutputsDisabled –1 1 µA
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
VIH (max.)= Vdd + 0.3V dc; VIH (max.)= Vdd + 2.0V Ac (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 1.65V-2.2V
Symbol Parameter Test Conditions VDD Min. Max. Unit
VoH Output HIGH Voltage IoH = -0.1mA 1.65-2.2V 1.4 — V
VoL Output LOW Voltage IoL = 0.1mA 1.65-2.2V — 0.2 V
VIH InputHIGHVoltage 1.65-2.2V 1.4 Vdd + 0.2 V
VIL(1) Input LOW Voltage 1.65-2.2V –0.2 0.4 V
ILI Input Leakage GND ≤ VIn ≤ Vdd –1 1 µA
ILo Output Leakage GND ≤ Vout ≤ Vdd, OutputsDisabled –1 1 µA
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
VIH (max.)= Vdd + 0.3V dc; VIH (max.)= Vdd + 2.0V Ac (pulse width < 10 ns). Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com5
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
AC TEST LOADS
Figure 1.
R1
5 pF
Including
jig and
scope
R2
OUTPUT
VTM
Figure 2.
ZO = 50Ω
VDD/2
50Ω
OUTPUT
30 pF
Including
jig and
scope
AC TEST CONDITIONS
Parameter Unit Unit Unit
(2.4V-3.6V) (3.3V + 5%) (1.65V-2.2V)
Input Pulse Level 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V
InputRiseandFallTimes 1V/ns 1V/ns 1V/ns
InputandOutputTiming VDD/2 VDD+0.05 0.9V
and Reference Level (VRef) 2
OutputLoad SeeFigures1and2 SeeFigures1and2 SeeFigures1and2
R1 ( Ω ) 1909 317 13500
R2 ( Ω ) 1105 351 10800
Vtm (V) 3.0V 3.3V 1.8V
6 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
Vterm TerminalVoltagewithRespecttoGND –0.5toVdd+0.5 V
Vdd Vdd Relates to GND –0.3 to 4.0 V
tstg StorageTemperature –65to+150 °C
Pt Power Dissipation 1.0 W
Notes:
1.StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamageto
thedevice.Thisisastressratingonlyandfunctionaloperationofthedeviceattheseoranyotherconditions
abovethoseindicatedintheoperationalsectionsofthisspecicationisnotimplied.Exposuretoabsolute
maximumratingconditionsforextendedperiodsmayaffectreliability.
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
cIn Input Capacitance VIn = 0V 6 pF
cI/o Input/Output Capacitance Vout = 0V 8 pF
Notes:
1.Testedinitiallyandafteranydesignorprocesschangesthatmayaffecttheseparameters.
2. Testconditions:TA = 25°c, f=1MHz,Vdd = 3.3V.
Integrated Silicon Solution, Inc. — www.issi.com7
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
OPERATING RANGE (VDD) (IS61WV12816DBLL)(1)
Range Ambient Temperature VDD (8 nS)1 VDD (10 nS)1
Commercial 0°Cto+70°C 3.3V+5% 2.4V-3.6V
Industrial –40°Cto+85°C 3.3V+5% 2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range
of 3.3V +5%,thedevicemeets8ns.
OPERATING RANGE (VDD) (IS64WV12816DBLL)(2,3)
Range Ambient Temperature VDD (10 nS)2 VDD (12 nS)2
Automotive –40°Cto+125°C 3.3V+5% 2.4V-3.6V
Note:
2. When operated in the range of 2.4V-3.6V, the device meets 12ns. When operated in the range of
3.3V +5%,thedevicemeets10ns.
3. If the device is operated in the temperature range of -40oCto+85oC, the device meets 10ns.
HIGH SPEED (IS61WV12816DALL/DBLL)
OPERATING RANGE (VDD) (IS61WV12816DALL)
Range Ambient Temperature VDD Speed
Commercial 0°Cto+70°C 1.65V-2.2V 20ns
Industrial –40°Cto+85°C 1.65V-2.2V 20ns
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 -10 -12 -20
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
Icc Vdd Dynamic Operating Vdd = Max., Com. — 65 — 60 — 55 — 40 mA
Supply Current Iout = 0 mA, f = fmAX Ind. — 70 — 65 — 55 — 45
CE = VIL Auto.(3) — — — 75 — 60 — 50
VIn ≥ Vdd – 0.3V, or typ.(2) 45 45
VIn ≤ 0.4V
Icc1 Operating Vdd = Max., Com. — 2 — 2 — 2 — 2 mA
Supply Current Iout = 0 mA, f = 0 Ind. — 2 — 2 — 2 — 2
CE = VIL Auto. — — — 2 — 2 — 2
VIn ≥ Vdd – 0.3V, or
VIn ≤ 0.4V
Isb2 CMOS Standby Vdd = Max., Com. — 50 — 50 — 50 — 50
µ
A
Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 70 — 70 — 70 — 70
VIn ≥ Vdd – 0.2V, or Auto. — — — 100 — 100 — 100
VIn ≤ 0.2V
, f = 0 typ.(2) 4 4
Note:
1. At f = fmAX,addressanddatainputsarecyclingatthemaximumfrequency,f=0meansnoinputlineschange.
2.TypicalvaluesaremeasuredatVdd=3.0V,TA=25oC and not 100% tested.
3.ForAutomotivegradeat15ns,typ.Icc=38mA,not100%tested.
8 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25 -35 -45
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
Icc Vdd Dynamic Operating Vdd = Max., Com. — 20 — 20 — 18 mA
Supply Current Iout = 0 mA, f = fmAX Ind. — 25 — 25 — 20
CE = VIL Auto. — 40 — 35 — 30
VIn ≥ Vdd – 0.3V, or typ.(2) 18
VIn ≤ 0.4V
Icc1 Operating Vdd = Max., Com. — 2 — 2 — 2 mA
Supply Current Iout = 0 mA, f = 0 Ind. — 2 — 2 — 2
CE = VIL Auto. — 2 — 2 — 2
VIn ≥ Vdd – 0.3V, or
VIn ≤ 0.4V
Isb2 CMOS Standby Vdd = Max., Com. — 40 — 40 — 40
µ
A
Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 50 — 50 — 50
VIn ≥ Vdd – 0.2V, or Auto. — 75 — 75 — 75
VIn ≤ 0.2V
, f = 0 typ.(2) 4
Note:
1. At f = fmAX,addressanddatainputsarecyclingatthemaximumfrequency,f=0meansnoinputlineschange.
2.TypicalvaluesaremeasuredatVdd=3.0V,TA=25oC and not 100% tested.
OPERATING RANGE (VDD) (IS61WV12816DBLS)
Range Ambient Temperature VDD (35 nS)
Commercial 0°Cto+70°C 2.4V-3.6V
Industrial –40°Cto+85°C 2.4V-3.6V
LOW POWER (IS61WV12816DALS/DBLS)
OPERATING RANGE (VDD) (IS61WV12816DALS)
Range Ambient Temperature VDD Speed
Commercial 0°Cto+70°C 1.65V-2.2V 45ns
Industrial –40°Cto+85°C 1.65V-2.2V 45ns
OPERATING RANGE (VDD) (IS64WV12816DBLS)
Range Ambient Temperature VDD (35 nS)
Automotive –40°Cto+125°C 2.4V-3.6V
Integrated Silicon Solution, Inc. — www.issi.com9
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 -10 -12
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
trc ReadCycleTime 8 — 10 — 12 — ns
tAA AddressAccessTime — 8 — 10 — 12 ns
toHA OutputHoldTime 2.0 — 2.0 — 3 — ns
tAce CEAccessTime — 8 — 10 — 12 ns
tdoe OEAccessTime — 5.5 — 6.0 — 6.0 ns
tHzoe(2) OE to High-Z Output — 3 — 4 — 6 ns
tLzoe(2) OE to Low-Z Output 0 — 0 — 0 — ns
tHzce(2 CE to High-Z Output 0 3 0 4 0 6 ns
tLzce(2) CE to Low-Z Output 3 — 3 — 3 — ns
tbA LB, UBAccessTime — 5.5 — 6.5 — 6.5 ns
tHzb(2) LB, UBtoHigh-ZOutput 0 5.5 0 6.5 0 6.5 ns
tLzb(2) LB, UB to Low-Z Output 0 — 0 — 0 — ns
tPu PowerUpTime 0 — 0 — 0 — ns
tPd PowerDownTime — 8 — 10 — 10 ns
Notes:
1. Testconditionsassumesignaltransitiontimesof3nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0Vto3.0V
andoutputloadingspeciedinFigure1.
2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.
10 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-20 ns -25 ns -35 ns -45 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
trc ReadCycleTime 20 — 25 — 35 — 45 — ns
tAA AddressAccessTime — 20 — 25 — 35 — 45 ns
toHA OutputHoldTime 2.5 — 6 — 8 — 10 — ns
tAce CEAccessTime — 20 — 25 — 35 — 45 ns
tdoe OEAccessTime — 8 — 12 — 15 — 20 ns
tHzoe(2) OEtoHigh-ZOutput 0 8 0 8 0 10 0 15 ns
tLzoe(2) OE to Low-Z Output 0 — 0 — 0 — 0 — ns
tHzce(2 CEtoHigh-ZOutput 0 8 0 8 0 10 0 15 ns
tLzce(2) CE to Low-Z Output 3 — 10 — 10 — 10 — ns
tbA LB, UBAccessTime — 8 — 25 — 35 — 45 ns
tHzb LB, UBtoHigh-ZOutput 0 8 0 8 0 10 0 15 ns
tLzb LB, UB to Low-Z Output 0 — 0 — 0 — 0 — ns
Notes:
1. Testconditionsassumesignaltransitiontimesof1.5nsorless,timingreferencelevelsof1.25V,inputpulselevelsof0.4Vto
Vdd-0.3VandoutputloadingspeciedinFigure1a.
2. TestedwiththeloadinFigure1b.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com 11
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z DATA VALID
UB_CEDR2.eps
t
HZB
ADDRESS
OE
CE
LB, UB
D
OUT
t
HZCE
t
BA
t
LZB
t
RC
t
PD
I
SB
I
CC
50%
V
DD
Supply
Current
50%
t
PU
READ CYCLE NO. 2(1,3)
Notes:
1. WE is HIGH for a Read Cycle.
2. Thedeviceiscontinuouslyselected.OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
12 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 -10 -12
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
twc WriteCycleTime 8 — 10 — 12 — ns
tsce CEtoWriteEnd 6.5 — 8 — 9 — ns
tAw AddressSetupTime 6.5 — 8 — 9 — ns
to Write End
tHA Address Hold from Write End 0 — 0 — 0 — ns
tsA AddressSetupTime 0 — 0 — 0 — ns
tPwb LB, UBValidtoEndofWrite 6.5 — 8 — 9 — ns
tPwe1 WEPulseWidth 6.5 — 8 — 9 — ns
tPwe2 WE Pulse Width (OE = LOW) 8.0 — 10 — 11 — ns
tsd DataSetuptoWriteEnd 5 — 6 — 9 — ns
tHd Data Hold from Write End 0 — 0 — 0 — ns
tHzwe(2) WELOWtoHigh-ZOutput — 3.5 — 5 — 6 ns
tLzwe(2) WE HIGH to Low-Z Output 2 — 2 — 3 — ns
Notes:
1. Testconditionsassumesignaltransitiontimesof3nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0Vto3.0V
andoutputloadingspeciedinFigure1.
2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. TheinternalwritetimeisdenedbytheoverlapofCE LOW and UB or LB, and WE LOW. All signals must be in valid states
toinitiateaWrite,butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedto
the rising or falling edge of the signal that terminates the write. Shaded area product in development
Integrated Silicon Solution, Inc. — www.issi.com 13
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-20 ns -25 ns -35 ns -45ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
twc WriteCycleTime 20 — 25 — 35 — 45 — ns
tsce CEtoWriteEnd 12 — 18 — 25 — 35 — ns
tAw AddressSetupTime 12 — 15 — 25 — 35 — ns
to Write End
tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns
tsA AddressSetupTime 0 — 0 — 0 — 0 — ns
tPwb LB, UBValidtoEndofWrite 12 — 18 — 30 — 35 — ns
tPwe1 WE Pulse Width (OE=HIGH) 12 — 18 — 30 — 35 — ns
tPwe2 WE Pulse Width (OE=LOW) 17 — 20 — 30 — 35 — ns
tsd DataSetuptoWriteEnd 9 — 12 — 15 — 20 — ns
tHd Data Hold from Write End 0 — 0 — 0 — 0 — ns
tHzwe(3) WELOWtoHigh-ZOutput — 9 — 12 — 20 — 20 ns
tLzwe(3) WEHIGHtoLow-ZOutput 3 — 5 — 5 — 5 — ns
Notes:
1. TestconditionsforIS61WV6416LLassumesignaltransitiontimesof1.5nsorless,timingreferencelevelsof1.25V,inputpulse
levels of 0.4V to Vdd-0.3VandoutputloadingspeciedinFigure1a.
2. TestedwiththeloadinFigure1b.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. TheinternalwritetimeisdenedbytheoverlapofCE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiateaWrite,butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtothe
rising or falling edge of the signal that terminates the write.
14 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
WRITE CYCLE NO. 2
(WE Controlled. OE is HIGH During Write Cycle) (1,2)
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
DOUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR2.eps
Notes:
1. WRITEisaninternallygeneratedsignalassertedduringanoverlapoftheLOWstatesontheCE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2. WRITE=(CE) [ (LB) = (UB) ] (WE).
AC WAVEFORMS
WRITE CYCLE NO. 1
(CE Controlled, OE is HIGH or LOW) (1 )
Integrated Silicon Solution, Inc. — www.issi.com 15
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
AC WAVEFORMS
WRITE CYCLE NO. 3
(WE Controlled. OE is LOW During Write Cycle) (1)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATAIN VALID
t
LZWE
t
SD
UB_CEWR3.eps
WRITE CYCLE NO. 4
(LB, UB Controlled, Back-to-Back Write) (1,3)
DATA UNDEFINED
t
WC
ADDRESS 1 ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
LOW
WORD 2
UB_CEWR4.eps
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATAIN
VALID
t
LZWE
t
SD
t
PBW
DATAIN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
Notes:
1. TheinternalWritetimeisdenedbytheoverlapofCE = Low, UB and/or LB = Low, and WE = LOW. All signals must be in
validstatestoinitiateaWrite,butanycanbedeassertedtoterminatetheWrite.Thet sA, t HA, t sd, and t Hd timing is referenced
to the rising or falling edge of the signal that terminates the Write.
2. TestedwithOE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
16 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
DATA RETENTION WAVEFORM (CE Controlled)
HIGH SPEED (IS61WV12816DALL/DBLL)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit
Vdr Vdd for Data Retention See Data Retention Waveform 2.0 — 3.6 V
Idr Data Retention Current Vdd = 2.0V, CE ≥ Vdd–0.2V Com. — 10 50
µA
Ind. — — 70
Auto. 100
tsdr DataRetentionSetupTime SeeDataRetentionWaveform 0 — — ns
trdr RecoveryTime SeeDataRetentionWaveform trc — — ns
Note 1: TypicalvaluesaremeasuredatVdd=3.0V,TA = 25
o
c and not 100% tested.
VDD
CE ≥ V
DD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
Data Retention Mode
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V)
Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit
Vdr Vdd for Data Retention See Data Retention Waveform 1.2 — 3.6 V
Idr Data Retention Current Vdd = 1.2V, CE ≥ Vdd–0.2V Com. — 10 50
µA
Ind. — — 70
Auto. — — 100
tsdr DataRetentionSetupTime SeeDataRetentionWaveform 0 — — ns
trdr RecoveryTime SeeDataRetentionWaveform trc — — ns
Note 1: TypicalvaluesaremeasuredatVdd=1.8V,TA = 25
o
c and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com 17
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
DATA RETENTION WAVEFORM (CE Controlled)
LOW POWER (IS61WV12816DALS/DBLS)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit
Vdr Vdd for Data Retention See Data Retention Waveform 2.0 — 3.6 V
Idr Data Retention Current Vdd = 2.0V, CE ≥ Vdd – 0.2V Com. — 20 40
µA
Ind. — — 50
Auto. 75
tsdr DataRetentionSetupTime SeeDataRetentionWaveform 0 — — ns
trdr RecoveryTime SeeDataRetentionWaveform trc — — ns
Note 1: TypicalvaluesaremeasuredatVdd=3.0V,TA = 25
o
c and not 100% tested.
VDD
CE ≥ V
DD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
Data Retention Mode
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V)
Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit
Vdr Vdd for Data Retention See Data Retention Waveform 1.2 — 3.6 V
Idr Data Retention Current Vdd = 1.2V, CE ≥ Vdd – 0.2V Com. — 20 40
µA
Ind. — — 50
Auto. — — 75
tsdr DataRetentionSetupTime SeeDataRetentionWaveform 0 — — ns
trdr RecoveryTime SeeDataRetentionWaveform trc — — ns
Note 1: TypicalvaluesaremeasuredatVdd=1.8V,TA = 25
o
c and not 100% tested.
18 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
ORDERING INFORMATION (HIGH SPEED)
Commercial Range: 0°C to +70°C
Voltage Range: 2.4V to 3.6V
Speed (ns) Order Part No. Package
10 (81) IS61WV12816DBLL-10TL TSOP(TypeII),Lead-free
Note:
1. Speed = 8ns for Vdd = 3.3V +5%.Speed=10nsforVdd = 2.4V to 3.6V.
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed (ns) Order Part No. Package
10 (81) IS61WV12816DBLL-10BI 48miniBGA(6mmx8mm)
IS61WV12816DBLL-10BLI 48miniBGA(6mmx8mm),Lead-free
IS61WV12816DBLL-10TI TSOP(TypeII)
IS61WV12816DBLL-10TLI TSOP(TypeII),Lead-free
Note:
1. Speed = 8ns for Vdd = 3.3V +5%.Speed=10nsforVdd = 2.4V to 3.6V.
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
Speed (ns) Order Part No. Package
20 IS61WV12816DALL-20BI 48miniBGA(6mmx8mm)
IS61WV12816DALL-20TI TSOP(TypeII)
Automotive Range: -40°C to +125°C
Voltage Range: 2.4V to 3.6V
Speed (ns) Order Part No. Package
12 (102,3) IS64WV12816DBLL-12BA3 48miniBGA(6mmx8mm)
IS64WV12816DBLL-12BLA3 48miniBGA(6mmx8mm),Lead-free
IS64WV12816DBLL-12CTA3 TSOP(TypeII),CopperLeadframe
IS64WV12816DBLL-12CTLA3
TSOP(TypeII),Lead-free,CopperLeadframe
Note:
2. Speed = 10ns for Vdd = 3.3V +5%.Speed=12nsforVdd = 2.4V to 3.6V.
3. Speed = 10ns for Vdd = 2.4V to 3.6V and temperature = -40oCto+85oC.
Integrated Silicon Solution, Inc. — www.issi.com 19
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
ORDERING INFORMATION (LOW POWER - IN EVALUATION)
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed (ns) Order Part No. Package
35 IS61WV12816DBLS-35TLITSOP(TypeII),Lead-free
20 Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
2. Reference document : JEDEC MO-207
1. CONTROLLING DIMENSION : MM .
NOTE :
08/12/2008
Package Outline
Integrated Silicon Solution, Inc. — www.issi.com 21
Rev. E
01/10/2013
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
06/04/2008
Package Outline