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FEATURES
D PACKAGE
(TOP VIEW)
GND
1
2
3
45
6
7
8
Sx
Rx
Tx
Ty
Ry
Sy
VCC
P PACKAGE
(TOP VIEW)
1
2
3
45
6
7
8
Sx
Rx
Tx
GND Ty
Ry
Sy
VCC
DGK PACKAGE
(TOP VIEW)
1
2
3
45
6
7
8
Ty
Ry
Sy
VCC
Sx
Rx
Tx
GND
PW PACKAGE
(TOP VIEW)
1
2
3
45
6
7
8
Sx
Rx
Tx
GND Ty
Ry
Sy
VCC
DESCRIPTION/ORDERING INFORMATION
P82B96DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
•Operating Power-Supply Voltage Range Forward (Tx/Ty) and Reverse (Rx/Ry) Signalsof 2 V to 15 V for Interface With Optoelectrical Isolators andSimilar Devices That Need Unidirectional•Can Interface Between I
2
C Buses Operating at
Input and Output Signal PathsDifferent Logic Levels (2 V to 15 V)
•400-kHz Fast I
2
C Bus Operation Over at Least•Supports Bidirectional Data Transfer of I
2
C
20 Meters of WireBus Signals
•Low Standby Current Consumption•Allows Bus Capacitance of 400 pF on the MainI
2
C Bus (Sx/Sy Side) and 4000 pF on the •Latch-Up Performance Exceeds 100 mA PerTransmission Side (Tx/Ty) JESD 78, Class II•Outputs on the Transmission Side (Tx/Ty) •ESD Protection Exceeds JESD 22Have High Sink Capability for Driving
– 3500-V Human-Body Model (A114-A)Low-Impedance or High-Capacitive Buses
– 200-V Machine Model (A115-A)•I
2
C Bus Signals Can Be Split Into Pairs of
– 1000-V Charged-Device Model (C101)
The P82B96 is a bipolar device that supports bidirectional data transfer between the normal I
2
C bus and a rangeof other bus configurations with different voltage and current levels. It can function as the interface without anylimitations on the normal I
2
C operation and clock speed.
ORDERING INFORMATION
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
PDIP – P Tube of 50 P82B96P P82B96PReel of 2000 P82B96DRSOIC – D PG96Tube of 75 P82B96D–40 °C to 85 °C
Reel of 2000 P82B96PWRTSSOP – PW PG96Tube of 150 P82B96PWVSSOP – DGK Reel of 2500 P82B96DGKR 7DS
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
One of the advantages of the P82B96 is that it can isolate bus capacitance such that the total loading (devicesand trace lengths) of the new bus or remote I
2
C nodes are not apparent to other I
2
C buses (or nodes). Thisdevice also adds minimal loading to I
2
C node where it is positioned. Any restrictions on the number of I
2
Cdevices in a system, or the physical separation between them, are virtually eliminated.
The P82B96 easily can transmit SDA/SCL signals via balanced transmission lines (twisted pairs) or withgalvanic isolation (optocoupling), because separate directional Tx and Rx signals are provided. The Tx and Rxsignals may be connected directly (without causing bus latching), to provide an alternative bidirectional signalline with I
2
C properties.
Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design does not support this configuration.Bidirectional I
2
C signals do not allow any direction control pin so, instead, slightly different logic low-voltagelevels are used at Sx/Sy to avoid latching of this buffer. A regular I
2
C low applied at the Rx/Ry of a P82B96 ispropagated to Sx/Sy as a buffered low with a slightly higher voltage level. If this special buffered low is appliedto the Sx/Sy of another P82B96, the second P82B96 does not recognize it as a regular I
2
C bus low and doesnot propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to similar buffers that relyon special logic thresholds for their operation, such as the PCA9515A.
The Sx/Sy side is intended only for, and compatible with, the normal I
2
C logic voltage levels of I
2
C master andslave devices or Tx/Rx signals of a second P82B96, if required. The Tx/Rx and Ty/Ry I/O pins use the standardI
2
C logic voltage levels of all I
2
C parts. If Rx and Tx are connected, Sx can function as either the SDA or SCLline. Similarly, if Ry and Ty are connected, Sy can function as either the SDA or SCL line. There are norestrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star ormulti-point configuration with the Tx/Rx and Ty/Ry I/O pins on the common bus, and the Sx/Sy side connectedto the line-card slave devices.
TERMINAL FUNCTIONS
NO. NAME DESCRIPTION
1 Sx Serial data bus or SDA. Connect to V
CC
of I
2
C master through a pullup resistor.2 Rx Receive signal. Connect to V
CC
of P82B96 through a pullup resistor.3 Tx Transmit signal. Connect to V
CC
of P82B96 through a pullup resistor.4 GND Ground5 Ty Transmit signal. Connect to V
CC
of P82B96 through a pullup resistor.6 Ry Receive signal. Connect to V
CC
of P82B96 through a pullup resistor.7 Sy Serial clock bus or SCL. Connect to V
CC
of I
2
C master through a pullup resistor.8 V
CC
Supply voltage
2
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P82B96
Sx (SDA)
Sy (SCL)
Ry (RxD, SCL)
Ty (TxD, SCL)
Rx (RxD, SDA)
Tx (TxD, SDA)
1
7
4
GND
6
5
2
3
8
V (2–15V)
CC
Functional Description
Sx and Sy
Tx and Ty
P82B96DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
FUNCTIONAL BLOCK DIAGRAM
The I
2
C pins, Sx and Sy, are designed to interface with a normal I
2
C bus. The logic threshold-voltage levels onthe I
2
C bus are independent of the supply V
CC
. The maximum I
2
C bus supply voltage is 15 V, and the specifiedstatic sink current is 3 mA.
Sx and Sy have two identical buffers. Each buffer is made up of two logic signal paths. The first one, named Txor Ty, is a forward path from the I
2
C interface pin, which drives the buffered bus. The second one, named Rx orRy, is a reverse signal path from the buffered bus input to drive the I
2
C bus interface.
There are two purposes for these paths: to sense the voltage state of the I
2
C pin (Sx or Sy) and transmit thisstate to Tx or Ty, respectively, and to detect the state of the Rx or Ry and pull the I
2
C pin low when Rx or Ry islow.
Tx and Ty are open-collector outputs without ESD protection diodes to V
CC
. Each pin may be connected via apullup resistor to a supply voltage in excess of V
CC
, as long as the 15-V rating is not exceeded. Tx and Ty havea larger current-sinking capability than a normal I
2
C device and can sink a static current of greater than 30 mA.They also have dynamic pulldown capability of 100-mA, typically.
A logic low is transmitted to Tx or Ty only when the voltage at the I
2
C pin (Sx or Sy) is below 0.6 V. A logic lowat Rx or Ry causes the I
2
C bus (Sx or Sy) to be pulled to a logic low level in accordance with I
2
C requirements(maximum 1.5 V in 5-V applications), but not low enough to be looped back to the Tx or Ty output and cause thebuffer to latch low.
The minimum low level that the P82B96 can achieve on the I
2
C bus by a low at Rx or Ry typically is 0.8 V.
If V
CC
fails, neither the I
2
C pins nor the Tx or Ty outputs are held low. Their open-collector configuration allowsthem to be pulled up to the rated maximum of 15 V without V
CC
present. The input configuration on Sx, Sy, Rx,and Ry also presents no loading of external signals when V
CC
is not present.
The effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than 4 pF forall bus voltages and supply voltages, including V
CC
= 0 V.
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.3 18 VSx or Sy (SDA or SCL) –0.3 18V
I
Voltage range on buffered input VRx or Ry –0.3 18Sx or Sy (SDA or SCL) –0.3 18V
O
Voltage range on buffered output VTx or Ty –0.3 18Sx or Sy 250I
O
Continuous output current mATx or Ty 250I
CC
Continuous current through V
CC
or GND 250 mAD package 97P package 85θ
JA
Package thermal impedance
(2)
°C/WPW package 149DGK package 172T
stg
Storage temperature range –55 125 °CT
A
Operating free-air temperature range –40 85 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN MAX UNIT
V
CC
Supply voltage 2 15 VSx, Sy V
Sx
, V
Sy
= 1 V, V
Rx
, V
Ry
≤0.42 V 3I
OL
Low-level output current mATx, Ty V
Sx
, V
Sy
= 0.4 V, V
Tx
, V
Ty
= 0.4 V 30Sx, Sy V
Tx
, V
Ty
= 0.4 V 15V
IOmax
Maximum input/output voltage level VTx, Ty V
Sx
, V
Sy
= 0.4 V 15V
ILdiff
Low-level input voltage difference Sx, Sy 0.4 VT
A
Operating free-air temperature –40 85 °C
4
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Electrical Characteristics
P82B96DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
V
CC
= 2.3 V to 2.7 V, voltages are specified with respect to GND (unless otherwise noted)
T
A
= 25 °C T
A
= –40 °C to 85 °CTESTPARAMETER UNITCONDITIONS
MIN TYP
(1)
MAX MIN MAX
Temperature coefficient ofΔV/ ΔT
IN
Sx, Sy –2 mV/ °Cinput thresholds
I
Sx
, I
Sy
= 3 mA 0.8 0.88 1V
OL
Low-level output voltage Sx, Sy
(2)
VI
Sx
, I
Sy
= 0.2 mA 0.67 0.73 0.79
(2)
Temperature coefficient ofΔV/ ΔT
OUT
Sx, Sy I
Sx
, I
Sy
= 0.2 mA –1.8 mV/ °Coutput low levels
(3)
I
CC
Quiescent supply current Sx = Sy = V
CC
0.9 1.8 2 mAAdditional supply currentΔI
CC
Tx, Ty 1.7 2.75 3 mAper pin lowDynamic output sink V
Sx
, V
Sy
> 2 V,
7 18 5.5 mAcapability on I
2
C bus V
Rx
, V
Ry
= lowI
IOS
Sx, Sy
V
Sx
, V
Sy
= 2.5 V,Leakage current on I
2
C bus 0.1 1 1 μAV
Rx
, V
Ry
= highV
Tx
, V
Ty
> 1 V,Dynamic output sink
Tx, Ty V
Sx
, V
Sy
= low on 60 100 60 mAcapability on buffered bus
I
2
C bus = 0.4 VI
IOT
V
Tx
, V
Ty
= V
CC
=Leakage current
2.5 V, 0.1 1 1 μAon buffered bus
V
Sx
, V
Sy
= highBus low, V
Rx
,Input current from I
2
C bus Sx, Sy –1 1V
Ry
= highInput current Bus low, V
Rx
,I
I
–1 1 μAfrom buffered bus V
Ry
= 0.4 VRx, RyLeakage current
V
Rx
, V
Ry
= V
CC
1 1.5on buffered bus input
Input logic level highthreshold
(4)
0.65 0.7
(2)
on normal I
2
C busSx, Sy
Input logic level lowthreshold
(4)
0.6 0.65
(2)V
IT
Input threshold Von normal I
2
C busInput logic level high 0.58 V
CC
0.58 V
CC
Rx, Ry Input threshold 0.5 V
CC
Input logic level low 0.42 V
CC
0.42 V
CC
(V
Sx
output lowInput/output logic level at 3 mA) –V
IOdiff
Sx, Sy 100 150 100 mVdifference
(5)
(V
Sx
input high max)for I
2
C applications
Sx, Sy are low, V
CCV
CC
voltage at which all Sx, Sy ramping, voltage onV
IOrel
1 1 Vbuses are released Tx, Ty Tx, Ty lowered untilreleasedTemperature coefficient of releaseΔV/ ΔT
REL
–4 mV/ °CvoltageC
in
Input capacitance Rx, Ry 2.5 4 4 pF
(1) Typical value is at V
CC
= 2.5 V, T
A
= 25 °C(2) See the Typical Characteristics section of this data sheet.(3) The output logic low depends on the sink current.(4) The input logic threshold is independent of the supply voltage.(5) The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for V
SX
output low always exceeds theminimum V
Sx
input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of anotherP82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices should never be linked,because the resulting system would be very susceptible to induced noise and would not support all I
2
C operating modes.
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Electrical Characteristics
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
V
CC
= 3 V to 3.6 V, voltages are specified with respect to GND (unless otherwise noted)
T
A
= 25 °C T
A
= –40 °C to 85 °CPARAMETER TEST CONDITIONS UNITMIN TYP
(1)
MAX MIN MAX
TemperatureΔV/ ΔT
IN
coefficient of Sx, Sy –2 mV/ °Cinput thresholds
I
Sx
, I
Sy
= 3 mA 0.8 0.88 1Low-level outputV
OL
Sx, Sy
(2)
Vvoltage
I
Sx
, I
Sy
= 0.2 mA 0.67 0.73 0.79
(2)
Temperature
coefficient ofΔV/ ΔT
OUT
Sx, Sy I
Sx
, I
Sy
= 0.2 mA –1.8 mV/ °Coutput lowlevels
(3)
I
CC
Quiescent supply current Sx = Sy = V
CC
0.9 1.8 2 mAAdditional supplyΔI
CC
current per pin Tx, Ty 1.7 2.75 3 mAlow
Dynamic output
V
Sx
, V
Sy
> 2 V,sink capability 7 18 5.7 mAV
Rx
, V
Ry
= lowon I
2
C busI
IOS
Sx, SyLeakage current V
Sx
, V
Sy
= 5 V,
0.1 1 1 μAon I
2
C bus V
Rx
, V
Ry
= highDynamic output V
Tx
, V
Ty
> 1 V,sink capability V
Sx
, V
Sy
= low on I
2
C 60 100 60 mAon buffered bus bus = 0.4 VI
IOT
Tx, TyLeakage current V
Tx
, V
Ty
= V
CC
=
0.1 1 1 μAon buffered bus 3.3 V, V
Sx
, V
Sy
= highInput current Bus low, V
Rx
,Sx, Sy –1 1from I
2
C bus V
Ry
= highInput current Bus low, V
Rx
,
–1 1I
I
from buffered bus V
Ry
= 0.4 V μARx, RyLeakage currenton buffered bus V
Rx
, V
Ry
= V
CC
1 1.5input
Input logic-level highthreshold
(4)
0.65 0.7
(2)
on normal I
2
C busSx, Sy
Input logic-level lowthreshold
(4)
0.6 0.65
(2)V
IT
Input threshold Von normal I
2
C busInput logic level high 0.58 V
CC
0.58 V
CC
Rx, Ry Input threshold 0.5 V
CC
Input logic level low 0.42 V
CC
0.42 V
CC
(V
Sx
output lowInput/output logic at 3 mA) –V
IOdiff
Sx, Sy 100 150 100 mVlevel difference
(5)
(V
Sx
input high max)for I
2
C applications
Sx, Sy are low, V
CCV
CC
voltage at
Sx, Sy ramping, voltage onV
IOrel
which all buses 1 1 VTx, Ty Tx, Ty lowered untilare released
released
(1) Typical value is at V
CC
= 3.3 V, T
A
= 25 °C(2) See the Typical Characteristics section of this data sheet.(3) The output logic low depends on the sink current.(4) The input logic threshold is independent of the supply voltage.(5) The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for V
SX
output low always exceeds theminimum V
Sx
input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of anotherP82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices never should be linked,because the resulting system would be very susceptible to induced noise and would not support all I
2
C operating modes.
6
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P82B96DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
Electrical Characteristics (continued)V
CC
= 3 V to 3.6 V, voltages are specified with respect to GND (unless otherwise noted)
T
A
= 25 °C T
A
= –40 °C to 85 °CPARAMETER TEST CONDITIONS UNITMIN TYP
(1)
MAX MIN MAX
Temperature coefficient ofΔV/ ΔT
REL
–4 mV/ °Crelease voltageC
in
Input capacitance Rx, Ry 2.5 4 4 pF
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Electrical Characteristics
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
V
CC
= 4.5 V to 5.5 V, voltages are specified with respect to GND (unless otherwise noted)
T
A
= 25 °C T
A
= –40 °C to 85 °CPARAMETER TEST CONDITIONS UNITMIN TYP
(1)
MAX MIN MAX
TemperatureΔV/ ΔT
IN
coefficient of Sx, Sy –2 mV/ °Cinput thresholds
I
Sx
, I
Sy
= 3 mA 0.8 0.88 1Low-level outputV
OL
Sx, Sy
(2)
Vvoltage
I
Sx
, I
Sy
= 0.2 mA 0.67 0.73 0.79
(2)
Temperature
coefficient ofΔV/ ΔT
OUT
Sx, Sy I
Sx
, I
Sy
= 0.2 mA –1.8 mV/ °Coutput lowlevels
(3)
I
CC
Quiescent supply current Sx = Sy = V
CC
0.9 1.8 2 mAAdditional supplyΔI
CC
current Tx, Ty 1.7 2.75 3 mAper pin lowDynamic output
V
Sx
, V
Sy
> 2 V,sink capability 7 18 6 mAV
Rx
, V
Ry
= lowon I
2
C busI
IOS
Sx, SyLeakage current V
Sx
, V
Sy
= 5 V,
0.1 1 1 μAon I
2
C bus V
Rx
, V
Ry
= highDynamic output V
Tx
, V
Ty
> 1 V,sink capability V
Sx
, V
Sy
= low on 60 100 60 mAon buffered bus I
2
C bus = 0.4 VI
IOT
Tx, TyLeakage current V
Tx
, V
Ty
= V
CC
=
0.1 1 1 μAon buffered bus 5 V, V
Sx
, V
Sy
= highInput current Bus low, V
Rx
,Sx, Sy –1 1from I
2
C bus V
Ry
= highInput current Bus low, V
Rx
,
–1 1I
I
from buffered bus V
Ry
= 0.4 V μARx, RyLeakage currenton buffered bus V
Rx
, V
Ry
= V
CC
1 1.5input
Input logic-level highthreshold
(4)
0.65 0.7
(2)
on normal I
2
C busSx, Sy
Input logic-level lowthreshold
(4)
0.6 0.65
(2)V
IT
Input threshold Von normal I
2
C busInput logic level high 0.58 V
CC
0.58 V
CC
Rx, Ry Input threshold 0.5 V
CC
Input logic level low 0.42 V
CC
0.42 V
CC
(V
Sx
output low atInput/output logic 3 mA) –V
IOdiff
Sx, Sy 100 150 100 mVlevel difference
(5)
(V
Sx
input high max)for I
2
C applications
Sx, Sy are low, V
CCV
CC
voltage at
Sx, Sy ramping, voltage onV
IOrel
which all buses 1 1 VTx, Ty Tx, Ty lowered untilare released
released
(1) Typical value is at V
CC
= 5 V, T
A
= 25 °C(2) See the Typical Characteristics section of this data sheet.(3) The output logic low depends on the sink current.(4) The input logic threshold is independent of the supply voltage.(5) The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for V
SX
output low always exceeds theminimum V
Sx
input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of anotherP82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices never should be linked,because the resulting system would be very susceptible to induced noise and would not support all I
2
C operating modes.
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P82B96DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
Electrical Characteristics (continued)V
CC
= 4.5 V to 5.5 V, voltages are specified with respect to GND (unless otherwise noted)
T
A
= 25 °C T
A
= –40 °C to 85 °CPARAMETER TEST CONDITIONS UNITMIN TYP
(1)
MAX MIN MAX
Temperature coefficient ofΔV/ ΔT
REL
–4 mV/ °Crelease voltageC
in
Input capacitance Rx, Ry 2.5 4 4 pF
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Electrical Characteristics
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
V
CC
= 15 V, voltages are specified with respect to GND (unless otherwise noted)
T
A
= 25 °C T
A
= –40 °C to 85 °CPARAMETER TEST CONDITIONS UNITMIN TYP
(1)
MAX MIN MAX
TemperatureΔV/ ΔT
IN
coefficient of Sx, Sy –2 mV/ °Cinput thresholds
I
Sx
, I
Sy
= 3 mA 0.8 0.88 1Low-level outputV
OL
Sx, Sy
(2)
Vvoltage
I
Sx
, I
Sy
= 0.2 mA 0.67 0.73 0.79
(2)
Temperature
coefficient ofΔV/ ΔT
OUT
Sx, Sy I
Sx
, I
Sy
= 0.2 mA –1.8 mV/ °Coutput lowlevels
(3)
Quiescent supplyI
CC
Sx = Sy = V
CC
0.9 1.8 2 mAcurrent
Additional supplyΔI
CC
current Tx, Ty 1.7 2.75 3 mAper pin lowDynamic output
V
Sx
, V
Sy
> 2 V,sink capability 7 18 6.5 mAV
Rx
, V
Ry
= lowon I
2
C busI
IOS
Sx, SyLeakage current V
Sx
, V
Sy
= 15 V,
0.1 1 1 μAon I
2
C bus V
Rx
, V
Ry
= highDynamic output V
Tx
, V
Ty
> 1 V,sink capability V
Sx
, V
Sy
= low on 60 100 60 mAon buffered bus I
2
C bus = 0.4 VI
IOT
Tx, Ty
V
Tx
, V
Ty
= V
CC
=Leakage current
15 V, 0.1 1 1 μAon buffered bus
V
Sx
, V
Sy
= highInput current Bus low, V
Rx
,Sx, Sy –1 1from I
2
C bus V
Ry
= highInput current Bus low, V
Rx
,
–1 1I
I
from buffered bus V
Ry
= 0.4 V μARx, RyLeakage currenton buffered bus V
Rx
, V
Ry
= V
CC
1 1.5input
Input logic-level highthreshold
(4)
0.65 0.7
(2)
on normal I
2
C busSx, Sy
Input logic-level highthreshold
(4)
0.6 0.65
(2)V
IT
Input threshold Von normal I
2
C busInput logic level high 0.58 V
CC
0.58 V
CC
Rx, Ry Input threshold 0.5 V
CC
Input logic level low 0.42 V
CC
0.42 V
CC
(V
Sx
output low atInput/output logic 3 mA) –V
IOdiff
Sx, Sy 100 150 100 mVlevel difference
(5)
(V
Sx
input high max)for I
2
C applications
(1) Typical value is at V
CC
= 15 V, T
A
= 25 °C(2) See the Typical Characteristics section of this data sheet.(3) The output logic low depends on the sink current.(4) The input logic threshold is independent of the supply voltage.(5) The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for V
SX
output low always exceeds theminimum V
Sx
input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of anotherP82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices never should be linked,because the resulting system would be very susceptible to induced noise and would not support all I
2
C operating modes.
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Switching Characteristics
P82B96DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
Electrical Characteristics (continued)V
CC
= 15 V, voltages are specified with respect to GND (unless otherwise noted)
T
A
= 25 °C T
A
= –40 °C to 85 °CPARAMETER TEST CONDITIONS UNITMIN TYP
(1)
MAX MIN MAX
Sx, Sy are low, V
CCV
CC
voltage at
Sx, Sy ramping, voltage onV
IOrel
which all buses 1 1 VTx, Ty Tx, Ty lowered untilare released
releasedTemperature coefficient ofΔV/ ΔT
REL
–4 mV/ °Crelease voltageC
in
Input capacitance Rx, Ry 2.5 4 4 pF
V
CC
= 5 V, T
A
= 25 °C, no capacitive loads, voltages are specified with respect to GND (unless otherwise noted)
FROM TOPARAMETER TEST CONDITIONS TYP UNIT(INPUT) (OUTPUT)
R
Tx
pullup = 160 Ω,Buffer delay time on falling V
Sx
(or V
Sy
) = input switching V
Tx
(or V
Ty
) output fallingt
pzl
C
Tx
= 7 pF + board 70 nsinput
(1)
threshold 50% of V
LOAD
trace capacitance
R
Tx
pullup = 160 Ω,Buffer delay time on rising V
Sx
(or V
Sy
) = input switching V
Tx
(or V
Ty
) outputt
plz
C
Tx
= 7 pF + board 90 nsinput
(2)
threshold reaching 50% of V
LOAD
trace capacitance
R
Sx
pullup = 1500 Ω,Buffer delay time on falling V
Rx
(or V
Ry
) = input switching V
Sx
(or V
Sy
) output fallingt
pzl
C
Tx
= 7 pF + board 250 nsinput
(3)
threshold 50% of V
LOAD
trace capacitance
R
Sx
pullup = 1500 Ω,Buffer delay time on rising V
Rx
(or V
Ry
) = input switching V
Sx
(or V
Sy
) outputt
plz
C
Tx
= 7 pF + board 270 nsinput
(4)
threshold reaching 50% of V
LOAD
trace capacitance
(1) The fall time of V
Tx
from 5 V to 2.5 V in the test is approximately 15 ns.(2) The fall time of V
Sx
from 5 V to 2.5 V in the test is approximately 50 ns.(3) The rise time of V
Tx
from 0 V to 2.5 V in the test is approximately 20 ns.(4) The rise time of V
Sx
from 0.9 V to 2.5 V in the test is approximately 70 ns.
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TYPICAL CHARACTERISTICS
1200
400
1000
800
600
-50 100
75
50250–25 125
V – mV
OL
T – °C
j
Maximum
Typical
Minimum
600
800
1000
400
-50 100
75
50250–25 125
V – mV
OL
T – °C
j
Maximum
Typical
Minimum
1000
200
800
600
400
-50 100
75
50250–25 125
V – mV
IH(min)
T – °C
j
1000
200
800
600
400
-50 100
75
50250–25 125
V – mV
IL(max)
T – °C
j
600
1400
400
800
1000
1200
-50 100
75
50250–25 125
V – mV
CC(max)
T – °C
j
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
V
OL
AT Sx V
OL
AT Sxvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATUREI
OL
= 0.2 mA I
OL
= 3 mA
V
IL(max)
AT Sx V
IH(min)
AT Sxvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
V
CC(max)
vsJUNCTION TEMPERATURE
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PARAMETER MEASUREMENT INFORMATION
tPLZ/tPZL VCC
TEST S1
C = Probe and jig capacitance
(see Note A)
L
S1
GND
R = 160 to 1500
LW
VCC
Tx or Ty
PULSE
GENERATOR DUT
RT
VCC
VIN VOUT
tPLZ
tPZL
VCC
0 V
Sx or Sy
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
TEST CIRCUIT FOR OPEN-DRAIN OUTPUT
0.6 V
VCC
VOL
0.5 V´CC
P82B96DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
A. C
L
includes probe and jig capacitance.B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, Z
O
= 50 Ω, t
r
/t
f
≤30 ns.
Figure 1. Test Circuit and Voltage Waveforms
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APPLICATION INFORMATION
Typical Applications
5V
1/2 P82B96
I C
2
SDA
R1
Tx
(SDA)
Rx
(SDA)
R2
R3
VCC
VCC1
R4
R5
I C
2
SDA
SCL SCL
SDA
P82B96
Main Enclosure Remote-Control Enclosure
3.3–5 V
3.3–5 V
12 V 12 V
12 V
Long Cables
3.3–5 V
3.3–5 V
SDA
P82B96
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
Figure 2 through Figure 4 show typical applications for the P82B96.
Figure 2. Interfacing I
2
C Bus With Different Logic Levels
Figure 3. Galvanic Isolation of I
2
C Nodes
Figure 4. Long-Distance I
2
C Communications
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SCL SCL
SDA
P82B96
3-m to 20-m Cables
P82B96
V+V Cable Drive
VCC
I C/DDC
2
Master
GND
Sx
Sy
Rx
Tx
Ry
Ty
470 kW
4700 W
I C/DDC
2
Rx
Tx
Ty
Ry
VCC1
VCC2
Sx
Sy
I C/DDC
2
Slave
PC/TV Receiver/Decoder Box
Monitor/Flat TV
Video Signals
R
G
B
100 kW
100 nF
470 kW
+V Cable Drive
VCC
GND
BC
847B
BC
847B
SDA
P82B96DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
APPLICATION INFORMATION (continued)Figure 5 shows how a master I
2
C bus can be protected against short circuits or failures in applications thatinvolve plug/socket connections and long cables that may become damaged. A simple circuit is added tomonitor the SDA bus and, if its low time exceeds the design value, disconnect the master bus. P82B96 frees allof its I/Os if its supply is removed, so one option is to connect its V
CC
to the output of a logic gate from, forexample, the LVC family. The SDA and SCL lines could be timed, and V
CC
disabled via the gate, if a lineexceeds a design value of the low period. If the supply voltage of logic gates restricts the choice of V
CC
supply,the low-cost discrete circuit in Figure 5 can be used. If the SDA line is held low, the 100-nF capacitor charges,and Ry is pulled toward V
CC
. When it exceeds V
CC
/2, Ry sets Sy high, which effectively releases it.
Figure 5. Extending DCC Bus
In this example, the SCL line is made unidirectional by tying Rx to V
CC
. The state of the buffered SCL linecannot affect the master clock line, which is allowed when clock stretching is not required. It is simple to add anadditional transistor or diode to control the Rx input in the same way as Ry, when necessary. The +V cable drivecan be any voltage up to 15 V, and the bus may be run at a lower impedance by selecting pullup resistors for astatic sink current up to 30 mA. V
CC1
and V
CC2
may be chosen to suit the connected devices. Because DDCuses relatively low speeds (<100 kHz), the cable length is not restricted to 20 m by the I
2
C signaling, but it maybe limited by the video signaling.
Figure 6 and Table 1 show that P82B96 can achieve high clock rates over long cables. While calculating withlumped wiring capacitance yields reasonable approximations to actual timing; even 25 m of cable is bettertreated using transmission line theory. Flat ribbon cables connected as shown, with the bus signals on the outeredge, have a characteristic impedance in the range 100–200 Ω. For simplicity, they cannot be terminated in theircharacteristic impedance, but a practical compromise is to use the minimum pullup allowed for P82B96 andplace half this termination at each end of the cable. When each pullup is below 330 Ω, the rising-edgewaveforms have their first voltage step level above the logic threshold at Rx, and cable timing calculations canbe based on the fast rise/fall times of resistive loading, plus simple one-way propagation delays. When thepullup is larger, but below 750 Ω, the threshold at Rx is crossed after one signal reflection. So, at the sending
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SCL
SDA
P82B96
GND
SCL
SDA
P82B96
R1R1
R2R2 R2 R2
R1
R1
Cable
+V Cable Drive
Propagation
Delay = 5 ns/m
I C
MASTER
2I C
SLAVE(S)
2
C2 C2
VCC1
VCC
Rx
Tx
Ry
Ty
Sx
Sy
VCC
Rx
Tx
Ry
Ty
Sx
Sy
VCC2
GND
BAT54A BAT54A
C2 C2
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
APPLICATION INFORMATION (continued)end, it is crossed after two times the one-way propagation delay and, at the receiving end, after three times thatpropagation delay. For flat cables with partial plastic dielectric insulation (by using outer cores) the one-waypropagation delays are about 5 ns/m. The 10% to 90% rise and fall times on the cable are between 20 ns and50 ns, so their delay contributions are small. There is ringing on falling edges that can be damped, if required,using Schottky diodes, as shown.
Figure 6. Driving Ribbon or Flat Telephone Cables
Table 1. Bus Capabilities
MASTER SCL
BUS MAXIMUMPULSE+V CABLE CABLEV
CC1
V
CC2
R1 R2 C2 CABLE CLOCK SLAVEDURATIONCABLE LENGTH DELAY(V) (V) ( Ω) (k Ω) (pF) CAPACITANCE SPEED RESPONSE(ns)(V) (m) (ns)
(kHz) DELAYHIGH LOW
5 12 5 750 2.2 400 250
(1)
1250 600 4000 120
(2)
5 12 5 750 2.2 220 100
(1)
500 600 2600 185
(2)
3.3 5 3.3 330 1 220 25 1 nF 125 600 1500 390
(2)
3.3 5 3.3 330 1 100 3 120 pF 15 600 1000 500 600 ns
(1) Not applicable; calculations are delay based.(2) Normal 400-kHz bus specification
When the master SCL high and low periods can be programmed separately, the timings can allow for busdelays. The low period should be programmed to achieve the minimum 1300 ns plus the net delay in the slaveresponse data signal caused by bus and buffer delays. The longest data delay is the sum of the delay of thefalling edge of SCL from master to slave and the delay of the rising edge of SDA from slave data to master.Because the buffer stretches the programmed SCL low period, the actual SCL frequency is lower thancalculated from the programmed clock periods. In the example for the 25-m cable in Table 1 , the clock isstretched 400 ns, the falling edge of SCL is delayed 490 ns, and the SDA rising edge is delayed 570 ns. Therequired additional low period is (490 + 570) = 1060 ns and the I
2
C bus specifications already include anallowance for a worst-case bus rise time (0% to 70%) of 425 ns. The bus rise time can be 300 ns (30% to 70%),which means it can be 425 ns (0% to 70%). The 25-m cable delay times include all rise and fall times.Therefore, the device only needs to be programmed with an additional (1060 – 400 – 425) = 235 ns, making atotal programmed low period 1535 ns. The programmed low is stretched by 400 ns to yield an actual bus lowtime of 1935 ns, which, allowing the minimum high period of 600 ns, yields a cycle period of 2535 ns or 394 kHz.
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Calculating System Delays and Bus-Clock Frequency for Fast Mode System
MASTER
I C
2I C
2
SLAVE
P82B96 P82B96
SCL Rm Rb Rs
VCCS
SCL
Sx Tx/Rx Tx/Rx Sx
GND
Falling edge of SCL at master is delayed by the buffers and bus fall times.
Local Master Bus
V
CCB
EffectiveDelayofSCL atSlave=255+17V +(2.5+4 10 Cb)V (ns)
C=F,V=Volts
CCM CCB
×9
VCCM
Cb=BufferedBus
WiringCapacitance
Cm=MasterBus
Capacitance
Cs=SlaveBus
Capacitance
BufferedExpansionBus RemoteSlaveBus
MASTER
P82B96
VCCM
SCL Rm Rb
Sx Tx/Rx Tx/Rx
GND
VCCB
I C
2
Cb=BufferedBus
WiringCapacitance
Cm=MasterBus
Capacitance
RisingedgeofSCL atmasterisdelayed(clockstretch)bybufferandbusrisetimes.
EffectivedelayofSCL atmaster=270+RmCm+0.7RbCb(ns)
C=F,R= Ω
LocalMasterBus BufferedExpansionBus
P82B96DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
Note that, in both the 100-m and 250-m examples, the capacitive loading on the I
2
C buses at each end is withinthe maximum allowed Standard mode loading of 400 pF, but exceeds the Fast mode limit. This is an example ofa hybrid mode, because it relies on the response delays of Fast mode parts, but uses (allowable) Standardmode bus loadings with rise times that contribute significantly to the system delays. The cables cause largepropagation delays. Therefore, these systems must operate well below the 400-kHz limit, but illustrate how theystill can exceed the 100-kHz limit, provided all parts are capable of Fast mode operation. The fastest exampleillustrates how the 400-kHz limit can be exceeded, provided master and slave parts have delay specificationssmaller than the maximum allowed. Many TI slaves have delays shorter than 600 ns, but none have thatspecified.
Figure 7 through Figure 9 show the P82B96 used to drive extended bus wiring, with relatively large capacitance,linking two Fast mode I
2
C bus nodes. It includes simplified expressions for making the relevant timingcalculations for 3.3-/5-V operation. Because the buffers and the wiring introduce timing delays, it may benecessary to decrease the nominal SCL frequency below 400 kHz. In most cases, the actual bus frequency islower than the nominal master timing, due to bit-wise stretching of the clock periods.
Figure 7.
Figure 8.
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MASTER
P82B96 P82B96
SDA Rm Rb Rs SDA
Sx Tx/Rx Tx/Rx Sx
GND
I C
2
VCCS
Local Master Bus
VCCM
Cb=BufferedBus
WiringCapacitance
Cm=MasterBus
Capacitance
Cs=SlaveBus
Capacitance
BufferedExpansionBus RemoteSlaveBus
I C
2
SLAVE
VCCB
RisingedgeofSDA atslaveisdelayedbythebuffersandbusrisetimes.
EffectivedelayofSDA atmaster=270+0.2RsCs+0.7(RbCb+RmCm)(ns)
C=F,R= Ω
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
Figure 9.
The delay factors involved in calculation of the allowed bus speed are:1. The propagation delay of the master signal through the buffers and wiring to the slave. The importantdelay is that of the falling edge of SCL, because this edge requests the data or ACK from a slave.2. The effective stretching of the nominal low period of SCL at the master, caused by the buffer and bus risetimes.
3. The propagation delay of the slave response signal through the buffers and wiring back to the master.The important delay is that of a rising edge in the SDA signal. Rising edges always are slower and,therefore, are delayed by a longer time than falling edges. (The rising edges are limited by the passivepullup, while falling edges actively are driven.)
The timing requirement in any I
2
C system is that a slave’s data response (which is provided in response to afalling edge of SCL) must be received at the master before the end of the corresponding low period of SCL as itappears on the bus wiring at the master. Because all slaves, as a minimum, satisfy the worst-case timingrequirements of a 400-kHz part, they must provide their response within the minimum allowed clock low periodof 1300 ns. Therefore, in systems that introduce additional delays, it is necessary only to extend that minimumclock low period by any effective delay of the slave response. The effective delay of the slave's response equalsthe total delays in SCL falling edge from the master reaching the slave (A) minus the effective delay (stretch) ofthe SCL rising edge (B) plus total delays in the slave response data, carried on SDA, and reaching the master(C).
The master microcontroller should be programmed to produce a nominal SCL low periodof (1300 + A – B + C) ns and should be programmed to produce the nominal minimum SCL high period of600 ns. Then, a check should be made to ensure the cycle time is not shorter than the minimum 2500 ns. Iffound to be necessary, increase either clock period.
Due to clock stretching, the SCL cycle time always is longer than (600 + 1300 + A + C) ns.
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Sample Calculations
P82B96DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
The master bus has an RmCm product of 100 ns and V
CCM
= 5 V.
The buffered bus has a capacitance of 1 nF and a pullup resistor of 160 Ωto 5 V, giving an RbCb product of160 ns. The slave bus also has an RsCs product of 100 ns.
The master low period should be programmed to be ≥(1300 + 372.5 – 482 + 472) ns, which calculates to≥1662.5 ns.
The master high period may be programmed to the minimum 600 ns. The nominal master clock period is≥(1662.5 + 600) ns = 2262.5 ns, equivalent to a frequency of 442 kHz.
The actual bus-clock period, including the 482-ns clock stretch effect, is below(nominal + stretch) = (2262.5 + 482) ns or ≥2745 ns, equivalent to an allowable frequency of 364 kHz.
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PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
P82B96D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
P82B96DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
P82B96DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
P82B96DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
P82B96DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
P82B96DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
P82B96P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
P82B96PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
P82B96PW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
P82B96PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
P82B96PWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
P82B96PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
P82B96DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
P82B96DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
P82B96PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
P82B96DGKR VSSOP DGK 8 2500 358.0 335.0 35.0
P82B96DR SOIC D 8 2500 367.0 367.0 35.0
P82B96PWR TSSOP PW 8 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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