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Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
Cautions
Keep safety first in your circuit designs!
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Hitachi Single -Chip Microcompu ter
H8S/2199 Series
H8S/2199
HD6432199
H8S/2198
HD6432198
H8S/2197
HD6432197
H8S/2196
HD6432196
H8S/2199F-ZTAT™
HD64F2199
Hardwa re Manual
ADE-602-191
Rev 1.0
2/15/00
Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright , trademark, or other intellectual propert y rights for information c ontained in
this docum ent. Hitachi bears no responsibility for problems tha t may a rise with third party’s
rights, including intellectual property right s, in connection with use of the information
contained in this document.
2. Products and product specifications ma y be subject to change without notice. Confirm t hat you
have received t he latest product sta ndards or specifications before final design, purchase or
use.
3. Hitachi makes every a t tempt to ensure tha t its products are of high quality and reliability.
However, c ontact Hitachi’s sales office before using the product in an a pplication that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human l ife or cause risk of bodily i njury, such as aerospace, aeronautics, nuclear
power, combus tion cont rol , trans port at ion , traffic, safety equipmen t or medic al equip me nt for
life support.
4. Design your application so that the product is used wit hin the ra nges guarant eed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally fore seeable fai lure rates or failure modes in semiconductor devices and
employ systemic measures such a s fail-safe s, so t hat the equi pment incorpora ting Hitachi
product does not ca use bodily injury, fire or othe r consequential dama ge due t o operation of
the Hitachi product.
5. Thi s produc t is not designed t o be radiation resistant .
6. No one i s permitted to reproduce or duplicate, in any form, the whole or part of this document
without wri tten approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding t his doc ument or Hitachi
semiconductor products.
Rev. 1.0, 02/00, page i of 19
Contents
Section 1 Overview...................................................................................................... 1
1.1 Overview.....................................................................................................................1
1.2 Internal Block Diagram................................................................................................ 7
1.3 Pin Arrangement and Functions .................................................................................... 8
1.3.1 Pin Arrangement .......................................................................................... 8
1.3.2 Pin Functions................................................................................................ 9
Section 2 CPU ............................................................................................................... 17
2.1 Overview.....................................................................................................................17
2.1.1 Features........................................................................................................ 17
2.1.2 Differences bet ween H8S/2600 CPU and H8S/2000 CPU.............................. 18
2.1.3 Differences from H8/300 CPU...................................................................... 18
2.1.4 Differences from H8/300H CPU................................................................... 19
2.2 CPU Operating Modes................................................................................................. 20
2.3 Address Space.............................................................................................................. 25
2.4 Register Configuration................................................................................................. 26
2.4.1 Overview...................................................................................................... 26
2.4.2 General Registers ......................................................................................... 27
2.4.3 Control Registers.......................................................................................... 28
2.4.4 Initial Register Values .................................................................................. 29
2.5 Data Formats ............................................................................................................... 30
2.5.1 General Register Data Formats ..................................................................... 30
2.5.2 Memory Data Formats.................................................................................. 32
2.6 Instruction Set..............................................................................................................33
2.6.1 Overview...................................................................................................... 33
2.6.2 Instructions and Addressing Modes............................................................... 34
2.6.3 Table of Instructions Classified by Function.................................................. 35
2.6.4 Basic Instruction Formats ............................................................................. 45
2.6.5 Notes on Use of Bit-Manipulation Instructions.............................................. 46
2.7 Addressing Mod es and Effec tiv e Address Calculation .................................................. 47
2.7.1 Addressing Mode ......................................................................................... 47
2.7.2 Effective Address Calculation....................................................................... 50
2.8 Processing States.......................................................................................................... 54
2.8.1 Overview...................................................................................................... 54
2.8.2 Reset State.................................................................................................... 55
2.8.3 Exception-Ha ndling State............................................................................. 56
2.8.4 Program Execution State............................................................................... 57
2.8.5 Power-Down State........................................................................................ 58
2.9 Bas ic Timin g ............................................................................................................... 5 9
Rev. 1.0, 02/00, page ii of 19
2.9.1 Overview ..................................................................................................... 59
2.9.2 On-Chip Memory (ROM, RAM)................................................................... 59
2.9.3 On-Chip Supporting Module Access Timing................................................. 60
Section 3 MCU Operating Modes............................................................................ 61
3.1 Overview.....................................................................................................................61
3.1.1 Operating Mode Selection ............................................................................ 61
3.1.2 Register Configuration.................................................................................. 61
3.2 Register Descriptions................................................................................................... 62
3.2.1 Mode Control Register (MD CR)................................................................... 62
3.2.2 System Control Register (SYSCR)................................................................ 62
3.3 Operating Mode (Mode 1) ............................................................................................ 63
3.4 Address Map in Ea ch Operating Mode ......................................................................... 64
Section 4 Power-Down State..................................................................................... 67
4.1 Overview.....................................................................................................................67
4.1.1 Register Configuration.................................................................................. 71
4.2 Register Descriptions................................................................................................... 72
4.2.1 Standby Cont rol Registe r (SBYCR).............................................................. 72
4.2.2 Low-Power Control Register (LPWRCR)..................................................... 74
4.2.3 Timer Register A (TMA).............................................................................. 76
4.2.4 Module Stop Control Re gister (MSTPCR).................................................... 77
4.3 Medium-Speed Mode................................................................................................... 78
4.4 Sleep Mode .................................................................................................................. 79
4.4.1 Sleep Mode.................................................................................................. 79
4.4.2 Clearing Sleep Mode.................................................................................... 79
4.5 Module Stop Mode ...................................................................................................... 80
4.5.1 Module Stop Mode....................................................................................... 80
4.6 Standby Mode.............................................................................................................. 81
4.6.1 Standby Mode .............................................................................................. 81
4.6.2 Clearing Standby Mode ................................................................................ 81
4.6.3 Setting Oscillation Settling Time after Clearing Standby Mode ..................... 81
4.7 Watch Mode................................................................................................................ 83
4.7.1 Watch Mode................................................................................................. 83
4.7.2 Clearin g Watch Mode................................................................................... 83
4.8 Subsleep Mode ............................................................................................................ 84
4.8.1 Subsleep Mode............................................................................................. 84
4.8.2 Clearing Subsleep Mode............................................................................... 84
4.9 Subactive Mode........................................................................................................... 85
4.9.1 Subactive Mode............................................................................................ 85
4.9.2 Clearing Subactive Mode.............................................................................. 85
4.10 Dir e ct Tran sitio n.......................................................................................................... 86
4.10.1 Overview of Direct Transition ...................................................................... 86
Rev. 1.0, 02/00, page iii of 19
Section 5 Exception Handling................................................................................... 87
5.1 Overview.....................................................................................................................87
5.1.1 Exception Handling Types and Priority......................................................... 87
5.1.2 Exception Handling Operation...................................................................... 88
5.1.3 Exception Sources and Vector T a ble............................................................. 88
5.2 Reset ........................................................................................................................... 90
5.2.1 Overview...................................................................................................... 90
5.2.2 Reset Sequence............................................................................................. 90
5.2.3 Interrupts after Reset .................................................................................... 91
5.3 Interrupts..................................................................................................................... 92
5.4 Trap Instruction ........................................................................................................... 93
5.5 Stack Status after Exception Handling.......................................................................... 94
5.6 Notes on Use of the Stack ............................................................................................ 95
Section 6 Interr upt Controller...................................................................................... 97
6.1 Overview.....................................................................................................................97
6.1.1 Features........................................................................................................ 97
6.1.2 Block Diagram............................................................................................. 98
6.1.3 Pin Configuration......................................................................................... 99
6.1.4 Register Configuration.................................................................................. 99
6.2 Register Descriptions................................................................................................... 100
6.2.1 System Control Register (SYSCR) ................................................................ 100
6.2.2 Interrupt Control Regist e rs A to D (ICRA to ICRD)...................................... 101
6.2.3 IRQ Enable Register (IENR) ......................................................................... 102
6.2.4 IRQ Edge Select Registers (IEGR)................................................................ 103
6.2.5 IRQ Status Register (IRQR).......................................................................... 104
6.2.6 Port Mode Register (PMR1) ......................................................................... 105
6.3 Interrupt Sources.......................................................................................................... 106
6.3.1 External Interrup ts........................................................................................ 106
6.3.2 Internal Int e rrupts......................................................................................... 107
6.3.3 Interrupt Exception Vector Table.................................................................. 108
6.4 Interrupt Operation....................................................................................................... 111
6.4.1 Interrupt Control Modes and Interrupt Operation ........................................... 111
6.4.2 Interrupt Control Mode 0.............................................................................. 113
6.4.3 Interrupt Control Mode 1.............................................................................. 115
6.4.4 Interrupt Exception Handling Sequence ........................................................ 118
6.4.5 Interrupt Response Times ............................................................................. 119
6.5 Usage Notes................................................................................................................. 120
6.5.1 Contention between Interrupt Genera tion and Disa bling................................ 120
6.5.2 Instructions that Di sable Interrupts................................................................ 121
6. 5.3 Int errupts during Exec uti o n of EEPMOV Instr uction..................................... 121
Rev. 1.0, 02/00, page iv of 19
Section 7 ROM............................................................................................................. 123
7.1 Overview..................................................................................................................... 123
7.1.1 Block Diagram............................................................................................. 123
7.2 Overview of Flash Memory.......................................................................................... 124
7.2.1 Features........................................................................................................ 124
7.2.2 Block Diagram............................................................................................. 125
7.2.3 Flash Memory Operating Mode s................................................................... 126
7.2.4 Pin Configuration......................................................................................... 130
7.2.5 Register Configuration.................................................................................. 130
7.3 Flash Me mory Regi ster Descriptions............................................................................ 131
7.3.1 Flash Memory Control Register 1 (FLMCR1)............................................... 131
7.3.2 Flash Memory Control Register 2 (FLMCR2)............................................... 134
7.3.3 Erase Block Register 1 (EBR1)..................................................................... 137
7.3.4 Erase Block Register 2 (EBR2)..................................................................... 137
7.3.5 Serial/Timer Control Register (STCR).......................................................... 138
7.4 On-Board Programming Modes .................................................................................... 140
7.4.1 Boot Mode................................................................................................... 141
7.4.2 User Progra m Mode ..................................................................................... 146
7.5 Programming/Erasing Flash Mem ory........................................................................... 147
7.5.1 Program Mode (n= 1 when t he target addre ss range is H'00000 t o H'3FFFF
and n=2 when the target address range i s H'40000 to H'47FFF)..................... 147
7.5.2 Program-Veri fy Mode .................................................................................. 148
7.5.3 E ra se Mode (n = 1 whe n the target addre ss range is H'00000 to H' 3FFFF
and n = 2 when the targ et address range is H '4000 0 to H'47FFF) ................... 150
7.5.4 E ra se-Verify Mode (n = 1 when th e target addre ss range is H'00000 to H'3FFFF
and n = 2 when the targ et address range is H '4000 0 to H'47FFF) ................... 152
7.6 Flash Me mory Protection............................................................................................. 153
7.6.1 Hardware Protection..................................................................................... 153
7.6.2 Software Protection...................................................................................... 154
7.6.3 Error Prote ction............................................................................................ 155
7.7 Interrupt Handling whe n Progra mming/Erasing Fl ash Memory..................................... 156
7.8 Flash Me mory Wri ter Mode......................................................................................... 157
7.8.1 Writer Mode Setting..................................................................................... 157
7.8.2 Socket Adapters and Memory Map............................................................... 157
7.8.3 Writer Mode Operation................................................................................. 158
7.8.4 Memory Read Mode..................................................................................... 159
7.8.5 Auto-Program Mode..................................................................................... 162
7.8.6 Auto-Erase Mode ......................................................................................... 164
7.8.7 Status Read Mode......................................................................................... 165
7.8.8 Status Polling............................................................................................... 167
7.8.9 Writer Mode Transition Time ....................................................................... 168
7.8.10 Notes on Memory Programm i ng................................................................... 168
Rev. 1.0, 02/00, page v of 19
7.9 Notes whe n Converting the F–ZTAT Application Software to the Mask-ROM
Versions ...................................................................................................................... 169
Section 8 RAM............................................................................................................. 171
8.1 Overview..................................................................................................................... 171
8.1.1 Block Diagram............................................................................................. 171
Section 9 Clock Pulse Generator.............................................................................. 173
9.1 Overview..................................................................................................................... 173
9.1.1 Block Diagram............................................................................................. 173
9.1.2 Register Configuration.................................................................................. 173
9.2 Register Descriptions................................................................................................... 174
9.2.1 Standby Cont rol Registe r (SBYCR).............................................................. 174
9.2.2 Low-Power Control Register (LPWRCR) ..................................................... 175
9.3 Oscillator..................................................................................................................... 176
9.3.1 Connecting a Crystal Resonat or.................................................................... 176
9.3.2 External Clock Input..................................................................................... 178
9.4 Duty Adjustment Circuit .............................................................................................. 181
9.5 Medium-Speed Clock Divider...................................................................................... 181
9.6 Bus Master Clock Selection Circuit.............................................................................. 181
9.7 Subclock Oscillator Circuit .......................................................................................... 182
9.7.1 Connecting 32.768 kHz Crystal Re sonator.................................................... 182
9.7.2 When Subclock is not Needed ....................................................................... 183
9.8 Subclock Waveform Shapi ng Ci rc uit............................................................................ 183
9.9 No tes on the R esonator ................................................................................................ 183
Section 10 I/O Port ......................................................................................................... 185
10.1 Overview..................................................................................................................... 185
10.1.1 Port Functions .............................................................................................. 185
10.1.2 Port Input..................................................................................................... 185
10. 1. 3 MOS Pull-Up Tran sisto r s.............................................................................. 188
10.2 Port 0........................................................................................................................... 189
10.2.1 Overview...................................................................................................... 189
10.2.2 Regi ster Configuration.................................................................................. 190
10.2.3 Pin Functions................................................................................................ 191
10.2.4 Pin States ..................................................................................................... 191
10.3 Port 1........................................................................................................................... 192
10.3.1 Overview...................................................................................................... 192
10.3.2 Regi ster Configuration.................................................................................. 192
10.3.3 Pin Functions................................................................................................ 196
10.3.4 Pin States ..................................................................................................... 197
10.4 Port 2........................................................................................................................... 198
10.4.1 Overview...................................................................................................... 198
Rev. 1.0, 02/00, page vi of 19
10.4.2 Regi ster Configuration.................................................................................. 198
10.4.3 Pin Functions ............................................................................................... 201
10.4.4 Pin States ..................................................................................................... 203
10.5 Port 3........................................................................................................................... 204
10.5.1 Overview ..................................................................................................... 204
10.5.2 Regi ster Configuration.................................................................................. 204
10.5.3 Pin Functions ............................................................................................... 208
10.5.4 Pin States ..................................................................................................... 211
10.6 Port 4........................................................................................................................... 212
10.6.1 Overview ..................................................................................................... 212
10.6.2 Regi ster Configuration.................................................................................. 212
10.6.3 Pin Functions ............................................................................................... 215
10.6.4 Pin States ..................................................................................................... 217
10.7 Port 6........................................................................................................................... 218
10.7.1 Overview ..................................................................................................... 218
10.7.2 Regi ster Configuration.................................................................................. 219
10.7.3 Pin Functions ............................................................................................... 224
10.7.4 Operation..................................................................................................... 226
10.7.5 Pin States ..................................................................................................... 227
10.8 Port 7........................................................................................................................... 228
10.8.1 Overview ..................................................................................................... 228
10.8.2 Regi ster Configuration.................................................................................. 229
10.8.3 Pin Functions ............................................................................................... 234
10.8.4 Operation..................................................................................................... 235
10.8.5 Pin States ..................................................................................................... 236
10.9 Port 8........................................................................................................................... 237
10.9.1 Overview ..................................................................................................... 237
10.9.2 Regi ster Configuration.................................................................................. 238
10.9.3 Pin Functions ............................................................................................... 244
10.9.4 Pin States ..................................................................................................... 246
Section 11 Timer A........................................................................................................ 247
11.1 Overview..................................................................................................................... 247
11.1.1 Features........................................................................................................ 247
11.1.2 Block Diagram............................................................................................. 248
11.1.3 Regi ster Configuration.................................................................................. 248
11.2 Register Descriptions................................................................................................... 249
11.2.1 Timer Mode Register A (TMA).................................................................... 249
11.2.2 Timer Counter A (TCA)............................................................................... 251
11.2.3 Module Stop Control Register (MSTPCR).................................................... 251
11.3 Operation..................................................................................................................... 252
11.3.1 Operation as the Interval Timer ..................................................................... 252
11.3.2 Operation as Clock Timer............................................................................. 252
Rev. 1.0, 02/00, page vii of 19
11.3.3 Initializing the Count s ................................................................................... 252
Section 12 Timer B........................................................................................................ 253
12.1 Overview..................................................................................................................... 253
12.1.1 Features........................................................................................................ 253
12.1.2 Block Diagram............................................................................................. 253
12.1.3 Pin Configuration......................................................................................... 254
12.1.4 Regi ster Configuration.................................................................................. 254
12.2 Register Descriptions................................................................................................... 255
12.2.1 Timer Mode Register B (TMB)..................................................................... 255
12.2.2 Timer Counter B (TCB)................................................................................ 257
12.2.3 Timer Load Register B (TLB)....................................................................... 257
12.2.4 Port Mode Register A (PMRA)..................................................................... 258
12.2.5 Module Stop Control Register (MSTPCR) .................................................... 259
12.3 Operation..................................................................................................................... 260
12.3.1 Operation as the Interval Timer..................................................................... 260
12.3.2 Operation as the Auto Reload Timer............................................................. 260
12.3.3 Even t Coun ter .............................................................................................. 260
Section 13 Timer J ......................................................................................................... 261
13.1 Overview..................................................................................................................... 261
13.1.1 Features........................................................................................................ 261
13.1.2 Block Diagram............................................................................................. 261
13.1.3 Pin Configuration......................................................................................... 263
13.1.4 Regi ster Configuration.................................................................................. 263
13.2 Register Descriptions................................................................................................... 264
13.2.1 Timer Mode Register J (TMJ)....................................................................... 264
13.2.2 Timer J Control Register (TMJC).................................................................. 267
13. 2. 3 Timer J Statu s Register (T MJS) .................................................................... 270
13.2.4 Timer Counter J (TCJ).................................................................................. 271
13.2.5 Timer Counter K (TCK) ............................................................................... 271
13.2.6 Timer Load Register J (TLJ)......................................................................... 272
13.2.7 Timer Load Register K (TLK) ...................................................................... 272
13.2.8 Module Stop Control Register (MSTPCR) .................................................... 273
13.3 Operation..................................................................................................................... 274
13.3.1 8-bit Reload Timer (TMJ-1).......................................................................... 274
13.3.2 8-bit Reload Timer (TMJ-2).......................................................................... 274
13.3.3 Remote Controlled Data Transmission.......................................................... 275
13.3.4 TM J-2 Expans io n Functio n........................................................................... 278
Section 14 Timer L ........................................................................................................ 279
14.1 Overview..................................................................................................................... 279
14.1.1 Features........................................................................................................ 279
Rev. 1.0, 02/00, page viii of 19
14.1.2 Block Diagram............................................................................................. 280
14.1.3 Regi ster Configuration.................................................................................. 281
14.2 Register Descriptions................................................................................................... 282
14.2.1 Timer L Mode Register (LMR)..................................................................... 282
14.2.2 Li near Ti me Count er (LTC).......................................................................... 284
14.2.3 Reload/Compare Match Register (RCR) ....................................................... 284
14.2.4 Module Stop Control Register (MSTPCR).................................................... 285
14.3 Operation..................................................................................................................... 286
14.3.1 Compare Match Clear Operation................................................................... 286
Section 15 Timer R........................................................................................................ 289
15.1 Overview..................................................................................................................... 289
15.1.1 Features........................................................................................................ 289
15.1.2 Block Diagram............................................................................................. 289
15.1.3 Pin Configuration......................................................................................... 291
15.1.4 Regi ster Configuration.................................................................................. 291
15.2 Register Descriptions................................................................................................... 292
15.2.1 Timer R Mode Register 1 (TMRM1)............................................................. 292
15.2.2 Timer R Mode Register 2 (TMRM2)............................................................. 294
15.2.3 Timer R Control/Status Register (TMRCS)................................................... 297
15.2.4 Timer R Capture Register 1 (TMRCP1)........................................................ 299
15.2.5 Timer R Capture Register 2 (TMRCP2)........................................................ 300
15.2.6 Timer R Load Register 1 (TMRL1)............................................................... 300
15.2.7 Timer R Load Register 2 (TMRL2)............................................................... 301
15.2.8 Timer R Load Register 3 (TMRL3)............................................................... 301
15.2.9 Module Stop Control Register (MSTPCR).................................................... 302
15.3 Operation..................................................................................................................... 303
15.3.1 Rel oad Timer Counter Equipped with Capturing Function TMRU-1.............. 303
15.3.2 Rel oad Timer Counter Equipped with Capturing Function TMRU-2.............. 304
15.3.3 Rel oad Counter Timer TMRU-3 ................................................................... 304
15.3.4 M o d e I d entif icatio n...................................................................................... 305
15.3.5 Reeling Controls........................................................................................... 305
15.3.6 Acceleration and Braking Processes of the Capstan Motor............................. 305
15.3.7 Slow Tracking Mono-Multi Function............................................................ 306
15.4 Interrupt Cause ............................................................................................................ 308
15.5 Settings for Respective Functions ................................................................................. 309
15.5.1 M o d e I d entif icatio n...................................................................................... 309
15.5.2 Reeling Controls........................................................................................... 310
15.5.3 Slow Tracking Mono-Multi Function............................................................ 310
15.5.4 Acceleration and Braking Processes of the Capstan Motor............................. 311
Section 16 Timer X1...................................................................................................... 313
16.1 Overview..................................................................................................................... 313
Rev. 1.0, 02/00, page ix of 19
16.1.1 Features........................................................................................................ 313
16.1.2 Block Diagram............................................................................................. 314
16.1.3 Pin Configuration......................................................................................... 315
16.1.4 Regi ster Configuration.................................................................................. 316
16.2 Register Descriptions................................................................................................... 317
16.2.1 Free Running Counte r (FRC)........................................................................ 317
16.2.2 Output Comparing Registe rs A and B (OCRA and OCRB)............................ 318
16.2.3 Input Capture Registers A Through D (ICRA T hrough ICRD)....................... 319
16.2.4 Timer Interrupt Enabling Register (TIER)..................................................... 321
16.2.5 Timer Control/Status Register X (TCSRX) ................................................... 324
16.2.6 Timer Control Register X (TCRX)................................................................ 328
16.2.7 Timer Output Comparing Control Register (TOCR)...................................... 330
16.2.8 Module Stop Control Register (MSTPCR) .................................................... 332
16.3 Operation..................................................................................................................... 333
16.3.1 Operation of Timer X1 ................................................................................. 333
16.3.2 Counting Timing of the FRC ........................................................................ 334
16.3.3 Output Comparing Signal Outputting Timing................................................ 335
16.3.4 FRC Clearing Timing................................................................................... 335
16.3.5 Input Capture Signal Inputting Timing.......................................................... 336
16.3.6 Input Capture Flag (ICFA t hrough ICFD) Setting Up Timing........................ 337
16.3.7 Output Comparing Flag (OCFA and OCFB) Setting Up Timing.................... 338
16.3.8 Overflow Flag (CVF) Setting Up Timing...................................................... 338
16.4 Op er ation Mode of Timer X1....................................................................................... 339
16.5 Interrupt Causes........................................................................................................... 340
16.6 Exempl ar y Uses of Timer X1....................................................................................... 34 1
16.7 Precautions when Using Timer X1 ............................................................................... 342
16.7.1 Competition between Writing and Clearing with the FRC ............................. 342
16.7.2 Competition betw een Writing and Coun ting Up with the FRC....................... 343
16.7.3 Competition between Wr iting an d C o mpar in g Match wit h th e OCR.............. 344
16.7.4 Changing Over the Internal Clocks and Counter Operations .......................... 345
Section 17 Watchdog Timer (WDT).......................................................................... 347
17.1 Overview..................................................................................................................... 347
17.1.1 Features........................................................................................................ 347
17.1.2 Block Diagram............................................................................................. 348
17.1.3 Regi ster Configuration.................................................................................. 349
17.2 Register Descriptions................................................................................................... 350
17.2.1 Watchdog Timer Count er (W TCNT)............................................................. 350
17.2.2 Watchdog Timer Control/Status Register (WTCSR)...................................... 350
17.2.3 System Control Register (SYSCR)................................................................ 353
17.2.4 N o tes o n R e gister Access.............................................................................. 354
17.3 Operation..................................................................................................................... 355
17.3.1 Wa tch dog Timer Opera tion........................................................................... 355
Rev. 1.0, 02/00, page x of 19
17.3.2 Interval Timer Operat io n.............................................................................. 356
17. 3. 3 Timing of Setting of Overflow Fla g (OVF) ................................................... 357
17.4 Interrupts..................................................................................................................... 358
17.5 Usage Notes................................................................................................................. 358
17.5.1 Contention betwee n Watch dog Timer Counter (WTCN T)
Write and Increment..................................................................................... 358
17.5.2 Changing Value of CKS2 to CKS0 ............................................................... 359
17.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode............ 359
Section 18 8-Bit PWM.................................................................................................. 361
18.1 Overview..................................................................................................................... 361
18.1.1 Features........................................................................................................ 361
18.1.2 Block Diagram............................................................................................. 361
18.1.3 Pin Configuration......................................................................................... 362
18.1.4 Regi ster Configuration.................................................................................. 362
18.2 Register Descriptions................................................................................................... 363
18.2.1 8-bit PWM Data Registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3)....... 363
18.2.2 8-bit PWM Control Re gister (PW8CR)......................................................... 364
18.2.3 Port Mode Register 3 (PMR3) ...................................................................... 365
18.2.4 Module Stop Control Register (MSTPCR).................................................... 366
18.3 8-Bi t PWM Ope ration.................................................................................................. 367
Section 19 12-Bit PWM................................................................................................ 369
19.1 Overview..................................................................................................................... 369
19.1.1 Features........................................................................................................ 369
19.1.2 Block Diagram............................................................................................. 370
19.1.3 Pin Configuration......................................................................................... 371
19.1.4 Regi ster Configuration.................................................................................. 371
19.2 Register Descriptions................................................................................................... 372
19.2.1 12-Bit PWM Control Re gisters (CPWCR, DPW CR)..................................... 372
19.2.2 12-Bit PWM Da ta Registers (DPWDR, CPWDR)......................................... 375
19.3 Operation..................................................................................................................... 376
19.3.1 O u tp u t Wavef o rm......................................................................................... 376
Section 20 14-Bit PWM................................................................................................ 379
20.1 Overview..................................................................................................................... 379
20.1.1 Features........................................................................................................ 379
20.1.2 Block Diagram............................................................................................. 380
20.1.3 Pin Configuration......................................................................................... 380
20.1.4 Regi ster Configuration.................................................................................. 381
20.2 Register Descriptions................................................................................................... 382
20.2.1 PWM Control Register (PWCR)................................................................... 382
20.2.2 PWM Data Registers U and L (PWDRU, PWDRL)....................................... 383
Rev. 1.0, 02/00, page xi of 19
20.2.3 Module Stop Control Register (MSTPCR) .................................................... 384
20.3 14-Bit PWM Operation................................................................................................ 385
Section 21 Pr escal ar Unit.............................................................................................. 387
21.1 Overview..................................................................................................................... 387
21.1.1 Features........................................................................................................ 387
21.1.2 Block Diagram............................................................................................. 388
21.1.3 Pin Configuration......................................................................................... 389
21.1.4 Regi ster Configuration.................................................................................. 389
21.2 Registers...................................................................................................................... 390
21.2.1 Input Capture Register 1 (ICR1) ................................................................... 390
21.2.2 Prescalar Unit Control/ Status Register (PCSR) .............................................. 390
21.2.3 Port Mode Register 1 (PMR1)....................................................................... 393
21.3 No ise Cancel C i rcui t.................................................................................................... 394
21.4 Operation..................................................................................................................... 394
21. 4. 1 Prescala r S (PSS).......................................................................................... 394
21.4.2 P r escalar W (P SW)....................................................................................... 395
21.4.3 Stable Oscillation Wait Time Count.............................................................. 395
21.4.4 8-bit PWM ................................................................................................... 396
21.4.5 8-bit Input Ca pture Using
,&
Pin................................................................... 396
21.4.6 Frequency Division Clock Output................................................................. 396
Section 22 Seri al Com municat ion Interf ace 1 (SCI 1)............................................ 397
22.1 Overview..................................................................................................................... 397
22.1.1 Features........................................................................................................ 397
22.1.2 Block Diagram............................................................................................. 399
22.1.3 Pin Configuration......................................................................................... 400
22.1.4 Regi ster Configuration.................................................................................. 400
22.2 Register Descriptions................................................................................................... 401
22.2.1 Receive Shift Register 1 (RSR1)................................................................... 401
22.2.2 Receive Data Register 1 (RDR1) ................................................................... 401
22.2.3 Transmit Shift Register 1 (TSR1).................................................................. 402
22.2.4 Transmit Data Register 1 (TDR1) ................................................................. 402
22.2.5 Serial Mode Register 1 (SMR1).................................................................... 403
22.2.6 Serial Control Regist er 1 (SCR1).................................................................. 406
22.2.7 Serial Status Register 1 (SSR1)..................................................................... 410
22.2.8 Bit Rate Regi ster 1 (BRR1)........................................................................... 413
22.2.9 Serial Interface Mode Register 1 (SCMR1)................................................... 420
22.2.10 Module Stop Control Re gister (MSTPCR) .................................................... 421
22.3 Operation..................................................................................................................... 422
22.3.1 Overview...................................................................................................... 422
22.3.2 Operation in Asynchronous Mode................................................................. 424
22.3.3 Multiprocessor Com munication Fu nc tion...................................................... 434
Rev. 1.0, 02/00, page xii of 19
22.3.4 Operation in Sync hronous Mode................................................................... 442
22.4 SCI Interrupts.............................................................................................................. 450
22.5 Usage Notes................................................................................................................. 451
Section 23 I2C Bus Int erf ace (IIC)............................................................................. 459
23.1 Overview..................................................................................................................... 459
23.1.1 Features........................................................................................................ 459
23.1.2 Block Diagram............................................................................................. 460
23.1.3 Pin Configuration......................................................................................... 461
23.1.4 Regi ster Configuration.................................................................................. 462
23.2 Register Descriptions................................................................................................... 463
23.2.1 I2C Bus Data Register (ICDR)....................................................................... 463
23.2.2 Slave Address Register (SAR)...................................................................... 466
23.2.3 Second Slave Address Register (SARX) ....................................................... 468
23.2.4 I2C Bus Mode Regi ster (ICMR) .................................................................... 469
23.2.5 I2C Bus Control Registe r (ICCR) .................................................................. 473
23.2.6 I2C Bus Status Re gister (ICSR)..................................................................... 480
23.2.7 Serial/Timer Control Register (STCR).......................................................... 484
23.2.8 DDC Switch Register (DDCSWR)................................................................ 485
23.2.9 Module Stop Control Register (MSTPCR).................................................... 488
23.3 Operation..................................................................................................................... 489
23.3.1 I2C Bus Data Format..................................................................................... 489
23.3.2 Master Transmit Operation........................................................................... 490
23.3.3 Master Receive Operation............................................................................. 494
23.3.4 Slave Receive Operation ............................................................................... 496
23.3.5 Slav e Transmi t Opera tion ............................................................................. 499
23.3.6 IRIC Setting Timing and SCL Control.......................................................... 500
23.3.7 Automatic Switching from Formatless Transfer to I2C
Bus Format Transfer..................................................................................... 502
23.3.8 N o ise Can c eler............................................................................................. 503
23.3.9 Sample Flowcharts....................................................................................... 503
23.3.10 Initializing Internal Status ............................................................................. 507
23.4 Usage Notes................................................................................................................. 509
Section 24 A/D Converter............................................................................................ 513
24.1 Overview..................................................................................................................... 513
24.1.1 Features........................................................................................................ 513
24.1.2 Block Diagram............................................................................................. 514
24.1.3 Pin Configuration......................................................................................... 515
24.1.4 Regi ster Configuration.................................................................................. 516
24.2 Register Descriptions................................................................................................... 517
24.2.1 Software-Triggered A/D Result Register (ADR) ........................................... 517
24.2.2 Hardware-Triggered A/D Result Register (AHR).......................................... 517
Rev. 1.0, 02/00, page xiii of 19
24.2.3 A/D Control Register (ADCR)...................................................................... 518
24.2.4 A/D Control/Status Register (ADCSR) ......................................................... 521
24.2.5 Trigger Select Register (ADTSR) ................................................................. 524
24.2.6 Port Mode Register 0 (PMR0)....................................................................... 524
24.2.7 Module Stop Control Register (MSTPCR) .................................................... 525
24.3 Interface to Bus Master ................................................................................................ 526
24.4 Operation..................................................................................................................... 527
24.4.1 Software-Triggered A/D Conversion ............................................................. 527
24.4.2 Hardware- or Extern al-Tri gger ed A/D Conversion ........................................ 528
24.5 Interrupt Sources.......................................................................................................... 529
Section 25 Address Trap Controller (AT C).............................................................. 531
25.1 Overview..................................................................................................................... 531
25.1.1 Features........................................................................................................ 531
25.1.2 Block Diagram............................................................................................. 531
25.1.3 Regi ster Configuration.................................................................................. 532
25.2 Register Descriptions................................................................................................... 532
25.2.1 Address Trap Cont rol Regi ster (AT CR) ........................................................ 532
25.2.2 Trap Address Register 2 to 0 (TAR2 to TAR0).............................................. 534
25.3 Pr ecauti o n s in Usage.................................................................................................... 535
25.3.1 Basic Operations .......................................................................................... 535
25.3.2 Enabling....................................................................................................... 537
25.3.3 Bcc Instruction............................................................................................. 537
25.3.4 BSR Instruction............................................................................................ 541
25.3.5 JSR Instruction............................................................................................. 542
25. 3. 6 JMP Inst r uct ion ............................................................................................ 544
25.3.7 RTS Instruction............................................................................................ 545
25.3.8 SLEEP Instruction........................................................................................ 546
25.3.9 Competing Interrupt ..................................................................................... 550
Section 26 Servo Circuits............................................................................................. 555
26.1 Overview..................................................................................................................... 555
26.1.1 Functions...................................................................................................... 555
26.1.2 Block Diagram............................................................................................. 556
26.2 Servo Port.................................................................................................................... 557
26.2.1 Overview...................................................................................................... 557
26.2.2 Block Diagram............................................................................................. 557
26.2.3 Pin Configuration......................................................................................... 560
26.2.4 Regi ster Configuration.................................................................................. 561
26.2.5 Register Description..................................................................................... 561
26.2.6 DFG/DPG Input Signals............................................................................... 565
26.3 Reference Signal Generators ........................................................................................ 566
26.3.1 Overview...................................................................................................... 566
Rev. 1.0, 02/00, page xiv of 19
26.3.2 Block Diagram............................................................................................. 566
26.3.3 Regi ster Configuration.................................................................................. 568
26.3.4 Register Description..................................................................................... 569
26.3.5 Operation..................................................................................................... 574
26.4 HSW (Head-switch) Timing Generator ......................................................................... 589
26.4.1 Overview ..................................................................................................... 589
26.4.2 Block Diagram............................................................................................. 589
26.4.3 HSW Timing Generator Configuration.......................................................... 591
26.4.4 Regi ster Configuration.................................................................................. 592
26.4.5 Register Description..................................................................................... 592
26.4.6 Operation..................................................................................................... 606
26.4.7 Interrupts...................................................................................................... 612
26.4.8 Cautions....................................................................................................... 613
26.5 High-Speed Switching Circuit for Four-Head Special Playback .................................... 614
26.5.1 Overview ..................................................................................................... 614
26.5.2 Block Diagram............................................................................................. 614
26.5.3 Pin Configuration......................................................................................... 615
26.5.4 Register Description..................................................................................... 615
26.6 Drum Speed Error Detector.......................................................................................... 618
26.6.1 Overview ..................................................................................................... 618
26.6.2 Block Diagram............................................................................................. 618
26.6.3 Regi ster Configuration.................................................................................. 620
26.6.4 Register Description..................................................................................... 621
26.6.5 Operation..................................................................................................... 626
26.6.6 fH Correction i n Trick Play Mode.................................................................. 628
26.7 Drum Phase Error Detector .......................................................................................... 629
26.7.1 Overview ..................................................................................................... 629
26.7.2 Block Diagram............................................................................................. 630
26.7.3 Regi ster Configuration.................................................................................. 631
26.7.4 Register Description..................................................................................... 632
26.7.5 Operation..................................................................................................... 635
26.7.6 P h ase Com p a riso n........................................................................................ 637
26.8 Ca pstan Speed E rror Detector ...................................................................................... 638
26.8.1 Overview ..................................................................................................... 638
26.8.2 Block Diagram............................................................................................. 639
26.8.3 Regi ster Configuration.................................................................................. 640
26.8.4 Register Description..................................................................................... 641
26.8.5 Operation..................................................................................................... 646
26.9 Ca pstan Phase Error Detector....................................................................................... 648
26.9.1 Overview ..................................................................................................... 648
26.9.2 Block Diagram............................................................................................. 648
26.9.3 Regi ster Configuration.................................................................................. 650
26.9.4 Register Description..................................................................................... 651
Rev. 1.0, 02/00, page xv of 19
26.9.5 Operation..................................................................................................... 654
26.10 X-Value and Tracking Adjustment Circuit.................................................................... 656
26.10.1 Overview...................................................................................................... 656
26.10.2 Block Diagram............................................................................................. 656
26.10.3 Register Description..................................................................................... 658
26.11 Digital Filters............................................................................................................... 661
26.11.1 Overview...................................................................................................... 661
26.11.2 Block Diagram............................................................................................. 662
26.11.3 Arithmetic Buffer......................................................................................... 664
26.11.4 Register Configuration.................................................................................. 665
26.11.5 Register Description..................................................................................... 666
26.1 1.6 Filt er C h arac teristics..................................................................................... 674
26.11.7 Operations in Case of Transient Response..................................................... 676
26.11.8 Initialization of Z-1 ........................................................................................ 676
26.12 Additional V Signal Generator..................................................................................... 678
26.12.1 Overview...................................................................................................... 678
26.12.2 Pin Configuration......................................................................................... 679
26.12.3 Register Configuration.................................................................................. 679
26.12.4 Register Description..................................................................................... 679
26.12.5 Additional V Pulse Signal............................................................................. 681
26.13 CTL Circuit ................................................................................................................. 684
26.13.1 Overview...................................................................................................... 684
26.13.2 Block Diagram............................................................................................. 685
26.13.3 Pin Configuration......................................................................................... 686
26.13.4 Register Configuration.................................................................................. 686
26.13.5 Register Description..................................................................................... 687
26.13.6 Operation..................................................................................................... 701
26.13.7 CTL Input Section........................................................................................ 704
26.13.8 Duty Discriminator....................................................................................... 707
26.13.9 CTL Output Section...................................................................................... 713
26.13.10 Trapezoid Waveform Circuit......................................................................... 716
26.13.11 Note on CTL Interrupt.................................................................................. 717
26.14 Frequency Dividers...................................................................................................... 718
26.14.1 Overview...................................................................................................... 718
26.14.2 CTL Frequency Divider................................................................................ 718
26.14.3 CFG Frequency Divider ................................................................................ 722
26. 1 4.4 DFG Noise R emo val Circ uit......................................................................... 731
26.15 Sync Signal Detector.................................................................................................... 733
26.15.1 Overview...................................................................................................... 733
26.15.2 Block Diagram............................................................................................. 734
26.15.3 Pin Configuration......................................................................................... 735
26.15.4 Register Configuration.................................................................................. 735
26.15.5 Register Description..................................................................................... 736
Rev. 1.0, 02/00, page xvi of 19
26.15.6 Noise Detection............................................................................................ 744
26.15.7 Activation of the Sync Signal Detector.......................................................... 747
26.16 Servo Interrupt............................................................................................................. 748
26.16.1 Overview ..................................................................................................... 748
26.16.2 Register Configuration.................................................................................. 748
26.16.3 Register Description..................................................................................... 748
Section 27 Sync Separator for OSD and Data Slicer.............................................. 757
27.1 Overview..................................................................................................................... 757
27.1.1 Features........................................................................................................ 758
27.1.2 Block Diagram............................................................................................. 758
27.1.3 Pin Configuration......................................................................................... 760
27.1.4 Regi ster Configuration.................................................................................. 760
27.2 Register Description..................................................................................................... 761
27.2.1 Sync Separation Input Mode Registe r (SEPIMR).......................................... 761
27.2.2 Sync Separation Control Register (SEPCR)................................................... 765
27.2.3 Sync Separation AFC Control Register (SEPACR) ....................................... 768
27.2.4 Horizontal Sync Signal Threshold Register (HVTHR) ................................... 770
27.2.5 Vertical Sync Signal Threshold Register (VVTHR)....................................... 773
27.2.6 Field Detection Window Register (FWIDR).................................................. 775
27.2.7 H Complement and Mask Timing Register (HCMMR).................................. 777
27.2.8 Noise Detection Counter (NDETC) ............................................................... 779
27.2.9 Noise Detection Level Register (NDETR)..................................................... 780
27.2.10 Data Slicer Detection Window Register (DDETWR)..................................... 781
27.2.11 Internal Sync Frequency Register (INFRQR)................................................ 783
27.3 Operation..................................................................................................................... 784
27.3.1 Selecting Source Signals for Sync Separation ................................................ 784
27.3.2 Vsync Separation.......................................................................................... 790
27.3.3 Hsync Separation.......................................................................................... 791
27.3.4 Field Detection............................................................................................. 792
27.3.5 Noise Detection............................................................................................ 792
27.3.6 Automatic Frequenc y Controll er (AFC)........................................................ 793
27.3.7 Module Stop Control Register (MSTPCR).................................................... 797
Section 28 Data Slicer................................................................................................... 799
28.1 Overview..................................................................................................................... 799
28.1.1 Features........................................................................................................ 799
28.1.2 Block Diagram............................................................................................. 800
28.1.3 Pin Configuration......................................................................................... 801
28.1.4 Regi ster Configuration.................................................................................. 802
28.1.5 Data Slicer Use Conditions........................................................................... 802
28.2 Register Description..................................................................................................... 803
28.2.1 Slice Even- (Odd-) Field Mode Re gi ster (SEVFD, SODFD).......................... 803
Rev. 1.0, 02/00, page xvii of 19
28.2.2 Slice Line Setting Registers 1 to 4 (SLINE1 to SLINE4)............................... 807
28.2.3 Slice Detection Registers 1 to 4 (SDTCT1 to SDTCT4)................................. 808
28. 2. 4 Sli ce Data Regist ers 1 to 4 (SDATA1 to SDATA4)....................................... 811
28.2.5 Module Stop Control Register (MSTPCR) .................................................... 812
28.2.6 Monitor Output Setting Register (DOUT) ..................................................... 813
28.3 Operation..................................................................................................................... 814
28.3.1 Slice Line Specif ication................................................................................ 814
28.3.2 Slice Sequence ............................................................................................. 817
Section 29 On-Scr een Display (OSD) ....................................................................... 819
29.1 Overview..................................................................................................................... 819
29.1.1 Features........................................................................................................ 819
29.1.2 Block Diagram............................................................................................. 821
29.1.3 Pin Configuration......................................................................................... 822
29.1.4 Regi ster Configuration.................................................................................. 823
29.1.5 TV Formats and Display Modes.................................................................... 824
29.2 Description of Display Functions.................................................................................. 824
29.2.1 Superimposed Mode and Text Display Mode................................................ 824
29.2.2 Character Configuration................................................................................ 825
29.2.3 On-Screen Di splay Configuration ................................................................. 826
29.3 Settings in C h ara cter Un its........................................................................................... 827
29.3.1 Character Configuration................................................................................ 827
29.3.2 Character Colors........................................................................................... 827
29.3.3 Halftones/Cursors......................................................................................... 828
29.3.4 Blinking....................................................................................................... 829
29.3.5 Button Display ............................................................................................. 830
29. 3. 6 Cha racter Data ROM (OSDR OM) ................................................................ 831
29. 3. 7 Displa y Data RAM (OSDRAM) ................................................................... 833
29.4 Settings in R o w Units................................................................................................... 838
29.4.1 Button Patterns............................................................................................. 838
29.4.2 D is p lay Enlargemen t .................................................................................... 838
29.4.3 Character Brightness..................................................................................... 838
29.4.4 Cursor Color, Brightne ss, Halftone Levels .................................................... 838
29.4.5 Row Registers (CLINEn, n = rows 1 to 12)................................................... 840
29.5 Settings in Screen Units ............................................................................................... 845
29.5.1 Display Positions.......................................................................................... 845
29.5.2 T urning the OSD Di splay On and Off ........................................................... 846
29.5.3 Display Method............................................................................................ 846
29.5.4 Blinking Period ............................................................................................ 846
29.5.5 Borders ........................................................................................................ 847
29.5.6 Bac kground Color and Brightness................................................................. 847
29.5.7 Character, Cursor, and Background Chroma Saturation................................. 847
29. 5. 8 Displa y Positi o n Registe r s (HPOS and VPOS).............................................. 848
Rev. 1.0, 02/00, page xviii of 19
29.5.9 Screen Control Register (DCNTL)................................................................ 850
29.6 Other Settings.............................................................................................................. 855
29.6.1 TV Format ................................................................................................... 855
29.6.2 Display Data RAM Control .......................................................................... 855
29. 6. 3 Timing of OSD Displa y Updates Usi ng Regi ste r Rewri tin g........................... 855
29.6.4 4fsc/2fsc....................................................................................................... 855
29.6.5 OSDV Int errupts .......................................................................................... 855
29. 6. 6 OSD Form at Registe r ( DFOR M) .................................................................. 856
29.7 Digital Output.............................................................................................................. 860
29.7.1 R, G, and B Outputs ..................................................................................... 860
29.7.2 YCO and YBO Outputs................................................................................ 863
29.7.3 Digital Output Specification Register (DOUT).............................................. 864
29.7.4 Module Stop Control Register (MT STPCR).................................................. 866
29.8 Notes on OSD Font Creation........................................................................................ 868
29.8.1 Note 1 on Font Creation (Font Width) ........................................................... 868
29.8.2 Note 2 on Font Creation (Borders)................................................................ 868
29.8.3 Note 3 on Font Creation (Blinking)............................................................... 870
29.8.4 Note 4 on Font Creation (Buttons) ................................................................ 871
29. 9 OSD Osc i ll at or, AFC, and Dot Cloc k........................................................................... 872
29.9.1 Sync Signals ................................................................................................ 872
29.9.2 AFC Circuit.................................................................................................. 872
29.9.3 Dot Clock..................................................................................................... 872
29.9.4 4/2fsc........................................................................................................... 873
29. 1 0 OSD Ope r at i on in CPU Operati on Modes..................................................................... 875
29. 1 1 Ch a rac te r Data ROM (OSDR OM) Acce ss by CPU....................................................... 876
29.1 1.1 Seri al Timer Co n tr ol Register (S TC R ).......................................................... 876
Section 30 Electrical Char act er isti cs.......................................................................... 877
30.1 Absolute Maximum Ratings......................................................................................... 877
30.2 E l ectrical Characteristics of HD6432199, HD6432198, HD6432197, and
HD6432196................................................................................................................. 878
30.2.1 DC Characteristics of HD6432199, HD6432198, HD6432197,
and HD6432196 ........................................................................................... 878
30.2.2 Allowable Output Current s of HD6432199, HD6432198, HD6432197,
and HD6432196 ........................................................................................... 885
30.2.3 AC Characteristics of HD6432199, HD6432198, HD6432197,
and HD6432196 ........................................................................................... 886
30.2.4 Serial Interface Timing of HD6432199, HD6432198, HD6432197,
and HD6432196 ........................................................................................... 889
30.2.5 A/D Converter Characte ristics of HD6432199, HD6432198, HD6432197,
and HD6432196 ........................................................................................... 893
30.2.6 Servo Section E l ectrical Characteristics of HD6432199, HD6432198,
HD6432197, and HD643219 6....................................................................... 894
Rev. 1.0, 02/00, page xix of 19
30.2.7 OSD E lectrical Characteristics of HD6432199, HD6432198, HD6432197,
and HD6432196 ........................................................................................... 896
30.3 Electrical Characteristics of HD64F2199...................................................................... 900
30.3.1 DC Characteristics of HD64F2199................................................................ 900
30.3.2 Allowable Output Currents of HD64F2199................................................... 907
30.3.3 AC Characteristics of HD64F2199................................................................ 908
30.3.4 Serial Interface Ti ming of HD64F2199......................................................... 911
30.3.5 A/D Converter Charac teristics of HD64F2199 .............................................. 915
30.3.6 Servo Section E l ectrical Characteristics of HD64F2199 ................................ 916
30. 3. 7 OSD Elect r ic al Cha ract e ristics of HD64F2 199.............................................. 918
Appendix A Instruction Set.......................................................................................... 923
A.1 Instructions.................................................................................................................. 923
A.2 Instruction Codes......................................................................................................... 934
A.3 Operation Code Map.................................................................................................... 944
A.4 Number of Execution States......................................................................................... 948
A.5 Bus Sta t us during Instruction Exe cution ....................................................................... 958
A.6 Change of Condition Codes.......................................................................................... 972
Appendix B Internal I/O Registers............................................................................. 977
B.1 Addresses .................................................................................................................... 977
B.2 Func tion List................................................................................................................ 986
Appendix C Pin Cir cuit Diagrams............................................................................ 1116
C.1 Pin Circuit Diagrams.................................................................................................. 1116
Appendix D Port States in Each Processing State................................................. 1130
D.1 Pin Circuit Diagrams .................................................................................................. 1130
Appendix E Usage Notes............................................................................................ 1131
E.1 Power Supply Rise and Fall Order.............................................................................. 1131
E.2 Sample External Circuits............................................................................................ 1133
E.3 Handling of Pins When OSD Is Not Used ................................................................... 1138
Appendix F Product Lineup....................................................................................... 1140
Appendix G Package Dimensions............................................................................. 1141
Rev. 1.0, 02/ 00, page 1 of 1141
Section 1 Ov erview
1.1 Overview
The H8S/2199 Series comprise microcomputers (MCUs) built around the H8S/2000 CPU,
employing Hitachi's proprietary architecture, and equipped with supporting modules on-chip.
The H8S/2000 has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Serie s.
The H8S/2199 Series is equipped with a digital servo circuit, sync separator, OSD, d ata slicer,
ROM, RAM, seven types of timers, three types of PWM, two types of serial communication
interface, an I2C bus interface, A/D converter, and I/O port as on-chip supporting modules.
The on-chip ROM is either flash memory (F-ZTAT*) or mask ROM, with a capacity of 128,
112, 96, or 80 kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte
and word data to be accessed in one state. Instruction fetching has been speeded up, and
processing speed increased.
The fea t ures of the H8S/2199 Serie s are shown in ta bl e 1. 1.
Note: *F-ZTAT is a trademark of Hitachi, Ltd.
Rev. 1.0, 02/ 00, page 2 of 1141
Table 1.1 Features of the H8S/2199 Series
Item Specifications
CPU • General-r egist er ar chitect ur e
Sixteen 16-bit general regist er s ( also usable as sixteen 8-bit r egister s
or eight 32-bit r egister s)
• High-speed operation suitable for real-tim e cont r ol
Maximum oper at ing f r equency: 10 M Hz/4 t o 5. 5 V
High-speed arithmetic operat ions
8/16/32-bit register -register add/ subtract : 100 ns ( 10-MHz operat ion)
16 × 16-bit r egister - r egister m ult iply: 2000 ns (10- M Hz operation)
32 ÷ 16-bit regist er - r egister divide: 2000 ns (10- M Hz oper at ion)
• Instr uct ion set suitable for high- speed oper at ion
Sixty-five basic instructions
8/16/32- bit t r ansf er / ar it hm et ic and logic instructions
Unsigned/signed multiply and divide inst r uct ions
Powerful bit-manipulation instruct ions
• CPU operating modes
Advanced mode: 16-M byte address space
Timer • Seven t ypes of timer ar e incor por at ed
Timer A
•8-bit interval timer
•Clock source can be selected among 8 types of inter nal clock of
which frequencies are divided from t he system clock (φ) and
subclock (φSUB)
•Functions as clock time base by subclock input
Timer B
•Functions as 8-bit int er val t imer or r eload t imer
•Clock source can be selected among 7 types of inter nal clock or
external event input
Timer J
•Functions as two 8-bit down counter s or one 16- bit down count er
(reload t imer / event counter t im er / t im er out put , etc. , 5 types of
operation m odes)
•Remote contr olled tr ansm it f unct ion
•Take up/Supply Reel Pulse Frequency division
Rev. 1.0, 02/ 00, page 3 of 1141
Item Specifications
Timer Timer L
•8-bit up/ down counter
•Clock source can be selected among 2 types of inter nal clock,
CFG frequency division signal, and PB and REC-CTL (control
pulse)
•Compare- m at ch clear ing funct ion/ aut o r eload f unct ion
Timer R
•Three reload t imer s
•Mode discrimination
•Reel control
•Capstan mot or acceleration/decelerat ion detection funct ion
•Slow tracking mono-multi
Timer X1
•16-bit f r ee- r unning count er
•Clock source can be selected among 3 types of inter nal clock and
DVCFG
•Two output com par e out puts
•Four input capt ur e input s
Watchdog t im er
•Functions as watchdog t imer or 8- bit inter v al tim er
•Generat es r eset signal or NMI at over f low
Prescaler unit Divides system clock frequency and generat es frequency division
clock for support ing m odule funct ions
Divides subclock frequency and gener at es input clock f or Timer A
(clock time base)
Generat es 8- bit PWM f r equency and dut y per iod
8-bit input capt ure at ext er nal signal edge
Frequency division clock output enabled
PWM • Three t y pes of PWM ar e incor por at ed
14-bit PWM : Pulse resolut ion type x 1 channel
8-bit PWM: Dut y cont r ol type x 4 channels
12-bit PWM : Pulse pitch cont r ol t ype x 2 channels
Rev. 1.0, 02/ 00, page 4 of 1141
Item Specifications
Serial
communication
interface ( SCI)
Asynchronous mode or synchr onous m ode select able
Desired bit rat e selectable with built-in baud rate generat or
Multiprocessor com m unicat ion funct ion
I2C bus interface
(2 channels) Conf o rm s to Phillip s I2C bus interf ace st andar d
Start and st op condit ions generated autom at ically
Selection of acknowledge output levels when receiving, and autom atic
loading of acknowledge bit when transmitt ing
Selection of acknowledgement m ode or ser ial mode (without
acknowledge bit)
A/D converter Resolution: 10 bits
Input : 12 channels
High-speed conversion: 13.4 µs minimum conversion time ( 10 M Hz
operation)
Sample-and-hold f unct ion
A/D conversion can be activated by sof t ware or ext er nal tr igger
Address tr ap
controller Int er r upt occur s when the pr eset addr ess is f ound dur ing bus cycle
To-be-t rapped addresses can be individually set at thr ee dif f er ent
locations
I/O port 56 input/out put pins
8 input-only pins
Can be switched for each suppor t ing module
Servo circuit • Digital servo circuits on- chip
Input and out put circ uits
Error det ection circuit
Phase and gain compensation
Sync signal
(servo) • O n- c hip sync signal detection circuit
Can separately detect hor izontal and ver t ical sync signals
Noise detection funct ion
Sync separator
for OSD and
data slicer
• Sync separator including AFC
Horizontal and vertical sync signals separated fr om t he com posit e
video signal
Noise detection
Selection of sync separation met hods
Rev. 1.0, 02/ 00, page 5 of 1141
Item Specifications
OSD (O n Screen
Display) Screen of 32 char act er s × 12 lines
384 types of char act er s
Character conf iguration: 12 dot s × 18 lines
Character colors: Eight hues
Background colors: Eight hues
Cursor colors: Eight hues
Halftone display
Button display
Dat a s lic e r Slice lines: Four lines
Slice lev e ls : Sev e n le v e ls
Sampling clock generated by AFC
Slice interr u pt
Error det ect ion
Flash memor y or m ask RO M ( Refer to the pr oduct line-up)
High-speed static RAM
Product Nam e ROM RAM
H8S/2199 128 k bytes 3 k bytes
H8S/2198 112 k bytes 3 k bytes
H8S/2197 96 k bytes 3 k bytes
H8S/2196 80 k bytes 3 k bytes
Memory
Power-down
state M edium - speed m ode
Sleep mode
Module stop m ode
Standby mode
Subclock operation
Subactive mode, wat ch m ode, subsleep m ode
Interrupt
controller Six external interrupt pins (
,54
to
,54
)
48 internal inter r upt sour ces
Three prior ity levels settable
Rev. 1.0, 02/ 00, page 6 of 1141
Item Specifications
Clock pulse
generator • Two t ypes of clock pulse generat or on- chip
System clock pulse generator : 8 t o 10 M Hz
Subclock pulse generator: 32. 768 kHz
Packages 112-pin plastic QFP (FP-112)
Product lineup
Note: *F-ZTAT version
Product Code
Series Mask RO M
Versions F-ZTAT
Versions ROM/RAM
(bytes) Packages
HD6432199 HD64F2199 128 k/3 k
(256 k*/
8 k*)
FP-112
HD6432198 112 k/3 k FP-112
HD6432197 96 k/3 k FP-112
H8S/2199
HD6432196 80 k/3 k FP-112
Rev. 1.0, 02/ 00, page 7 of 1141
1.2 Internal Block Diagram
Figure 1.1 shows an inte rnal bl ock di a gram of t he H8S/2199 Serie s.
P23/SDA1
P25/SDA0
P22/SCK1
P26/SCL0
P21/SO1
P27/SYNCI
P20/SI1
P24/SCL1
V
SS
VCL
V
SS
V
CC
V
SS
V
CC
MD0
OSC2
OSC1
X2
X1
Hsync(Csync) Sync signal
detection
OV
CC
OV
SS
SV
SS
SV
CC
CAPPWM
CTL(+)
CTLSMT(i)
CTLBias
CVin2
Csync/Hsync
VLPF/Vsync
CTL(–)
AUDIO FF
VIDEO FF
Vpulse
CTL FB
CTL REF
CTLAmp(o)
DFG
CFG
DRMPWM
DPG
P13/
P15/
P12/ Interrupt
controller
R A M
R O M
Internal data bus
External data bus
External address bus
External data bus
External address bus
Internal address bus
Servo pins (CTL input/output
amplifier, three-level output, etc.)
CVin1
CVout
OSD
(Analog input/output) Sync
separation
Sub-carrier
oscillator
AFC
H8S/2000 CPU
Bus
controller
Address trap
controller
P16/
P11/
P17/TMOW
P10/
P14/
P03/AN3
P05/AN5
P02/AN2
P06/AN6
P01/AN1
P07/AN7
P00/AN0
P04/AN4
ANA
AN9
AN8
ANB
AV
CC
AV
SS
P83/C.Rotary/R
P85/COMP/B
P82/EXCTL
P86/EXTTRG
P81/EXCAP/YBO
P87/DPG
P80/YCO
P84/H.Amp SW/G
P33/PWM1
P35/PWM3
P32/PWM0
P36/BUZZ
P31/SV2
P37/TMO
P30/SV1
P34/PWM2
P43/FTIC
P45/FTOA
P42/FTIB
P46/FTOB
P41/FTIA
P47/RPTRG
P40/PWM14
P44/FTID
P73/PPG3
P75/PPG5/RP9
P72/PPG2
P76/PPG6/RPA
P71/PPG1
P77/PPG7/RPB
P70/PPG0
P74/PPG4/RP8
4fscout/2fscout
AFC pc
AFC osc
AFC LPF
4fscin/2fscin
P63/RP3
P65/RP5
P62/RP2
P66/RP6/
P61/RP1
P67/RP7/TMBI
P60/RP0
P64/RP4
14-bit PWM
12-bit PWM
8-bit PWM Prescaler unit
Watchdog
timer
Timer L
Timer A
SCI1 Timer B
Timer J
I
2
C bus
interface
Timer R
A/D converter Timer 1
Port 7 Port 6 Port 4 Port 3
Port 2Port 1Port 0Port 8 Analog
port
Subclock pulse
generator
Subclock pulse
pulse generator
Servo circuit Data slicer
OSD
Figure 1.1 Internal Block Diagram of H8S/2199 Series
Rev. 1.0, 02/ 00, page 8 of 1141
1.3 Pin Arrangement and Functions
1.3.1 Pin Arrangement
Figure 1.2 shows the pin arrangement of the H8S/2199 Series.
P33/PWM1
P34/PWM2
MD0
VCL
OSC2
V
SS
OSC1
X1
X2
FWE
P40/PWM14
P41/FTIA
P42/FTIB
P43/FTIC
P44/FTID
P45/FTOA
P46/FTOB
P47/RPTRG
P21/SO1
P20/SI1
P22/SCK1
P23/SDA1
P24/SCL1
P25/SDA0
P26/SCL0
P27/SYNCI
V
SS
P32/PWM0
P31/SV2
P30/SV1
P70/PPG0
P71/PPG1
P72/PPG2
P73/PPG3
P74/PPG4/RP8
P75/PPG5/RP9
P76/PPG6/RPA
P77/PPG7/RPB
P80/YCO
P81/EXCAP/YBO
P82/EXCTL
P83/C.Rotary/R
P84/H.Amp SW/G
P85/COMP/B
P86/EXTTRG
P87/DPG
DFG
VIDEO FF
AUDIO FF
DRM PWM
CAP PWM
Vpulse
V
SS
Csync
V
CC
V
CC
P35/PWM3
P36/BUZZ
P37/TMO
P60/RP0
P61/RP1
P62/RP2
P63/RP3
P64/RP4
P65/RP5
P66/RP6/
P67/RP7/TMBI
P17/TMOW
P16/
P15/
P14/
P13/
P12/
P11/
P10/
AV
CC
P00/AN0
P01/AN1
P02/AN2
P03/AN3
P04/AN4
P05/AN5
P06/AN6
1SV
SS
FP-112
(Top view)
84
2CTLREF 83
3CTL(+) 82
4CTL(–) 81
5CTLBias 80
6CTLFB 79
7CTLAmp(o) 78
8CTLSMT(i) 77
9CFG 76
10SV
CC
75
11AFCpc 74
12AFCosc 73
13AFCLPF 72
14Csync/Hsync 71
15VLPF/Vsync 70
16CVin2 69
17CVin1 68
18OV
CC
67
19CVout 66
20OV
SS
65
214fscout/2fscout 64
224fscin/2fscin 63
23
AV
SS
62
24
ANB 61
25ANA 60
26AN9 59
27AN8 58
28P07/AN7 57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Figure 1.2 Pin Arrangement of H8S/2199 Series
Rev. 1.0, 02/ 00, page 9 of 1141
1.3.2 Pin Functions
Table 1.2 summarizes the functions of the H8S/2199 Series pins.
Table 1.2 Pin Functions
Type Symbol Pin No. I/O Name and Function
VCC 56, 112 Input Power supply:
All Vcc pins should be connected to the syst em
power supply (+5V)
VSS 57, 79,
110 Input Ground:
All Vcc pins should be connected to the syst em
power supply (0V)
SVCC 10 Input Servo power supply:
SVcc pin should be connected to t he ser v o
analog power supply (+5V)
SVSS 1 Input Servo ground:
SVss pin should be connected to t he ser v o
analog power supply (0V)
AVCC 36 Input Analog power supply:
Power supply pin for A/D converter . I t should be
connected to the system power supply (+5V)
when the A/D convert er is not used
AVSS 23 Input Analog ground:
Ground pin f or A/ D convert er. I t should be
connected to the system power supply (0V)
OVCC 18 Input OSD power supply:
VCC(OSD) should be connected t o the OSD
analog power supply (+5 V)
OVSS 20 Input OSD ground:
VSS (OSD) should be connected t o the OSD
analog power supply (0 V)
Power
supply
VCL 81 Input Smoot hing capacitor connect ion:
Connect 0.1- µF power- s m oot hing capacitance
between VCL and VSS
OSC1 78 Input
OSC2 80 Output
Connected t o a cr y stal oscillat or. I t can also
input an external clock. See sect ion 9, Clock
Pulse Generat or , f or t ypical connection
diagram s f o r a cryst al os cillat o r and external
clock input
X1 76 Input
Clock
X2 75 Output
Connected t o a 32. 768 kHz c r y st al os cillator.
See section 9, Clock Pulse Generator, for t ypical
connection diagrams
Rev. 1.0, 02/ 00, page 10 of 1141
Type Symbol Pin No. I/ O Nam e and Funct ion
Operating
mode
control
MD0 82 Input M ode pin:
This pin sets the oper at ing mode. This pin
should not be changed while the MCU is in
operation
5(6
77 Input Reset input:
When this pin is driven low, the chip is reset
System
control
FWE 74 Input Flash mem or y enable:
Enables/disables flash memor y pr ogr am m ing.
This pin is available only with MCU with flash
memory on-chip. For mask ROM type, do not
connect anything t o t his pin
,54
37 Input Ext er nal inter r upt r equest 0:
External inter r upt input pin for which rising edge
sense, falling edge sense or both edges sense
are selectable
Interrupts
,54
,54
,54
,54
,54
38
39
40
41
42
Input Ext er nal inter r upt r equests 1 to 5:
External inter r upt input pins for which rising or
falling edge sense are selectable
,&
43 Input I nput captur e input:
Input capt ur e input pin f or pr escaler unit
Prescaler
unit
TMOW 44 Output Frequency division clock output:
Output pin for clock of which fr equency is divided
by prescaler
TMBI 45 Input Timer B event input :
Input pin for event s to be input t o Timer B
counter
,54
,54
38
39 Input Timer J event input:
Input pin for event s to be input t o Timer J RDT-
1or RDT-2 counter
TMO 53 Out put Timer J tim er out put :
Out put pin for toggle at underflow of RDT-1 of
Timer J, or r em ot e controlled tr ansm it data
Timers
BUZZ 54 Out put Timer J buzzer out put:
Out put pin for toggle which is selectable among
fixed fr equency, 1Hz fr equency divided fr om
subclock (32 kHz), and f r equency division CTL
signal
Rev. 1.0, 02/ 00, page 11 of 1141
Type Symbol Pin No. I/ O Nam e and Funct ion
,54
40 Input Timer R input capture:
Input pin for input capt ur e of Tim er R TMRU-1 or
TMRU-2
FTOA
FTOB 68
67 Out put Timer X1 output com par e A and B output:
Out put pin for output com par e A and B of Timer
X1
Timers
FTIA
FTIB
FTIC
FTID
72
71
70
69
Input Timer X1 input capture A, B, C and D input:
Input pin for input capt ur e A, B, C and D of
Timer X1
PWM0
PWM1
PWM2
PWM3
85
84
83
55
Out put 8-bit PWM squar e wavef or m out put:
Out put pin for waveform gener ated by 8-bit
PWM 0, 1, 2 and 3
PWM
PWM14 73 Out put 14-bit PWM squar e wavef or m out put:
Out put pin for waveform gener ated by 14-bit
PWM
SCK1 63 Input
/output SCI clock input/output:
Clock input pins for SCI 1
SI1 65 Input SCI receive data input:
Receive data input pins for SCI 1
Serial
commu-
nication
interface
(SCI) SO 1 64 Out put SCI transm it dat a out put :
Transmit dat a out put pins for SCI 1
SCL0
SCL1 59
61 Input
/output I2C bus interface clock input/out put :
Clock input/ out put pin for I 2C bus interf ace
SDA0
SDA1 60
62 Input
/output I2C bus interface dat a input / out put :
Data input/output pin f or I 2C bus interf ace
I2C bus
interface
SYNCI 58 Input I2C bus interface clock input:
I2C formalless serial clock input
Rev. 1.0, 02/ 00, page 12 of 1141
Type Symbol Pin No. I/ O Nam e and Funct ion
AN7 t o
AN0 28 to 35 Input Analog input channels 7 to 0:
Analog data input pins. A/D conversion is
start ed by a software t r igger ing
AN8
AN9
ANA
ANB
27
26
25
24
Input Analog input channels 8, 9, A and B:
Analog data input pins. A/D conversion is
started by an exter nal t r igger, a har dwar e
trigger , or sof tware
A/D
converter
$'75*
46 Input A/ D conversion ext er nal tr igger input:
A/D conversion for analog data input pins 8, 9,
A, and B is start ed by an external tr igger
AUDIO FF 106 Out put Audio FF:
Out put pin for audio head switching signal
VIDEO FF 105 Output Video FF:
Output pin for video head switching signal
CAPPWM 108 O u tput Caps tan mix:
12-bit PWM out put pin giving result of capst an
speed error and phase er r or aft er filtering
DRMPWM 107 Output Drum m ix:
12-bit PWM out put pin giving result of dr um
speed error and phase er r or aft er filtering
Vpulse 109 Output Additional V pulse:
Three-level output pin f or additional V signal
synchronized to t he Video FF signal
C.Rotary 99 Output Color rotary signal:
Output pin for color signal processing contr ol
signal in four- head special-ef f ect s playback
H.AmpSW 100 Output Head-amp switch:
Output pin for pr eam plifier out put select signal in
four- head special-ef f ect s playback.
COMP 101 Input Compar e input:
Input pin f or signal giving the result of
preamplifier output com par ison in four - head
special-effects playback.
CTL (+ )
CTL (-) 3
4Input
/output CTL head (+) and (-) pins:
I/O pins for CTL signals
Servo
circuits
CTL Bias 5 Input CTL primar y am p bias supply:
Bias supply pin for CTL primar y am p
Rev. 1.0, 02/ 00, page 13 of 1141
Type Symbol Pin No. I/ O Nam e and Funct ion
CTL Amp
(o) 7 Output CTL amp output:
Out put pin for CTL amp
CTL SMT
(l) 8 Input CTL Schmitt am p input :
Input pin for CTL Schmit t am p
CTLFB 6 Input CLT f eedback input :
Input pin for CTL amp high- r ange char act er ist ics
control
CTLREF 2 Output CTL amp refer ence volt age out put :
Output pin for 1/ 2Vcc ( SV)
CFG 9 Input Capst an FG input:
Schmitt com par at or input pin for CFG signal
DFG 104 Input Drum FG input:
Schmitt input pin f or DFG signal
DPG 103 Input Drum PG input :
Schmitt input pin f or DPG signal
EXCTL 98 I nput External CTL input:
Input pin for ext ernal CTL signal
Csync 111 Input M ixed sync signal input:
Input pin f or m ixed sync signal
EXCAP 97 Input Capstan ext er nal sync signal input:
Signal input pin for ext er nal synchr onization of
capstan phase contr ol
EXTTRG 102 Input Exter nal t r igger signal input:
Signal input pin for synchr onizat ion with
refer ence signal generat or
SV1 87 Out put Servo monitor out put pin 1:
Out put pin for servo m odule inter nal signal
SV2 86 Out put Servo monitor out put pin 2:
Out put pin for servo m odule inter nal signal
Servo
circuits
PPG7 to
PPG0 95 t o 88 Out put PPG:
Out put pin for HSW timing generat or . To be
used when head switching is required as well as
Audio FF and Video FF
Rev. 1.0, 02/ 00, page 14 of 1141
Type Symbol Pin No. I/O Name and Functi on
Csync/
Hsync 14 Input/
output Sync signal input/output :
Composite sync signal input/output or hor izont al
sync signal input
VLPF/
Vsync 15 Input Sync signal input:
Pin for connecting ext er nal LPF for ver t ical sync
signal or input pin for vert ical sync signal
AFC pc 11 Input /
output AFC os c illation :
Pin for connecting exter nal circuit f or AFC
oscillation
AFC osc 12 Input/
output AFC os c illation :
Pin for connecting exter nal circuit f or AFC
oscillation
AFC LPF 13 Input /
output Pin for connecting external LPF for AFC
4 fsc in/
2 fsc in 22 Input fsc osc illat ion:
Input pin f or s ubcar r ier osc illat or . 4fs c or 2f s c
can be selected
fsc: Subcar r ier f r equency
4 fsc out/
2 fsc out 21 Out p u t fsc o s c illa tion:
Ou tput pin for s u b c a r rier os c illator. 4 fsc o r 2 fsc
can be selected
fsc: Subcar r ier f r equency
Sync
separator
CVin2 16 Input Composite video input:
Composite video signal input. Input 2- Vp-p
composite video signal, and the sync tip of t he
signal is clamped to about 2. 0 V
CVin1 17 Input Composite video input:
Composite video signal input for OSD. Input 2-
Vp-p composite video signal, and the sync t ip of
the signal is clamped to about 1.4 V
CVout 19 Output Composite video out put :
Composite video signal output for OSD. 2-Vp-p
composite video signal is output
R 99 Out put OSD digital output :
Color signal R output
G 100 Output O SD digital output:
Color signal G output
OSD
B 101 Output O SD digital output:
Color signal B output
Rev. 1.0, 02/ 00, page 15 of 1141
Type Symbol Pin No. I/O Name and Functi on
OSD YCO 96 Out put OSD digital output :
Character dat a out put
YBO 97 Out put OSD digital output :
Character display position output
Data
slicer CVin2 16 Input Composite video input:
Composite video signal input. Input 2- Vp-p
composite video signal, and the sync tip of t he
signal is clamped to about 2. 0 V.
P07 to P00 28 to 35 Input Port 0:
8-bit input pins
P17 to P10 44 to 37 Input
/output Port 1:
8-bit I / O pins
P27 to P20 58 to 65 Input
/output Port 2:
8-bit I / O pins
P37 to P30 53 to 55
83 to 87 Input
/output Port 3:
8-bit I / O pins
P47 to P40 66 to 73 Input
/output Port 4:
8-bit I / O pins
P67 to P60 45 to 52 Input
/output Port 6:
8-bit I / O pins
P77 to P70 95 to 88 Input
/output Port 7:
8-bit I / O pins
P87 to P80 103 to
96 Input
/output Port 8:
8-bit I / O pins
RP7 to RP0 45 to 52 Out put Realtime out put por t :
8-bit r ealtim e out put pins
RPB to
RP8 95 to 92 Output Realtime out put por t:
4-bit r ealtim e out put pins
I/O port
RPTRG 66 Input Realtime out put port t r igger input:
Input pin for r ealt ime out put port t rigger
Rev. 1.0, 02/ 00, page 17 of 1141
Section 2 CPU
2.1 Overview
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture
that is upward-compatible with the H8/300 and H8/300H CPUs. T he H8S/ 2000 CPU has six teen
16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space,
and is ideal for realtime control.
2.1.1 Features
The H8S/2000 CPU has the following features.
• Upwa rd-compatible with H8/300 and H8/300H CPUs
Can execute H8/300 and H8/300H object programs
• General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• Sixty-five basic instructions
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addre ssing mode s
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:32, ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
• 16-Mbyte address space
Program: 16 Mbytes
Data: 16 Mbytes (4 Gbytes architecturally)
• High-speed operation
All frequently-used instructions execute in one or two states
Maximum clock rate: 10 MHz
8/16/32-bit register-register add/subtract: 100 ns
8 × 8-bit register-register multiply: 1200 ns
Rev. 1.0, 02/ 00, page 18 of 1141
16 ÷ 8-bit regi ster-re gi ster di vi de: 1200 ns
16 × 16-bit register-register multiply: 2000 ns
32 ÷ 16-bit re giste r-re giste r di vide : 2000 ns
• Two CPU operating modes
Normal mode*/Advanced mode
• Powe r-down state
Transition to power-down state by SLEEP instruction
CPU clock speed selection
Note: *Normal mode is not available for this LSI.
2.1.2 Differences between H8S/2600 CPU and H8S/ 2000 CPU
The diffe re nce s bet ween t he H8S/2600 CPU and the H8S/2000 CPU are shown below.
• Register configuration
The MAC register i s supported onl y by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, a nd ST MAC a re support ed only by t he
H8S/2600 CPU.
• Number of execution states
The number of execution states of the MULXU and MULXS instructions differ as follows.
Number of Execut i on St at es
Instruction Mnemonic H8S/2600 H8S/2000
MUL XU.B Rs, Rd 3 12MULXU
MULXU.W Rs, Er d 4 20
MULXS.B Rs, Rd 4 1 3MULXS
MULXS.W Rs , Er d 5 2 1
There are also differences in the address space, EXR register functions, power-down state, etc.,
depending on t he product .
2.1.3 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
• More general re gi sters and c ont rol re gi sters
Eight 16-bi t ext e nded re gi sters, and one 8-bi t c ont rol re gi ster, ha ve bee n a dded.
Rev. 1.0, 02/ 00, page 19 of 1141
• Expanded addre ss space
Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced a ddre ssing mode
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Addressi ng modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide instructions have been added.
Two-bit shift instructions have been added.
Instructions for sa ving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
2.1.4 Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2000 CPU has the followi ng enhancements.
• Additional c ont rol re gi ster
One 8-bit cont rol regi ste r has bee n a dded.
• Enhanced instructions
Addressi ng modes of bit-manipulation instructions have been enhanced.
Two-bit shift instructions have been added.
Instructions for sa ving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
Rev. 1.0, 02/ 00, page 20 of 1141
2.2 CPU Op erat in g Mod es
The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total
address space (architecturally the maximum total address space is 4 Gbytes, with a maximum of
16 Mbytes for the program area and a maximum of 4 Gbytes for the data area).
The mode is selected by the mode pins of the microcontroller.
CPU operating mode
Normal mode*
Advanced mode
Maximum 64 kbytes for program
and data areas combined
Maximum 16 Mbytes for program
and data areas combined
Note: * Normal mode is not available for this LSI.
Figure 2.1 CPU Operating Modes
(1) Normal Mode (Not available for this LSI)
The exception vector table and stack have the same structure as in the H8/300 CPU.
(a) Address Space
A maximum address space of 64 kbytes can be accessed.
(b) E xte nde d Regi ste rs (En)
The ext e nded re gi sters (E0 t o E 7) ca n be used as 16-bit re giste rs, or a s the upper 16-bi t
segments of 32-bit registers. When En is used as a 16-bit register it can contain any
value, e ve n when the c orresponding ge ne ral re giste r (Rn) i s used as an addre ss registe r.
If the general register is referenced in the register indirect addressing mode with pre-
decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the
value in the corresponding extended register (En) will be affected.
(c) Instructi on Set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
Rev. 1.0, 02/ 00, page 21 of 1141
(d) Exception Vector Table and Memory Indirect Branch Addresses
In normal mode the top area starting at H'0000 is allocated to the exception vector table.
One branch address is stored per 16 bits. The configuration of the exception vector table
in normal mode is shown in figure 2. 2. For details of the exception vector table, see
section 5, Exception Handling.
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Reset exception vector
Exception vector 1
Exception vector 2
Exception vector table
(Reserved for system use)
Figure 2. 2 Exc e ption Vector Table (Normal Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR
instructions uses an 8-bit absolute address included in the instruction code to specify a
memory operand that contains a branch address. In normal mode the operand is a 16-bit
word operand, provi ding a 16-bi t bra nc h addre ss. Branc h a ddresses can be store d in t he
top area from H'0000 to H'00FF. Note that this area is also used for the exception vector
table.
Rev. 1.0, 02/ 00, page 22 of 1141
(e) Stack Structure
When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC
and condition-code register (CCR) are pushed onto the stack in exception handling, they
are stored a s shown in figure 2. 3. T he e xt ende d c ontrol re giste r (E XR) is not pushed onto
the stack. For details, see section 5, Exception Handling.
(a) Subroutine Branch (b) Exception Handling
PC
(16 bits) CCR
CCR*
PC
(16 bits)
SP SP
Note: * Ignored when returning.
Figure 2.3 Stack Structure in Normal Mode
(2) Advanc ed Mode
(a) Address Space
Linear access is provided to a 16-Mbyte maximum address space (architecturally a
maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum
of 4 Gbytes for program and data areas combined).
(b) E xte nde d Regi ste rs (En)
The ext e nded re gi sters (E0 t o E 7) ca n be used as 16-bit re giste rs, or a s the upper 16-bi t
segments of 32-bit re giste rs or addre ss registers.
(c) Instructi on Set
All instruct i ons and addre ssing mode s can be used.
Rev. 1.0, 02/ 00, page 23 of 1141
(d) Exception Vector Table and Memory Indirect Branch Addresses
In advanced mode the top area starting at H'00000000 is allocated to the exception vector
table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address
is stored in the lowe r 24 bits (figure 2.4). For details of the exception vector table, see
section 5, Exception Handling.
H'00000000
H'00000003
H'00000004
H'0000000B
H'0000000C
Exception vector table
Reserved
Reset exception vector
(Reserved for system use)
Reserved
Exception vector 1
Reserved
H'00000010
H'00000008
H'00000007
Figure 2. 4 Exc e ption Vector Table (Advanced Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR
instructions uses an 8-bit absolute address included in the instruction code to specify a
memory operand that contains a branch address. In advanced mode the operand is a 32-
bit longword opera nd, provi ding a 32-bi t bra nc h addre ss. The uppe r 8 bit s of the se 32
bits are a re served a re a t ha t i s rega rded a s H'00. Branc h a ddresses can be store d in t he
area from H'00000000 t o H'000000FF. Note t ha t t he first pa rt of thi s range is al so the
exception vector table.
Rev. 1.0, 02/ 00, page 24 of 1141
(e) Stack Structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a
subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack
in exce pt ion ha ndl ing, t he y are store d as shown in figure 2. 5. T he ext e nded c ont rol
register (EXR) is not pushed onto the stack. For details, see section 5, Exception
Handling.
(a) Subroutine Branch (b) Exception Handling
PC
(24 bits)
CCR
PC
(24 bits)
SP SP
Reserved
Figure 2.5 Stack Structure in Advanced Mode
Rev. 1.0, 02/ 00, page 25 of 1141
2.3 Address Space
Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/ 2000 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode.
(b) Advanced mode
H'0000
H'FFFF
H'00000000
H'FFFFFFFF
H'00FFFFFF
(a) Normal mode*
Data area
Program area
Cannot be used
with this LSI
Note: * Normal mode is not available for this LSI.
Figure 2.6 Memory Map
Rev. 1.0, 02/ 00, page 26 of 1141
2.4 Register Configuration
2.4.1 Overview
The CPU has the int e rnal re giste rs shown in figure 2. 7. T here a re t wo type s of registe rs:
general re giste rs and c ontrol re giste rs.
T – – – – I2 I1 I0EXR 76543210
PC
23 0
15 0 7 0 7 0
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
General Registers (Rn) and Extended Registers (En)
Control Registers (CR)
[Legend]
SP
PC
EXR
T
I2 to I0
CCR
I
UI
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7 (SP)
IUIHUNZVC
CCR 76543210
: Half-carry flag
: User bit
: Negative flag
: Zero flag
: Overflow flag
: Carry flag
H
U
N
Z
V
C
: Stack pointer
: Program counter
: Extended control register
: Trace bit
: Interrupt mask bits
: Condition-code register
: Interrupt mask bit
: User bit or interrupt mask bit
Note: * Does not affect operation in this LSI.
*
Fi g ur e 2 .7 CP U Regi st e rs
Rev. 1.0, 02/ 00, page 27 of 1141
2.4.2 General Registers
The CPU has eight 32-bit general registers. These general registers are all functionally alike and
can be used as both address registers and data registers. When a general register is used as a
data register, it can be accesse d as a 32-bit, 16-bit, or 8-bit register. When the general registers
are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to
ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E regi ste rs (E0 to E 7) a re a l so referre d t o as ext e nded re gi sters.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen
8-bit regi ste rs.
Figure 2.8 illustrates the usage of the general registers. The usage of each register can be
selected independently.
● Address registers
● 32-bit registers ● 16-bit registers ● 8-bit registers
ER registers
(ER0 to ER7)
E registers (extended registers)
(E0 to E7)
R registers
(R0 to R7)
RH registers
(R0H to R7H)
RL registers
(R0L to R7L)
Figure 2.8 Usage of General Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the
stack.
Rev. 1.0, 02/ 00, page 28 of 1141
SP (ER7)
Free area
Stack area
Figure 2. 9 Stack
2.4.3 Control Register s
The cont rol regi ste rs are t he 24-bit progra m c ount er (PC), 8-bit e xte nde d cont rol regi ste r (EXR),
and 8-bit c ondi ti on-c ode re gi ster (CCR).
(1) Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The
length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored.
(When an instruction is fetched, the least significant PC bit is regarded as 0.)
(2) Extended Control Register (EXR)
An 8-bit register. In this LSI, this register does not affect operation.
Bit 7: Trace Bi t (T)
This bit is reserved. In this LSI, this bit does not affect operation.
Bits 6 to 3: Reserved
These bits are reserved. They are always read as 1.
Bits 2 to 0: Interrupt Mask Bits (I2 to I0)
These bits are reserved. In this LSI, these bits do not affect operation.
(3) Condit i o n: Code Re giste r (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit
(I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Bit 7: Interrupt Mask Bit (I)
Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit
setting.) The I bit is set to 1 by hardware at the start of an exception-handling sequence.
For details, see section 6, Interrupt Controller.
Rev. 1.0, 02/ 00, page 29 of 1141
Bit 6: User Bit or Interr upt Mask Bit (UI)
Can be written and read by software using the LDC, STC, ANDC, ORC , and XOR C
instructions. This bit can also be used as an interrupt mask bit. For details, see section 6,
Interrupt Controller.
Bit 5: Half-Carr y F lag (H )
When t h e ADD.B, ADDX. B , SUB .B, SUBX.B, C MP.B, or NE G.B i n st r uction is
executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
oth e r wi se. W h e n t h e ADD.W , SUB. W, C MP. W, o r NEG. W i n st r u ction is executed, the
H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When
the ADD. L , SUB.L , C MP.L , o r NE G.L i n st r uction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 27, and cleared to 0 otherwise.
Bit 4: User Bit (U)
Can be written and read by software using the LDC, STC, ANDC, ORC , and XOR C
instructions.
Bit 3: Negative F l ag (N)
Stores the value of the most significant bit (sign bit) of data.
Bit 2: Zero F l ag (Z)
Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1: Over fl ow Flag (V)
Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise.
Bit 0: Carry Fl ag (C)
Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
(a) Add instructions, to indicate a carry
(b) Subtract instructions, to indicate a borrow
(c) Shift and rotate instructions, to store the carry
The carry flag is also used as a bit accumulator by bit-manipulation instructions.
Some instructions leave some or all of the flag bits unchanged. For the action of each
instruction on the flag bits, see section 29, Appendix A.1, List of Instructions.
Operat i ons c a n be perform e d on t he CCR bi t s by the L DC, STC, ANDC, ORC, a nd XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional
branch (Bcc ) i nstruct i ons.
2.4.4 Initial Regi ster Values
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the
trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits
and the general registers are not initialized. In particular, the stack pointer (ER7) is not
initialized. The stack pointer should therefore be initialized by an MOV.L i n st r u ction executed
immediately after a reset.
Rev. 1.0, 02/ 00, page 30 of 1141
2.5 Data Form at s
The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data.
Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte
operand data. The DAA and DAS d ecimal-adjust instructions treat byte data as two digits of 4-
bit BCD data.
2.5.1 Ge neral Regi ster Data For mats
Figure 2.10 shows the data formats in general registers.
70
70
MSB LSB
MSB LSB
7043
Upper digit Lower digit
Don't care
Don't care
Don't care
7043
Upper digit Lower digit
70
Don't care
65432710
70
Don't care 65432710
Don't care
Data FormatData type
1-bit data
1-bit data
4-bit BCD data
4-bit BCD data
Byte data
Byte data
General Register
RnH
RnL
RnH
RnL
RnH
RnL
Figure 2. 10 G e neral Regi ster Data For mats (1)
Rev. 1.0, 02/ 00, page 31 of 1141
15 0
MSB LSB
15 0
MSB LSB
31 16
MSB
15 0
LSB
En Rn
Data Type
Word data
Word data
Longword data
General Register
Rn
En
ERn
Data format
ERn
En
Rn
RnH
RnL
MSB
LSB
: General register ER
: General register E
: General register R
: General register RH
: General register RL
: Most significant bit
: Least significant bit
[Legend]
Figure 2. 11 G e neral Regi ster Data For mats (2)
Rev. 1.0, 02/ 00, page 32 of 1141
2.5.2 Memory Data For mats
Figure 2.12 shows the data formats in memory.
The CPU can access word data and longword data in memory, but word or longword data must
begin at an even address. If an attempt is made to access word or longword data at an odd
address, no address error occurs but the least significant bit of the address is regarded as 0, so the
access starts at the preceding address. This also applies to instruction fetches.
70
76 543210
MSB LSB
MSB
MSB
LSB
LSB
Address
Address L
Address L
Address 2M
Address 2N
Address 2N+1
Address 2N+2
Address 2N+3
1-bit data
Byte data
Word data
Longword data
Data Type Data Format
Address 2M+1
Figure 2. 12 M e mory Data For mats
When ER7 (SP) is used as an address register to access the stack, the operand size should be
word size or longword size.
Rev. 1.0, 02/ 00, page 33 of 1141
2.6 Instruction Set
2.6.1 Overview
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in
table 2.1.
Tabl e 2 .1 Instruc t i o n Cl a ssi f i cat i o n
Function Instructions Size Types
MOV BWL
POP*1, PUSH*1WL
LDM, STM L
Data transfer
MO VFPE, M OVTPE B
5
ADD, SUB, CM P, NEG BWL
ADDX, SUBX, DAA, DAS B
INC, DEC BWL
ADDS, SUBS L
MULXU, DI VXU, M ULXS, DI VXS BW
EXTU, EXTS WL
Arithmetic
TAS B
19
Logic operations AND, OR, XO R, NOT BWL 4
Shif t SHAL, SHAR, SHLL, SHLR, ROTL, RO TR,
ROTXL, RO TXR BWL 8
Bit m a n ipula tion RSET, BCLR, BNOT, BTST, BLD, BILD, BST,
BIST, BAND, BIAND, BOR, BIO R, BXOR,
BIXOR
B14
Branch Bcc*2, JMP, BSR, JSR, RTS 5
System c o ntr o l TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC,
XORC, NO P 9
Block d ata tra ns fer EEPMOV 1
Total : 65 t ypes
Notes: B: byt e size; W : word size; L: longword size.
1. POP.W Rn and PUSH.W Rn are identical to MO V. W @SP+, Rn and MO V.W Rn, @ -
SP.
POP.L ERn and PUSH.L ERn are identical to MOV. L @ SP+, ERn and MO V. L ERn,
@-SP.
2. Bcc is the general name for condit ional branch instruct ions.
Rev. 1.0, 02/ 00, page 34 of 1141
2. 6.2 Instructi o ns a nd Addr e ssing M o de s
Table 2.2 indicates the combinations of instructions and addressi ng modes that the H8S/2000
CPU can use.
Tabl e 2 .2 Combi nat i o ns o f Inst r ucti o ns a nd Addr e ssing M o de s
Addressing Modes
Function
Arithmetic operationsSystem control
Branch
Logic
operation
Instruction
MOV
POP, PUSH
LDM, STM
ADD, CMP
SUB
ADDX, SUBX
ADDS, SUBS
INC, DEC
DAA, DAS
NEG
EXTU, EXTS
TAS
MOVFPE,
MOVTPE*
MULXU,
DIVXU
MULXS,
DIVXS
AND, OR,
XOR
ANDC,
ORC, XORC
NOT
Bcc, BSR
JMP, JSR
RTS
TRAPA
RTE
SLEEP
LDC
STC
NOP
Shift
Bit manipulation
Block data transfer
Data transfer
BWL
#xx
—
—
BWL
WL
B
—
—
—
—
—
—
—
—
—
BWL
B
—
—
—
—
—
—
—
B
—
—
—
—
—
BWL
Rn
—
—
BWL
BWL
B
L
BWL
B
BWL
WL
—
—
BW
BW
BWL
—
BWL
—
—
—
—
—
—
B
B
—
BWL
B
—
BWL
@ERn
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
B
—
BWL
@(d:16, ERn)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
BWL
@(d:32, ERn)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
BWL
@-ERn/@ERn+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
B
@aa:8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
BWL
@aa:16
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
B
—
—
@aa:24
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL
@aa:32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
B
—
—
@(d:8, PC)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
@(d:16, PC)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
@@aa:8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WL
L
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BW
[Legend]
B: Byte
W: Work
L: Longword
Note: *Cannot be used in this LSI .
Rev. 1.0, 02/ 00, page 35 of 1141
2. 6.3 Tabl e o f Instruc tions Cl a ssi f i e d by F uncti o n
Tables 2.3 to 2.10 summarize the functions of the instructions. The notation used in table 2.3 is
defined be l ow.
Operation Notati on
Rd General r egister (destination) *
Rs General r egister (source) *
Rn General r egister *
ERn General r egister (32-bit r egist er )
(EAd) Destination operand
(EAs) Source operand
EXR Extended contr ol register
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (o v erf lo w) f la g in CCR
C C (carry) flag in CCR
PC Program count er
SP Stack pointer
#IMM Imm ediat e dat a
Disp Displacement
+ Addition
−Subtraction
×Multiplication
÷Division
∧Logical AND
∨Logical OR
⊕Logical exclusiv e O R
→Move
∼NOT (logic al c o mplement)
:8/ : 16/ : 24/:32 8-, 16- , 24-, or 32- bit length
Note: *General regist er s include 8-bit regist er s ( R0H to R7H, R0L to R7L), 16- bit r egister s ( R0 to
R7, E0 to E7), and 32- bit r egist er s ( ER0 to ER7).
Rev. 1.0, 02/ 00, page 36 of 1141
Table 2.3 Data Transfe r Instr uc ti ons
Instruction Size*Function
MOV B/W/L (EAs) → Rd, Rs → (EAd)
Moves data between two general regist er s or bet ween a general
register and m em or y, or m oves imm ediat e dat a t o a gener al
register
MOVFPE B Cannot be used in this LSI
MOVTPE B Cannot be used in this LSI
POP W/L @SP+ → Rn
Pops a general register f r om t he st ack
POP.W Rn is identical to M O V. W @ SP+, Rn
POP.L ERn is identical to MO V. L @ SP+, ERn
PUSH W/L Rn → @-SP
Pushes a general register ont o t he st ack
PUSH.W Rn is identical to M O V.W Rn, @-SP
PUSH.L ERn is identical to MO V.L ERn, @-SP
LDM L @SP+ → Rn (register list)
Pops two or mor e gener al register s f r om t he stack
STM L Rn (register list) → @-SP
Pushes two or mor e general r egister s ont o t he stack
Note: *Size refers t o t he oper and size.
B: Byte
W: Word
L: Longword
Rev. 1.0, 02/ 00, page 37 of 1141
Tabl e 2 .4 Ari thm e t i c Instr ucti o ns
Instruction Size*Function
ADD
SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
Perfor m s addit ion or subt raction on data in t wo general r egister s,
or on imm ediate dat a and data in a general register . ( Imm ediate
byte dat a cannot be subt r act ed from byt e data in a general
register. Use the SUBX or ADD instruction)
ADDX
SUBX BRd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Perfor m s addit ion or subt raction with carr y on byte data in t wo
general register s, or on im m ediate data and data in a general
register
INC
DEC B/W /L Rd ± 1 → Rd, Rd ± 2 → Rd
Increm ent s or decr em ent s a gener al r egister by 1 or 2. ( Byt e
operands can be increment ed or decr em ent ed by 1 only)
ADDS
SUBS BRd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtr act s t he value 1, 2, or 4 to or f r om data in a 32-bit
register
DAA
DAS B/W Rd decimal adjust → Rd
Decimal-adjusts an addition or subtr act ion result in a general
regist er by r eferring to t he CCR to produc e 4- bit BCD data
MULXU B/W Rd × Rs → Rd
Perfor m s unsigned m ultiplication on data in t wo general
registers: either 8 bits × 8 bits → 16 bits or 16 bit s ×16 bit s → 32
bits
MULXS B/W Rd × Rs → Rd
Perfor m s signed m ultiplication on data in t wo general regist er s:
either 8 bits × 8 bit s → 16 bits or 16 bit s ×16 bits → 32 bits
DIVXU B/W Rd ÷ Rs → Rd
Perform s unsigned division on data in two general registers:
either 16 bits ÷ 8 bits × 8- bit quot ient and 8- bit r em ainder or 32
bits ÷ 16 bits × 16- bit quotient and 16-bit r em ainder
Rev. 1.0, 02/ 00, page 38 of 1141
Instruction Size*Function
DIVXS B/W Rd ÷ Rs → Rd
Perform s signed division on data in two general registers: either
16 bits ÷ 8 bits → 8-bit quot ient and 8- bit r em ainder or 32 bit s ÷
16 bits → 16-bit quot ient and 16- bit r em ainder
CMP B/W/L Rd - Rs, Rd - #IMM
Compares dat a in a general regist er with dat a in anot her
general r egist er or with imm ediate data, and set s CCR bits
according to the r esult
NEG B/W/L 0 - Rd → Rd
Takes the two's com plement ( ar ithm et ic complement ) of data in
a general register
EXTU W/L Rd (zero extension) → Rd
Extends the lower 8 bits of a 16- bit r egist er t o word size, or t he
lower 16 bits of a 32- bit r egist er t o longword size, by padding
with zeros on the left
EXTS W/L Rd (sign extension) → Rd
Extends the lower 8 bits of a 16- bit r egist er t o word size, or t he
lower 16 bits of a 32- bit r egist er t o longword size, by ext ending
the sign bit
TAS B @ERd - 0, 1 → (<bit 7> of @ERd)
Tests mem or y cont ents, and set s t he m ost significant bit ( bit 7)
to 1
Note: *Size refer s t o t he oper and size.
B: Byte
W: Word
L: Longword
Rev. 1.0, 02/ 00, page 39 of 1141
Tabl e 2 .5 Logi c Instr ucti o ns
Instruction Size*Function
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Perfor m s a logical AND operation on a general register and
another gener al r egister or immediat e dat a
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Perfor m s a logical OR operat ion on a general r egister and
another gener al r egister or immediat e dat a
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Perfor m s a logical exclusive OR operation on a general r egister
and another gener al r egister or immediat e dat a
NOT B/W/L ~ Rd → Rd
Takes the one's complem ent ( logical complement ) of gener al
register contents
Note: *Size refers t o t he oper and size.
B: Byte
W: Word
L: Longword
Tabl e 2 .6 Shift Instruc tions
Instruction Size*Function
SHAL
SHAR B/W/ L Rd (shift ) → Rd
Perfor m s an ar it hm et ic shift on general regist er cont ent s
A 1-bit or 2- bit shif t is possible
SHLL
SHLR B/W/ L Rd (shif t ) → Rd
Perfor m s a logical shift on gener al regist er cont ents
A 1-bit or 2- bit shif t is possible
ROTL
ROTR B/W/L Rd (rotate) → Rd
Rotates general regist er cont ent s
1-bit or 2- bit r ot ation is possible
ROTXL
ROTXR B/W/L Rd (rotate) → Rd
Rotates general regist er cont ent s t hr ough t he car r y f lag
1-bit or 2- bit r ot ation is possible
Note: *Size refers t o t he oper and size.
B: Byte
W: Word
L: Longword
Rev. 1.0, 02/ 00, page 40 of 1141
Tabl e 2 .7 Bit M a ni pul a t i o n Instruc tions
Instruction Size*Function
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general regist er or m em or y oper and to
1. The bit num ber is specified by 3-bit imm ediat e dat a or the
lower three bit s of a gener al r egister
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memor y oper and
to 0. The bit num ber is specified by 3- bit im m ediate data or t he
lower three bit s of a gener al r egister
BNOT B ~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Invert s a specif ied bit in a general register or m em or y oper and.
The bit number is specified by 3-bit imm ediate data or t he lower
three bit s of a gener al r egister
BTST B ~ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general regist er or m em or y oper and
and sets or clears t he Z flag accordingly. The bit number is
specified by 3-bit imm ediate data or t he lower t hr ee bit s of a
general register
BAND B C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry f lag with a specified bit in a general regist er or
memor y oper and and st or es t he r esult in the carry f lag
BIAND B C ∧ [~(<bit-No.> of <EAd>)] → C
ANDs the carry f lag with t he inverse of a specified bit in a
general register or m em or y oper and and st or es t he result in the
carry flag
The bit number is specified by 3-bit imm ediat e dat a
BOR B C ∨ (<bit-No.> of <EAd>) → C
ORs the car r y f lag with a specified bit in a general register or
memor y oper and and stores t he r esult in the car r y flag
BIOR B C∨ [~(<bit-No.> of <EAd>)] → C
ORs the car r y flag with the inverse of a specif ied bit in a general
register or memory oper and and st or es t he r esult in the car r y
flag
The bit number is specified by 3-bit imm ediat e dat a
Rev. 1.0, 02/ 00, page 41 of 1141
Instruction Size*Function
BOXR B C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carr y f lag with a specified bit in a general
register or m em or y oper and and stores t he r esult in the car r y
flag
BIXOR B C ⊕ [~ (<bit-No.> of <EAd>)] → C
Exclusive-ORs the carr y f lag with the inverse of a specif ied bit in
a general register or m em or y oper and and st or es the result in
the carr y f lag
The bit number is specified by 3-bit imm ediate data
BLD B (<bit-No.> of <EAd>) → C
Transfer s a specified bit in a general r egister or mem or y
operand to the carr y f lag
BILD B ~ (<bit-No.> of <EAd>) → C
Transfer s t he invers e of a specified bit in a gener al regist er or
memor y oper and t o t he car r y f lag
The bit number is specified by 3-bit imm ediat e dat a
BST B C → (<bit-No.> of <EAd>)
Transfer s t he car r y flag value to a specified bit in a general
register or m em or y oper and
BIST B ~ C → (<bit-No.> of <EAd>)
Transfer s t he invers e of t he car r y f lag value to a specified bit in
a general register or m em or y oper and
The bit number is specified by 3-bit imm ediat e dat a
Note: *Size refers t o t he oper and size.
B: Byte
Rev. 1.0, 02/ 00, page 42 of 1141
Tabl e 2 .8 Bra nc h Inst r uc t i o ns
Instruction Size*Function
Bcc Branches to a specif ied address if a specif ied condition is true
The branching conditions are listed below
JMP Branches unconditionally to a specified address
BSR Branches to a subroutine at a specified address
JSR Branches to a subrout ine at a specif ied address
RTS Returns fr om a subr out ine
Mnemonic Description Condition
BRA (BT) Always (Tr u e) Alwa ys
BRN (BF) Never (False) Never
BHI HIgh CVZ = 0
BLS Low of Sam e CVZ = 1
BCC (BHS) Carr y Clea r ( High o r
Same) C = 0
BCS (BLO) Carry Set (LOw) C = 1
BNE Not Equal Z = 0
BEQ EQual Z = 1
BVC oVerflow Clear V = 0
BVS oVerflow Set V = 1
BPL PLus N = 0
BMI MInus N = 1
BGE Gr eater or Equal NV = 0
BLT Less Than N ⊕ V = 1
BGT Greater Than Z∨ (N ⊕ V) = 0
BLE Less or Equal Z∨ (N ⊕ V) = 1
Rev. 1.0, 02/ 00, page 43 of 1141
Tabl e 2 .9 Syste m Co nt r o l Inst r uc t i o ns
Instruction Size*Function
TRAPA Start s t r ap- instr uct ion except ion handling
RTE Returns f r om an except ion- handling rout ine
SLEEP Causes a transition t o a power- down stat e
LDC B/W (EAs) → CCR, (EAs) → EXR
Moves content s of a gener al r egister or m em or y or imm ediat e
data t o CCR or EXR. Although CCR and EXR are 8-bit
register s, word- s ize t r ansf er s ar e per form ed bet ween t hem and
memor y . The upper 8 bits ar e valid
STC B/W CCR → (EAd), EXR → (EAd)
Transf ers CCR or EXR c ont ents t o a gener al r egis t er or
mem or y . Although CCR and EXR are 8-bit regist er s , wor d-size
transfers ar e per form ed bet ween t hem and m em or y. The upper
8 bits are valid
ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs t he CCR or EXR cont ents wit h im m ediate dat a
ORC B CCR∨ #IMM → CCR, EXR∨ #IMM → EXR
Logically O Rs the CCR or EXR c ont ents wit h im mediate data
XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exc lusiv e- ORs t he CCR or EXR c ontents with
immediate dat a
NOP PC + 2 → PC
Only increment s t he pr ogr am count er
Note: *Size refers t o t he oper and size.
B: Byte
W: Word
Rev. 1.0, 02/ 00, page 44 of 1141
Table 2.10 Block Data Tr ansfe r Instr uct i ons
Instruction Size*Function
EEPMOV.B if R4L ≠ 0 t hen
Repeat @ER5+→@er6+
R4L−1→R4L
Unt il R4L = 0
else next;
EEPMOV.W if R4 ≠ 0 t hen
Repeat @ER5+→@er6+
R4−1→R4
Unt il R4 = 0
else next;
Transfer s a dat a block according t o par am et er s set in general
registers R4L or R4, ER5, and ER6
R4L or R4: size of block (bytes)
ER5: start ing source addr ess
ER6: starting destination address
Execution of the next inst r uct ion begins as soon as the t r ansf er
is co mpleted
Rev. 1.0, 02/ 00, page 45 of 1141
2.6. 4 Basic Instr uct i on F or mats
The CPU inst ructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (op field), a register field (r field), an effective address extensi on (EA field), and a
condition field (cc).
Figure 2.13 shows examples of instruction formats.
op
op rn rm
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B@(d:16, Rn), Rm, etc.
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
rn rm
op
EA (disp)
(4) Operation field, effective address extension, and condition field
op cc EA (disp) BRA d:16, etc.
Fig ure 2.13 Instruc ti on F or mats (Exampl e s)
(1) Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
(2) Register Field
Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits
or 4 bits. Some instructions have two register fields. Some have no register field.
(3) Effective Address Extensi on
Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
(4) Condition Field
Specifies the branching condition of Bcc instructions.
Rev. 1.0, 02/ 00, page 46 of 1141
2. 6.5 Notes on Use o f Bit- M a ni pul a t i o n Instruct i o ns
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit
manipulation, then write back the byte of data. Caution is therefore required when using these
instructions on a register containing write-only bits, or a port.
The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the
relevant flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt
handling routine, etc.
Rev. 1.0, 02/ 00, page 47 of 1141
2.7 Addressing Modes and Effective Address Calculation
2.7.1 Addressi ng Mode
The CPU supports the eight addressing modes listed in table 2. 11. Each instruction uses a subset
of these addressing modes. Arithmetic and logic instructions can use the register direct and
immediate modes. Data transfer instructions can use all addressing modes except program-
counter relative and memory indirect. Bit-manipulation instructions use register direct, register
indirect, or absolute addressi ng mode to specify an operand, and register direct (BSET, BCLR,
BNOT, and BTST inst ructions) or immediate (3-bit) addressing mode to specify a bit number in
the opera nd.
Tabl e 2 .11 Addr e ssing M o de s
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn)/ @ ( d: 32,ERn)
4 Register indirect with post- increm ent
Register indirect with pre- decr ement @ERn+
@-ERn
5 Absolute address @aa: 8/ #@ aa: 16/@aa: 24/@aa: 32
6 Immediate #xx:8/#xx:16/#xx:32
7 Program - count er relative @(d:8,PC)/ @ ( d:16,PC)
8 Memor y indirect @@aa:8
(1) Register Direct–Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register
containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0
to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as
32-bit regi ste rs.
(2) Register Indirect–@Ern
The register field of the instruction code specifies an address register (ERn) which contains
the address of the operand in memory. If the address is a program instruction address, the
lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00).
(3) Register Indirect with Displacement–@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction is added to an address register
(ERn) specified by the register field of the instruction, and the sum gives the address of a
memory operand. A 16-bit displacement is sign-extended when added.
Rev. 1.0, 02/ 00, page 48 of 1141
(4) Register Indirect with Post-Increment or Pre-Decrement–@ERn+ or @-ERn
(a) Register indirect with post-increment–@ERn+
The register field of the instruction code specifies an address register (ERn) which
contains the address of a memory operand. After the operand is accesse d, 1, 2, or 4 is
added to t he addre ss registe r cont e nts and t he sum is stored i n t he a ddre ss register. T he
value added is 1 for byte access, 2 for word access, or 4 for longword access. For word
or longword access, the register value should be even.
(b) Register indirect with pre-decrement–@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register
field in the instruction code, and the result becomes the address of a memory operand.
The result is also stored in the address register. The value subtracted is 1 for byte access,
2 for word access, or 4 for longword access. For word or longword access, the register
value should be e ven.
(5) Absol ute Addr e ss–@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute
address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits
long (@aa:32).
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1
(H'FFFF). For a 16-bi t ab sol ut e a ddre ss th e uppe r 16 bit s a re a si gn e xt e nsi on. A 32-bi t
absolute address can access the entire address space.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The
upper 8 bits are all assumed to be 0 (H'00).
Table 2.12 indicates the accessi ble absolute address ranges.
Tabl e 2 .12 Absolute Addre ss Ac c e ss Ra ng e s
Absolute Addr ess Normal M ode Advanced Mode
8 bits
(@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF
16 bits
(@aa:16) H'000000 to H007FFF, H'FF8000 to
H'FFFFFF
Data address
32 bits
(@aa:32)
Program inst r uct ion
address 24 bits
(@aa:24)
H'0000 to H'FFFF
H'000000 to H'FFFFFF
Rev. 1.0, 02/ 00, page 49 of 1141
(6) Immediate –#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as
an operand.
The ADDS, SUB S, I NC , and DE C i n st r uctions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a
bit nu m b e r . The TRAPA i n st r uction contains 2-bit immediate data in its instruction code,
specifying a ve ct or a ddress.
(7) P rogr am-Counter Relati ve–@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement
contained in the instruction is si gn-extended and added to the 24-bit PC contents to generate
a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are
all assumed to be 0 (H'00). The PC value to which the displacement is added is the address
of the first byt e of the ne xt i nstruc ti on, so the possible bra nc hing ra nge is -126 to + 128 byt es
(-63 to +64 words) or -32766 to +32768 byte s (-16383 to + 16384 words) from the bra nc h
instructi on. T he re sult ing va l ue should be a n eve n num ber.
(8) Memory Indirect–@@aa:8
This m od e ca n b e u se d b y the JMP a n d JSR inst r u ctions. The instruction code contains an 8-
bit absolute address specifying a memory operand. This memory operand contains a branch
address. The upper bits of the absolute address are all assumed to be 0, so the address range
is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).
In normal mode the memory operand is a word operand and the branch address is 16 bits
long. In advanced mode the memory operand is a longword operand, the first byte of which
is assumed to be all 0 (H'00).
Note that the first part of the address range is also the exception vector area. For further
details, see section 5, Exception Handling.
(a) Normal Mode*
Note: * Not available for this LSI
(b) Advanced Mode
Branch address Specified by
@aa:8
Specified by
@aa:8 Reserved
Branch address
Figure 2.14 Branch Address Specification in Memory Indirect Mode
Rev. 1.0, 02/ 00, page 50 of 1141
If an odd address is specified in word or longword memory access, or as a branch address,
the least significant bit is regarded as 0, causing data to be accessed or an instruction code to
be fetched at the address preceding the specified address. (For further information, see
section 2.5.2, Memory Data Formats. )
2.7.2 Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode.
In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit
address.
Rev. 1.0, 02/ 00, page 51 of 1141
Table 2.13 Effective Address Calculation
No. Addressing M ode and
Inst r uct i on For m at Eff ective Address
Calculat ion Effect i ve Addr ess ( EA)
1 Register direct ( Rn)
op rm rn
Operand is gener al regist er
contents
2 Register indirect ( @ ERn)
General register contents
31 0 31 0
rop
24 23
Don’t
care
3 Register indirect with displacement
@(d:16, ERn) or @ ( d: 32, ERn)
General register contents
Sign extension disp
31 0
31 0
31 0
op r disp Don’t
care
24 23
4 Register indirect with post - increm ent or pr e- decr em ent
• Register indirect with post- increm ent @ ERn+
General register contents
1, 2, or
4
31 0 31 0
r
op
Don’t
care
24 23
• Register indirect with pre- decr ement @–ERn
General register contents
1, 2, or
4
Byte
Word
Longword
1
2
4
Operand
Size Value
Added
31 0
31 0
op rDon’t
care
24 23
Rev. 1.0, 02/ 00, page 52 of 1141
No. Addressing M ode and
Inst r uct i on For m at Eff ective Address
Calculat ion Effect i ve Addr ess ( EA)
5 Absolute address
@aa:8
@aa:16
@aa:32
31 08 7
@aa:24
31 016 15
31 0
31 0
op abs
op abs
abs
op
op
abs
H'FFFF
24 23
Don’t
care
Don’t
care
Don’t
care
Don’t
care
24 23
24 23
24 23
Sign
exten-
sion
6 Im m ediat e #xx: 8/ #xx: 16/ #xx: 32
op IMM
Operand is imm ediat e dat a
7 Progr am - count er relative
@(d:8, PC)/ @ ( d:16, PC)
0
0
23
23
disp 31 0
24 23
op disp
PC contents
Don’t
care
Sign
exten-
sion
Rev. 1.0, 02/ 00, page 53 of 1141
No. Addressing M ode and
Inst r uct i on For m at Eff ective Address
Calculat ion Effect i ve Addr ess ( EA)
8 Mem or y indirect @@aa: 8
• Nor m a l mode
0
0
31 8 7
0
15
H'000000 31 0
16 15
op abs
abs
Memory
contents
H'00
24 23
Don’t
care
• Advanced mode
31
0
31 8 7
0
abs
H'000000
31 0
24 23
op abs
Memory contents Don’t
care
Rev. 1.0, 02/ 00, page 54 of 1141
2.8 P rocessin g S t at es
2.8.1 Overview
The CPU has four main processing states: the reset state, exception-handling state, program
execution state, and power-down state. Figure 2.15 shows a diagram of the processing states.
Figure 2.16 indicates the state transitions.
Reset state
The CPU and all on-chip supporting modules have been initialized and are stopped.
Exception-handling
state
A transient state in which the CPU changes the normal processing flow in response
to a reset, interrupt or trap instruction.
Program execution
state
The CPU executes program instructions in sequence.
Power-down state
CPU operation is stopped
to conserve power.*
Sleep mode
Standby mode
Processing
states
Note: *
The power-down state also includes a medium-speed mode, modue stop mode, sub-active mode,
sub-sleep mode and watch mode.
Figure 2. 15 P r oce ssing States
Rev. 1.0, 02/ 00, page 55 of 1141
Reset state
Exception-handling state
Sleep mode
Standby mode
Power-down state
Program execution state
Interrupt request
External interrupt request
= High
Request for exception handling
SLEEP instruction
with LSON=0,
SSBY=1,
TMA3=0
SLEEP instruction
with LSON=0,
SSBY=0
Notes:
End of exception handling
*1
*2
1.
2.
From any state, a transition to the reset state occurs whenever goes low. A transition can
also be made to the reset state when the watchdog timer overflows.
The power-down state also includes a watch mode, subactive mode, subsleep mode, etc. For
details, see section 4, Power-Down State.
Figure 2. 16 State Tr ansitions
2.8.2 Reset State
When the
5(6
input goes low all current processing stops and the CPU enters the reset state.
All interrupts are disabled in the reset state. Reset exception handling starts when the
5(6
signal cha nge s from low to hi gh.
The reset state can also be entered by a watchdog timer overflow. For details, see section 17,
Watchdog Timer.
Rev. 1.0, 02/ 00, page 56 of 1141
2.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address
(vector) from the exception vector table and branches to that address.
(1) T ypes of Exc e pti on Handl ing a nd T hei r Priori ty
Exception handling is performed for resets, interrupts, and trap instructions. Table 2.14
indicates the types of exception handling and their priority. Trap instruction exception
handling is always accepted in the program execution state.
Exception handling and the stack structure depend on the interrupt control mode set in
SYSCR.
Table 2.14 Exception Handling Types and Priority
Prior i ty Type of Excepti on Detection Timi ng St ar t of Except ion Handli ng
Reset Synchronized with
clock Exception handling start s
immediately af t er a low-t o- high
transit ion at the
5(6
pin, or when the
watchdog timer overf lows
Inter r upt End of instruct ion
execution or end of
exception-handling
sequence*1
When an interr upt is request ed,
exception handling start s at the end
of the cur rent instr uct ion or current
exception-handling sequence
High
Low Trap instr uct ion When TRAPA
instruction is executed Exception handling start s when a tr ap
(TRAPA) instr u c tion is ex e c u t e d*2
Notes: 1. Int errupt s ar e not detected at the end of t he ANDC, ORC, XORC, and LDC
instructions, or imm ediately af t er r eset except ion handling.
2. Tr ap instr uct ion except ion handling is always accepted in the progr am execution state.
(2) Reset Exception Handling
After the
5(6
pin has gone low and the reset state has been entered, when
5(6
goes high
again, reset exception handling starts. When reset exception handling starts the CPU fetches
a start address (vector) from the exception vector table and starts program execution from
that a ddre ss. All i nte rrupt s, i ncl udi ng NMI, are disabl e d during re set exc e pti on ha ndli ng a nd
after it ends.
(3) Interrupt Exception Handling and Trap Instruction Exception Handling
When interrupt or trap-instruction exception handling begins, the CPU references the stack
pointer (ER7) and pushes the program counter and other control registers onto the stack.
Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the
CPU fetches a start address (vector) from the exception vector table and program execution
starts from tha t start a ddress.
Rev. 1.0, 02/ 00, page 57 of 1141
Figure 2.17 shows the stack after exception handling ends.
PC
(16 bits)
SP CCR
CCR
*1
PC
(24 bits)
SP CCR
Normal Mode Advanced Mode
*2
Notes: 1. Ignored when returning.
2. Normal mode is not available for this LSI.
Figure 2. 17 Stack Structure afte r Exce ption Handling (Examples)
2.8.4 Pr ogram Exe c ution State
In this state the CPU executes program instructions in se quence.
Rev. 1.0, 02/ 00, page 58 of 1141
2.8.5 Power-Down State
The power-down state includes both modes in which the CPU stops operating and modes in
which the CPU does not stop. There are five modes in which the CPU stops operating: sleep
mode, standby mode, subsleep mode, and watch mode. There are also three other power-down
modes: medium-speed mode, module stop mode, and subactive mode. In medium-speed mode,
the CPU operates on a medium-speed clock. Module stop mode permits halting of the operation
of individual modules, other than the CPU. Subactive mode, subsleep mode, and watch mode
are power-down modes that use subclock input. For details, see section 4, Power-Down State.
(1) Sleep Mode
A transition to sleep mode is made if the SLEEP instruction is executed while the software
standby bi t (SSBY) i n t he sta ndby c ont rol re gist e r (SBYCR) a nd t he L SON bi t i n t he l ow-
power control register (LPW RCR) are both cleared to 0. In sleep mode, CPU operations st op
immediately after execution of the SLEEP instruction. The contents of CPU registers are
retained.
(2) Sta ndby Mode
A transition to standby mode is made if the SLEEP instruction is executed while the SSBY
bit i n SBYCR i s set t o 1 a nd t he L SON bit i n L PWRCR a nd t he T MA3 bi t in th e T MA
(timer A) are both cleared to 0. In standby mode, the CPU and clock halt and all MCU
operations stop. As long as a specified voltage is supplied, the contents of CPU registers and
on-chip RAM are retained.
Rev. 1.0, 02/ 00, page 59 of 1141
2.9 Basic Tim ing
2.9.1 Overview
The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising e dge
of φ to the next is referred to as a “state.” The memory cycle or bus cycle consists of one or two
states. Different methods are used to access on-chip memory and on-chip supporting modules.
2.9.2 On-Chip Memory (ROM , RAM)
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 2.18 shows the on-chip memory access cycle.
Internal address bus
Internal read signal
Internal data bus
Internal write signal
Internal data bus
φ
Bus cycle
T1
Address
Read data
Write data
Read access
Write access
Figure 2. 18 On-Chip Memory Access Cycle
Rev. 1.0, 02/ 00, page 60 of 1141
2. 9.3 On-Chip Suppor t i ng M o dul e Access T i m i ng
The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16
bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows
the access timing for the on-chip supporting modules.
Internal address bus
Internal read signal
Internal data bus
Internal write signal
Internal data bus
φ
Bus cycle
T1
Address
Read access
Write access
Read data
Write data
T2
Fi g ur e 2 .19 O n- Chi p Suppo r t i ng M o dul e Access Cycle
Rev. 1.0, 02/ 00, page 61 of 1141
Section 3 MCU Operating Modes
3.1 Overview
3.1.1 Operating Mode Selection
This LSI has one operating mode (mode 1). This mode is selected depending on settings of the
mode pin (MD0).
Table 3.1 lists the MCU operating modes.
Table 3.1 MCU Operating Mode Selection
MCU Oper at i ng Mode MD0 CPU Operat ing Mode Descript ion
00
1 1 Advanced Single-chip mode
The CPU's architecture allows for 4 Gbytes of address space, but this LSI actually accesses a
maximum of 16 Mbytes.
Mode 1 operation starts in single-chip mode after reset release.
This LSI can only be used in mode 1. This means that the mode pins must be set at mode 1. Do
not changes the inputs at the mode pins during operation.
3.1.2 Register Configuration
This LSI has a mode control register (MDCR) that indicates the inputs at the mode pin (MD0)
and a system control register (SYSCR) and that controls the operation of this LSI. Table 3.2
summarizes these registers.
Table 3.2 MCU Registers
Name Abbreviation R/W Initial Value Address*
Mode contr ol r egister M DCR R Undeterm ined H'FFE9
Syst e m con t rol r e gis ter SYSCR R/W H'09 H'FFE8
Note: *Lower 16 bits of t he addr ess.
Rev. 1.0, 02/ 00, page 62 of 1141
3.2 Register Descripti on s
3. 2.1 Mo de Co nt r o l Re g i st e r (M DCR)
0
—*
1
0
2
0
3
0
4
0
5—————
0
6
—
0
7
—
——————
—R
MDS0
0
Bit :
Initial value :
R/W
:
Note: *
Determined by MD0 pin
MDCR is an 8-bit read-only register monitors the current operating mode of this LSI.
Bit 7 to 1: Reserved.
These bit s ca nnot be m odifi e d and a re al ways rea d as 0.
Bit 0: Mode Select 0 (MDS0)
This bit indicates the value which reflects the input levels at mode pin (MD0) (the current
operat ing m ode ). Bi t MDS0 corre sponds t o MD0 pi n. Th ey a re re ad-onl y bi t s-the y ca nnot be
written to. The mode pin (MD0) input levels are latched into these bits when MDCR is read.
3. 2.2 System Co ntrol Regi st e r ( SYSCR)
0
—
1
1
0
—
2
0
—
3
1
4
0
R/W
5
0
6
—
0
7
—
——— RR
INTM1 INTM0 XRST — —
0
Bit :
Initial value :
R/W :
Bits 7 and 6Reserved: These bi t s cannot be modi fi ed a nd a re a l ways read a s 0.
Rev. 1.0, 02/ 00, page 63 of 1141
Bits 5 and 4Interrupt c o nt r o l m odes 1 and 0 ( INTM1, INTM 0 )
These bits are for selecting the interrupt control mode of the interrupt controller. For details of
the interrupt control modes, see section 6.4.1, Interrupt Control Modes and Interrupt Operation.
Bit 5 Bit 4
INTM1 INTM0 Interrupt
Control Mode Descr i ption
0 0 Int er r upt is cont r olled by bit I (Init ial value)0
1 1 Int er r upt is cont r olled by bits I and UI, and ICR
0Cannot be used in this LSI1
1Cannot be used in this LSI
Bit 3External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a
reset can be generated by watchdog timer overflow as well as by external reset input. XRST is a
read-only bit. It is set to 1 by an external reset and cleared to 0 by watchdog timer overflow.
Bit 3
XRST Description
0 A reset is gener at ed by wat chdog t im er over f low
1 A reset is generat ed by an external reset (Initial value)
Bits 2 and 1Reserved: These bi t s cannot be modi fi ed a nd a re a l ways read a s 0.
Bit 0Reserved: This bit is always read as 1.
3.3 Operat in g Mod e (Mod e 1)
The CPU can access a 16 Mbyte address space in advanced mode.
Rev. 1.0, 02/ 00, page 64 of 1141
3.4 Add ress Map in Each O perating Mod e
H8S/2196 H8S/2197
Memory indirect
branch address
Absolute address, 16 bits
3 kbytes
Vector area
On-chip ROM
(80 kbytes)
Internal I/O register
Internal I/O register
On-chip RAM
Vector area
On-chip ROM
(96 kbytes)
Internal I/O register
Internal I/O register
OSD ROM
(24 kbytes)
On-chip RAM
H'000000 H'000000
H'017FFF
H'FFD000
H'040000
H'045FFF
H'FFD2FF
H'FFD800
H'FFDAFF
H'FFF3B0
H'FFFFAF
H'FFFFB0
H'FFFFFF
H'0000FF
H'007FFF
H'013FFF
H'FF8000
H'FFD000
H'FFD2FF
H'FFF3B0
H'FFFF00
H'FFFFAF
H'FFFFB0
H'FFFFFF
OSD RAM (768 bytes)
OSD ROM
(24 kbytes)
H'040000
H'045FFF
H'FFD800
H'FFDAFF
OSD RAM (768 bytes)
Absolute address,
8 bits
Absolute address, 16 bits
Figure 3.1 Address Map (1)
Rev. 1.0, 02/ 00, page 65 of 1141
H8S/2198 H8S/2199
Vector area
On-chip ROM
(112 kbytes)
Internal I/O register
Internal I/O register
On-chip RAM
Vector area
On-chip ROM
(128 kbytes)
Internal I/O register
Internal I/O register
On-chip RAM
H'000000 H'000000
H'01FFFF
H'FFD000
H'FFD2FF
H'FFF3B0
H'FFFFAF
H'FFFFB0
H'FFFFFF
H'01BFFF
H'FFD000
H'FFD2FF
H'FFF3B0
H'FFFFAF
H'FFFFB0
H'FFFFFF
OSD ROM
(24 kbytes)
H'040000
H'045FFF
H'FFD800
H'FFDAFF
OSD RAM (768 bytes)
OSD ROM
(24 kbytes)
H'040000
H'045FFF
H'FFD800
H'FFDAFF
OSD RAM (768 bytes)
Figure 3.2 Address Map (2)
Rev. 1.0, 02/ 00, page 67 of 1141
Section 4 Po wer-Down State
4.1 Overview
In addition to the normal program execution state, this LSI has a power-down state in which
operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power
operation can be achieved by individually controlling the CPU, on-chip supporting modules, and
so on.
This LSI operating modes are as follows:
1. High-speed m ode
2. Medium -spee d mode
3. Sub-active mode
4. Sleep mode
5. Sub-sleep mode
6. Watch mode
7. Module stop m ode
8. Standby m ode
Of these, 2 to 8 are power-down modes. Certain combinations of these modes can be set.
After a reset , t he MCU is in high-spee d m ode.
Table 4.1 shows the internal chip states in each mode, and table 4.2 shows the conditions for
transition to the various modes. Figure 4.1 shows a mode transition diagram.
Rev. 1.0, 02/ 00, page 68 of 1141
Table 4.1 H8S/2199 Series Internal States in Each Mode
Function High-Speed Medium-
Speed Sleep Module
Stop Watch Sub-active Sub-sleep Standby
System clock Functioning Functioning Functioning Functioning Halted Halted Halted Halted
Subclock pulse generator Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning
Instructions Halted Halted Halted HaltedCPU
operation Registers Functioning Medium-
speed Retained Functioning Retained Subclock
operation Retained Retained
IRQ0
IRQ1 Functioning Functioning Functioning Functioning
IRQ2
IRQ3
IRQ4
External
interrupts
IRQ5
Functioning Functioning Functioning Functioning
Halted Halted Functioning Halted
I/O Functioning Functioning Retained Functioning Halted Functioning Retained Halted
Timer A Functioning Functioning Functioning Functionin
g
/halted
(retained)
Subclock
operation Subclock
operation Subclock
operation Halted
(retained)
Timer B
Timer J
Timer L
Functionin
g
/halted
(retained)
Halted
(retained) Halted
(retained) Halted
(retained) Halted
(retained)
Timer R
On-chip
supporting
module
operation
Timer X1
Functioning Functioning Functioning
Functionin
g
/halted
(reset)
Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset)
Watchdog
timer Functioning Functioning Functioning Functioning Halted
(retained) Halted
(retained) Halted
(retained) Halted
(retained)
8-bit PWM
12-bit PWM*2
14-bit PWM
Functioning Functioning Functioning Functionin
g
/halted
(retained)
Halted
(retained) Halted
(retained) Halted
(retained) Halted
(retained)
PSU Functioning Functioning Functioning Functionin
g
/halted Subclock
operation Subclock
operation Subclock
operation Halted
SCI1 Functionin
g
/halted*1Halted*1Halted*1Halted*1Halted*1
IIC Functionin
g
/halted
(retained)
Halted
(retained) Halted
(retained) Halted
(retained) Halted
(retained)
A/D
Functioning Functioning Functioning
Functionin
g
/halted
(reset)
Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset)
Servo Functioning Functioning Halted
(reset) Functionin
g
/halted
(reset)
Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset)
Sync
separator Functioning Functioning Halted
(retained) Functionin
g
/halted
(retained)
Halted
(retained) Halted
(retained) Halted
(retained) Halted
(retained)
Data slicer Halted
(reset)
OSD
Functioning Functioning Halted
(reset) Functionin
g
/halted
(reset)
Halted
(reset) Halted
(reset) Halted
(reset)
Notes: 1. "Halted (retained)" means that internal r egister values ar e r et ained. The inter nal st at e
is "operation suspended."
2. "Halted (reset )" means that inter nal regist er values and internal st at es ar e initialized.
3. I n m odule st op m ode, only modules f or which a stop set ting has been made are halt ed
(reset or ret ained).
Rev. 1.0, 02/ 00, page 69 of 1141
4. I n t he power - down mode, the analog section of t he ser v o circuit s ar e not turned of f ,
therefore Vcc (Ser vo) cur r ent does not go low. When power- down is needed,
externally shut down the analog syst em power.
*1 The SCI1 stat us differs f r om the internal register . For det ails, r efer t o sect ion 22, Serial
Communication I nt er f ace 1.
*2 The stat e of t he 12-bit PWM is t he sam e as t hat of t he ser v o circuit .
Program-halted state
Conditions for mode transition (1) Conditions for mode transition (2)
Interruption factor
Sleep
(high-speed)
mode
Sleep
(medium-speed)
mode
Subsleep
mode
Program execution state
Reset state
Flag
SLEEP
instruction
Interrupt
LSON SSBY TMA3 DTON
a010*
b*110
c0111
d1111
e00**
f101*
gSCK1 to 0 = 0
h
SCK1 to 0 0 (either 1 bit = 0)
Power-down mode
Active
(high-speed)
mode
Active
(medium-speed)
mode
Subactive
mode
Program-halted state
Watch
mode
Standby
mode
IRQ0
to
1
IRQ0
to
1, Timer A interruption
All interruption (excluding servo system)
IRQ0
to
5, Timer A interruption
1
2
3
4
Interrupt
Interrupt
SLEEP
instruction
SLEEP
instruction
e
Note: When a transition is made between
modes by means of an interrupt,
transition cannot be made on interrupt
source generation alone. Ensure that
interrupt handling is performed after
accepting the interrupt request
SLEEP
instruction a
1
Interrupt
1
2
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
a
b
ghd
SLEEP
instruction
c
e
3
Interrupt 2
Interrupt 3
Interrupt 2Interrupt 4
c
SLEEP
instruction
d
b
b
SLEEP
instruction SLEEP
instruction 1
Note:
*
Don't care
Figure 4. 1 M ode Tr ansitions
Rev. 1.0, 02/ 00, page 70 of 1141
Table 4.2 Power-Down Mode Transition Conditions
Control Bi t St at es at Tim e of
Transition
State bef or e
Transition SSBY TMA3 LSON DTON St at e af t er Tr ansi tion
by SLEEP Ins t ruct ion State af t er Retur n
by Int er r upt
0*0*Sleep High-speed/
medium-speed*1
0*1*
100*Standby High-speed/
medium-speed*1
101*
1100 Watch High-speed/
medium-speed*1
1110 Watch Subactive
1101 
High-speed/
medium-
speed
1111 Subactive
00** 
010*
011*Subsleep Subactive
10** 
1100 Watch High-speed/
medium-speed*2
1110 Watch Subactive
1101 High-speed/
medium-speed*2
Subactive
1111 
Notes: *Don't car e
: Do not set .
1. Retur ns t o t he state bef or e t ransition.
2. M ode var ies depending on the st at e of SCK1 to SCK0.
Rev. 1.0, 02/ 00, page 71 of 1141
4.1.1 Register Configuration
The power-down state is controlled by the SBYCR, LPWRCR, TMA (Timer A), and MSTPCR
registers. Table 4.3 summarizes these registers.
Table 4.3 Power-Down State Registers
Name Abbreviation R/W Initial Value Address*
Standby c ont rol regis t er SBYCR R/W H'00 H'FFEA
Low-power contr ol regist er LPWRCR R/W H'00 H'FFEB
MSTPCRH R/W H'FF H'FFECModule stop cont r ol register
MSTPCRL R/W H'FF H'FFED
Timer m ode r egist er A TMA R/W H'30 H'FFBA
Note: *Lower 16 bits of the address.
Rev. 1.0, 02/ 00, page 72 of 1141
4.2 Register Descri pt i on s
4. 2.1 Standby Co ntrol Regi st e r (SBYCR)
0
0
1
0
R/W
2
0
3
——
——
0
4
0
R/W
5
0
6
0
7
R/WR/W
STS1
R/W
STS2
0
R/W
SSBY STS0 SCK1 SCK0
Bit :
Initial value :
R/W :
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
SBYCR is initialized to H'00 by a reset.
Bit 7Software Standby (SSBY): Determines the operating mode, in combination with other
control bits, when a power-down mode transition is made by executing a SLEEP instruction.
The SSBY setting is not changed by a mode transition due to an interrupt, etc.
Bit 7
SSBY Description
0 Transit ion t o s leep mode afte r exec ut ion of SLEEP inst r uc t ion in high- s peed m ode
or medium - speed m ode
Transit ion to subsleep m ode after execut ion of SLEEP inst r uc t ion in s ubactive
mode (Init ial value)
1 Tr ansition t o st andby m ode, subactive mode, or watch mode aft er execut ion of
SLEEP instr uc t ion in high-speed mode or medium - s peed m ode
Transition to wat ch m ode or high- speed m ode af t er execution of SLEEP
instruction in subactive mode
Rev. 1.0, 02/ 00, page 73 of 1141
Bits 6 to 4Standby T i m e r Select 2 to 0 (STS2 to STS0): These bits select the time the MCU
waits for the clock to stabilize when standby mode, watch mode, or subactive mode is cleared
and a transition is made to high-speed mode or medium-speed mode by means of a specific
interrupt or instruction. With crystal oscillation, see table 4.5 and make a selection according to
the operating frequency so that the standby time is at least 10 ms (the oscillation settling time).
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Description
0 0 0 Standby t im e = 8192 st at es
0 0 1 Standby t im e = 16384 st at es
0 1 0 Standby t im e = 32768 st at es
0 1 1 Standby t im e = 65536 st at es
1 0 0 Standby t im e = 131072 st at es
1 0 1 Standby t im e = 262144 st at es
11*Reserved
Note: *Don't car e
Bits 3 and 2Reserved: These bi t s cannot be modi fi ed a nd a re a l ways read a s 0.
Bits 1 and 0System Clock Select 1, 0 (SCK1, SCK0): These bits select the CPU clock for the
bus master in hi gh-spee d mode a nd me di um-spee d m ode.
Bit 1 Bit 2
SCK1 SCK0 Description
0 0 Bus master is in high-speed mode ( I nitial value)
0 1 Medium- speed clock is φ/16
1 0 Medium- speed clock is φ/32
1 1 Medium- speed clock is φ/64
Rev. 1.0, 02/ 00, page 74 of 1141
4. 2.2 Low-Powe r Control Regi st e r (LPWRCR)
0
0
1
0
R/W R/W
2
0
3
0
4
———
———
0
5
0
6
0
7
R/W
NESEL
R/W
LSON
0
R/W
DTON SA1 SA0
Bit :
Initial value :
R/W :
LPWRCR is an 8-bit readable/writable register that performs power-down mode control.
LPWRCR is initialized to H'00 by a reset.
Bit 7Direct-Transfer on Flag (DTON): Specifies whether a direct transition is made between
high-speed mode, medium-speed mode, and subactive mode when making a power-down
transition by executing a SLEEP instruction. The operating mode to which the transition is
made after SLEEP instruction execution is determined by a combination of other control bits.
Bit 7
DTON Description
0•When a SLEEP inst r uc t ion is ex ecuted in high-s peed m ode or m edium-speed
mode, a transition is made to sleep mode, st andby mode, or wat ch m ode
•When a SLEEP inst r uc t ion is ex ecuted in subact ive mode, a transition is m ade
to subsleep mode or watc h m ode (Init ial value)
1•When a SLEEP inst r uc t ion is ex ecuted in high-s peed m ode or m edium-speed
mode, transition is made dir ect ly t o subact ive mode, or a t r ansit ion is made t o
sleep mode or standby m ode
•When a SLEEP inst r uc t ion is ex ecuted in subact ive mode, a transition is m ade
directly to high- speed m ode, or a tr ansit ion is made t o subsleep mode
Rev. 1.0, 02/ 00, page 75 of 1141
Bit 6Low-Speed on Flag (LSON): Determines the operating mode in combination with other
control bits when making a power-down transition by executing a SLEEP instruction. Also
controls whether a transition is made to high-speed mode or to subactive mode when watch
mode is cleared.
Bit 6
LSON Description
0•When a SLEEP inst r uc t ion is ex ecuted in high-s peed m ode or m edium-speed
mode, transition is made to sleep mode, st andby mode, or wat ch m ode
•When a SLEEP inst r uc t ion is ex ecuted in subact ive mode, a transition is m ade
to watch m ode, or directly t o high-speed mode
•After wat ch m ode is cleared, a t ransition is made to high- speed m ode
(Init ial value)
1•When a SLEEP inst r uc t ion is ex ecuted in high-s peed m ode a t ransit ion is m ade
to watch m ode, subact ive mode, sleep mode or standby mode
•When a SLEEP inst r uc t ion is ex ecuted in subact ive mode, a transition is m ade
to subsleep mode or watc h m ode
•After wat ch m ode is cleared, a tr ansit ion is made t o subact ive m ode
Bit 5Noise Elimination Sampling Frequency Select (NESEL): Selects the frequency at
which the subclock (φw) generated by the subclock pulse generator is sampled with the clock (φ)
generated by the system clock oscillator. When φ = 5 MHz or higher, clear this bit to 0.
Bit 5
NESEL Description
0 Sam pling at φ divided by 16
1 Sam pling at φ divided by 4
Bits 4 to 2Reserved: These bit s cannot be modi fi ed a nd a re a l ways read a s 0.
Bits 1 and 0Subacti v e M o de Cloc k Select 1, 0 (SA1, SA0): These bits select the CPU
operating clock in the subactive mode. These bits cannot be modified in the subactive mode.
Bit 1 Bit 0
SA1 SA0 Description
0 0 Oper at ing clock of CPU is φw/8 (Initial va lu e )
0 1 Oper at ing clock of CPU is φw/4
1*Operat ing clock of CPU is φw/2
Note: *Don’t care
Rev. 1.0, 02/ 00, page 76 of 1141
4.2.3 Time r Regi ster A (TMA)
0
0
1
0
R/W
2
0
3
0
4
1
5
——
1
6
0
7
R/WR/WR/WR/W
TMA3
R/W
TMA2
R/W
TMAIE
0
R/(W)*
TMAOV TMA1 TMA0
Bit :
Initial value :
R/W :
Note: *
Only 0 can be written, to clear the flag.
The timer register A (TMA) controls timer A interrupts and selects input clock.
Only bit 3 is explained here. For details of other bits, see section 11.2.1, Timer Mode Register
A.
TMA is a readable/writable register which is initialized to H'30 by a reset.
Bit 3Clock Source, Prescaler Select (TMA3): Selects timer A clock source between PSS and
PSW. It also controls transition operation to the power-down mode. The operation mode to
which the MCU is transited after SLEEP instruction execution is determined by the combination
with other c ont rol bi t s.
For details, see the description of clock select 2 to 0 in section 11.2.1, Timer Mode Register A.
Bit 3
TMA3 Description
0•Timer A counts φ-based prescaler (PSS) div ided clock pulse s
•When a SLEEP instruction is ex ecuted in high-speed m ode or medium- speed
mode, a transition is made to sleep mode or sof tware standby m ode
(Init ial value)
1•Timer A counts φw-based prescaler ( PSW) divided clock pulses
•When a SLEEP inst r uc t ion is ex ecuted in high-s peed m ode or m edium-speed
mode, a transition is made to sleep mode, wat ch m ode, or subact ive mode
•When a SLEEP inst r uc t ion is ex ecuted in subact ive mode, a transition is m ade
to subsleep mode, watc h m ode, or high- speed m ode
Rev. 1.0, 02/ 00, page 77 of 1141
4. 2.4 Module Sto p Co ntrol Re g i st e r (M ST P CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode
control.
MSTPCR is initialized to H'FFFF b y a r e se t.
MSTRCRH and M ST P CRL B i t s 7 t o 0M odule Stop (MSTP 15 to MSTP 0): These bits
specify module stop mode. See table 4.4 for the method of selecting on-chip supporting
modules.
MSTPCRH, M STPCRL
Bits 7 to 0
MSTP 15 to MSTP 0 Descripti on
0 Module stop mode is cleared
1 Module stop mode is set (Initial value)
Rev. 1.0, 02/ 00, page 78 of 1141
4.3 Mediu m - S peed Mod e
When the SCK1 and SCK0 bits in SBYCR are set to 1 in high-speed mode, the operating mode
changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU
operates on the operating clock (φ16, φ32 or φ64) specified by the SCK1 and SCK0 bits. The
on-chip supporting modules other than the CPU always operate on the high-speed clock (φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect
to the bus master operating clock. For example, if φ16 is selected as the operating clock, on-
chip memory is accessed in 16 states, and internal I/O registers in 32 states.
Medium-speed mode is cleared by clearing the both bits SCK1 and SCK0 to 0. A transition is
made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON b i t in
LPWRCR are cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by
an inte rrupt , me di um-spee d m ode i s restore d.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, and the LSON b i t
in LPWRCR and the TMA3 bit in TMA (Timer A) are both cleared to 0, a transition is made to
software standby mode. When standby mode is cleared by an external interrupt, medium-speed
mode is restore d.
When the
5(6
pin is driven low, a transition is made to the reset state, and medium-speed mode
is cleared. The same applies in the case of a reset caused by overflow of the watchdog timer.
Figure 4.2 shows the timing for transition to and clearance of medium-speed mode.
Medium-speed mode
Internal φ,
supporting module clock
CPU clock
Internal address bus
Internal write signal
SBYCR SBYCR
Figure 4.2 Medium-Speed Mode Transition and Clearance Timing
Rev. 1.0, 02/ 00, page 79 of 1141
4.4 Sleep Mod e
4.4.1 Sleep Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON b i t in
LPWRCR are both cleared to 0, the CPU will enter sleep mode. In sleep mode, CPU operation
stops but the contents of the CPU's internal registers are retained. Other supporting modules
(excludi ng some funct i ons) do not stop.
4.4.2 Clearing Sleep Mode
Sleep mode is cleared by any interrupt, or with the
5(6
pin.
Clearing with an Interrupt: When an interrupt request signal is input, sleep mode is cleared
and interrupt exception handling is started. Sleep mode will not be cleared if interrupts are
disabled, or i f i nte rrupt s other t ha n NMI have bee n m asked by t he CPU.
Clearing with the
5(6
5(6
Pin: When the
5(6
pin is driven low, the reset state is entered. When
the
5(6
pin is driven hi gh a fte r t he pre scri bed re set input pe riod, t he CPU begins reset e xc ept i on
handling.
Rev. 1.0, 02/ 00, page 80 of 1141
4.5 Module Stop Mode
4.5.1 Module Stop Mode
Module stop mode c a n be set for i ndivi dua l on-c hi p supporting m odul es.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
Table 4. 4 shows MSTP bits and the on-chi p supporting m odul es.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating again at the end of the bus cycle. In module stop mode, the internal states of
modules excluding some modules are retained.
After reset release, all modules are in module stop mode.
When an on-chip supporting module is in module stop mode, read/write access to its registers is
disabled.
Tabl e 4 .4 MSTP B i t s a nd Corr e spo ndi ng O n- Chi p Suppo r t i ng M o dul e s
Register Bit Module
MSTP15 Timer A
MSTP14 Timer B
MSTP13 Timer J
MSTP12 Timer L
MSTP11 Timer R
MSTP10 Timer X1
MSTP9 Sync separator
MSTPCRH
MSTP8 Serial communication interf ace 1 ( SCI1)
MSTP7 I2C bus interf ace ( I I C0)
MSTP6 I2C bus interf ace ( I I C1)
MSTP5 14-bit PWM
MSTP4 8-bit PWM
MSTP3 Data slicer
MSTP2 A/D converter
MSTP1 Ser vo circuit
MSTPCRL
MSTP0 OSD
Rev. 1.0, 02/ 00, page 81 of 1141
4.6 Standby Mode
4. 6.1 Standby M o de
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bi t in
LPWRCR is cleared to 0, and the TMA3 bit in TMA (Timer A) is cleared to 0, standby mode
will be entered. In this mode, the CPU, on-chip supporting modules, and oscillator (except for
subclock oscillator) all stop. However, the contents of the CPU's internal registers and data in
the on-chip RAM, as well as on-chip peripheral circuits (with some exceptions), are maintained
in the current state. (Timer X1 and SCI1 are partially reset.) The I/O port, at this time, is
caused to the high impedance state.
In this mode the oscillator stops, and therefore power dissipation is si gnificantly reduced.
4.6.2 Cle a r i ng St andby M o de
Standby mode is cleared by an external interrupt (pin
,54
to
,54
), or by means of the
5(6
pin.
Clearing with an Interrupt: When an
,54
to
,54
interrupt re quest signa l is input , c loc k
oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable
clocks are supplied to the entire chip, standby mode is cleared, and interrupt exception handling
is started.
Standby mode cannot be cleared with an
,54
to
,54
interrupt i f the c orresponding e na ble bi t
has been cleared to 0 or has been masked by the CPU.
Clearing with the
5(6
5(6
Pin: When the
5(6
pin is driven low, clock oscillation is started. At
the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the
5(6
pin must be held low until clock oscillation stabilizes. When the
5(6
pin goes high, the
CPU begins reset exce pt ion ha ndl ing.
4.6.3 Setting Oscillation Settling Time after Clearing Standby Mo de
Bits STS2 to STS0 in SBYCR should be set as describe d be low.
Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 10 ms (the
oscillation settling time).
Table 4.5 shows the standby times for different operating frequencies and settings of bits STS2
to STS0.
Rev. 1.0, 02/ 00, page 82 of 1141
Table 4.5 Oscillation Settling Time Settings
STS2 STS1 STS0 Standby Ti me 10 MHz 8 MHz Unit
0 8192 states 0.8 1.0
0
1 16384 states 1.6 2.0
0 32768 states 3.3 4.1
0
1
1 65536 states 6.6 8.2
0 131072 states 13.1*116.4*1
0
1 262144 states 26.2 32.8
ms
1
1*Reserved µs
Notes: *Don't car e
1. Recomm ended time setting
Using an External Clock: Any value can be set.
Rev. 1.0, 02/ 00, page 83 of 1141
4.7 Watch Mode
4.7.1 Watch Mode
If a SLEEP instruction is executed in high-speed mode, medium-speed mode or subactive mode
when the SSBY in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the TMA3
bit in TMA (Timer A) is set to 1, the CPU will make a transition to watch mode.
In this mode, the CPU and all on-chip supporting modules except timer A stop. As long as the
prescribed voltage is supplied, the contents of CPU registers, some on-chip supporting module
registers, and on-chip RAM, are retained, and I/O ports are placed in the high-impedance state.
4.7.2 Clear ing Watch Mode
Watch mode is cleared by an interrupt (Timer A interrupt, or pin
,54
to
,54
), or by means of
the
5(6
pin.
Clearing with an Interrupt: When an interrupt request signal is input, watch mode is cleared
and a t ra nsi t i on is m a de to high-spe e d m ode or m e di um -spe ed mode i f t he L SON bi t in
LPWRCR is cleared to 0, or to subactive mode if the LSON bit i s se t to 1 . Whe n m aki n g a
transition to medium-speed mode, after the elapse of the time set in bits STS2 to STS0 in
SBYCR, stable clocks are supplied to the entire chip, and interrupt exception handling is started.
Watch mode cannot be cleared with an
,54
to
,54
interrupt i f the c orresponding e na ble bi t
has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the
relevant interrupt has been disabled by the interrupt enable register or masked by the CPU.
See section 4.6.3, Setting Oscillation Settling Time after Clearing Standby Mode, for the
oscillation settling time setting when making a transition from watch mode to high-speed mode
or medium-speed mode.
Clearing with the
5(6
5(6
Pin: See (2) Clearing with the
5(6
Pin in section 4.6.2, Clearing
Standby Mode.
Rev. 1.0, 02/ 00, page 84 of 1141
4.8 Subsleep Mode
4.8.1 Subsleep Mode
If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0,
the LSON bi t i n L PW RCR i s set t o 1, and t he T MA3 bi t i n T MA (Timer A) is set to 1, the CPU
will make a transition to subsleep mode.
In this mode, the CPU and all on-chip supporting modules other than Timer A stop. As long as
the prescribed voltage is supplied, the contents of CPU registers, some on-chip supporting
module registers, and on-chip RAM, are retained, and I/O ports are placed in the high-
impedance state.
4. 8.2 Clear ing Subsleep Mode
Subsleep mode is cleared by an interrupt (Timer A interrupt, or pin
,54
to
,54
), or by means
of the
5(6
pin.
Clearing with an Interrupt: When an interrupt request signal is input, subsleep mode is cleared
and interrupt exception handling is started. Subsleep mode cannot be cleared with an
,54
to
,54
interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip
supporting module interrupt if acceptance of the relevant interrupt has been disabled by the
interrupt e nabl e regi ste r or ma sked by t he CPU.
Clearing with the
5(6
5(6
Pin: See (2) Clearing with the
5(6
Pin in section 4.6.2, Clearing
Standby Mode.
Rev. 1.0, 02/ 00, page 85 of 1141
4.9 Subactive Mode
4. 9.1 Subac t i v e M o de
If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the
DTON bit in LPWRCR, and the TMA3 bit in TMA (timer A) are all set to 1, the CPU will make
a transition to subactive mode. When an interrupt is generated in watch mode, if the LSON b i t
in LPWRCR is set to 1, a transition is made to subactive mode. When an interrupt is generated
in subsleep mode, a transition is made to subactive mode.
In subactive mode, the CPU performs sequential program execution at low speed on the
subclock. In this mode, all on-chip supporting modules other than timer A stop.
4. 9.2 Clear ing Suba c t i v e M o de
Subsleep mode is cleared by a SLEEP instruction, or by means of the
5(6
pin.
Clea r i ng with a SLEEP Instr uc ti o n: When a SLEEP instruction is executed while the SSBY
bit in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the TMA3 bit in TMA
(timer A) is set to 1, subactive mode is cleared and a transition is made to watch mode. When a
SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the LSON bi t i n
LPWRCR is set to 1, and the TMA3 bit in TMA (timer A) is set to 1, a transition is made to
subsleep mode. When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to
1, t h e DT ON b i t i s se t to 1 a n d the L SON b i t i s cleared to 0 in LPWRCR, and the TMA3 bit in
TMA (timer A) is set to 1, a transition is made directly to high-speed or medium-speed mode.
For details of direct transition, see section 4.10, Direct Transition.
Clearing with the
5(6
5(6
Pin: See (2) Clearing with the
5(6
Pin in section 4.6.2, Clearing
Standby Mode.
Rev. 1.0, 02/ 00, page 86 of 1141
4.10 Direct Transit i on
4.10.1 Overview of Direct Transition
There a re thre e opera t ing m ode s in which t he CPU execut e s programs: hi gh-spee d mode ,
medium-speed mode, and subactive mode. A transition between high-speed mode and subactive
mode without halting the program* is called a direct transition. A direct transition can be
carried out by setting the DTON bit in LPWRCR to 1 and executing a SLEEP inst ruction. After
the transition, direct transition interrupt exception handling is started.
Direct Transition from High-Speed Mode to Subact i v e M o de : If a SLEEP instruction is
executed in high-speed mode while the SSBY bit in SBYCR, the LSON bit a n d DTON bi t in
LPWRCR, and the TMA3 bit in TMA (Timer A) are all set to 1, a transition is made to
subactive mode.
Direct Transition from Subact i v e M o de t o H i g h- Spe e d Mode/Medium-Speed Mode: If a
SLEEP instruction is executed in subactive mode while the SSBY bit in SBYCR is set to 1, the
LSON bit i s cleared to 0 and the DTON bit is set to 1 in LPWRCR, and the TMA3 bit in TMA
(timer A) is set to 1, after the elapse of the time set in bits STS2 to STS0 in SBYCR, a transition
is made to directly to high-speed mode or medium-speed mode.
Note: * At the time of transition from subactive mode to high- or medium-speed mode, an
oscillation stabilization wait time is generated.
Rev. 1.0, 02/ 00, page 87 of 1141
Section 5 Exception Handling
5.1 Overview
5.1.1 Exception Handling Types and Priority
As table 5.1 indicates, exception handling may be caused by a reset, trap instruction, or
interrupt. Exception handling is prioritized as shown in table 5.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority. Trap instruction
exceptions are accepted at all times in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the i nt errupt c ont rol m ode se t by t he INT M0 and INT M1 bit s in SYSCR.
Table 5.1 Exception Types and Priority
Priority Exception
Type Start of Excepti on Handl ing
Reset Starts immediat ely aft er a low-t o-high t r ansition at the
5(6
pin, or
when the watchdog t imer over f lows
Trace*1St ar t s when execution of t he cur r ent instr uct ion or except ion
handling ends, if the t r ace ( T) bit is set t o 1
Inter r upt Start s when execut ion of t he cur r ent inst r uct ion or except ion
handling ends, if an interr upt r equest has been issued*2
Direct tr ansition St ar t ed by a direct t r ansit ion resulting fr om execution of a SLEEP
instruction
High
Low Trap instruction
(TRAPA)*3Sta rt ed b y e x e c ution o f a tra p ins tr u ction ( T RAPA)
Notes: 1. Traces ar e enabled only in interr upt cont rol modes 2 and 3. ( They cannot be used in
this LSI. ) Tr ace except ion handling is not executed af ter execut ion of an RTE
instruction.
2. I nterr u pt de tec tion is n o t perf o rme d o n c o mpletion o f ANDC, ORC, XORC, o r LDC
instruction execut ion, or on com pletion of r eset except ion handling.
3. Tr ap instr uction exception handling requests ar e accept ed at all times in t he pr ogr am
execution stat e.
Rev. 1.0, 02/ 00, page 88 of 1141
5.1.2 Exception Handling Operati on
Exceptions originate from various sources. Trap instructions and interrupts are handled as
follows:
1. The program counter (PC) and condition-code register (CCR) are pushed onto the stack.
2. The interrupt mask bits are updated. The T bit is cleared to 0.
3. A vector address corresponding to the exception source is generated, and program execution
starts from tha t addre ss.
For a reset exc e pti on, ste ps 2 and 3 above a re c a rrie d out .
5.1.3 Exception Sources and Vector Table
The exception sources are classified as shown in figure 5.1. Different vector addresses are
assigned to diffe re nt e xc ept i on sources.
Table 5. 2 l ists the e xce pt ion source s and t hei r ve ct or a ddresses.
Exception sources
• Reset
• Interrupts
• Trap instruction
Note: * In this LSI, the watchdog timer generates NMIs.
• Trace (cannot be used in this LSI)
• Direct transition
External interrupts NMI*, IRQ5 to IRQ0
Internal interrupts Interrupt sources in on-chip supporting modules
…
…
Figure 5.1 Exception Sources
Rev. 1.0, 02/ 00, page 89 of 1141
Table 5.2 Exception Vector Table
Exception Sour ce Vector Number Vector Address*1
Reset 0 H'0000 to H'0003
1 H'0004 to H'0007
2 H'0008 to H'000B
3 H'000C to H'000F
4 H'0010 to H'0013
Reserved for system use
5 H'0014 to H'0017
Direct tr ansit ion 6 H'0018 to H001B
External inter r upt NMI*27 H'001C to H'001F
8 H'0020 to H'0023
9 H'0024 to H'0027
10 H'0028 to H'002B
Trap instruct ion ( 4 sour ces)
11 H'002C to H'002F
12 H'0030 to H'0033
13 H'0034 to H'0037
14 H'0038 to H'003B
Reserved for system use
15 H'003C to H'003F
#0 16 H'0040 to H'0043
#1 17 H'0044 to H'0047
Address tr ap
#2 18 H'0048 to H'004B
Int er nal inter r upt ( I C) 19 H'004C to H'004F
Int er nal inter r upt ( HSW1) 20 H'0050 to H'0053
IRQ0 21 H'0054 t o H'0057
IRQ1 22 H'0058 t o H'005B
IRQ2 23 H'005C to H'005F
IRQ3 24 H'0060 t o H'0063
IRQ4 25 H'0064 t o H'0067
External inter r upt
IRQ5 26 H'0068 t o H'006B
Internal interrupt*227
…
31
H'006C to H'006F
…
H'007C to H'007F
Reserved 32
…
33
H'0080 to H'0083
…
H'0084 to H'0087
Internal interrupt*334
…
67
H'0088 to H'008B
…
H'010C to H'010F
Notes: 1. Lower 16 bits of t he addr ess.
2. I n this LSI, t he wat ch dog timer gener ates NMIs .
3. For det ails on internal interr upt vector s, see sect ion 6. 3. 3, Inter r upt Except ion Vector
Table.
Rev. 1.0, 02/ 00, page 90 of 1141
5.2 Reset
5.2.1 Overview
A reset has the highest exception priority. When the
5(6
pin goes low, all processing halts and
the LSI enters the reset state. A reset initializes the internal state of the CPU and the registers of
on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set.
Reset exc e pti on ha ndli ng be gins when the
5(6
pin change s from l ow to high.
The LSIs can also be reset by overflow of the watchdog timer. For details, see section 17,
Watchdog Timer.
5. 2.2 Reset Se quenc e
The LSI enters the reset state when the
5(6
pin goes low.
To ensure that the chip is reset, hold the
5(6
pin low during the oscillation stabilizing time of
the clock oscillator when powering on. To reset the chip during operation, hold the
5(6
pin low
for at least 20 states. For pin states in a reset, see Appendix D, Port States in the Different
Processing States.
When the
5(6
pin goes high after being held low for the necessary time, the chip starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
2. The re set e xc ept i on vec t or addre ss is read a nd tra nsferre d to t he PC, a nd program e xec ut ion
starts from the address indicated by the PC.
Figure 5.2 shows exampl es of the re set seque nc e.
Rev. 1.0, 02/ 00, page 91 of 1141
φ
RES
Internal address bus
Internal read signal
Internal write signal
Internal data bus
Vector
fetch
(1)
(2)
(3)
(4)
: Reset exception vector address ((1) = H'0000 or H'000000)
: Start address (contents of reset exception vector address)
: Start address ((3) = (2))
: First program instruction
(1) (3)
High level
Internal
processing Fetch of first program
instruction
(2) (4)
Figure 5. 2 Reset Sequence (M ode 1)
5. 2.3 Inte r rupts a ft e r Re se t
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt
requests, including NMI, are disabled immediately after a reset. Since the first instruction of a
program is always executed immediately after the reset state ends, make sure that this instruction
initializes the stack pointer (example: MOV.L #xx: 32, SP).
Rev. 1.0, 02/ 00, page 92 of 1141
5.3 Interrupts
Interrupt e xc ept i on handl i ng ca n be reque ste d by six ext e rnal source s (
,54
to
,54
) and
interna l sources in t he on-chi p supporti ng modul e s. Figure 5. 3 shows the inte rrupt sources and
the number of interrupts of each type.
The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),
prescaler unit (PSU), Timers A, B, J, L, R and X1 (TMR), serial communication interface (SCI),
A/D converter (ADC), I2C bus interface (IIC), servo circuits, sync detection, data slicer, OSD,
address trap, etc. Each interrupt source has a separate vector address.
NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The
interrupt controller has two interrupt control modes and can assign interrupts other than NMI to
either three priority/mask levels to enable multiplexed interrupt control.
For details on interrupts, see section 6, Interrupt Controller.
WDT*
2
(1)
PSU (1)
TMR (15)
SCI (4)
ADC (1)
IIC (3)
Servo circuits (9)
Synchronized detection (1)
Address trap (3)
Interrupts
Internal
interrupts
External
interrupts
Notes: Numbers in parentheses are the numbers of interrupt sources.
In this LSI, the watchdog timer generates NMIs.
When the watchdog timer is used as an interval timer, it generates an interrupt
request at each counter overflow.
1.
2.
NMI*
1
(1)
IRQ5 to IRQ0 (6)
Figure 5.3 Interrupt Sources and Number of Interrupts
Rev. 1.0, 02/ 00, page 93 of 1141
5.4 Trap In st ru ct i o n
Trap i n st r u c t ion e x c e p t ion h a n d l i n g st a r t s wh e n a TRAPA i n st r u ction is executed. Trap
instruction exception handling can be executed at all times in the program execution state.
The T RAPA inst r u ction fetches a start address from a vector table entry corresponding to a
vector number from 0 to 3, as specified in the inst ruction code.
Table 5.3 shows the status of CCR and EXR after execution of trap instruction exception
handling.
Table 5.3 Status of CCR and EXR afte r Tr ap Instr uc ti on Exc e pti on H andl i ng
CCR EXR*
Interrupt
Control Mode I UI I2 to I0 T
01
111
Legend:
1: Set to 1
0: Cleared t o 0
: Retains value prior t o execut ion.
*: Does not aff ect operation in this LSI.
Rev. 1.0, 02/ 00, page 94 of 1141
5.5 Sta ck S t at u s aft er Except i on Han d lin g
Figures 5.4 and 5.5 show the stack after completion of trap instruction exception handling and
interrupt e xce pt ion ha ndl ing.
CCR
CCR*
PC
(16 bits)
SP→
Note: * Ignored on return.
Interrupt control modes 0 and 1
Figure 5. 4 Stack Status after Exception Handling (Normal M ode)*
Note: *Normal mode is not available for this LSI.
CCR
PC
(24 bits)
SP→
Interrupt control modes 0 and 1
Figure 5. 5 Stack Status after Exception Handling (Advanced Mode)
Rev. 1.0, 02/ 00, page 95 of 1141
5.6 Notes on Use of the St ack
When accessing word data or longword data, this chip assumes that the lowest address bit is 0.
The stack should always be accessed by word transfer instruction or longword transfer
instruction, and the value of the stack pointer (SP: ER7) should always be kept even.
Use the following instructions to save registers:
PUSH.W Rn (or MOV.W Rn, @- SP)
PUSH.L ERn (or MOV.L E Rn, @- SP)
Use the following i nstruc ti ons to re store re gi sters:
POP.WRn (or MOV.W @ SP+ , Rn)
POP.L E Rn (or MOV.L @ SP+ , ERn)
Setting SP to an odd value may lead to a malfunction. Figure 5.6 shows an example of what
happens when the SP value i s odd.
SP
[Legend] : Condition-code register
: Program counter
: General register R1L
: Stack pointer
H'FFFEFA
H'FFFEFB
H'FFFEFC
H'FFFEFD
H'FFFEFF
R1L
PC
SP CCR
PC
SP
CCR
PC
R1L
SP
Note: This diagram illustrates an example in which the interrupt control mode is 0, is advanced mode.
TRAPA instruction executed MOV.B R1L, @-ER7
SP set to H'FFFEFF Data saved above SP Contents of CCR lost
Figure 5.6 Operation when SP Value is Odd
Rev. 1.0, 02/ 00, page 97 of 1141
Section 6 Interrupt Controller
6.1 Overview
6.1.1 Features
This LSI controls interrupts by means of an interrupt controller. The interrupt controller has the
following fea t ures:
• Two Interrupt Control Modes
Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits
in the system control register (SYSCR).
• Priorities Settable with ICR
An interrupt control register (ICR) is provided for setting interrupt priorities. Three
priority levels can be set for each module for all interrupts except NMI.
• Independent Vector Addresses
All interrupt sources are assigned independent vector addresses, making it unnecessary
for the source t o be ide nt ifi e d in t he int e rrupt ha ndl ing rout i ne.
• Six External Int errupt Pins
NMI is the highest-priority interrupt, and is accepted at all times.
Falling edge, rising edge, or both edge detection can be selected for interrupt IRQ0.
Falling edge or rising edge can be individually selected for interrupts IRQ5 to IRQ1.
Note: *In this LSI, the watch dog timer generates NMIs.
Rev. 1.0, 02/ 00, page 98 of 1141
6.1.2 Block Diagram
Figure 6.1 shows a block diagram of the interrupt controller.
IRQ input
Internal
interrupt
requests
[Legend]
IEGR
IENR
IRQR
ICR
SYSCR
: IRQ edge select register
: IRQ enable register
: IRQ status register
: Interrupt control register
: System control register
Interrupt
request
Vector
number
I, UI
IRQ input
unit IRQR
IEGR IENR
ICR
CPU
Interrupt controller
SYSCR
INTM1, INTM0
CCR
Priority
determina-
tion
Figure 6.1 Block Diagram of Interrupt Controller
Rev. 1.0, 02/ 00, page 99 of 1141
6.1.3 Pin Configuration
Table 6.1 summarizes the pins of the interrupt controller.
Table 6.1 Interrupt Controller Pins
Name Symbol I/O Function
External inter r upt
request 0
,54
Input Maskable ext er nal interr upt s ; r ising, f alling, or bot h
edges can be selected
External inter r upt
requests 1 t o 5
,54
to
,54
Input Maskable external interr upts: r ising, or falling
edges can be selected
6.1.4 Register Configuration
Table 6.2 summarizes the registers of the interrupt controller.
Table 6.2 Interrupt Controller Registers
Name Abbreviation R/W Initial Value Address*1
Syst e m con t rol r e gis ter SYSCR R/W H'0 0 H'FFE8
IRQ edge select register I EG R R/W H'00 H'FFF0
IRQ enable r egister I ENR R/W H'00 H'FFF1
IRQ st at us r egister IRQR R/ (W) *2H'00 H'FFF2
Int e r r upt cont r o l r egis t er A I CRA R/W H'00 H'FFF3
Int e r r upt cont r o l r egis t er B I CRB R/W H'00 H'FFF4
Int e r r upt cont r o l r egis t er C I CRC R/ W H'00 H'FFF5
Int e r r upt cont r o l r egis t er D I CRD R/ W H'00 H'FFF6
Port m ode r egist er 1 PMR1 R/W H'00 H'FFCE
Notes: 1. Lower 16 bits of t he addr ess.
2. O nly 0 can be writ t en, f or flag clearing.
Rev. 1.0, 02/ 00, page 100 of 1141
6.2 Register Descri pt i on s
6. 2.1 System Co ntrol Regi st e r ( SYSCR)
0
0
1
0
—
2
0
—
3
1
R
4
0
R/W
5
0
R
0
7——XRSTINTM0INTM1
0
6
——
——
—
—
Bit :
Initial value :
R/W :
SYSCR is an 8-bit readable register that selects the interrupt control mode.
Only bits 5, 4, 2 and 1 are described here; for details on the other bits, see section 3. 2. 2, System
Control Re gi st er (SYSCR).
SYSCR is initialized to H'08 by a reset.
Bits 5 and 4Interrupt Co ntrol M o de ( INT M 1 , INT M 0 ) : These bits select one of two
interrupt control modes for the interrupt controller. The INTM1 bit must not be set to 1.
Bit 5 Bit 4
INTM1 INTM0 Inte r r upt Control
Mode Description
0 0 I nt er r upt s ar e controlled by I bit (Initial value)0
1 1 Inter r upt s ar e controlled by I and UI bit s and I CR
0Cannot be used in this LSI1
1Cannot be used in this LSI
Rev. 1.0, 02/ 00, page 101 of 1141
6. 2.2 Interr upt Co nt r o l Re g i st e rs A to D ( ICRA t o ICRD)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7ICR4 ICR3 ICR2 ICR1 ICR0
0
R/W
ICR7
R/WR/WR/W
ICR6 ICR5
6
Bit :
Initial value :
R/W :
The ICR registers are four 8-bit readable/writable registers that set the interrupt control level for
interrupt s othe r tha n NMI.
The correspondence between ICR settings and interrupt sources is shown in table 6.3.
The ICR registers are initialized to H'00 by a reset.
Bits 7 to 0Interr upt Contr ol Le ve l (ICR7 to ICR0): Set the c ont rol l e vel for t he
corresponding int e rrupt source .
Bit n
ICRn Description
0 Corresponding inter r upt source is cont r ol level 0 (non-pr iorit y) (Init ial value)
1 Corresponding interr upt source is contr ol level 1 (priority)
(n = 7 to 0)
Table 6.3 Correspondence between Interrupt Sources and ICR Se t t i ng s
ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 CIRA0ICRA
Reserved Input
capture HSW1 IRQ0 IRQ1 IRQ2
IRQ3 IRQ4
IRQ5 Sync
separator,
OSD
ICRB7 ICRB6 ICRB5 ICRB4 ICRB3 ICRB2 ICRB1 ICRB0ICRB
Data slicer Sync
separator Servo
(drum,
capstan
latch)
Timer A Timer B Timer J Timer R Timer L
ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0ICRC
Time r X1 Synchro-
nized
detection
Watchdog
timer Servo IIC SCI1
(UART) IIC0 A/D
ICRD7 ICRD6 ICRD5 ICRD4 ICRD3 ICRD2 ICRD1 ICRD0ICRD
HSW2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Rev. 1.0, 02/ 00, page 102 of 1141
6.2.3 IRQ Enable Register (IENR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
00
7
R/WR/WR/W
IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
0
6
——
——
Bit :
Initial value :
R/W :
IENR is an 8-bit readable/writable register that controls enabling and disabling of interrupt
requests IRQ5 to IRQ0.
IENR is initialized to H'00 by a reset.
Bits 7 and 6Reserved: These bits are always read as 0. Do not write 1 to them.
Bits 5 to 0IRQ5 to IRQ0 Enabl e (IRQ5E to IRQ0E): These bits select whether IRQ5 to
IRQ0 are enabled or disabled.
Bit n
IRQnE Description
0
,54Q
interr upt disabled (Init ial value)
1
,54Q
interr upt enabled
(n = 5 to 0)
Rev. 1.0, 02/ 00, page 103 of 1141
6.2.4 IRQ Edge Select Registers (IEGR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
00
7
—
—R/WR/WR/W
IRQ4EG
R/W
IRQ5EG IRQ3EG IRQ2EG IRQ1EG IRQ0EG1 IRQ0EG0
0
6
Bit :
Initial value :
R/W :
IEGR is an 8-bit readable/writable register that selects detected edge of the input at pins
,54
to
,54
.
IEGR register is initialized to H'00 by a reset.
Bit 7Reserved: This bit is always read as 0. Do not write 1 to it.
Bits 6 to 2
,54
,54
to
,54
,54
Pins Detected Edge Select (IRQ5EG to IRQ1EG): These bits
select detected edge for interrupts IRQ5 to IRQ1.
Bits 6 to 2
IRQnEG Description
0 Interr upt request generated at falling edge of
,54Q
pin input (Init ial value)
1 Int errupt r equest gener ated at r ising edge of
,54Q
pin input
(n = 5 to 1)
Bits 1 and 0
,54
,54
Pin Detected Edge Select (IRQ0EG1, IRQ0EG0): These bits select
detected edge for interrupt IRQ0.
Bit 1 Bit 0
IRQ0EG1 IRQ0EG0 Description
0 0 I nt er r upt request generat ed at falling edge of
,54
pin input (Init ial
value)
0 1 Interr upt r equest generated at r ising edge of
,54
pin input
1*Int er r upt request generat ed at both f alling and rising edges of
,54
pin
input
Note: *Don't care
Rev. 1.0, 02/ 00, page 104 of 1141
6. 2.5 IRQ Sta t us Re g i st e r ( IRQ R)
0
0
1
0
R/(W)*
2
0
R/(W)*
3
0
4
0
R/(W)*
5
00
7
R/(W)*R/(W)*R/(W)*
IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
0
6
——
——
Note: * Only 0 can be written, to clear the flag.
Bit :
Initial value :
R/W :
IRQR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt
requests.
IRQR is initialized to H'00 by a reset.
Bits 7 and 6Reserved: These bits are always read as 0. Do not write 1 to them.
Bits 5 to 0IRQ5 to IRQ0 Flags: These bits indicate the status of IRQ5 to IRQ0 interrupt
requests.
Bit n
IRQnF Description
0 [Clearing conditions] (Init ial value)
Cleared by reading IRQnF set t o 1, then writ ing 0 in IRQnF
When IRQn int er r upt exception handling is executed
1 [Setting conditions]
• When a falling edge oc curs in
,54Q
input while f alling edge detect ion is set
(I RQnEG = 0)
• When a rising edge occurs in
,54Q
input while rising edge detection is set
(I RQnEG = 0)
• When a falling or r ising edge occurs in
,54
input while both-edge detect ion is
set (IRQ0EG1 = 1) (n = 5 to 0)
Rev. 1.0, 02/ 00, page 105 of 1141
6.2.6 Port Mode Regi ster (PM R1)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W
PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10
R/WR/WR/W
6
Bit :
Initial value :
R/W :
Port Mode Register 1 (PMR1) controls pin function switching-over of port 1. Switching is
specified for each bit.
PMR1 is an 8-bit readable/writable register and is initialized to H'00 by a reset.
Only bits 5 to 0 are explained here. For details, see section 10. 3. 2, Register Configuration.
Bits 5 to 0P15/
,54
,54
to P10/
,54
,54
pin switching (PMR15 to PMR10): These bits are for
setting the P1n/
,54Q
pin as the i nput pin for P1n or as the
,54Q
pin for exte rna l i nt errupt
request input .
Bit n
PMR1n Description
0 P1n/
,54Q
pin functions as the P1n input/output pin (Initial value)
1 P1n/I RQn pin functions as the
,54Q
input/out put pin
(n = 5 to 0)
Notes on switching the pin function by PMR1 are as follows:
• When the port i s set as the
,&
input pin or
,54
to
,54
input pin, t he pin l e vel m ust be hi gh
or low regardless of active mode or power-down mode. Do not set the pin level at medium.
• Switching the pin function of P16/
,&
or P15/
,54
to P10/
,54
may be mistakenly identified
as edge detection and detection signal may be generated. To prevent this, operate as follows:
Set the interrupt enable/disable flag to disable before switching the pin function.
Clear the applicable interrupt request flag to 0 after switching the pin function and
execut i ng anot he r instruc t ion.
Program exam pl e
:
MOV.B R0L,@IENR ⋅⋅⋅⋅⋅⋅ Interrupt disabled
MOV.B R1L,@PMR1 ⋅⋅⋅⋅⋅⋅ Pin function change
NOP ⋅⋅⋅⋅⋅⋅ Optional instruction
BCLR m @IRQR ⋅⋅⋅⋅⋅⋅ Applicable interrupt clear
MOV.B R1L,@IENR ⋅⋅⋅⋅⋅⋅ Interrupt enabled
:
Rev. 1.0, 02/ 00, page 106 of 1141
6.3 Interru p t So urces
Interrupt sources compr ise extern al in terr upts (IRQ5 to IRQ0) and internal in terrupts.
6.3.1 Exter nal Interrupts
There are six extern al in terr upt sources; IRQ5 to IRQ0. Of these, IRQ1 to IRQ0 can be used to
restore this ch ip from standby mode.
• IRQ5 to IRQ0 Interrupts: In t er rupts IRQ5 to IRQ0 are requeste d by an i nput signal a t pi ns
,54
to
,54
. Interrupts IRQ5 to IRQ0 have the followi ng features:
(a) Using IEGR, it is possible to select whether an interrupt is requested by a falling edge,
rising edge, or bot h e dges, at pi n
,54
.
(b) Using IEGR, it is possible to select whether an interrupt is requested by a falling edge or
rising edge a t pins
,54
to
,54
.
(c) Enablin g or di sablin g of inter rupt requests IRQ5 to IRQ0 can be select ed with IE NR.
(d) Th e interrupt control level can be set with ICR.
(e) The status of interrupt requests IRQ5 to IRQ0 is indicated in IRQR. IRQR flags can be
cleared to 0 by software.
Figure 6.2 shows a block di agra m of int e rrupts IRQ5 to IRQ0.
Clear signal
R
SQ
Edge detection
circuit
IRQnEG IRQnF
IRQnE
Note: n = 5 to 0
IRQn interrupt
request
input
Figure 6. 2 Bl oc k Diagram of Interrupts IRQ5 to IRQ0
Rev. 1.0, 02/ 00, page 107 of 1141
Figure 6.3 shows the timing of IRQnF setting.
Internal φ
IRQnF
IRQn
input pin
Figure 6. 3 Ti mi ng of IRQnF Setting
The vector numbers for IRQ5 to IRQ0 interrupt exception han dlin g are 21 to 26.
Upon detection of IRQ5 to IRQ0 interr upts, the applicable pin is set in the por t r egister 1 (PMR1)
as
,54Q
pin .
6. 3.2 Internal Int e rrupt s
There a re 38 sources for int e rnal i nte rrupt s from on-chi p supporti ng modul e s.
• For each on-chip supporting module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. If any one of these is set
to 1, an interrupt request is issued to the interrupt controller.
• The interrupt control level can be set by means of ICR.
• The NMI is the highest priority interrupt and is always accepted regardless of the control
mode and CPU interrupt mask bit. In this LSI, NMIs are used as interrupts generated by the
watchdog timer
Rev. 1.0, 02/ 00, page 108 of 1141
6.3.3 Interrupt Exception Vector Table
Table 6.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority.
Priorities among modules can be set by means of ICR. The situation when two or more modules
are set to the same priority, and priorities within a module, are fixed as shown in table 6.4.
Table 6.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities
Priority Interrupt Source Origin of Interrupt
Source Vector
No. Vector Address ICR Remarks
Reset External pin 0 H'0000 to H'0003
1 H'0004 to H'0007
2 H'0008 to H'000B
3 H'000C to H'000F
4 H'0010 to H'0013
Reserved
5 H'0014 to H'0017
Direct transition Instruction 6 H'0018 to H'001B
NMI Watchdog timer 7 H'001C to H'001F
TRAPA#0 8 H'0020 to H'0023
TRAPA#1 9 H'0024 to H'0027
TRAPA#2 10 H'0028 to H'002B
Tr ap i nstruction
TRAPA#3
Instruction
11 H'002C to H'002F
12 H'0030 to H'0033
13 H'0034 to H'0037
14 H'0038 to H'003B
High
Low
Reserved
15 H'003C to H'003F
Rev. 1.0, 02/ 00, page 109 of 1141
Priority Interrupt Source Origin of Interrupt
Source Vector
No. Vector Address ICR Remarks
#0 16 H'0040 to H'0043
#1 17 H'0044 to H'0047
Address trap
#2
ATC
18 H'0048 to H'004B
IC PSU 19 H'004C to H'004F ICRA6
HSW1 Servo circuit 20 H'0050 to H'0053 ICRA5
IRQ0 21 H'0054 to H'0057 ICRA4
IRQ1 22 H'0058 to H'005B ICRA3
IRQ2 23 H'005C to H'005F
IRQ3 24 H'0060 to H'0063
ICRA2
IRQ4 25 H'0064 to H'0067
IRQ5
External pin
26 H'0068 to H'006B
ICRA1
External V interrupt Sync separator 27 H'006C to H'006F ICRA0
OSD V interrupt OSD 28 H'0070 to H'0073
Data slicer odd field interrupt Data slicer 29 H'0074 to H'0077 ICRB7
Data slicer even field interrupt 30 H'0078 to H'007B
Noise interrupt Sync separator 31 H'007C to H'007F ICRB6
Reserved 32 H'0080 to H'0083
33 H'0084 to H'0087
Drum latch 1 (speed) Servo circuit 34 H'0088 to H'008B ICRB5
Capstan latch 1 (speed) 35 H'008C to H'008F
TMAI Timer A 36 H'0090 to H'0093 ICRB4
TMBI Timer B 37 H'0094 to H'0097 ICRB3
High
TMJ1I Timer J 38 H'0098 to H'009B ICRB2
TMJ2I 39 H'009C to H'009F
TMR1I Timer R 40 H'00A0 to H'00A3 ICRB1
TMR2I 41 H'00A4 to H'00A7
TMR3I 42 H'00A8 to H'00AB
Low TMLI Timer L 43 H'00AC to H'00AF ICRB0
Rev. 1.0, 02/ 00, page 110 of 1141
Priority Interrupt Source Origin of Interrupt
Source Vector
No. Vector Address ICR Remarks
ICXA Timer X1 44 H'00B0 to H'00B3
ICXB 45 H'00B4 to H'00B7
ICXC 46 H'00B8 to H'00BB
ICXD 47 H'00BC to H'00BF
OCX1 48 H'00C0 to H'00C3
OCX2 49 H'00C4 to H'00C7
OVFX 50 H'00C8 to H'00CB
ICRC7
VD interrupts Sync signal
detection 51 H'00CC to H' 00CF ICRC6
Reserved 52 H'00D0 to H'00D3
8-bit interval timer Watchdog timer 53 H'00D4 to H'00D7 ICRC5
CTL 54 H'00D8 to H'00DB
Drum latch 2 (speed) 55 H'00DC to H'00DF
Capstan latch 2 (speed) 56 H'00E0 to H'00E3
Drum latch 3 (phase) 57 H'00E4 to H'00D7
Capstan latch 3 (phase)
Servo circuit
58 H'00E8 to H'00EB
ICRC4
IIC1 IIC1 59 H'00E C to H'00E F I CRC3
ERI 60 H'00F0 to H'00F3
RXI 61 H'00F4 to H'00F7
TXI 62 H'00F8 to H'00FB
SCI1
TEI
SCI1
(UART)
63 H'00FC to H'00FF
ICRC2
64 H'0100 to H'0103IIC0
DDCSW IIC0
65 H'0104 to H'0107
ICRC1
A/D conversion end A/D 66 H'0108 to H'010B ICRC0
High
Low HSW2 Servo circuit 67 H'010C to H'010F ICRD7
Rev. 1.0, 02/ 00, page 111 of 1141
6.4 Interrup t Op erat ion
6. 4.1 Inte r rupt Co ntrol Mode s a nd Inter r upt O pe rat i o n
Interrupt operations in this LSI differ depending on the interrupt control mode.
NMI* interrupts and address trap interrupts are accepted at all times except in the reset state. In
the ca se of IRQ int errupt s and on-c hip supporti ng m odule i nte rrupt s, a n ena bl e bi t is provide d
for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request.
Interrupt sources in which the enable bits are set to 1 are controlled by the interrupt controller.
Table 6. 5 shows the int errupt c ontrol m odes.
The interrupt controller performs interrupt control according to the interrupt control mode set by
the INTM1 and INTM0 bits in SYSCR, the priorities set in ICR, and the masking state indicated
by the I and UI bit s in t he CPU’s CCR.
Note: *In this LSI, the NMI interrupt is generated by the watchdog timer.
Table 6.5 Interrupt Control Modes
SYSCRInterrupt
Control
Mode INTM1 INTM0 Priority Setting
Register Interrupt
Mask Bit s Descripti on
0 0 ICR I Interrupt mask control is
perfor med by the I bit
Priority can be set with I CR
1
0
1 ICR I, UI 3-leve l in ter rup t m as k c o n tr ol is
perfor med by the I and UI bits
Priority can be set with I CR
Rev. 1.0, 02/ 00, page 112 of 1141
Figure 6.4 shows a block diagram of the priority decision circuit.
Interrupt control modes 0 and 1
I
Interrupt source
UI
Vector number
Interrupt acceptance
control and 3-level
mask control
Default priority
determination
I C R
Figure 6.4 Block Diagram of Interrupt Priority Determination Operation
• Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1,
interrupt acceptance control and 3-level mask control is performed by means of the I and UI
bits in CCR, and ICR (c ont rol l e vel ).
Table 6.6 shows the interrupts selected in each interrupt control mode.
Table 6.6 Interrupts Selected in Each Interrupt Control Mode
Inter r upt Mask BitInterrupt
Control
Mode I UI Select ed Inter r upts
0*All interr upt s ( cont r ol level 1 has priority)0
1*NMI*1 and address t r ap int er r upt s
0*All interr upt s ( cont r ol level 1 has priority)
0NMI
*1, address t r ap and control level 1 interrupts
1
1
1NMI
*1 and address tr ap int er r upt s
Notes: *Don't car e
1. I n t his LSI , t he NM I inter rupt is gener at ed by t he wat chdog t im er .
• Default Priority Determination: If the same value is set for ICR, acceptance of multiple
interrupts is enabled, and so only the interrupt source with the highest priority according to
the preset default priorities is selected and has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 6.7 shows operations and control signal functions in each interrupt control mode.
Rev. 1.0, 02/ 00, page 113 of 1141
Tabl e 6 .7 Ope r a tions a nd Cont r o l Signal F unc t i o ns i n E ach Inte rrupt Co ntrol Mode
Setting Interr upt Accept ance Cont r ol ,
3-Level Contr ol
Interrupt
Control
Mode INTM1 INTM0 I UI ICR Default Priority
Determination
00
{
IM PR
{
1
0
1
{
IM IM PR
{
Legend:
{
: Int er r upt oper at ion cont r ol perform ed
IM: Used as interrupt mask bit
PR: Sets priority
: Not used
6. 4.2 Interr upt Co nt r o l M o de 0
Enabli ng a nd disabl i ng of IRQ inte rrupt s and on-chi p supporti ng modul e int e rrupts ca n be set by
the I bit in the CPU’s CCR, and ICR. Interrupts are enabled when the I bit is cleared to 0, and
disabled when set t o 1. Control l eve l 1 int e rrupt source s have highe r pri orit y.
Figure 6.5 shows a flowchart of the interrupt acceptance operation in this case.
• If an interrupt source occ urs when the corre sponding i nte rrupt ena bl e bi t is set t o 1, a n
interrupt request is se nt to the interrupt controller.
• When interrupt requests are sent to the interrupt controller, a control level 1 interrupt,
according to the control level set in ICR, has priority for selection, and other interrupt
requests are held pending. If a number of interrupt requests with the same control level
setting are generated at the same time, the interrupt request with the highest priority
according to the priority system shown in table 6.4 is selected.
• The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If
the I bit is set to 1, only an NMI*1 or an address trap interrupt is accepted, and other interrupt
requests are he l d pendi ng.
• When an interrupt request is accepted, interrupt exception handling starts after execution of
the current instruction has been completed.
• The PC and CCR are sa ved to the stack area by interrupt exception handling. The PC saved
on the stack shows the address of the first instruction to be executed after returning from the
interrupt ha ndli ng rout ine .
• Next, the I bit in CCR is set to 1. This disables all interrupts except NMI* and address trap.
• A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
Note: *In this LSI, the NMI interrupt is generated by the watchdog timer.
Rev. 1.0, 02/ 00, page 114 of 1141
Program execution state
Interrupt
generated?
NMI
Address trap
interrupt?
Control level 1
interrupt?
I C
I = 0
Yes
Yes
Yes
Yes Yes
Yes
Yes
No
Yes
Yes
Yes Yes
No
No
No
No
No
No
Save PC and CCR
I ← 1
Read vector address
Branch to interrupt handling routine
I C No
No
H S W 1H S W 1
H S W 2H S W 2
Hold pending
Figure 6. 5 Flowchart of Procedure Up to Interrupt Acceptance in
Interr upt Co nt r o l M o de 0
Rev. 1.0, 02/ 00, page 115 of 1141
6. 4.3 Interr upt Co nt r o l M o de 1
Three-level masking is implemented for IRQ interrupts and on-chip supporting module
interrupts by means of the I and UI bits in the CPU’s CCR and ICR.
• Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled
when set to 1.
• Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and
disabled when both the I bit and the UI bit are set to 1.
For example , i f the i nte rrupt ena bl e bi t for an i nt errupt re quest i s set t o 1, and H' 04, H'00, H'00
and H'00 are set in ICRA, ICRB, ICRC and ICRD respectively, (i.e. IRQ2 interrupt is set to
control level 1 and other interrupts to control level 0), the situation is as follows:
• When I = 0, all interrupts are enabled
(Priority order: NMI > IRQ2 > IC > HSW1 > ...)
• When I = 1 and UI = 0, onl y NMI, addre ss trap a nd IRQ2 inte rrupt s are e na ble d
• When I = 1 and UI = 1, onl y NMI and addre ss trap int e rrupts are e nabl e d
Figure 6.6 shows the state transitions in these cases.
Only NMI, address trap and
IRQ2 interrupts enabled
All interrupts enabled
Exception handling
execution or UI ← 1
Exception handling
execution or
I ← 1, UI ← 1
I ← 0
I ← 1, UI ← 0
UI ← 0I ← 0
Only NMI and address trap
interrupts enabled
Figure 6.6 Example of State Transitions in Interrupt Control Mode 1
Figure 6.7 shows an operation flowchart of interrupt reception.
Rev. 1.0, 02/ 00, page 116 of 1141
(1) If a n int e rrupt source oc curs when the c orresponding i nt errupt e nabl e bit i s set to 1, a n
interrupt request is se nt to the interrupt controller.
(2) When interrupt requests are sent to the interrupt controller, a control level 1 interrupt,
according to the control level set in ICR, has priority for selection, and other interrupt
requests are held pending. If a number of interrupt requests with the same control level
setting are generated at the same time, the interrupt request with the highest priority
according to the priority system shown in table 6.4 is selected.
(3) The I bit is then referenced. If the I bit is cleared to 0, the UI bit has no effect.
An interrupt request set to interrupt control level 0 is accepted when the I bit is cleared to 0.
If the I bit is set to 1, only NMI* and address trap interrupts are accepted, and other interrupt
requests are he l d pendi ng.
An interrupt re que st set t o i nte rrupt cont rol le ve l 1 ha s priori ty ove r a n int e rrupt re que st set
to interrupt control level 0, and is accepted if the I bit is cleared to 0, or if the I bit is set to 1
and the UI bit is cleared to 0.
When both t he I bit a nd the UI bit are set to 1, onl y NMI* and addre ss trap int e rrupts are
accepted, and other interrupt requests are held pending.
(4) When an interrupt request is accepted, interrupt exception handling starts after execution of
the current instruction has been completed.
(5) The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved
on the stack shows the address of the first instruction to be executed after returning from the
interrupt ha ndli ng rout ine .
(6) Next, the I and UI bits in CCR are set to 1. This masks all interrupts except NMI* and
address trap.
(7) A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
Note: *In this LSI, the NMI interrupt is generated by the watchdog timer.
Rev. 1.0, 02/ 00, page 117 of 1141
Program execution state
NMI
I C
Yes
Yes
Yes
Yes Yes
Yes
Yes
No
Yes
Yes
Yes Yes
No
No
No
No
No
No
I C No
No
H S W 1H S W 1
H S W 2H S W 2
Yes
No
Yes
No
Interrupt
generated?
Address trap
interrupt?
Control level 1
interrupt?
I = 0 I = 0
UI = 0
Save PC and CCR
I ← 1, UI ← 1
Read vector address
Branch to interrupt handling routine
Hold pending
Figure 6. 7 Flowchart of Procedure Up to Interrupt Acceptance in
Interr upt Co nt r o l M o de 1
Rev. 1.0, 02/ 00, page 118 of 1141
6. 4.4 Interr upt E x c e pt i o n H a ndl ing Se que nce
Figure 6.8 shows the int errupt e xce pt ion ha ndl ing seque nc e. T he exa m ple shown is for the c ase
where interrupt control 0 is set in advanced mode, and the program area and stack area are in on-
chip me m ory.
φ
(1)
(1) Instruction prefetch address (Not executed.
This is the contents of the saved PC, the
return address.)
Saved PC and saved CCR
Vector address
Interrupt handling routine start address (vector address contents)
Interrupt handling routine start address ((13) = (10)(12))
First instruction of interrupt handling routine
(2)(4)
(6)(8)
(10)(12)
(13)
(9)(11)
(14)
(3) (5) (7) (9) (11) (13)
Internal
address bus
Interrupt
request signal
Internal read
signal
Internal
write signal
Internal
data bus (2) (4) (6) (8) (10) (12) (14)
Stack Vector fetch
Interrupt level
determination
Wait for end of
instruction
Interrupt
acceptance
Internal
operation Internal
operation
Instruction
prefetch Interrupt handling routine
instruction prefetch
Instruction code (Not executed.)
(3) Instruction prefetch address (Not executed.)
(5) SP-2
(7) SP-4
Figure 6.8 Interrupt Exception Handling
Rev. 1.0, 02/ 00, page 119 of 1141
6. 4.5 Interr upt Response T i m e s
Table 6.8 shows interrupt response times-the interval between generation of an interrupt request
and exec ut ion of t he first i nstruc ti on i n the i nte rrupt handl i ng routi ne . The symbol s used in ta bl e
6.8 are explained in table 6.9.
Tabl e 6 .8 Inter rupt Re spo nse T i m e s
No. Num ber of St at es Advanced Mode
1 Interr upt pr ior ity determ inat ion*13
2 Num ber of wait states until executing instruct ion ends*21 to 19+2⋅SI
3 PC, CCR stac k s a v e 2⋅Sk
4 Vector fetch 2⋅SI
5 Instruction fetch*32⋅SI
6 Inter nal processing*42
Total (using on-chip mem ory) 12 to 32
Notes: 1. Two states in case of int er nal interr upt.
2. Ref e r s to DIVXS ins t ruc tion.
3. Prefetch af ter interrupt accept ance and int er r upt handling routine pref etch.
4. I nt er nal processing af t er inter r upt acceptance and inter nal processing af t er vect or
fetch.
Table 6.9 Number of States in Interrupt Handling Routine Execution
Obj ect of Access
Symbol Internal Memory
Instruction fetch SI1
Stack operat ion SK 1
Rev. 1.0, 02/ 00, page 120 of 1141
6.5 Usage Notes
6. 5.1 Contenti o n be t we en Inte rrupt G ene r a tion a nd Di sa bl i ng
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or
MOV, if an in te rrupt i s gene rated during execution of the instruction, the interrupt concerned
will still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will be executed on completion of the instruction. However, if there is an interrupt
request of higher priority than that interrupt, interrupt exception handling will be executed for
the higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 6.9 shows an example in which the OCIAE bit in timer X1 TIER is cleared to 0.
φ
TIER address
Internal
address bus
Internal
write signal
OCIAE
OCFA
OCIA
interrupt signal
TIER write cycle
by CPU OCIA interrupt
exception handling
Figure 6.9 Contention between Interrupt Generation and Disabling
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the int e rrupt i s ma sked.
Rev. 1.0, 02/ 00, page 121 of 1141
6. 5.2 Instructi o ns t hat Di sa bl e Interrupts
Instruct i ons t ha t di sa bl e i nt errupt s a re L DC, ANDC, ORC, a nd XORC. Aft e r a ny of th ese
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit or UI bit is set by one of these instructions, the new value
becomes valid two states after execution of the instruction ends.
6.5.3 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B in st r uct i o n and the EE PMOV. W in st r u ction.
With the EEPMOV.B i nstru ct i on, an i nt errupt re quest (i nc ludi ng NMI) issued during the tra nsfer
is not accepted until the move is completed.
With the EEPMOV.W i n st r u ct i on, if a n i nte rrupt reque st i s issued during the t ransfer, i nt errupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W inst r u ction, the
following codi ng should be used.
L1: EEPMOV.W
MOV.W R4,R4
BNE L1
Rev. 1.0, 02/00, page 123 of 1141
Section 7 ROM
7.1 Overview
The H8S/2199 has 128 kbytes of on-chip ROM (flash memory or mask ROM), the H8S/ 2198 has
112 kbytes, the H8S/2197 has 96 kbytes, and the H8S/2196 has 80 kbytes*. The ROM is
connected to the CPU by a 16-bit data bus. The CPU accesses both byte and word data in one
state, enabling faster instruction fe tches and higher processing spee d.
The flash memory ve rsions of t he H8S/2199 can be era sed a nd programmed on-board as well as
with a genera l -purpose PROM programmer.
Note: *For details on product line-up, refe r to section 1, Ove rview.
7.1.1 Block Diagram
Figure 7. 1 shows a bloc k diagra m of the ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000
H'000002
H'01FFFE
H'000001
H'000003
H'01FFFF
Figure 7.1 RO M Block Diagram (H8S/2199)
Rev. 1.0, 02/00, page 124 of 1141
7.2 Overview of F l ash Memory
7.2.1 Features
The features of the flash memory a re summarized below.
• Four flash memory opera ting mode s
Program mod e
Erase mode
Program-verify mode
Erase-verify m ode
• Progra mm ing/erase methods
The flash memory i s programmed 128 bytes a t a ti me. Era sing is performed by block era se (in
single-block units). When erasing all blocks, the individual blocks must be erased
sequentially. Block e rasing ca n be performed as required on 4-kbyte, 32-kbyt e, and 64-kbyte
blocks. (In OSD ROM, bl ock erasing can be perform e d on 1-kbyte, 2-kbyt e, and 28-kbyte
blocks).
• Progra mm ing/erase times
The flash memory programming ti me is T BD ms (typ.) for simultaneous 128-byte
programming, equivalen t to TBD µs (typ.) per byte, and the erase time is TBD ms (typ.) per
block.
• Reprogram ming ca pa bility
The flash memory c an be re programmed up to TBD times.
• On-board programming modes
There are two m odes in which flash me m ory c an be programmed/erased/ve ri fied on-boa rd:
Boot mode
User program mode
• Automatic bit rate adjustment
If data transfer on boot mode, automatic adjustment is possible at host transfer bit rates and
MCU' s bit rates.
• Protect modes
There are three protec t modes, hardware, software, and error prote ct, which allow prote ct ed
status to be designated for flash memory program/erase/verify operations.
• Writer mode
Flash memory ca n be programmed/erased in writer m ode, using a PROM programme r, as well
as in on-board programming mode.
Rev. 1.0, 02/00, page 125 of 1141
7.2.2 Bl oc k Diagram
Figure 7. 2 shows a bloc k diagra m of the flash memory.
Module bus
Bus interface/controller
Flash memory
(256 kbytes)
Operat-
ing
mode
FLMCR1
STCR
FLMCR1
FLMCR2
EBR1
EBR2
: Serial timer control register
: Flash memory control register 1
: Flash memory control register 2
: Erase block register 1
: Erase block register 2
[Legend]
Internal address bus
Internal data bus (16 bits)
STCR
FWE pin
Mode pin
FLMCR2
EBR1
Flash memory
(OSD ROM)
(32 kbytes)
EBR2
Figure 7.2 Block Diagr am of Flash Memory (H8S/2199 Only)
Rev. 1.0, 02/00, page 126 of 1141
7.2.3 Flash Memory Operating Modes
Mode Transitions
When each mode pin and the FWE pin are set in the reset state and a reset-start is executed, the
MCU ent e rs one of t he operating m ode s shown in figure 7.3. In user m ode, flash memory can be
read but not programmed or erase d.
Flash memory ca n be programmed and era sed in boot mode, user program mode , and wri ter mode .
Boot mode
On-board program mode
User
program
mode
User mode
Reset state
Writer mode
FWE = 1, MD0 = 0,
P12 = P13 = P14 = 1
MD0 = 0,
P12 = P13 = 1, P14 = 0
= 0
= 0
FWE = 1
SWE = 1
FWE = 0
or
SWE = 0
= 0
MD1 = 1, FWE = 0 or 1
= 0
Only make a transition between user mode
and user program mode when the CPU is not
accessing the flash memory.
Note:
Figure 7.3 Flash Memory Mode Transitions
Rev. 1.0, 02/00, page 127 of 1141
On-Board Prog ram ming Modes
• Boot mode
<Flash memory>
<This LSI>
<RAM>
<Host>
Programming control
program
SCI
Application
program
(old version)
New application
program
Programming control
program
Programming control
program
<This LSI>
<RAM>
<Host>
SCI
Boot program area
<This LSI>
<RAM>
<Host>
SCI
Flash memory erase
<This LSI>
Program execution state
<RAM>
<Host>
SCI
New application
program
"#
!"
1. Initial state 2. Writing control program transfer
3. Flash memory initialization 4. Writing new application program
Boot program
<Flash memory>
Application
program
(old version)
Boot program
<Flash memory>
Boot program
<Flash memory>
Boot program
Boot program area Programming control
program
The flash memory is in the erased state when the
device is shipped. The description here applies to
the case where the old program version or data is
being rewritten. The user should prepare the
programming control program and new application
program beforehand in the host.
When boot mode is entered, the boot program in
this LSI chip (originally incorporated in the chip) is
started, and SCI communication check is carried
out, and the boot program required for flash memory
erasing is automatically transferred to the RAM boot
program area.
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, entire flash
memory erasure is performed, without regard to
blocks.
The programming control program transferred from
the host to RAM by SCI communication is executed,
and the new application program in the host is
written into the flash memory.
New application
program
New application
program
Figure 7.4 Boot Mode
Rev. 1.0, 02/00, page 128 of 1141
• User program mode
<Flash memory>
<This LSI>
<RAM>
<Host>
Programming/erase control program
SCI
Boot program
New application
program
<This LSI>
<RAM>
<Host>
SCI
<Flash memory>
<This LSI>
<RAM>
<Host>
SCI
Flash memory erase
Boot program
New application
program
<This LSI>
Program execution state
<RAM>
<Host>
SCI
Programming/erase
control program
1. Initial state 2. Programming/erase control program transfer
3. Flash memory initialization 4. Writing new application program
FWE assessment program
Transfer program
Application
program
(old version)
,
FWE assessment program
Transfer program
Programming/erase control program Programming/erase control program
<Flash memory>
New application
program
Boot program
FWE assessment program
Transfer program
(1) The FWE assessment program that confirms that
the FWE pin has been driven high, and (2) the
program that will transfer the programming/erase
control program from the flash memory to on-chip RAM
should be written into the flash memory by the user
beforehand. (3) The programming/erase control
program should be prepared in the host or in the flash
memory.
When the FWE pin is driven high, user software
confirms this fact, executes the transfer program in the
flash memory, and transfers the programming/erase
control program to RAM.
The programming/erase control program in RAM is
executed, and the flash memory is initialized (to H'FF).
Erasing can be performed in block units, but not in byte
units.
Next, the new application program in the host is written
into the erased flash memory blocks. Do not write to
unerased blocks.
New application
program
<Flash memory>
Boot program
FWE assessment program
Transfer program
Application
program
(old version)
Figure 7.5 User Program M ode (Example)
Rev. 1.0, 02/00, page 129 of 1141
Differences between Boot Mode and User Program Mode
Boot Mode User Program Mode
Entire memory erase Yes Yes
Block er ase No Yes
Programming control program*Program/program-verify Erase/erase-verify
Program/program-verify
Note: *To be provided by t he user, in accor dance with the recommended algorithm.
Block Confi guration
The main ROM area is divided into three 64-kbyte blocks, one 32-kbyte bloc k, and eight 4-kbyte
blocks. The OSD ROM area is divided into two 1-kbyte blocks, one 2-kbyte block, and one 28-
kbyte block.
Address H'00000
Address H'3FFFF
256 kbytes
64 kbytes
64 kbytes
64 kbytes
32 kbytes
4 kbytes 8Address H'40000
Address H'47FFF
32 kbytes
OSD ROM area
Main ROM area
28 kbytes
2 kbytes
1 kbyte
1 kbyte
Figure 7.6 Flash Memory Block Configuration
Rev. 1.0, 02/00, page 130 of 1141
7.2.4 Pin Configuration
The flash memory is controlled by means of the pins shown in table 7.1.
Table 7.1 F l ash Me mory Pins
Pin Name Abbreviation I/O Function
Reset
5(6
Input Reset
Flash writ e enable FWE Input Flash program/erase protection by hardware
Mode 0 MD0 Input Set s this LSI operating m ode
Port 12 P12 Input Sets this LSI operating m ode when MD0 = 0
Port 13 P13 Input Sets this LSI operating m ode when MD0 = 0
Port 14 P14 Input Sets this LSI operating m ode when MD0 = 0
Transmit dat a SO1 Output Serial transmit data output
Receive dat a SI 1 Input Ser ial receive data input
7.2.5 Register Configur ati on
Table 7.2 shows the registers used to control the flash memory when enabled.
In order for these registers to be accessed, the FLSHE bit must be set to 1 in STCR.
Table 7.2 F l ash Me mory Re gi sters
Register Name Abbreviation R/ W Initi al Value Address*1
Flash memory control register 1 FLM CR1*5R/W*2H'00*3H'FFF8
Flash memory control register 2 FLM CR2*5R/W*2H'00*4H'FFF9
Erase block register 1 EBR1*5R/W*2H'00*4H'FFFA
Erase block register 2 EBR2*5R/W*2H'00*4H'FFFB
Serial timer control register STCR R/W H'00 H'FFEE
Notes: 1. Lower 16 bits of the address .
2. When the FWE bit in FLMCR1 is not set at 1, writes are disabled.
3. When a high level is input to the FWE pin, the initial value is H'80.
4. When a low level is input t o the FWE pin, or if a high level is input and the SWE bit in
FLM CR1 is not set, t hese re gist ers are init ia liz e d to H'00.
5. FLM CR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byt e accesses are valid
for these r egisters, the access requiring 2 states.
Rev. 1.0, 02/00, page 131 of 1141
7.3 F la sh Mem ory Regi st er Descri p t io ns
7. 3.1 Fl a sh Memory Co ntro l Regist er 1 (FLMCR1)
7
FWE
—*
R
6
SWE1
0
R/W
5
ESU1
0
R/W
4
PSU1
0
R/W
3
EV1
0
R/W
0
P1
0
R/W
2
PV1
0
R/W
1
E1
0
R/W
Bit
Initial value
R/W
:
:
:
Note: * Determined by the state of the FWE pin.
FLMCR1 i s an 8-bit re gister used for flash memory operating mode control. With addresses
H'00000 to H'3FFFF, program-verify mode or erase-verify mode is entered by setti ng SWE to 1
when FW E = 1, then set ting the PV1 bit and EV1 bit. Program mode is ent ered by setting SW E1
whe n FWE = 1, then setti n g the SWE1 bit and PSU1, and fi n ally setting the P1 bit. Wi th
addresses H'00000 to H'3FFFF, erase m o de is entered by setting SWE1 whe n FWE = 1, then
setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a reset, and in
standby mode. Its initial val ue is H'80 when a high level is input to t he FWE pin, and H' 00 when a
low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are
invalid.
Write s to the SWE1 bi t in FLMCR1 a re enabled only when FW E = 1; write s to th e ESU1, PSU1,
EV1 and PV1 bits only when FWE = 1 and SWE1 = 1; writes to the E1 bit only when FWE = 1,
SWE 1 = 1, and ESU1 = 1; and writes to the P1 bit onl y when FWE = 1, SWE 1 = 1, an d PSU1 = 1.
Bit 7Flash Write Enable (FWE): Sets hardware protection against flash memory
programming/erasing.
Bit 7
FWE Description
0 When a low level is input to the FWE pin (hardware-prot ected state)
1 When a high level is input to the FWE pin
Rev. 1.0, 02/00, page 132 of 1141
Bit 6Softwar e Write Enable (SWE): Enables or disable s flash memory programming. SWE
should be set before setting bits 5 to 0, bits 7 to 0 i n EBR1, and bits 3 to 0 in EBR2.
Bit 6
SWE1 Description
0 Writes are disabled (Init ial value)
1Writes are enabled
[Setting condition]
Setting is available when FWE = 1 is selected
Bit 5Erase Set-Up 1 (ESU1): Prepares for erase mode. ESU1 should be set to 1 before setting
th e E 1 bit in FLMCR1 to 1. Do not set the SWE1, PSU1, EV1, PV1, E1, o r P1 bit at the same
time.
Bit 5
ESU1 Description
0 Erase set - up clear ed (Initial value)
1Transition t o erase set-up mode
[Setting condition]
Setting is available when FWE = 1 and SWE = 1 are selected
Bit 4Program Set-Up 1 (PSU1): Prep ares for program mode. PSU1 should be set to 1 be fore
setting the P1 bit in FLMCR1 to 1. Do not set the SWE1, ESU1, EV1, PV1, E1 or P1 bit at the
sa me time .
Bit 4
PSU1 Description
0 Program set - up cleared (Initial value)
1Transition t o program set-up mode
[Setting condition]
Setting is available when FWE = 1 and SWE = 1 are selected
Rev. 1.0, 02/00, page 133 of 1141
Bit 3Erase-Ver ify (EV1): Selects era se-verify mode transition or clearing. Do not set the
SWE 1, ESU1, PSU1 , PV1 , E1, o r P1 bit at the same tim e.
Bit 3
EV1 Description
0 Erase-verify mode cleared (Init ial value)
1Transition t o erase-verify mode
[Setting condition]
Setting is available when FWE = 1 and SWE = 1 are selected
Bit 2Program-Verify (PV1): Selects program-verify mode t ransition or cl earing. Do not set
th e SWE1 , ESU1, PSU1 , E V1, E1, or P1 bit at the same time.
Bit 2
PV1 Description
0 Progr am-ver if y mode cleared (Init ial value)
1Transition t o program-verify m ode
[Setting condition]
Setting is available when FWE = 1 and SWE = 1 are selected
Bit 1Erase (E1): Selects erase mo de transitio n or clear i n g. Do not set t he SWE 1, ESU1, PSU1,
EV1 , PV 1 , or P1 b it at the same ti me.
Bit 1
E1 Description
0 Erase mode cleared (Init ial value)
1 Transition to erase mode
[Setting condition]
Setting is available when FWE = 1, SWE = 1, and ESU = 1 are select ed
Bit 0Program (P1): Selects p rogr am mode transitio n or cl eari n g. Do not set the SWE1, PSU1,
ESU1, EV1, PV1, or E1 bit at the same time.
Bit 0
P1 Description
0 Progr am mode cleared (Init ial value)
1 Transition to program mode
[Setting condition]
Setting is available when FWE = 1, SWE = 1, and PSU = 1 are select ed
Rev. 1.0, 02/00, page 134 of 1141
7. 3.2 Flash Memory Contro l Regi ster 2 (FLMCR2 )
7
FLER
0
R
6
SWE2
0
R/W
5
ESU2
0
R/W
4
PSU2
0
R/W
3
EV2
0
R/W
0
P2
0
R/W
2
PV2
0
R/W
1
E2
0
R/W
Bit
Initial value
R/W
:
:
:
FLMCR2 i s an 8-bit re gister used for flash memory operating control m ode.
With addresses H'40000 to H'47FFF, program -ve rify mode and erase -verify mode is ent e red by
setting SWE2 when FWE (FLMCR1) = 1, the n setting the E V2 bit and t he PV2 bit. Program mode
is entered by se tti ng SW E 2 when FW E (FLMCR1) = 1, then setting the SW E 2 bit and PSU2 bi t,
and finally setting the P2 bit.
With addresses H'40000 to H'47FFF, erase mode is e ntered by setti ng SWE2 when FW E
(FLMCR1) = 1, then setting the E SU2 bit , a nd finally setting the E2 bit . FLMCR2 is initialized to
H'00 by a reset, in standby mode, when a low le vel is i nput to t he FW E pin, and when a high level
is input to the FWE pin and the SWE2 bit in FLMCR2 is not set. FLER can be initialized only by
a reset.
Writes to the SWE2 bit in the FLMCR2 are enabled only when FWE (FLMCR1) = 1; writes to the
ESU2, PSV2, EV2, and PV2 bi t s only when FWE (FLMCR1) = 1 and SWE2 = 1; wri tes to the E 2
bit only when FWE (FLMCR1) = 1, SW2 = 1, and ESU2 = 1; writes t o the P2 bit only when FW E
(FLMCR1) = 1, SW E 2 = 1, and PSU2 = 1.
Bit 7Flash Memory Error (FLER): Indicates that an error has occ urred during a n operation
on flash memory (programming or erasing). Whe n FLE R is se t to 1, flash memory goe s to t he
error-protection state.
Bit 7
FLER Description
0 Flash memory is operating normally
Flash memory pr ogram/erase protection (error protection) is disabled
[Clearing condition]
Reset or hardware standby m ode (Init ial value)
1An error has occurred dur ing flash memory programming/erasing
Flash memory pr ogram/erase protection (error protection) is enabled
[Setting condition]
See section 7.6.3, Error Protection
Rev. 1.0, 02/00, page 135 of 1141
Bit 6Softwar e Write Enable 2 (SWE2): E na bles or disables flash memory programming
(tar get address ra nge: H'40000 t o H'47FFF). SW2 should be set when setting bits 5 to 0 and bits 7
to 4 in EBR2.
Bit 6
SWE2 Description
0 Writes are disabled (Init ial value)
1 Writes are enabled
[Setting condition]
Setting is available when FWE=1 is selected
Bit 5Erase Set-up 2 (ESU2): Pre pares for erase mode. (Target address range: H'40000 to
H'4 7 FFF). Do not set t he PSU2, E V2, PV2, W2, P2 bits at the same time .
Bit 5
ESU2 Description
0 Erase set - up clear ed (Initial value)
1Transition t o erase set-up mode
[Setting condition]
Setting is enabled when FWE=1 and SW2=1 are selected
Bit 4Program Set-up 2 (PSU2): Prepare s for program mode (Target address rang: H'40000 to
H'4 7 FFF). Do not set t he ESU2, EV2 , PV2, E2, P2 bits at t he same tim e.
Bit 4
PSU2 Description
0 Program set - up cleared (Initial value)
1Transition t o program set-up mode
[Setting condition]
Setting is enabled when FWE=1 and SW2=1 are selected
Bit 3Erase-Verify 2 (EV2): Selects erase-ve rify mode transition or clearing (target addre ss
range H'40000 to H' 47FFF). Do not set th e ESU2, PSU2, PV2, E2, P2 bits a t the same time.
Bit 3
EV2 Description
0 Erase-verify mode cleared (Init ial value)
1 Transition t o erase-ver if y mode
[Setting condition]
Setting is available when FWE=1 and SWE2=1 are select ed
Rev. 1.0, 02/00, page 136 of 1141
Bit 2Program-Verify 2 (P V2): Sel ects progra m-verify m ode tra nsition or clearing (t a rget
address range: H' 40000 to H'47FFF). Do not se t the ESU2, PSU2, EV2, E2, a nd P2 bits at the
sa me time .
Bit 2
PV2 Description
0 Program-verify m ode cleared
1 Transition t o program - verify m ode
[Setting condition]
Setting is available when FWE=1 and SWE2=1 are select ed
Bit 1Erase 2 (E2): Selects era se m ode transition or clearing (targe t address range: H'40000 to
H'4 7FFF, do not set the ESU2, PSU2, EV2, PV2, and P2 bits at the same time.
Bit 1
E2 Description
0 Erase mode cleared
1Transition t o erase m ode
[Setting condition]
Setting is available when FWE=1, SWE2=1, and ESU=1 are selected
Bit 0Program 2 (P2): Selects program mode transition or cle a ring (ta rget addre ss range :
H'40000 to H'47FFF). Do not set th e ESU2, PSU2, EV2, PV2, and E2 bits a t the same time.
Bit 0
P2 Description
0 Progra m mode cleared
1Transition to program mode
[Setting condition]
Setting is available when FWE=1, SW2=1, and PSU2=1 are selected
Rev. 1.0, 02/00, page 137 of 1141
7.3.3 Erase Block Re gister 1 (EBR1)
7
EB7
0
R/W
6
EB6
0
R/W
5
EB5
0
R/W
4
EB4
0
R/W
3
EB3
0
R/W
0
EB0
0
R/W
2
EB2
0
R/W
1
EB1
0
R/W
Bit
EBR2
Initial value
R/W
:
:
:
:
EBR1 is an 8-bit register that specify the flash memory erase area block by block.
EBR1 is initialized to H'00 by a reset, in standby mode, whe n a low level is input to the FW E pin,
and when a high level is input to the FWE pin and the SWE1 bit in FLMCR1 is not set. When a bit
in EBR1 i s set to 1, the corresponding block c an be e rased. Othe r blocks are era se-protected. Set
only one bit in EBR1 a nd EBR2. More than one bit cannot be set. If set, all bits are cleared to 0.
Table 7.3 shows the flash memory block c onfiguration.
7.3.4 Erase Block Register 2 (EBR2)
7
EB15
0
R/W
6
EB14
0
R/W
5
EB13
0
R/W
4
EB12
0
R/W
3
EB11
0
R/W
0
EB8
0
R/W
2
EB10
0
R/W
1
EB9
0
R/W
Bit
EBR2
Initial value
R/W
:
:
:
:
EBR2 is an 8-bit register that specify the flash memory erase area block by block; EBR2 is
initialized to H'00 by a reset, is standby mode, and when a low leve l is input to the FWE pin. Bits
3 to 0 are initialized to 0 when a high level is input to the FWE pin and the SWE1 in FLMCR1 is
not set. Bits7 to 4 are initialized to 0 when the SWE2 in FLMCR2 is not set. When a bit in EBR2
is set t o 1, the corresponding bl ock can be era sed. Other blocks are erase-prote cted.
Set only one bit in EBR1 and EBR2. More than one bit cannot be set. If set, all bits are cleared to
0.
The flash memory bl ock confi guration i s shown in ta ble 7.3.
Rev. 1.0, 02/00, page 138 of 1141
Table 7.3 F l ash Me mory Erase Bl ocks
Block (Size) Address
EB0 (4 kbytes) H'000000 t o H'000FFF
EB1 (4 kbytes) H'001000 t o H'001FFF
EB2 (4 kbytes) H'002000 t o H'002FFF
EB3 (4 kbytes) H'003000 t o H'003FFF
EB4 (4 kbytes) H'004000 t o H'004FFF
EB5 (4 kbytes) H'005000 t o H'005FFF
EB6 (4 kbytes) H'006000 t o H'006FFF
EB7 (4 kbytes) H'007000 t o H'007FFF
EB8 (32 kbytes) H'008000 to H'00FFFF
EB9 (64 kbytes) H'010000 to H'01FFFF
EB10 (64 kbytes) H'020000 to H'02FFFF
EB11 (64 kbytes) H'030000 to H'03FFFF
EB12 (1 kbyte) H'040000 to H'0403FF
EB13 (1 kbyte) H'040400 to H'0407FF
EB14 (2 kbytes) H'040800 t o H'040FFF
EB15 (28 kbytes) H'041000 to H'047FFF
7.3.5 Serial/Timer Control Register (STCR)
7
—
0
—
6
IICX1
0
R/W
5
IICX0
0
R/W
4
—
0
—
3
FLSHE
0
R/W
0
—
0
—
2
OSROME
0
R/W
1
—
0
—
Bit
Initial value
R/W
:
:
:
STCR is an 8-bit re ad/write regi ster that controls the I2C bus inte rface operating mode, on-chip
fl a sh mem ory (i n F-ZTAT version s), and OSD ROM. For detai ls on IIC bus interfa ce , refer to
section 23, I2C Bus Interface. If a module controlled by STCR is not used, do not write 1 to the
corresponding bit. STCR is initialized to H'00 by a reset.
Bits 6 to 5I2C Contr ol (IICX1, IICX0): These bits control the operation of the I2C bu s
interface. For details, see section 23, I2C Bus Inte rface.
Rev. 1.0, 02/00, page 139 of 1141
Bit 3Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables
read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash
memory cont rol registers are de selected. In this ca se, the flash memory control regi ster contents
are retained.
Bit 3
FLSHE Description
0 Flash memory control registers deselected (Init ial value)
1 Flash memory cont rol regist ers selected
Bit 2OSD ROM Enable (OSROME): Co ntr ols the OSD chara cter data ROM (OSDROM)
acc e ss. When this bit i s set to 1, the OSDROM can be accesse d by the CPU, and whe n this bit i s
cl ea red to 0, the OSDROM can n ot be accesse d by the CPU but acce sse d by the OSD module .
Bef o re writi ng to or erasin g the OSDROM in the F-ZTAT ve rsion, be sure to set this bit to 1.
Not e : Du ring OSD di splay, the OSDROM cann ot be accessed by the CPU. Bef ore acce ssing the
OSDROM by the C PU, be sure to clear the OSDON bit in the scree n cont rol re gist e r to 0
then set the OSROME bit to 1. If the OSROME bit is set to 1 during OSD display , the
character data ROM cannot be accessed correctly by CPU.
Bit 2
OSROME Description
0 OSD ROM is accessed by the OSD (Initial value)
1 OSD ROM is accessed by the CPU
Bits 7, 4, 1 and 0Reserved: Always read as 0. If 1 is written to, correct operation cannot be
guaranteed.
Rev. 1.0, 02/00, page 140 of 1141
7.4 On-Board Programming Modes
When pins are set to on-board programming mode, program/erase/verify ope rations ca n be
performed on the on-chi p flash me mory. T here are two on-board program ming mode s: boot mode
and user program m ode. T he pin settings for t ransition to ea ch of the se m odes are shown in table
7.4 . For a diagra m of the transitions to the v arious fl as h memor y mo des, see f igu re 7 .3.
Table 7.4 Setti ng On-Boar d Programmi ng Modes
Mode Pin
Mode Name FWE MD0 P12 P13 P14
Boot mode 1 0 1*21*21*2
User program mode 1*11
Notes: 1. I n user pr ogram m ode, the FWE pin should not be constantly set t o 1. Set FWE to 1 to
make a transition t o user program mode before performing a program/erase/ver ify
operation.
2. Can be used as I/O ports after boot mode is initiat ed.
Rev. 1.0, 02/00, page 141 of 1141
7.4.1 Boot Mode
When boot mode is used, the flash memory programming cont rol program must be prepared in t he
host before hand. T he channel 1 SCI to be used is se t to asynchronous m ode.
When a reset -start is e xecuted aft er the LSI’s pins have be e n set to boot mode, the boot program
built into the MCU is started a nd the programming cont rol program prepared in t he host is serially
transmitted to the L SI via the SCI. In the LSI, the programming c ontrol progra m received via t he
SCI is written into the programming control program area in on-chi p RAM. After t he transfer is
completed, c ontrol bra nches to the start addre ss of the programming c ontrol program area and the
programming c ontrol progra m execution st ate is e ntered (flash m emory programming is
performed).
The transferre d programming control program must therefore i nclude coding t hat follows t he
programming algorith m given later .
Figure 7. 7 shows the system confi guration in boot mode. Figure 7.8 shows the boot program mode
execution procedure.
SI1
SO1 SCI1
This LSI
Flash memory
Write data reception
Verify data
transmission
Host
On-chip RAM
Figure 7.7 System Configur ation in Boot Mode
Rev. 1.0, 02/00, page 142 of 1141
Start
Set pins to boot mode and
execute reset-start
Host transfers data (H'00)
continuously at prescribed bit rate
Host transmits user program
sequentially in byte units
Transfer received programming
control program to on-chip RAM
This LSI calculates bit rate and
sets value in bit rate register
Host transmits number of user
program bytes (N), upper byte
followed by lower byte
This LSI transmits received user
program to host as verify data
(echo-back)
n = 1
End of transmission
n = N?
n+1 → n
Note :
Yes
No
This LSI measures low period of
H'00 data transmitted by host
After bit rate adjustment, transmits
one H'00 data byte to host to
indicate end of adjustment
Upon receiving H'55, this LSI
sends part of the boot program to
RAM
Host confirms normal reception of
bit rate adjustment end indication
(H'00) and transmits one H'55
data byte
After confirming that all flash
memory data has been erased,
this LSI transmits one H'AA data
byte to host
Transmit one H'AA data byte to
host, and execute programming
control program transferred to on-
chip RAM
Check flash memory data, and if
data has already been written,
erase all blocks
This LSI transmits received
number of bytes to host as verify
data (echo-back)
If a memory cell does not operate normally and cannot be erased, one
H'FF byte is transmitted as an erase error, and the erase operation and
subsequent operations are halted.
Figure 7.8 Boot Mode Execution Procedure (Preliminary)
Rev. 1.0, 02/00, page 143 of 1141
Automatic SCI Bit Rate Adjustment
Start
bit Stop
bit
D0 D1 D2 D3 D4 D5 D6 D7
Low period (9 bits) measured (H'00 data) High period
(1 or more bits)
Figure 7.9 Automatic SCI Bit Rate Adjustment
When boot mode is initiated, the LSI me a sures the low pe riod of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format shoul d be set a s follows: 8-bit data, 1 stop bit, no pari ty. The LSI calculates the bit rate of
the transmission from the host from the measured low period, and transmits one H'00 byte to the
host to indicate the e nd of bit rate adjustm ent. The host should confirm tha t this a djustment end
indication (H'00) has been received normally, and tra nsmit one H'55 byte to the LSI. If rec eption
cannot be performed normally, initiate boot mode agai n (reset), and repe at the above opera t ions.
Depending on the host's transmission bit rate and the MCU's system clock frequency, there will be
a discrepancy between the bit rates of the host and t he LSI. To ensure correct SCI operation, the
host's transfer bit rate should be set to (2400, 4800, or 9600) bps.
Table 7.5 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the LSI’s bi t rate is possible. T he boot program should be exe cuted wit hin this
system clock ra nge.
Table 7.5 System Clock Frequencies for which Automatic Adjustment of This LSI Bit
Rate Is Possi ble
Host Bit Rate (bps) System Clock Frequency
9600 8 MHz to 10 MHz (T. B.D.)
4800 4 MHz to 10 MHz (T. B.D.)
2400 2 MHz to 10 MHz (T. B.D.)
Rev. 1.0, 02/00, page 144 of 1141
On-Chip RAM Area Divisions i n Boot M ode: In boot mode, the T BD-byte are a from TBD t o
TBD is reserved for use by t he boot program, as shown i n figure 7.10. The a rea to which the
programming c ontrol progra m is transferred is TBD to TBD (TBD bytes). T he boot program area
can be used when the progra mming c ont rol program transferred into RAM enters t he execution
state. A stack area should be set up as required.
TBD
TBD
Programming
control program
area
(TBD bytes)
TBD
Boot program
area*
(TBD bytes)
Note: * The boot program area cannot be used until a transition is made to the execution
state for the programming control program transferred to RAM. Note that the boot
program reamins stored in this area after a branch is made to the programming
control program.
Fi g ure 7. 10 RAM Ar eas i n Boot Mode
Rev. 1.0, 02/00, page 145 of 1141
Notes on Use of Boot Mode:
1. When the chip comes out of reset in boot mode, it measures the low period of the input at the
SCI's SI1 pin. T he reset shoul d end with SI1 pin high. After the re set ends, i t takes about 100
states for the c hip to get ready to measure the low period of the SI1 pi n input.
2. In boot mode, if any data has been programmed into the flash memory (if al l data is not 1), all
flash me m ory blocks are erased. Boot mode is for use when user program mode i s
unavailable, such as the first time on-board programming is performe d, or if the program
activated in user program mode is accide nt ally eras ed.
3. Inte rrupts cannot be used while the fl ash m emory is being progra mmed or erased.
4. The SI1 and SO1 pins should be pulled up on the boa rd.
5. Before branching t o the programming cont rol program (RAM a rea TBD), the chip terminat e s
transmit and receive operations by the on-chi p SCI (channel 1) (by clearing the RE and TE bits
in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin,
SO1, goes to the high-l e vel output state (P21PCR = 1, P21PDR = 1).
The conte nts of t he CPU' s internal gene ral registers are undefine d at this time, so these
registers m ust be initia l ized immediately aft er branchi ng to the programming control program .
In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack
area must be specified for use by the program ming cont rol program.
The initial values of other on-chip registers are not changed.
6. Boot mode can be entered by making the pin set tings shown in tabl e 7.4 and executing a re set-
start.
When the chip detects the boot mode setting at reset release*1, it retains that state internally.
Boot mode can be cleared by driving the rese t pin low, waiting at least 20 states, then setting
the FWE pin and mode pins, and executing reset release*1. Boot mode can also be cleared by a
WDT overfl ow re set.
If the mode pin input levels are changed in boot mode, the boot mode state will be maintained
in the microcomputer, and boot mode continued, unless a reset occurs. However, the FWE pin
must not be driven low while the boot program is running or flash memory is being
programmed or erased.
Notes: 1. Mode pin a nd FW E pin input must satisfy the mode programming setup time (tMDS = 4
states) with respect to the reset release timing.
Rev. 1.0, 02/00, page 146 of 1141
7.4 .2 Us er Progra m Mode
When set to user program mode, the chip can program and erase its flash memory by executing a
user program /erase c ontrol program. The refore, on-board reprogramming of the on-chip fl ash
memory ca n be ca rried out by providing on-board me a ns of FWE cont rol and supply of
programming data, and storing a program/erase control program i n part of the program area a s
necessary.
In this mode, the chip starts up in mode 1 and applies a high level to the FWE pin.
The flash memory i tself cannot be read whi le the SWE bi t is set t o 1 to perform programming or
erasing, so the control program that performs programming and e rasing should be run in on-chip
RAM or external memory.
Figure 7. 11 shows the procedure for exe cuting t he program /erase control program when
transferred to on-ch ip RAM.
Clear FWE
FWE = high
Branch to flash memory
application program
Branch to program/erase control
program in RAM area
Execute program/erase control
program (flash memory rewriting)
Transfer program/erase
control program to RAM
MD0 = 1
Reset start
Write the FWE assessment program and
transfer program (and the program/erase
control program if necessary) beforehand
Note: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only
when the flash memory is programmed or erased. Also, while a high level is applied to the
FWE pin, the watchdog timer should be activated to prevent overprogramming or
overerasing due to program runaway, etc.
Figure 7.11 User Program Mode Execution Procedure (Preliminary)
Rev. 1.0, 02/00, page 147 of 1141
7.5 Programm ing/Erasing Flash Memory
In the on-board programming modes, flash memory programming and era sing is pe rformed by
software, using the CPU. There are four flash memory operating modes: program m ode, erase
mode, progra m-verify mode, and e rase-verify m ode. With a ddresses H'00000 to H' 3FFFF,
tr a n sit i ons to the se modes ca n be made by set tin g the PSU1, ESU1, P1, E1, PV1 an d EV1 bits in
FLMCR1. With addresses H'40000 to H'47FFF, transitions to these modes can be made by setting
the PSU2, ESU2, P2, E2, PV2, and EV2 bi t s in the FLMCR2.
The flash memory c annot be read whil e being program med or erased. There fore, the program that
controls flash memory programming/erasing (t he programming c ontrol program) should be
located and execute d in on-chip RAM or extern al memory.
Notes: 1. Ope rat i o n is not guarante e d if settin g /re set tin g of the SWE1, ESU1, PSU1 , EV1, PV1,
E1 , and P1 bit s in FLMC R 1, an d the SWE2, ESU2 , PSU2, EV2, PV2, E 2, an d P2 in
FLMCR2 , is executed by a progr am in flash memory.
2. W hen programming or erasing, set FWE to 1 (programming/erasing will not be
executed if FWE = 0).
3. Perform programming in the erased state. Do not perform additiona l programming on
previously programmed a ddresses.
4. Do not write to a ddresses H'00000 to H'3FFFF and H' 40000 to H' 47FFF at the same
time. Otherwise operation ca nnot be guaranteed.
5. Do not operate the OSD whe n writing or erasing addresses H'40000 to H'47FFF. Do
not set t he OSROME in ST CR to 1 before ma nipulating t he flash control re gister.
7.5.1 Pr ogram Mode (n=1 when the target address r ange i s H'00000 to H'3FFFF and
n=2 when the target address range i s H'40000 to H'47FFF)
Follow the procedure shown in the program/program-verify flowcha rt in figure 7.12 to write data
or program s to fl a sh memory. Performing program opera t ions a ccording to thi s flowchart wil l
enable da ta or programs to be written to flash memory without subje cting t he device to voltage
stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a
time.
Following the elapse of 1.0 µs or more after the SWEn bit is set to 1 in flash memory control
register n (FLMCRn), 128-byte program data is stored i n the progra m data area and reprogram
data area, and the 128-byte data in the reprogram data area written consecutively to the write
addresses. The lower 8 bit s of the start addre ss written to m ust be H'00, or H'80. One hundred
and twent y-eight consecutive byte da ta transfers are performed. T he program address and
program data are latched in the flash memory . A 128-byte data transf er must be perform ed ev en if
writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
Next, the watchdog t imer is set to pre vent ove rprogramming in the event of program runaway, etc.
Set 6.6 ms as the WDT overflow period. After this, preparation for program mode (program
set u p) i s carried out by sett ing the PSUn bit in FLMCRn, and after t he elapse of 50 µs or more, the
operating m ode is switched to program mode by setting the Pn bit i n FLMCRn. The time duri ng
Rev. 1.0, 02/00, page 148 of 1141
which the Pn bi t is set is t he flash memory programming t ime. Make a program setting for one
programming operation using the table in the progra mming flowchart.
7.5.2 Program-Ve rify Mode
In program -verify mode, the da ta written in program mode i s read to c heck whet her it ha s been
correctly written in the flash memory.
After the elapse of a given programming t ime, the progra mming mode is exited (the P bit i n
FLMC R1 i s clea re d, then the PSU bit i n FLMC R2 is cleare d at least 5 µs later). Th e watchdo g
timer is cleared after the elapse of 5 µs or more, and the ope rating mode is switched t o program-
verify mode by setting the PVn bit in FLMCRn. Before reading in program-verify mode, a
dummy wri te of H'FF data should be made to the addre sses to be read. T he dummy wri te should
be executed after the elapse of 4 µs or mo re. When the flash memory is r ead in th is state (ver if y
data is read in 16-bit units), the data at the latched address is read. Wait at least 2 µs after the
dummy write before performing this read operation. Next, the originally written data is compared
with the verify da ta, and reprogram data is computed (see figure 7. 12) and transferred t o the
reprogram data area. After 128 bytes of data ha ve been verified, exit program-verify mode, wait
for at l east TBD µs, then clear the SWEn bit in FLMCRn. If reprogramming is necessary, set
program mode a gain, and repeat the program/program-verify sequence as before. However,
ensure that the progra m/program -verify seque nce is not repeate d more than 1,000 tim e s on the
same bits.
Rev. 1.0, 02/00, page 149 of 1141
Programming pulse apply subroutine
Start
Set SWE1 (2) bit in FLMCR(2)
Set PV1(2) bit in FLMCR1(2)
Clear PV1(2) bit in FLMCR1(2)
Clear SWE1(2) bit in FLMCR1(2)
Write pulse additional program pulse 10 µs
Store 128-byte program data in program
data area and reprogram data area
Write 128-byte program data in RAM reprogram
data area consecutevely to flash memory
Write 128-byte program data in RAM additional
data area consecutively to flash memory
Wait 1 µs
Wait 4 µs
Wait 2 µs
Wait 2 µs
Wait 100 µs
End of programming
Programming pulse 30 µs or 200 µs
H'FF dummy write to verify address
Read verify data
Calculate additional program data
Calculate reprogram data
Complete 128-byte
data verification?
Transfer additional program data to additional program data area
Transfer reprogram data to reprogram data area
Program data= verify data?
Refer to note *6
for the pulse width
*1
*2
*5
*4
*3
*4
*1
NG
NG
NG
NG
NG
OK
OK
OK
OK
OK
6n?
n←n+1
6n ?
m= 0?
Clear SWE1 (2) bit in FLMCR1(2)
Wait 100 µs
Programming Failure
NG
OK
n 1000?
m= 1
*4
Call subroutine
n= 1
m= 0
Enable WDT
Set PSU1 (2) bit in FLMCR1 (2)
Set P1 (2) bit in FLMCR1 (2)
Clear P1(2) bit in FLMCR1 (2)
Clear PSU1(2) bit in FLMCR1 (2)
Wait 50 µs
Wait 5 µs
Wait 5 µs
Disable WDT
End of subroutine
Note: 6. Programming pulse width
Number of times
of programming Programming
time (z) µsec
The programming pulse must be 10 µs in
additional programming
Perform programming after erasing data. Do not perform additional programming to addresses that have already been written to.
Notes: 1. Data transfer is performed by byte transfer. The lower eight bits of the start address must be H'00 or H'80. A 128-byte data transfer must be performed even if writing
fewer than 128 bytes: in this case, H'FF must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Even in case of the bit which is already-programmed in the 128-byte programming loop, perform additional programming if the bit fails at the next verify.
4. An area for storing program data (128 bytes), reprogram data (128 bytes), and additional program (128bytes) must be provided in RAM. The contents of the reprogram
and additional program areas are rewritten as programming processes.
5. A 30 µs or 200 µs programming pulse must be applied.
For details on programming pulse, refer to Notes*6.
To perform additional data programming, apply a programming pulse of 10 µs. Reprogram data X' is the reprogram data after program pulse is applied.
Program data storage are
(128 bytes)
Reprogram data storage
area (128 bytes)
Additional program data
storage area (128 bytes)
Reprogram Data Calculation Table Additiona l program data calculation table
Increment address
Wait for 10 µs, 30 µs or 200 µs
1
2
3
4
5
6
7
8
9
10
11
12
13
998
999
1000
30
30
30
30
30
30
200
200
200
200
200
200
200
200
200
200
RAM
Source Data (D)
0
0
1
1
Reprogram data (X)
1
0
1
1
Additional program data (Y)
0
1
1
1
Reprogram data (X')
0
0
1
1
CommentsVerify data (V)
0
1
0
1
Verify data (V)
0
1
0
1
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Comments
Additional programming performed
Additional programming not performed
Additional programming not performed
Figure 7.1 2 Pro gram/ Progra m - V erify Flowcha rt
Rev. 1.0, 02/00, page 150 of 1141
7.5.3 Erase Mode (n = 1 when the target address range is H'00000 to H'3FFFF and n = 2
when the target address range i s H' 40000 to H'47F FF)
Flash memory era sing shoul d be perform ed block by block following t he proce dure shown in the
erase/erase-verify flowchart (single-block erase) shown in figure 7.13.
To perform data or program e ra sure, make a 1 bit set ting for the flash memory area to be erased in
erase block re gi ster 1 or 2 (EBR1 or EBR2) at least 1 µs after setting th e SW En bit to 1 in flash
memory cont rol register n (FLMCRn). Next, the watchdog t imer is set to pre vent ove rerasing i n
the event of program runaway, etc.
Set more than 19.8 ms as the WDT overflow period. After this, preparation for erase mode (erase
setup) is carried out by setting the ESUn bit in FLMCRn, and after a elapse of 100 µs or mor e, the
operating m ode is switched to era se mode by setting the En bit in FLMCRn. The time during
which the En bit is set is the fl as h memo ry erase time. Ensure that er ase time doe s no t exceed 1 0
ms.
Note: W ith flash memory era sing, preprogramming (setting all data in the memory t o be erased
to 0) is not necessary before starting the erase procedure.
Rev. 1.0, 02/00, page 151 of 1141
End of erasing
START
Set SWE bit in FLMCR1
Set ESU1 (2) bit in FLMCR1 (2)
Set E1 (2) bit in FLMCR1 (2)
Wait 1 µs
Wait 100 µs
n = 1
Set EBR1 (2)
Enable WDT
*
3
Wait 10 ms
Wait 10 µs
Wait 10 µs
Wait 6 µs
Set block start address to
verify address
Wait 2 µs
Wait 4 µs
*
2
*
4
Start of erase
Clear E1 (2) bit in FLMCR1 (2)
Clear ES1 (2) bit in FLMCR1 (2)
Set EV1 (2) bit in FLMCR1 (2)
H'FF dummy write to verify address
Read verify data
Clear EV1 (2) bit in FLMCR1 (2)
Wait 4 µs
Clear EV1 (2) bit in FLMCR1 (2)
Clear SWE bit in FLMCR1
Disable WDT
Halt erase
*
1
Verify data =
all 1?
Wait 100 µs Wait 100 µs
End of erasing of
all erase blocks?
Erase failure
Clear SWE bit in FLMCR1
n ≥ 100?
NO
NO
NO NO
YES
YES
YES
YES
Notes: 1.
2.
3.
4.
Increment
address
n←n+1
Last address
of block?
Preprogramming (setting erase block data to all 0) is not necessary.
Verify data is read in 16-bit (word) units.
Set only one bit in EBR. More than two bit cannot be set.
Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
Figure 7.1 3 Erase/E ra s e- Verif y Flo w ch art
Rev. 1.0, 02/00, page 152 of 1141
7.5.4 Erase-Verify Mode (n = 1 when the target address range is H'00000 to H'3FFFF
and n = 2 when the ta rget address range is H'4 0000 to H'47F FF)
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of t he erase time, erase m ode is exited (the En bit in FLMCRn is c leared, t hen the
ESU n bit is cl eared at least 10 µs later), the watchdog t imer is cleared after the elapse of 10 µs o r
more, and the ope rating mode i s switched to erase-ve ri fy m ode by setting t he EVn bit in
FLMCRn. Before reading in e rase-verify mode, a dummy write of H'FF data should be made to
the addresses to be read. The dummy write should be executed after the elapse of 6.0 µs or more.
When the flash memory is read in this state (verify dat a is read in 16-bit uni ts), the data at the
latched address is read. Wait at least 2 µs after the dummy write before performing t his read
operation. If the read data has bee n erased (all 1), a dummy writ e is performed to the next
address, a nd erase-ve rify is perform ed. If the re a d data has not been erase d, set e ra se m ode aga in,
and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/erase-
verify sequence is not repeated more than 100 times. When verification is completed, exit erase-
verify mode, and wait for at least 4 µs. If erasure has been completed on all the erase blocks, clear
the SWEn bit in FLMCRn. If there are any unerased blocks, make a 1 bi t setting for the flash
memory area to be erased, and repeat the erase/erase-verify sequence in the same way.
Rev. 1.0, 02/00, page 153 of 1141
7.6 Flash Memory Protection
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and e rror protection.
7.6.1 Hardware Protection
Hardware protection re fers to a state in which programming/erasing of flash me m ory is forcibly
disabled or aborted. Hardware prot ection is reset by settings in flash memory control registers 1
and 2 (FLMCR1, FL MCR2) a nd erase bl ock registers 1 and 2 (EBR1, E BR2). (See table 7.6.)
In error protected sta te, the FLMCR1, FLMCR2, EBR1, and EBR2 set tings are maintained.
Table 7.6 H ar dware Prote c tion
Functions
Item Description Program Erase
FWE pin
protection •When a low level is input t o the FWE pin, FLMCR1,
FLMCR2 (excluding the FLER bit), EBR1, and EBR2
are initialized, and t he program/erase-protected state
is entered
Yes Yes
Reset/standby
protection •In a reset (including a WDT overflow r eset) and in
standby m ode, FLM CR1, FLMCR2, EBR1, and EBR2
are initialized, and t he program/erase-protected state
is entered
•In a reset via the
5(6
pin, t he reset state is not
entered unless the
5(6
pin is held lo w until osc illa tion
st a b iliz e s aft e r po w erin g on. In the case of a reset
during operation , hold the
5(6
pin low for the
5(6
pulse wid th specifie d in the AC charact eris tics
Yes Yes
Rev. 1.0, 02/00, page 154 of 1141
7.6.2 Software Pr otection
Software protection can be implemented by setting the SWE1 bit in FLMCR1 and SWE2 bit in
FLMCR2 a nd erase block re gi sters 1 and 2 (EBR1, EBR2). When software protection is in effect,
setting the P1 or E1 bit in flash memory cont rol regi ster 1 (FLMCR1) or P2 or E2 bi t in fla sh
memory cont rol register 2 (FLMCR2) does not cause a transi tion to program mode or e rase mode.
(See table 7.7.)
Table 7.7 Software Protection
Functions
Item Description Program Erase
SWE bit
protection •Clearing the SWE bit to 0 in FLMCR1 sets the
program/erase-protected stat e for all blocks
(Execute in on-chip RAM or external memory)
Yes Yes
Block
specification
protection
•Erase prot ection can be set for individual blocks by
settings in erase block registers 1 and 2 (EBR1, EBR2)
•Setting EBR1 and EBR2 to H'00 places all blocks in
the erase-pro tected state
−Yes
Rev. 1.0, 02/00, page 155 of 1141
7.6 .3 Erro r Prote ct ion
In error protection, an error is detected when MCU runaway occurs duri ng fl a sh memory
programming/ erasing, or operation i s not performed in accordance with the progra m/erase
algorithm, and t he program/erase operation is aborted. Aborting the program/erase operation
prevents damage to t he flash memory due to overprogramming or overerasing.
If the MCU malfunctions during flash memory programming/e ra sing, the FLER bi t is set to 1 in
FLMCR2 a nd the e rror protection state is ente re d. The FLMCR1, FLMCR2, EBR1, and EBR2
settings a re retained, but program mode or e rase mode is abort ed at the poi nt at which the error
occurred. Program mode or e rase mode cannot be re-entered by re -setting t he P or E bit .
However, PV1, PV2, EV1 and EV2 bit setting is enabled, and a transition can be made to verify
mode.
FLER bit setting conditions are as follows:
• When fl ash memory is read during programming/erasing (inc luding a vector rea d or i nstruction
fetch)
• Immediately a fter except ion handling (excluding a reset) during programming/erasing
• When a SLEEP instruc tion (inc l uding standby) i s exe cuted during programming/erasing
Error prot ection is released onl y by a reset and i n hardware standby mode.
Figure 7. 14 shows the flash memory sta te transi t ion diagram.
: Memory read possible
: Verify-read possible
: Programming possible
: Erasing possible
RD
VF
PR
ER
[Legend] : Memory read impossible
: Verify-read impossible
: Programming impossible
: Erasing impossible
PR ER FLER = 0
Error occurrence
Error occurrence
Power-down mode
= 0
= 0
= 0
P FLER = 0
Program mode
Erase mode Reset
(hardware protection)
RD VF FLER = 1 FLER = 1
Error protection mode Error protection
mode (power-down mode)
Power-down mode
FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2
initialization state
FLMCR1, FLMCR2,
EBR1, EBR2 initialization
state
Power-down mode release
Figure 7.14 Flash Me mory State Transitions
Rev. 1.0, 02/00, page 156 of 1141
7.7 Interrupt Handling when P rogramming/Erasing Flash Memory
All interrupts, including NMI input is disabl ed when flash memory is being programmed or erased
(when the P1 or E1 bit is set in FLMCR1, or the P2 or E2 bit is set in FLMR2), and while the boot
program is executing i n boot mode*1, to give priority to the progra m or eras e operation. There are
three reasons for this:
• Interrupt during progra mming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
• In the i nterrupt e xception handling seque nce duri ng programming or e rasing, the vector would
not be read correctly*2, possibly resultin g in MCU runawa y.
• If interrupt occ urred during boot program execution, it would not be possible to e xecute the
normal boot mode seque nce.
For these reasons, in on-board programming mode alone the re are conditions for disabling
interrupt, as an exception to the ge neral rule. Howe ver, this provision does not guarantee norm al
erasing a nd programming or MCU operation. All requests, including NMI i nput, must therefore
be disabl e d inside a nd outside t he MCU during FWE a pplication. Interrupt i s also disabled in the
error-protection state while the P1 or E1 bit remains set in FLMCR1, or P2 or E2 bit remains set in
FLMCR2.
Notes: 1. Interrupt requests must be disabled inside and outside the MCU until data write by the
write control program (vector ta ble and NMI processing program) is compl ete.
2. The vector may not be read correctly in this case for the following two reasons:
• If flash memory is read while being progra mmed or erased (whi le the P or E bit is set
in FLMCR1), correct re ad data will not be obtained (undetermined values will be
returned).
• If the interrupt entry in t he NMI vector table has not been programmed yet, interrupt
exception handling will not be executed correctly.
Rev. 1.0, 02/00, page 157 of 1141
7.8 Flash Memory Writ er Mode
7.8 .1 Writ er Mode Setting
Programs and data can be written a nd erased in writer mode as well as in the on-boa rd
programming modes. In writer mode, flash memory read mode, auto-progra m mode, auto-erase
mode, and status rea d mode a re supported with these device type s. In auto-program m ode, a ut o-
erase mode, and status rea d mode, a status polling procedure is used, and i n status read mode ,
detailed inte rnal signa l s are output aft er execution of an auto-program or aut o-e rase operation.
7.8.2 Socket Adapters and Memory Map
In writer mode, a socket adapter is mounted on the writ er programmer. The socket ada pter
product codes are listed in table 7.8.
Figure 7. 15 shows the memory map in writer mode.
Tabl e 7.8 Socket Adapter Product Co des
Product Codes Package Socket Adapter Product Code
HD64F2199 112-pin QFP TBD
H8S/2199
H'000000
MCU mode Writer mode
H'47FFF
H'00000
H'47FFF
On-chip ROM area
Figure 7.1 5 Mem ory Map in Writer Mo de
Rev. 1.0, 02/00, page 158 of 1141
7.8 .3 Writ er Mode Operatio n
Table 7.9 shows how the different operating modes are set when using writer mode, and table 7.10
lists the commands used in writer mode. Details of each mode are given below.
• Memory Rea d Mode: Memory read mode supports byte reads.
• Auto-Progra m Mode : Auto-program mode support s progra m ming of 128 byt e s at a t ime.
Status polling is used to confirm the end of auto-program ming.
• Auto-Erase Mode: Auto-era se mode supports autom atic erasing of the e ntire flash memory.
Status polling is used to confir m the en d o f auto-erasing.
• Status Read Mode: Status polling is used for auto-programming and auto-erasing, and normal
termination can be confirmed by reading the IO6 signal. In status read mode, error
information is output i f an error occurs.
Table 7.9 Settings for Each Ope rating Mode in Writer Mod e
Pin Names
Mode FWE
&(
&( 2(
2( :(
:(
IO0 to IO7 A0 to A17
Read H or L L L H Data output Ain
Output disable H or L L H H Hi-z X
Comma n d write H or L*3L H L Data input Ain*2
Chip disable*1H or L H X X Hi-z X
Notes: 1. Chip disable is not a st andby state; internally, it is an operation state.
2. Ain indicates t hat there is also address input in auto-program mode.
3. For command wr it es when making a transition to auto-program or auto-erase mode,
input a high level t o the FWE pin.
Table 7.10 Writer Mode Commands
1st Cycle 2nd Cycle
Command Name Numb er of
Cycles Mode Address Data Mode Address Data
Memory read mode 1 + n write X H'00 Read RA Dout
Auto-program mode 129 write X H'40 write WA Din
Au to - e ra se mod e 2 wri te X H'2 0 w ri te X H'2 0
Status read mode 2 write X H'71 write X H'71
Notes: 1. In auto-pr ogram mode. 129 cycles are required for command wr iting by a simultaneous
128-byte write.
2. I n memory read mode, the num ber of cycles depends on the number of address wr ite
cycles (n ).
Rev. 1.0, 02/00, page 159 of 1141
7.8.4 Memory Read Mode
• After the end of an auto-progra m, auto-era se, or status read operation, the c ommand wait state
is entered. To read memory contents, a transition must be made to memory read mode by
mean s of a comma n d write befo re the r ead is executed.
• Command writes ca n be performed in memory rea d mode, just as in the c ommand wait state.
• Once memory read mode has be en enter ed, conse cut ive reads can be perform ed.
• After power-on, memory read mode i s ent e red.
Tab le 7.1 1 AC Ch aracte ris t ics in Memory Re a d Mo d e (1) − Preliminary −
Conditions: VCC = 5. 0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit Notes
Comma n d write cyc le tnxtc 20 µs
&(
hold time tceh 0ns
&(
setup t ime tces 0ns
Data hold time tdh 50 ns
Da ta se tup ti me tds 50 ns
Write pulse width t wep 70 ns
:(
rise time tr30 ns
:(
fall time tf30 ns
CE
A18 to A0
IO7 to IO0 DATA
OE
WE
Command write
t
wep
t
ceh
t
dh
t
ds
t
f
t
r
t
nxtc
Note: Data is latched on the rising edge of WE.
t
ces
Memory read mode
ADDRESS STABLE
DATA
Figure 7.16 Memory Read Mode Timing Waveforms after Command Write
Rev. 1.0, 02/00, page 160 of 1141
Table 7.12 AC Charac teristics when Entering Another Mode from Memor y Read M ode
− Preliminary −
Conditions: VCC = 5. 0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit Notes
Comma n d write cyc le tnxtc 20 µs
&(
hold time tceh 0ns
&(
setup t ime tces 0ns
Data hold time tdh 50 ns
Da ta se tup ti me tds 50 ns
Write pulse width t wep 70 ns
:(
rise time tr30 ns
:(
fall time tf30 ns
CE
A18 to A0
IO7 to IO0 H'XX
OE
WE
XX mode command write
t
wep
t
ceh
t
dh
t
ds
t
nxtc
Note: Do not enable WE and OE at the same time.
t
ces
ADDRESS STABLE
DATA
t
f
t
r
Figure 7.17 Timing Waveforms when Entering Another Mode from Me mory Read Mode
Rev. 1.0, 02/00, page 161 of 1141
Table 7.13 AC Charac teristics i n Memory Read Mode (2) − Preliminary −
Conditions: VCC = 5. 0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit Notes
Access time tacc 20 µs
&(
output delay tim e t ce 150 ns
2(
output delay tim e toe 150 ns
Output disable delay tim e t df 100 ns
Data output hold time toh 5ns
CE
A18 to A0
IO7 to IO0
VIL
VIL
VIH
OE
WE t
acc
t
oh
t
oh
t
acc
ADDRESS STABLE ADDRESS STABLE
DATA
DATA
Figure 7.18 Timing Wav eforms for
&(
&(
/
2
2(
(
Enable State Read
CE
A18 to A0
IO7 to IO0
VIH
OE
WE
t
ce
t
acc
t
oe
t
oh
t
oh
t
df
t
ce
t
acc
t
oe
ADDRESS STABLE ADDRESS STABLE
DATA DATA
t
df
Figure 7.19 Timing Wav eforms for
&(
&(
/
2
2(
(
Clocked Rea d
Rev. 1.0, 02/00, page 162 of 1141
7.8.5 Auto-Program Mode
AC Characteristics
Table 7.14 AC Characteristics in Auto-Program − Preliminary −
Conditions: VCC = 5. 0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit Notes
Comma n d write cyc le tnxtc 20 µs
&(
hold time tceh 0ns
&(
setup t ime tces 0ns
Data hold time tdh 50 ns
Da ta se tup ti me tds 50 ns
Write pulse width t wep 70 ns
Status polling start t ime twsts 1ms
Status polling access time tspa 150 ns
Address set up time t as 0ns
Address hold time tah 60 ns
Memory write time twrite 1 3000 ms
:(
rise time tr30 ns
:(
fall time tf30 ns
Write setup time tpns 100 ns
Write end setup time t pnh 100 ns
Rev. 1.0, 02/00, page 163 of 1141
CE
FWE
A18 to A0
IO7
OE
WE
t
nxtc
t
wsts
t
spa
t
nxtc
t
ces
t
ds
t
dh
t
wep
t
as
t
pnh
t
pns
t
ah
t
ceh
ADDRESS STABLE
Data transfer
1 byte to 128 bytes
IO6
Programming wait
DATA
IO5 to IO0 H'40 DATA
H'00
t
f
t
r
t
write
(1 to 3,000 ms)
Programming operation
end identification signal
Programming normal end
identification signal
Figure 7.20 Auto-Program Mode Timi ng Waveforms
Notes on Use of Auto-Program Mode
• In auto-program mode, 128 bytes are programmed si m ultaneously. This should be carried out
by executing 128 consecutive byte transfers.
• A 128-byt e data transfe r is necessary even when programming fe wer than 128 byt e s. In this
case, H'FF data must be written to t he extra addre sses.
• The lower 8 bits of the transfer address must be H'00 or H'80. If a value other than an effective
address is input, proc e ssing will switch to a memory write operat ion but a write e rror wi ll be
flagged.
• Memory address transfer is performed in the second c ycle (figure 7.20). Do not perform
trans fer aft er th e second cy c le.
• Do not perform a command write duri ng a programming opera tion.
• Perform one auto-programming operation for a 128-byte block for each address.
Characteristics a re not gua ranteed for two or more programming operations.
• Confirm normal end of auto-programming by che cking IO6. Alternatively, status rea d mode
can also be used for this purpose (IO7 status poll ing uses t he aut o-program ope ration e nd
identification p in ).
• The sta tus polling IO6 a nd IO7 pin information is reta i ned unti l the ne xt command write.
Until the next command write is performed, reading is possible by enabling
&(
and
2(
.
Rev. 1.0, 02/00, page 164 of 1141
7.8.6 Auto-Erase Mode
AC Characteristics
Table 7.15 AC Characteristics in Auto-Erase Mode − Preliminary −
Conditions: VCC = 5. 0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit Notes
Comma n d write cyc le tnxtc 20 µs
&(
hold time tceh 0ns
&(
setup t ime tces 0ns
Data hold time tdh 50 ns
Da ta se tup ti me tds 50 ns
Write pulse width t wep 70 ns
Status polling start t ime tests 1ms
Status polling access time tspa 150 ns
Memory erase time terase 100 40000 ms
:(
rise time tr30 ns
:(
fall time tf30 ns
Erase setup tim e tens 100 ns
Erase end setup time tenh 100 ns
CE
FWE
A18 to A0
IO5 to IO0
IO6
IO7
OE
WE t
erase
(100 to 40000ms)
t
ests
t
spa
t
nxtc
t
nxtc
t
ces
t
ceh
t
dh
CL
in
DL
in
t
ds
t
wep
t
ens
H'00
H'20 H'20
t
enh
Erase end
identification signal
Erase normal end
identification signal
t
f
t
r
Figure 7.21 Auto-Erase Mode Ti ming Wave forms
Rev. 1.0, 02/00, page 165 of 1141
Notes on Use of Er ase-Program Mode
• Auto-erase mode supports only entire memory erasing.
• Do not perform a command write duri ng auto-erasing.
• Confirm normal end of auto-era sing by chec ki ng IO6. Alt e rnatively, st atus read mode can also
be used for this purpose (IO7 status polling use s the auto-erase operat i on end identification
pin).
• The sta tus polling IO6 a nd IO7 pin information is reta i ned unti l the ne xt command write.
Until the next command write is performed, reading is possible by enabling
&(
and
2(
.
7.8.7 Status Read Mode
Status read mode is used to identify what type of abnormal end has occurred. Use this mode when
an abnormal end occ urs in auto-program mode or auto-e rase mode.
The return code is retained unt il a command write for other tha n status rea d mode is performed.
Table 7.16 AC Charac teristics i n Status Read Mode − Preliminary −
Conditions: VCC = 5. 0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit Notes
Comma n d write cyc le tnxtc 20 µs
&(
hold time tceh 0ns
&(
setup t ime tces 0ns
Data hold time tdh 50 ns
Da ta se tup ti me tds 50 ns
Write pulse width t wep 70 ns
2(
output delay tim e toe 150 ns
Disable delay tim e tdf 100 ns
&(
output delay tim e t ce 150 ns
:(
rise time tr30 ns
:(
fall time tf30 ns
Rev. 1.0, 02/00, page 166 of 1141
CE
A18 to A0
IO7 to IO0
OE
WE t
ces
t
nxtc
t
nxtc
t
df
Note: IO2 and IO3 are undefined.
t
ces
t
dh
t
ceh
t
ds
t
wep
t
wep
DATA
t
dh
t
ceh
t
ds
t
oe
t
ce
t
nxtc
H'71 H'71
t
f
t
r
t
f
t
r
Figure 7.22 Status Read Mode Timing Waveforms
Table 7.17 Status Read Mode Re turn Commands
Pin Name IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
Attribute Normal end
identification Command
error Programming
error Erase error Programming
or erase count
exceeded
Effective
address
error
Initial value 0 0 0 0 0 0 0 0
Indications Normal
end: 0
Abnormal
end: 1
Command
error: 1
Otherwise: 0
Programming
error: 1
Otherwise: 0
Erase error: 1
Otherwise: 0
Count
exc eede d: 1
Otherwise: 0
Effective
address
error: 1
Otherwise: 0
Note: IO2 and IO3 are undef ined.
Rev. 1.0, 02/00, page 167 of 1141
7.8.8 Status Polling
The IO7 status polling fla g indicates t he operating sta t us in a uto-program or aut o-erase m ode.
The IO6 status polling fla g indicates a normal or abnormal end in auto-program or auto-erase
mode.
Table 7.18 Status Polling Output Truth Table
Pin Names Internal Operation
in Progress Abnorm al End Normal End
IO7 0 1 0 1
IO6 0 0 1 1
IO0 to IO5 0 0 0 0
Rev. 1.0, 02/00, page 168 of 1141
7.8.9 Writer M ode Transition Time
Commands cannot be accepted during the oscillation sta bilization peri od or the writer mode setup
period. After the writer mode setup time, a transition is made to memory read mode.
Table 7.19 Command Wai t State Transition Time Specifications
Item Symbol Min Max Unit Notes
Standby release
(oscillation stabilization time) tosc1 10 ms
Writer mode setup time tbmv 10 ms
VCC hold time tdwn 0ms
VCC
RES
FWE
Memory read
mode
Command wait
state
Command
wait state
Normal/abnormal
end identifica-
tion
Auto-program mode
Auto-erase mode
tosc1 tbmv tdwn
Note: Except in auto-program mode and auto-erase mode, drive the FWE input pin low.
Don't care
Don't care
Figure 7.23 Oscillation Stabilization Time,
Boot Program Transfer Time, and Power Supply Fall Sequence
7.8.10 Notes on Memory Programming
• When programming addre sses which ha ve previ ously be en programmed, carry out auto-
erasing be fore aut o-programming.
• When perfor mi ng progr am ming using writ er mod e on a chip that has been progr am me d/erased
in an on-board program mi ng mod e, auto- er asing is recommended befor e carrying out auto-
programming.
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi.
For other c hips for which the erasure history i s unknown, it i s recomm e nded that auto-
erasing be executed to check and supplement the initialization (erase) level.
2. Auto-programming should be performed once only on the same address block.
Rev. 1.0, 02/00, page 169 of 1141
7.9 Notes wh en Con vert i n g the F–ZTAT Appl icat i on S oftware t o the
Mask- RO M Versio n s
Please note the following when converting the F-ZTAT application software to the mask-ROM
versions.
The values read from the internal registers for the flash ROM of the mask-ROM version and
F–ZTAT version differ as follows.
Status
Register Bit F–ZTAT Ver si on Mask-RO M Version
FLMCR1 FWE 0: Applica tion software
running
1: Programming
0: Is not read out
1: Application software
running
Note: This difference applies to all the F-ZTAT versions and all the mask-ROM versions that have
different ROM size.
Rev. 1.0, 02/00, page 171 of 1141
Section 8 RAM
8.1 Overview
The H8S/2199, H8S/2198, H8S/2197, and H8S/2196 ha ve 3 kbyte s of on-chip high-spee d static
RAM, and the H8S/2199 F-ZTAT has 8 kbytes. The on-c hip RAM is connec ted to t he CPU by a
16-bit da ta bus, enabling both byte da ta and word data to be accessed in one state. T hi s ma ke s it
possible to perform fa st word data transfer.
8.1.1 Block Diagram
Figure 8. 1 shows a bloc k diagra m of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FFE3B0
H'FFE3B2
H'FFE3B4
H'FFFFAE
H'FFE3B1
H'FFE3B3
H'FFE3B5
H'FFFFAF
Figure 8.1 Block Diagr am of RAM (H 8S/2199)
Rev. 1.0, 02/00, page 173 of 1141
Section 9 Clock Pulse Generator
9.1 Overview
This LSI has a built-in clock pulse generator (CPG) that generates the system clock (φ), the bus
master clock, and in ternal clocks.
The clock pulse generator consists of a system clock oscillator, a duty adjustment circuit, clock
selection circuit, medium-speed clock divider, subclock oscillator, and subclock division circuit.
9.1.1 Block Diagram
Figure 9. 1 shows a bloc k diagra m of the clock pulse gene rator.
System
clock
oscillator
Duty
adjustment
circuit Clock
selection
circuit
Medium-
speed clock
divider
Subclock
oscillator Subclock
division
circuit
OSC1
OSC2
X1
X2
φ/16, φ/32, φ/64
φw/2, φw/4, φw/8
φ SUB
φ or φ SUB
Timer A
count clock
Internal clock
To supporting modules
Bus master clock
To CPU
φSUB (φw/2, φw/4, φw/8)
Figure 9.1 Block Diagram of Clock Pulse Generator
9.1.2 Register Configur ati on
The clock pulse generator is controlled by SBYCR and LPWRCR. T able 9.1 shows the regi ster
configuration.
Table 9.1 CPG Registers
Name Abbreviation R/W Initial Value Address*
Standby control register SBYCR R/ W H'00 H'FFEA
Low-power contr ol register LPWRCR R/ W H'00 H'FFEB
Note: *Lower 16 bits of the address .
Rev. 1.0, 02/00, page 174 of 1141
9.2 Register Descri pt i on s
9. 2.1 Standby Cont r ol Register (SBYCR)
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
—
0
—
0
SCK0
0
R/W
2
—
0
—
1
SCK1
0
R/W
Bit
Initial value
R/W
:
:
:
SBYCR is an 8-bit readable/writable re gister that pe rforms power-down m ode cont rol.
Only bits 0 and 1 are descri bed here . For a description of the other bi t s, see section 4. 2.1, Standby
Control Re gister (SBYCR). SBYCR is initialized to H'00 by a reset.
Bits 1 and 0System Clock Select 1 and 0 (SCK1, SCK0 ): These bits select the bus master
clock for high-spee d mod e and medium-speed mode .
Bit 1 Bit 0
SCK1 SCK0 Description
0 Bus master is in high-speed mode (Init ial value)0
1 M edium-speed clock is φ/16
0 M edium-speed clock is φ/321
1 M edium-speed clock is φ/64
Rev. 1.0, 02/00, page 175 of 1141
9. 2.2 Low-Po wer Contr ol Register (LPWRCR)
7
DTON
0
R/W
6
LSON
0
R/W
5
NESEL
0
R/W
4
—
0
—
3
—
0
—
0
SA0
0
R/W
2
—
0
—
1
SA1
0
R/W
Bit
Initial value
R/W
:
:
:
LPWRCR is an 8-bit readable/writ ab le regist er that perfo rms power-down mode contro l.
Only bit 1 and 0 i s descri bed here . For a description of the other bits, see section 4. 2.2, Low-
Power Cont rol Regi ster (LPWRCR).
LPWRCR is initialized to H'00 by a reset.
Bits 1 and 0Subactive Mode Clock Select (SA1, SA0): Selects CPU clock for subactive m ode.
In subactive mod e, wri tes are disabled.
Bit 1 Bit 0
SA1 SA0 Description
0 CPU operating clock is φw/8 (I n itial value )0
1 CPU operating clock is φw/4
1*CPU operat ing clock is φw/2
Note: *Don't care
Rev. 1.0, 02/00, page 176 of 1141
9.3 Oscillator
Clock pul ses can be supplied by connecting a crystal resonator, or by input of an external clock.
9.3.1 Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator c an be c onnected as shown in the example in fi gure
9.2. An AT-cut parallel-resonanc e crystal should be used.
OSC1
OSC2 C
L2
C
L1
C
L1 =
C
L2
= 10 to 22pF
Figure 9.2 Connection of Crystal Resonator (Example )
Crystal Re sonator: Figure 9.3 shows the equivalent circuit of the crystal resonator. Use a crystal
resonator that has the characteristics shown in table 9. 2 and the same frequency as the system
clock (φ).
OSC1
C
L
AT-cut parallel-resonance type
OSC2
C
0
LR
s
Fi g ure 9. 3 Cr yst a l Reso na tor Equiv ale nt Circ uit
Table 9.2 Crystal Resonator Parameters
Frequency (MHz) 8 10
RSma x ( Ω)8060
COmax (pF) 7 7
Rev. 1.0, 02/00, page 177 of 1141
Note on Board Design: When a crystal resonator is connected, the following points should be
noted.
Other signa l lines should be routed away from the oscillator ci rcuit t o prevent induct i on from
interfering with corre ct oscillation. See figure 9.4.
Whe n designin g th e b oar d, place the cr ystal reso nator an d its load cap acitors as close as poss ible
to the OSC1 and OSC2 pins.
C
L2
Signal A Signal B
C
L1
This chip
OSC1
OSC2
Avoid
Figure 9.4 Example of Incorrect Board Design
Rev. 1.0, 02/00, page 178 of 1141
9.3.2 External Clock Input
Circuit Configuration: An external clock signal can be input as shown in the exa mples in figure
9.5. If the OSC2 pin is left open, make sure that stray capacitance is no more than 10 pF.
In example (b), make sure that the external clock is held high in standby mode, subactive mode,
sub s leep mode, and w atch mod e.
OSC1
OSC2
External clock input
Open
(a) OSC2 pin left open
OSC1
OSC2
External clock input
(b) Inverted-phase clock input at OSC2 pin
Fig ure 9.5 External Clock Input (Examples)
Rev. 1.0, 02/00, page 179 of 1141
External Clock: The external c l ock signal should have the same frequency as t he syst em clock
(φ).
Table 9.3 and figure 9.6 show the input conditions for the external clock.
Table 9.3 External Clock Input Conditions
VCC = 4.0 t o 5.5 V
Item Symbol Min Max Unit Test Conditions
External clock input low
pulse width tEXL 40 ns
External clock input high
pulse width tEXH 40 ns
External clock rise time tEXr 10 ns
External clock fall time tEXf 10 ns
Figure 9.6
t
EXH
t
EXL
t
EXr
t
EXf
OSC1
Fi g ure 9. 6 Ex ter na l Clock Input Timing
Table 9.4 shows the external clock output settling delay time, and figure 9.7 shows the external
clock output settling de lay ti ming. The oscillator and duty adjustm ent ci rc uit have a function for
adjusting the waveform of the external clock input at the OSC1 pin. When the prescribed clock
signal is input at the OSC1 pin, internal clock signal output is fixed after the elapse of the external
clock output settling delay time (tDEXT). As the clock signal output is not fixed during the tDEXT
period, the reset signal should be driven low to maintain the reset state.
Rev. 1.0, 02/00, page 180 of 1141
Table 9.4 External Clock Output Settling Delay Time
Conditions: VCC = 4.0 V to 5.5 V , AVCC = 4.0 V t o 5.5 V, VSS = AVSS = 0 V
Item Symbol Min Max Unit Notes
External clock output settling
delay time tDEXT*500 µs Figure 9.7
Note: *tDEXT includes 20 tCYC of
5(6
pulse width (tRESW).
t
DEXT
*
RES
(Internal)
OSC1
V
CC
4.0 V
φ
Note: * t
DEXT
includes 20 t
cyc
of RES pulse width (t
RESW
).
Figure 9.7 External Clock Output Settling Delay Timing
Rev. 1.0, 02/00, page 181 of 1141
9.4 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (φ).
9.5 Medium - Speed Clock Divider
The medium-speed di vi der divi des the system clock to generate φ/16, φ/32, and φ/ 64 clocks.
9.6 Bus Master Clock Select i on Circu it
The bus master clock selection circuit selects the system clock (φ) or one of the medium-spee d
clocks (φ/16, φ/ 32 or φ/64) to be supplied to t he bus m a ster (CPU), according to the set tings of bit s
SCK2 t o SCK0 in SBYCR.
Rev. 1.0, 02/00, page 182 of 1141
9.7 Subclock Oscillator Circuit
9.7.1 Connecting 32.768 kHz Crystal Resonator
When using a subclock, c onnect a 32. 768 kHz crystal resonat or to X1 and X2 pins as shown in
figure 9.8.
For precautions on connecting, see Note on Board Design, in se ction 9. 3.1 Conne cting a Crystal
Resonator.
X1
X2 C
2
C
1
C
1
= C
2
= 15 pF (Typ)
Figure 9.8 Connecting a 32.768 kHz Crystal Resonator (Example)
Figure 9. 9 shows a crystal resonator equivalent circ uit.
X1
C
S
C
0
= 1.5 pF (Typ)
R
S
= 14 kΩ (Typ)
f
W
= 32.768 kHz
Type: MX38T (Nihon Denpa Kogyo Co., Ltd.)
Note: Values shown are the reference values.
X2
C
0
L
s
R
s
Figure 9.9 32.768 kHz Crystal Resonator Equi valent Circuit
Rev. 1.0, 02/00, page 183 of 1141
9. 7.2 Whe n Subcl ock is not Nee de d
Connect X1 pin to VCL, and X2 pin should remain open as shown in figure 9. 10.
X1
X2
V
CL
Open
Fi g ure 9.10 Ter m i nal Whe n Subcl ock i s not Nee ded
9.8 Subclock Waveform Shaping Circuit
To eliminate noise in the subclock input from the X1 pin, this circuit samples the clock using a
clock obtained by div iding the φ clock. The sampling frequency is set with the NESEL bit in
LPWRCR. For details, see section 4. 2.2, Low-Power Control Re gister (L PWRCR). T he clock is
not sampled in subactive mode, subsleep mode, or watch mode.
9.9 Notes on the Resonator
Resonator characteristics are closely rela ted to the user board de sign. Perform appropria te
assessment of resonator connection, mask version and F-ZTAT TM, by referring to the connection
example given in this section. The resonator circuit rate differs depending on the free capacity of
the resonator a nd the e xecution circuit, so consult with the resonator manufac turer before
determination. Make sure the voltage applied to the resona tor pin does not exceed the maximum
rated voltage.
Rev. 1.0, 02/00, page 185 of 1141
Section 10 I/O Port
10.1 Overview
10.1.1 Port Functi ons
This LSI ha s seven 8-bit I/O ports (inc l uding one CMOS high-current port), and one 8-bit input
port. Table 10.1 shows the funct ions of eac h port . Ea c h I/O part a port control registe r (PCR) t hat
controls an input and out put and a port da ta regist e r (PDR) for stori ng output data. The input and
output c a n be controlled in a unit of bit. The pin whose peripheral function i s used bot h as a n
alternative function can set the pin function in a unit of bit by a port mode register (PMR).
10. 1. 2 Por t Input
• Reading a Port
When a gene ral port of PCR = 0 (input) i s read, the pi n level is rea d.
When a gene ral port of PCR = 1 (output) i s read, the value of the correspondi ng PDR bit is
read.
When the pins (excluding AN7 to AN0 a nd RPB7 to RP0 pins) set to the peripheral
function are read, the re sults are a s given in items (1) and (2) according to the PCR value.
• Processing Input Pins
The genera l input port or ge neral I/O port is gated by read signa l s. Unused pins can be left
open if they a re not read. However, if an open pin i s read, a feedthrough current may a pply
during the read pe riod ac cording to an intermediate level. T he read period is about one-state.
Relevant port s: P0, P1, P2, P3, P4, P5, P6, P7, and P8
When an alternative pin is set to an alternative function other than the general I/O, always set
the pin le vel to a high or low leve l. If the pi n is left open, a feedthrough current applies
according t o an intermediate level, which a dversely affects reliabil ity, causes malfunctions,
and in the worst case may damage the pin.
Bec au s e the PM R is no t initialized in lo w p o w er co n s u mption mode, pa y attentio n to th e pin
input level after the mode has been shifted to the low power consumption m ode.
Relevant pins:
,&
,
,54
to
,54
, SC K1, SI1, SDA1 , SCL1 , SDA0, SCL 0, SYNC I , FTIA,
FTIB, FTIC, FTID, RPTRG, TMBI,
$'75*
, EXCTL, C OMP, DPG, E XCAP, a nd E XTTRG
Rev. 1.0, 02/00, page 186 of 1141
Table 10. 1 Port Func tions
Port Description Pins Alternative Functions
Function
Switching
Register
Port 0 P07 to P00 input-
only port s P0 7/AN7 to
P00/AN0 Ana lo g data in put cha nnels 7 to 0 PMR 0
P17/TMOW Prescalar unit fre quency di vision clo ck
output
P16/
,&
Pre scalar unit input capture input
Port 1 P17 to P10 I/O ports
(Built-in MOS pull- up
transistors)
P15/
,54
to
P10/
,54
External interrupt request input
PMR1
P27/SYNCI Fo rmatless serial clock i nput
P26/SCL0 I2C bus in terface clock I/O
P25/SDA0 I2C bus in terfa ce da ta I/O
STCR
ICCR
P24/SCL1 I2C bus in terface clock I/O
P23/SDA1 I2C bus in terfa ce da ta I/O
P22/SCK1 SCI1 clock I/O
P21 /S O1 SC I1 t ra ns m it dat a ou t p ut
Port 2 P27 to P20 I/O ports
(Built-in MOS pull- up
transistors)
P20 /S I 1 SCI1 r ec e iv e dat a input
SMR
SCR
P37/TMO Timer J timer output
P36/BUZZ Timer J buzzer output
P35/PWM3 to
P32/PWM0 8-bit PWM output
P31/SV2 Servo monitor output
Port 3 P37 to P30 I/O ports
(Built-in MOS pull- up
transistors)
P30/SV1
PMR3
P47/RPTRG R ealtime outpu t port trigger input
P46/FTOB Timer X output compare B output
P45/FTOA Timer X output compare A output TOCR
P44/FTID Timer X input capture D input
P43/FTIC Timer X input capture C input
P42/FTIB Timer X input capture B input
P41/FTIA Timer X input capture A input
Port 4 P47 to P40 I/O ports
P40/PWM14 14-bit PWM output PMR4
Realt ime output port
P67/RP7/
TMBI Timer B event output
Realt ime output portP66/RP6/
ADTRG A/D conversion start external trigger
input
Port 6 P63 to P60 I/O ports
P65/RP5 to
P60/RP0 Realt ime output port
PMR6
PMRA
PPG outputP77/PPG7/
RPB to P74/
PPG4/RP8 Re altime output port
Port 7 P77 to P70 I/O ports
P73/PPG3 to
P70/PPG0 PPG output
PMR7
PMRB
Rev. 1.0, 02/00, page 187 of 1141
Port Description Pins Alternative Functions
Function
Switching
Register
P87/DPG DPG signal inpu t
P86/EXTTRG External trigger signal input
Pre-amplifier output resul t signal
input
P85/COMP/B
Color signal output ( B)
Pre-amplifier output select signal
input
P84/H.AMP
SW/G
Color signal output ( G)
Control signal output for
processing col or signals
P83/C.Rotary/
R
Color signal output ( R)
P82/EXCTL Ext ernal CTL signal input
External capstan signal input
P81/EXCAP/
YBO OSD character position out put
Port 8 P87 to P80 I/O ports
P80/YCO OSD character data output
PMR8
PMRC
Note: This LSI does not have port 5.
Rev. 1.0, 02/00, page 188 of 1141
10. 1. 3 MOS Pull- Up Transistors
The MOS p ull -up transi stor s in ports 1 to 3 can be switched on or off by the MOS pull-up selec t
registers 1 to 3 (PUR1 to PUR3) in unit s of bits. Set tings in PUR1 to PUR3 are vali d when the pi n
function is se t to an input by PCR1 to PCR3. If the pi n function i s set to an output, the MOS pull-
up transistor is turned off. Figure 10.1 shows the circuit configur at ion of a pin with a MOS pull-
up transist or.
VCC
PUR
STBY
LPWRM
Legend
PCR
PDR
PUR
PCR
PDR
: Low power consumption mode signal
(The pull-up MOS transistor is turned off by the STBY signal in low power
consumption mode except for sleep mode)
: MOS pull-up select register
: Port control register
: Port data register
Input data
VCC
VSS
Figure 10.1 Ci rcuit Configuration of Pin with MOS P ull-Up Transistor
Rev. 1.0, 02/00, page 189 of 1141
10.2 P ort 0
10.2.1 Overview
Port 0 is an 8-bit input-only port. Table 10.2 shows the port 0 configura t ion.
Port 0 consists of pi ns tha t are used both as standard i nput ports (P07 to P00) and analog input
channels (AN7 to AN0). It is switched by port mode register 0 (PMR0).
Table 10. 2 Port 0 Configuration
Port Function Al t ernative Functi on
P07 (standard input port) AN7 (analog input channel)
P06 (standard input port) AN6 (analog input channel)
P05 (standard input port) AN5 (analog input channel)
P04 (standard input port) AN4 (analog input channel)
P03 (standard input port) AN3 (analog input channel)
P02 (standard input port) AN2 (analog input channel)
P01 (standard input port) AN1 (analog input channel)
Port 0
P00 (standard input port) AN0 (analog input channel)
Rev. 1.0, 02/00, page 190 of 1141
10.2.2 Regi ster Configur ati on
Table 10. 3 shows the port 0 regi ster confi guration.
Tabl e 10. 3 Po r t 0 Register Co nfig ur a tion
Name Abbrev. R/W Si z e Initi al Value Address*
Port mode register 0 PMR0 R/W Byt e H'00 H'FFCD
Port dat a register 0 PDR0 R Byte H'FFC0
Note: *Lower 16 bits of the addr ess .
(1) Port Mode Register 0 (PMR0)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PMR04 PMR03 PMR02 PMR01 PMR00PMR07 PMR06 PMR05
Bit :
Initial value :
R/W :
Port mode register 0 (PMR0) control s switching of each pin function of port 0. The switc hing is
specified in a un it of b it.
PMR0 is an 8-bit read/write enable register. When reset, PMR0 is initialized to H'00.
Bits 7 to 0P07/AN7 to P00/AN0 Pin Switching (PM R07 to PMR00): PMR07 to PMR00 sets
whether t he P0n/ANn pin is used as a P0n input pi n or an ANn pin for t he analog input channel of
an A/D converter.
Bit n
PMR0n Description
0 The P0n/ANn pin functions as a P0n input pin (Init ial value)
1 The P0n/ANn pin functions as an ANn input pin
(n = 7 to 0)
Rev. 1.0, 02/00, page 191 of 1141
(2) P ort Data Register 0 (PDR0)
01
R
2
R
34
RR
57 PDR04 PDR03 PDR02 PDR01 PDR00
R
PDR07
RRR
PDR06 PDR05
6
————————
Initial value :
R/W :
Bit
@:
Port data register 0 (PDR0) reads the port states. When t he corre sponding bit of PMR0 is 0
(general i nput port), the pin state is re ad if PDR0 is read. When the corresponding bit of PMR0 is
1 (analog input cha nnel), 1 is read if PDR0 i s read.
PDR0 is an 8-bit read-onl y registe r. Whe n PDR0 is reset, its values become unde fined.
10.2.3 Pin Functions
This section de scribes the pin functions of port 0 a nd their selec tion me t hods.
P07/AN7 to P00/AN0: P07/AN7 to P00/AN0 are switched according to the PMR0n bit of PMR0
as shown below.
PMR0n Pin Function
0 P0n input pin
1 ANn input pin
(n = 7 to 0)
10.2.4 Pin States
Table 10.4 shows the pin 0 states in each operation mode.
Table 10. 4 Port 0 Pin States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
P07/AN7 to
P00/AN0 High-
impedance High-
impedance High-
impedance High-
impedance High-
impedance High-
impedance High-
impedance
Rev. 1.0, 02/00, page 192 of 1141
10.3 P ort 1
10.3.1 Overview
Port 1 is an 8-bit I/O port. Table 10.5 shows the port 1 configuration.
Port 1 consists of pi ns tha t are used both as standard I/ O ports (P17 to P10) a nd frequency division
clock output (TMOW), input capture input (
,&
), or external interrupt reque st inputs (
,54
to
,54
). It is swit ched by port mode register 1 (PMR1) and port control regi ster 1 (PCR1).
Port 1 ca n select the functions of MOS pull -up transistors.
Table 10. 5 Port 1 Configuration
Port Function Al t ernative Functi on
P17 (standard I /O port) TMOW (frequency division clock out put)
P16 (standard I /O port)
,&
(input capture input)
P15 (standard I /O port)
,54
(external inter rupt request input)
P14 (standard I /O port)
,54
(external inter rupt request input)
P13 (standard I /O port)
,54
(external inter rupt request input)
P12 (standard I /O port)
,54
(external inter rupt request input)
P11 (standard I /O port)
,54
(external inter rupt request input)
Port 1
P10 (standard I /O port)
,54
(external inter rupt request input)
10.3.2 Register Configurati on
Table 10. 6 shows the port 1 regi ster confi guration.
Tabl e 10. 6 Po r t 1 Register Co nfig ur a tion
Name Abbrev. R/W Si z e Initi al Value Address*
Port mode register 1 PMR1 R/W Byt e H'00 H'FFCE
Port cont rol register 1 PCR1 W Byte H'00 H'FFD1
Port data register 1 PDR1 R/W Byte H'00 H'FFC1
MOS pu ll- up select
register 1 PUR1 R/W Byte H'00 H'FFE1
Note: *Lower 16 bits of the address .
Rev. 1.0, 02/00, page 193 of 1141
Port Mode Register 1 (PMR1)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PMR14 PMR13 PMR12 PMR11 PMR10PMR17 PMR16 PMR15
Bit :
Initial value :
R/W :
Port mode register 1 (PMR1) control s switching of each pin function of port 1. The switc hing is
specified in a un it of b it.
PMR1 is an 8-bit read/write enable register. When reset, PMR1 is initialized to H'00.
Note the following items when the pin functions are switched by PMR1.
• If port 1 is set to an
,&
input pi n and
,54
to
,54
by PMR1, the pin level needs be set to the
high or low level regardless of the active mode and low power consumption mode. T he pin
level must not be set to an intermediate level.
• When t he pin functions of P16/
,&
and P1 5/
,34
to P10/
,54
are switched by PMR1, they are
incorrectly recognized as edge detection according to the state of a pin signal and a detection
signal m a y be gene rated. To prevent this, perform the ope ration in the following proce dure.
Before swit ching the pin functions, inhibit an interrupt ena ble flag from being i nterrupted.
After having switched the pin functions , clear the relevan t interrup t requ est flag to 0 by a
single instruction.
Program Example:
:
MOV.B ROL, @I ENR ⋅⋅⋅⋅⋅⋅ Inter rup t di sab led
MOV.B R1L, @P MR1 ⋅⋅⋅⋅⋅⋅ Pi n funct i on change
NOP ⋅⋅⋅⋅⋅⋅ Op tiona l instru ction
BCLR m @IRQR ⋅⋅⋅⋅⋅⋅ Applica ble in te rrup t cle ar
MOV.B R1L, @I ENR ⋅⋅⋅⋅⋅⋅ Interrupt enabled
:
Rev. 1.0, 02/00, page 194 of 1141
Bit 7P17/TMO W Pin Switching (PMR17): PMR17 sets whether the P17/TMOW pin is used
as a P17 I/O pin or a TMOW pin for the frequency division c lock output.
Bit 7
PMR17 Description
0 The P17/TMOW pin functions as a P17 I/O pin (Initial value)
1 The P17/TMOW pin functions as a TMOW output pin
Bit 6P16/
,
,&
&
Pin Switching (P MR16): PMR16 sets whether the P16/
,&
pin as a P16 I/O pin or
an
,&
pin for the i nput capture i nput of the prescalar uni t. The
,&
pin has a built-in noise cancel
circuit. See section 21, Prescalar Unit.
Bit 6
PMR16 Description
0 The P16/
,&
pin functions as a P16 I/O pin (Init ial value)
1 The P16/
,&
pin functions as an
,&
input pin
Bits 5 to 0P15/
,54
,54
to P10/
,
,54
54
Pin Switching (PMR15 to PM R10): PMR15 to PMR10 set
whether the P1n/
,54Q
pin is used as a P1n I/O pin or an
,54Q
pin for the e xternal interrupt
request input.
Bit n
PMR1n Description
0 The P1n/
,54Q
pin functions as a P1n I/O pin (Init ial value)
1 The P1n/
,54Q
pin functions as an
,54Q
input pin
(n = 5 to 0)
Port Control Regist er 1 (PCR1)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5
0
7
0
W WWW
6PCR14 PCR13 PCR12 PCR11 PCR10PCR17 PCR16 PCR15
Bit :
Initial value :
R/W :
Port control register 1 (PCR1) c ontrols the I/Os of pins P17 t o P10 of port 1 in a unit of bit.
When PCR1 is set to 1, the corre sponding P17 to P10 pins become out put pins, and when i t is se t
to 0, they become input pins. When t he relevant pin i s set t o a gene ral I/O by PMR1, settings of
PCR1 a nd PDR1 become valid.
PCR1 is a n 8-bit write-only registe r. When PCR1 is read, 1 i s read. When reset, PCR1 is
initialized to H'00.
Rev. 1.0, 02/00, page 195 of 1141
Bits 7 to 0P17 to P10 Pin Switching (PCR17 toPCR10)
Bit n
PCR1n Description
0 The P1n pin functions as an input pin (Init ial value)
1 The P1n pin functions as an output pin
(n = 7 to 0)
Port Data Register 1 (PDR1)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PDR14 PDR13 PDR12 PDR11 PDR10PDR17 PDR16 PDR15
Bit :
Initial value :
R/W :
Port data register 1 (PDR1) stores the data for the pins P17 to P10 of port 1. When PCR1 is 1
(output), the PDR1 va lues are directly read if port 1 is read. Accordingly, the pi n states a re not
affected. When PCR1 is 0 (input), the pin states are read if port 1 is read.
PDR1 is an 8-bit read/ write enable register. When reset, PDR1 is initialized to H'00.
MO S Pull- Up Selec t Regist er 1 (PUR1)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PUR14 PUR13 PUR12 PUR11 PUR10PUR17 PUR16 PUR15
Bit :
Initial value :
R/W :
MOS pull-up selector register 1 (PUR1) cont rols the on and off of the MOS pull-up transi st or of
port 1. Onl y the pi n whose corresponding bit of PCR1 was set t o 0 (input) becom es valid. W hen
the corresponding bit of PCR1 is set to 1 (output), the corre sponding bi t of PUR1 becomes invalid
and the MOS pull-up transistor i s turned off.
PUR1 is an 8-bit read/ write enable register. When reset, PUR1 is initialized to H'00.
Bits 7 to 0P17 to P10 MOS Pull-Up Control (PCR17 to PCR10)
Bit n
PUR1n Description
0 The P1n pin has no MOS pull-up transistor (Init ial value)
1 The P1n pin has a MOS pull-up pin
(n = 7 to 0)
Rev. 1.0, 02/00, page 196 of 1141
10.3.3 Pin Functions
This section describes the port 1 pin functions and their selection methods.
P17/TMOW: P17/TMOW is switched as shown bel ow ac cording t o the PMR17 bit in PMR1 a nd
the PCR17 bit in PCR1.
PMR17 PCR17 Pin Function
0 P17 input pin
0
1 P17 output pin
1*TMOW output pin
Note: *Don’t care
P16/
,
,&
&
: P16/
,&
is switched as shown below according to the PMR16 bit in PMR1, the NC on/off
bit in prescalar unit control/status register (PCSR), and the PCR16 bi t in PCR1.
PMR16 PCR16 NC on/off Pin Function
0 P16 input pin
0
1
P16 output pin
0 Noise cancel invalid1*
1
,&
input pin
Noise c a ncel v a lid
Not e : *Don’t care
P15/
,54
,54
to P10/
,54
,54
: P15/
,54
to P10/
,54
are switched as shown below according to the
PMR1n bit in PMR1 and the PCR1n bit in PCR1.
PMR1n PCR1n Pin Function
0 P1n input pin
0
1 P1n output pin
1*
,54Q
input pin
(n = 5 to 0)
Notes: 1. * Don’t care.
2. The
,54
to
,54
input pins can select the leading or f alling edge as an edge sense
(the
,54
pin can select both edges). See section 6.2.4, IRQ Edge Select Register
(IEGR).
3.
,54
or
,54
can be used as a timer J event input and
,54
can be used as a t imer R
input capture input. For details, see section 13, Timer J or sect ion 15, Timer R.
Rev. 1.0, 02/00, page 197 of 1141
10.3.4 P i n States
Table 10. 7 shows the port 1 pin states i n each operation mode.
Table 10. 7 Port 1 Pin States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
P17/TMOW
P16/
,&
P15/
,54
to
P10/
,54
High-
impedance Operation Holding High-
impedance High-
impedance Operation Holding
Note: If the
,&
input pin and
,54
to
,54
input pins are set, the pin level need be set to the high
or low level regardless of t he active mode and low power consumption m ode. Note that the
pin level must not reach an intermediate level.
Rev. 1.0, 02/00, page 198 of 1141
10.4 P ort 2
10.4.1 Overview
Port 2 is an 8-bit I/O port. Table 10.8 shows the port 2 configuration.
Port 2 consists of pi ns tha t are used both as standard I/ O ports (P27 to P20) a nd SCI clock I/O
(SCK1), receive data input (SI1), send data out put (SO1), I2C bus interface clock I/ O (SCL0,
SCL 1) , o r data I/O (SDA0, SDA1 ). It is switched by seria l mode reg i ste r (SMR), se rial con tro l
register (SCR), and port control registe r 2 (PCR2).
Port 2 can sele ct the MOS pull- up fu nct ion .
Table 10. 8 Port 2 Configuration
Port Function Al t ernative Functi on
P27 (standard I /O port) SYNCI (Formatless serial clock input)
P26 (standard I /O port) SCL0 (I2C bus int erface clock I/O)
P25 (standard I /O port) SDA0 (I2C bus interface data I/O)
P24 (standard I /O port) SCL1 (I2C bus int erface clock I/O)
P23 (standard I /O port) SDA1 (I2C bus interface data I/O)
P22 (standard I /O port) SCK1 (SCI1 clock I/O)
P21 (standard I /O port) SO1 (SCI1 transmit data out put)
Port 2
P20 (standard I /O port) SI1 (SCI1 r eceive data input)
10.4.2 Register Configurati on
Table 10. 9 shows the port 2 regi ster confi guration.
Tabl e 10. 9 Po r t 2 Register Co nfig ur a tion
Name Abbrev. R/W Si z e Initi al Value Address*
Port cont rol register 2 PCR2 W Byte H'00 H'FFD2
Port data register 2 PDR2 R/W Byte H'00 H'FFC2
MOS pu ll- up select
register 2 PUR2 R/W Byte H'00 H'FFE2
Note: *Lower 16 bits of the address .
Rev. 1.0, 02/00, page 199 of 1141
Port Control Regist er 2 (PCR2)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5
0
7
0
W WWW
6PCR24 PCR23 PCR22 PCR21 PCR20PCR27 PCR26 PCR25
Bit :
Initial value :
R/W :
Port control register 2 (PCR2) c ontrols the I/Os of pins P27 t o P20 of port 2 in a unit of bit.
When PCR2 is set to 1, the corre sponding P27 to P20 pins become out put pins, and when i t is se t
to 0, they become input pins. When the relevant pin is set to a general I/O, settings of PCR2 and
PDR2 are valid.
PCR2 is a n 8-bit write-only registe r. When PCR2 is read, 1 i s read. When reset, PCR2 is
initialized to H'00.
Bits 7 to 0P27 to P20 Pin Switching (PCR27 to PCR20)
Bit n
PCR2n Description
0 The P2n pin functions as an input pin (Init ial value)
1 The P2n pin functions as an output pin
(n = 7 to 0)
Port Data Register 2 (PDR2)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PDR24 PDR23 PDR22 PDR21 PDR20PDR27 PDR26 PDR25
Bit :
Initial value :
R/W :
Port data register 2 (PDR2) stores the data for the pins P27 to P20 of port 2. When PCR2 is 1
(output), the PDR2 va lues are directly read if port 2 is read. Accordingly, the pi n states a re not
affected. When PCR2 is 0 (input), the pin states are read if port 2 is read.
PDR2 is an 8-bit read/write enable register. When reset, PDR2 is initialized to H'00.
Rev. 1.0, 02/00, page 200 of 1141
MO S Pull- Up Selec t Regist er 2 (PUR2)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PUR24 PUR23 PUR22 PUR21 PUR20PUR27 PUR26 PUR25
Bit :
Initial value :
R/W :
MOS pul l-u p select o r re gister 2 (PUR2 ) control s the ON and OFF of the MOS pull-up tran sist or
of port 2. Only the pin whose corresponding bit of PCR2 was set to 0 (input) bec omes val id. If
the corresponding bit of PCR2 is set to 1 (output), the corre sponding bi t of PUR2 becomes invalid
and the MOS pull-up transistor i s turned off.
PUR2 is an 8-bit read/write enable register. When reset, PUR2 is initialized to H'00.
Bits 7 to 0P27 to P20 Pull-Up MOS Control (PUR27 to PUR20)
Bit n
PUR2n Description
0 The P2n pin has no MOS pull-up transistor (Init ial value)
1 The P2n pin has a MOS pull-up transistor
(n = 7 to 0)
Rev. 1.0, 02/00, page 201 of 1141
10.4.3 Pin Functions
This section describes the port 2 pin functions and their selection methods.
P27/SYNCI: P27/SYNCI i s switched as shown bel ow according to the PCR27 bit in PCR2.
PCR Pin Function
0 P27 input pin
1 P27 output pin
Not e : B e ca u se t he SYNC I always fu ncti o n s, the alte r n at i ve pin nee d alwa ys be set to the high or
low level regardless of active mode or low p o w er co n s u mption mo de.
P26/SCL0: P26/SCL0 i s switche d as shown below according t o the PCR26 bit in PCR2 and the
II0CE bit in the I2C Bus c ontrol re gister (ICCR0).
II0CE PCR26 Pin Function
0 P26 input pin
0
1 P26 output pin
1*SCL0 I/O pin
Note: *Don’t care
P25/SDA0: P25/SDA0 is switched as shown belo w acco rding to th e PCR25 bi t in PCR2 and t he
II0CE bit in the I2C Bus c ontrol re gister (ICCR0).
II0CE PCR25 Pin Function
0 P25 input pin
0
1 P25 output pin
1*SDA0 I/O pin
Not e: *Don’t care
P24/SCL1: P24/SCL1 i s switche d as shown below according t o the PCR24 bit in PCR2 and the
II1CE bit in the I2C Bus c ontrol re gister (ICCR1).
II1CE PCR24 Pin Function
0 P24 input pin
01 P24 output pin
1*SCL1 I/O pin
Note: *Don’t care
Rev. 1.0, 02/00, page 202 of 1141
P23/SDA1: P23/SDA1 is switched as shown belo w acco rding to th e PCR23 bi t in PCR2 and t he
II1CE bit in the I2C Bus c ontrol re gister (ICCR1).
II1CE PCR23 Pin Function
0 P23 input pin
0
1 P23 output pin
1*SDA1 I/O pin
Not e: *Don’t care
P22/SCK1: P22/SCK1 is switched as shown below according to the PCR22 bit in PCR2, the C/
$
bit in SMR, and the CKE1 and CKE0 bits in SCR.
CKE1 C/
$
$
CKE0 PCR22 Pi n Function
0 P22 input pin
0
1 P22 output pin
0
1
0
1
SCK1 out put pin
1*
*
*
SCK1 input pin
Note: *Don’t care
P21/SO1: P21/SO1 is switched a s shown below according to the PCR21 bit in PCR2 and the TE
bit in SCR.
TE PCR21 Pin Function
0 P21 input pin
01 P21 output pin
1*SO1 output pin
Note: *Don’t care
P20/SI1: P20/ SI1 i s switched as shown below according to the PCR20 bit in PCR2 and the RE bit
in SCR.
RE PCR20 Pi n Function
0 P20 input pin
01 P20 output pin
1*SI1 input pin
Note: *Don’t care
Rev. 1.0, 02/00, page 203 of 1141
10.4.4 Pin States
Table 10.10 shows the port 2 pin states in each operation mode.
Table 10. 10 Port 2 Pin States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
P27/SYNCI
P26/SCL0
P25/SDA0
P24/SCL1
P23/SDA1
P22/SCK1
P21/SO1
P20/SI1
High-
impedance Operation Holding High-
impedance High-
impedance Operation Holding
Note: Because the SYNCI , SCL0, SDA0, SCL1, and SDA1 always f unction, the alternat ive pin
need always be set to the high or low level r egardless of active mode or low power
consu mption mode.
If the SCK1, and SI 1 input pins are set, the pin level needs be set to the high or low level
regardless of the active m ode and low power consumpt ion mode. Note t hat the pin level
must not reach an intermediate level.
Rev. 1.0, 02/00, page 204 of 1141
10.5 P ort 3
10.5.1 Overview
Port 3 is an 8-bit I/O port. Table 10.11 shows the port 3 c onfiguration.
Port 3 consists of pi ns tha t are used both as standard I/ O ports (P37 to P30) a nd timer J timer
output (TMO), buzzer output (BUZZ), 8-bit PWM out puts (PWM3 t o PWM0), SCI2 strobe out put
(STRB), or chip select input (
&6
). It is switched by port mode re gister 3 (PMR3) and port cont rol
register 3 (PCR3).
Port 3 can sele ct the MOS pull- up fu nct ion .
Table 10. 11 Port 3 Configuration
Port Function Al t ernative Functi on
P37 (standard I /O port) TMO (timer J timer output)
P36 (standard I /O port) BUZZ (timer J buzzer output)
P35 (standard I /O port) PWM3 (8- bit PWM output)
P34 (standard I /O port) PWM2 (8- bit PWM output)
P33 (standard I /O port) PWM1 (8- bit PWM output)
P32 (standard I /O port) PWM0 (8- bit PWM output)
P31 (standard I /O port) SV2 (servo m onitor output)
Port 3
P30 (standard I /O port) SV1 (servo m onitor output)
10.5.2 Register Configurati on
Table 10.12 shows the port 3 register configuration.
Tabl e 10. 12 P ort 3 Register Config ur a tio n
Name Abbrev. R/W Si z e Initi al Value Address*
Port mode register 3 PMR3 R/W Byt e H'00 H'FFD0
Port cont rol register 3 PCR3 W Byte H'00 H'FFD3
Port data register 3 PDR3 R/W Byte H'00 H'FFC3
MOS pu ll- up select
register 3 PUR3 R/W Byte H'00 H'FFE3
Note: *Lower 16 bits of the address .
Rev. 1.0, 02/00, page 205 of 1141
Port Mode Register 3 (PMR3)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PMR34 PMR33 PMR32 PMR31 PMR30PMR37 PMR36 PMR35
Bit :
Initial value :
R/W :
Port mode register 3 (PMR3) control s switching of each pin function of port 3. The switc hing is
specified in a un it of b it.
PMR3 is an 8-bit read/write enable register. When reset, PMR3 is initialized to H' 00.
Bit 7P37/TMO Pin Switchi ng (PMR37): PMR37 sets whether the P37/T MO pin i s used as a
P37 I/O pin or a TMO pin for the timer J output timer.
Bit 7
PMR37 Description
0 The P37/TMO pin funct ions as a P37 I/O pin (Initial value)
1 The P37/TMO pin funct ions as a TMO output pin
Note: If the TMO pin is used for remote cont r ol sending, a careless tim er output pulse may be
output when the rem ote cont r ol mode is set after the out put has been switched t o the TMO
output. Perform the switching and setting in the following order .
1. Set the remote control mode.
2. S et t he TMJ- 1 and 2 co unter da ta of the tim er J.
3. Switch the P37/TMO pin t o the TMO output pin.
4. Set the ST bit to 1.
Bit 6P36/BUZZ Pin Switching (PMR36): PMR36 sets whether t he P36/BUZZ pi n as a P36
I/O pin or an BUZZ pi n for the t imer J buzzer output. For the selection of the BUZZ output, see
13.2.2, T imer J Cont rol Register (TMJC).
Bit 6
PMR36 Description
0 The P36/BUZZ pin functions as a P36 I /O pin (Init ial value)
1 The P36/BUZZ pin functions as a BUZZ output pin
Rev. 1.0, 02/00, page 206 of 1141
Bits 5 to 2P35/PWM3 to P32/PWM0 P in Switc hing (PMR35 to PMR32): PMR35 to PMR32
set whethe r the P3n/PWMm pin is used as a P3n I/O pin or a PWMm pin for the 8-bit PWM
output.
Bit n
PMR3n Description
0 The P3n/PWMm pin functions as a P3n I/O pin (Initial value)
1 The P3n/PWMm pin functions as a PWMm output pin
(n = 5 to 2, m = 3 t o 0)
Bit 1P31/ SV2 Pin Swi tchi ng (PMR3 1): PMR31 sets whether the P31/SV2 pin is used as a P31
I/O pin or an SV2 pin for the se rvo mon ito r outpu t.
Bit 1
PMR31 Description
0 The P31/SV2 pin functions as a P31 I/O pin (Init ial value)
1 The P31/SV2 pin functions as an SV2 out put pin
Bit 0P30/ SV1 Pin Swi tchi ng (PMR3 0)
PMR30 set s whether the P30/SV1 pin is used a s a P30 I/O pin or an SV1 pi n for servo monitor
output.
Bit 0
PMR30 Description
0 The P30/SV1 pin functions as a P30 I/O pin (Init ial value)
1 The P30/SV1 pin functions as an SV1 out put pin
Rev. 1.0, 02/00, page 207 of 1141
Port Control Regist er 3 (PCR3)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5
0
7
0
W WWW
6PCR34 PCR33 PCR32 PCR31 PCR30PCR37 PCR36 PCR35
Bit :
Initial value :
R/W :
Port control register 3 (PCR3) c ontrols the I/Os of pins P37 t o P30 of port 3 in a unit of bit.
When PCR3 is set to 1, the corre sponding P37 to P30 pins become out put pins, and when i t is se t
to 0, they become input pins. When t he relevant pin i s set t o a gene ral I/O by PMR3, settings of
PCR3 a nd PDR3 become valid.
PCR3 is a n 8-bit write-only registe r. When PCR3 is read, 1 i s read. When reset, PCR3 is
initialized to H'00.
Bits 7 to 0Pin 37 to P30 Pin Switc hing (P CR37 to PCR30)
Bit n
PCR3n Description
0 The P3n pin functions as an input pin (Init ial value)
1 The P3n pin functions as an output pin
(n = 7 to 0)
Port Data Register 3 (PDR3)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PDR34 PDR33 PDR32 PDR31 PDR30PDR37 PDR36 PDR35
Bit :
Initial value :
R/W :
Port data register 3 (PDR3) stores the data for the pins P37 to P30 of port 3. When PCR3 is 1
(output), the PDR3 va lues are directly read if port 3 is read. Accordingly, the pi n states a re not
affected. When PCR3 is 0 (input), the pin states are read if port 3 is read.
PDR3 is an 8-bit read/write enable register. When reset, PDR3 is initialized to H'00.
Rev. 1.0, 02/00, page 208 of 1141
MO S Pull- Up Selec t Regist er 3 (PUR3)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PUR34 PUR33 PUR32 PUR31 PUR30PUR37 PUR36 PUR35
Bit :
Initial value :
R/W :
MOS pul l-u p select o r re gister 3 (PUR3 ) control s the ON and OFF of the MOS pull-up tran sist or
of port 3. Only the pin whose corresponding bit of PCR3 was set to 0 (input) bec omes val id. If
the corresponding bit of PCR3 is set to 1 (output), the corre sponding bi t of PUR3 becomes invalid
and the MOS pull-up transistor i s turned off.
PUR3 is an 8-bit read/write enable register. When reset, PUR3 is initialized to H'00.
Bits 7 to 0P37 to P30 MOS Pull-Up Control (PUR37 to PUR30)
Bit n
PCR3n Description
0 The P3n pin has no MOS pull-up transistor (Init ial value)
1 The P3n pin has a MOS pull-up transistor
(n = 7 to 0)
10.5.3 Pin Functions
This section describes the port 3 pin functions and their selection methods.
P37/TMO: P37/TMO i s switche d as shown below according t o the PMR37 bit in PMR3 a nd the
PCR37 bi t in PCR3.
PMR37 PCR37 Pin Function
0 P37 input pin
01 P37 output pin
1*TM O ou tp ut pi n
Not e: *Don’t care
Rev. 1.0, 02/00, page 209 of 1141
P36/BUZZ: P36/BUZZ is switched as shown below ac c ording to the PMR36 bit i n PMR3 and the
PCR36 bi t in PCR3.
PMR36 PCR36 Pin Function
0 P36 input pin
0
1 P36 output pin
1*BUZZ output pin
Note: *Don’t care
P35/PWM3: P35/PWM3 is swit ched as shown bel ow according to the PMR3n bit in PMR3 and
the PCR3n bit in PCR3.
PMR35 PCR35 Pin Function
0 P35 input pin
0
1 P35 output pin
1*PWM3 out put pin
Note: *Don’t care
P34/PMW2: P34/PMW2 i s swi t ched as shown bel ow according to the PMR34 bit in PCR3 and
the PCR34 bit in PCR3.
PMR34 PCR34 Pin Function
0 P34 input pin
0
1 P34 output pin
1*PWM2 out put pin
Note: *Don’t care
P33/PWM1: P33/PWM1 is swit ched as shown bel ow according to the PMR33 bit in PMR3 and
the PCR33 bit in PCR3.
PMR33 PCR33 Pin Function
0 P33 input pin
01 P33 output pin
1*PWM1 input pin
Note: *Don’t care
Rev. 1.0, 02/00, page 210 of 1141
P32/PWM0: P32/PWM0 is swit ched as shown bel ow according to the PMR32 bit in PMR3 and
the PCR32 bit in PCR.
PMR32 PCR32 Pin Function
0 P32 input pin
0
1 P32 output pin
1*PWM0 out put pin
P31/SV2: P31/SV2 is switched as shown below according to the PMR31 bit in PMR3 and the
PCR31 bi t in PCR3.
PMR31 PCR3 Pin Function
0 P31 input pin
0
1 P31 output pin
1*SV2 out put pin
P30/SV1: P30/SV1 is switched as shown below according to the PMR30 bit in PMR3 and the
PCR30 bi t in PCR3.
PMR30 PCR30 Pin Function
0 P30 input pin
0
1 P30 output pin
1*SV1 out put pin
Note: *Don’t care
Rev. 1.0, 02/00, page 211 of 1141
10.5.4 P i n States
Table 10.13 shows the port 3 pin states in each operation mode.
Table 10. 13 Port 3 Pin States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
P37/TMO
P36/BUZZ
P35/PWM3
to
P32/PWM0
P31/SV2
P30/SV1
High-
impedance Operation Holding High-
impedance High-
impedance Operation Holding
Rev. 1.0, 02/00, page 212 of 1141
10.6 P ort 4
10.6.1 Overview
Port 4 is an 8-bit I/O port. Table 10.14 shows the port 4 c onfiguration.
Port 4 consists of pi ns tha t are used both as standard I/ O ports (P47 to P40) a nd output c ompare
output (FTOA, FTOB), input c apture input (FT IA, FTIB, FTIC, FTID) or 14-bit PWM output
(PWM14). It i s switched by port mode register 4 (PRM4), ti mer output com pa re cont rol regist er
(TOCR), and port control regist er 4 (PCR4).
Table 10. 14 Port 4 Configuration
Port Function Al t ernative Functi on
P47 (standard I/O port) RPTRG (realtime outpu t port trigger input)
P46 (standard I /O port) FTOB (t im er X1 output compare output )
P45 (standard I /O port) FTOA (t im er X1 output compare output )
P44 (standard I /O port) FTID (timer X1 input capture input)
P43 (standard I /O port) FTIC (timer X1 input capture input)
P42 (standard I /O port) FTIB (timer X1 input capture input)
P41 (standard I /O port) FTIA (timer X1 input capture input)
Port 4
P40 (standard I /O port) PWM14 (14-bit PWM output)
10.6.2 Register Configurati on
Table 10.15 shows the port 4 register configuration.
Tabl e 10. 15 P ort 4 Register Config ur a tio n
Name Abbrev. R/W Si z e Initi al Value Address*
Port mode register 4 PMR4 R/W Byt e H'7E H'FFDB
Port cont rol register 4 PCR4 W Byte H'00 H'FFD4
Port data register 4 PDR4 R/W Byte H'00 H'FFC4
Note: *Lower 16 bits of the address .
Rev. 1.0, 02/00, page 213 of 1141
Port Mode Register 4 (PMR4)
0
0
1
1
2
1
3
1
4
11
5
1
7
0
R/W
6—————PMR47 —
—————R/W —
PMR40
Bit :
Initial value :
R/W :
Port mode register 4 (PMR4) control s switching of the P47/RPTRG pin a nd the P40/PWM14 pi n
function. The switchings of the P46/FTOB and P45/FTOA functions are controll e d by TOCR.
See section 16, Timer X1. The FTIA, FTIB, FTIC, and FTID inputs always function.
PMR4 is an 8-bit read/write enable register. When reset, PMR4 is initialized to H'7E.
Because the RPTRG input al ways func t ion, the al t ernative pi n need always be set to the high or
low level regardless of the active mod e and low power cons umptio n mode. Note that the p in level
must not reach an intermediate level.
Because the FTIA, FTIB, FTIC, and FT ID input s always function, e ach input uses the input edge
to the al ternative genera l I/O pins P44, P43, P42, and P41 as input si gnals.
Bit 7P47/RP TRG Pin Switching (PM R47): PMR47 se t s whether the P47/RPTRG pin i s used
as a P40 I/O pin or a RPTRG pin for the realtime output port trigger input.
Bit 7
PMR47 Description
0 The P47/RPTRG pin functions as a P47 I/O pin ( I nit ial value)
1 The P47/RPTRG pin functions as a RPTRG I/O pin
Bits 6 to 1Reserved Bits: R es er ved bits. Wh en the b its are read, 1 is always r ead. The write
operation i s invalid.
Bit 0P40/PWM14 Pin Switching (PMR40): PMR40 sets whether the P40/PWM14 pin is used
as a P40 I/O pin or a PWM14 pin for the 14-bit PWM square wave out put.
Bit 0
PMR40 Description
0 The P40/PWM14 pin f unctions as a P40 I/O pin ( Initial value)
1 The P40/PWM 14 pin f unctions as a PWM 14 output pin
Rev. 1.0, 02/00, page 214 of 1141
Port Control Regist er 4 (PCR4)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5
0
7
0
W WWW
6PCR44 PCR43 PCR42 PCR41 PCR40PCR47 PCR46 PCR45
Bit :
Initial value :
R/W :
Port control register 4 (PCR4) c ontrols the I/Os of pins P47 t o P40 of port 4 in a unit of bit.
When PCR4 is set to 1, the corre sponding P47 to P40 pins become out put pins, and when i t is se t
to 0, they become input pins. When t he relevant pin i s set t o a gene ral I/O by PMR4, settings of
PCR4 a nd PDR4 become valid.
PCR4 is a n 8-bit write-only registe r. When PCR4 is read, 1 i s read. When reset, PCR4 is
initialized to H'00.
Bits 7 to 0P47 to P40 Pin Switching (PCR47 to PCR40)
Bit n
PCR4n Description
0 The P4n pin functions as an input pin (Init ial value)
1 The P4n pin functions as an output pin
(n = 7 to 0)
Port Data Register 4 (PDR4)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PDR44 PDR43 PDR42 PDR41 PDR40PDR47 PDR46 PDR45
Bit :
Initial value :
R/W :
Port data register 4 (PDR4) stores the data for the pins P47 to P40 of port 4. When PCR4 is 1
(output), the PDR4 va lues are directly read if port 4 is read. Accordingly, the pi n states a re not
affected. When PCR4 is 0 (input), the pin states are read if port 4 is read.
PDR4 is an 8-bit read/write enable register. When reset, PDR4 is initialized to H'00.
Rev. 1.0, 02/00, page 215 of 1141
10.6.3 Pin Functions
This section describes the port 4 pin functions and their selection methods.
P47/RPTRG: P47/ RPTRG is switched a s shown below ac cording t o the PMR47 bit i n PMR4 and
the PMR47 bit in PMR4 and the PCR47 bit in PCR4.
PMR47 PCR47 Pin Function
0 0 P47 input pin
1 P47 output pin
1*RPTRG input pin
P46/FTOB: P46/FTOB is swit c hed as shown be low according to the PCR46 bit in PCR4 a nd the
OEB bit i n TOCR.
OEB PCR46 Pin Function
0 P46 input pin
0
1 P46 output pin
1*FTOB output pin
Note: *Don’t care
P45/FTOA: P45/FTOA is swi tched as shown below according t o the PCR45 bit in PCR4 and the
OEA bit in TOCR.
OEA PCR45 Pin Function
0 P45 input pin
0
1 P45 output pin
1*FTOA output pin
Note: *Don’t care
P44/FTID: P44/FTID i s switche d as shown below according t o the PCR44 bit in PCR4.
PCR44 Pin Function
0 P44 input pin
1 P44 output pin
FTID input pin
Rev. 1.0, 02/00, page 216 of 1141
P43/FTIC: P43/FTIC is swit ched as shown below a ccording to the PCR43 bit in PCR4.
PCR43 Pin Function
0 P43 input pin
1 P43 output pin
FTIC input pin
P42/FTIB: P42/FTIB is swi tched as shown below according to the PCR42 bit in PCR4.
PCR42 Pin Function
0 P42 input pin
1 P42 output pin
FTIB input pin
P41/FTIA: P41/FTIA i s switche d as shown below according t o the PCR41 bit in PCR4.
PCR41 Pin Function
0 P41 input pin
1 P41 output pin
FTIA input pin
P40/PWM14: P40/PWM14 is switched as shown below according to the PMR40 bit in PMR4 and
the PCR40 bit in PCR4.
PMR40 PCR40 Pin Function
0 P40 input pin
01 P40 output pin
1*PWM14 input pin
Note: *Don’t care
Rev. 1.0, 02/00, page 217 of 1141
10.6.4 P i n States
Table 10.16 shows the port 4 pin states in each operation mode.
Table 10. 16 Port 4 Pin States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
P47
P46/FTOB
P45/FTOA
P44/FTID
P43/FTIC
P42/FTIB
P41/FTIA
P40/
PWM14
High-
impedance Operation Holding High-
impedance High-
impedance Operation Holding
Note: If the RPTRG input pin is set, the pin level must be set to the high or low level regardless of
the active mode or low power consum pt ion m ode. Note that the pin level must not reach an
int ermediat e le vel.
Because the FTI A, FTIB, FTIC, and FTID inputs always function, the alternative pin need be
set to the high or low level regardless of the active mode and low power consumption
mode.
Rev. 1.0, 02/00, page 218 of 1141
10.7 P ort 6
10.7.1 Overview
Port 6 is an 8-bit I/O port. Table 10. 17 shows the port 6 confi guration. Port 6 is a large current I/ O
port.
The synchronous c urrent i s 20 mA maximum (VOL=1.5 V) and four pins can be turne d on at t he
same time. Port 6 consi sts of pi ns that are used a s large current I/O ports (P67 to 67) and realtime
output port s (RP7 to RP0). It is switched by port mode register 6 (PMR6), port mode regi ste r A
(PMRA), a nd port cont rol register 6 (PCR6).
The realtime output function can instantaneously switch the output data by an external or internal
trigger port.
Table 10. 17 Port 6 Configuration
Port Function Al t ernative Functi on
P67 (large cur r ent I/O port) RP7/TMBI (timer B event input)
P66 (large curr ent I/O port) RP6/
$'75*
(A/D conversion start external
trigger input)
P65 (large cur r ent I/O port) RP5 (r ealt ime output port pin)
P64 (large cur r ent I/O port) RP4 (r ealt ime output port pin)
P63 (large cur r ent I/O port) RP3 (r ealt ime output port pin)
P62 (large cur r ent I/O port) RP2 (r ealt ime output port pin)
P61 (large cur r ent I/O port) RP1 (r ealt ime output port pin)
Port 6
P60 (large cur r ent I/O port) RP0 (realtime output port pin)
Rev. 1.0, 02/00, page 219 of 1141
10.7.2 Regi ster Configur ati on
Table 10.18 shows the port 6 register configuration.
Tabl e 10. 18 P ort 6 Register Config ur a tio n
Name Abbrev. R/W Si ze Initi al Value Address*
Port mode register 6 PMR6 R/W Byt e H'00 H'FFDD
Port mode register A PM RA R/W Byte H'3F H'FFD9
Port cont rol register 6 PCR6 W Byte H'00 H'FFD6
Port data register 6 PDR6 R/W Byte H'00 H'FFC6
Realtime output trigger
select regist er 1 RTPSR1 R/W Byte H'00 H'FFE5
Realtime output trigger
edge select register RTPEGR*2R/W Byte H'FC H'FFE4
Port cont rol register slave
6PCRS6 Byte H'00
Port dat a register slave 6 PDRS6 Byte H'00
Notes: 1. Lower 16 bits of the address .
2. RTPEGR is also used by port 7.
Port Mode Register 6 (PMR6)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PMR64 PMR63 PMR62 PMR61 PMR60
0
R/W
PMR67
R/WR/WR/W
PMR66 PMR65
Bit :
Initial value :
R/W :
Port mode register 6 (PMR6) control s switching of each pin function of port 6. The switc hing is
specified in units of bits.
PMR6 is an 8-bit read/write enable register. When reset, PMR6 is initialized to H'00.
Bits 7 to 0P67/RP7 to P60/RP0 Pi n Switching (PMR67 to PM R60): PMR67 to PMR60 set
whether t he P6n/RPn pin i s used as a P6n I/O pin or an RPn pin for the realtime output port.
Bit n
PMR6n Description
0 The P6n/RPn pin functions as a P6n I /O pin (Init ial value)
1 The P6n/RPn pin functions as an RPn out put pin
(n = 7 to 0)
Rev. 1.0, 02/00, page 220 of 1141
Port Mode Re gist er A (PMRA)
0
1
1
1
—
2
1
—
3
1
4
1
—
1
—
5
0
7
0
R/W ——R/W
6—————PMRA7 PMRA6 —
Bit :
Initial value :
R/W :
Port mode register A (PMRA) switches the pin funct ions in port 6. Switching is specified i n a unit
of bit. PMR6 i s an 8-bit read/ write regi ster.
When reset, PMRA is initialized to H'3F.
Bit 7P67/RP 7/ TMBI Pin Switching (PM RA7): PMRA7 can be used as a P6n I/O pin or a
TMBI pin for timer B event input.
Bit 7
PMRA7 Description
0 P67/RP7/TMBI pin f unctions as a P67/RP7 I/O pin (Initial value)
1 P67/RP7/TMBI pin f unctions as a TMBI pin
Bit 6Timer B Event Input Edg e Switching (PMRA6) : PMRA6 selects the T MBI edge se nse.
Bit 6
PMRA6 Description
0 Timer B event input detects falling edge
1 Timer B event input detects rising edge
Rev. 1.0, 02/00, page 221 of 1141
Port Control Regist er 6 (PCR6)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PCR64 PCR63 PCR62 PCR61 PCR60
0
W
PCR67
WWW
PCR66 PCR65
Bit :
Initial value :
R/W :
Port control register 6 (PCR6) selects the ge neral I/O of port 6 and controls the realtime output i n
a unit of bit together with PMR6.
When PMR6 = 0, the corre sponding P67 to P60 pins become general output pins if PCR6 i s set to
1, and they become general input pins if it is set to 0.
When PMR6 = 1, PCR6 controls the corresponding RP7 to RP0 realtime output pins. For details,
see section 10.8.4, Operation.
PCR6 is a n 8-bit write-only registe r. When PCR6 is read, 1 i s read. When reset, PCR6 is
initialized to H'00.
PMR6 PCR6
Bit n Bit n
PMR6n PCR6n Description
0The P6n/RPn pin functions as a P6n general I/O input pin
(Init ial value)
0
1 The P6n/RPn pin functions as a P6n general out put pin
1*The P6n/RPn pin functions as an RPn realtime output pin
Note: *Don’t care (n = 7 to 0)
Port Data Register 6 (PDR6)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PDR64 PDR63 PDR62 PDR61 PDR60
0
R/W
PDR67
R/WR/WR/W
PDR66 PDR65
Bit :
Initial value :
R/W :
Port data register 6 (PDR6) stores the data for the pins P67 to P60 of port 6.
For PMR6 = 0, when PCR6 is 1 (output), the PDR6 val ues a re directly rea d if port 6 i s rea d.
Accordingly, the pin states are not affected. When PCR6 is 0 (input), the pin states are read if port
6 is rea d.
For PMR6 = 1, port 6 becomes a realtime output pin. For details, see section 10. 7.4, Operation.
PDR6 is an 8-bit read/write enable register. When reset, PDR6 is initialized to H'00.
Rev. 1.0, 02/00, page 222 of 1141
Realtime Output Tri g ger Selec t Regi ster (RTPSR1 )
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7RTPSR14 RTPSR13 RTPSR12 RTPSR11 RTPSR10
0
R/W
RTPSR17
R/WR/WR/W
RTPSR16 RTPSR15
Bit :
Initial value :
R/W :
The realtime output trigger select register (RTPSR1) sets whether the external trigger (RPTRG pin
input) or the i nternal tri gger (HSW) is used as an trigge r input for the re altime output i n a unit of
bit. For the internal t rigger HSW, see section 26.4, HSW Timing Generation Circuit.
RTPSR is an 8-bit read/write enable register. When reset, RTPSR is initialized to H' 00.
Bits 7 to 0RP7 to RP0 Trigge r Switching
Bit n
RTPSR1n Description
0 Selects the external trigger (RPTRG pin input ) as a trigger input (Init ial value)
1 Selects the internal trigger (HSW) a trigger input
(n = 7 to 0)
Rev. 1.0, 02/00, page 223 of 1141
Real Time Output Trigge r Edge Select Regi ster (RTPEGR)
0
0
1
0
R/W
2
1
3
1
4
11
56
1
7——————
——————
RTPEGR1 RTPEGR0
1R/W
Bit :
Initial value :
R/W :
The realtime output trigger edge select register (RTPEGR) specifies the edge sense of the external
or internal trigger input for the realtime output.
RTPEGR is an 8-bit read/write enable register. When reset, RTPEGR is initialized to H'FC.
Bits 7 to 2Reserved Bits: Reserved bits. When the bits are read, 1 is always read. The write
operation i s invalid.
Bits 1 and 0Real time Output Tri gger Edge Select (RTPEGR1, RTPEGR0): RTPEGR1 and
RTPEGR0 select the edge sense of the external or internal trigger input for the realtime output.
Bit 1 Bit 0
RTPEGR1 RTPEGR0 Description
0 Inhibits a trigger input ( Initial value)01 Selects the r ising edge of a trigger input
0 Selects the falling edge of a t r igger input1
1 Selects both the leading and falling edges of a tr igger input
Rev. 1.0, 02/00, page 224 of 1141
10.7.3 Pin Functions
This section describes the port 6 pin functions and their selection methods.
P67/RP7/TMBI: P67/RP7/TMBI is switched as shown below according to the PMRA7 bit in
PMRA, PMR67 bit in PMR6, and PCR67 bit in PCR6.
PMRA7 PMR67 PCR67 Pin Function Output Value Value When PDR6n
Was Read
0 P67 input pin P67 pin
01 P67 output pin PDR67 PDR67
0 Hi-Z*1,*2
0
1
1
RP7 out put pin
PDRS67*2
PDR67
0 P67 pin1*
1
TMBI input pin
PDR67
Notes: 1. Hi-Z: High impedance
2. When PMR67=1 (r ealt ime output pin), indicates the state after t he PCR67 setup value
has been transferred to PCRS67 by a trigger input.
P66/RP6/
$
$
'
'75*
75*
: P66/ RP6/
$
'75*
is switched as shown below according to the PMR66 bit in
PMR6 and PCR66 bit in PCR6. The
$'75*
pin function switching i s controlle d by the ADTSR.
For details, refer t o section 24, A/D converter.
PMR66 PCR66 Pi n Function Output Value Value When PDR66 Was Read
0 P66 input pin P67 pin
01 P66 output pin PDR66 PDR66
0 Hi-Z*1,*2
1
1
RP6 out put pin
PDRS66*2
PDR66
Notes: 1. Hi-Z: High impedance
2. When PMR66=1 (r ealt ime output pin), indicates the state after t he PCR66 setup value
has been transferred to PCRS66 by a trigger input.
Rev. 1.0, 02/00, page 225 of 1141
P65/RP5 to P60/RPD: P65/RP5 to P60/RPD are switched below according to the PMRAn bit in
PMRA, PMR6n bit in PMR6, and PCR6n bit in PCR6.
PMR6n PCR6n Pi n Function Output Value Value When PDR6n Was Read
0 P6n input pin P6n pin
0
1 P6n output pin PDR6n PDR6n
0 RPn output pin Hi-Z*1,*2
1
1 RPn output pin PDRS6n*2
PDR6n
(n = 5 to 0)
Notes: 1. Hi-Z: High impedance
2. When PMR6n=1 (r ealt ime output pin), indicates the state after t he PCR6n setup value
has been transferred to PCRS6n by a trigger input.
Rev. 1.0, 02/00, page 226 of 1141
10.7.4 Operation
Port 6 ca n be used as a realtime output port or general I/O output port by PMR6. Port 6 functions
as a realtime output port when PMR6 = 1 and as a general I/O port when PMR6 = 0. The
operation pe r port 6 function is shown be l ow. (Se e figure 10.2.)
P6/RP
RTPEGR write
[Legend]
PMR6
PCR6
PDR6
PCRS6
PDRS6
RTPSR1
RTPEGR
HSW
RPTRG
: Port mode register 6
: Port control register 6
: Port data register 6
: Port control register slave 6
: Port data register slave 6
: Realtime output trigger select register
: Realtime output trigger edge select register
: Internal trigger signal
: External trigger pin
RTPSR write
RMR6 write
RDR6 write
RCR6 write
RDR6 read
RTPEGR
Selection
circuit
Selection
circuit
Internal data bus
External trigger
RPTRG
Internal trigger
HSW
CK
RTPSR
CK
PMR6
CK
PDR6
CK
PCR6
CK
RDRS6
CK
RCRS6
CK
Figure 10.2 Port 6 Function Block Diagram
Rev. 1.0, 02/00, page 227 of 1141
• Operation of the Realtime Output Port (PMR6 = 1)
When PMR6 is 1, it operates as a re altime out put port. When a trigger is input , the PDR6 data
is transferred to PDRS6 and the PCR6 is transferred data to PCRS6, respectively. In this case,
when PCRS6 is 1, the PDRS6 data of t he corre sponding bit i s output to the RP pin. When
PCRS6 is 0, the RP pin of the corre sponding bit is output to the high-im pedance state. In other
words, the pin output sta te (high or low) or high- impedance state can instantan eously be
switched by a trigger input .
Adversely, whe n PDR6 is read, the PDR6 val ues are read regardless of the PCR6 and PCRS6
values.
• Operation of the genera l I/O port (PMR6 = 0)
When PMR6 is 0, it operates as a general I/O port. When data is written to PDR6, the same
data is al so written to PDRS6. Acc ordingly, because both PDR6 and PDRS6 and bot h PCR6
and PCRS6 can be handled as one register, respectively, they can be used in the same way as a
normal general I/O port. In other words, if PCR6 is 1, the PDR6 data of the corresponding bit
is output t o the P6 pin. If PCR6 is 0, the P6 pin of t he corresponding bit be c omes an input.
Adversely, assuming that PDR6 is read, the PDR6 values are read when PCR6 is 1 and the pin
values are read when PCR6 is 0.
10.7.5 Pin States
Table 10.19 shows the port 6 pin states in each operation mode.
Table 10. 19 Port 6 Pin States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
P67/RP7 to
P60/RP0
P66/RP6/
$'75*
P65/RP5 to
P60/RP0
High-
impedance Operation Holding High-
impedance High-
impedance Operation Holding
Note: If the TMBI and
$
'75*
input pins are set, the pin level m ust be set to the high or low level
regardless of the active m ode or low power consumption m ode. Note that pin level must not
reach an intermediate level.
Rev. 1.0, 02/00, page 228 of 1141
10.8 P ort 7
10.8.1 Overview
Port 7 is an 8-bit I/O port. Table 10.20 shows the port 7 c onfiguration.
Port 7 consists of pi ns tha t are used both as standard I/ O ports (P77 to P70) a nd HSW timing
generation circuit (programmabl e pattern generator: PPG) outputs (PPG7 to PPG0). It is swi tched
by port m ode register 7 (PMR7) and port control register 7 (PCR7).
For the programmable generator (PPG), see section 26.4, HSW (Head-switch) Timing Gene rati on
Circuit.
Table 10. 20 Port 7 Configuration
Port Function Al t ernative Functi on
PPG7 (HSW timing output)
P77 (standard I /O port) RPB (realtime output port)
PPG6 (HSW timing output)P76 (standard I /O port) RPA (realtime output port)
PPG5 (HSW timing output)P75 (standard I /O port)
RP9 (realtime output port)
PPG4 (HSW timing output)P74 (standard I /O port)
RP8 (realtime output port)
P73 (standard I /O port) PPG3 (HSW timing output)
P72 (standard I /O port) PPG2 (HSW timing output)
P71 (standard I /O port) PPG1 (HSW timing output)
Port 7
P70 (standard I /O port) PPG0 (HSW timing output)
Rev. 1.0, 02/00, page 229 of 1141
10.8.2 Register Configurati on
Table 10.21 shows the port 7 register configuration.
Tabl e 10. 21 P ort 7 Register Config ur a tio n
Name Abbrev. R/W Si ze Initi al Value Address*
Port mode register 7 PMR7 R/W Byt e H'00 H'FFDE
Port mode register B PM RB R/W Byte H'0F H'FFDA
Port cont rol register 7 PCR7 W Byte H'00 H'FFD7
Port data register 7 PDR7 R/W Byte H'00 H'FFC7
Realtime output trigger
select regist er 2 RTPSR2 R/W Byte H'0F H'FFE6
Realtime output trigger
edge select register RTPEGR R/W Byte H'FC H'FFE4
Port cont rol register slave
7PCRS7 Byte H'00
Port dat a register slave 7 PDRS7 Byte H'00
Note: *Lower 16 bits of the addr ess .
Rev. 1.0, 02/00, page 230 of 1141
Port Mode Register 7 (PMR7)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PMR74 PMR73 PMR72 PMR71 PMR70
0
R/W
PMR77
R/WR/WR/W
PMR76 PMR75
Bit :
Initial value :
R/W :
Port mode register 7 (PMR7) control s switching of each pin function of port 7. The switc hing is
specified in a un it of b it.
PMR7 is an 8-bit read/write enable register. When reset, PMR7 is initialized to H'00.
Bits 7 to 0P77/PPG7 to P70/PPG0 Pi n Switching (PMR77 to PMR70): PMR77 to PMR70
set whet her t he P7n/PPGn pin is used as a P7n I/O pin or a PPGn pin for the HSW timing
generation circuit out put.
Bit n
PMR7n Description
0 The P7n /PP Gn pin func tions as a P7n I/O pin (Initial value)
1 The P7n/PPGn pin functions as a PPGn out put pin
(n = 7 to 0)
Port Mode Register B (PMRB)
0
1
1
1
2
1
3
1
4———PMRB4
———R/W
00
R/W
5
0
7
0
R/W —R/W
6—PMRB7 PMRB6 PMRB5
Bit :
Initial value :
R/W :
Port mode register B (PMRB) control s switching of each pin function of port 7. T he switching is
specified in a un it of b it.
PMRB is an 8-bit read/write enable register. When reset, PMRB is initialized to H'0F.
Rev. 1.0, 02/00, page 231 of 1141
Bits 7 to 4P77/RP7B to P74/RP8 Pin Switching (PMRB7 to PMRB4): P77 /RP7B to
P74/RP8 set whether the P7n/RPm pin i s used a s a P7n I/ O pin or a RPm pin for the realtime
output port. (n= 7 to 4 and m= B, A, 9, or 8)
Bit n
PMRBn Description
0 P7n/RPm pin functions as a P7n I/O pin (Initial value)
1 P7n/RPm pin functions as a RPm I/O pin
(n = 7 t o 4 and m = B, A, 9, and 8)
Bits 3 to 0Reserved Bits: R es er ved bits. Wh en the b its are read, 1 is always r ead. The write
operation i s invalid.
Port Control Regist er 7 (PCR7)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PCR74 PCR73 PCR72 PCR71 PCR70
0
W
PCR77
WWW
PCR76 PCR75
Bit :
Initial value :
R/W :
Port control register 7, together with PMRB, enable the ge neral-purpose input/ output of port 7 and
controls realtime output in bit units.
For details, refer to section 10.8.4. Operation.
PCR7 is a n 8-bit write-only registe r. When the PCR7 i s read, 1 is always read. Whe n reset, PCR7
is initialized to H'00.
Bits 7 to 0P77 to P70 Pi n I/O Switchi ng (P CR77 to PCR70)
PMRB PCR7
Bitn Bitn
PMRBn PCR7n Description
0 P7n/RPm pin f unctions as a P7n general input pin (Initial Value)01 P7n/RPm pin f unctions as a P7n general output pin
1*P7n/RPm pin funct ions as a RPm realtime output pin
(n = 7 t o 4 and m = B, A, 9, and 8)
Note: *Don’t care
Rev. 1.0, 02/00, page 232 of 1141
Port Data Register 7 (PDR7)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PDR74 PDR73 PDR72 PDR71 PDR70
0
R/W
PDR77
R/WR/WR/W
PDR76 PDR75
Bit :
Initial value :
R/W :
Port data register 7 (PDR7) stores the data for the pins P77 to P70 of port 7.
If PCR7 i s 1 (out put) when PMRB=0, t he PDR7 values are directly rea d when port 7 is read.
Accordingly, the pin states are not affected. When PCR7 is 0 (input), the pin states are read if port
7 is rea d. When PMRB=1, port 7 pin functions as a realtime out put pin. For details, refer t o
section 10.8.4, Operation.
PDR7 is an 8-bit read/write enable register. When reset, PDR7 is initialized to H'00.
Realtime Output Tri g ger Selec t Regi ster 2 (RTPSR2)
0
1
1
1
—
2
1
—
3
1
4
0
R/W
0
R/W
56
0
7RTPSR24 — — — —
0
R/W
RTPSR27
——R/W
RTPSR26 RTPSR25
Bit :
Initial value :
R/W :
Realtime output trigger select register (RTPSR2) selects whether to use an external trigger
(RPTRG pi n input) or internal trigger (HSW) for the realtime output trigger i nput by specifying a
unit of bit. For details on internal trigger HSW, refer to section 26.4, HSW (Head-switch) Timing
Generator.
RTPSR2 is an 8-bit read/write enable regist er .
When reset, RTPSR2 is initialized to H'0F.
Rev. 1.0, 02/00, page 233 of 1141
Bits 7 to 4RPB to RP8 Pin Tri gger Swi tching (RTPSR27 to RTPSR24 )
Bit7
RTPSR2n Description
0 Selects external trigger (RPTRG pin input) for trigger input (Initial value)
1 Selects internal trigger (HSW) for trigger input
(n = 7 to 4)
Realtime Output Trigger Edge Selection Re gister (RTPEG R)
0
0
1
0
R/W
2
1
3
1
4
11
56
1
7——————
——————
RTPEGR1 RTPEGR0
1R/W
Bit :
Initial value :
R/W :
The realtime output trigger edge selection register (RTPEGR) specifies the sensed edge(s) of
external or internal trigger input for realtime out put.
RTPEGR is an 8-bit readable/writable register. In a reset, RTPEGR is initialized to H'FC.
Bits 7 to 2—Reser ved: These bits are always read as 1 and cannot be modified.
Bits 1 and 0—Realtime Output Trigger Edge Select (RTPEGR1, RTPEG R0): Th es e b its
select the sensed edge (s) of e xternal or internal trigger input for realtime output.
Bit 1 Bit 0
RTPEGR1 RTPEGR0 Description
0 Disables trigger input (Init ial value)0
1 Selects trigger input rising edge
0 Select s trigger input falling edge1
1 Select s trigger input rising and falling edges
Rev. 1.0, 02/00, page 234 of 1141
10.8.3 Pin Functions
This section describes the port 7 pin functions and their selection methods.
P77/PPG7/RPB to P74/PPG4/RP8: P77/PPG7/RPB to P74/PPG4/RP8 are switched as shown
below according to the PMRBn bit in PMRB a nd the PCR7n bit in PCR7.
PMRBn PMR7n PCR7n Pin Function Output Value Value Returned w hen
PDR7n is Read
0 P7n input pin P7n pin
001 P7n output pin PDR7n PDR7n
0 P7n pin01
1
PPGn output pin PPGn
PDR7n
0 Hi-Z*
1*
1
RPm output pin
PDRS7n*
PDR7n
(n = 7 to 4, m = B, A, 9, 8)
Notes: *Don’t car e
1. When PMRBn = 1 (realtime output pin), the st at e indicated is that after t he PCR7n set
value has been transferred t o PCRS7n by trigger input .
Hi-Z: High impedance
P73 /PPG t o P7 0/PP G0 : P73/PPG to P70/PPG0 a re switc hed as shown bel ow according to the
PMR7n bit in PMR7 and the PCR7n bit in PCR7.
PMR7n PCR7n Pi n Function Output Value Value Returned when PDR7n
is Read
0 P7n input pin P7n pin
0
1 P7n output pin PDR7n PDR7n
0 P7n pin1
1
PPGn output pin PPGn
PDR7n
(n = 3 to 0)
Rev. 1.0, 02/00, page 235 of 1141
10.8.4 Operation
Port 7 can be used by the PMRB as a realtime output port or an I/O port.
Port 7 functions as a realtime output port when PMRB=1 and functions as an I/O port when
PMRB=0. Figure 10.3 show the block diagram of port 7.
P7/RP
RTPEGR write
RTPSR2 write
PMRA write
PDR7 write
PCR7 write
PDR7 read
RTPEGR
Select
Select
External trigger
RPTRG
Internal
trigger HSW
CK
RTPSR2
CK
PMRB: Port mode register B
PCR7: Port control register 7
PDR7: Port data register 7
PCRS7: Port control register slave 7
PDRS7: Port data register slave 7
[Legend] RTPSR2: Realtime output trigger select register
RTPEGR: Realtime output trigger edge select register
HSW: Internal trigger signal
RPTRG: External trigger pin
Internal data bus
PMRB
CK
PDR7
CK
PCR7
CK
PDRS7
CK
PCRS7
CK
Figure 10.3 Block Diagram of Port 7
Rev. 1.0, 02/00, page 236 of 1141
Port 7 functions as follows:
1. Realt ime out put port function (PMRB=1)
Port function as a realtime output port when PMRB is 1. After a trigger input , the PDR7 data
is transferred to PDRS7 and PCR7 data is transferred to PCRS7. In this case, when PCRS7 is
1, the PDRS7 data of the c orresponding bit is output from the RP pin. When PCRS7 is 0, the
RP pin of the corre sponding bit enters hi gh-impedance state. In ot her words, the realtime
output port function c an instantaneousl y switch the pin output state (High or Low) or high-
imp ed ance by a tr igger inp u t.
2. I/O port funct ion (PMRB=0)
Port 7 functions as an I/O port when PMRB is 0. After data is written to PDR7, the same data
is written to PDRS7. After data is written to PCR7, the same data is written to PCRS7. Since
PDR and PDRS7, and PCR7 and PCRS7 can be used as one register, the registers can be used
as the I/O ports. In other words, if PCR7 is 1, the PDR7 data of the corre sponding bi t is output
from the P7 pin. If PCR is 0, the P7 pin of the corre sponding bit is a n input pi n. If PD7 i s read,
the PDR7 value is read when PCR7 is 1 and the pin value is read when PCR7 is 0.
10.8.5 Pin States
Table 10.22 shows the port 7 pin states in each operation mode.
Table 10. 22 Port 6 Pin States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
P77/PPG7/RPB
to
P74/PPG4/RP8
P73/PPG3
to
P70/PPG0
High-
impedance Operation Holding High-
impedance High-
impedance Operation Holding
Rev. 1.0, 02/00, page 237 of 1141
10.9 P ort 8
10.9.1 Overview
Port 8 is an 8-bit I/O port. Table 10.23 shows the port 8 c onfiguration.
Port 8 consists of pi ns tha t are used both as standard-current I/O ports (P87 to P80) and an ext ernal
CTL signal input (EXCTL), a pre-amplifier output result signal input (COMP), color si gnal
outputs (R, G, and B), a pre-amplifier output selection signal out put (H. Amp SW), a control signal
out p ut f or proce ssi n g colo r signal (C .R ota r y ), a DPG signal i nput (DPG) , a ca psta n ext e r nal sync
signal input (E XCAP), an OSD cha r acter display posit i on output (YB0), an OSD c haracter data
output (YC0), and a n external re fe rence signal input (EXT TRG). It i s switched by port mode
register 8 (PMR8), port mode re gister C (PMRC), and port control regist er 8 (PCR8).
Table 10. 23 Port 8 Configuration
Port Function Al ternative Funct ion
P87 (standard I /O port) DPG signal input
P86 (standard I/O port) External reference signal inpu t
Pre-amplifie r output result signal inputP85 (standard I /O port)
Color signal output
Pre-amplifier output select ion signal outputP84 (standard I /O port)
Color signal output
Control signal output for processing color signalP83 (standard I /O port)
Color signal output
P82 (standard I /O port) External CTL signal input
Capstan ext ernal sync signal inputP81 (standard I /O port)
OSD character display position output
Port 8
P80 (standard I /O port) OSD character data output
Rev. 1.0, 02/00, page 238 of 1141
10.9.2 Register Configurati on
Table 10.24 shows the port 8 register configuration.
Tabl e 10. 24 P ort 8 Register Config ur a tio n
Name Abbrev. R/W Si z e Initi al Value Address*
Port mode register 8 PMR8 R/W Byt e H'00 H'FFDF
Port mode register C PMRC R/ W Byte H'C5 H'FFE0
Port cont rol register 8 PCR8 W Byte H'00 H'FFD8
Port data register 8 PDR8 R/W Byte H'00 H'FFC8
Note: *The address indicates the low-order 16 bits.
Rev. 1.0, 02/00, page 239 of 1141
Port Mode Register 8 (PMR8)
0
0
1
0
R/W
2
0
R/W
3
0
4
00
56
0
7PMR84PMR85PMR86PMR87
R/WR/WR/WR/W
PMR83 PMR82 PMR81 PMR80
0R/WR/W
Bit :
Initial value :
R/W :
Port mode register 8 (PMR8) control s switching of each pin function of port 8. The switc hing is
specified in a un it of b it.
PMR8 is an 8-bit read/write enable register. When reset, PMR8 is initialized to H'F0.
If t he EXCTL, COMP, DPG and EXTT RG in put pi ns are set , the pin le vel nee d alwa y s be set to
the hig h or lo w level re gar dless of th e active mode an d low pow er consumpt io n mo de. Note that
the pin level must not reach an intermediate level.
Bit 7P87/DP G Pin Switching (PMR87): PMR87 sets wh et her the P87/ DPG pin is used as a
P87 I / O pin or a DPG sig nal inp ut pin.
Bit 7
PMR87 Description
0P87/DPG pin functions as a P87 I/O pin
(Drum control signals are input as an overlapped signal) (Initial value)
1 P87/DPG pin functions as a DPG input pin
(Drum control signals are input as separate signals)
Bit 6P86/ E XTTRG Pin Switching (PMR86): PMR86 sets whether the P86/EXTTRG pin is
used as a P86 I/O p in or an extern al trig ger sig nal inpu t p in.
Bit 6
PMR86 Description
0 P86/EXTTR G pin functions as a P86 I/O pin (Initial value)
1 P86/EXTTR G pin functions as a EXTTR G input pin
Bit 5P85/C OM P Pin Swit ching (P MR85): PMR8 5 sets whether the P85/C OMP pin is used as
a P85 I/O pin or a COMP input pin of the preamplifier output result signal.
Bit 5
PMR85 Description
0 P85/COMP pin functions as a P85 I/O pin (I nit ial value)
1 P85/COMP pin functions as a CO M P input pin
Rev. 1.0, 02/00, page 240 of 1141
Bit 4P84/H.Amp SW Pin Swi tching (PMR84 ): PMR84 sets whet her the P8 4/H. Amp SW pin
is used as a P84 I/ O pin or H. Amp SW pin of the pre amplifier output select signal output .
Bit 4
PMR84 Description
0 P84/H.Amp SW pi n fu nctions as a P 84 I /O pi n (Initial v al ue)
1 P84/H.Amp SW pi n fu nctions as a H .Amp S W output pin
Bit 3P83/ C. Rotar y Pin Switc hi ng (PMR83): PMR83 sets whether the P83/C. Rotary pin is
used as a P83 I/ O pin or a C.Rotary pi n of a cont rol signal output for processing col or signal.
Bit 3
PMR83 Description
0 P83/C.Rotary pin functions as a P83 I/O pin ( Initial value)
1 P83/C.Rotary pin functions as a C.Rotary out put pin
Bit 2P82/EXCTL Pin Switching (PMR82): PMR82 sets whether the P82/EXCTL pin
functions a s a P82 I/O pin or a EXCTL input pin of external CTL signal i nput.
Bit 2
PMR82 Description
0 P82/EXCTL pin functions as a P82 I/O pin (Init ial value)
1 P82/EXCTL pin functions as a EXCTL input pin
Bit 1P81/EXCAP Pin Switching (PMR81): PMR81 sets whether the P81/EXCAP pi n
functions a s a P81 I/O pin or a EXCAP pi n of capsta n external synchronous signa l input.
Bit 1
PMR81 Description
0 P81/EXCAP pin func tions as a P81 I/O pin (Initial value)
1 P81/EXCAP pin functions as a EXCAP input pin
Bit 0P80/ YC0 Pin Swi tchi ng (PMR8 0): PMR80 sets whether the P80/YC0 pin funct ions as a
P80 I/O pin or a YC0 pin of OSD character data output.
Bit 0
PMR80 Description
0 P80/YC0 pin functions as a P80 I /O pin (Init ial value)
1 P80/YC0 pin functions as a YC0 output pin
Rev. 1.0, 02/00, page 241 of 1141
Port Mode Re gist er C (PMRC)
0
1
1
0
R/W
2
1
—
3
0
4
0
R/W
0
R/W
56
1
7PMRC4 PMRC3 — PMRC1 —
1
—
—
—R/W—
— PMRC5
Bit :
Initial value :
R/W :
Port mode register C (PMRC) control s switching of each pin function of port 8. T he switching is
specified in a un it of a b it.
PMRC is an 8-bit read/write enable register. When reset, PMRC is initialized to H'C5.
Bits 7, 6, 2, and 0Reserved B it s : Reserve d b its. Wh en th e bits are read, 1 is always r ead. Th e
write operation is invalid.
Bit 5P85/ B Pin Switc hi ng (PMRC5 ): PMRC5 sets whether to use the P85/B pin as a P85 I/O
pin or a B pin of the OSD color signal output.
Bit 5
PMRC5 Description
0 P85/B pin f unctions as a P85 pin (Initial value)
1 P85/B pin f unctions as a B out put pin
Bit 4P84/G Pi n Switching (PMRC4): PMRC4 sets whet he r to use the P84/ G pin as a P84 I/O
pin or a G pin of the OSD colo r signal outp ut.
Bit 4
PMRC4 Description
0 P84/G pin functions as a P84 I /O pin (Initial value)
1 P84/G pin func tions as a G output pin
Bit 3P83/ R Pin Switchi ng (PMRC3 ) : PMRC3 sets whether to use the P83/R pin as a P83 I/O
pin or a R pin of the OSD color signal output.
Bit 3
PMRC3 Description
0 P83/R pin functions as a P83 I/O pin (Initial value)
1 P83/R pin functions as a R out put pin
Rev. 1.0, 02/00, page 242 of 1141
Bit 1P81/YB0 Pin Switching (PMRC1): PMRC1 sets whether to use the P81/YB0 pin as a
P81 I/O pin or a YB 0 pin of the OSD character disp la y posi ti on outpu t.
Bit7
PMR1 Description
0 P81/YB0 pin functions as a P81 I /O pin (I nitial value)
1 P81/YB0 pin functions as a YB0 out put pin
Port Control Regist er 8 (PCR8)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PCR84 PCR83 PCR82 PCR81 PCR80
0
W
PCR87
WWW
PCR86 PCR85
Bit :
Initial value :
R/W :
Port control register 8 (PCR8) c ontrols I/O of pins P87 to P80 of port 8. The I/O is specified in a
unit of bit.
When PCR8 is set to 1, the corre sponding P87 to P80 pins become out put pins, and when i t is se t
to 0, they become input pins.
When the pins are set as gene ral I/O pins, the settings of PCR8 a nd PDR8 bec ome valid.
PCR8 is a n 8-bit write-only registe r. When PCR8 is read, 1 i s read. When rese t PCR8 i s initialized
to H'00.
Bits 7 to 0P87 to P80 Pin I/O Switching
Bit n
PCR8n Description
0 P8n pin functions as an input pin (Init ial value)
1 P8n pin functions as an output pin
(n = 7 to 0)
Rev. 1.0, 02/00, page 243 of 1141
Port Data Register 8 (PDR8)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PDR784 PDR83 PDR82 PDR81 PDR80
0
R/W
PDR87
R/WR/WR/W
PDR86 PDR85
Bit :
Initial value :
R/W :
Port data register 8 (PDR8) stores the data of pins P87 to P80 port 8. Whe n PCR is 1 (out put), the
pin states are read is port 8 is read. Accordingly, the pin states are not affected. When PCR8 is 0
(input), the pin states are read it port 8 is read.
PDR8 is an 8-bit read/write enable register. When reset, PDR8 is initialized to H'00.
Rev. 1.0, 02/00, page 244 of 1141
10.9.3 Pin Functions
This section describes the port 8 pin functions and their selection methods.
P87/DPG: P87/DPG is switch ed as sho wn below acco rdi ng to the PMR87 bit in PMR8 and
PCR87 bi t in PCR8.
PMR87 PCR87 Pi n Function
0 P87 input pin
0
1 P87 output pin
1*DPG input pin
P86/EXTTRG: P86/EXTTRG is switched as shown below according to the PMR86 bit in PMR8
and PCR86 bit in PCR8.
PMR86 PCR86 Pi n Function
0 P86 input pin
0
1 P86 output pin
1*EXTTRG input pin
P85/COMP/B: P85/COMP/B is switched as shown below according to the PMR85 bit in PMR8,
PMRC5 bit in PMRC, and PCR85 bit in PCR8.
PMRC5 PMR85 PCR85 Pin Function
0 P85 input pin
001 P85 output pin
*1*COMP input pin
10*B output pin
P84/H.Amp SW/G: P84/ H.Amp SW / G is switched a s shown below according to the PMR84 bit
in PMR, PMRC4 bi t in PMRC, and PCR84 bit in PCR8.
PMRC4 PMR84 PCR84 Pin Function
0 P84 input pin
00
1 P84 output pin
*1*H.Amp SW o u tput p in
10*G outp ut pin
Rev. 1.0, 02/00, page 245 of 1141
P83/C.Rotary/R: P83/C.Rotary/R is switched as shown below ac cording to the PMR83bit in
PMR8, PMRC3 bit in PMRC, and PCR83 bit in PCR8.
PMRC3 PMR83 PCR83 Pin Function
0 P83 input pin
00
1 P83 output pin
*1*C.Rotary output pin
10*R output pin
P82/EXCTL: P82/EXCTL is switched as shown below according to the PMR82 bit in PMR8 and
PCR82 bi t in PCR8.
PMR82 PCR82 Pi n Function
0 P82 input pin
01 P82 output pin
1*EXCTL input pin
P81/EXCAP/YB0: P81/EXCAP/YB0 is swit ched as shown bel ow accordi ng to the PMR81 bi t in
PMR8, PMRC1 bit in PMRC, and PCR81 bit in PCR8.
PMRC1 PMR81 PCR81 Pin Function
0 P81 input pin
00
1 P81 output pin
*1*EXCAP output pin
10*YB0 out put pin
P80/YC0: P80/YC0 is switched as shown below according to the PMR80 bit in PMR8 and PCR80
bit in PCR
PMR80 PCR80 Pi n Function
0 P80 input pin
0
1 P80 output pin
1*YC0 out put pin
Note: *Don’t care
Rev. 1.0, 02/00, page 246 of 1141
10.9.4 P i n States
Table 10.25 shows the port 8 pin states in each operation mode.
Table 10. 25 Port 8 Pin States
Pins Reset Active Sleep Standby Watch Subactive Subsleep
P87/DPG
P86/
EXTTRG
P85/COMP/
B
P84/H.Amp
SW/G
P83/
C.Rotary/R
P82/EXCTL
P81/
EXCAP/
YB0
P80/YC0
High-
impedance Operation Holding High-
impedance High-
impedance Operation Holding
Notes: 1. I f the EXCTL, COMP, and EXTTRG input pins are set, the pin level need always be set
to the high or low level r egardless of the active mode and low power consumption
mode. Note that the pin level must not reach an intermediate level.
2. As the DPG always functions, a high or low pin level must be input to the multiplexed
pins regardless of whether act ive mode or power- down mode is in effect.
Rev. 1.0, 02/00, page 247 of 1141
Section 11 Timer A
11.1 Overview
Timer A is an 8-bit i nterval timer. It can be used as a clock timer when connected t o a 32.768 kHz
crystal oscillator.
11.1.1 Features
Features of timer A are as follows:
• Choices of eight different types of internal clocks (φ/16384, φ/8192, φ/4096, φ/1024, φ/512,
φ/256, φ/64 and φ/ 16) are available for your selection.
• Four different overflowing cycles (1s, 0.5s, 0.25s and 0.03125s) are selectable as a clock timer.
(When usi ng a 32.768 kHz crystal oscillator.)
• Requests for interrupt will be output when the c ounter ove rflows.
Rev. 1.0, 02/00, page 248 of 1141
11.1.2 Block Diagram
Figure 11. 1 shows a bloc k diagram of timer A.
[Legend]
TMA
32 kHz
Crystal oscillator
Overflowing of
the interval
timer
System
clock
φw
φw/128
φ/16384, φ/8192,
φ/4096, φ/1024,
φ/512, φ/256,
φ/64, φ/16
φ
TCA
: Timer mode register A
: Timer counter A
Note: * Selectable only when the prescaler W output (φw/128) is
working as the input clock to the TCA.
Prescaler S
(PSS) Interrupting
circuit
Prescaler unit
Prescaler W
(PSW)
TCA
1/4 TMA
Interrupt
requests
Internal data bus
÷8 *
÷64 *
÷128 *
÷256 *
Figure 11.1 Block Diagr am of Timer A
11.1.3 Register Configurati on
Table 11.1 shows the register configuration of timer A.
Table 11. 1 Register Configurati on
Name Abbrev. R/W Size I nitial Value Address*
Timer mode register A TMA R/W Byte H'30 H'FFBA
Timer counter A TCA R Byte H'00 H'FFBB
Note: * Lower 16 bits of the address.
Rev. 1.0, 02/00, page 249 of 1141
11.2 Regi ster Descri pt i on s
11.2.1 Timer Mode Register A (TMA)
0
0
1
0
R/W
2
0
R/W
3
0
4
1
5——
——
1
6
0
7
R/WR/WR/W
TMAIE
0
R/(W)*
TMAOV TMA3 TMA2 TMA1 TMA0
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
The timer mode register A (T MA) works t o control the interrupts of timer A and to se lect the input
clock.
TMA is an 8-bit read/write register. When reset, the TMA will be initialized to H'30.
Bit 7Timer A Overflow Flag (TM AOV): This is a status flag indicating the fact that the TCA
is overflowing (H'FF → H'00).
Bit 7
TMAOV Description
0[Clearing condit ions] (Initial value)
When 0 is written t o the TMAO V f lag after reading the TMAO V flag under the status
where TMAOV = 1
1 [Setting condition s]
When the TCA overflows
Bit 6Enabling Interrupt of the Ti mer A (TMAIE): This bit works to permit/prohibi t
occu rrence of i nterrupt of the Timer A (T MAI) when the TCA ove rflows and when the TMAOV
of the TMA is set to 1.
Bit 6
TMAIE Description
0 Prohibits occurrence of interrupt of the Timer A (TM AI) ( I nit ial value)
1 Permits occurrence of interrupt of the Timer A (TMAI)
Bits 5 and 4Reserved: These bits cannot be modified and are always read as 1.
Rev. 1.0, 02/00, page 250 of 1141
Bit 3Selection of the Clock Source and Pr escaler (TMA3): This bit works to select the PSS
or PSW as the clock source for the Timer A.
Bit 3
TMA3 Description
0 Selects the PSS as the clock source for the Timer A (Initial value)
1 Selects the PSW as the clock source for the Timer A
Bits 2 to 0Clock Selection (TMA2 to TMA0): These bits work to select the clo ck to input to
the TCA. In combination with the TMA3 bit, the choices are as follows:
Bit 3 Bit 2 Bit 1 Bit 0
TMA3 TMA2 TMA1 TMA0 Prescaler Division Rati o (Interval Timer)
or Overflow Cycle (Time Base) Operation
Mode
0 PSS, φ/16384 (Initial value)01 PSS, φ/8192
0 PSS, φ/4096
0
1
1 PSS, φ/1024
0 PSS, φ/5120
1 PSS, φ/256
0 PSS, φ/64
0
1
1
1 PSS, φ/16
Interval
timer mode
01s010.5s
0 0.25s
0
11 0.03125s
00 1
0
1
1
1
1
Works to clear the PSW and TCA to H'00
Clock time
base mode
Note: φ = f osc
Rev. 1.0, 02/00, page 251 of 1141
11. 2. 2 T i m er Counte r A (TCA)
0
0
1
0
R
2
0
R
3
0
4567
RR
TCA3
0
R
TCA4
0
R
TCA5
0
R
TCA6
0
R
TCA7 TCA2 TCA1 TCA0
Bit :
Initial value :
R/W :
The timer count er A (TCA) is an 8-bi t up-counter that c ounts up on inputs from the internal clock.
The inputting clock can be selected by TMA3 to TMA0 bits of the TMA
Wh en the TCA ove rfl ows, the TMAOV bit of the TMA is set to 1.
The TCA can be cleared by setting the TMA3 and TMA2 bits of the TMA to 11.
The TCA is always readable. When reset, the TCA will be initialized into H'00.
11. 2. 3 Modul e Sto p Contr ol Regi ster (MSTP CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Initial value :
R/W :
Bit :
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP15 bit is set to 1, the Timer A stops its operation at the ending point of the bus
cycle to shift to the m odule stop mode. For more i nformation, se e section 4.5, Module Stop
Mode . When re set, the MST PCR will be init i al iz e d int o H'FFFF.
Bit 7Module Stop (MSTP15): This bit works t o designate the module stop m ode for the Timer
A.
MSTPCRH
Bit 7
MSTP15 Description
0 Cancels the module stop mode of the Timer A
1 Sets the module stop mode of the Timer A (Initial value)
Rev. 1.0, 02/00, page 252 of 1141
11.3 Operation
Timer A is an 8-bit interval timer. It can be used as a clock timer wh en connec ted to a 32.768 kH z
crystal oscillator.
11.3.1 Operation as the Inter val Timer
When the TMA3 bit of the TMA is cl eared t o 0, timer A works as an 8-bit interva l timer.
After reset, the TCA is cleared to H'00 and as the TMA3 bit is cleared to 0, the Timer A continues
counting up as the interval counter without interrupts right after reset ting.
As the operation clock for timer A, selection can be made from eight different t ypes of internal
cl ock s bei ng outp ut from t he PSS by the TMA2 to TMA0 bits of the TMA.
When the clock signal i s input aft er the readi ng of the T CA reache s H'FF, timer A ove rflows a nd
the TMAOV bit of the TMA wi ll be set to 1. An i nte rrupt oc c urs when t he TMAIE bit of the
TMA i s 1.
When overflowing occurs, the re a ding of the TCA returns to H' 00 be fore resumi ng counti ng up.
Consequentl y, it works a s the int erval t imer to produce overflow outputs periodically at every 256
input cloc ks.
11.3.2 Operation as Clock Timer
When the TMA3 bit of the TMA is set t o 1, ti mer A works a s a time base for the c l ock.
As the overflow cycles for ti mer A, selection can be made from four different types by counti ng
the clock being output from the PSW by the TMA1 bit and TMA0 bit of the TMA.
11.3.3 Initializing the Counts
When the TMA3 and TMA2 bits are set to 11, the PSW and TCA will be cleared to H'00 to come
to a sto p .
At this state, writing 10 to the TMA3 bit and TMA2 bit makes timer A start counting from H'00 in
the time base mode for clocks.
After clearing the PSW and TCA using the TMA3 and TMA2 bits, writing 00 or 01 to the TMA3
bit and TMA2 bit to make timer A start counting from H'00 in the interval timer mode. However,
th e pe ri od to the fi r st count is n ot con sta nt, si nce t he PSS is n ot cleared.
Rev. 1.0, 02/00, page 253 of 1141
Section 12 Timer B
12.1 Overview
Timer B i s an 8-bit up-counter. Timer B is equipped wit h two di fferent types of functions namely,
the interval function and the auto reloading function.
12.1.1 Features
• Seven diffe rent type s of i nternal cl ocks (φ/16384, φ/4096, φ/1024, φ/512, φ/128, φ/32 and φ/8)
or an of external c lock can be selected.
• When the count er overflows , a interrup t requ est wil l be issued.
12.1.2 Block Diagram
Figure 12. 1 shows a bloc k diagram of timer B.
[Legend]
TMB
φ/16384
φ/4096
φ/1024
φ/512
φ/128
φ/32
φ/8
TMBI
TCB : Timer mode register B
: Timer counter B
TLB
TMBI : Timer re-loading register B
: Event input terminal of the Timer B
Re-loading
Clock sources
Overflowing
Timer B
Interrupt requests
Internal data bus
TCB
TMB
TLB
Interrupting
circuit
Figure 12.1 Block Diagr am of Timer B
Rev. 1.0, 02/00, page 254 of 1141
12.1.3 P i n Confi guration
Table 12. 1 shows the pi n configuration of timer B.
Table 12. 1 Pin Configuration
Name Abbrev. I/O Function
Event inputs to timer B TM BI Input Event input pin f or inputs to the TCB
12.1.4 Register Configurati on
Table 12.2 shows the register configuration of timer B.
The TCB and TLB are being allocated to the same address. Reading or writing determines the
accessing register.
Table 12. 2 Register Configurati on
Name Abbrev. R/W Size I nitial Value Address*
Timer mode register B TMB R/W Byte H'18 H'D110
Timer counter B TCB R Byte H'00 H'D111
Timer load r egister B TLB W Byt e H'00 H'D111
Port mode register A PM RA R/W Byte H'3F H'FFD9
Note: * Lower 16 bits of the address.
Rev. 1.0, 02/00, page 255 of 1141
12.2 Regi ster Descri pt i on s
12.2.1 Timer Mode Register B (TMB)
0
0
1
0
R/W
2
0
R/W
3
1
4
——
——
1
5
0
6
0
7
R/WR/W
TMBIE
R/(W)*
TMBIF
0
R/W
TMB17 TMB12 TMB11 TMB10
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
The TMB is an 8-bi t read/write registe r which works to control the interrupts, to select the a uto
reloading function and to select the input clock.
When reset, the TMB is initialized to H'18.
Bit 7Selecting the Auto Reloading F unction (TMB17): This bit works to select the a ut o
reloading function of the Timer B.
Bit 7
TMB17 Description
0 Selects the interval funct ion (I nit ial value)
1 Selects the auto reloading function
Bit 6Interrupt Requesting Flag for the Timer B (TMBIF): This is an interrupt requesting
flag for the Timer B. It indicates the fact that the TCB is overflowing.
Bit 6
TMBIF Description
0 [Clearing conditions] (Initial value)
When 0 is written after reading 1
1[Setting condition s]
When the TCB overflows
Rev. 1.0, 02/00, page 256 of 1141
Bit 5Enabling Interrupt of the Ti mer B (TM BIE): This bi t works to per mit/pro hib it
occurrence of interrupt of timer B when t he TCB overfl ows and when the T MBIF is set to 1.
Bit 5
TMBIE Description
0 Prohibits interrupt of timer B (Initial value)
1 Permits interrupt of timer B
Bits 4 and 3Reserved: These bits cannot be modified and are always read as 1.
Bits 2 to 0Clock Selection (TMB12 to TMB10): These bits work to sel ect the clock to input to
the TCB. Selection of the rising edge or the falling edge is workable with the external event
inputs.
Bit 2 Bit 1 Bit 0
TMB12 TMB11 TMB10 Descriptions
0 0 0 Internal clock: Counts at φ/16384 (I nitial value)
0 0 1 Internal clock: Counts at φ/4096
0 1 0 Internal clock: Counts at φ/1024
0 1 1 Internal clock: Counts at φ/512
1 0 0 Internal clock: Counts at φ/128
1 0 1 Internal clock: Counts at φ/32
1 1 0 Internal clock: Counts at φ/8
1 1 1 Counts at the rising edge and the falling edge of external
event inputs (TMBI) *
Note: * The edge selection for the ext ernal event inputs is made by setting the PMRA6 of the
port mode register A (PMRA) . See sect ion 12. 2.4, Por t Mode Register A (PMRA).
Rev. 1.0, 02/00, page 257 of 1141
12.2.2 Ti mer Counter B (TCB)
0
0
1
0
R
2
0
R
345
0
6
0
7
RR
TCB15
0
R
TCB14
0
R
TCB13
R
TCB16
0
R
TCB17 TCB12 TCB11 TCB10
Bit :
Initial value :
R/W :
The TCB is an 8-bit re adable regi ster which works to c ount up by the int e rnal cl ock input s and
external event inputs. The input clock can be selected by the TMB12 to TMB10 of the TMB.
When the TCB overflows (H 'FF → H'00 or H'FF → TL B setting), a inte rrupt reque st of t he Timer
B will be i ssued.
When reset, the TCB is initialized to H'00.
12.2.3 Timer Load Re gister B (TLB)
0
0
1
0
W
2
0
W
345
0
6
0
7
WW
TLB15
0
W
TLB14
0
W
TLB13
W
TLB16
0
W
TLB17 TLB12 TLB11 TLB10
Bit :
Initial value :
R/W :
The TLB i s an 8-bit writ e only re gi ster which works to set the reloading value of the TCB.
When the reloading value is set to the TLB, the value will be simultaneously loaded to the TCB
and the TCB starts counting up from t he se t value. Also, during an aut o reloading operation, when
the TCB overflows, the value of the TLB will be l oaded to the T CB. Consequently, the
overflowing cycl e can be set within the range of 1 to 256 input cl oc ks.
When reset, the TLB is initialized to H' 00.
Rev. 1.0, 02/00, page 258 of 1141
12. 2. 4 Por t Mode Register A (PMRA)
01
1
—
2
1
—
34
1
567
——PMRA6PMRA7
—
—
——R/WR/W
—
1
—
——
1100
Bit :
Initial value :
R/W :
The port mode register A (PMRA) works to changeover the pin functions of the port 6 and to
designate the edge sense of the eve nt inputs of timer B (TMBI).
The PMRA is an 8-bit read/write regi ster. When re set, the PMRA will be initialized to H'3F.
See section 10. 7, Port 6 for other i nformation tha n bit 6.
Bit 6Selec ting the Edge s of the Event Inputs to the Timer B (PMRA6): This bit works to
select the input edge sense of the TMBI pins.
Bit 6
PMRA6 Description
0 Detects the falling edge of the event inputs t o the Timer B (I nit ial value)
1 Detects the rising edge of the event inputs t o the Timer B
Rev. 1.0, 02/00, page 259 of 1141
12. 2. 5 Modul e Sto p Contr ol Regi ster (MSTPCR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Initial value :
R/W :
Bit :
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP14 bit is se t to 1, the Timer B stops its ope ration at the ending point of the bus
cycle to shift to the m odule stop mode. For more i nformation, se e section 4.5, Module stop m ode.
When rese t, the MSTPCR is initia l iz ed to H'FFFF.
Bit 6Module Stop (MSTP14): This bit works t o designate the module stop m ode for the Timer
B.
MSTPCRH
Bit 6
MSTP14 Description
0 Cancels the module stop mode of the Timer B
1 Sets the module stop mode of the Timer B (Initial value)
Rev. 1.0, 02/00, page 260 of 1141
12.3 Operation
12.3.1 Operation as the Inter val Timer
When the TMB17 bit of t he TMB is set to 0, timer B works as an 8-bit interval timer.
When reset, since the TCB is cleared to H'00 and as the TMB17 bit is cleared to 0, timer B
continues count ing up as the interval time r withou t interrupts right after rese tt ing .
As the cl ock source for t imer B, selection can be made from seven diffe rent type s of internal
clocks being output from the prescaler unit by the TMB12 to TMB10 bits of the TMB or an
external clock through the TMBI i nput pin c an be chosen instead.
When the clock signal i s input aft er the readi ng of the T CB reaches H' FF, timer B overflows a nd
the TMBIF bit of the TMB will be set to 1. At this time, when the TMBIE bit of the TMB is 1,
interrupt occ urs.
When overflowing occurs, the re a ding of the TCB returns t o H'00 before resuming c ounting up.
When a value is set to the TLB while the interval timer is in operation, the value which has been
set to the TLB will be loaded to the TCB simultaneously.
12.3.2 Operation as the Auto Reload Timer
When the TMB17 of the TMB is set to 1, the Ti mer B works as an 8-bit auto reload timer.
When a reload value is set in the TLB, the value is loaded onto the TCB at the same time, and the
TCB starts counting up from the value.
When the clock signal i s input aft er the readi ng of the T CB reaches H' FF, timer B overflows a nd
the TLB value is loaded onto the TCB, then the TCB continues counting up from the loaded value.
Accordingl y, overflow interval c an be set within the range of 1 to 256 clocks depending on the
TLB value.
Clock sourc e and interrupts i n the a ut o re l oad operation a re the same as those in t he interval
operation. When the TLB value is re-set while the auto reload timer is in operation, the value
which has been set to the TLB will be loaded onto the TCB simultaneously.
12.3.3 Event Counter
Timer B works as an event count er using the TMBI pin as the event inpu t pin. When the TMB12
to TMB10 are set to 111, the external event will be selected as the clock source and the TCB
counts up at the le ading edge or the traili ng edge of the T MBI pin inputs.
Rev. 1.0, 02/00, page 261 of 1141
Section 13 Timer J
13.1 Overview
Timer J consists of twin counters. It carries different operation modes such as reloading and event
counting.
13.1.1 Features
Timer J consists of a n 8-bi t reloading time r and an 8-bit/16-bit selectable reloading timer. It has
various functions as listed below. The two timers can be used separately, or they can be connected
together to operate as a single timer.
• Reloadin g timers
• Event counters
• Remote-co ntro lled transmiss ions
• Takeup/Supply reel pulse division
13.1.2 Block Diagram
Figure 13.1 is a block diagra m of timer J. Timer J consists of two reload timers namely, TMJ-1
and TMJ-2.
Rev. 1.0, 02/00, page 262 of 1141
[Legend]
TCJ
Note: * At the Low level under the timer mode.
TLJ
: Timer counter J
: Timer load register J
TCK
TLK
: Timer counter K
: Timer load register K
TMO
REMOout
: TMJ-1 timer output
: TMJ-2 toggle output
(Remote controller
transmission data)
BUZZ
Reloading register
(Burst/space
width register
PS22, 21,20
EXN
: Buzzer output
TGL : TMJ-2 toggle flag
PS22, 21,20
ST
: TMJ-2 input clock selection
: Starting the remote controlled operation
PS11,10 : TMJ-1 input clock selection
8/16
T/R
EXN
: 8-bit/16-bit operation changeover
: Timer output/Remote controller output changeover
: Expansion function switching
Internal data bus
Edge
detection
Toggle
T/R
Down-counter
(8/16-bit)
BUSS
Output
Control
Monitor
Output
Control
Toggle
Reloading
register
8/16
ST
PS11,10
Down-
counter (8-bit)
UnderÐ
flow Under-
flow
TCJ
TMJ-1 TMJ-2 TCK
PB/REC-CTL
DVCTL
TCA7
φ/4096
φ/8192
TGL
REMOout
TMO
TMO
BUZZ
Clock sources
IRQ2
φ/64
φ/128
φ/1024
φ/2048
φ/16384
Clock sources
IRQ1
φ/4
φ/256
φ/512
*
Synchronization
TLJ
Reloading
Reloading
TLK
TMJ-1
Interrupting circuit Interrupt request
by the TMJ1I
Interrupt request
by the TMJ2I
TMJ-2
Interrupting circuit
Figure 13.1 Block Diagr am of timer J
Rev. 1.0, 02/00, page 263 of 1141
13.1.3 P i n Confi guration
Table 13. 1 shows the pi n configuration of timer J.
Table 13. 1 Pin Configuration
Name Abbrev. I/O Function
Event input pin
,54
Input Event inputs t o the TMJ-1
Event input pin
,54
Input Event inputs t o the TMJ-2
13.1.4 Register Configurati on
Table 13.2 shows the register configuration of timer J.
The TCJ and TLJ or the TCK and TLK are being allocated to the same address respectively.
Reading or writing determines the accessing register.
Table 13. 2 Register Configurati on
Name Abbrev. R/W Si ze Initi al Value Address*2
Timer mode register J TMJ R/W Byt e H'00 H'D13A
Timer J control regist er TMJC R/W Byte H'09 H'D13B
Timer J status register TM JS R/(W)*1 Byte H'3F H'D13C
Timer counter J TCJ R Byt e H'FF H'D139
Timer counter K TCK R Byte H'FF H'D138
Timer load r egister J TLJ W Byte H'FF H'D139
Timer load r egister K TLK W Byt e H'FF H'D138
Notes: 1. O nly 0 can be wr itten to clear the flag.
2. Lower 16 bits of the address .
Rev. 1.0, 02/00, page 264 of 1141
13.2 Regi ster Descri pt i on s
13.2.1 Timer Mode Register J (TMJ)
0
0
1
0
R
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/W
ST
R/W
PS10
0
R/W
PS11 8/16 PS21 PS20 TGL T/R
Bit :
Initial value :
R/W :
The timer mode registe r J (TMJ) works to select the inputting clo ck for the TMJ-1 and TMJ-2 and
to set the operation mode.
The TMJ is an 8-bit register and bit 1 is for read only. All the remaining bits are applicable to
read/write.
When reset, the TMJ is initialized to H' 00.
Under all other modes than the remote contro lling mod e, writin g into the TMJ works to initializ e
the counters (TCJ and TCK) to H'FF.
Bits 7 and 6Selecting the Inputti ng Clock to the TMJ-1 (PS11 and P S10): These bits work
to select the clock to input to t he TMJ-1. W hen the external cloc k is selected, the counted edge
(rising or falling) ca n also be selected.
Bit 7 Bit 6
PS11 PS10 Description
0 Count ing by the PSS, φ/512 (Initial value)01 Count ing by the PSS, φ/256
0 Count ing by the PSS, φ/411Counting at the rising edge or the falling edge of the external clock
inputs (
,54
) *
Note: * The edge selection for the ext ernal clock input s is m ade by sett ing the IRQ edge select
register (IEGR). See section 6.2. 4, IRQ Edge Select Register (IEGR) for more
information.
When using an external clock under the remote contr olling m ode, set t he opposite edge
with the IRQ1 and the I RQ 2 when using an external clock under t he remote controlling
mode. (When IRQ1 fall ing, select IRQ 2 rising and whe n IRQ1 rising, selec t IRQ2
falling)
Rev. 1.0, 02/00, page 265 of 1141
Bit 5Starting the Remote Controlled Operation (ST): This bit works to start the remote
controlled operat i ons.
Whe n this bit is se t to 1 , clo ck signal is sup plied to the TMJ - 1 to start signal tr ansmissions.
When this bit is cleared to 0, clock supply stops to disc ontinue the operation. The ST bit will be
valid under the remote controlling mode, namely, when bit 0 (T/R bit) is 1 and bit 4 (8/16 bit) is 0.
Un der o ther modes than the remote con tr ollin g mo de, it will be f ixed to 0. When a shif t to the low
power consumption mode is made during remote controlled operation, the ST bit will be cleared to
0. When resuming operation after returning to the active mode, write 1.
Bit 5
ST Description
0 Works to stop clock signal supply to the TMJ-1 under the remote controlling mode
(Init ial value)
1 Works to supply clock signal to t he TMJ-1 under the r emot e controlling mode
Bit 4Switching Over Be tween 8-bit/ 16-bit Operations (8/ 16): This bit works to c hoose if
using tim e r J a s two unit s of 8-bit time r/counter or if using it as a single unit of 16-bit
timer/counter. Even under 16-bit ope rations, TMJ1I interrupt requests from the T MJ-1 wi ll be
valid.
Bit 4
8/16 Description
0 Makes the TMJ-1 and TMJ-2 operate separately ( I nit ial value)
1 Makes the TMJ-1 and TMJ-2 operate altogether as 16-bit timer/counter
Bits 3 and 2Selecting the Inputti ng Clock for the TMJ-2 (PS21 and PS20): These bits,
together wit h the PS22 bit i n the t imer J control re gi ster (TMJC), work to select the cl ock for the
TMJ-2. When the external clock is selected, the counted edge (rising or falling) can also be
selected. For details, refer to section 13.2.2, Timer J Control Register (TMJC).
Bit 1TMJ-2 Toggle Flag (TG L): This flag indicates the toggled status of the underflowing
with the TMJ-2. Reading onl y is workable.
It will be cleared t o 0 under the low power c onsumption mode.
Bit 1
TGL Description
0 The toggle output of the TMJ-2 is 0 (Initial value)
1 The toggle output of the TMJ-2 is 1
Rev. 1.0, 02/00, page 266 of 1141
Bit 0Switching Over Between Timer Output/Remote Controlling Output (T/R): This bi t
works to select if using the timer output s from the TMJ-1 a s the output signal through the TMO
pin or if using the toggle outputs (remote controlled transmission data) from the TMJ-2 as the
output signal through the TMO pin.
Bit 0
T/R Description
0 Timer outputs from the TMJ-1 (Init ial value)
1 Toggle outputs from the TMJ-2 (remote cont rolled transmission data)
Selecting the Operation Mode
The operating mode of ti mer J is determined by bit 3 (EXN) of the time r J c ont rol register (TMJC)
and bits 4 (8/16) a nd 0 (T/R) of t he timer mode register J (TMJ).
TMJC TMJ
Bit 3 Bit 4 Bit 0
EXN 8/16 T/R Description
0 0 0 8-bit timer + 16-bit timer
1 Remote-controlling mode ( TMJ-2 works as a 16-bit t imer)
1 * 24-bit timer
1 0 0 Two 8-bit timers (Init ial value)
1 Remote-controlling mode ( TMJ-2 works as an 8-bit timer)
1 * 16-bit timer
Note: *Don’t care
Writing to the TMJ i n timer mode initializes the counte rs (TCJ a nd TCK) (H' FF). Consequently,
write to the reloading registers (TLJ an TLK) after finishing settings with the TMJ.
Under the remote contr oll ing mode, althoug h the TLJ and the TLK will not be initial iz ed even
when writing is made into the TMJ, follow the sequence listed below when starting a remote
controlling operation:
1. Make setting to the remote controlling mode with the TMJ.
2. Wri te the d ata into the TLJ and TLK.
3. Start the rem ote cont rolled operation by use of the TMJ. (ST bit = 1).
Even unde r 16-bit operations, TMJ1I interrupt requests from the TMJ-1 wil l be va lid.
Rev. 1.0, 02/00, page 267 of 1141
13. 2. 2 T i m er J Contro l Regi ster (TMJC)
01
0
2
0
R/W
3PS22EXN
R/W
R/W
4
0
R/W
5
0
6
0
7
R/WR/W
MON1
R/W
BUZZ0
0
R/W
BUZZ1 MON0 TMJ2IE TMJ1IE
11
Bit :
Initial value :
R/W :
The timer J control register (TMJC) works to select the buzzer output frequency and to control
permission/ prohibition of interrupts.
The TMJC is an 8-bit read/write register.
Whe n r es et, the TM JC is initialized to H '0 9.
Bits 7 and 6Selecting the Buzzer Output (BUZZ1 or BUZZ0): This bi t works to select i f
using the buzzer output s as the output signal t hrough the BUZZ pin or i f using the monitor signals
as the output signal through the BUZZ pi n.
Wh en set ti ng i s made to the moni tor sign al s, c hoos e the mon ito r sig nal us ing th e MON1 bit and
MON0 bit.
Bit 7 Bit 6
BUZZ1 BUZZ0 Description Frequency when
φ = 10 M Hz
0φ/ 4096 (Initial value) 2.44 kHz01φ/ 8192 1. 22 kHz
0 Works to output monito r signals11 W orks to output BUZZ signals from timer J
Rev. 1.0, 02/00, page 268 of 1141
Bits 5 and 4Selecting the Monitor Signals (MON1 or MON0): These bit s work to select the
type of signals being output through t he BUZZ pi n for monitoring purpose. The se settings a re
valid only when the BUZZ 1 and BUZZ0 bits are being set to 10.
When PB-CTL or REC-CTL is chosen, signal duties will be output as they are.
In case of DVCTL signals, signals from the CTL dividi ng circuit will be toggled before being
output. Signal waveforms divide d by the CT L dividing ci rc uit int o n-divisions will furthe r be
divided into halves. (Nam ely, 2n divisions, 50% duty waveform).
In case of TCA7, Bit 7 of the counter of the Timer A will be output. (50% duty)
When prescal er W is being used with the Timer A, 1 H z outpu ts are ava il able.
Bit 5 Bit 4
MON1 MON0 Description
0 PB or REC-CTL (Init ia l value)0
1DVCTL
1 * Outputs TCA7
Note: * Don't care.
Bit 3Expansion Function Control Bit (EXN): This bit enables or disables the expansion
function of TMJ-2. W hen the expansion func tion is enabled, TMJ-2 works as a 16-bi t counte r, and
further input clock sources and types can be selected.
Bit 3
EXN Description
0 Enables the TMJ-2 expansion funct ion
1 Disables the TMJ-2 expansion function (Init ial value)
Bit 2Enabling Interrupt of the TM J2I (TM J2IE): Thi s bit works to permit/prohibit
occu rrence of T MJ2I interrupt of the TMJS in 1-set of the TMJ2I.
Bit 2
TMJ2IE Description
0 Prohibits occurrence of TMJ2I interrupt (I nitial value)
1 Permits occurrence of TMJ2I int errupt
Rev. 1.0, 02/00, page 269 of 1141
Bit 1Enabling Interrupt of the TM J1I (TM J1IE): Thi s bit works to permit/prohibit
occu rrence of T MJ1I interrupt of the TMJS in 1-set of the TMJ1I.
Bit 1
TMJ1IE Description
0 Prohibits occurrence of TMJ1I interrupt (I nitial value)
1 Permits occurrence of TMJ1I int errupt
Bit 0TMJ-2 Input Clock Se l ection (PS22): This bit, together with the PS21 and PS20 bits of
the timer mode register J (TMJ), selects the TMJ-2 input clock source.
TMJC TMJ
Bit 3 Bit 0 Bit 3 Bit 2
EXN PS22 PS21 PS20 Description
0100PSS; count at φ/128
1 PSS; count at φ/64
1 0 Count at TM J-1 underflow
1 External clock (IRQ2 ); count at rising or falling edge*1
0 * * Reserved
1100PSS; count at φ/16384 (Initial value)
1 PSS; count at φ/2048
1 0 Count at TM J-1 underflow
1 External clock (IRQ2 ); count at rising or falling edge*1
0 0 0 PSS; count at φ/1024
1 PSS; φ/1024
1 0 Count at TM J-1 underflow
1 External clock (IRQ2 ); count at rising or falling edge*1
Note: * Don't care
1. The external clock edge can be selected by the IRQ edge select register (IEGR). For
details, refer to sect ion 6.2.4, IRQ Edge Select Registers (IEGR).
Rev. 1.0, 02/00, page 270 of 1141
13. 2. 3 T i m er J Status Re gister (TM J S)
012345
——————
——————
6
0
7
R/(W)*
TMJ1I
0
R/(W)*
TMJ2I
111111
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
The timer J status register (TMJS) works to indicate issuance of th e interrupt re que st of ti mer J.
The TMJS is an 8-bit read/ write register. W h en reset, the TMJS is initialized to H'3F.
Bit 7TMJ2I Interr upt Reque sting Flag (TMJ2I)
Bit 7
TMJ2I Description
0[Clearing condit ions] (Initial value)
When 0 is written after reading 1
1 [Setting condition s]
When the TMJ-2 underflows
Bit 6TMJ1I Interrupt Requesting Fl ag (TM J1I): This is the TMJ1I interrupt requesting flag.
This flag is set out when the TMJ-1 underflows.
TMJ1I i nterrupt requests will also be ma de under a 16-bit operation.
Bit 6
TMJ1I Description
0[Clearing condit ions] (Initial value)
When 0 is written after reading 1
1 [Setting condition s]
When the TMJ-1 underflows
Bits 5 to 0Reserved: Thes e bits canno t be mo d ified an d are always r ead as 1.
Rev. 1.0, 02/00, page 271 of 1141
13.2.4 Ti mer Counter J (TCJ)
0
1
1
1
R
2
1
R
3
1
4
1
R
5
1
6
1
7
RRR
TDR15
R
TDR16
1
R
TDR17 TDR14 TDR13 TDR12 TDR11 TDR10
Bit :
Initial value :
R/W :
The timer count er J (TCJ) is an 8-bit readable down-counter which works to count down by t he
internal clock inputs or externa l clock input s. The inputting cl ock can be selected by t he PS11 and
PS10 bits of the TMJ. TCJ values can be readout always. Nonetheless, when the EXN bit in
TMJC a nd the 8/ 16 bit i n TMJ are both set to 1, (means when setting is made to 16-bit operation),
reading is possible under the word command onl y.
At this time, the TCK of the TMJ-2 can be read by the upper 8 bits and the TCJ can be read by the
lower 8 bits. When the EXN bit in TMJC is 0, TCJ can be read only in byte units.
When the TCJ underflows (H'00 → Reloading va lue), regardless of the operation mode setting of
the 8 / 16 bit, the TMJ1I bit of the TMJS will be set to 1 bit. The TCJ and TLJ are be ing allocat e d
to the same address.
When reset, the TCJ is initialized to H'FF.
13.2.5 Timer Counter K (TCK)
0
1
1
1
R
2
1
R
3
1
4
1
R
5
1
6
1
7
RRR
TDR25
R
TDR26
1
R
TDR27 TDR24 TDR23 TDR22 TDR21 TDR20
Bit :
Initial value :
R/W :
The timer count er K (TCK) is an 8-bi t or a 16-bit re adable down-counte r which works t o count
down by the internal clock inputs or external clock inputs. The inputting clock can be selected by
the EXN and PS2 bits of the TMIC, and the PS21 and PS20 bits of the TMJ. TCK values can be
readout always. Nonetheless, when the EXN bit in TMJC and the 8/16 bit in TMJ are both set to
1, (means when setting is made to 16-bit ope ration), rea ding is possible under the word command
only.
At this time, the TCK can be read by the upper 8 bits and the TCJ of the TMJ-1 can be read by the
lower 8 bi ts. Whe n the EXN bit in T MJC is 0, T CK works as a 16-bit count e r and can be read only
in word units.
When the TCK unde rflows (H'00 → Rel oa ding valu e ), the TMJ2 I bi t of the TMJS wil l be set to 1.
The TCK and TL K are bei ng allocated to the same address.
When reset, the TCK is initialized to H'FF.
Rev. 1.0, 02/00, page 272 of 1141
13.2.6 Ti mer Load Register J (TLJ)
0
1
1
1
W
2
1
W
3
1
4
1
W
5
1
6
1
7
WWW
TLR15
W
TLR16
1
W
TLR17 TLR14 TLR13 TLR12 TLR11 TLR10
Bit :
Initial value :
R/W :
The timer loa d register J (TLJ) is an 8-bit write onl y register whi c h works to set the reloading
value of the TC J .
When the reloading value is set to the TLJ, the value will be simultaneously loaded to the TCJ and
the TCJ starts counting down from the set value. Also, during an auto reloading operation, when
the TCJ underflows, t he value of the TLJ will be loaded to the T CJ. Consequently, t he
underflowing cycle can be set within the range of 1 to 256 i nput clocks. Nonet heless, when the
EXN bi t in TMJC and the 8/16 bit in TMJ are both set to 1, (means when setting i s made to 16-bit
operation), writing is possible unde r the word command only.
At this time, the upper 8 bits can be written into the TLK of the TMJ-2 and the lower 8 bits can be
written into the TLJ. When the EXN bit in TMJC is 0, TLJ can be written to only in byte units; an
8-bit reload value is written to TLJ.
The TLJ and TCJ are being allocated to the same address.
When reset, the TLJ is initialized to H'FF.
13.2.7 Timer Load Re gister K (TLK)
0
1
1
1
W
2
1
W
3
1
4
1
W
5
1
6
1
7
WWW
TLR25
W
TLR26
1
W
TLR27 TLR24 TLR23 TLR22 TLR21 TLR20
Bit :
Initial value :
R/W :
The timer loa d register K (TLK) is an 8-bit or a 16-bit write onl y registe r which works to set t he
reloading value of the TCK.
When the reloading value is set to the TLK, the value will be simultaneously loaded to the TCK
and the TCK starts counting down from the set value . Also, during an au to reload ing operation,
when the TCK underflows, the value of the TLK will be loaded to the TCK. Consequently, the
underflowing cycle can be set within the range of 1 to 256 i nput clocks. Nonet heless, when the
EXN bi t in TMJC and the 8/16 bit in TMJ are both set to 1, (means when setting i s made to 16-bit
operation), writing is possible unde r the word command only. At this ti me, the upper 8 bit s can be
written into the TLK and the lower 8 bits can be written into the TLJ of the TMJ-1. When the
EXN bit in TMJC is 0, TLK can be written to only in word units; a 16-bit reload value is written
to TLK. The TLK and TC K are b eing al lo cated to th e s ame addr es s.
When reset, the TLK is initialized to H'FF.
Rev. 1.0, 02/00, page 273 of 1141
13. 2. 8 Modul e Sto p Contr ol Regi ster (MSTPCR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Initial value :
R/W :
Bit :
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP13 bit is set to 1, timer J stops its operation at the ending point of the bus cycle to
shift to t he modul e stop mode. For more information, se e section 4.5, Module Stop Mode.
When rese t, the MSTPCR is initia l iz ed to H'FFFF.
Bit 5Module Stop (MSTP13): This bit works t o designate the module stop m ode for the Timer
J.
MSTPCRH
Bit 5
MSTP13 Description
0 Cancels the module stop mode of timer J
1 Sets the module stop m ode of timer J (Initial value)
Rev. 1.0, 02/00, page 274 of 1141
13.3 Operation
13.3.1 8-bit Re l oad Timer (TMJ-1)
The TMJ-1 i s an 8-bit re l oad timer. As t he cloc k source, dividing clock or edge signals through
the
,54
pin are being used. By selecting the e dge signal s through the
,54
pin, it can also be
used as an event counter. While it is working as an event count er, its reload ing func tio n is
workable simultaneously. When data are wri tten into the rel oading re gister, these data will be
written into the counters (e vent counter, timer counter) simultaneously. Also, when the eve nt
counter underfl ow s, the even t counter valu e is reset to the reload reg ister valu e, and a TMJ1I
interrupt re quest occurs. Every time the count er underflows, t he output level toggles. This output
can be used as a buzzer or the carrier frequency at remote-controlled transmission by selecting an
appropriate divide d clock.
The TMJ-1 and TMJ-2, in combinat ion , can be used as a 16-bit or a 24-bit reload timer .
Nonetheless , when they are being used , in combinat ion , as a 16-bit timer , word command only is
valid and the TCK works as the down counte r for the uppe r 8 bits and the TCJ works as t he down
counter for the lower 8 bits, means a rel oading re gister of total 16 bit s.
When data are writ ten into a 16-bit reloading regi ster, the same dat a will be written i nto the 16-bit
down counter .
Also, when the 16-bit down counte r underflow signals, the data of t he 16-bit reloading register
will be reloaded into the down counter. When the EXN bit of TMJC is set to 0, the expansion
function of TMJ-2 is enabled, that i s, TMJ-2 works as a 16-bit reloading ti mer, and i t can be
connected t o TMJ-1 to be a 24-bit reloading timer. In this ca se, TCK works as the upper 16-bit
part and TCJ works as the l ower 8-bit pa rt of a 24-bit down counter, and TLK works as the uppe r
16-bit pa rt and T L J works as the l ower 8-bit part of a 24-bit reloading register.
Even when they are making a 16-bit or a 24-bit ope ration, the TMJ1I interrupt re quests of the
TMJ-1 a nd BUZZER out puts are effec tive. In case the se functions a re not ne cessary, make them
invalid by programming.
The TMJ-1 and TMJ-2, in combinat ion , can be used for remot e control led data trans missio n.
Regarding the remote controlled data transmission, see section 13.3.3, Remote Controlled Data
Transmission.
13.3.2 8-bit Re l oad Timer (TMJ-2)
The TMJ-2 i s an 8-bit or a 16-bit down-counting reload timer. As the clock source, divi ding
clock, edge signa ls through the
,54
pin or the underflow signals from the TMJ-1 are being used.
By selecting the e dge signal s through the
,54
pin, it can also be used as an event counter. While
it is working as an event counter, its reloading function is workable simultaneously.
When data are written into the reloading register, these data will be written into the counter
simultaneously. Also, whe n the counter underflows, reloadi ng will be made to the data counter of
the reloading register.
When the counter unde rflows, TMJ2I int errup t requ ests will be issued.
The TMJ-2 and TMJ-1, in combinat ion , can be used as a 16-bit or a 24-bit reload timer . For more
Rev. 1.0, 02/00, page 275 of 1141
information on the 16-bit or 24-bit reload timer, see section 13. 3.1, 8-bit Re l oad Ti mer (TMJ-1).
The TMJ -2 a nd TM J-1, in combin ation , can be o p erated b y re mote co ntrol led d ata tran smiss io n.
Regarding the remote controlled data transmission, see section 13.3.3, Remote Controlled Data
Transmission.
13.3.3 Remote Controlled Data Transmi ssion
The Timer J is capable of making remote controlled data transmission. The carrier frequencies for
the remote cont rolled data transmission can be gene rated by the T MJ-1 and the burst width
duration and the spac e width duration can be setup by the TMJ-2.
The data having been written into the reloading register TMJ-1 and into the burst/space duration
register (TLK) of the TMJ-2 will be loaded to the counter at the same time as the remote
controlled data transmission starts. (Remote controlled data transmission starting bit (ST) ← 1)
While remote controlled data transmission is being made, t he contents of the burst/space duration
register will be loa ded to t he counter only while re l oading i s being made by underflow signals.
Even when a writing is made to the burst/space duration register while remote controlled data
transmission i s being made, reloading operation will not be made unt il an unde rflow signal is
issued. T he TMJ-2 issues T MJ2I int errupt re quests by the unde rfl ow signa ls. The TMJ-1
performs normal reloading operation (including t he TMJ1I interrupt requests).
Figure 13. 2 shows the output wave form for the remote control led dat a transmission function.
Whe n a shift to th e low power cons umptio n mode is effected w h ile remote con trolled d ata
transmission is being made, the ST bit will be cleared to 0. When resuming the remote controlled
data transmissio n aft er returni ng to th e active mod e, write 1.
Burst width Space width Burst width
TMJ-2 toggle output
= 1 TMJ-2 toggle output
= 0 TMJ-2 toggle
output = 1
Setting the
space width Setting the
burst width Setting the
space width
ST bit ← 1 Underflow Underflow Underflow
TMJ-1 can generate
the carrier frequencies
Remote controlled data
transmission outputs
Setting the remote
controlled mode
Setting the burst width
Figure 13.2 Re mote Controlle d Data Transmission Output Waveform
Rev. 1.0, 02/00, page 276 of 1141
TMJ-1
UDF
TMO
(BUZZ)
TMJ-2
UDF
REMOout
TMO
Remote controlled data
transmission output
Figure 13.3 Timer Output Timing
Rev. 1.0, 02/00, page 277 of 1141
When the Timer J is set to the remote controlled operation mode, since the start bit (ST) is being
set or cleared in synchronization with the input ting clock to the TMJ-2, a del a y upt o a cyc le of the
inputting cl ock at the maximum oc curs, namely, after t he ST bit has been set to 1 until the remote
controlled data transmission starts. Consequent ly, when the TLK is updat ed during the period
after setting the ST bit to 1 until the next cycle of the inputting clock comes, the initial burst width
will be cha nged as shown i n figure 13.4.
Therefore, when making remote controlled data transmission, determine I/O of the TGL bit at the
time of t he first burst widt h control opera tion without fai l. (Or, set the space widt h to the TLK
after waiting for a cycle of the inputting clock.)
After that, operations can be continued by interrupts.
Similarly, pay attention to t he control works when ending remote cont rolled data tra nsmission.
Example:
1) Set the burst width with t he TLK.
2) ST bi t ← 1.
3) Ex ecute th e pr ocedur e 4) if th e TG L flag = 1 .
4) Set the space width with the TLK under the status where the TGL flag = 1.
5) Make TMJ-2 interrupt.
6) Set the burst width with t he TLK.
:
n) After ma king TMJ-2 interrupt, make setting of the ST ← 0 under the status where the TGL
flag = 0.
The period during which the
space width settig can be
made. (S)
Delay
Interrupt
Interrupt
TLK setting
(Burst width)
(B)
Burst width
according to (B) Space width
according to (S)
Stopping the remote controlled
data transmission
TGL flag
Inputting clock
to the TMJ-2
ST ← 0
Delay
ST ← 1
Remote controlled data
transmission starts here.
If an updating is made with the
TLK during this period, the burst
width will be changed.
Figure 13.4 Controls of the Remote Controlled Data Transmission
Rev. 1.0, 02/00, page 278 of 1141
13.3.4 TMJ-2 Expansion F unction
The TMJ-2 expansion function is enabled by setting the EXN bit in the timer J control register
(TMJC) t o 0. This function makes TMJ-2, which usually works as an 8-bit counter, work as a 16-
bit counter. When this function is selected, timer counter K (TCK) and timer load register K
(T L K) must be accesse d as foll ows:
TCK Re ad: To read TCK, use t he word-length MOV instruction. In this case, the upper 8 bit s of
TCK are read out to the lower byte of the on-chip data bus, and the lower 8 bits are read out to the
upper byte of t he on-chip data bus. That is, when MOV.W @TCK, Rn is executed, the lower 8
bits of TCK are stored in RnH and the upper 8 bits are stored in RnL.
TLK Write: T o write to TLK, use the word-length MOV instruction. In this case, the upper 8 bits
are written to the lower byte of TLK, and the lower 8 bits are written to the upper byte of TLK.
That is, when MOV.W Rn, @TLK is executed, the RnH data is written to the lower byte of TLK,
and the RnL data is written to the upper byte of TLK.
Rev. 1.0, 02/00, page 279 of 1141
Section 14 Timer L
14.1 Overview
Timer A is an 8-bit up/ down c ounter using the cont rol pulses or the CFG division signals as the
clock source.
14.1.1 Features
Features of timer L ar e as fol lo w s :
• Two types of internal clocks (φ/128 and φ/ 64), DVCFG2 (CFG divisi on signa l 2), PB a nd
REC-CTL (control pulse s) are available for your se lection.
— When the PB-CTL is not available, such as when reproducing un-recorded ta pes, tape
count can be made by the DVCFG2.
— Selection of the l eading edge or the t railing edge is workable with t he CTL pulse counting.
• Interrupts occur when the counter ove rflows or underflows and at oc currences of compa re
match clear.
• Capable to switch over betwee n the up-c ounting a nd down-counting func tions with t he
counter.
Rev. 1.0, 02/00, page 280 of 1141
14.1.2 Block Diagram
Figure 14. 1 shows a bloc k diagram of timer L.
[Legend]
Internal data bus
DVCFG2 : Division signal 2 of the CFG
PB and REC-CTL : Control pluses necessary when making
reproduction and storage
LMR : Timer L mode register
LTC : Linear time counter
RCR : Reload/compare match register
OVF : Overflow
UDF : Underflow
LMR
LTC
RCR
Comparator
Write
OVF/UDF
Reloading
Match clear
Interrupt request
Interrupting
circuit
DVCFG2
PB and
REC-CTL
INTERNAL CLOCK
φ/128
φ/64
Read
Figure 14.1 Block Diagr am of Timer L
Rev. 1.0, 02/00, page 281 of 1141
14.1.3 Regi ster Configur ati on
Table 14.1 shows the register configuration of timer L. The linear time counter (LTC) and the
reload compare patch registe r (RCR) are being allocated to the sam e address.
Reading or writing determines the accessing register.
Table 14. 1 Register Configurati on
Name Abbrev. R/W Size I nitial Value Address*
Timer L m ode regist er LM R R/W Byte H'30 H'D112
Linear time counter LTC R Byte H'00 H'D113
Reload/compare m atch
register RCR W Byte H'00 H'D113
Note: * Lower 16 bits of the address.
Rev. 1.0, 02/00, page 282 of 1141
14.2 Regi ster Descri pt i on s
14.2.1 Timer L Mode Re gister (LMR)
0
0
1
0
R/W
2
0
R/W
3
0
4
1
5
——
——
1
6
0
7
R/WR/WR/W
LMIE
0
R /(W)*
LMIF LMR3 LMR2 LMR1 LMR0
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
The timer L m ode regi ster A (L MR) i s an 8-bit read/write re gi ster which works to control the
interrupts, t o select betwe en up-count ing and down-counting and to select the c l ock source. When
reset, the LMR is initialized to H'30.
Bit 7Timer L Inter r upt Reque sting Fl ag (LMIF): This is the Timer L interrup t requ est ing
flag. It indicates occurrence of overflow or underflow of the LTC or occ urrence of compa re
match clear.
Bit 7
LMIF Description
0[Clearing condit ions] (Initial value)
When 0 is written after reading 1
1 [Setting condition s]
When the LTC overflows, underflows or when compare match clear has occurred
Bit 6Enabling Interrupt of the Ti mer L (LM IE): Thi s bit works to permit/prohi bit
occurrence of interrupt of timer L when the LTC overflows, underflows or whe n compare ma tch
clear has occurred.
Bit 6
LMIE Description
0 Prohibits occurrence of interrupt of Timer L (Init ial value)
1 Perm its occurrence of interr upt of Timer L
Bits 5 and 4Reserved: These bits cannot be modified and are always read as 1.
Bit 3Up-Count / Do wn- Count Contr ol (LMR3 ): This bit is for selection if timer L is to be
controlled to the up-counting func tion or down-counting function.
Rev. 1.0, 02/00, page 283 of 1141
1. When Controlled to the Up-Count ing Func tion
When any other values than H'00 are input to the RCR, the LTC will be cleared to H'00
before starting counting up. When the LTC value and the RCR value match, the LTC will
be cleared to H'00. Also, interrupt requests will be issued by the m atch signal. (Compare
patch cle a r function)
When H' 00 is set to the RCR, the counter ma ke s 8-bit interval timer operation to i ssue a
interrupt re quest whe n overflowing occurs. (Interval ti mer function)
2. When Controlled to the Down-Counti ng Function
When a value is set to the RCR, the set value is reloaded to the LTC and counting down
starts from that value. When the LTC underflows, the value of the RCR will be reloaded to
the LTC. Also, when the L TC underfl ows, a interrupt request will be issued. (Auto reload
timer function)
Bit 3
LMR3 Description
0 Contr olling to the up-count ing funct ion (Initial value)
1 Contr olling to the down-counting function
Bits 2 to 0Clock Selection (LMR2 to LMR0)
The bits LMR2 to LMR0 work to select the clock to input to timer L. Selection of the leading
edge or the t railing edge is workable for counting by the PB and the RE C-CTL.
Bit 2 Bit 1 Bit 0
R2 LMR1 LMR0 Description
0Counts at the rising edge of the PB and REC-CTL
(Init ial value)
0
1 Counts at the falling edge of the PB and REC-CTL
0
1 * Counts the DVCFG2
0 * Counts at φ/128 of the internal clock1
1 * Counts at φ/64 of the internal clock
Note: * Don't care.
Rev. 1.0, 02/00, page 284 of 1141
14.2.2 Li near Time Counter (LTC)
0
0
1
0
R
2
0
3
0
456
0
7
RRRR
LTC6
0
R
LTC5
0
R
LTC4
0
R
LTC7 LTC3 LTC2 LTC1 LTC0
Bit :
Initial value :
R/W :
The linear time counter (LTC) is a readable 8-bit up/down-counter. The inputting clock can be
selected by th e LMR2 to LMR0 b its of the LM R .
When reset, the LTC is initialized to H' 00.
14. 2. 3 Rel oa d/ Compare Match Regi ster ( RCR)
0
0
1
0
W
2
0
3
0
456
0
7
WWWW
RCR6
0
W
RCR5
0
W
RCR4
0
W
RCR7 RCR3 RCR2 RCR1 RCR0
Bit :
Initial value :
R/W :
The reloa d/compare matc h re gi ster (RCR) is an 8-bit write only register.
When timer L i s being cont rolled to the up-counti ng function, when a compare match val ue is set
to the RCR, the L TC will be cleared at the same time and t he LTC wi ll then start counti ng up from
the initial value (H'00).
While, when the Timer L is being controlled to the down-counting function, when a reloading
value is set to the RCR, the same value will be loaded to the LTC at the same time and the LTC
will then start counting up from said value. Also, when the LTC underflows, the value of the RCR
will be r eloaded to the LTC.
When reset, the RCR is initialized to H'00.
Rev. 1.0, 02/00, page 285 of 1141
14. 2. 4 Modul e Sto p Contr ol Regi ster (MSTP CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP12 bit is set to 1, timer L stops its operation at the ending point of the bus cycle to
shift to t he modul e stop mode. For more information, se e section 4.5, Module Stop Mode.
When rese t, the MSTPCR is initia l iz ed to H'FFFF.
Bit 4Module Stop (MSTP12): This bit works t o designate the module stop m ode for timer L.
MSTPCRH
Bit 4
MSTP12 Description
0 Cancels the module stop mode of timer L
1 Sets the module stop m ode of timer L (Initial value)
Rev. 1.0, 02/00, page 286 of 1141
14.3 Operation
Timer L is an 8-bit up/down counter.
The inputting clock for Timer L can be selected by the LMR2 to LMR0 bits of the LMR from the
choices of the internal clock (φ/128 and φ/64), DVCDG2, PB and REC-CTL.
Timer L is provided wi th three diffe rent types of operation m odes, nam ely, the c ompare match
clear mode when c ontrolled to the up-counting func tion, the a uto rel oa ding mode when controlled
to the down- counting func tion and the int erval timer mode.
Respective operation modes and operation methods will be explained below.
14.3.1 Compare Match Clear Oper ation
When the LMR3 bit of t he LMR is cleared to 0, timer L will be c ontrolled to the up-counting
function.
When any other values than H'00 are written into the RCR, the LTC will be cleared to H'00
simultaneously before starting counting up.
Figure 14. 2 shows RCR wri t ing and LTC clearing timing. When the LTC val ue and the RCR
value match (compare match), the LTC readings will be cleared to H'00 to resume counting from
H'00.
Figure 14. 3 indicated on the next page shows the compare match clear timing.
RCR
LTC
φ
Write signal
1 state
N
H' 00
Figure 14.2 RCR Writing and LTC Clearing Ti ming Chart
Rev. 1.0, 02/00, page 287 of 1141
LTC
RCR
N H' 00N-1
N
Interrupt
request
Count-up
signal
Compare match
clear signal
φ
PB-CTL
Figure 14.3 Compare Match Clearing Timing Chart
(In case the rising edge of the PB-CTL is selected)
Rev. 1.0, 02/00, page 289 of 1141
Section 15 Timer R
15.1 Overview
Timer R consists of triple 8-bit down-counters. It carries VCR mode identification function and
slow tracking function in addition to the reloading function and event counter function.
15.1.1 Features
The Timer R consists of t riple 8-bit re loading timers. By combining the funct i ons of three units of
reloading timers/counters and by combining three units of timers, it can be used for the following
applications:
• Applications ma king use of the functions of three units of reloading t imers.
• For identification of the VCR m ode.
• For reel controls.
• Fo r accelera tio n and br aking of th e capstan motor when be ing ap plied to in termittent
movements.
• Slow tracking mono-m ulti applications.
15.1.2 Block Diagram
Timer R c onsists of three units of reload t imer counte rs, namely, two units of reload timer
counters e quipped wit h capturing function (TMRU-1 and TMRU-2) and a unit of reload timer
counter (TMRU-3).
Figure 15.1 is a block diagra m of timer R.
Rev. 1.0, 02/00, page 290 of 1141
Notes:
Internal bus
Internal bus
Clock sources
DVCTL
CFG↑
Clock
selection
(2 bits)
Reloading register
(8 bits)
Down-counter
(8 bits)
Capture register
(8 bits)
TMRI2
Interrupt request
TMRI1
Interrupt
request
TMRI3
Interrupt
request
TMRU-1
TMRCP1 *2
Under–
flow
TMRU-3 Underflow
*1
TMRL3
PS31,30
External signals
IRQ3
φ /1024
φ /2048
φ /4096
Clock source
φ /64
φ /128
φ /256
Clock sources
φ /4
φ /256
φ /512
Down-counter
(8 bits)
Latch
clock
selection
Clock
selection
(2 bits)
Resetting
Available/
Not
available
CP/
SLM
SLW
CAPF
Capture register
(8 bits)
Down-counter
(8 bits)
Reloading register
(8 bits)
Acceleration/
braking
Reloading
Available/
not
available
Reloading
clock
selection
Reloading register
(8 bits)
RLD/
CAP
Clock
selection
(2 bits)
CPS
LAT PS21,20
CLR2
Res
Res
TMRCP2
Under–
flowTMRU-2 CFG mask F/F
R
SQ
R
S
Q
Acceleration
braking
AC/BR
TMRL2
RLD
RLCK
TMRL1PS11,10
Interrupting circuit
1. When the DVCTL is being used as the clock source, reloading will be made when the counter underflows and when
the dividing clock is being used as the clock source, reloading will be made by the DVCTL.
2. When the LAT bit = 0, the capture signal against the TMRU-1 will not be output.
Figure 15.1 Block Diagr am of Timer R
Rev. 1.0, 02/00, page 291 of 1141
15.1.3 P i n Confi guration
Table 15. 1 shows the pi n configuration of timer R.
Table 15. 1 Pin Configuration
Name Abbrev. I/O Function
Input capture inputting pin
,54
Input Input capture inputting for the Timer R
15.1.4 Register Configurati on
Table 15.2 shows the register configuration of timer R.
Table 15. 2 Register Configurati on
Name Abbrev. R/ W Size I nit i al Value Address
Ti me r R mode reg i s t e r 1 T MRM1 R /W Byte H'0 0 H' D 1 1 8
Ti me r R mode reg i s t e r 2 T MRM2 R /W Byte H'0 0 H' D 1 1 9
Timer R control/status
register TMRCS R/W Byte H'03 H'D11F
Timer R captur e register 1 TMRCP1 R Byte H'FF H'D11 A
Timer R captur e register 2 TMRCP2 R Byte H'FF H'D11 B
Timer R load register 1 TM RL1 W Byte H'FF H'D11C
Timer R load register 2 TM RL2 W Byte H'FF H'D11D
Timer R load register 3 TM RL3 W Byte H'FF H'D11E
Note: M emor ies of respective r egister s will be preserved ev en under t he low power c onsumption
mod e. Nonethele ss, t he CAPF flag and SLW flag of the TMRM2 will be cleared to 0.
Rev. 1.0, 02/00, page 292 of 1141
15.2 Regi ster Descri pt i on s
15. 2. 1 T i m er R Mode Register 1 (TMRM1)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/W
RLD
R/W
AC/BR
0
R/W
CLR2 RLCK PS21 PS20 RLD/CAP CPS
Bit :
Initial value :
R/W :
The timer R mode regist e r 1 (T MRM1) works to cont rol the acceleration and braking processes
and to select the inputting clo ck for th e TMRU-2. This is an 8-bi t read/write register .
When reset, the TMRM1 is initialized to H'00.
Bit 7Selecting Clearing/Not Clearing of TMRU-2 (CLR2): This bit is used for selecting if
the TMRU-2 counter reading is to be cleared or not as it is captured.
Bit 7
CLR2 Description
0 TMRU-2 count er reading is not to be cleared as soon as it is captur ed. ( Initial value)
1 TMRU-2 count er reading is to be cleared as soon as it is captured
Bit 6Accel era t ion/ Bra ki ng Proce ssi ng (AC/BR) : This bi t works to control occ urrences of
interrupt re quests t o detect c ompletion of acceleration or braki ng whil e the capstan mot or is
making intermittent revolutions.
For more i nformation, see section 15. 3.6, Ac celeration and Braking Processes of the Ca pstan
Motor.
Bit 6
AC/BR Description
0 Braking (Init ial value)
1 Acceleration
Rev. 1.0, 02/00, page 293 of 1141
Bit 5Using / Not Usi ng the TMRU-2 for Reloa di ng (RLD) : This bit is used for selecting if the
TMRU-2 reloa d func tion is t o be turned on or not.
Bit 5
RLD Description
0 Not using t he TMRU-2 as t he reload timer (Init ial value)
1 Using the TMRU-2 as the r eload timer
Bit 4Reloading Timing for the TMRU-2 (RLCK): This bit works to select if the TMRU-2 is
reloading by the CFG or by underfl owing of the TMRU-2 c ounter. This choice is valid only whe n
the bit 5 (RLD) is being set to 1.
Bit 4
RLCK Description
0 Reloading at the rising edge of t he CFG ( I nitial value)
1 Reloading by underflowing of the TMRU-2
Bits 3 and 2Cloc k Source for the TMRU-2 (PS21 and PS20): These bits work to select the
inputting clock to the TMRU-2 .
Bit 3 Bit 2
PS21 PS20 Description
0 Counting by underflowing of the TMRU-1 (Init ial value)0
1 Counting by t he PSS, φ/256
0 Counting by t he PSS, φ/1281
1 Counting by t he PSS, φ/64
Bit 1Operation Mode of the TMRU-1 (RLD/CAP ): This bi t works to select if the operation
mode of the TMRU-1 is reload timer mode or capture timer mode.
Under the capture t imer mode, reloading operation will not be made. Also, the counte r reading
will be cleared as soon as capture has been made.
Bit 1
RLD/CAP Description
0 The TMRU-1 works as t he reloading timer (Initial value)
1 The TMR U-1 works a s the capture timer
Rev. 1.0, 02/00, page 294 of 1141
Bit 0Capture Signals of the TMRU-1 (CPS): In combination with the LAT bit (Bit 7) of the
TMR2, this bit works to select the capture signals of the TMRU-1. Thi s bit bec omes val id when
the LAT bit is being set to 1. It will also become valid when the RLD/CAP bit (Bit 1) is being set
to 1. Nonetheless, it will be invalid when the RLD/CAP bit (Bit 1) is being set to 0.
Bit 0
CPS Description
0 Capture signals at the r ising edge of the CFG ( I nitial value)
1 Capture signals at the edge of the IRQ3
15. 2. 2 T i m er R Mode Register 2 (TMRM2)
0
0
1
0
R/(W)*
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/(W)*R/WR/W
PS10
R/W
PS11
0
R/W
LAT PS31 PS30 CP/SLM CAPF SLW
Bit :
Initial value :
R/W :
The timer R mode regist e r 2 (T MRM2) is an 8-bit re ad/write regi ster which works to identify the
operation m ode and to control the slow tracking processing.
When reset, the TMRM2 is initialized to H'00.
Note: * T he CAPF bit and the SLW bit, respectively, works to latch the interrupt causes and
writing 0 only is valid. Consequently, when these bits are being set to 1, respective
interrupt re quests wil l not be issued. Therefore, it is necessary to check the se bits
during the course of the interrupt processi ng rout ine to have them clear ed .
Also, priority is given to the set and, when an interrupt cause occur while the a clearing
co mman d (BC LR, MOV, et c. ) is being exec uted, the CAPF bit and the SLW bit will
not be cleared respectively and it thus becomes necessary to pay attention to the
clear ing ti ming.
Rev. 1.0, 02/00, page 295 of 1141
Bit 7Capture Signals of the TMRU-2 (LAT): In combination with the CPS bit (Bit 0) of the
TMRM1, thi s bit works t o select the capture signals of the T MRU-2.
TMRM2 TMRM1
Bit 7 Bit 0
LAT CPS Description
0 * Captures when the TMRU-3 underflows (Init ial value)
0 Captures at the rising edge of the CFG1
1 Captures at the edge of the IRQ 3
Note: * Don't care.
Bits 6 and 5Cloc k Source for the TMRU-1 (PS11 and PS10): These bits work to select the
inputting clock to the TMRU-1 .
Bit 6 Bit 5
PS11 PS10 Description
0 Counting at the r ising edge of the CFG (I nit ial value)0
1 Counting by t he PSS, φ/4
0 Counting by t he PSS, φ/2561
1 Counting by t he PSS, φ/512
Bits 4 and 3Clock Source for the TM RU-3 (PS31 and PS30)
These bi t s work to select the inputting c lock to t he TMRU-3.
Bit 4 Bit 3
PS31 PS30 Description
0Counting at the rising edge of the DVCTL from t he dividing circuit.
(Init ial value)
0
1 Counting by t he PSS, φ/4096
0 Counting by t he PSS, φ/204811 Counting by t he PSS, φ/1024
Rev. 1.0, 02/00, page 296 of 1141
Bit 2Interrupt Causes ( CP/SLM) : This bi t works t o select the interrupt causes for the TMRI3.
Bit 2
CP/SLM Description
0 M akes int errupt request s upon the capt ure signals of the TM RU-2 valid (Initial value)
1 M akes int errupt request s upon ending of the slow tracking mono-multi valid
Bit 1Capture Signa l Flag (CAPF) : This is a flag being set out by the capture signal of the
TMRU-2. Although both rea ding/writing are possibl e, 0 onl y is valid for writing.
Also, priority is being given to the set and, when the capture signal and writing 0 occur
simultaneously, this flag bit remains being set to 1 and the interrupt request will not be issued and
it is necessary to be attentive about this fact.
Wh en the CP/SLM bit (bit 2) is being set to 1, this CAPF bit shou l d alwa y s be set to 0.
Th e CAPF flag is cleared to 0 unde r the low powe r consu mption mode.
Bit 1
CAPF Description
0[Clearing condit ions] (Initial value)
When 0 is written after reading 1
1 [Setting condi tion s]
At occurr ences of the TMRU-2 capture signals while the CP/ SLM bit is set to 0
Bit 0Slow Trac king Mono-multi Flag (SLW): This is a fl ag being set out when the slow
tracking mono- mul ti processing ends . Although both reading /wri tin g are possib le , 0 only is valid
for writing.
Also, priori t y i s being give n to the set and, when e nding of the slow trac king mono-multi
processing and writing 0 occur simultaneously, this flag bit remains being set to 1 and the interrupt
request will not be issued and it is necessary to be attentive about this fact.
When the CP/SLM bit (bit 2) is being set to 0, this SLW bit should al ways be set to 0.
The SL W f lag is cle ared to 0 und er th e low power cons umptio n mo d e.
Bit 0
SLW Description
0[Clearing condit ions] (Initial value)
When 0 is written after reading 1
1 [Setting condi tion s]
When the slow tracking mono-multi processing ends while the CP/SLM bit is set to 1
Rev. 1.0, 02/00, page 297 of 1141
15. 2. 3 T i m er R Control/ St at us Regi ster (TMRCS)
0
1
1——
——
1
2
0
R/(W)*
3
0
4
0
R/(W)*
5
0
6
0
7
R/(W)*R/W
TMRI1E
R/W
TMRI2E
0
R/W
TMRI3E TMRI3 TMRI2 TMRI1
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
The timer R control/status register (TMRCS) works to c ontrol t he interrupts of time r R.
The TMRCS is an 8-bit read/write register. When reset, the TMRCS is initialized to H'03.
Bit 7Enabli ng the TMRI3 Interr upt (TMRI3 E): This bit works to perm it/prohibit occurre nce
of the TMRI3 inte rrupt when an i nterrupt cause being sel ected by the CP/SLM bit of the T MRM2
has occurre d, such a s occ urrences of the TMRU-2 capture signals or when the slow tracking
mono-multi processing ends, and t he TMRI3 has been set to 1.
Bit 7
TMRI3E Description
0 Prohibits occurrences of TM RI3 interrupts (I nit ial value)
1 Permits occurrences of TMRI3 interrupts
Bit 6Enabli ng the TMRI2 Interr upt (TMRI2 E): This bit works to perm it/prohibit occurre nce
of the TMRI2 inte rrupt when the TMRI2 has been set to 1 by issua nce of t he underfl ow signal of
the TMRU-2 or by ending of the slow tracking mono-multi processing.
Bit 6
TMRI2E Description
0 Prohibits occurrences of TM RI2 interrupts (I nit ial value)
1 Permits occurrences of TMRI2 interrupts
Rev. 1.0, 02/00, page 298 of 1141
Bit 5Enabli ng the TMRI1 Interr upt (TMRI1 E): This bit works to perm it/prohibit occurre nce
of the TMRI1 inte rrupt when the TMRI1 has been set to 1 by issua nce of t he underfl ow signal of
the TMRU-1.
Bit 5
TMRI1E Description
0 Prohibits occurrences of TM RI1 interrupts (I nit ial value)
1 Permits occurrences of TMRI1 interrupts
Bit 4TMRI3 Inter r upt Re que sting Flag (TMRI3 ) : This is the TMRI3 interrupt requesting
flag.
It indicates occurrence of an interrupt cause being selected by the CP/SLM bit of the TMRM2,
such as occurrences of the T MRU-2 ca pture signa ls or e nding of the slow tracking m ono-multi
processing.
Bit 4
TMRI3 Description
0[Clearing condit ions] (Initial value)
When 0 is written after reading 1
1 [Setting condition s]
At occurr ence of the interr upt cause being selected by the CP/SLM bit of t he TMRM2
Bit 3TMRI2 Inter r upt Re que sting Flag (TMRI2 ) : This is the TMRI2 interrupt requesting
flag.
It indicates occ urrences of the TMRU-2 underflow signals or ending of the a cceleration/braking
processing of the capst an motor .
Bit 3
TMRI2 Description
0 [Clearing conditions] (Initial value)
When 0 is written after reading 1
1[Setting condition s]
At occurr ences of the TMRU-2 underflow signals or ending of the acceleration
/braking pr ocessing of the capstan motor
Rev. 1.0, 02/00, page 299 of 1141
Bit 2TMRI1 Inter r upt Re que sting Flag (TMRI1 ) : This is the TMRI1 interrupt requesting
flag.
It indicates occ urrences of the TMRU-1 underflow signals.
Bit 2
TMRI1 Description
0 [Clearing conditions] (Initial value)
When 0 is written after reading 1.
1[Setting condition s]
When the TMRU-1 underflows.
Bits 1 and 0Reserved: These bits cannot be modified and are always read as 1.
15. 2. 4 T i m er R Capture Regist e r 1 (TMRCP1 )
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
R
TMRC17
R
TMRC16
R
TMRC15
R
TMRC14
R
TMRC13
R
TMRC12
R
TMRC11
R
TMRC10
Bit :
Initial value :
R/W :
The timer R ca pture re gister 1 (TMRCP1) works to store the captured data of t he TMRU-1.
During the course of the capturing operation, the TMRU-1 counter readi ngs are captured by the
TMRCP1 a t the CFG e dge or the IRQ3 e dge. The capturi ng operation of the TMRU-1 is
performed using 16 bits, in combination with the capturin g oper ation of the TMRU -2.
The TMRCP1 i s an 8-bit re ad only re gister. When re set, t he TMRCS is ini tialized to H'FF.
Notes: 1. When the TMRCP1 is readout while the capture signal is being received, the reading
data become unstable. Pay attention to the timing for reading out.
2. Whe n a shift to th e low pow er cons umptio n mode is made whi le th e captur in g
operating i s in progre ss, t he counter reading be comes unsta ble. After returning t o the
active mode, always write H'FF into the TMRL1 to initialize the counter.
Rev. 1.0, 02/00, page 300 of 1141
15. 2. 5 T i m er R Capture Regist e r 2 (TMRCP2 )
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
R
TMRC27
R
TMRC26
R
TMRC25
R
TMRC24
R
TMRC23
R
TMRC22
R
TMRC21
R
TMRC20
Bit :
Initial value :
R/W :
The timer R ca pture re gister 2 (TMRCP2) works to store the capture data of the T MRU-2. At
each CFG e dge, IRQ3 edge, or at oc currence of unde rflow of the TMRU-3, the TMRU-2 counter
readings are captu red by the TM R C P 2 .
The TMRCP2 i s an 8-bit re ad only re gister. When re set, t he TMRCS will be initialized i nto H'FF.
Notes: 1. When the TMRCP2 is readout while the capture signal is being received, the reading
data become unstable. Pay attention to the timing for reading out.
2. W hen a shift to the low power c onsumption mode is made, the counte r reading
becomes unstabl e . After returni ng to the activ e mod e, always write H'FF into the
TMRL2 to initialize the counter.
15.2.6 Timer R Load Regi ster 1 (TMRL1)
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
W
TMR17
W
TMR16
W
TMR15
W
TMR14
W
TMR13
W
TMR12
W
TMR11
W
TMR10
Bit :
Initial value :
R/W :
The timer R load register 1 (TMRL1) is an 8-bit write-only register which works to set the load
value of the TM R U - 1 .
When a load value is set to the TMRL1, the same value will be set to the TMRU-1 counter
simultaneo u sly and th e cou nter st ar ts co u n ting dow n fr om the set v alue. Also, when the co u nter
underflows during the c ourse of the reload timer ope ration, the TMRL1 value will be set t o the
counter.
When reset, the TMRL1 is initialized to H'FF.
Rev. 1.0, 02/00, page 301 of 1141
15.2.7 Ti mer R Load Register 2 (TMRL2)
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
W
TMR27
W
TMR26
W
TMR25
W
TMR24
W
TMR23
W
TMR22
W
TMR21
W
TMR20
Bit :
Initial value :
R/W :
The timer R load regist e r 2 (T MRL2) is an 8-bit writ e only regi ster which works to set the loa d
value of the TM R U - 2 .
When a load value is set to the TMRL2, the same value will be set to the TMRU-2 counter
simultaneo u sly and th e cou nter st ar ts co u n ting dow n fr om the set v alue. Also, when the co u nter
underflows or a CFG edge is detected duri ng the c ourse of the reload timer operation, the TMRL 2
value will be set to the counter.
When reset, the TMRL2 is initialized to H'FF.
15.2.8 Timer R Load Regi ster 3 (TMRL3)
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
W
TMR37
W
TMR36
W
TMR35
W
TMR34
W
TMR33
W
TMR32
W
TMR31
W
TMR30
Bit :
Initial value :
R/W :
The timer R load regist e r 3 (T MRL3) is an 8-bit writ e only regi ster which works to set the loa d
value of the TM R U - 3 .
When a load value is set to the TMRL3, the same value will be set to the TMRU-3 counter
simultaneo u sly and th e cou nter st ar ts co u n ting dow n fr om the set v alue. Also, when the co u nter
underflows or a DVCTL edge is det ected, the TMRL2 value will be set to the count er. (Re l oading
will be made by the underflowing signals when the DVCTL signal is selected as the clock source,
and reloading will be made by the DVCTL signals when the dividing clock is selected as the clock
source.)
When reset, the TMRL3 is initialized to H'FF.
Rev. 1.0, 02/00, page 302 of 1141
15. 2. 9 Modul e Sto p Contr ol Regi ster (MSTP CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode.
When the MSTP11 bit is set to 1, timer R stops its operation at the ending point of the bus cycle to
shift to t he modul e stop mode. For more information, se e section 4.5, Module Stop Mode.
When rese t, the MSTPCR is initia l iz ed to H'FFFF.
Bit 3Module Stop (MSTP11): This bit works t o designate the module stop mode for the Timer
R.
MSTPCRH
Bit 3
MSTP11 Description
0 Cancels the module stop mode of timer R
1 Sets the module stop m ode of timer R (I nitial value)
Rev. 1.0, 02/00, page 303 of 1141
15.3 Operation
15. 3. 1 Rel oa d Timer Counter Equi pped with Capturi ng Function TMRU-1
TMRU-1 i s a reload timer counter equipped with capturing function. It c onsists of an 8-bit down-
counter, a reloading regi ster and a capture register.
The clock sourc e can be sel ected from a mong the leading edge of the CFG signals a nd three types
of dividi ng clocks. It is also se lectable whether using it as a reload counte r or as a capture counter.
Even when the capturing function is selected, the counter readings can be updated by writing the
values into the reloading register.
When the counter underflows, t he TMRI1 interrupt request will be issued.
The initial values of the TMRU-1 counter, reloading register and capturing register are all H'FF.
• Operation of the Reload Timer
When a value is written into to the reloading register, the same value will be written into the
counter simultane ously. Also, when the counter underflows, the reloading regi ster val ue will
be reloaded to the counter. The TMRU-1 is a dividing circuit for the CFG. In combination
with the TMRU-2 and TMRU-3, it can also be used for the mod e identific at ion purpos e.
• Capturing Operation
Capturing operation is carried out in combination with the TMRU-2 using the combined 16
bits. It ca n be so programmed that the c ounter m ay be cleared by t he capture signal. The CFG
edges or IRQ3 edges are used as the capture signals. It is possible to issue the TMRI3
interrupt re quest by the capt ure signal.
In addition to the capturing function being worked out in combination with the TMRU-2, the
TMRU-1 can be used as a 16-bit CFG counter. Selecting the IRQ3 a s the ca pture signal, the
CFG withi n the duration of the reel pulse being input into the
,54
pin can be counted by t he
TMRU-1.
Rev. 1.0, 02/00, page 304 of 1141
15. 3. 2 Relo a d Timer Counter Equi pped with Capturi ng Function TMRU-2
TMRU-2 i s a reload timer counter equipped with capturing function. It c onsists of an 8-bit down-
counter, a reloading regi ster and a capture register.
The clock sourc e can be sel ected from a mong the undedrflowing signal of the TMRU-1 a nd three
types of di viding cl ocks. Also, although the reloa ding function is workable during its ca pturing
operation, equipping or not of the reloading function is selectable. Even when without-reloading-
function is chosen, the counter reading can be update d by writing t he val ue s to t he rel oa ding
register.
When the counter underflows, t he TMRI2 interrupt request will be issued.
The initial values of the TMRU-2 counter, reloading register and capturing register are all H'FF.
• Operation of the Reload Timer
When a value is written into to the reloading register, the same value will be written into the
counter, sim ultaneously. Also, when the c ounter unde rflows or when a CFG edge i s detected,
the reloading regi ster val ue will be rel oaded t o the counter.
The TMRU-2 c an make acceleration a nd bra king work for the capstan mot or using the reload
timer operation.
• Capturing Operation
Using the capture signals, the counte r reading can be latched into the capturing register. As the
capture signa l, you can choose from am ong e dges of the CFG, edges of the IRQ3 or the
underflow signals of the TMRU-3. It is possible t o issue the T MRI3 i nterrupt request by the
capture signal.
The capturing function (stopping the reloading function) of the TMRU-2, in combination with
the TMRU-1 and TMRU-3, can also be used for t he mode identification purpose.
15.3.3 Reload Counter Timer TMRU-3
The reloa d counter timer TMRU-3 consists of a n 8-bi t down-counte r and a reloading register. Its
clock source can be selected from between the undedrflowing signal of the counter and the edges
of the DVCTL signals. (When the DVCTL signal is selected as the clock source, reloading will be
effected by the unde rflowing signals and when the divi ding clock is selected as the clock source,
reloading will be effected by the DVCTL signals.) The reloading signal works to reload t he
reloading register value into the counter. Also, when a value is written into to the reloading
register, the same value will be written into the counter, simultaneously.
The initial values of the counte r and the reloading register are H' FF.
The underflowing signals ca n be used as the ca pt uring signal for the TMRU-2.
The TMRU-3 can also be used as a dividing circuit for the DVCTL. Also, in combination with
the TMRU-1 and TMRU-2 (capturing function), the TMRU-3 ca n be used for the mode
identification purpose. Since the divided signals of t he DVCTL are bei ng used a s the clock
source, CTL signals (DVCTL) c onforming t o the double speed c a n be input when making
Rev. 1.0, 02/00, page 305 of 1141
searches. These DVCTL signals can also be used for phase controls of the capstan motor.
Also, by selecting the dividing cl ock as the clock source, it is possible to make a delay wit h the
edges of t he DVCTL to provi de the slow tracking mono-m ulti func tion.
15.3.4 Mode Ide ntification
When making mode i dentification (2/ 4/6 identification) of the SP/LP/E P modes of reproducing
tapes, the TMRU-1 (CFG divi ding circuit), TMRU-2 (ca pt uring function/without reloading
function) and TMRU-3 (DVCTL dividing circuit) of timer R should be used.
Timer R will become to th e af oremen tioned s tatus after a reset.
Under the aforementioned status, the divided CFG should be written into the reloading register of
the TMRU-1 and divi ded DVCTL should be written into the reloading re gister of the TMRU-3.
When the TMRU-3 underflows, the counter value of the TMRU-2 is captured. Such capturing
register value represents the number of the CFG within the DVCTL cycle.
As aforementione d, the Timer R can work to count t he number of the CFG corresponding to n
times of DVCTL's or to identify the mode being searched.
For registe r settings, se e section 15.5.1, Mode Identification.
15.3.5 Reeling Controls
CFG count s can be captured by making 16-bit c a pturing operation combining the T MRU-1 and
TMRU-2. Choosing the IRQ3 a s the capture signal and counti ng the CFG within the duration of
the reel pulse being input throu gh the
,54
pin affect reeling c ont rols. For regi ster se ttings, se e
section 15.5. 2, Reeling Controls.
15.3.6 Acceleration and Braking P rocesses of the Capstan M otor
When making intermit tent movem ents such as those for slow reproductions or for still
reproductions, it is ne cessary to conduct quick accelerations and abrupt stoppings of the ca pstan
motor. The acceleration and braking processes functions to check if the revolution of a capstan
motor has reached t he prescri bed rate when accelerated or braked. For t his purpose, t he TMRU-2
(reloading function) shoul d be used.
Whe n making accelerations:
• Set the AC/BR bit of the TMRM1 to acceleration (set to 1). Also, use the rising edge of the
CFG as the reloading signal.
• Set the prescribed time on the CFG frequency to determine if the acceleration has been
finished, into the reloading register.
• The TMRU-2 will work to down-count the reloading data.
• In case t he acceleration has not been finished (i n case t he CFG signa l is not input e ven whe n
the prescribed time has e lapsed = underflowing of down-counting has occ urred), such
Rev. 1.0, 02/00, page 306 of 1141
underflowing works to set to CFG ma sk F/F (masking move ment) a nd the reload timer will be
cleared by the CFG.
• When t he acceleration has been fini shed (when the CFG signal is input be fore the prescribed
time has elapsed = reloading movement has been made before the down counter underflows),
an interrupt request will be issued because of the CFG.
Whe n making br eaking:
• Set the AC/ BR bit of the TMRM1 to braking (clear to 0). Also, use the rising edge of the CFG
as the reloading signal.
• Set the prescribed time on the CFG frequency to determine if the braking has been finished,
into the reloading register.
• The TMRU-2 will work to down-count the reloading data.
• If the bra king has not finished (when the CFG signal is input before the prescribed time has
elapsed and reloading movement has been made before the down counter underflows), the
reload timer movement will continue.
• When the acceleration has finished (when the CFG signal is not input even when the
prescribed time has elapse d and underflowing of down-count i ng ha s occurred), interrupt
request wil l be i ssued because of the unde rflowing signal.
The acceleration and braking proc esses should be em ployed when m aking special reproduct ions,
in combination with the slow tracking mono-multi funct i on out lined in section 15. 3.7.
For registe r settings, se e section 15.5.4, Ac celeration and Braking Processes of the Ca pstan Motor.
15.3.7 Slow Tracking Mono-Multi Function
When performing slow reproductions or still reproductions, the braking timing for the capst a n
motor is determined by use of t he edge of the DVCTL signal. The slow tracking mono-multi
function works to me asure the time from the risi ng edge of the DVCTL signal down to the desired
point to issue the interrupt request. In actua l programming, this interrupt should be used to
activate the brake of the capst an motor. The TMRU-3 should be used t o perform time
measurements for the slow t racking mono-multi function. Also, the braking process ca n be ma de
using the TMRU-2. Figure 15.2 shows the time series movements when a slow reproduction is
being pe rformed.
For registe r settings, se e section 15.5.3, Slow Tracking Mono-Multi Function.
Rev. 1.0, 02/00, page 307 of 1141
HSW
FG acceleration detection
Compensation for vertical vibrations
(Supplementary V-pulse)
DVCTL↑Interrupt
Reloading
Reverse
rotation
Frame feeds
Compensation for
horizontal vibrations Compensation for
horizontal vibrations
Braking
process
Acceleration
process
Slow tracking
delay
C.Rotary
H.AmpSW
Accelerating the
capstan motor
Braking the
drum motor
Slow tracking
mono-multi
Braking the
capstan motor
Servo
Hi-Z
[Legend]
Hi-Z : High impedance state
In case of 4-head SP mode.
In case of 2-head application, H.AmpSW and
C.Rotary should be "Low".
FG stopping detection
Forward
rotation
Fi g ure 15.2 Time Serie s Movement s when a Slow Reproduct i o n
Is Being Performed
Rev. 1.0, 02/00, page 308 of 1141
15.4 Interrupt Cause
In timer R, bits TMRI1 to TMRI3 of the timer R control/status register cause interrupts. The
following a re descri ptions of the interrupts.
1. Inte rrupts caused by the underflowing of the TMRU-1 (T MRI1)
These i nterrupts wil l constitute the timi ng for reloading wit h the TMRU-1.
2. Inte rrupts caused by the underflowing of the TMRU-2 or by an end of the acceleration or
braking process (TMRI2)
When interrupts occur at the reload timing of the TMRU-2, clear the AC/ BR
(acceleration/braking) bit of the timer R mode register 1 (TMRM1) to 0.
3. Inte rrupts caused by the c apture si gnals of the TMRU-2 and by e nding the slow t racking
mono-multi process (TMRI3)
Since these t wo interrupt causes a re constit uting the OR, it bec omes necessary to determine
which int e rrupt ca use is occurring using the software.
Respective interrupt cause s are being set to the CAPF flag or the SLW fl a g of the timer R
mode register 2 (TMRM2), have the software determine which.
Since the CAPF fl a g and the SLW flag will not be cleared automatically, progra m the software
to clear them. (Writing 0 only is valid for these flags.) Unless these flags are cleared,
detection of the next cause becomes unworkable. Also, if the CP/SLM bit is changed leaving
these flags uncleared as they are, these flags will get cleared.
Rev. 1.0, 02/00, page 309 of 1141
15.5 Settings for Respective Functions
15.5.1 Mode Ide ntification
When making mode i dentification (2/ 4/6 identification) of the SP/LP/E P modes of reproducing
tapes, the TMRU-1 (CFG divi ding circuit), TMRU-2 (ca pt uring function/without reloading
function) and TMRU-3 (DVCTL dividing circuit) of the timer R should be used.
Timer R will be initialized to this mode identification status after a reset.
Under this status, t he divided CFG should be writ ten into the reloading re gister of the TMRU-1
and divi de d DVCTL should be written into t he rel oading register of the T MRU-3. W hen the
TMRU-3 underflows, t he counter val ue of the TMRU-2 is captured. Such capturing regi ster value
represents t he numbe r of the CFG within the DVCTL cycle.
Thus, timer R can work to count the num ber of the CFG c orrespondi ng to n times of DVCTL's or
to identify the mode being searched.
Settings
• Setting the timer R mode register 1 (TMRM1)
CLR2 bit (bit 7) = 1: W orks to clear a fter ma king the TMRU-2 capture.
RLD bit (bit 5) = 0: Set s the TMRU-3 without reloading funct ion.
PS21 and PS20 (bits 3 and 2) = (0 and 0): The underflowing signals of the T MRU-1 are to
be us ed as th e clock sourc e fo r the TM R U - 2 .
RLD/CAP bit (bit 1) = 0: The TMRU-1 has been set to make the reload timer operation.
• Setting the timer R mode register 2 (TMRM2)
LAT bit (bit 7) = 0: The underflowing signals of the TMRU-3 are to be used as the capture
signal for the T MRU-2.
PS11 and PS10 (bits 6 and 5) = (0 and 0): The leading edge of the CFG signal is to be used
as the clock source for the TMRU-1.
PS31 and PS30 (bits 4 and 3) = (0 and 0): The leading edge of the DVCTL signal is to be
used as the clock source for the T MRU-3.
CP/SLM bi t (bit 2) = 0: The capture signa l is to work to issue the TMRI3 interrupt request.
• Setting the timer R load register 1 (TMRL1)
Set the divi ding value for the CFG. The set value shoul d become (n − 1) when di vided by
n.
• Setting the timer R load register 3 (TMRL3)
Set the dividing value for the DVCTL. The set value should become (n − 1) when divided
by n.
Rev. 1.0, 02/00, page 310 of 1141
15.5.2 Reeling Controls
CFG count s can be captured by making 16-bit c a pturing operation combining the T MRU-1 and
TMRU-2. By choosing the IRQ3 as t he capture signal, and by counting the CFG within the
duration of the reel pulse being i nput through the
,54
pin, reeling controls, etc. can be effected.
Settings
• Setting P13/
,54
pin as th e
,54
pi n
Set the PMR13 bit (bit 3) of the port mode register 1 (PMR1) to 1. See section 10.3.2, Port
Mode Register (PMR1).
• Setting the timer R mode register 1 (TMRM1)
CLR2 bit (bit 7) = 1: W orks to clear a fter ma king the TMRU-2 capture.
PS21 and PS20 (bits 3 and 2) = (0 and 0): The underflowing signals of the T MRU-1 are to
be us ed as th e clock sourc e fo r the TM R U - 2 .
RLD/CAP bit (bit 1) = 1: The TMRU-1 has been set to make the capturing operation.
CPS bit (bit 0) = 1: The edge of the IRQ3 signal is to be used as the capture signal for the
TMRU-1 a nd TMRU-2.
• Setting the timer R mode register 2 (TMRM2)
LAT bit (bit 7) = 1: The edge of the IRQ3 signal is to be used as the capture signal for the
TMRU-1 a nd TMRU-2.
PS11 and PS10 (bits 6 and 5) = (0 and 0): The rising e dge of the CFG signal is to be used
as the clock source for the TMRU-1.
CP/SLM bi t (bit 2) = 0: The capture signa l is to work to issue the TMRI3 interrupt request.
15.5.3 Slow Tracking Mono-Multi Function
When performing slow reproductions or still reproductions, the braking timing for the capst a n
motor is determined by use of t he edge of the DVCTL signal. The slow tracking mono-multi
function works to me asure the time from the leading edge of the DVCTL signal down to t he
desired point t o issue the i nterrupt request. In actual programming, this int errupt should be used t o
activate the brake of the capst an motor. The TMRU-3 should be used t o perform time
measurements for the slow t racking mono-multi function. Also, the braking process ca n be ma de
using the TMRU-2.
Rev. 1.0, 02/00, page 311 of 1141
Settings
• Setting the timer R mode register 2 (TMRM2)
PS31 and PS30 (bits 4 and 3) = Other than (0, 0): The dividing clock is to be used as the
clock source for the TMRU-3.
CP/SLM bit (bit 2) = 1: The slow tracking delay signal is to work to issue the TMRI3
interrupt re quest.
• Setting the timer R load register 3 (TMRL3)
Set the slow tracking delay value. W hen the delay count is n, t he set va lue should be
(n - 1).
Regarding the delaying duration, see figure 15.2.
15.5.4 Acceleration and Braking P rocesses of the Capstan M otor
When making intermit tent movem ents such as those for slow reproductions or for still
reproductions, it is ne cessary to conduct quick accelerations and abrupt stoppings of the ca pstan
motor. The acceleration and braking processes will function to check if the revolution of a capstan
motor has reached t he prescri bed rate when accelerated or braked. For t his purpose, t he TMRU-2
(reloading function) shoul d be used.
The acceleration and braking proc esses should be em ployed when m aking special reproduct ions,
in combination with the slow tracking mono-multi funct i on.
Settings for the acceler ation process
• Setting the timer R mode register 1 (TMRM1)
AC/BR bit (bit 6) = 1: Acceleration process
RLD bit (bit 5) = 1: The TMRU-2 is to be used as the reload timer.
RLCK bit (bit 4) = 0: The TMRU-2 is to reload at the risi ng edge of the CFG.
PS21 and PS20 (bits 3 and 2) = Other than (0, 0): The dividing clock is to be used as the
clock source for the TMRU-2.
• Setting the timer R load register 2 (TMRL2)
Set the count reading for the durat i on until the acceleration proce ss finishes. When the
count is n, the set value shoul d be (n − 1).
Regarding the duration unti l the acceleration proce ss finishe s, see figure 15.2.
Settings for the braking process
• Setting the timer R mode register 1 (TMRM1)
AC/BR bit (bit 6) = 0: Braking process
RLD bit (bit 5) = 1: The TMRU-2 is to be used as the reload timer.
RLCK bit (bit 4) = 0: The TMRU-2 is to reload at the risi ng edge of the CFG.
Rev. 1.0, 02/00, page 312 of 1141
PS21 and PS20 (bits 3 and 2) = Other than (0, 0): The dividing clock is to be used as the
clock source for the TMRU-2.
• Setting the timer R load register 2 (TMRL2)
Set the count reading for the durat i on until the bra king proce ss finishe s. When t he count is
n, the set value should be (n - 1).
Regarding the duration unti l the braking process finishes, see fi gure 15.2.
Rev. 1.0, 02/00, page 313 of 1141
Section 16 Timer X1
16.1 Overview
Timer X1 is capabl e of outputting t wo diffe rent types of inde pendent waveforms using a 16-bit
free running counter (FRC) as the basic means and it is also applicable to measurements of the
durations of input pulses and the cycles external clocks.
16.1.1 Features
Timer X1 has the following features:
• Four different types of counte r inputting cloc ks.
Three different types of internal clocks (φ/4, φ/16 and φ/64) and the DVCFG.
• Two in dependent ou tp ut comp aring function s
Capable of outputting two different types of indepe ndent waveforms.
• Four independe nt input capturing func tions
The rising edge or falling edge can be sel ected for use. The buffer operation can a l so be
designated.
• Counter clear ing designa tio n is workable.
The counter readings can be cleared by compare match A.
• Seven types of interrupt causes
Comparing ma tch × 2 causes, input capture × 4 causes and over flow × 1 cause are available fo r
use and they can make resp ectiv e interrupt requests ind epen den tly .
Rev. 1.0, 02/00, page 314 of 1141
16.1.2 Block Diagram
Figure 16. 1 shows a bloc k diagram of the Ti mer X1.
Internal data bus
[Legend]
TIER
ICRA
ICRB
ICRC
ICRD
TCRX
OCRB
Comparison circuit
FRC
Comparison circuit
OCRA
TOCR
TCSRX
TIER
Input
capture
control
Output comparing output
Interrupt
request × 7
FTOA
FTOB
FTIA*
(HSW)
FTIB*
(VD)
FTIC*
(DVCTL)
FTID*
(NHSW)
(DVCFG)
φ / 4
φ / 16
φ / 64
TCSRX
FRC
OCRA
OCRB
TCRX
TOCR
ICRA
ICRB
ICRC
ICRD
: Timer interrupt enabling register
: Timer control/status register X
: Free running counter
: Output comparing register A
: Output comparing register B
: Timer control register X
: Output comparing control register
: Input capture register A
: Input capture register B
: Input capture register C
: Input capture register D
Note: * stands for the external terminal.
( ) stands for the internal signal.
Figure 16.1 Block Diagr am of Timer X1
Rev. 1.0, 02/00, page 315 of 1141
16.1.3 P i n Confi guration
Table 16. 1 shows the pi n configuration of timer X1.
Table 16. 1 Pin Configuration
Name Abbrev. I/O Function
Output com paring A output -pin FTO A Output O utput pin for the out put comparing A
Output com paring B output -pin FTO B Output O utput pin for the out put comparing B
Input capture A input-pin FTIA I nput Input-pin for the input capture A
Input capture B input-pin FTIB I nput Input-pin for the input capture B
Input capture C input-pin FTIC Input Input-pin for the input capture C
Input capture D input-pin FTID Input Input-pin for the input capture D
Rev. 1.0, 02/00, page 316 of 1141
16.1.4 Regi ster Configur ati on
Table 16.2 shows the register configuration of timer X1.
Table 16. 2 Register Configurati on
Name Abbrev. R/ W Initial Value Address*3
Timer interrupt enabling r egister TI ER R/W H'00 H'D100
Timer control/s tatus regis ter X TCSRX R/ (W)*1 H'00 H'D101
Free running counter H FRCH R/W H'00 H'D102
Free running counter L FRCL R/W H'00 H'D103
Output com paring regist er AH OCRAH R/W H'FF H'D104*2
Output com paring regist er AL OCRAL R/W H'FF H'D105*2
Output com paring regist er BH OCRBH R/W H'FF H'D104*2
Output com paring regist er BL OCRBL R/W H'FF H'D105*2
Timer c ontrol reg is ter X TCRX R/W H'00 H'D1 06
Timer output comparing cont r ol register TO CR R/W H'00 H'D107
Input capture regist er AH I CRAH R H'00 H'D108
Input capture regist er AL ICRAL R H'00 H'D109
Input capture regist er BH I CRBH R H'00 H'D10A
Input capture regist er BL ICRBL R H'00 H'D10B
In put capture register CH ICRCH R H'0 0 H'D1 0C
In put capture register CL ICRCL R H'00 H'D10D
In put capture register DH ICRDH R H'0 0 H'D1 0E
In put capture register DL ICRDL R H'00 H'D10F
Notes: 1. O nly 0 can be wr itten to clear the flag for Bit s 7 to 1. Bit 0 is readable/wr itable.
2. The addresses of the OCRA and OCRB are the sam e. Changeover between them are
to be m ade by use of the TOCR bit and OCRS bit.
3. Lower 16 bits of the address .
Rev. 1.0, 02/00, page 317 of 1141
16.2 Regi ster Descri pt i on s
16. 2. 1 Free Runni ng Co unt er (F RC)
Free runni ng counter H (FRCH)
Free runni ng counter L (FRCL)
0
3
0
R/W
5
0
R/W
7
0
9
0
R/W
11
0
13
0
15
R/WR/WR/W
0
R/W R/W
1
0
2
0
R/W
4
0
R/W
6
0
8
0
R/W
10
0
12
0
14
FRC
FRCH FRCL
R/WR/WR/WR/W
0
R/W
0
Bit :
Initial value :
R/W :
The FRC i s a 16-bit read/wri te up-counter which count s up by the input ting internal cl ock/externa l
clock. T he input ting clock is to be sel ected from the CKS1 and CKS0 of the T CRX.
By the setting of the CCLRA bit of the TCSRX, the FRC can be cl eared by compa ring ma tch A.
Wh en the FRC ov erf l o ws (H'FFFF → H'0000), the OVF of the TCSRX will be set to 1.
At this time, when t he OVIE of the TIER is being set to 1, an inte rrupt reque st will be issued t o the
CPU.
Reading/writi ng can be made from and to the FRC through the CPU a t 8-bit or 16-bit.
The FRC i s initialized t o H'0000 when reset or under the sta ndby mode, watch m ode, subsleep
mode, modu le st op mo de or subactive mode.
Rev. 1.0, 02/00, page 318 of 1141
16. 2. 2 Output Co m pari ng Regist er s A and B (OCRA and OCRB)
Output comparing registe r AH and BH (OCRAH and OCRBH)
Output comparing registe r AL and BL (OCRAL and OCRBL)
1
3
1
R/W
5
1
R/W
7
1
9
1
R/W
11
1
13
1
15
R/WR/WR/W
1
R/W R/W
1
1
2
1
R/W
4
1
R/W
6
1
8
1
R/W
10
1
12
1
14
OCRA, OCRB
OCRAH, OCRBH OCRAL, OCRBL
R/WR/WR/WR/W
1
R/W
0
Bit :
Initial value :
R/W :
The OCR c onsists of twin 16-bit read/ write registers (OCRA and OCRB). The c ontents of the
OCR are always being compared with the FRC and, when the value of these two match, the OCFA
and OCRB of the TCSRX will be set to 1. At this time, if the OCIAE and OCIB of the TIER are
being set to 1, an interrupt reque st will be issued to the CPU.
When performing compa re ma t ching, if the OEA a nd OEB of the TOCR are set to 1, the level
value se t to the OLVLA and OL VLB of the TOCR will be output t hrough t he FTOA a nd FT OB
pins. Afte r resetting, 0 wi ll be output t hrough the FTOA and FTOB pins until the fi rst compare
matching occurs.
Reading/writi ng can be made from and to the OCR through the CPU a t 8-bit or 16-bit.
The OCR is c leared to H'FFFF when re set or under t h e standby mode, watch mode, subsleep
mode, modu le st op mo de or subactive mode.
Rev. 1.0, 02/00, page 319 of 1141
16. 2. 3 Input Ca pture Regist e r s A Thro ug h D (ICRA Through ICRD)
Input capture registe r AH to DH (ICRAH to ICRDH)
Input capture registe r AL to DL (ICRAL to ICRDL)
0
3
0
R
5
0
R
7
0
9
0
R
11
0
13
0
15
RRR
0
RR
1
0
2
0
R
4
0
R
6
0
8
0
R
10
0
12
0
14
ICRA, ICRB, ICRC, ICRD
ICRAH, ICRBH, ICRCH, ICRDH ICRAL, ICRBL, ICRCL, ICRDL
RRRR
0
R
0
Bit :
Initial value :
R/W :
The ICR consists of four 16-bi t read-onl y registe rs (ICRA through ICRD).
When the falling edge of the input capture input signal is det ected, the val ue is tra nsferred to the
ICRA through ICRD. The ICFA through ICFD of the TCSRX are set t o 1 simultaneously. If the
IDIAE through IDIDE of the TCRX ar e all set to 1, an interrupt request will be issued to the CPU.
The edge of the i nput signal can be selected by setting the IEDGA through IEDGD of the T CRX.
The ICRC and ICRD can also be used as the buffer register, of t he ICRA and ICRB, respectively
by setting the BUFE A and BUFEB of the T CRX to perform buffer operations. Figure 16.2 shows
the connec tions necessary whe n using the ICRC as the buffer regi ster of the ICRA. (BUFEA = 1)
When the ICRC is used as the buffer of t he ICRA, by setting IEDGA ≠ IEDGC, both of the rising
and falling edg es can be designated for use. In case of IEDGA = IEDGC, either one of the rising
edge or the falling edge only is usable. Regarding selection of the input signal edge, se e table
16.3.
Note: Transference from the FRC to the ICR will be performed regardless of the value of the
ICF.
Rev. 1.0, 02/00, page 320 of 1141
Edge detection and
capture signal
generating circuit.
BUFEAIEDGA
FTIA
IEDGC
ICRC ICRA FRC
Figure 16.2 Buffer Operation (Examp l e)
Tabl e 16. 3 Input Si gna l Edge Selec tion when Maki ng Buffer Operation
IEDG A IEDGC Sel ecti on of the Input Signal Edge
0 Captures at the falling edge of the input capture input A (Initial value)
0
1
0Captures at both r ising and falling edges of the input capture input A
1
1 Captures at the rising edge of the input capture input A
Reading ca n be made from t he ICR through the CPU at 8-bit or 16-bit.
For stable input ca pturing ope ration, maintain the pulse duration of the input c apture input signals
at 1.5 system clock (φ) or more in case of single edge capturing and at 2.5 system clock (φ) or
more in case of bo th ed ge capt uring.
The ICR is initialized to H'0000 when reset or under the standby mode, watch mode, subsleep
mode, modu le st op mo de or subactive mode.
Rev. 1.0, 02/00, page 321 of 1141
16. 2. 4 T i m er Inte rrupt E nabli ng Regist er (TIER)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/W
ICICE
R/W
ICIBE
0
R/W
ICIAE ICIDE OCIAE OCIBE OVIE ICSA
Bit :
Initial value :
R/W :
The TIER i s an 8-bit read/write register that control s permission/prohibition of interrupt requests.
The TIER i s ini t ialized t o H'00 when reset or under the standby m ode, wa tch mode , subsleep
mode, modu le st op mo de or subactive mode.
Bit 7Enabling the Input Capture Interrupt A (ICIAE): This bit works to permit/prohibi t
interrupt re quests (ICIA) by t he ICFA when the ICFA of the TCSRX is being set t o 1.
Bit 7
ICIAE Description
0 Prohibits interrupt requests (ICIA) by the ICFA ( I nit ial value)
1 Permits interrupt requests (ICIA) by the ICFA
Bit 6Enabli ng the Input Ca pt ure Interr upt B (ICIB E): This bit works to permit/prohibit
interrupt re quests (ICIB) by the ICFB whe n the ICFB of the TCSRX is bei ng set to 1.
Bit 6
ICIBE Description
0 Prohibits interrupt requests (ICIB) by the ICFB ( I nit ial value)
1 Permits interrupt requests (ICIB) by the ICFB
Bit 5Enabling the Input Capture Interrupt C (ICICE): This bit works to permit/prohibi t
interrupt re quests (ICIC) by the ICFC whe n the ICFC of the TCSRX is bei ng set to 1.
Bit 5
ICICE Description
0 Prohibits interrupt requests (ICIC) by t he ICFC (Initial value)
1 Permits interrupt requests (ICIC) by the ICFC
Rev. 1.0, 02/00, page 322 of 1141
Bit 4Enabling the Input Capture Interrupt D (ICIDE): This bit works to permit/prohibi t
interrupt re quests (ICID) by t he ICFD when the ICFD of the TCSRX is being set t o 1.
Bit 4
ICIDE Description
0 Prohibits interrupt requests (ICID) by t he ICFD (Initial value)
1 Permits interrupt requests (ICID) by the ICFD
Bit 3Enabling the Output Comparing Inter r upt A (OCIAE): This bit works to
permit/prohi bit interrupt requests (OCIA) by the OCFA when the OCFA of the TCSRX is bei ng
set to 1 .
Bit 3
OCIAE Description
0 Prohibits interrupt requests (OCIA) by t he OCFA (Init ial value)
1 Permits interrupt requests (OCIA) by the OCFA
Bit 2Enabling the Output Comparing Inter r upt B (OCIBE): This bit works t o
permit/prohi bit interrupt requests (OCIB) by the OCFB when the OCFB of the TCSRX is bei ng
set to 1 .
Bit 2
OCIBE Description
0 Prohibits interrupt requests (OCIB) by t he OCFB (Init ial value)
1 Permits interrupt requests (OCIB) by the OCFB
Bit 1Enabling the Timer Overflow Inter r upt (OVIE): This bit works to permi t/prohibit
interrupt requests (FOVI) by t he OVF when the OVF of t he TCSRX is being set to 1.
Bit 1
OVIE Description
0 Prohibits interrupt requests (FOVI) by the O VF (Initial value)
1 Permits interrupt requests (FOVI) by the OVF
Rev. 1.0, 02/00, page 323 of 1141
Bit 0Selec ting the Input Capture A Signals (ICSA) : This bit works to select the input capture
A signals.
Bit 0
ICSA Description
0 Selects the FTIA pin f or inputt ing of the input capture A signals (Initial value)
1 Selects the HSW for input ting of the input capture A signals
Rev. 1.0, 02/00, page 324 of 1141
16.2.5 Ti mer Control/Status Register X (TCSRX)
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
R/WR/(W)*
ICFB
0
R/(W)*
ICFA
R/(W)*
ICFD
R/(W)*
ICFC
R/(W)*
OCFB
R/(W)*
OCFA CCLRA
R/(W)*
OVF
Note: * Only 0 can be written to clear the flag for Bits 7 to 1.
Bit :
Initial value :
R/W :
The TCSRX i s an 8-bit re gi ster which works to select count e r clearing t iming and to control
respective interrupt requesting signals. The T CSRX is initialized t o H'00 whe n reset or under the
standby mode, watch m ode, subsleep mode, m odule stop mode or subactive mode.
Meanwhile, as for the timing, see section 16.3, Operation.
The FTIA t hrough FTID pins are for fixed i nputs inside t he LSI under the l ow power c onsumption
mode excluding the sleep mode. Consequently, when such shifts as active mode → low power
consumption mode → active mode are ma de, wrong edges may be detected de pending on the pi n
status or on the type of the detecting edge.
To avoi d such error, clear the interrupt requesting flag onc e immedi ately after shifting to the
active mode from the low power consumption mode.
Bit 7Input Capt ure Flag A (ICFA): This is a status flag indicating the fact that the value of
the FRC ha s bee n transferre d to the ICRA by the input c apture signals.
When the BUFEA of the TCRX is being set to 1, the ICFA indicates the status that the FRC value
has been transferred to the ICRA by the input ca pture signa ls and that the ICRA value before
being upda ted has been transferred to the ICRC.
This flag should be cleared by use of of the software. Such setting should only be made by use of
the hardware. It is not possible to ma ke this setting usi ng a software.
Bit 7
ICFA Description
0 [Clearing conditions] (Initial value)
When 0 is written into t he ICFA after r eading the I CFA under the set t ing of ICFA = 1
1[Setting condition s]
When the value of the FRC has been tr ansferred t o the ICRA by the input capture
signals
Rev. 1.0, 02/00, page 325 of 1141
Bit 6Input Capture Flag B (ICFB): This status flag indicates the fact that the value of the
FRC ha s been tra nsferred to the ICRB by the input capture signals.
When the BUFEB of the TCRX is being set to 1, the ICFB indicates the status that the FRC value
has been transferred to the ICRB by the input capture signals a nd that the ICRB value before being
updated has been tra nsferred to the ICRC.
This flag should be cleared by use of the software. Such setting should only be made by use of the
hardware. It is not possible to make t his set ting using a software.
Bit 6
ICFB Description
0 [Clearing conditions] (Initial value)
When 0 is written into t he ICFB after r eading the I CFB under the set t ing of ICFB = 1
1[Setting condition s]
When the value of the FRC has been tr ansferred t o the ICRB by the input capture
signals
Bit 5Input Capt ure Flag C (ICFC): This status flag indicates the fact that the value of the
FRC ha s been tra nsferred to the ICRC by the input capture signals.
When an input capture signal occurs while the BUFEA of the TCRX is being set to 1, although the
ICFC wil l be set out, da ta transference t o the ICRC will not be performed.
Therefore, in buffe r ope ration, the ICFC c an be used as an external interrupt by setting the ICICE
bit to 1.
This flag should be cleared by use of the software. Such setting should only be made by use of the
hardware. It is not possible to make t his set ting using a software.
Bit 5
ICFC Description
0[Clearing condit ions] (Initial value)
When 0 is written into t he ICFC after r eading the ICFC under the set t ing of ICFC = 1
1 [Setting condition s]
When the input captur e signal has occurred
Rev. 1.0, 02/00, page 326 of 1141
Bit 4Input Capt ure Flag D (ICFD): This status flag indicates the fact that the value of the
FRC ha s been tra nsferred to the ICRD by the input capture si gnals.
When an input captur e signa l occurs wh ile the BUFE B of the TCRX is being set to 1, although the
ICFD will be set out, da ta transference t o the ICRD will not be performed.
Therefore, in buffe r ope ration, the ICFD ca n be used as an external interrupt by setting t he ICIDE
bit to 1.
This flag should be cleared by use of the software. Such setting should only be made by use of the
hardware. It is not possible to make t his set ting using a software.
Bit 4
ICFD Description
0 [Clearing conditions] (Initial value)
When 0 is written into t he ICFD after r eading the ICFD under the set t ing of ICFD = 1
1[Setting condition s]
When the input captur e signal has occurred
Bit 3Out put Compari ng Flag A (OCF A): This status flag indicates the fact that the FRC and
the OCRA have come to a comparing match.
This flag should be cleared by use of the software. Such setting should only be made by use of the
hardware. It is not possible to make t his set ting using a software.
Bit 3
OCFA Description
0 [Clearing conditions] (Initial value)
When 0 is written into th e OCFA after reading t he OCFA under t he setting of OCFA =
1
1[Setting condition s]
When the FRC and the OCRA have come to the comparing match
Rev. 1.0, 02/00, page 327 of 1141
Bit 2Output Compari ng Fl ag B (OCFB): This status flag indicates the fact that the FRC and
the OCRB have come to a comparing match.
This flag should be cleared by use of the software. Such setting should only be made by use of the
hardware. It is not possible to make t his set ting using a software.
Bit 2
OCFB Description
0[Clearing condit ions] (Initial value)
When 0 is written into th e OCFB after reading t he OCFB under t he setting of OCFB =
1
1[Setting condition s]
When the FRC and the OCRB have come to the comparing match
Bit 1Time Over Flow (OVF): This is a status flag indicating the fact that the FRC overflowed.
(H'FFFF → H'0000).
This flag should be cleared by use of the software. Such setting should only be made by use of the
hardware. It is not possible to make t his set ting using a software.
Bit 1
OVF Description
0 [Clearing conditions] (Initial value)
When 0 is written into t he OVF af ter reading the OVF under the setting of OVF = 1
1[Setting condition s]
When the FRC value has bec ome H'FFFF → H'0000
Bit 0Counter Cle ari ng (CCLRA) : This bi t works to select i f or not to c l ear the FRC by
occurrence of comparing match A (matching signal of the FRC and OCRA).
Bit 0
CCLRA Description
0 Prohibits clearing of the FRC by occurr ence of com paring m atch A (Initial value)
1 Permit s cle aring of t he FRC by occ ur rence of comparing matc h A
Rev. 1.0, 02/00, page 328 of 1141
16. 2. 6 T i m er Contr ol Register X (TCRX)
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
R/WR/W
IEDGB
0
R/W
IEDGA
R/W
IEDGD
R/W
IEDGC
R/W
BUFEB
R/W
BUFEA CKS0
R/W
CKS1
Bit :
Initial value :
R/W :
The TCRX is an 8-bit read/write regi ster tha t selects the input capture signal edge, designat es the
buffer ope ration, and selects the i nputting clock for the FRC.
The TCRX is initialized to H'00 when reset or under the standby mode, watch mode, subsleep
mode, modu le st op mo de or subactive mode.
Bit 7Input Capt ure Signal Edg e Selec t ion A (IEDGA) : This bi t works to select the rising
edge or falling edge of the input capt ure signal A (FTIA).
Bit 7
IEDGA Description
0 Captures the falling edge of the input capt ure signal A (Initial value)
1 Captures the rising edge of the input capt ure signal A
Bit 6Input Capture Signal Edge Selection B (IEDGB): This bit works to select the rising
edge or falling edge of the input capt ure signal B (FTIB).
Bit 6
IEDGB Description
0 Captures the falling edge of the input capt ure signal B (Initial value)
1 Captures the rising edge of the input capt ure signal B
Bit 5Input Capt ure Signal Edg e Selec t ion C (IEDGC) : This bi t works to select the rising
edge or falling edge of the input capt ure signal C (FTIC). However, when t he DVCTL has bee n
selected as the signal for the input capture signal edge selection C, this bit will not influence the
operation.
Bit 5
IEDGC Description
0 Captures the falling edge of the input capt ure signal C (Initial value)
1 Captures the rising edge of the input capt ure signal C
Rev. 1.0, 02/00, page 329 of 1141
Bit 4Input Capt ure Signal Edg e Selec t ion D (IEDGD) : This bi t works to select the rising
edge or falling edge of the input capt ure signal D (FTID).
Bit 4
IEDGD Description
0 Captures the falling edge of the input capt ure signal D (Initial value)
1 Captures the rising edge of the input capt ure signal D
Bit 3Buffer Enabli ng A (BUFEA): Thi s bit works to select whet her or not t o use the ICRC as
the buffer regi ster for the ICRA.
Bit 3
BUFEA Description
0 Not using t he ICRC as the buffer register f or the ICRA ( I nit ial value)
1 Us in g the ICRC as the buffer reg ist er fo r t he ICRA
Bit 2Buffer Enabli ng B (BUFEB): T hi s bit works to select whet her or not to use the ICRD as
the buffer regi ster for the ICRB.
Bit 2
BUFEB Description
0 Not using t he ICRD as the buffer register f or the ICRB ( I nit ial value)
1 Us in g the ICRD as the buffer reg ist er fo r t he ICRB
Bits 1 and 0Clock Select (CKS1, 0): These bits work to select the inputting clock to the FRC
from among three types of int ernal clocks a nd the DVCFG.
The DVCFG is the edge detecting pulse selected by the CFG dividing timer.
Bit 1 Bit 0
CKS1 CKS0 Description
0 0 I nt ernal clock: Counts at φ/4 (I nitial value)
0 1 I nt ernal clock: Counts at φ/16
1 0 I nt ernal clock: Counts at φ/64
1 1 DVCFG: The edge detecting pulse selected by the CFG dividing timer
Rev. 1.0, 02/00, page 330 of 1141
16.2.7 Ti mer Output Comparing Contr ol Re gi ster (TOCR)
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
R/W R/W
ICSC
0
R/W
ICSB
R/W
OSRS
R/W
ICSD
R/W
OEB
R/W
OEA OLVLB
R/W
OLVLA
Bit :
Initial value :
R/W :
The TOCR is an 8-bit read/write regi ster tha t select input capture si gnals and output com paring
output level, permits output comparing outputs, and controls switching over of the access of the
OCRA and OCRB. See section 16.2. 4, Timer Interrupt Enabling Register (T IER) rega rding the
input capt ure inputs A.
The TOCR is initialized to H'00 when reset or under the standby mode, watch mode, subsleep
mode, modu le st op mo de or subactive mode.
Bit 7Selec ting the Input Capture B Signals ( ICSB ): This bit works to select the input capture
B signals.
Bit 7
ICSB Description
0 Selects the FTIB pin f or inputt ing of the input capture B signals (Initial value)
1 Selects the VD as the input capture B signals
Bit 6Selec ting the Input Capture C Signals (ICSC) : This bit works to select the input capture
C signals. The DVCTL is the edge detecting pulse selected by the CTL dividing timer.
Bit 6
ICSC Description
0 Selects the FTIC pin f or inputting of the input capt ure C signals (Initial value)
1 Selects the DVCTL as the input capture C signals
Bit 5Selec ting the Input Capture D Signals (ICSD) : This bit works to select the input capture
D signals.
Bit 5
ICSD Description
0 Selects the FTID pin f or inputting of the input capt ure D signals (Initial value)
1 Selects the NHSW as t he input capture D signals
Rev. 1.0, 02/00, page 331 of 1141
Bit 4Selec ting the Output Compari ng Regist er (OCRS): The a ddresses of the OCRA and
OCRB a re the same. The OCRS works to c ontrol whic h register to choose when rea ding/writing
this address. The choice will not influence the operation of the OCRA and OCRB.
Bit 4
OCRS Description
0 Selects the OCRA regist er (Init ial value)
1 Selects the OCRB regist er
Bit 3Enabling the Output A (OEA): This bit works t o control the output comparing A signals.
Bit 3
OEA Description
0 Prohibits the output comparing A signal outputs (I nitial value)
1 Permits the output comparing A signal outputs
Bit 2Enabling th e Outpu t B (OEB): This bit works to control the output comparing B signals.
Bit 2
OEB Description
0 Prohibits the output comparing B signal outputs (I nitial value)
1 Permits the output comparing B signal outputs
Bit 1Output Level A (OLVLA): This bit works to select the output leve l to output through t he
FTOA pin by use of the comparing match A (matching signal between the FRC and OCRA).
Bit 1
OLVLA Description
0 Lo w le v e l (Initial value)
1 High le v e l
Rev. 1.0, 02/00, page 332 of 1141
Bit 0Output Level B (OLVLB): This bit works to select the output le vel to out put through the
FTOB pi n by use of the comparing m atch B (matching signal betwee n the FRC and OCRB).
Bit 0
OLVLB Description
0 Lo w le v e l (Initial value)
1 High le v e l
16. 2. 8 Modul e Sto p Contr ol Regi ster (MSTP CR)
7
0
MSTP15
R/W
MSTPCRH
6
0
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Initial value :
R/W :
Bit :
The MSTPCR consists of twin 8-bit read/write registers that control the module stop mode.
When the MSTP10 bit is set to 1, the Timer X1 stops its operation at the ending point of the bus
cycle to shift to the m odule stop mode. For more i nformation, se e section 4.5, Module Stop
Mode.
When rese t, the MSTPCR is initia l iz ed to H'FFFF.
Bit 2Module Stop (MSTP10): This bit works t o designate the module stop m ode for timer X1.
MSTPCRH
Bit 2
MSTP10 Description
0 Cancels the module stop mode of the Timer X1
1 Sets the module stop mode of the Timer X1 (I nitial value)
Rev. 1.0, 02/00, page 333 of 1141
16.3 Operation
16.3.1 Operation of Timer X1
• Output Comparing Operation
Right afte r resetting, the FRC is initialized to H'0000 to start counti ng up. The inputt ing clock
can be selected from among t hree different types of interna l clocks or the external clock by
setting the CKS1 and CKS0 of the TCRX.
The contents of the FRC are always being compared with the OCRA and OCRB and, when
the value of these two match, the level set by the the OLVLA and OLVLB of the TOCR is
output t hrough the FTOA pin and FTOB pin.
After rese tting, 0 will be output through the FTOA and FTOB pins until the first com pare
matching occurs.
Also, when the CCLRA of the TCSRX is being set to 1, the FRC will be cleared to H'0000
when th e comparing match A occu r s.
• Input Capt uring Operation
Right afte r resetting, the FRC is initialized to H'0000 to start counti ng up. The inputt ing clock
can be selected from among t hree different types of interna l clocks or the external clock by
setting the CKS1 and CKS0 of the TCRX.
The inputs are transferred t o the IEDGA through IE DGD of the TCRX through t he FTIA
through FTID pins and, at the s am e time, th e ICFA through ICFD of the TCSRX are set to 1.
At this time, if the ICIAE through ICIED of the TIER a re bei ng set to 1, due int errupt re quest
will be issued to the CPU.
When the BUFEA and BUFEB of the T CRX are set to 1, the ICRC and ICRD work as t he
buffer register, respectively, of the ICRA and ICRB. Whe n the e dge selected by se tting the
IEDGA through IEDGD of the TCRX is input through the FTIA and FTIB pi ns, the value at
the time of the FRC is transferred to the ICRA and ICRB and, at the same time, the values of
the ICRA a nd ICRB before updating are transferred to the ICRC and ICRD. At this time,
when the ICFA and ICFB are be i ng set to 1 and if the ICIAE and ICIBE of the TIER are be ing
set to 1, du e interrup t request will be issued to the CPU.
Rev. 1.0, 02/00, page 334 of 1141
16.3.2 Counting Timing of the FRC
The FRC is counted up by the inputting clock. By setting the CKS1 and CKS0 of the TCRX, the
inputting cl ock can be selected from among three different types of clocks ( φ/4, φ/16 and φ/64)
and the DV CFG.
• Internal Clock Operation
By setting the CKS1 and CKS0 bits of the TCRX, three types of internal clocks (φ/4, φ/16 and
φ/64), ge nerated by dividing t he system clock ( φ) c a n be selected. Figure 16.3 shows the
timing chart.
FRC
Internal clock
φ
FRC input
clock
NN-1 N+1
Fi g ure 16.3 Count Timing for Interna l Clock Oper atio n
• DVCFG Clock Operati o n
By setting the CKS1 and CKS0 bits of the TCRX to 1, DVCFG clock input can be selected.
The DVCFG clock makes counting by use of the edge detecting pulse being selected by the
CFG dividing timer .
Figure 16. 4 shows the t iming chart.
FRC
CFG
FRC input
clock
φ
N N+1
DVCFG
Figure 16.4 Count Timing for CFG Clock Oper ation
Rev. 1.0, 02/00, page 335 of 1141
16.3.3 Output Comparing Signal Outputting Timing
When a comparing match occurs, the output level having been set by the OLVL of the TOCR is
output t hrough the output comparing signal outputting pins (FTOA and FTOB).
Figure 16. 5 shows the t iming chart for the output com paring signal out putting A.
FRC
OLVLA
FTOA
Output comparing
signal outputting
A pin
N
N
↓ Clearing
*1
N
N
N+1N+1
Comparing match
signal
φ
OCRA
Note: 1. Execution of the command is to be designated by the software.
Figure 16.5 Output Comparing Signal Outputting A Timi ng
16. 3. 4 FRC Clea ring Ti ming
The FRC can be cleared when the comparing match A occurs. Figure 16.6 shows the timing chart.
FRC
Comparing match
A signal
φ
N H' 0000
Figure16.6 Clearing Timing by Occurrence of the Comparing Match A
Rev. 1.0, 02/00, page 336 of 1141
16. 3. 5 Input Ca pture Sig nal Inputt i ng Ti ming
• Input Capt ure Si gnal Inputting T iming
As for the input ca pture signal inputting, rising or falling e dge is selected by settings of the
IEDGA through IEDGD bit s of t he TCRX.
Figure 16. 7 shows the t iming chart when the rising e dge is selected (IEDGA through IEDGD =
1).
Input capture signal
inputting pin
φ
Input capture signal
Fi g ure 16.7 Input Capture Sig nal Input ting Timing (under norm al sta te)
• Input Capt ure Si gnal Inputting T iming whe n Maki ng Buffer Opera tion
Buffer operatio n can be made using the ICRA or ICRD as the buffer of the ICRA or ICRB .
Figure 16. 8 shows the i nput ca pture signa l inputting timing chart in case both of the rising and
falling edges are designated (IEDGA = 1 and IEDGC = 0, or IEDGA = 0 and IEDGC = 1),
using the ICRC as the buffer register for the ICRA (BUFEA = 1).
Input capture
signal
FTIA
FRC
ICRA
ICRC
n n+1 N
Mn
mM
n
M
N
n
φ
Fi g ure 16.8 Input Capture Sig nal Input ting Timing Char t Under the Buffer Mode
(under normal state)
Rev. 1.0, 02/00, page 337 of 1141
Even when the ICRC or ICRD is used as the buffer re gister, the input capture flag will be set up
corresponding to the designa ted edge change of respective input capture signals.
For example, when using t he ICRC as the buffer register for the ICRA, when an edge cha nge
having been designated by the IEDGC bit is detected with the input capture signals C and if the
ICIEC bit is duly set, an interrupt re quest wi l l be issued.
However, in this case, the FRC value will not be transferred to the ICRC.
16. 3. 6 Input Ca pture Flag (ICFA throug h ICFD) Sett i ng Up Timing
The input capture signal works t o set the ICFA through ICFD to 1 and, simultaneousl y, the FRC
value is transferr ed to the corr espondi ng ICRA thro ugh ICRD. Figure 16.9 shows the timing
chart.
Input capture
signal
ICFA to ICFD
ICRA to ICRD
FRC
N
N
φ
Fi g ure 16.9 ICFA throug h ICFD Se tti ng Up Timing
Rev. 1.0, 02/00, page 338 of 1141
16.3.7 O utput Compari ng Fl ag (OCFA and OCF B) Setti ng Up Timing
The OCFA and OCFB are being set to 1 by the comparing match signal being output when the
values of the OCRA, OCRB and FRC match. The comparing match signal is generated at the last
state of the value match (the timing of the FRC's updating the matching count reading).
After the values of the OCRA, OCRB and FRC match, up until the count up clock signal is
generated, the comparing match signal will not be issued. Figure 16.10 shows the OCFA and
OCFB setting timing chart.
Comparing match
signal
OCFA, OCFB
OCRA, OCRB
FRC N
N
N+1
φ
Figure 16.10 OCF Setti ng Up Timing
16.3.8 Overflow Flag (CVF) Setting Up Ti mi ng
The OVF i s set to when the FRC overflows ( H'FFFF → H'0000). Figure 16. 11 shows the timi ng
chart.
Overflowing
signal
FRC H'FFFF H'0000
OVF
φ
Figure 16.11 OVF Setti ng Up Timing
Rev. 1.0, 02/00, page 339 of 1141
16.4 Op erat ion Mod e of Timer X1
Table 16.4 indicated below shows the operation mode of Timer X1.
Table 16. 4 Operation Mode of Ti mer X1
Operation
Mode Reset Active Sleep Watch Subactive Standby Subsleep Module
Stop
FRC Reset Functions Functions Reset Reset Reset Reset Reset
OCRA, OCRB Reset Functions Functions Reset Reset Reset Reset Reset
ICRA to ICRD Reset Functions Functions Reset Reset Reset Reset Reset
TIER Reset Functions Functions Reset Reset Reset Reset Reset
TCRX Reset Functions Functions Reset Reset Reset Reset Reset
TOCR Reset Functions Functions Reset Reset Reset Reset Reset
TCSRX Reset Functions Functions Reset Reset Reset Reset Reset
Rev. 1.0, 02/00, page 340 of 1141
16.5 Interrupt Causes
Total seven interrupt c auses e xi st wit h Timer X1, namely, ICIA through ICID, OCIA, OCIB and
FOVI. Table 16. 5 lists the con ten t s of inter rupt cau se s. Interr upt re quests can be permitted or
prohibited by setting interrupt ena bling bi t s of the TIER. Also, independent vector addre sses are
allocated t o respective interrupt causes.
Tabl e 16. 5 Inte r r upt Cause s of Timer X1
Abbreviations of the I nt errupt Causes Priority Degree Contents
ICIA Interrupt reques t by the ICFA
ICIB Interrupt reques t by the ICFB
ICIC Inte rrupt request by the ICFC
ICID Inte rrupt request by the ICFD
OCIA Inte rrupt request by the OCFA
OCIB Inte rrupt request by the OCFB
FOVI Inte rrupt request by the OVF
High
Low
Rev. 1.0, 02/00, page 341 of 1141
16.6 Exemp lary Uses of Timer X1
Figure 16. 12 shows an exa m ple of outputting at optional phase difference of the pul ses of t he 50%
duty. For this setting, follow the procedures listed be low.
1. Set the CC LR A bit of the TC S R X to 1.
2. Each time a comparin g match occurs, the O LVIA bit and th e O LVLB bi t are r ever sed by use
of the software.
H'FFFF
OCRA
OCRB
H'0000
FTOA
FTOB
Clearing the
counter
FRC
Figure 16.12 Pulse O utputting Example
Rev. 1.0, 02/00, page 342 of 1141
16.7 P recau t io ns wh en Usi ng Timer X1
Pay great attention to the fac t that the follow ing competi tions and operations occ ur durin g
operation of timer X1.
16.7.1 Competition between Wr iting and Cle aring with the FRC
When a counter clearing signal is issued under the T2 state where the FRC is under the writing
cycle, writing into the FRC will not be effected and the priority will be given to clearing of the
FRC.
Figure 16. 13 shows the timi ng chart.
Address FRC address
Internal writing
signal
Counter clearing
signal
FRC N H'0000
T1 T2
Writing cycle with the FRC
φ
Figure 16.13 Competition between Writing and Clearing wi th the F RC
Rev. 1.0, 02/00, page 343 of 1141
16.7.2 Competition be tween Writing and Counting Up with the FRC
When a counting up cause occurs under the T2 state where the FRC is under the writing cycle, the
counting up will not be effected and the priori ty will be give n to count writing.
Figure 16. 14 shows the timi ng chart.
Address
φ
FRC address
Internal writing
signal
Inputting clock
to the FRC
Writing data
FRC N M
T1 T2
Writing cycle with the FRC
Figure 16.14 Competition between Writing and Counting Up with the FRC
Rev. 1.0, 02/00, page 344 of 1141
16.7.3 Competition be tween Writing and Comparing Matc h with the OCR
When a comparing match occurs under the T2 state where the OCRA and OCRB are under the
writing cycle, the priority will be given to writing of the OCR and the comparing match signal will
be prohibi ted.
Figure 16. 15 shows the timi ng chart.
φ
Address OCR address
Internal writing
signal
Comparing match
signal
FRC
Writing data
Will be prohibited
OCR N M
N N+1
T1 T2
Writing cycle with the OCR
Figure 16.15 Competition between Writing and Compar ing Match with the OCR
Rev. 1.0, 02/00, page 345 of 1141
16. 7. 4 Cha ng i ng Over t he Inter nal Cloc ks and Counter Opera tions
Depen ding on the timing of ch anging ov er the int er nal clock s , the FRC may count up. Table 16.6
shows the relations be tween the timing of changing over the interna l clocks (Re-writing of the
CKS1 and CKS0) and the FRC operations.
When using an internal clock, the counting clock is being generated detecting the falling edge of
the internal clock di viding the syst em clock (φ). For this reason, like Item No. 3 of tabl e 16.6,
count clock signals are issu ed deem ing th e timing befor e the chang eov er as the falling edge to
have the FRC to count up.
Also, when changing over between an internal clock and the external clock, the FRC may count
up.
Table 16.6 Changing Over the Internal Clocks and the FRC Operation
No. Rewriting Timing for
the CKS1 and CKS0 FRC Operati on
1 Low → low level
changeover
Clock before
the changeover
Clock after
the changeover
Count
clock
FRC
Rewriting of the CKS1 and CKS0
N N+1
2 Low → High level
changeover
Clock before
the changeover
Clock after
the changeover
Count
clock
FRC
Rewriting of the CKS1 and CKS0
N N+1 N+2
Rev. 1.0, 02/00, page 346 of 1141
No. Rewriting Timing for
the CKS1 and CKS0 FRC Operation
3 High → lo w le vel
changeover
Clock before
the changeover
Clock after
the changeover
Count
clock
FRC
Rewriting of the CKS1 and CKS0
N
*
N+1 N+2
4 High → high level
changeover
Clock before
the changeover
Clock after
the changeover
Count
clock
FRC
Rewriting of the CKS1 and CKS0
N N+1 N+2
Note: * The count clock s ignals are issued determining the changeover timing as the falling
edge to have the FRC to count up.
Rev. 1.0, 02/00, page 347 of 1141
Section 17 Watchdog Timer (WDT)
17.1 Overview
This LSI ha s an on-chip watchdog time r with one channel (WDT ) for m onitoring syste m
operation. The WDT outputs an overflow signal if a system crash prevents the CPU from writing
to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an
internal reset signal or i nternal NMI i nterrupt signal.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer mo d e, an in terval timer int er rupt is generated each time the co unter ov er flows .
17.1.1 Features
WDT features are list ed b e lo w .
• Sw itchable be tw ee n w atchdog timer mode and inte rva l timer mode
WOVI interrup t gen eration in interv al timer mod e
• Internal reset or int ernal interrupt gene rated whe n the timer counter overfl ows
Choice of internal reset or NMI i nterrupt generation in watchdog ti mer mode
• Choice of 8 counte r input clocks
Maximum WDT interval: system clock period × 131072 × 256
Rev. 1.0, 02/00, page 348 of 1141
17.1.2 Block Diagram
Figure 17. 1 shows block di a gram of WDT.
Overflow
Interrupt
control
•
Reset
control
WOVI
(Interrupt request signal)
Internal reset signal*
WTCNT WTCSR
φ / 2
φ / 64
φ / 128
φ / 512
φ / 2048
φ / 8192
φ / 32768
φ / 131072
Clock Clock
select
Internal clock
source
Bus
interface
Module bus
WTCSR
WTCNT
Note: * The internal reset signal can be generated by means of a register setting.
: Timer control/status register
: Timer counter
Internal bus
WDT
[Legend]
Internal NMI
interrupt request signal
Figure 17.1 Block Diagram of WD T
Rev. 1.0, 02/00, page 349 of 1141
17.1.3 Regi ster Configur ati on
The WDT has two registers, as described in table 17.1. These registers control clock selection,
WDT mode switching, the reset signal, etc.
Table 17. 1 WDT Registers
Address*1
Name Abbre v . R/W Initial Value Write*2 Read
Watchdog timer
control/status register WTC S R R/ (W)*3 H'00 H'FFBC H'FFBC
Watchdog tim er counter WTCNT R/ W H'00 H'FFBC H'FFBD
Syst em control register SYSCR R/ W H'09 H'FFE8 H'FFE8
Notes: 1. Lower 16 bits of the address.
2. For details of write oper ations, see section 17.2.4, Not es on Regist er Access.
3. O nly 0 can be written in bit 7, to clear t he flag.
Rev. 1.0, 02/00, page 350 of 1141
17.2 Regi ster Descri pt i on s
17.2.1 Watchdog Timer Counter (WTCNT)
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit :
Initial value :
R/W :
TCNT is an 8-bit readable/writable* up-counter.
When the TME bit is set to 1 in WTCSR, WT CNT sta rts counting pulses generated from the
internal clock source selected by bits CKS2 to CKS0 i n W T CSR. When the c ount overfl ows
(changes from H'FF to H'00), the OVF fl a g in W T C SR is set to 1.
WTCNT is initialized to H'00 by a reset, or when the TME bit is cleared to 0.
Note: * WTCNT is write-protect ed by a password to prevent accidenta l overwriting. For
details see section 17.2.4, Notes on Register Access.
17.2.2 Watchdog Timer Contr o l/Status Register (WTCSR)
7
OVF
0
R/(W)*
6
WT/
0
R/W
5
TME
0
R/W
4
—
0
—
3
RST/
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
WTCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to
be input to W TC N T, and th e time r mo de.
WTCSR is initialized to H'00 by a reset.
Note: * WT CSR is write-protected by a password to preve nt accidental overwriting. For
details see section 17.2.4, Notes on Register Access.
Rev. 1.0, 02/00, page 351 of 1141
Bit 7Overflow Flag (OVF ): A status flag t hat indicates t hat WT CNT has overflowed from
H'FF t o H'00.
Bit 7
OVF Description
0 [Clearing conditions] (Initial value)
1 . Wri te 0 in t he TME bi t
2. Read WTCSR when O VF = 1, then write 0 in OVF
1[Setting condition]
When WTCNT overflows ( changes from H'FF to H'00)
When internal reset request generat ion is select ed in watc hdog timer mode, OVF is
cleared automatically by the inter nal reset
Bit 6Timer Mode Select (WT/
,7
,7
): Sel ects whet her the W DT is use d as a watchdog ti mer or
interval timer. If used as an interval time r, the WDT generates an i nterval timer interrupt reque st
(WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates a reset or NMI
interrupt when TCNT overfl ows.
Bit 6
WT/
,7
,7
Description
0Int erval timer mode: Sends t he CPU an interval timer interrupt request (WOVI) when
WTCNT overf lows (Init ia l value)
1 Watchdog tim er mode: Sends t he CPU a reset or NMI interrupt request when
WTCNT overflows
Bit 5Timer Enable (TME): S e le cts whether WTCNT runs or is halted .
Bit 5
TME Description
0 W TCNT is init ializ e d to H'00 and halted (Initial value)
1 W TCNT counts
Bit 4Reserved: This bit should not be set to 1.
Rev. 1.0, 02/00, page 352 of 1141
Bit 3Reset or NMI (RST/
10,
10,
): Specifies whether an int ernal reset or NMI interrupt is
requested on WTCNT over flow in watchdo g timer mod e.
Bit 3
RST/
1
10
0,
,
Description
0 An NMI interrupt r equest is generated (Init ial value)
1 An internal r eset request is generated
Bits 2 to 0Clock Select 2 to 0 (CK S2 to CKS0): These bits select an internal clock source,
obtained by dividing the system clock (φ) for input t o WTCNT.
WDT Input Clock Selec tion
Bit 2 Bi t 1 Bi t 0 Descripti on
CSK2 CSK1 CSK0 Clock O v erflow Peri od* (when φ = 10 MHz)
0φ/2 (Initial
value) 51.2 µs0
1φ/64 1.6 ms
0φ/128 3.3 ms
0
11φ/ 512 13. 1 ms
0φ/ 2048 52. 4 ms01φ/8192 209.7 ms
0φ/32768 838.9 ms
1
1
1φ/ 131072 3. 36 s
Note: * The overflow period is the time from when WTCNT starts counting up fr om H'00 until
overflow occurs.
Rev. 1.0, 02/00, page 353 of 1141
17. 2. 3 Sy st e m Contro l Regi ster (SYSCR)
7
—
0
—
6
—
0
—
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
0
—
1
—
2
—
0
—
1
—
0
—
Bit :
Initial value :
R/W :
Only bit 3 is descri bed here. For details on functions not related to the wat chdog tim er, see
sections 3. 2.2 and 6.2. 1, System Control Register (SYSCR), and the descri ptions of the relevant
modules.
Bit 3External Reset (XRST): Indicates the reset source. When the wa tchdog timer is used, a
reset can be generated by watchdog timer ove rflow in addition t o external rese t input. XRST is a
read-only bit. It is set to 1 by an external re set, and cle a red to 0 by watchdog timer overflow.
Bit 3
XRST Description
0 Reset is gener ated by watchdog tim er overflow
1 Reset is gener ated by external r eset input ( Initial value)
Rev. 1.0, 02/00, page 354 of 1141
17.2.4 Notes on Register Access
The watchdog timer's WTCNT and WTCSR registers differ from other registers in being more
difficult t o write t o. The procedures for writi ng to and reading these registers are given be l ow.
• Writing to WTCNT and WTCS R
These registers must be written to by a word transfer instruction. They cannot be written to
with byte transfer instructions.
Figure 17. 2 shows the format of data written t o W T CNT a nd WTCSR. W TCNT and WTCSR
both have the same write address. For a write to WTCNT, the upper byte of the written word
must contain H'5A and the lower byte must contain the write data. For a write to WTCSR, the
upper byte of the written word must contain H'A5 and t he lower byte m ust contain the write
data. This transfers the write data from the lower byte to WTCNT or WTCSR.
<WTCNT write>
<WTCSR write>
Address : H'FFBC
Address : H'FFBC
H'5A Write data
15 8 7 0
0
H'A5 Write data
15 8 7 0
0
Figure 17.2 Format of Data Written to WTCNT and WTCSR
• Reading WTCNT and WTCSR
These registers are read in the same way as other registers. The read addresses are H'FFBC for
WTCSR, and H'FFBD for WTC NT.
Rev. 1.0, 02/00, page 355 of 1141
17.3 Operation
17.3.1 Watchdog Timer Oper ation
To use the WDT as a watchdog timer, set the WT/
,7
and TME bits in WTCSR to 1. Software
must prevent W TCNT overfl ows by rewriting the WTCNT value (normally by wri t ing H'00)
before overflow occurs. T his ensure s that WTCNT does not overfl ow while the system i s
operating normally. If WTCNT overflows without being rewritten because of a system crash or
other error, the chip i s reset , or an NMI interrupt is gene rated, for 518 system cl ock periods (518
φ). This is illustrated in figure 17.3.
An interna l reset request from the wa tchdog timer and re set input from the
5(6
pin are handled
via the same vector. The reset source can be identified from the value of the XRST bit in SYSCR.
If a re set caused by an input signal from the
5(6
pin and a rese t caused by WDT overflow occ ur
simultaneously, the
5(6
pin rese t has priority, and the XRST bit in SYSCR is set to 1.
WTCNT value
H'00 Time
H'FF
WT/ =1
TME=1 H'00 written
to WTCNT WT/ =1
TME=1 H'00 written
to WTCNT
518 system clock period
Internal reset
signal
WT/
TME
[Legend]
Overflow
Internal reset
generated
OVF=1*
: Timer mode select bit
: Timer enable bit
Note: * Cleared to 0 by an internal reset when OVF is set to 1. XRST is cleared to 0.
Figure 17.3 Operation in Watchdog Timer Mode (when Reset)
Rev. 1.0, 02/00, page 356 of 1141
17.3.2 Interval Timer Operation
To use the WDT as an interval timer, clear the WT/
,7
bit in WTCSR to 0 and set the TME bit to
1. An interval ti mer interrupt (WOVI) is generated each time WTCNT ove rflows, provided that
the WDT is operating as an interval timer, as shown in fi gure 17.4. This function c a n be used to
generate interrupt requests at regular intervals.
WTCNT value
H'00 Time
H'FF
WT/IT=0
TME=1 WOVI
Overflow Overflow Overflow Overflow
WOVI : Interval timer interrupt request generation
WOVI WOVI WOVI
Figure 17.4 Operation in Interval Timer Mode
Rev. 1.0, 02/00, page 357 of 1141
17.3.3 Timing of Setting of Overflow Flag (OVF)
The OVF bit in WTCSR is set to 1 if WTCNT overflows during interval timer operation. At the
same time, a n interval time r interrupt (WOVI) is requested. This timing is shown in figure 17.5.
If NMI request generation is selected in watchdog t imer mode, when WT CNT overflows the OVF
bit in WT CSR is set to 1 and at t he same time an NMI interrupt is requested.
CK
WTCNT H'FF H'00
Overflow signal
(internal signal)
OVF
Figure 17.5 Timing of OVF Setting
Rev. 1.0, 02/00, page 358 of 1141
17.4 Interrupts
During inte rval timer mode operation, an overfl ow generates an i nterval timer i nterrupt (W OVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in W TCSR. OVF must
be cleared to 0 in the interrupt handl ing routi ne. W hen NMI interrupt reque st ge neration is
selected in watchdog timer mode, an overfl ow ge nerates an NMI interrupt request.
17.5 Usage Notes
17.5.1 Contention between Watc hdog Timer Counter (WTCNT) Write and Inc rement
If a timer counter clock pulse is generated during the T2 state of a WTCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 17.6 shows this operation.
Internal address
Internal φ
Internal write
signal
WTCNT input
clock
WTCNT NM
T
1
T
2
WTCNT write cycle
Counter write data
Fi g ure 17.6 Conte nt ion be t ween WTCNT Write and Incre ment
Rev. 1.0, 02/00, page 359 of 1141
17. 5. 2 Cha ng i ng Value of CKS2 to CKS0
If bits CKS2 to CKS0 in WTCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the value of bits CKS2 to CKS0.
17. 5. 3 Switc hing between Watchdo g Timer Mode and Int erv a l Timer Mode
If the mode i s switched from watchdog timer to i nterval timer, or vice versa, while the WDT is
operating, correct ope ration cannot be guara nteed. Software must stop the watchdog timer (by
clearing the TME bit to 0) before switchin g the mode.
Rev. 1.0, 02/00, page 361 of 1141
Section 18 8-Bit PWM
18.1 Overview
The 8-bit PWM incorporat e s 4 channels of the dut y control method. Its outputs ca n be used to
control a reel motor or loading mot or.
18.1.1 Features
• Convers ion per iod: 256-s ta te
• Duty control method
18.1.2 Block Diagram
Figure 18. 1 shows a bloc k diagram of the 8-bit PWM (1 cha nnel).
PWMn
(n=3 to 0)
2
0
2
7
OVF
Match signal
[Legend]
PWRn
φ
PW8CR: 8-bit PWM data register n
: 8-bit PWM control register
PWMn
OVF : 8-bit PWM square-wave output pin n
: Overflow signal from FRC lower 8-bit
PWRn
Free-running counter (FRC)
Comparator
PW8CR
Polarity
specification
Internal data bus
R
S
Q
Figure 18.1 Block Diagr am of 8-Bit PWM (1 channel)
Rev. 1.0, 02/00, page 362 of 1141
18.1.3 Pin Confi guration
Table 18. 1 shows the 8-bit PWM pin configuration.
Table 18. 1 Pin Configuration
Name Abbrev. I/O Function
8-bit PWM squar e- wave output pin 0 PWM0 O utput 8-bit PWM square-wave output 0
8-bit PWM squar e- wave output pin 1 PWM1 O utput 8-bit PWM square-wave output 1
8-bit PWM squar e- wave output pin 2 PWM2 O utput 8-bit PWM square-wave output 2
8-bit PWM squar e- wave output pin 3 PWM3 O utput 8-bit PWM square-wave output 3
18.1.4 Register Configurati on
Table 18. 2 shows the 8-bit PWM register c onfiguration.
Table 18. 2 8-Bit PWM Registers
Name Abbr ev. R/W Size Initial Value Address*
8-bit PWM data regist er 0 PWR0 W Byte H'00 H'D126
8-bit PWM data regist er 1 PWR1 W Byte H'00 H'D127
8-bit PWM data regist er 2 PWR2 W Byte H'00 H'D128
8-bit PWM data regist er 3 PWR3 W Byte H'00 H'D129
8-bit PWM cont r ol register PW8CR R/W Byte H'F0 H'D12A
Port mode register 3 PM R3 R/W Byt e H'00 H'FFD0
Note: * Lower 16 bits of the address.
Rev. 1.0, 02/00, page 363 of 1141
18.2 Regi ster Descri pt i on s
18.2.1 8-bit PWM Data Registers 0, 1, 2 and 3 (PWR0, PWR1, P WR2, PWR3)
PWR0
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PW04 PW03 PW02 PW01 PW00
0
W
PW07
WWW
PW06 PW05
Bit :
Initial value :
R/W :
PWR1
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PW14 PW13 PW12 PW11 PW10
0
W
PW17
WWW
PW16 PW15
Bit :
Initial value :
R/W :
PWR2
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PW24 PW23 PW22 PW21 PW20
0
W
PW27
WWW
PW26 PW25
Bit :
Initial value :
R/W :
PWR3
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PW34 PW33 PW32 PW31 PW30
0
W
PW37
WWW
PW36 PW35
Bit :
Initial value :
R/W :
8-bit PWM data registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3) control the dut y cycle at 8-
bit PWM pins. The data written in PWR0, PWR1, PWR2 and PWR3 correspond to t he high-level
width of one PWM output wave form cyc le (256 states).
When data is set in PWR0, PWR1, PWR2 and PWR3, the contents of the data are latched in the
PWM waveform generators, updating the PWM waveform generation data.
PWR0, PWR1, PWR2 a nd PWR3 are 8-bit write-only registers. When rea d, all bits are a lways
read as 1.
PWR0, PWR1, PWR2 and PWR3 are initialized to H'00 by a reset.
Rev. 1.0, 02/00, page 364 of 1141
18.2.2 8-bit PWM Control Register (PW8CR)
0
0
1
0
R/W
2
0
R/W
3
0
4567 ————
————
PWC3 PWC2 PWC1 PWC0
R/WR/W
1111
Bit :
Initial value :
R/W :
The 8-bit PWM control re gister (PW8CR) is an 8-bit readable/writable regist er that cont rols PWM
functions. PW8CR is initialized t o H'00 by a rese t.
Bits 7 to 4Reserved: Thes e bits canno t be mo d ified an d are always r ead as 1.
Bits 3 to 0Outpu t Pola rity S el ect (PWC3 to PWC0): These bits select the output polarity of
PWMn pin between positive or negative (reverse).
Bit n
PWCn Description
0 PWMn pin output has positive polarity (Initial value)
1 PWMn pin output has negative polarity
(n = 3 to 0)
Rev. 1.0, 02/00, page 365 of 1141
18.2. 3 Po rt Mo d e Regis ter 3 (PM R 3)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PMR34 PMR33 PMR32 PMR31 PMR30
0
R/W
PMR37
R/W R/WR/W
PMR36 PMR35
Bit :
Initial value :
R/W :
The port mode register 3 (PMR3) c ontrols function switching of each pin in the port 3. Switching
is specified for each bit.
The PMR3 is a 8-bit re adable/writ able registe r and is ini tialized to H'00 by a reset.
For bits other than 5 to 2, see section 10. 5, Port 3.
Bits 5 to 2P35/PWM3 to P32/PWM0 P in Switc hing (PMR35 to PMR32): These bits set
whether the P3n/PWMn pin is used as I/O pin or it is used as 8-bit PWM output PWMm pin.
Bit n
PMR3n Description
0 P3n/PMWm pin functions as P3n I/O pin (Init ial value)
1 P3n/PMWm pin functions as PWMm output pin
(n = 5 to 2, m = 3 t o 0)
Rev. 1.0, 02/00, page 366 of 1141
18. 2. 4 Modul e Sto p Contr ol Regi ster (MSTP CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
The MSTPCR consists of two 8-bit readable/writable registers that control module stop mode.
When MSTP4 bit is set to 1, the 8-bit PWM stops its operation upon completion of the bus cycle
and transits to the module stop mode. For details, see section 4.5, Module Stop Mode.
The MST PC R is initial i ze d to H'FFFF by a reset.
Bit 4Module Stop (MST P4): This bit sets the module stop mode of the 8-bit PWM.
MSTPCRL
Bit 4
MSTP4 Description
0 8-bit PWM module stop mode is r eleased
1 8-bit PWM module stop mode is set (Initial value)
Rev. 1.0, 02/00, page 367 of 1141
18.3 8-Bit P WM Operation
The 8-bit PWM outputs PWM pul ses ha ving a cycle length of 256 states and a pulse width
determined by the dat a registers (PWR).
The output PWM pulse can be conve rted to a DC voltage through integration in a l ow-pass filter.
Figure 18. 2 shows the output wave form exa mple of 8-bit PWM. The pul se widt h (Twidth) c an be
obtained by the following expression:
Twidth = (1/φ) × (PWR setting value)
T width
Pulse width
T width
Pulse cycle
(256 states)
T width
Pulse width
T width
Pulse cycle
(256 states)
H'00
PWRn setting
value
H'FFFRC lower
8-bit value
PWRn pin
output (Positive
polarity)
(n=3 to 0)
(Negative
polarity)
Figure 18.2 8-bit PWM Output Waveform (Example)
Rev. 1.0, 02/00, page 369 of 1141
Section 19 12-Bit PWM
19.1 Overview
The 12-bit PWM incorporat e s 2 channels of the pul se pitch control method and functions as t he
drum and capstan mot or controller.
19.1.1 Features
Two on-chip 12-bit PWM signal generators are provided to control mot ors. These PWMs use t he
pulse-pitch control method (periodi cally overri ding part of the output). This reduce s low-
frequency components in the pulse output, enabling a quick response without increasing the clock
frequency. The pi tch of t he PWM signal is modified in response to error dat a (represe nting le a d
or lag in relation to a preset speed and phase).
Rev. 1.0, 02/00, page 370 of 1141
19.1.2 Block Diagram
Figure 19. 1 shows a bloc k diagram of the 12-bit PWM (1 channel). The PWM signal is generated
by combining qua ntizing pulses from a 12-bit pulse gene rator wit h quantizing pul ses derived from
the co ntents of a data register. Low-frequency com pone nts ar e redu ced bec ause the two
quantizing pulses have different frequencies. T he error data is represented by an unsigned 12-bit
binary number.
Internal data bus
[Legend]
Note: * Refer to section 26, Servo Circuit.
CAPPWM
or
DRMPWM
CAPPWM
φ/2
φ/4
φ/8
φ/16
φ/32
φ/64
φ/128
DRMPWM : Capstan mix pin
: Drum mix pin
PWM control register
Digital filter
circuit
Error data
PTON
PWM data register
Output control circuit
Pulse generator
Counter
DFUCR
CP/
Figure 19.1 Block Diagr am of 12-Bit PWM (1 c hannel)
Rev. 1.0, 02/00, page 371 of 1141
19.1.3 P i n Confi guration
Table 19. 1 shows the 12-bit PWM pin configurati on.
Table 19. 1 Pin Configuration
Name Abbrev. I/O Function
Capstan mix CAPPWM
Drum mix DRMPWM Output 12-bit PWM square-wave output
19.1.4 Register Configurati on
Table 19. 2 shows the 12-bit PWM register c onfiguration.
Table 19. 2 12-Bit PWM Registers
Name Abbrev. R/W Size I nit i al Value Address*
CPWCR W Byte H'42 H'D07B
12-bit PWM control register
DPWCR W Byte H'42 H'D07A
CPWDR R/W Word H'F000 H'D07C12-bit PWM dat a register DPWDR R/W Word H'F000 H'D078
Note: * Lower 16 bits of the address.
Rev. 1.0, 02/00, page 372 of 1141
19.2 Regi ster Descri pt i on s
19.2.1 12-Bit PWM Control Regi sters (CP WCR, DPWCR)
CPWCR
0
0
1
1
W
2
0
W
3
0
4
0
W
0
W
56
1
7CH/L CSF/DF CCK2 CCK1 CCK0
0
W
CPOL
WWW
CDC CHiZ
Bit :
Initial value :
R/W :
DPWCR
0
0
1
1
W
2
0
W
3
0
4
0
W
0
W
56
1
7DH/L DSF/DF DCK2 DCK1 DCK0
0
W
DPOL
WWW
DDC DHiZ
Bit :
Initial value :
R/W :
CPWCR is the PWM output control register for the capstan motor. DPWCR is the PWM output
control regi ster for the drum mot or. Bot h are 8-bit writable registe rs.
CPWCR and DPWCR a re initialized to H'42 by a rese t, or when in standby or module-stop mode.
Bit 7Polarity Invert (PO L): This bit can invert the polarity of the modulated PWM signal for
noise suppression and other purposes. This bit is i nvalid when fixed output is selected (whe n bit
DC is set to 1).
Bit 7
POL Description
0 Output with positive polarity (Initial value)
1 Output with inverted pol arity
Bit 6Out put Select ( DC): Selects either PWM modulated output, or fixed output controlled by
the pin output bits (bits 5 and 4).
Rev. 1.0, 02/00, page 373 of 1141
Bits 5 and 4PWM Pi n Ou t p ut (HiZ, H/ L ): When bi t DC is set t o 1, the 12-bit PWM output
pins (CAPPWM, DRMPWM) output a value determined by the HiZ and H/L bits. The output is
not affected by bit POL.
In powe r-down m ode s, the 12-bi t PWM circuit and pin statuses are retained. Before making a
transition to a power-down mode, first set bits 6 (DC), 5 (HiZ), and 4 (H/L) of the 12-bit PWM
control regi sters (CPWCR and DPWCR) to select a fixed output level. Choose one of t he
following settings:
Bit 6 Bit 5 Bit 4
DC HiZ H/L Output state
0 Low output (Initial value)01 High output
1
1 * High-impedance
0 * * Modulation signal output
Note: * Don't care
Bit 3Output Data Select (SF / DF): Selects whether the data to be converted to PWM output is
taken from the data registe r or from the digital filter ci rcuit.
Bit 3
SF/DF Description
0 Modulation by error data fr om the digit al f ilter circuit (Init ial value)
1 Modulation by error data written in the data register
Note: When PWM s output data from the digital filter circuit, the data consist ing of the speed and
phase filtering results are modulated by PW Ms and output from the CAPPWM and
DRMPWM pins. However, it is possible to output only drum phase filter r esults from
CAPPWM pin and only capstan phase f ilter result from DRMPWM pin, by DFUCR settings
of the digital f ilter circuit. See section 26.11, Digital Filters.
Rev. 1.0, 02/00, page 374 of 1141
Bits 2 to 0Carrier Frequency Se l ect (CK2 to CK0): Selects the carrier frequency of the PWM
modulated signal. Do not set them to 111.
Bit 2 Bit 1 Bit 0
CK2 CK1 CK0 Description
0φ20 1φ4
0φ8 (Initial value)
0
1
1φ16
0φ320
1φ64
0φ128
1
1
1 (Do not set)
Rev. 1.0, 02/00, page 375 of 1141
19.2.2 12-Bi t PWM Data Regi sters (DP WDR, CPWDR)
CPWDR
1
0
R/W
CPWDR1
0
0
R/W
CPWDR0
3
0
R/W
CPWDR3
2
0
R/W
CPWDR2
5
0
R/W
CPWDR5
4
0
R/W
CPWDR4
7
0
R/W
CPWDR7
6
0
R/W
CPWDR6
9
0
R/W
CPWDR9
8
0
R/W
CPWDR8
11
0
R/W
CPWDR11
10
0
R/W
CPWDR10
12
1
13
1
14
1
15
————
————
1
Bit :
Initial value :
R/W :
DPWDR
1
0
R/W
DPWDR1
0
0
R/W
DPWDR0
3
0
R/W
DPWDR3
2
0
R/W
DPWDR2
5
0
R/W
DPWDR5
4
0
R/W
DPWDR4
7
0
R/W
DPWDR7
6
0
R/W
DPWDR6
9
0
R/W
DPWDR9
8
0
R/W
DPWDR8
11
0
R/W
DPWDR11
10
0
R/W
DPWDR10
12
1
13
1
14
1
15
1
————
————
Bit :
Initial value :
R/W :
The 12-bit PWM data re gi sters (DPWDR and CPWDR) are 12-bit readable/writable regi sters
in which the data to be converted to PWM output is written.
The data in these registers is converted to PWM output only when bit SF/DF of the
corresponding control regi ster is set to 1. When the SF/ DF bit is 0, the error data from the
digital filter circuit is written in the data register, and then modulated by PWM. At this time,
the error data from the digital filter circuit can be monitored by reading the data register.
These registers can be accessed by word only, and cannot be accessed by byte. Byte access
gives unassured results.
Both registers are initialized to H'F000 by a reset.
Rev. 1.0, 02/00, page 376 of 1141
19.3 Operation
19.3.1 Output Waveform
The PWM signal ge nerator c ombines t he error data with the output from a n internal pul se
generator t o produc e a pul se-width modulated signal.
When Vcc/2 is set as the reference value, the following conditions apply:
1. When the mot or is running at the correct spee d and phase, the PW M signa l is output with a
50% duty cycle.
2. When the mot or is running behi nd the c orrect spe ed or phase, it is corrected by peri odically
holding pa rt of the PWM signal low. T he part held l ow depends on the size of the error.
3. When the mot or is running ahe a d of the c orrect speed or phase, i t is corrected by periodically
holding pa rt of the PWM signal high. The pa rt held high depends on the size of the e rror.
When the motor is running at the correct speed a nd pha se, the error data is a 12-bit value
representing 1/2 (1000 0000 0000), and the PWM output has the same freque ncy as the selected
division clock .
After the error data has been converted into a PWM signal, the PWM signal can be smoothed i nto
a DC voltage by an external low-pass filter (LPF). The smoothe error data ca n be used to control
the motor.
Figure 19. 2 shows sample wa veform out puts.
The 12-bit PWM pin outputs a low-level signal upon re set, in power-down mode or at m odule-
stop.
Rev. 1.0, 02/00, page 377 of 1141
1
Counter
Pulse Generator
PWM data register
C10
C11
C12
C13
Corresponds to Pwr3=1
Corresponds to Pwr2=1
Corresponds to Pwr1=1
Corresponds to Pwr0=1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Pwr3 2 1 0 "L"
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12
Figure 19.2 Samp le Wavef orm Outp ut by 12-B it PW M (4 Bits)
Rev. 1.0, 02/00, page 379 of 1141
Section 20 14-Bit PWM
20.1 Overview
The 14-bit PWM is a pulse division type PWM that ca n be used for electronic tuner c ontrol, etc.
20.1.1 Features
Features of the 14-bit PWM are given below:
• Choice of two conversion peri ods
A conversion period of 32768/φ with a minimum modulation width of 2/φ, or a conversi on
period of 16384/φ with a minimum modulation width of 1/φ, can be sele cted .
• Pulse division method for less ripple
Rev. 1.0, 02/00, page 380 of 1141
20.1.2 Block Diagram
Figure 20. 1 shows a bloc k diagram of the 14-bit PWM.
[Legend]
PWCR
φ/4
φ/2
PWDRL
: PWM control register
: PWM data register L
PWDRU
PWM14
: PWM data register U
: PWM14 output pin
Internal data bus
PWCR
PWDRL
PWDRU
PWM waveform
generator PWM14
Figure 20.1 Block Diagr am of 14-Bit PWM
20.1.3 Pin Confi guration
Table 20. 1 shows the 14-bit PWM pin configurati on.
Table 20. 1 Pin Configuration
Name Abbrev. I/O Function
PWM 14- bit square- wave out put pin PWM14* Output 14-bit PWM square-wave output
Note: * This pin also functions as P40 general I/O pin. When using this pin, set the pin function
by the port mode r egister 4 ( PMR4). For details, see section 10.6, Port 4.
Rev. 1.0, 02/00, page 381 of 1141
20.1.4 Regi ster Configur ati on
Table 20. 2 shows the 14-bit PWM register c onfiguration.
Table 20. 2 14-Bit PWM Registers
Name Abbr ev. R/W Size Initial Value Address*
PWM control register PWCR R/W Byte H'FE H'D122
PWM dat a register U PWDRU W Byte H'00 H'D121
PWM dat a register L PWDRL W Byte H'00 H'D120
Note: * Lower 16 bits of the address.
Rev. 1.0, 02/00, page 382 of 1141
20.2 Regi ster Descri pt i on s
20. 2. 1 PWM Contro l Regist er (PWCR)
0
0
1
1
2
1
3
1
4
1
5
1
6
1
7———————
——————— R/W
PWCR0
1
Bit :
Initial value :
R/W :
The PWM control register (PWCR) is an 8-bit read/ write register t hat cont rol s the 14-bit PWM
functions. PWCR is initialized to H' FE by a reset.
Bits 7 to 1Reserved: Thes e bits canno t be mo d ified an d are always r ead as 1.
Bit 0Clock Select (PWCR0): Selects the clock supplied to the 14-bit PWM.
Bit 0
PWCR0 Description
0 The input clock is φ/2 (tφ = 2/φ) (I nitial value )
The conversion period is 16384/φ, with a minimum modulation width of 1/φ
1The input clock is φ/4 (tφ = 4/ φ)
The conversion period is 32768/φ, with a minimum modulation width of 2/φ
Note: t/φ: Period of PWM clock input
Rev. 1.0, 02/00, page 383 of 1141
20. 2. 2 PWM Data Regi ster s U and L (PWDRU, PWDRL )
PWDRU
0
0
1
0
2
0
3
0
4
0
5
0
6
1
7——
—— W
PWDRU0
W
PWDRU1
W
PWDRU2
W
PWDRU3
W
PWDRU4
W
PWDRU5
1
Bit :
Initial value :
R/W :
PWDRL
0
0
1
0
2
0
3
0
4
0
5
0
67
W
PWDRL0
W
PWDRL1
W
PWDRL2
W
PWDRL3
W
PWDRL4
W
PWDRL5
0
W
PWDRL6
W
PWDRL7
0
Bit :
Initial value :
R/W :
PWM data registers U and L (PWDRU and PWDRL) indicate high level width in one PWN
waveform c ycle.
PWDRU and PWDRL form a 14-bit write-only registe r, with the upper 6 bit s assigne d to PWDRU
and the lower 8 bits to PWDRL. The value written in PWDRU and PWDRL gives the total high-
level width of one PWM waveform cycle. Both PWDRU and PWDRL are accessible by byte
acc e ss onl y. Wor d access g ive s una ssured resu lts.
When 14-bit data is written in PWDRU and PWDRL, the contents are latched in the PWM
waveform generator and the PW M waveform gene ration data is updated. When writing the 14-bit
data, follow these steps:
1. Write the lower 8 bits to PWDRL.
2. Write the upper 6 bits to PWDRU.
Write the data first to PWDRL and then to PWDRU.
PWDRU and PWDRL are wri t e-only re gisters. When read, all bits always read 1.
PWDRU and PWDRL are init i alized to H' C000 by a reset.
Rev. 1.0, 02/00, page 384 of 1141
20. 2. 3 Modul e Sto p Contr ol Regi ster (MSTP CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
The module stop c ontrol re gister (MSTPCR) consists of two 8-bi t reada ble/writable registers tha t
control the module stop mode func tions.
When the MSTP5 bit is set t o 1, the 14-bit PWM operation stops at the end of the bus cyc le and a
transition is made to module stop mode. For details, see section 4.5, Module Stop Mode.
MSTPCR is ini tial iz e d to H'FFFF by a reset.
Bit 5Module Stop (MST P5): Specifies t he modul e stop mode of the 14-bit PWM.
MSTPCRL
Bit 5
MSTP5 Description
0 14-bit PW M module stop mode is released
1 14-bit PWM module sto p mode is set (Initial value)
Rev. 1.0, 02/00, page 385 of 1141
20.3 14-Bit P WM Operation
When using the 14-bit PWM, set the registers in this sequence:
1. Set bit PWM40 to 1 in port mode register 4 (PMR4) so that pin P40/PWM14 i s designa ted for
PWM outp ut.
2. Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either
32768/φ (PWCR0 = 1) or 16384/ φ (PWCR0 = 0).
3. Set the output waveform data in PWM data registers U and L (PWDRU, PWDRL). Be sure to
write byte data first to PWDRL and then to PWDRU. When the data is written in PWDRU,
the contents of these registers are latched in the PWM waveform generator, and the PWM
waveform generation data is updated i n synchroni zation with i nternal signals.
One conversion period consists of 64 pulses, as shown i n figure 20.2. The t otal high-le vel width
during thi s period (TH) corresponds to the data in PWDRU and PWDRL. This relation can be
expressed as follow s :
TH = (data valu e in P WDRU and PWD RL + 64) × tφ/2
where to is the period of PWM clock input: 2/φ (bit PWCR0 = 0) or 4/φ (bit PWCR0 = 1).
If the data value in PWDRU and PWDRL is from H'3FC0 to H'3FFF, the PWM out put stays high.
When the data value is H' 0000, TH is calcula ted as fo llo w s :
TH = 64 × tφ/ 2 = 32 ⋅ tφ
t H64t H63t H3t H2t H1
T H = t H1 + t H2 + t H3 + ... + t H64
t f1 = t f2 = t f3 = ... = t f64
t f1 t f2 t f63 t f64
1 conversion period
Figure 20.2 Waveform Output by 14-Bit PWM
Rev. 1.0, 02/00, page 387 of 1141
Section 21 Prescalar Unit
21.1 Overview
The prescalar unit (PSU) has a 18-bit free running counter (FRC) that uses φ a s a clock sourc e and
a 5-bit counter that uses φW as a clo ck sourc e.
21.1.1 Features
• Presc al a r S (PSS)
Generates frequency di vision clocks that are input t o periphe ral funct i ons.
• Pr es calar W (PSW)
When a timer A is used as a clock time base, the PSW frequency-divides subclocks and
generates in put clo ck s .
• Stab le osci llation w ait time cou nt
During the return from the low power consumption mode excluding the sleep mode, the FRC
counts the stable oscillation wait ti me.
• 8-bit PWM
The lower 8 bit s of t he FRC is used as 8-bit PWM cycle and duty cycle generation counte rs.
(Conversion cycle: 256 states)
• 8-bit input ca pture by
,&
pins
Catches the 8 bits of 215 to 28 of the FRC according to the edge of the
,&
pin for remote contr ol
receiving.
• Frequency division clo ck output
Can output the freque ncy division clock for the system c lock or t he frequenc y division clock
for the subclock from the frequenc y division clock out put pin (T MOW).
Rev. 1.0, 02/00, page 388 of 1141
21.1.2 Block Diagram
Figure 21. 1 shows a bloc k diagram of the prescalar unit.
φ
PWM3
ICR1
PCSR
18-bit free running counter (FRC)
φw/128
Prescalar W
φ/131072 to φ/2
Prescalar S
Internal data bus
MSB LSB
φw/4
φw/8
φw/16
φw/32
φ/32 φ/16 φ/8 φ/4
Interrupt
request
5-bit counter
pin
Stable oscillation
wait time count output
2
12
2
15
2
8
2
7
2
7
2
0
TMOW
pin
MSB LSB
8 bits
6 bits 8 bits
PWM2
PWM1
PWM0
[Legend]
ICR1
PCSR : Input capture register 1
: Prescalar unit control/status register
TMOW : Input capture input pin
: Frequency division clock output pin
Figure 21.1 Block Diagram of Pr esca lar Unit
Rev. 1.0, 02/00, page 389 of 1141
21.1.3 P i n Confi guration
Table 21. 1 shows the pi n configuration of the prescalar uni t.
Table 21. 1 Pin Configuration
Name Abbrev. I/O Function
Input capture input
,&
Input Prescalar unit input capture input pin
Frequency divi si on clock
output TMOW Output Prescalar unit frequency division clock
output pin
21.1.4 Register Configurati on
Table 21.2 shows the register configuration of the prescalar unit.
Table 21. 2 Register Configurati on
Name Abbr ev. R/W Size Initial Value Address*
Input capture regist er 1 I CR1 R Byte H'00 H'D12C
Pres c a lar unit
control/status register PCSR R/W Byte H'08 H'D12D
Note: * Lower 16 bits of the address.
Rev. 1.0, 02/00, page 390 of 1141
21.2 Registers
21. 2. 1 Input Ca pture Regist e r 1 (ICR1)
0
0
1
0
R
2
0
R
3
0
4
0
R
0
R
56
0
7ICR14 ICR13 ICR12 ICR11 ICR10
0
R
ICR17
RRR
ICR16 ICR15
Bit :
Initial value :
R/W :
Input capture registe r 1 (ICR1) ca ptures 8-bit data of 215 to 28 of the FRC according to the edge of
the
,&
pin.
ICR1 is an 8-bit re ad-only regi ster. The writ e operation becomes inval i d. The ICR1 val ues are
undefined until the first capture is generated after the mode has been set to the standby mode,
watch mode, subactive mode, and subsleeve m ode. When re set, ICR1 i s initialized to H'00.
21.2.2 P resc alar Unit Control/Status Register (PCSR)
0
0
1
0
R/W
2
0
R/W
3
—
—
1
4
0
R/W
5
0
6
0
7
R/WR/W
ICEG
R/W
ICIE
0
R/(W)*
ICIF NCon/off DCS2 DCS1 DCS0
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
The prescalar unit control/sta tus register (PCSR) c ontrols the input capture function a nd selects the
frequency division clock tha t is output from t he TMOW pin.
PCSR is an 8-bit read/write enable register. When reset, PCSR is initialized to H'08.
Bit 7Input Capt ure Interr upt Fl a g (ICIF) : Input capture interrupt reque st flag. This indicates
that the input capture was performed according to the edge of the
,&
pi n.
Bit 7
ICIF Description
0[Clear condition] (Init ial value)
When 0 is written after 1 has been read
1 [Set c o ndit io n]
When the input capture was performed according to the edge of the
,&
pin
Rev. 1.0, 02/00, page 391 of 1141
Bit 6Input Capture Interrupt Enable (ICIE): W hen ICIF was set to 1 by the input capture
according to the edg e of the
,&
pin, ICIE ena bles and disables t he gene ration of an input ca pture
interrupt.
Bit 6
ICIE Description
0 Disables the generation of an input capture interrupt (Init ial value)
1 Enables the gener at ion of an input capture interrupt
Bit 5
,
,&
&
Pin Edge Select (ICEG): ICEG selects the input edge sense of the
,&
pin.
Bit 5
ICEG Description
0 Detects the falling edge of the
,&
pin input (Initial value)
1 Detects the rising edge of the
,&
pin input
Bit 4Noise Cancel ON/O FF (NCon/off): NCon/off selects enable/disable of the noise cancel
function of the
,&
pin. For the noise cancel function, see section 21.3, Noise Cancel Circuit.
Bit 4
NCon/off Description
0 Disables the noise cancel function of the
,&
pin (I n itial value )
1 Enables the noise cancel function of the
,&
pin
Bit 3Reserved: This bit cannot be m odified a nd is always read as 1.
Rev. 1.0, 02/00, page 392 of 1141
Bits 2 to 0Freque nc y Divisi o n Clock Output Sel ect (DCS2 to DCS0 ): DCS2 to DCS0 select
eight types of frequency division clocks that are output from the TMOW pin.
Bit 2 Bit 1 Bit 0
DCS2 DCS1 DCS0 Description
0 Outputs PSS, φ/32 ( Init ia l value )01 Outputs PSS, φ/16
0 Outputs PSS, φ/8
0
1
1 Outputs PSS, φ/4
0 Outputs PSW, φW/320
1 Outputs PSW, φW/16
0 Outputs PSW, φW/8
1
1
1 Outputs PSW, φW/4
Rev. 1.0, 02/00, page 393 of 1141
21.2. 3 Po rt Mo d e Regis ter 1 (PM R 1)
7
PMR17
0
R/W
6
PMR16
0
R/W
5
PMR15
0
R/W
4
PMR14
0
R/W
3
PMR13
0
R/W
0
PMR10
0
R/W
2
PMR12
0
R/W
1
PMR11
0
R/W
Bit :
Initial value :
R/W :
The port mode register 1 (PMR1) controls switching of each pin function of port 1. The switching
is specified in a unit of bit.
PMR1 is an 8-bit read/write enable register. When reset, PMR1 is initialized to H'00. For details,
refer to Port Mode Register 1 in section 10. 3.2 Regi ste r Configurat i on.
Bit 7P17/TMO W Pin Switching (PMR17): PMR17 sets whether the P17/TMOW pin is used
as a P17 I/O pin or a TMOW pin for division clock output.
Bit 7
PMR17 Description
0 The P17/TMOW pin functions as a P17 I/O pin (Initial value)
1 The P17/TMOW pin functions as a TMOW output function
Bit 6P16/
,
,&
&
Pin Switching (P MR16): PMR16 sets whether the P16/
,&
p in is used as a P1 6 I /O
pin or an
,&
pin for th e in put cap tu re inpu t o f the pr escala r un it.
Bit 6
PMR16 Description
0 The P16/
,&
pin functions as a P16 I/O pin (Init ial value)
1 The P16/
,&
pin functions as an
,&
input function
Rev. 1.0, 02/00, page 394 of 1141
21.3 Noi se Cancel Circu i t
The
,&
pin has a built-in a noise cancel circuit. The circuit can be used for noise protection such
as remote control receiving. The noise cancel circuit samples the input values of the
,&
pin tw ice
at an interval of 256 states. If the input values are different, they are assumed to be noise.
The
,&
pin ca n specify enable/disa ble of t he noise cancel function a ccording to the bit 4
(NCon/off) of the prescalar unit control /status regi ster (PCSR).
21.4 Operation
21.4.1 Prescalar S (P SS)
The PSS is a 17-bit counter that uses t he system clock (φ=fosc) as an input clock and generates the
frequency division clocks (φ/131072 to φ/2) of the peripheral func tion. The low-order 17 bits of
the 18-bit free running counter (FRC) correspond t o the PSS. The FRC i s increm e nted by one
clock. The PSS output i s shared by t he timer and serial com munication interface (SCI), and the
frequency division ratio ca n independently be set by e ach built-in peripheral function.
When reset, the FRC is initialized to H'00000, and sta rts increment after reset has bee n released.
Because the system clock oscillator is stopped in standby mode, watch mode, subactive mode, and
subsl eep mode, t he PSS opera ti on is al so st oppe d. In this ca se, t he FCR is also initi a li ze d to
H'00000.
The FRC cannot be rea d and written from the CPU.
Rev. 1.0, 02/00, page 395 of 1141
21.4.2 P rescalar W (PSW)
PSW is a counter that uses the subclock as an input clock. The PSW also generates the input
clock of the timer A. In this case, the timer A functions as a clock time base.
When reset, the PSW is initialized to H' 00, and starts increment after reset has been released.
Even if the mode has been shifted to the standby mode *, watch m ode *, subactive mode *, and
subsleep m ode *, the PSW continues the operation as long a s the clocks are supplied by the X1
and X2 pins.
The PSW can also be initialized to H'00 by setting the TMA3 and TMA2 bits of the timer mode
re gister A (TMA) to 11.
Note: * When t he timer A is in module stop mode, the ope ration is stopped.
Figure 21.2 shows the supply of the clocks to the periphe r al function by the PSS and PSW .
φ/131072 to φ/2
φTimer
SCI
OSC1 fosc
OSC2
φw/128
φw/4
φwTimer A
Prescalar S
X1 (fx)
X2 CPU
ROM
RAM
TMOW pin
Peripheral register
I/O port
Intermediate
speed clock
frequency divider
Prescalar W
System clock
selection
Subclock
frequency
dividers
(1/2, 1/4, and 1/8)
Subclock
oscillator
System
clock
oscillator
System
clock
duty
correction
circuit
Fi g ure 21.2 Clock Supply
21.4.3 Stable Oscillation Wai t Time Count
For the count of the stable oscillation stable wait time during the return from the low power
consumption mode excluding the sleep mode, see section 4, Power-Down State.
Rev. 1.0, 02/00, page 396 of 1141
21.4.4 8-bit PWM
This 8-bit PWM c ontrols the duty c ontrol PWM signal in t he conversion cycle 256 states. It
counts the cycle and t he duty c ycle at 27 to 20 of the FRC. It can be used for controlling ree l
motors and loading motors. For det ails, see section 18, 8-Bit PWM.
21. 4. 5 8 - bi t Input Ca pt ure Using
,&
,&
Pin
This function c atches the 8-bi t data of 215 to 28 of the FRC according to the edge of the
,&
pi n. It
can be used for remote control receiving.
For the edge of the
,&
pin, the rising and falling edges can be selected.
The
,&
pin has a built-in noise cancel circuit. See section 21.3, Noise Cancel Circuit.
An interrupt reque st is generated due to the input capture using the
,&
pin.
Note: Re writing the ICEG bit, NCon/ off bit, or PMR16 bit is i ncorrectly recognized a s edge
detection ac cording to the combinations be t ween the state and detection edge of the
,&
pin
and the ICIF bi t may be set a fter up t o 384φ seconds.
21. 4. 6 Freque ncy Divisi on Clock Output
The frequency division clock can be output from t he TMOW pin. For the frequency division
clock, eight types of clocks can be selected according to the DCS2 to DCS0 bits in PCSR.
The clock in which the system cl oc k was frequency-divided is output in ac tive mode a nd sleep
mode and the clock in which the subclock was frequency-divided is output in active mode*, sleep
mode*, and subactive mode.
Note: * When t imer A i s in module stop mode, no c lock is output.
Rev. 1.0, 02/00, page 397 of 1141
Section 22 Serial Communication Interface 1 (SCI1)
22.1 Overview
The serial communication interface (SCI) can handle both a synchronous and clocked synchronous
serial com munication. A function is al so provide d for serial com munication betwee n processors
(multiproc ess or communicat ion functio n).
22.1.1 Features
SCI1 features are l i sted bel ow.
• Choice of asynchronous or synchronous seri al communi cation mode
Asynchrono us mode
• Serial data communicati on is e xecuted using an asynchronous syst em in which
synchronization is achieved chara cter by character
Serial data com munication can be carried out with standard asynchronous
communication chips such a s a Universal Asynchronous Receiver/Transmitter (UART)
or Asynchronous Communication Inte rface Ada pter (ACIA)
• A multiprocessor communic ation func tion is provided that enables serial data
communication with a number of processors
• Choice of 12 se rial data transfe r formats
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Multiprocess or bit : 1 or 0
• Receive e rror de tection: Pa rity, overrun, and framing errors
• Break detection: Break can be detected by reading the SI1 pin level directly in case of a
framing error
Clock synchronous mode
• Serial data communicati on is synchronized with a cl ock
Serial data com munication can be carried out with other c hips t hat have a synchronous
communic ation func tio n
• One serial data transfer format
Data length: 8 bits
• Receive e rror de tection: Ove rrun errors detected
Rev. 1.0, 02/00, page 398 of 1141
• Full-duple x com mun ic ation capability
The transmitter and receiver are mutually independent, enabling transmission and reception
to be executed simultaneously
Double-buffe ring is used in both the transmit ter and the receiver, ena bling continuous
transmission and continuous reception of serial data
• Built-in baud rate genera t or allows any bit rate to be selected
• Choice of se rial clock sourc e: interna l clock from baud rate generator or external cl ock from
SCK1 pin
• Four interrupt sourc e s
Four interrupt sources (transmit-data-empty, transmit-end, receive-dat a -full, and re ceive
error) that can issue requests inde pendently
Rev. 1.0, 02/00, page 399 of 1141
22.1.2 Block Diagram
Figure 22. 1 shows a bloc k diagram of the SCI.
SI1
SO1
SCK1
Clock
External clock
φ
φ/4
φ/16
φ/64
TEI
TXI
RXI
ERI
RSR1
RDR1
TSR1
TDR1
SMR1
SCR1
SSR1
SCMR1
BRR1
: Receive shift register 1
: Receive data register 1
: Transmit shift register 1
: Transmit data register 1
: Serial mode register 1
: Serial control register 1
: Serial status register 1
: Serial interface mode register 1
: Bit rate register 1
SCMR1
SSR1
SCR1
SMR1
Transmission/
reception
control
Baud rate
generator
BRR1
Module data bus
Bus interface
Internal data bus
RDR1
TSR1RSR1
Parity generation
Parity check
[Legend]
TDR1
Figure 22.1 Block Diagram of SCI
Rev. 1.0, 02/00, page 400 of 1141
22.1.3 P i n Confi guration
Table 22. 1 shows the serial pins used by the SCI.
Tabl e 22. 1 SCI Pi ns
Channel Pin Name Symbol I/O Function
Serial clock pin 1 SCK1 I/O SCI1 clock input/output
Receive dat a pin 1 SI1 Input SCI1 receive data input
1
Transmit dat a pin 1 SO1 O utput SCI1 transmit data output
22.1.4 Register Configurati on
The SCI1 has the internal registers shown in table 22.2. These registers are used to specify
asynchronous mode or synchronous mode, the data form at, and t he bit rate, and to cont rol the
transmitter/receiver.
Tabl e 22. 2 SCI Reg i ster s
Channel Name Abbrev. R/W I nitial Value Address*1
Serial mode regist er 1 SMR1 R/ W H'00 H'D148
Bit rate register 1 BRR1 R/W H'FF H'D149
Seria l c ontrol regist er 1 SCR1 R/W H'0 0 H'D14A
Transmit dat a register 1 TDR1 R/W H'FF H'D14B
Serial status regist er 1 SSR1 R/ (W)*2H'84 H'D14C
Receiv e data register 1 RDR1 R H'00 H'D14D
1
Serial interface m ode register 1 SCMR1 R/ W H'F2 H'D14E
MSTPCRH R/W H'FF H'FFECCommon Module stop control regis ter MSTPCRL R/W H'FF H'FFED
Notes: 1. Lower 16 bits of the address .
2. O nly 0 can be written, to clear flags.
Rev. 1.0, 02/00, page 401 of 1141
22.2 Regi ster Descri pt i on s
22. 2. 1 Rec eive Shift Regist er 1 (RSR1 )
7
—
6
—
5
—
4
—
3
—
0
—
2
—
1
—
Bit :
R/W :
RSR1 is a register used to receive serial data.
The SCI set s serial da ta input from the SI1 pi n in RSR1 in the order received, starting with the
LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
trans ferre d to RDR auto matica lly.
RSR1 c a nnot be directly re ad or written to by the CPU.
22. 2. 2 Rec eive Da t a Reg i ster 1 ( RDR1)
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Bit :
Initial value :
R/W :
RDR1 is a register that stores received serial data.
When the SCI has received one byte of serial data, it transfers the received serial data from RSR1
to RDR1 where it is stored, and completes the receive operation. After this, RSR1 is receive-
enabled.
Since RSR1 and RDR1 function as a double buffer in t his way, cont i nuous re ceive operations can
be performed.
RDR1 is a read-only register, and cannot be written to by the CPU.
RDR1 is initialized to H'00 by a reset, and in standby mode, w atch mode, subactive mode,
subsleep m ode, and module st op mode.
Rev. 1.0, 02/00, page 402 of 1141
22. 2. 3 T r a nsm i t Shif t Register 1 (TSR1)
7
—
6
—
5
—
4
—
3
—
0
—
2
—
1
—
Bit :
R/W :
TSR 1 is a reg ister us ed to tra n s mit serial data.
To perform serial data transmission, the SCI first transfers transmit data from TDR1 to TSR1, then
sends the data to the SO1 pin starting with the LSB (bit 0).
Whe n tran smiss io n of on e by te is completed, the next transmit d ata is trans ferr ed fr o m TD R1 to
TSR1, and transmission st a rted, automatically. Howe ver, da ta transfe r from TDR1 to TSR1 is not
performed if the TDRE bit in SSR1 is set to 1.
TSR1 cannot be directly read or written to by t he CPU.
22. 2. 4 T r a nsm i t Data Regist er 1 (TDR1)
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit :
Initial value :
R/W :
TDR1 is an 8-bit re gister that stores data for serial tra nsmission.
When the SCI detects that TSR is empty, it transfers the transmit data written in TDR1 to TSR1
and starts serial transmission. Continuous serial transmission can be carried out by writing the
next transmit data to TDR1 during serial transmission of the data in TSR1.
TDR1 can be read or written to by the CPU at all times.
TDR1 is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode,
subsleep m ode, and module st op mode.
Rev. 1.0, 02/00, page 403 of 1141
22.2.5 Serial Mode Register 1 (SMR1)
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
Bit :
Initial value :
R/W :
SMR1 is an 8-bit registe r used to set the SCI's serial t ra nsfer format and select the baud rate
generator clock source.
SMR1 can be read or written to by the CPU at all times.
SMR1 is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode,
subsleep m ode, and module st op mode.
Bit 7Commun ica tion Mo de (C /
$
$
): Selects asynchronous mode or clock synchronous mode as
the SCI ope rating m ode.
Bit 7
C/
$
$
Description
0 Asynchronous mode (Initial value)
1 Clock synchronous mode
Bit 6Characte r Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode.
In sync hronous mode, a fixe d data length of 8 bits is used regardless of the CHR setting.
Bit 6
CHR Description
0 8-bit data (Init ial value)
1 7-bit data*
Note: * When 7-bit data is selected, the MSB ( bit 7) of TDR1 is not transm itted, and LSB-
first/MSB-first selection is not available.
Rev. 1.0, 02/00, page 404 of 1141
Bit 5Parity Enable (PE): In asynchronous m ode, selects whe t her or not parity bit addition is
performed in transmission, and pa rity bit checking in rec e ption. In sync hronous m ode, or when a
multiprocessor format is use d, parity bit addition and che c king is not performed, regardless of the
PE bit sett i n g.
Bit 5
PE Description
0 Parity bit addition and checking disabled ( I nit ial value)
1 Parity bit addition and checking enabled*
Note: * When the PE bit is set to 1, the par ity (even or odd) specif ied by the O/
(
bit is added to
transmit data before transmission. In reception, the parity bit is checked for the parity
(even or odd) specified by t he O/
(
bit.
Bit 4Parity Mode (O/
(
(
): Selects either eve n or odd parity for use i n parity a ddition and
checking.
The O/
(
bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and
checking, in asynchronous mode. The O/
(
bit setting is inva lid in synchronous mode, when pari ty
bit additi on and checking is disabl ed in asynchronous m ode, and when a multiprocessor format is
used.
Bit 4
O/
(
(
Description
0 Even parity*1 (Init ial value)
1 Odd parity*2
Notes: 1. When even parity is set, parity bit addition is performed in trans mission so tha t the total
number of 1 bit s in t he transmit character plus the parit y bit is even. In reception, a
check is perf ormed to see if the total number of 1 bits in t he receive character plus the
parity bit is even.
2. When odd parity is set, parity bit addition is performed in tr ansmission so that the total
number of 1 bit s in t he transmit character plus the parit y bit is odd. In reception, a
check is perf ormed to see if the total number of 1 bits in t he receive character plus the
parity bit is odd.
Rev. 1.0, 02/00, page 405 of 1141
Bit 3Stop Bi t Length (STOP ): Se lects 1 or 2 bits as the stop bit length in asynchronous mode.
The STOP bit setting is only valid in a synchronous mode. If sync hronous mode is set the STOP
bit setting is invalid since stop bits are not added.
Bit 3
STOP Description
0 1 stop bit*1 (I nit ial value)
1 2 stop bits*2
Notes: 1. I n transmission, a single 1 bit (stop bit) is added to t he end of a transmit char acter
before it is sent.
2. I n transmission, two 1 bits ( stop bits) are added to the end of a tr ansmit character
before it is sent.
In reception, onl y the first stop bit i s checke d, regardless of the STOP bi t setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Bit 2Mu lt iproc es sor Mode (MP): Selects mu ltipro cesso r format. When mu ltipro cessor format
is selected, the PE bit and O/
(
bit parity settings are invalid. The MP bit setting is only valid in
asynchronous mode; it is invalid in synchron ous mod e.
For details of the multiprocessor communication function, see section 22. 3.3, Multiprocessor
Communication Function.
Bit 2
MP Description
0 Mult iprocessor funct ion disabled (Init ial value)
1 Multiprocessor format select ed
Rev. 1.0, 02/00, page 406 of 1141
Bits 1 and 0Cloc k Select 1 and 0 (CKS1, CK S0): These bits select the clock source for the
baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to
the setting of bits CKS1 and CKS0.
For the relation between t he clock source, the bit rate regi ster setti ng, and the ba ud rate, see
sect ion 22 . 2.8, Bi t Rat e Register 1.
Bit 1 Bit 0
CKS1 CKS0 Description
0φ clo c k ( Initial value)0
1φ/4 clock
0φ/ 16 clock1
1φ/ 64 clock
22.2.6 Serial Control Register 1 (SCR1)
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Bit :
Initial value :
R/W :
SCR1 is a register t hat performs enabl i ng or disabling of SCI transfer operations, serial clock
output i n asynchronous mode, and interrupt requests, a nd selection of the seri al clock source.
SCR1 c a n be rea d or written to by the CPU at all times.
SCR1 is i nitialized to H'00 by a reset , and i n standby mode , watch mode, subactive mode,
subsleep m ode, and module st op mode.
Bit 7Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty i nterrupt
(TXI) request generation whe n serial transmit da ta is tra nsferred from T DR1 t o TSR1 and the
TDRE flag in SSR1 is set to 1.
Bit 7
TIE Description
0 Transmit-data-empty interrupt (TXI) request disabled* (I nit ial value)
1 Transmit-data-empty interrupt (TXI) request enabled
Note: * TXI interrup t reque st cancel lation can be performed by reading 1 from the TDRE flag,
then clearing it to 0, or clearing the TIE bit to 0.
Rev. 1.0, 02/00, page 407 of 1141
Bit 6Recei ve Inter r upt Enable ( RIE) : Enables or disables re ceive-data-full interrupt (RXI)
request a nd receive-error interrupt (ERI) re quest generation whe n serial receive data is transfe rred
from RSR1 to RDR1 and the RDRF flag in SSR1 is set to 1.
Bit 6
RIE Description
0 Receive-data -full in terrup t (RXI ) request and receive-erro r interrup t (ERI ) request
disabled* (Init ial value)
1Receive-da ta -full interrupt (RXI) request and receive-error in ter rup t (ERI) request
enabled
Note: * RXI and ERI interrupt request cancellation can be performed by reading 1 from t he
RDRF, FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0.
Bit 5Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Bit 5
TE Description
0 Transmission disabled*1 (Init ial value)
1 Transmission enabled*2
Not es: 1. The TDRE flag in SSR1 is fixed at 1.
2. In this state, serial transmission is started when transmit data is written to TDR1 and the
TDRE fla g in SSR1 is cleare d to 0.
SMR1 setting m ust be performed to decide the transm ission format before setting the
TE bit to 1.
Bit 4Receive Enabl e (RE): Enables or disables the start of serial reception by the SCI.
Bit 4
RE Description
0 Reception disabled *1 ( I nit ial value)
1 Reception enabled*2
Not e s: 1. Clearing the RE bit to 0 does not aff ect t h e RDRF, FER, PER, and ORER flags, which
retain their stat es.
2. Serial recept ion is started in t his state when a start bit is det ected in asynchronous
mode or serial clock input is detected in sy nchronous mode.
SMR1 setting m ust be performed to decide the reception format before setting t he RE
bit to 1.
Rev. 1.0, 02/00, page 408 of 1141
Bit 3Multiprocessor Interrupt Enable (MPIE): Enab les or disabl es multipro cessor interrupts.
The MPIE bit setting is only valid in a synchronous m ode when receiving with the MP bit in
SMR1 se t to 1.
The MPIE bit setting is i nvalid in cl ock synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE Description
0Multiprocess or interrupts disabled (normal reception performed) (I nitial value)
[Clearing condit ions]
1. When the M PI E bit is cleared to 0
2. When data with M PB = 1 is received
1Multiprocess or interrupts enabled*
Receive interrupt (RXI) requests, receive-err or interrupt (ERI) request s, and setting of
th e RDRF, FER, and ORER flags in SSR1 are disab le d until da ta with the
mu ltiproc e ssor b it s et to 1 is receiv e d.
Note: * When receive data including MPB = 0 is received, receive data transfer from RSR1 to
RDR1, receiv e error detection, and setting of the RDRF, FER, and O RER flags in
SSR1, is not performed. When receive data with MPB = 1 is received, the M PB bit in
SSR1 is set to 1, the M PI E bit is clear ed to 0 automatically, and generation of RXI and
ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER f lag
setting is enabled.
Bit 2Transmit End Interrupt Enable (TEIE): Enabl e s or disables tra nsmit-end interrupt
(TEI) request generation if there is no valid transmit data in TDR when the MSB is transmitted.
Bit 2
TEIE Description
0 Transmit-end interrupt (TEI) request disabled* (Init ial value)
1 Transmit-end interrupt (TEI) request enabled*
Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR1, then
clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
Rev. 1.0, 02/00, page 409 of 1141
Bits 1 and 0Cloc k Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock
source and enable or disable clock output from the SCK pin. The combination of the CKE1 and
CKE0 bits determines whether the SCK pin funct ions as an I/O port, the serial c lock output pin, or
the serial clock input pin.
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in
asynchronous mode. T he CKE0 bit setting is invalid in synchronous mode, and in the case of
external clock operation (CKE1 = 1). Note that the SCI's operating mode must be decided using
SMR1 before setting t he CKE 1 and CKE0 bits.
For details of clock source selection, see table 22.9 in section 22.3, Operation.
Bit 1 Bit 0
CKE1 CKE0 Description
Asynchronous m ode Int ernal clock/SCK pin functions as I/O port*1
0
Clock synchronous
mode Int ernal clock/SCK pin f unctions as serial
clock out put*1
Asynchronous m ode Int ernal clock/SCK pin functions as clock
output*2
0
1
Clock synchronous
mode Int ernal clock/SCK pin f unctions as serial
clock out put
Asynchronous m ode External clock/ SCK pin functions as clock
input*3
0
Clock synchronous
mode External clock/ SCK pin functions as serial
clock input
Asynchronous m ode External clock/ SCK pin functions as clock
input*3
1
1
Clock synchronous
mode External clock/ SCK pin functions as serial
clock input
Not es: 1. I nitial v a lu e.
2. O utputs a clock of the same frequency as the bit rate.
3. I nputs a clock wit h a frequency 16 times the bit rate.
Rev. 1.0, 02/00, page 410 of 1141
22.2.7 Serial Status Register 1 (SSR1)
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
SSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI, and
multiprocessor bits.
SSR1 can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags the y must be
read as 1 beforehand. The TEND flag a nd MPB fla g are read-only flags and cannot be modified.
SSR1 is initialized to H'84 by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
Bit 7Transmit Data Regi ster Empty (TDRE): Indicates that data has been transferred from
TDR1 to TSR1 and the next serial data can be written to TDR1.
Bit 7
TDRE Description
0[Clearing condit ions]
When 0 is written in TDRE after reading TDRE = 1
1 [Setting condition s] (Initial value)
1. When the TE bit in SCR is 0
2. When data is transferred from TDR1 to TSR1 and data can be written to TDR1
Bit 6Recei ve Dat a Regist er Full ( RDRF): Indicates t hat the rec eived data is st ored in RDR1.
Bit 6
RDRF Description
0 [Clearing conditions] (Initial value)
When 0 is written in RDRF af ter reading RDRF = 1
1[Setting condition s]
When serial reception ends normally and receive data is transferred from RSR t o
RDR
Not e: RDR1 and the RDRF flag are not affecte d and reta in the ir prev io us va lues when an error is
detected during reception or when the RE bit in SCR1 is cleared to 0.
If reception of the next da ta is comp le te d wh ile th e RDRF flag is still se t to 1, an overrun
er ror will occur an d the rec eive d ata will be lost .
Rev. 1.0, 02/00, page 411 of 1141
Bit 5Overrun Error (ORER): Indicates that an ove rrun e rror occurre d during reception,
causing abnormal termina tion.
Bit 5
ORER Description
0 [Clearing conditions] (Initial value)*1
When 0 is written in ORER after r eading ORER = 1*1
1[Setting condition s]
Whe n the next serial reception is comp lete d while RDRF = 1*2
Notes: 1. The ORER f lag is not affected and retains it s previous state when the RE bit in SCR1 is
cleared to 0.
2. The rec e iv e data pr ior to the ov errun error is retained in RDR1, and t he data r eceiv e d
subsequently is lost. Also, subsequent serial reception cannot be continued while the
ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued,
either.
Bit 4Framing Error (FER): Indic ates that a framing error occurred during reception i n
asynchronous mode, causing abnormal termination.
Bit 4
FER Description
0[Clearing condit ions] (I nitial value)*1
Whe n 0 is writt en in FER afte r r e ading FER = 1*1
1 [Setting condition s]
When the SCI checks the stop bit at the end of the receive data when reception ends,
and the st op bit is 0*2
Notes: 1. The FER flag is not affected and retains its pr evious state when the RE bit in SCR1 is
cleared to 0.
2. I n 2-stop-bit mode, only the f ir st stop bit is checked for a value of 1; the second stop bit
is no t c heck e d. If a fram ing error occur s, th e receive data is tran sf e rr e d to RDR1 but
the RDRF flag is not set. Also, subsequent serial reception cannot be continued while
the FER flag is set to 1. In synchro nous mode, serial tra ns missi on cannot be
continued, either.
Rev. 1.0, 02/00, page 412 of 1141
Bit 3Parity Er ror (PER): Indicates that a parity error occ urred during reception usi ng parity
addition in asynchronous mode, c a using a bnormal termination.
Bit 4
PER Description
0 [Clearing conditions] (Initial value)
When 0 is written in PER after reading PER = 1*1
1[Setting condition s]
When, in r eception, the number of 1 bits in t he receive data plus the par ity bit does
not match the parity set ting (even or odd) specified by the O/
(
bit in SMR1*2
Notes: 1. The PER flag is not aff ected and r etains its pr evious state when the RE bit in SCR1 is
cleared to 0.
2. I f a par ity error o c cur s, t h e receive data is tra nsf erred to RDR1 but the RDRF fla g is not
set. Also, subsequent serial reception cannot be continued while the PER f lag is set to
1. In synchronous mode, serial transmission cannot be continued, either.
Bit 2Transmit End (TEND): Indicates tha t there is no valid data in TDR when the last bit of
the transmit character is sent, and transmission has been ended.
The TEND flag is read-only and cannot be modified.
Bit 2
TEND Description
0[Clearing condit ions]
When 0 is written in TDRE after reading TDRE = 1
1 [Setting condition s] (Initial value)
1. When the TE bit in SCR1 is 0
2. When TDRE = 1 at tr ansmission of the last bit of a 1- byte serial transmit character
Bit 1Multipr ocessor Bit (MPB): W hen rec e ption is performed using a multiprocessor format
in asynchronous mode, MPB stores the multiproc e ssor bit in the receive dat a.
MPB is a read-only bit, and cannot be modified .
Bit 1
MPB Description
0[Clearing condit ions] ( I nitial value)*
Whe n data with a 0 multiprocess or bit is rece iv e d
1 [Setting condition s]
Whe n data with a 1 multiprocess or bit is rece iv e d
Not e : * Ret a ins its pr evio us st at e when the RE bit in SCR1 is clear ed to 0 with multiproces s or
format.
Rev. 1.0, 02/00, page 413 of 1141
Bit 0Multipr ocessor Bit Transfer (MPBT): W hen transmi ssion is performed using a
multiprocessor format in asynchronous m ode, MPBT stores the m ultiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid when a multiprocessor format is not used, when not transmitting,
and in synchronous mode.
Bit 0
MPBT Description
0 Da ta with a 0 multiprocessor bit is transmit ted ( Initial value )
1 Data with a 1 multiprocessor bit is transmitted
22. 2. 8 B i t Rate Regist er 1 (BRR1 )
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit :
Initial value :
R/W :
BRR1 is an 8-bit re gister that sets the seri al transfer bit rate in a ccordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SMR.
BRR1 can be rea d or wri t ten to by the CPU at al l times.
BRR1 is initialized t o H'FF by a reset, and in standby mode, watch mode, subactive mode,
subsleep m ode, and module st op mode.
Table 22. 3 shows sample BRR1 settings in asynchronous mode, and table 22.4 shows sample
BRR1 se ttings in synchronous mode.
Rev. 1.0, 02/00, page 414 of 1141
Tabl e 22. 3 BRR1 Se t ting s for Vario us Bit Rate s (Async hr o nous Mode)
Operating Frequency φ (MHz)
2 2.097152 2.4576 3
Bit Rate
(bits/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 1 141 0.03 1 148 −0.04 1 174 −0.26 1 212 0.03
150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16
300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16
600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16
1200 0 51 0.16 0 54 −0.70 0 63 0.00 0 77 0.16
2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16
4800 0 12 0.16 0 13 −2.48 0 15 0.00 0 19 −2.34
9600  06 −2.48 0 7 0.00 0 9 −2.34
19200   03 0.00 04 −2.34
31250 0 1 0.00  0 02 0.00
38400   01 0.00 
Operating Frequency φ (MHz)
3.6864 4 4.9152 5
Bit Rate
(bits/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 −0.25
150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16
300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16
600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16
1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16
2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16
4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 −1.36
9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73
19200 0 5 0.00  07 0.00 07 1.73
31250  03 0.00 04 −1.70 0 4 0.00
38400 0 2 0.00  03 0.00 03 1.73
Rev. 1.0, 02/00, page 415 of 1141
Operating Frequency φ (MHz)
6 6.144 7.3728 8
Bit Rate
(bits/s) nN Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 106 −0.44 2 108 0.08 2 130 −0.07 2 141 0.03
150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16
300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16
600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16
1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16
2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16
4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16
9600 0 19 −2.34 0 19 0.00 0 23 0.00 0 25 0.16
19200 0 9 −2.34 0 9 0.00 0 11 0.00 0 12 0.16
31250 0 5 0.00 0 5 2.40  07 0.00
38400 0 4 −2.34 0 4 0.00 0 5 0.00 
Operating Frequency φ (MHz)
9.8304 10
Bit Rate
(bits/s) nN Error
(%) nN Error
(%)
110 2 174 −0.26 2 177 −0.25
150 2 127 0.00 2 129 0.16
300 1 255 0.00 2 64 0.16
600 1 127 0.00 1 129 0.16
1200 0 255 0.00 1 64 0.16
2400 0 127 0.00 0 129 0.16
4800 0 63 0.00 0 64 0.16
9600 0 31 0.00 0 32 −1.36
19200 0 15 0.00 0 15 1.73
31250 0 9 −1.70 0 9 0.00
38400 0 7 0.00 0 7 1.73
Rev. 1.0, 02/00, page 416 of 1141
Tabl e 22. 4 BRR1 Se t ting s for Vario us Bit Rate s (Sync hr o nous Mode)
Operating Frequency φ (MHz)
24810
Bit Rate
(bits/s) nNnNnNnN
110 3 70 
250 2 124 2 249 3 124 
500 1 249 2 124 2 249 
1 k 1 124 1 249 2 124 
2.5 k 0 199 1 99 1 199 1 249
5 k 0 99 0 199 1 99 1 124
10 k 0 49 0 99 0 199 0 249
25 k 0 19 0 39 0 79 0 99
50 k 0 9 0 19 0 39 0 49
100 k 0 4 0 9 0 19 0 24
250 k 0 1 0 3 0 7 0 9
500 k 0 0* 0 1 0 3 0 4
1 M 0 0* 0 1
2.5 M 00*
5 M
Note: As far as possible, the setting should be made so t hat the error is no more than 1%.
Legend:
Blank: Cannot be set.
—: Can be set, but there will be a degree of error.
*: Continuous transfer is not possible.
Rev. 1.0, 02/00, page 417 of 1141
The BRR1 setting is found from the following e quations.
• Asynchronous mode:
N = φ× 106 − 1
64 × 22n−1 × B
• Synchrono us mode:
N = φ× 106 − 1
8 × 22n−1 × B
Where
B: Bit rate (bits/s)
N: BRR1 setting for baud rate genera tor (0 ≤ N ≤ 255)
φ: Operating freque ncy (MHz)
n: Baud rat e generator input cl ock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SMR1 Setting
n Clock CKS1 CKS0
0φ00
1φ/4 0 1
2φ/16 1 0
3φ/64 1 1
The bit ra te error in asynchronous mode i s found from the following equation:
Er ror (% ) = { φ × 106− 1 } × 100
(N + 1) × B × 64 × 22n − 1
Table 22. 5 shows the maximum bi t rate for each frequency in asynchronous mode. Tables 22.6
and 22.7 show the ma ximum bit rates with exte rnal clock i nput.
Rev. 1.0, 02/00, page 418 of 1141
Table 22. 5 Maximum Bit Rate for Eac h Frequency (Asynchronous Mode)
φ (MHz) Maximum Bit Rate (bits/s) n N
2 62500 0 0
2.097152 65536 0 0
2.4576 76800 0 0
3 93750 0 0
3.6864 115200 0 0
4 125000 0 0
4.9152 153600 0 0
5 156250 0 0
6 187500 0 0
6.144 192000 0 0
7.3728 230400 0 0
8 250000 0 0
9.8304 307200 0 0
10 312500 0 0
Rev. 1.0, 02/00, page 419 of 1141
Tabl e 22. 6 Ma ximum Bit Rate with Externa l Cl ock Input ( Asy nc hrono us Mode )
φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s)
2 0.5000 31250
2.097152 0.5243 32768
2.4576 0.6144 38400
3 0.7500 46875
3.6864 0.9216 57600
4 1.0000 62500
4.9152 1.2288 76800
5 1.2500 78125
6 1.5000 93750
6.144 1.5360 96000
7.3728 1.8432 115200
8 2.0000 125000
9.8304 2.4576 153600
10 2.5000 156250
Tabl e 22. 7 Ma ximum Bit Rate with Externa l Cl ock Input ( Sy nc hrono us Mode)
φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s)
2 0.3333 333333.3
4 0.6667 666666.7
6 1.0000 1000000.0
8 1.3333 1333333.3
10 1.6667 1666666.7
Rev. 1.0, 02/00, page 420 of 1141
22.2.9 Serial Interface Mode Register 1 (SCMR1)
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
SDIR
0
R/W
0
SMIF
0
R/W
2
SINV
0
R/W
1
—
1
—
Bit :
Initial value :
R/W :
SCMR1 is an 8-bit readable/writable register used to select SCI functions.
SCMR1 is initialized to H'F2 by a reset, and i n sta ndby mode, watch mode, subactive mode,
subsleep m ode, and module st op mode.
Bits 7 to 4Reserved: Thes e bits canno t be mo d ified an d are always r ead as 1.
Bit 3Data Transfer Direct ion (SDIR) : Selects the serial/parallel conversion format.
Bit 3
SDIR Description
0 TDR contents are transm itted LSB- f irst (Init ial value)
Receiv e d ata is store d in RDR1 LSB-fir st
1TDR conten ts are transmitted MSB- first
Receiv e d ata is store d in RDR1 MSB-f irst
Bit 2Data Invert ( SINV): Specifies inversion of the data logic level. The SINV bit does not
affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/
(
bi t in
SMR1.
Bit 2
SINV Description
0 TDR1 cont ents are transmitted without modification (Initial value)
Receiv e d ata is store d in RDR1 witho ut mod ifica tion
1TDR1 cont ents are inverted before being transmitted
Receiv e d ata is store d in RDR1 in inverted fo rm
Bit 1Reserved: This bit cannot be m odified a nd is always read as 1.
Bit 0Reserved: 1 should not be written in this bit.
Rev. 1.0, 02/00, page 421 of 1141
22. 2. 10 M o dul e Sto p Contr ol Regi ster (MSTPCR)
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
MSTPCRH MSTPCRL
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Bit :
Initial value :
R/W :
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When bit MSTP8 is set to 1, SCI1 operation stops at the end of the bus cycle and a transition is
made to module stop mode. For details, see section 4.5, Module Stop Mode.
MSTPCR is ini tial iz e d to H'FFFF by a reset.
Bit 0Module Stop (MST P8): Specifies the SCI1 module stop mode.
MSTPCRH
Bit 0
MSTP8 Description
0 SCI1 module st op mode is cleared
1 SCI2 module st op mode is set (Init ial value)
Rev. 1.0, 02/00, page 422 of 1141
22.3 Operation
22.3.1 Overview
The SCI can carry out serial communication in two modes: asynchronous mode i n which
synchronization is achieved chara cter by character, a nd synchronous m ode in which
synchroniz at ion is achieved with clock pulses.
Selection of asynchronous or synchronous mode and the transmission format is made using SMR1
as shown in table 22.8. The SCI clock is determined by a combination of the C/
$
bit in SMR1
and the CKE1 and CKE0 bits in SCR1, as shown in table 22.9.
• Asynchronous Mode
Data lengt h: Choice of 7 or 8 bits
Choice of parity addition, m ultiprocessor bit a ddition, and addition of 1 or 2 st op bits (the
combination of these parameters determines the transfer format a nd chara cter length)
Detection of framing, parity, and overrun errors, and breaks, during reception
Choice of internal or external cl ock as SCI cloc k source
• When inter n al clock is selected :
The SCI operates on the baud rat e generator cloc k and a clock wit h the same frequency
as the bit rate can be output
• When external clock is selected:
A clock with a frequency of 16 times the bit rate must be input (the built-in baud rate
generator i s not used)
• Clock Synchronous Mode
Transfer format: Fixed 8-bit data
Detection of overrun errors during rec eption
Choice of internal or external cl ock as SCI cloc k source
• When inter n al clock is selected :
The SCI operates on the baud rat e generator cloc k and a seri al clock is output off-chip
• When external clock is selected:
The built-in baud rate generator i s not used, and the SCI operates on the input serial
clock
Rev. 1.0, 02/00, page 423 of 1141
Table 22.8 SMR1 Settings and Serial Transfer Format Selection
SMR1 Settings SCI Transfer Format
Bit 7 Bit 6 Bit 2 Bit 5 Bit 3
C/
$
$
CHR MP PE STOP Mode Data
Length Multiproc-
essor Bit Parity
Bit St op Bit
Length
01 bit0
1
No
2 bits
01 bit
0
1
1
8-bit
data
Yes
2 bits
01 bit0
1
No
2 bits
01 bit
1
0
1
1
Asynchro-
nous mode
7-bit
data
No
Yes
2 bits
01 bit018-bit
data 2 bits
01 bit
0
1
1
1
Asynchro-
nous mode
(multi-
processor
format) 7-bit
data
Yes
2 bits
1 Clock
synchronous
mode
8-bit
data No
No
Tabl e 22. 9 SMR1 and SCR1 Setti ng s and SCI Clock Source Selec tio n
SMR1 SCR1 Setting
Bit 7 Bit 1 Bit 0 SCI Transfer Clock
C/
$
$
CKE1 CKE0 Mode Cl ock Source SCK Pin Function
0 SCI does not use SCK pin0
1
Internal
Outputs clock wi th same frequenc y
as bit rat e
0
0
1
1
Asynchronous
mode
External Inputs clock with frequency of 16
time s the b i t rate
00
1
Internal Ou tputs serial cl ock
0
1
11
Clock
synchronous
mode External Inputs serial clock
Rev. 1.0, 02/00, page 424 of 1141
22.3.2 Operation i n Asynchronous Mode
In asynchronous mode, chara cters are sent or received, each preceded by a start bit indic a ting the
start of communication and followed by one or two stop bits indicating the end of communication.
Serial com munication i s thus carried out with synchroniz ation established on a cha racter-by-
character basis.
Inside the SCI, the tra nsmitter and receiver a re independent units, e nabling full-duplex
communication. Both the transmi tter and the receiver also have a double-buffered structure, so
that data can be read or written during transmission or recept i on, ena bling cont i nuous data
transfer.
Figure 22. 2 shows the ge neral format for asynchronous serial comm unication.
In asynchronous serial communication, the transmission line is usua lly held in t he mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication.
One serial communication character consists of a start bit (low level), followed by data (in LSB-
first order), a parity bit (high or low level ), and finally one or two st op bits (high level).
In asynchronous mode, the SCI performs synchronizati on a t the falling edge of the start bit in
reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the
length of one bit, so that the transfer data is latched at the center of each bit.
LSB
Start
bit
MSB
Idle state
(mark state)
Stop
bit(s)
0
Transmit/receive data
D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 1
Serial
data
Parity
bit
1 bit 1 or 2 bits7 or 8 bits 1 bit,
or none
One unit of transfer data (character or frame)
Figure 22.2 Data Format i n Asynchronous Communic ation
(Example with 8-Bit Data, Parity, Two Stop Bits)
Rev. 1.0, 02/00, page 425 of 1141
• Data Transfer Format
Table 22. 10 shows the data transfe r formats that can be used in asynchronous mode. Any of
12 transfer formats can be selected by settings in SMR1.
Table 22. 10 Serial Transfer Formats (Asynchronous Mode)
PE
0
0
1
1
0
0
1
1
—
—
—
—
S 8-bit data
STOP
S 7-bit data
STOP
S 8-bit data
STOP STOP
S 8-bit data P
STOP
S 7-bit data
STOP
P
S 8-bit data
MPB STOP
S 8-bit data
MPB STOPSTOP
S 7-bit data
STOPMPB
S 7-bit data
STOPMPB STOP
S 7-bit data
STOPSTOP
CHR
0
0
0
0
1
1
1
1
0
0
1
1
MP
0
0
0
0
0
0
0
0
1
1
1
1
STOP
0
1
0
1
0
1
0
1
0
1
0
1
SMR1 Settings
123456789101112
Serial Transfer Format and Frame Length
STOP
S 8-bit data P
STOP
S 7-bit data
STOP
P
STOP
[Legend]
S
STOP
P
MPB
: Start bit
: Stop bit
: Parity bit
: Multiprocessor bit
Rev. 1.0, 02/00, page 426 of 1141
• Clock
Either an internal clock generated by the built-in baud rate generator or an external clock input
at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/
$
bit
in SMR1 and the CKE1 and CKE 0 bits in SCR1. For details of SCI c lock source se lection, see
table 22.9.
When an external clock is input at the SCK pin, the clock frequenc y should be 16 t imes the bit
rate use d.
When the SCI is operate d on an int e rnal cl ock, the clock can be output from t he SCK pin. T he
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is at the center of each transmit data bit, as shown in figure 22.3.
0
1 frame
D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
Figure 22.3 Re l ation between Output Cloc k and Transfer Data Phase
(Asynchronous Mode)
Rev. 1.0, 02/00, page 427 of 1141
• Data Transfer Operations
SCI Initia lization (Asynchronous Mode)
Before transmitting and receiving data, first clear the TE and RE bits in SCR1 to 0, then
initialize the SCI as described below.
Whe n the op er ating mod e, trans f er format, etc., is ch anged , the TE an d R E bits must be
cleared to 0 before ma ki ng the change using the fol lowing procedure. When the TE bit is
cleared to 0, the TDRE flag is set to 1 and TSR1 is initialized. Note that clearing the RE
bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the
contents of RDR1.
When an external clock is used t he clock should not be stopped during operation, including
initialization, since operation is uncertain.
Figure 22. 4 shows a sample SCI initialization flowchart.
Wait
<Initialization completed>
Start initialization
Set data transfer format
in SMR1 and SCMR1
[1]
Set CKE1 and CKE0 bits in SCR1
(TE, RE bits 0)
No
Yes
Set value in BRR1
Clear TE and RE bits in SCR1 to 0
[2]
[3]
Set TE and RE bits in SCR1 to 1,
and set RIE, TIE, TEIE,
and MPIE bits [4]
1-bit interval elapsed?
Set the clock selection in SCR1.
Be sure to clear bits RIE, TIE, TEIE, and
MPIE, and bits TE and RE, to 0.
When the clock is selected in
asynchronous mode, it is output
immediately after SCR1 settings are made.
Set the data transfer format in SMR1 and
SCMR1.
Write a value corresponding to the bit rate
to BRR1. This is not necessary if an
external clock is used.
Wait at least one bit interval, then set the
TE bit or RE bit in SCR1 to 1. Also set the
RIE, TIE, TEIE, and MPIE bits.
Setting the TE and RE bits enables the
SO1 and SI1 pins to be used.
[1]
[2]
[3]
[4]
Fi g ure 22.4 Sample SCI Initiali z ati o n Flowchart
Rev. 1.0, 02/00, page 428 of 1141
Serial D at a Tr ansmissi on (A synchronous M ode)
Figure 22. 5 shows a sample fl owchart for serial transmi ssion.
The following procedure shoul d be used for serial data transmi ssion.
No
< End >
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR1 [1]
Write transmit data to TDR1 and
clear TDRE flag in SSR to 0
No
Yes
No
Yes
Read TEND flag in SSR1
[3]
No
Yes
[4]
Clear PDR to 0
and set PCR to 1
Clear TE bit in SCR1 to 0
TDRE=1
All data transmitted?
TEND=1
Break output?
SCI initialization:
The SO1 pin is automatically designated as
the transmit data output pin.
SCI status check and transmit data write:
Read SSR and check that the TDRE flag is
set to 1, then write transmit data to TDR1
and clear the TDRE flag to 0.
Serial transmission continuation procedure:
To continue serial transmission, read 1
from the TDRE flag to confirm that writing is
possible, then write data to TDR1, and then
clear the TDRE flag to 0.
Break output at the end of serial
transmission:
To output a break in serial transmission, set
PCR for the port corresponding to the SO1
pin to 1, clear PDR to 0, then clear the TE
bit in SCR1 to 0.
[1]
[2]
[3]
[4]
Fi g ure 22.5 Sample Serial Tra nsmission Flo wchart
Rev. 1.0, 02/00, page 429 of 1141
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written
to TDR1, and transfers the data from TDR1 to TSR1.
2. After transferring data from TDR1 to TSR1, the SCI sets the TDRE flag to 1 and starts
transmission.
If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.
The serial transmit data is sent from the SO1 pin in the following order.
a. Start bit:
One 0-bit is output.
b. Transmit data:
8-bit or 7-bit data is output i n LSB-first order.
c. Parity bit or multiprocessor bit:
One parit y bit (e ven or odd parity), or one multiprocessor bit i s out put.
A format in which neither a parity bit nor a multiprocessor bit is output can also be
selected.
d. Stop bit(s):
One or two 1-bits (stop bits) are output.
e. Mark state:
1 is output continuously until the start bit that starts the next tra nsmission is se nt.
3. The SCI checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is cleared to 0, the data is transferred from TDR1 to TSR1, the stop bit is
sent, and then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1, the stop bit is sent, and then the
mark sta te is e ntered in which 1 i s output cont i nuously. If the TEIE bit in SCR1 is set to 1 at
this time, a TEI interrupt requ est is gener ated.
Rev. 1.0, 02/00, page 430 of 1141
Figure 22. 6 shows an example of t he operation for transmission in asynchronous m ode.
TDRE
TEND
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1
1 1
Data
Start
bit
Parity
bit Stop
bit Start
bit
Data
Parity
bit Stop
bit
TXI interrupt
request
generated
Data written to TDR1 and
TDRE flag cleared to 0
in TXI interrupt handling
routine
TEI interrupt request
generated
Idle state
(mark state)
TXI interrupt request
generated
Figure 22.6 Example of O peration in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
Rev. 1.0, 02/00, page 431 of 1141
Serial Data Reception (Asynchronous Mode)
Figures 22.7 and 22. 8 show sampl e flowcharts for se rial reception.
The following procedure shoul d be used for serial data reception.
Yes
< End >
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR1 [4]
[5]
Clear RE bit in SCR1 to 0
Read ORER, PER,
FER flags in SSR1
Error handling
(Continued on next page)
[3]
Read receive data in RDR1, and clear
RDRF flag in SSR1 to 0
No
Yes
PER∨FER∨ORER=1
RDRF=1
All data received?
SCI initialization:
The SI1 pin is automatically designated as
the receive data input pin.
Receive error handling and break
detection:
If a receive error occurs, read the ORER,
PER, and FER flags in SSR to identify the
error. After performing the appropriate
error handling, ensure that the PERE, PER,
and FER flags are all cleared to 0.
Reception cannot be resumed if any of
these flags are set to 1. In the case of a
framing error, a break can be detected by
reading the value of the input port
corresponding to the SI1 pin.
SCI status check and receive data read:
Read SSR and check that RDRF = 1, then
read the receive data in RDR1 and clear
the RDRF flag to 0. Transition of the RDRF
flag from 0 to 1 can also be identified by an
RXI interrupt.
Serial reception continuation procedure:
To continue serial reception, before the
stop bit for the current frame is received,
read the RDRF flag, read RDR1, and clear
the RDRF flag to 0.
[1]
[2][3]
[4]
[5]
Figure 22.7 Sample Serial Reception Data Flowchart (1)
Rev. 1.0, 02/00, page 432 of 1141
< End >
[3]
Error handling
Parity error handling
Yes
No
Clear ORER, PER, and FER
flags in SSR1 to 0
No
Yes
No
Yes
Framing error handling
No
Yes
Overrun error handling
ORER=1
FER=1
Break?
PER=1
Clear RE bit in SCR1 to 0
Figure 22.8 Sample Serial Reception Data Flowchart (2)
Rev. 1.0, 02/00, page 433 of 1141
In serial reception, t he SCI operates as described below.
1. The SCI moni tors the transmission line, and if a 0 stop bit is detected, pe rforms internal
synchronization and starts reception.
2. The received data is store d in RSR1 in LSB-t o-MSB order.
3. The parity bi t and stop bi t are received.
After receiving these bits, the SCI carries out the following checks.
a. Parity check :
The SCI checks whether the number of 1 bits in the receive data agrees with the parity
(even or odd) set in the O/
(
bit i n SMR1.
b. Stop bit che ck:
The SCI checks whether the stop bit is 1.
If there are two stop bits, only the first is checked.
c. Status check:
The SCI checks whether the RDRF flag is 0, indicating that the receive data can be
transferred from RSR1 t o RDR1.
If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored
in RDR1.
If a re ceive error* is de t ected in t he error c heck, the ope ration is as shown i n table 22.11.
Note: * Subsequent receive operations cannot be performed when a receive error has oc c urred.
Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be
cleared to 0.
4. If the RIE bit in SCR1 is set to 1 when the RDRF flag changes to 1, a receive-da ta-full
interrupt (RXI) request is generated.
Also, if the RIE bit in SCR1 is set to 1 when the ORER, PER, or FER flag changes to 1, a
receive-error interrupt (ERI) request is generated.
Table 22.11 Receive Errors and Conditions for Occurrence
Receive Err or Abbrev. Occurrence Condition Data Transfer
Overrun error ORER When the next data reception is
completed while th e RDRF flag
in SSR1 is set to 1
Receive dat a is not transferred
from RSR1 to RDR1
Framing er r or FER When the st op bit is 0 Receive data is transferred fr om
RSR1 t o RDR1
Parity error PER W hen the received data differs
from the parity (even or odd) set
in SMR1
Receive dat a is transferred from
RSR1 t o RDR1
Rev. 1.0, 02/00, page 434 of 1141
Figure 22. 9 shows an example of t he operation for reception in asynchronous mode.
RDRF
FER
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0
1 1
Data
Start
bit
Parity
bit Stop
bit Start
bit Data
Parity
bit Stop
bit
ERI interrupt request
generated by framing
error
Idle state
(mark state)
RDR1 data read
and RDRF flag
cleared to 0 in
RXI interrupt
handling routine
RXI interrupt
request
generation
Figure 22.9 Example of SCI O peration in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
22.3.3 Multiprocessor Communication Function
The multiprocessor communication function performs serial communication using a
multiprocessor format, in which a multiprocessor bi t is adde d to the transfer data, in asynchronous
mode. Use of this function enables dat a transfer to be performed am ong a number of processors
sharing transmission lines.
Whe n multipr o c essor commun ication is carried o ut, each r eceiving station is addr es sed by a
unique ID code.
The serial communication cy cle consists of two co mp onen t cycles : an ID transmission cyc le
which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used
to differentiat e b etween th e ID tr an smiss ion cyc le an d th e data transmission cyc le.
The transmi tting sta tion first sends the ID of t he receivi ng station with which it want s to perform
serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data
with a 0 multiproce ssor bit added.
The receiving station skips t he dat a until dat a with a 1 mul tiprocessor bit is sent.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The st ation whose ID matches then receives the dat a sent ne xt. Sta tions whose ID does
not match con tinu e to skip th e data unt il data wi th a 1 multipr o cessor bit is again re ceived. In this
way, data comm unication is carried out among a number of proce ssors.
Figure 22. 10 shows an exa m ple of i nter-proce ssor com m unication using a multiprocessor format.
Rev. 1.0, 02/00, page 435 of 1141
1. Data Transfer Format
There are four data transfer formats.
When a multiprocessor format is specified, the parity bit specification is invalid.
For details, see table 22.10.
2. Clock
See the section on asynchronous m ode.
Transmitting
station
Receiving
station A
(ID=01)
Receiving
station B
(ID=02)
Receiving
station C
(ID=03)
Receiving
station D
(ID=04)
Serial communication line
Serial
data
ID transmission cycle:
receiving station
specification
Data transmission cycle:
data transmission to
receiving station
specified by ID
(MPB=1) (MPB=0)
H'01 H'AA
[Legend] MPB : Multiprocessor bit
Figure 22.10 Example of Inter-Processor Communic ation Using Multiprocessor Format
(Transmission of Data H'AA to Re ceiving Stati on A)
3. Data Transfer Operations
a. Mult iprocessor Serial Dat a Transmission
Figure 22. 11 shows a sampl e flowcha rt for mul tiprocessor serial data transmission.
The following procedure shoul d be used for m ultiprocessor serial data tra nsmission.
Rev. 1.0, 02/00, page 436 of 1141
No
< End >
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR1 [2]
Write transmit data to TDR1
and set MPBT bit in SSR1
No
Yes
No
Yes
Read TEND flag in SSR1
[3]
No
Yes
[4]
Clear PDR to 0 and set PCR to 1
Clear TE bit in SCR1 to 0
TDRE=1
Transmission end?
TEND=1
Break output?
Clear TDRE flag to 0
SCI initialization:
The SO2 pin is automatically designated as
the transmit data output pin.
SCI status check and transmit data write:
Read SSR and check that the TDRE flag is
set to 1, then write transmit data to TDR1.
Set the MPBT bit in SSR1 to 0 or 1.
Finally, clear the TDRE flag to 0.
Serial transmission continuation procedure:
To continue serial transmission, be sure to
read 1 from the TDRE flag to confirm that
writing is possible, then write data to TDR1,
and then clear the TDRE flag to 0.
Break output at the end of serial
transmission:
To output a break in serial transmission, set
the port PCR to 1, clear PDR to 0, then
clear the TE bit in SCR1 to 0.
[1]
[2]
[3]
[4]
Figure 22. 11 Sam p le Mult ip rocess o r Se rial Transmis s io n Flo wchart
Rev. 1.0, 02/00, page 437 of 1141
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written
to TDR1, and transfers the data from TDR1 to TSR1.
2. After transferring data from TDR1 to TSR1, the SCI sets the TDRE flag to 1 and starts
transmission.
If the TIE bi t is set to 1 at this ti me, a tra nsmit-data-empty i nterrupt (TXI) is generat ed.
The serial transmit data is sent from the SO2 pin in the following order.
a. Start bit:
One 0-bit is output.
b. Transmit data:
8-bit or 7-bit data is output i n LSB-first order.
c. Multiproc ess or bit
One multiprocessor bit (MPBT value) is output.
d. Stop bit(s):
One or two 1-bits (stop bits) are output.
e. Mark state:
1 is output continuously until the start bit that starts the next tra nsmission is se nt.
3. The SCI checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is cleared to 0, data is t ransferred from TDR1 to TSR1, the stop bit is sent,
and then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1, the stop bit is sent, and then the
mark sta te is e ntered in which 1 i s output cont i nuously. If the TEIE bit in SCR1 is set to 1 at
this time, a transmit-end interrupt (TEI) request is generated.
Rev. 1.0, 02/00, page 438 of 1141
Figure 22. 12 shows an exa m ple of SCI operation for tra nsmission using a m ultiprocessor format.
TDRE
TEND
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1
1Data Data
TXI interrupt
request
general
Data written to TDR1 and
TDRE flag cleared to 0
in TXI interrupt handling
routine
TEI interrupt
request
generated
Idle state
(mark state)
TXI interrupt request
generated
Start
bit
Multi-
processor
bit Stop
bit Start
bit
Stop
bit 1
Multi-
processor
bit
Fig ure 22.12 Exampl e of SCI Ope r ation in Tr ansmission
(Example with 8-Bit Data, Multiproc e ssor Bit, One Stop Bit)
b. Multiprocessor Serial Data Reception
Figure 22. 13 shows sample flowcharts for multiprocessor se rial reception.
The following procedure shoul d be used for m ultiprocessor serial data reception.
Rev. 1.0, 02/00, page 439 of 1141
Yes
< End >
[1]
No
Initialization
Start reception
No
Yes
[4]
Clear RE bit in SCR1 to 0
Error handling
(Continued on
next page)
[5]
No
Yes
FER∨ORER=1
RDRF=1
All data received?
Set MPIE bit in SCR1 to 1 [2]
Read ORER and FER flags in SSR1
Read RDRF flag in SSR1 [3]
Read receive data in RDR1
No
Yes
This station's ID?
Read ORER and FER flags in SSR1
Yes
No
Read RDRF flag in SSR1
No
Yes
FER∨ORER=1
Read receive data in RDR1
RDRF=1
SCI initialization:
The SI1 pin is automatically designated as
the receive data input pin.
ID reception cycle:
Set the MPIE bit in SCR1 to 1.
SCI status check, ID reception and
comparison:
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in
RDR1 and compare it with this station's ID.
If the data is not this station's ID, set the
MPIE bit to 1 again, and clear the RDRF
flag to 0.
If the data is this station's ID, clear the
RDRF flag to 0.
SCI status check and data reception:
Read SSR1 and check that the RDRF flag
is set to 1, then read the data in RDR1.
Receive error handling and break
detectioon:
If a receive error occurs, read the ORER
and FER flags in SSR1 to identify the error.
After performing the appropriate error
handling, ensure that the ORER and FER
flags are both cleared to 0.
Reception cannot be resumed if either of
these flags is set to 1.
In the case of a framing error, a break can
be detected by reading the SI1 in value.
[1]
[2]
[3]
[4]
[5]
Figure 22.13 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 1.0, 02/00, page 440 of 1141
< End >
Error handling
Yes
No
Clear ORER, PER, and FER
flags in SSR1 to 0
No
Yes
No
Yes
Framing error handling
Overrun error handling
ORER=1
FER=1
Break?
Clear RE bit in SCR1 to 0
[5]
Figure 22.14 Sample Multiprocessor Serial Reception Flowchart (2)
Rev. 1.0, 02/00, page 441 of 1141
Figure 22. 15 shows an exa m ple of SCI operation for mul tiprocessor format reception.
MPIE
RDR1
value
0D0 D1 D7 1 1 0 D0 D1 D7 0 1
11
Data (ID1)
Start
bit
MPB
Stop
bit Start
bit
Data (Data 1) MPB
Stop
bit
RXI interrupt
request (multi-
processor
interrupt)
generated
Idle state
(mark state)
RDRF
RDR1 data read
and RDRF flag
cleared to 0 in
RXI interrupt
handling routine
If not this station's
ID, MPIE bit is set
to 1 again
RXI interrupt request
is not generated, and
RDR1 retains its state
ID1
(a) Data does not match station's ID
MPIE
RDR1
value
0D0 D1 D7 1 1 0 D0 D1 D7 0 1
11
Data (ID2)
Start
bit
MPB
Stop
bit Start
bit
Data (Data 2) MPB
Stop
bit
RXI interrupt
request (multi-
processor
interrupt)
generated
Idle state
(mark state)
RDRF
RDR1 data read and
RDRF flag cleared
to 0 in RXI interrupt
handling routine
Matches this station's
ID, so reception continues,
and data is received in RXI
interrupt handling routine
MPIE bit set
to 1 again
ID2
(b) Data matches station's ID
Data2ID1
MPIE=0
MPIE=0
Figure 22.15 Exampl e of SCI Ope r ation in Receptio n
(Example with 8-Bit Data, Multiproc e ssor Bit, One Stop Bit)
Rev. 1.0, 02/00, page 442 of 1141
22.3.4 O peration in Synchronous Mode
In sync hronous mode, data is transmitted or received in synchronization with c l ock pulses, making
it suitable for high-speed serial communic ation.
Inside the SCI, the tra nsmitter and receiver a re independent units, e nabling full-duplex
com mu nication by use of a co mmon clo ck . Bot h th e tran s mitter and th e receiver also hav e a
double-buffered structure, so that data c an be read or written during transmission or reception,
enabling continuous da ta transfe r.
Figure 22. 16 shows the genera l format for synchronous serial communication.
Don't
care
Don't
care
One unit of transfer data (character or frame)
Bit 0
Serial
data
Synchronous
clock
Bit 1 Bit 3 Bit 4 Bit 5
LSB MSB
Bit 2 Bit 6 Bit 7
**
Note: * High except in continuous transfer
Figure 22.16 Data Format i n Synchronous Communication
In sync hronous seri al communi cation, da ta on t he transmi ssion line is output from one falling edge
of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock.
In sync hronous seri al communi cation, one character consi sts of data output starting with the LSB
and ending with the MSB. After the MSB is output, the transmission line holds the MSB state.
In sync hronous mode, the SCI receives data in sync hronization wit h the ri sing edge of t he se rial
clock.
• Data Transfer Format
A fixed 8-bit data format is used.
No parity or multiprocessor bits are added.
• Clock
Either an internal clock generated by the built-in baud rate generator or an external serial clock
input at t he SCK pin can be selected, a ccording to the setting of the C/
$
bit in SMR1 and the
CKE1 and CKE0 bits in SCR1. For details on SCI c lock source selection, see table 22.9.
When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.
Eight serial clock pulses are output in the transfer of one character, and when no transfer is
performed the clock is fixed high. When only receive ope rations a re performed, howe ve r, the
serial clock is output unti l an ove rrun e rror occurs or the RE bi t is cl eared to 0. To perform
receive operations in units of one character, sel ect an external clock as the clock source .
Rev. 1.0, 02/00, page 443 of 1141
• Data Transfer Operations
SCI Initia lization (Synchronous Mode)
Before transmitting and receiving data, first clear the TE and RE bits in SCR1 to 0, then
initialize the SCI as described below.
Whe n the op er ating mod e, trans f er format, etc., is ch anged , the TE an d R E bits must be
cleared to 0 before ma ki ng the change using the fol lowing procedure. When the TE bit is
cleared to 0, the TDRE flag is set to 1 and TSR1 is initialized. Note that clearing the RE
bit to 0 does not change the settings of the RDRF, PER, FER, and ORER flags, or the
contents of RDR1.
Figure 22. 17 shows a sampl e SCI initialization flowchart.
Wait
<Transfer start>
Start initialization
Set data transfer format
in SMR1 and SCMR
No
Yes
Set value in BRR1
Clear TE and RE bits in SCR1 to 0
[2]
[3]
Set TE and RE bits in SCR1 to 1,
and set RIE, TIE, TEIE, and MPIE
bits [4]
1-bit interval elapsed?
Set CKE1 and CKE0 bits in
SCR1 (TE, RE bits 0) [1]
Set the clock selection in SCR1. Be sure to
clear bits RIE, TIE, TEIE, and MPIE, TE
and RE, to 0.
Set the data transfer format in SMR1 and
SCMR1.
Write a value corresponding to the bit rate
to BRR1. This is not necessary if an
external clock is used.
Wait at least one bit interval, then set the
TE bit or RE bit in SCR1 to 1.
Also set the RIE, TIE, TEIE, and MPIE bits.
Setting the TE and RE bits enables the
SO1 and SI1 pins to be used.
[1]
[2]
[3]
[4]
Fi g ure 22.17 Sample SCI Initi alizati o n Flowc hart
Rev. 1.0, 02/00, page 444 of 1141
Serial D at a Tr ansmissi on (S ynch ronous Mode)
Figure 22. 18 shows a sampl e flowcha rt for serial tra nsmission.
The following procedure shoul d be used for serial data transmi ssion.
No
< End >
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR1 [2]
Write transmit data to TDR1 and
clear TDRE flag in SSR1 to 0
No
Yes
No
Yes
Read TEND flag in SSR1
[3]
Clear TE bit in
SCR1 to 0
TDRE=1
All data transmitted?
TEND=1
SCI initialization:
The SO2 pin is automatically designated as
the transmit data output pin.
SCI status check and transmit data write:
Read SSR1 and check that the TDRE flag
is set to 1, then write transmit data to TDR1
and clear the TDRE flag to 0.
Serial transmission continuation procedure:
To continue serial transmission, be sure to
read 1 from the TDRE flag to confirm that
writing is possible, then write data to TDR1,
and then clear the TDRE flag to 0.
[1]
[2]
[3]
Figure 22.18 Sample Serial Transmission Flowchar t
Rev. 1.0, 02/00, page 445 of 1141
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR1, and if it is 0, recognizes that data has been written
to TDR1, and transfers the data from TDR1 to TSR1.
2. After transferring data from TDR1 to TSR1, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty int errupt (T XI) is
generated.
When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an
external clock has been specified, data is output synchroniz e d wit h the i nput cloc k.
The serial transmit data is sent from the SO1 pin starting with the LSB (bit 0) and ending with
the MSB (bit 7).
3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
If the TDRE flag is cleared to 0, data is t ransferred from TDR1 to TSR1, a nd serial
transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR1 is set to 1, the MSB (bit 7) is sent, and the
SO1 pin maintains its state.
If the TEIE bit i n SCR1 i s set t o 1 at t hi s time , a transmit-end interrupt (TEI) request is
generated.
4. After completion of serial transmission, the SCK pin is held in a constant state.
Figure 22. 19 shows an exa m ple of SCI operation in transmission.
Transfer
direction
Bit 0
Serial
data
Synchronous
clock
1 frame
TDRE
TEND
Data written to TDR1
and TDRE flag cleared
to 0 in TXI interrupt
handling routine
TXI interrupt
request
generated
Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TXI interrupt
request
generated
TEI interrupt
request
generated
Fig ure 22.19 Exampl e of SCI Ope r ation in Tr ansmission
Rev. 1.0, 02/00, page 446 of 1141
Serial Data Reception (Synchronous Mode)
Figure 22. 20 shows a sampl e flowcha rt for serial reception.
The following procedure shoul d be used for serial data reception.
When changing the operating mode from asynchronous to synchronous, be sure to che c k
that the ORER, PER, and FER flags are all cleared to 0.
The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor
receive operations will be possible.
Rev. 1.0, 02/00, page 447 of 1141
Yes
< End >
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR1 [4]
[5]
Clear RE bit in SCR1 to 0
Error handling
(Continued below)
[3]
Read receive data in RDR1,
and clear RDRF flag in SSR1 to 0
No
Yes
ORER=1
RDRF=1
All data received?
Read ORER flag in SSR1
< End >
Error handling
Clear ORER flag in
SSR1 to 0
Overrun error handling
[3]
SCI initialization:
The SI1 pin is automatically designated as
the receive data input pin.
Receive error handling:
IF a receive error occurs, read the ORER
flag in SSR1, and after performing the
appropriate error handling, clear the ORER
flag to 0. Transfer cannot be resumed if
the ORER flag is set to 1.
SCI status check and receive data read:
Read SSR1 and check that the RDRF flag
is set to 1, then read the receive data in
RDR1 and clear the RDRF flag to 0.
Transition of the RDRF flag from 0 to 1 can
also be identified by and RXI interrupt.
Serial reception continuation procedure:
To continue serial reception, before the
MSB (bit 7) of the current frame is received,
finish reading the RDRF flag, reading
RDR1, and clearing the RDRF flag to 0.
[1]
[2][3]
[4]
[5]
Figure 22.20 Sample Serial Reception Flowchart
Rev. 1.0, 02/00, page 448 of 1141
In serial reception, t he SCI operates as described below.
1. The SCI perform s int e rnal initialization in sync hronization with seria l clock input or output.
2. The received data is store d in RSR1 in LSB-t o-MSB order.
After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be
transferred from RSR1 t o RDR1.
If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR1. If a
receive error is detected i n the e rror check, the operation is as shown i n table 22.11.
Neither transmit nor receive operations can be performed subsequently when a receive error
has been found in t he error check.
3. If the RIE bit in SCR1 is set to 1 when the RDRF flag changes to 1, a receive-da ta-full
interrupt (RXI) request is generated.
Also, if the RIE bit in SCR1 is set to 1 when the ORER flag changes to 1, a receive-error
interrupt (E RI) request is ge ne rated.
Figure 22. 21 shows an exa m ple of SCI operation in reception.
Bit 7
Serial
data
Synchronous
clock
1 frame
RDRF
ORER
ERI interrupt request
generated by
overrun error
RXI interrupt
request
generated
RDR1 data read and
RDRF flag cleared to 0
in RXI interrupt
handling routine
RXI interrupt
request
generated
Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figure 22.21 Exampl e of SCI Ope r ation in Receptio n
Rev. 1.0, 02/00, page 449 of 1141
Simultaneous Serial Da ta Transmission and Reception (Synchronous Mode )
Figure 22. 22 shows a sampl e flowcha rt for simultaneous se rial transmit and receive
operations.
The following procedure shoul d be used for sim ultaneous serial data tra nsmit and receive
operations.
Yes
< End >
[1]
No
Initialization
Start transfer
[5]
Error handling
[3]
Read receive data in RDR1, and
clear RDRF flag in SSR1 to 0
No
Yes
ORER=1
All data received?
[2]
Read TDRE flag in SSR1
No
Yes
TDRE=1
Write transmit data to TDR1 and
clear TDRE flag in SSR1 to 0
No
Yes
RDR=1
Read ORER flag in SSR1
[4]
Read RDRF flag in SSR1
Clear TE and RE
bits in SCR1 to 0
Note: When switching from transmit or receive operation
to simultaneous transmit and receive operations, first
clear the TE bit and RE bit to 0, then set both these
bits to 1 simultaneously.
SCI initialization:
The SO2 pin is designated as the transmit
data output pin, and the SI1 pin is
designated as the receive data input pin,
enabling simultaneous transmit and receive
operations.
SCI status check and transmit data write:
Read SSR1 and check that the TDRE flag
is set to 1, then write transmit data to TDR1
and clear the TDRE flag to 0.
Transition of the TDRE flag from 0 to 1 can
also be identified by a TXI interrupt.
Receive error handling:
If a receive error occurs, read the ORER
flag in SSR1, and after performing the
appropriate error handling, clear the ORER
flag to 0. Transmission/reception cannot
be resumed if the ORER flag is set to 1.
SCI status check and receive data read:
Read SSR1 and check that the RDRF flag
is set to 1, then read the receive data in
RDR1 and clear the RDRF flag to 0.
Transition of the RDRF flag from 0 to 1 can
also be identified by an RXI interrupt.
Serial transmission/reception continuation
procedure:
To continue serial transmission/reception,
before the MSB (bit 7) of the current frame
is received, finish reading the RDRF flag,
reading RDR1, and clearing the RDRF flag
to 0. Also before the MSB (bit 7) of the
current frame is transmitted, read 1 from
the TDRE flag to confirm that writing is
possible, then write data to TDR1 and clear
the TDRE flag to 0.
[1]
[2]
[3]
[4]
[5]
Figure 22.22 Sample Flowc hart of Simul taneous Serial Transmit and Receive O perations
Rev. 1.0, 02/00, page 450 of 1141
22.4 SCI Interrupts
The SCI ha s four interrupt sources: the transmit-end int e rrupt (TE I) request, receive-error interrupt
(ERI) request, receive-data-full interrupt (RXI) reque st, and t ransmit-da ta-empty i nterrupt (TXI)
request. Table 22.12 shows t he interrupt sources and t heir relat ive priori t ies. Individual int errupt
sources ca n be enabled or disable d with the TIE, RIE, and TEIE bits in SCR1. Each kind of
interrupt re quest is sent t o the interrupt control ler independe ntly.
When the TDRE flag in SSR1 is set t o 1, a T XI interrupt reque st is ge nerated. When the TEND
flag in SSR1 is se t to 1, a TEI interrupt reque st is generated.
When the RDRF flag in SSR1 is set t o 1, an RXI interrupt reque st i s generated. When the ORER,
PER, or FER flag i n SSR1 is set to 1, an ERI i nterrupt request is generated.
Tabl e 22. 12 SCI Inte rrupt Sourc e s
Channel I nterrupt Sour ce Descr i ption Priority*
ERI Int errupt by receive err or (ORER, FER, or PER)
RXI Interrupt b y receiv e data reg ist er fu ll ( RDRF)
TXI Int errupt by transmit data regist er empty (TDRE)
1
TEI Int errupt by transmit end (TEND)
High
Low
The TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The
TEND flag is cleared at the sam e time a s the TDRE flag. Consequent ly, if a TE I interrupt and a
TXI inte rrupt are request ed simultaneously, the TXI interrupt will have pri ority for acceptance,
and the TDRE fla g and TE ND flag may be cleared. Note that the TEI i nterrupt will not be
accepted in this case.
Rev. 1.0, 02/00, page 451 of 1141
22.5 Usage Notes
The following poi nts shoul d be noted when using the SCI.
• Relation between Writes to TDR1 and the TDRE Flag
The TDRE flag in SSR1 is a status flag that indicates that transmit data has been transferred
from TDR1 to TSR1. When t he SCI transfers data from TDR1 to TSR1, t he TDRE flag is set
to 1.
Data can be written to TDR1 regardless of the state of the TDRE flag. However, if new data is
written to TDR1 when the TDRE flag is cleared to 0, the data stored in TDR1 will be lost since
it has not yet been transferred to TSR1. It is therefore essential to check that the TDRE flag is
set to 1 before writing transmit data to TDR1.
• Operation whe n Multiple Rec eive Errors Oc c ur Sim ultaneously
If a num ber of receive errors occur at the same time, t he state of the status flags in SSR1 is as
shown in table 22. 13. If the re is an overrun error, data is not tra nsferred from RSR1 t o RDR1,
and the r eceive data is los t.
Table 22.13 State of SSR1 Status Flags and Transfe r of Receive Data
SSR1 Status Flags Recei ve Data Transfer
RDRF O RER FER PER RSR1 t o RDR1 Recei ve Error Status
1 1 0 0 X Overrun error
0010 Framing er r or
0001 Parity error
1 1 1 0 X Overrun error + framing error
1 1 0 1 X Overrun error + parity error
0011 Framing error + parity error
1 1 1 1 X Overrun error + framing error +
parity error
Notes: : Receiv e dat a is transf e rr e d from RSR1 t o RDR1.
X: Re c e iv e d at a is not tra n sfer r e d from RSR1 to RDR1.
Rev. 1.0, 02/00, page 452 of 1141
• Break Detection and Processing
When framing error (FER) detection is performed, a break can be detected by reading the SI1
pin value di rectly. In a brea k, the input from the SI1 pin becomes all 0s, and so the FER flag is
set, and the parity error flag (PER) may a l so be set.
Note that, since the SCI continues the receive operation after receiving a break, even if the
FER flag is cleared to 0, it will be set to 1 again.
• Sending a Break
The SO1 pin has a dual function as an I/O port whose di rection (input or output) is determined
by DR a nd DDR. This can be used to send a break.
Between serial transmission initialization and setting of the TE bit to 1, the mark state is
replaced by the va l ue of PDR (the pin does not function as the SO1 pin until the TE bit is set to
1). Conseque ntly, PCR a nd PDR for the port correspondi ng to the SO1 pin are fi rst set to 1.
To send a break during serial transmission, first cl ear PDR to 0, then c lear the TE bit to 0.
Whe n the TE b it is cleared to 0, the tr ansmi tter is initialized reg ardless of the cu r rent
transmission state, the SO1 pin become s an I/ O port, and 0 is output from the SO1 pin.
• Receive E rror Fla gs and Transmi t Operations (Clocked Synchronous Mode Only)
Transmission cannot be started whe n a rec eive e rror flag (ORER, PER, or FER) is set to 1,
even if the TDRE flag is c leared to 0. Be sure to cl ear the rec eive error flags to 0 before
starting transmission.
Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
• Receive Data Sampling T iming and Rec e ption Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times t he
transfer rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and
performs i nternal synchroniz ation. Rec eive data is latched internally at the rising edge of the
8th pulse of the basic c lock. This is illustrated i n figure 22.23.
Rev. 1.0, 02/00, page 453 of 1141
Internal basic
clock
16 clocks
8 clocks
Receive data
Synchronization
sampling timing
Start bit D0 D1
Data sampling
timing
15 0 7 15 007
Fi g ure 22.23 Receive Dat a Sampli ng Timing in Async hrono us Mode
Thus the reception margin in asynchronous mode is given by formula (1) below.
M = | (0.5 – 1
2N ) – (L – 0.5) F – | D – 0 .5 |
N (1 + F) | × 100%
... Formula (1)
Where M : Recepti on margin (%)
N : Rat io of bit ra te to cloc k (N = 16)
D : Clock duty (D = 0 t o 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
Assuming valu e s of F = 0 and D = 0.5 in formu la (1), a recep ti on marg in o f 46.87 5% is given by
formula (2) below.
When D = 0.5 a nd F = 0,
M = (0.5 – 1
2 × 16 ) × 100%
= 46.875% ... Formul a (2)
However, t hi s is only the comput ed value, a nd a ma rgin of 20% to 30% should be allowed in
system desig n.
Rev. 1.0, 02/00, page 454 of 1141
• Operation in Case of Mode Transition
Transmission
Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module
stop mode, standby mode, watc h mode, subactive m ode, or subsle ep mode transit i on.
TSR1, TDR1, and SSR1 are reset. The output pin states i n module stop mode, standby
mode, watch mode, subactive mode, or subsle ep mode depend on the port settings, and
becomes high-l eve l output after the relevant mode is cleared. If a transition is mad e during
transmission, the data being transmitted will be undefined. When transmitting without
changing the transmit mode after the relevant mode is cleared, transmission can be started
by setting TE to 1 again, and performing the following sequence: SSR1 read
Æ
TDR1
write
Æ
TDR E clea r ance. To tr ansmi t with a d iff eren t tr an s mit mode aft er clearin g th e
relevant m ode, the procedure must be started again from initialization. Figure 22.24 shows
a sample flowchart for mode transition during transmission. Port pin states are shown in
figures 22. 25 and 22.26.
Reception
Receive operation should be st opped (by clearing RE to 0) before making a modul e stop
mode, standby mode, watch mode, subactive mode, or subsleep mode transition. RSR1,
RDR1, and SSR1 are reset. If a transition is made without stoppi ng ope ration, the dat a
being received will be invalid. To continue receiving without changing the reception mode
aft er the r elevant mo de is cl eared, set RE to 1 bef o re st ar ting re ception. To receive wi th a
different re ceive mode, the proce dure must be started a gain from initialization.
Figure 22. 27 shows a sampl e flowcha rt for mode transition during rec eption.
Rev. 1.0, 02/00, page 455 of 1141
Read TEND flag in SSR1
TE= 0
Transition to standby
mode, etc.
Exit from standby
mode, etc.
Change
operating mode? No
All data
transmitted?
TEND = 1
Yes
Yes
Yes
<Transmission>
No
No
[1]
[3]
[2]
TE= 1Initialization
<Start of transmission>
[1] Data being transmitted is interrupted.
After exiting software standby
mode, etc., normal CPU transmis-
sion is possible by setting TE to 1,
reading SSR1, writing TDR1, and
clearing TDRE to 0.
[2] If TIE and TEIE are set to 1, clear
them to 0 in the same way.
[3] Includes module stop mode, watch
mode, subactive mode, and sub-
sleep mode.
Figure 22.24 Sample Flowc hart for Mode Transition during Transmi ssion
Rev. 1.0, 02/00, page 456 of 1141
SCK1 output pin
TE bit
SO1 output pin Port input/output High outputPort input/output High output Start Stop
Start of transmission End of
transmission
Port input/output
SCI TxD output Port SCI TxD
output
Port
Transition
to standby Exit from
standby
Fi g ure 22.25 Asynchr o no us Transmi ssi o n Using Inter na l Clock
Port input/output
Last TxD bit held
High output*Port input/output Marking output
Port input/output
SCI TxD output PortPort
Note: * Initialized by software standby.
SCK1 output pin
TE bit
SO1 output pin
SCI TxD
output
Start of transmission End of
transmission Transition
to standby Exit from
standby
Fi g ure 22.26 Synchr o no us Transmi ssi o n Using Inter na l Clock
Rev. 1.0, 02/00, page 457 of 1141
RE= 0
Transition to standby
mode, etc.
Read receive data in RDR1
Read RDRF flag in SSR1
Exit from standby
mode, etc.
Change
operating mode? No
RDRF= 1
Yes
Yes
<Reception>
No [1]
[2]
[1]
[2]
RE= 1Initialization
<Start of reception>
Receive data being received
becomes invalid.
Includes module stop mode,
watch mode, subactive mode,
and subsleep mode.
Figure 22.27 Sample Flowc hart for Mode Transition during Re ception
Rev. 1.0, 02/00, page 459 of 1141
Section 23 I2C Bus Interfa ce (IIC)
23.1 Overview
This LSI i ncorporates a 2-cha nnel I2C bus interface.
The I2C bus interface conforms to and provi des a subset of the Philips I2C bus (inter-IC bus)
interface functions. T he regi ster configuration that controls the I2C bus di ffers partly from the
Philips configuration, however.
Each I2C bus inte r face chann el uses onl y one data li ne (SDA) and one clo ck li ne ( SCL) to t ran sfer
data, savi ng board and connec tor space.
23.1.1 Features
• Selection of addressing format or non-addressing format
I2C bus format: a ddressing format with acknowledge bit, for master/slave operation
Serial format: non-a ddress i ng form at withou t acknow l edge bit , for master opera tion only
• Conforms to Philips I2C bus interface (I2C bus format)
• Two ways of setting slave address (I2C bus format)
• Start and stop conditions generated automatically in master mode (I2C bus f orma t)
• Selection of acknowle dge output levels whe n receiving (I2C bus format)
• Automatic loading of acknowledge bit when transmitting (I2C bus form at)
• Wait function in master mode (I2C bus format)
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait can be cleared by clearing the interrupt flag.
• Wait function in slave mode (I2C bus format)
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
• Three interru pt sources
Data transfer end (including transmission mode transition with I2C bus format and address
reception after loss of master arbitration)
Address matc h: whe n any slave address matches or the ge neral call address i s received in
slave receive mode (I2C bus form at)
Stop condition detec tio n
• Selection of 16 internal clocks (in master mode )
• Direct bus dri ve (with SCL and SDA pins)
Four pins P26/ SCL 0, P25/SDA0, P24/SCL1 a n d P23/SDA1 (norm all y CMOS pins)
function as NMOS-onl y outputs when th e bus drive function is selected.
Rev. 1.0, 02/00, page 460 of 1141
23.1.2 Block Diagram
Figure 23. 1 shows a bloc k diagram of the I2C bus interface.
Figure 23. 2 shows an example of I/ O pin connections to external circuits. I/O pins are driven only
by NMOS and appare ntl y function as NMOS open-drain outp uts. Ho wever, appli cab le volta ges to
input pi ns depend on the power (Vcc) voltage of this LSI.
φ
SCL
PS
Noise
canceller
Bus state
decision
circuit
Output data
control
circuit
ICCR
Clock
control ICMR
ICSR
ICDRS
Address
comparator
Arbitration
decision
circuit
SAR, SARX
SDA
Noise
canceler
Interrupt
generator Interrupt
request
Internal data bus
[Legend]
ICCR
ICMR
ICSR
ICDR
SAR
SARX
PS
: I
2
C control register
: I
2
C mode register
: I
2
C status register
: I
2
C data register
: Slave address register
: Slave address register X
: Prescaler
ICDRR
ICDRT
Figure 23.1 Block Diagram of I 2C Bus Inter face
Rev. 1.0, 02/00, page 461 of 1141
V
CC
SCL
in
out
SCL
SDA
in
out
(Master)
This chip
SDA
SCL
SDA
SCL
in
out
SCL
SDA
in
out
(Slave 1)
SDA
SCL
in
out
SCL
SDA
in
out
(Slave 2)
SDA
Figure 23.2 I2C Bus Interface Conne c tions (Example: This Chip as Master )
23.1.3 Pin Confi guration
Table 23.1 summarizes the input/output pins used by the I2C bus interface.
Table 23. 1 I2C Bus Interface Pins
Channel Name Abbrev.* I/O Function
Serial clock pin SCL0 I nput/output IIC0 ser ial clock input/output
Serial data pin SDA0 I nput/output I I C0 ser ial data input/output
0
Formatless serial clock pin SYNCI Input IIC0 formatless ser ial clock input
Serial clock pin SCL1 I nput/output IIC1 ser ial clock input/output1
Serial data pin SDA1 I nput/ output II C1 ser ial data input/output
Note: * In this sect ion, channel numbers in the abbr eviated regist er names are omitted; SCL0
and SCL1 are collectively ref erred to as SCL, and SDA0 and SDA1 as SDA.
Rev. 1.0, 02/00, page 462 of 1141
23.1.4 Regi ster Configur ati on
Table 23.2 summarizes the registers of the I2C bus interface.
Table 23. 2 Register Configurati on
Channel Nam e Abbrev. R/W I niti al Value Address*1
0I
2C bus control regis ter ICCR0 R/ W H'01 H'D0E8
I2C bus status r egister ICSR0 R/W H'00 H'D0E9
I2C bus data reg ist e r I CDR0 R/W H'D0EE*2
I2C bus mode r egister ICMR0 R/W H'00 H'D0EF*2
Slave addr ess register SAR0 R/W H'00 H'D0EF*2
Second slave address register SARX0 R/W H'01 H'D0EE*2
1I
2C bus control regis ter ICCR1 R/ W H'01 H'D15 8
I2C bus status r egister ICSR1 R/W H'00 H'D159
I2C bus data reg ist e r I CDR1 R/W H'D15E*2
I2C bus mode r egister ICMR1 R/W H'00 H'D15F*2
Slave addr ess register SAR1 R/W H'00 H'D15F*2
Second slave address register SARX1 R/W H'01 H'D15E*2
0 and 1 DDC swit c h register DDCSWR R/W H'0 F H'D0E5
Module stop control regis ter MSTPCR H
MSTPCRL R/W H'FF
H'FF H'FFEC
H'FFED
Notes: 1. Lower 16 bits of the address .
2. The registers that can be read from or written to depend on t he ICE bit in the I2C bus
control r egister. The slave address r egisters can be accessed when ICE = 0, and t he
I2C bus mode r egisters can be accessed when ICE = 1.
Rev. 1.0, 02/00, page 463 of 1141
23.2 Regi ster Descri pt i on s
23.2.1 I2C Bus Data Register (ICDR)
7
ICDR7
—
R/W
6
ICDR6
—
R/W
5
ICDR5
—
R/W
4
ICDR4
—
R/W
3
ICDR3
—
R/W
0
ICDR0
—
R/W
2
ICDR2
—
R/W
1
ICDR1
—
R/W
Bit :
Initial value :
R/W :
ICDRR
7
ICDRR7
—
R
6
ICDRR6
—
R
5
ICDRR5
—
R
4
ICDRR4
—
R
3
ICDRR3
—
R
0
ICDRR0
—
R
2
ICDRR2
—
R
1
ICDRR1
—
R
Bit :
Initial value :
R/W :
ICDRS
7
ICDRS7
—
—
6
ICDRS6
—
—
5
ICDRS5
—
—
4
ICDRS4
—
—
3
ICDRS3
—
—
0
ICDRS0
—
—
2
ICDRS2
—
—
1
ICDRS1
—
—
Bit :
Initial value :
R/W :
ICDRT
7
ICDRT7
—
W
6
ICDRT6
—
W
5
ICDRT5
—
W
4
ICDRT4
—
W
3
ICDRT3
—
W
0
ICDRT0
—
W
2
ICDRT2
—
W
1
ICDRT1
—
W
Bit :
Initial value :
R/W :
TDRE, RDRF (Inte r nal fla g)
—
RDRF
0
—
—
TDRE
0
—
Bit :
Initial value :
R/W :
Rev. 1.0, 02/00, page 464 of 1141
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is divided internally into a shift
register (ICDRS), receive buffer (ICDRR), and tra nsmit buffe r (ICDRT ). ICDRS cannot be read
or writte n by the CPU, ICDRR i s read-only, and ICDRT is write-only. Data transfers among the
three registers are performed automatically in coordination with changes in the bus state, and
affect the status of inte rnal flags such as TDRE and RDRF.
If IIC is in transmit mode and the next data is in ICDRT (the TDRE flag is 0) following
transmission/ reception of one frame of data usi ng ICDRS, data is transfe rred automatically from
ICDRT to ICDRS. If IIC is in receive m ode and no previous data remains in ICDRR (the RDRF
flag is 0) following transmi ssion/reception of one frame of data using ICDRS, data is transfe rred
automati cally from ICDRS to ICDR R.
If the number of bits in a frame, exclud ing the acknowl edge bit, is less than 8, transmit da ta and
receive data are stored differently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
ICDR is a ssigned to the same addre ss as SARX, and ca n be written and read only when the ICE
bit is set to 1 in ICCR.
The value of ICDR is undefined after a reset.
The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the
TDRE and RDRF fl ags affects the sta t us of the interrupt flags.
Rev. 1.0, 02/00, page 465 of 1141
TDRE Description
0 The next transmit data is in ICDR (ICDRT), or transmission cannot be started
[Clearing condit ions] (Initial value)
1. Wh e n tra n sm it d ata is wr itten in ICDR (ICDRT) in tra nsm it mod e (TRS = 1)
2. When a stop condition is detected in the bus line state after a stop condition is
issued with the I2C bus format or serial format selected
3. When a stop condition is detected with the I2C bus forma t select ed
4. In receive mode (TRS = 0)
(A 0 write to TRS during transfer is valid aft er reception of a frame cont aining an
acknowledge bit)
1 Th e n ext tr a nsm it d ata ca n be writt e n in ICDR (I CDRT)
[Setting condition s]
1. In transm it mode ( TRS = 1) , when a start condition is detected in the bus line state
after a st art condit ion is issued in master mode with the I2C bus format or serial
format select ed
2. In transm it mode ( TRS = 1) when f ormatless transfer is selected
3. Wh e n data is tra n sf erred from ICDRT to ICDRS
(Da ta transf er from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS is
empty)
4. When a switch is made from receive mode ( TRS = 0) to transmit m ode (TRS = 1)
aft er detection of a start condit ion
RDRF Description
0 Th e dat a in ICDR (ICDRR) is in valid (Initial value)
[Clearing condition]
Whe n ICDR (ICDRR) receive dat a is read in rec e iv e mode
1 Th e ICDR (I CDRR) r eceiv e data can be read
[Setting condition]
Whe n data is tr a n sf erred from ICDRS to ICDRR
(Da ta transfer from ICDRS to ICDRR in case of norma l terminatio n with TRS = 0 and
RDRF = 0)
Rev. 1.0, 02/00, page 466 of 1141
23. 2. 2 Slav e Address Regi ster (SAR)
7
SVA6
0
R/W
6
SVA5
0
R/W
5
SVA4
0
R/W
4
SVA3
0
R/W
3
SVA2
0
R/W
0
FS
0
R/W
2
SVA1
0
R/W
1
SVA0
0
R/W
Bit :
Initial value :
R/W :
SAR is an 8-bit readable/writable register that stores the slave address and selects the
communication format. W hen the chip i s in slave mode (a nd the addressing format is selected), if
the upper 7 bit s of SAR match the upper 7 bits of the first frame receive d after a start condition,
the chip operates as the slave device specified by the master device. SAR is assigned to the same
address as ICMR, a nd can be written and read onl y whe n the ICE bit i s cleared to 0 in ICCR.
SAR is initialized to H'00 by a reset.
Bits 7 to 1Slave Address ( SVA6 to SVA0) : Set a unique add ress in bit s SVA6 to SVA0,
differing from the addresses of other slave devices connected to the I2C bus.
Rev. 1.0, 02/00, page 467 of 1141
Bit 0Format Select (FS): Used togeth er wit h the FSX bit in SARX and th e SW bit in
DDCSWR to select the communication format.
•I2C bus format: a ddressing format with acknowledge bit
•Synchronous seria l format : non-a ddressing format without acknow l edge bit, for master
mode only
•Formatless transfer (only for channel 0): non-addressing with or without a n acknowledge
bit and without detection of start or stop condit ion, for slave mode only.
The FS bit also specifies whether or not SAR slave address recognition is performed in slave
mode.
DDCSWR
Bit 6
SAR
Bit 0
SARX
Bit 0
SW FS FSX Operating Mode
0I
2C bus format
• SAR and SARX slave addresses recognized
0
1I
2C bus format (I nitial value)
• SAR slave address recognized
• SARX slave address ignored
0I
2C bus format
• SAR slave address ignor ed
• SARX slave address r ecognized
0
1
1 Synchronous serial format
• SAR and SARX slave addresses ignored
00
1
Formatless t r ansfer (start and stop conditions are not
detected)
• With acknowledge bit
0
1
1
1
Formatless tr ansfer* (start and st op condit ions are not
detected)
• Without acknowledge bit
Note: * Do not use this setting when automatically switching the m ode from form atless t ransfer
to I2C bus format by setting DDCSWR.
Rev. 1.0, 02/00, page 468 of 1141
23. 2. 3 Seco nd Slav e Address Re gist er (SARX)
7
SVAX6
0
R/W
6
SVAX5
0
R/W
5
SVAX4
0
R/W
4
SVAX3
0
R/W
3
SVAX2
0
R/W
0
FSX
1
R/W
2
SVAX1
0
R/W
1
SVAX0
0
R/W
Bit :
Initial value :
R/W :
SARX is an 8-bit readable/writable regi ster tha t stores the second sla ve addre ss and selects the
communication format. W hen the chip i s in slave mode (a nd the addressing format is selected), if
the upper 7 bit s of SARX match the upper 7 bits of the first frame rec eived a fter a start condition,
the chip operates as the slave device specified by the master device. SARX is assigned to the
same address as ICDR , and can be written and read only wh en the ICE bit is cleared to 0 in ICCR .
SARX is initialized t o H'01 by a rese t and in hardware standby mode.
Bits 7 to 1Second Slave Addre ss ( SVAX6 to SVAX0): Set a unique address in bits SVAX6 to
SVAX0, diff e ri ng from the addresses of othe r slave devic e s con nected to the I2C bus.
Bit 0Format Select X (FSX): Used toget he r wit h the FSX bit in SARX and the SW bit in
DDCSWR to select the communication format.
• I2C bus format: addre ssing form at with acknowle dge bit
• Synchrono us serial form at : non-address i ng form at withou t acknow l edge bit , for master mode
only
• Formatless transfer: non-addressing wit h or without a n acknowle dge bit and without det ection
of start or stop condition, for slave mode only.
The FSX bit al so specifie s whether or not SARX sla ve address recognition is performed in slave
mode. For details, see the description of the FS bit in section 23.2.2, Slave Address Register
(SAR).
Rev. 1.0, 02/00, page 469 of 1141
23.2.4 I2C Bus Mode Regi ster ( ICM R)
7
MLS
0
R/W
6
WAIT
0
R/W
5
CKS2
0
R/W
4
CKS1
0
R/W
3
CKS0
0
R/W
0
BC0
0
R/W
2
BC2
0
R/W
1
BC1
0
R/W
Bit :
Initial value :
R/W :
ICM R is an 8- b it readabl e/w ritable reg is ter tha t se lects whether th e MSB or LS B is tr an s ferr ed
first, performs ma ster mode wait control, and selects the master m ode transfe r clock frequency and
the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written and
read onl y when the ICE bit is set to 1 in ICCR.
ICMR is initialized to H'00 by a reset.
Bit 7MSB-Fi r st/LSB-First Select (M LS): Selects whether data is transferred MSB-first or
LSB-first.
If the number of bits in a frame, exclud ing the acknowl edge bit, is less than 8, transmit da ta and
receive data are stored differently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
Do not set this bit to 1 when the I2C bus forma t is used.
Bit 7
MLS Description
0 M SB-first (Init ia l value)
1 LSB-first
Rev. 1.0, 02/00, page 470 of 1141
Bit 6Wait Inser t ion Bit (WAIT)
Selects whether to insert a wait between the transfer of data and the acknowledge bit, in master
mode with the I2C bus format. When WAIT is set to 1, after the fall of t he cloc k for the final data
bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When
the IRIC flag i s cleared to 0 in ICCR, the wait e nds and the a cknowledge bit is transferred. If
WAIT is cleared to 0, data and ac knowledge bits are transferred consec utively with no wait
inserted.
The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of the
WAIT setting.
The setting of this bit is invalid in slave mode.
Bit 6
WAIT Description
0 Data and acknowledge bi ts transferred con secu tively (Initial value)
1 Wait inserted between data and acknowledge bits
Rev. 1.0, 02/00, page 471 of 1141
Bits 5 to 3Transfer Clock Select (CKS2 to CKS0): These bits, together with the IICX1 bit
(for channel 1) or IICX0 bit (for c hannel 0) in STCR, select the serial clock freque ncy in ma ster
mode. They should be set according to the required transfer rate.
STCR
Bits 5, 6 Bit 5 Bit 4 Bit 3 Transfer Rate
IICX CKS2 CKS1 CKS0 Clock φ = 8 MHz φ = 10 MHz
0φ/ 28 286 kHz 357 kHz01φ/ 40 200 kHz 250 kHz
0φ/ 48 167 kHz 208 kHz
0
1
1φ/ 64 125 kHz 156 kHz
0φ/ 80 100 kHz 125 kHz0
1φ/ 100 80.0 kHz 100 kHz
0φ/ 112 71.4 kHz 89.3 kHz
0
1
1
1φ/ 128 62.5 kHz 78.1 kHz
0φ/ 56 143 kHz 179 kHz0
1φ/ 80 100 kHz 125 kHz
0φ/ 96 83.3 kHz 104 kHz
0
11φ/ 128 62.5 kHz 78.1 kHz
0φ/ 160 50.0 kHz 62.5 kHz01φ/ 200 40.0 kHz 50.0 kHz
0φ/ 224 35.7 kHz 44.6 kHz
1
1
1
1φ/ 256 31.3 kHz 39.1 kHz
Rev. 1.0, 02/00, page 472 of 1141
Bits 2 to 0Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be
trans ferre d n ext. With the I 2C bus forma t (when the FS bit i n SAR or the FSX bi t in SARX is 0),
the data is transferred with one addition acknowle dge bit . Bit BC2 to BC0 settings should be
made during an interval betwee n transfer frames. If bits BC2 to BC0 are set to a value othe r than
000, the setting should be ma de while the SCL line is low.
The bit counter is initialized to 000 by a reset and when a start condition is detected. The value
returns to 000 at the e nd of a data transfer, including the ac knowledge bit.
Bit 2 Bit 1 Bit 0 Bits/Frame
BC2 BC1 BC0 Synchronous Serial Format I2C Bus Format
0 8 9 (Init ial value)011 2
02 3
0
113 4
04 50
15 6
06 7
1
1
17 8
Rev. 1.0, 02/00, page 473 of 1141
23.2.5 I2C Bus Control Regi ster (ICCR)
7
ICE
0
R/W
6
IEIC
0
R/W
5
MST
0
R/W
4
TRS
0
R/W
3
ACKE
0
R/W
0
SCP
1
W
2
BBSY
0
R/W
1
IRIC
0
R/(W)*
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
ICCR is an 8-bit readable /wri tab le regist er that en ables or disabl es the I2C b u s in terface, enables or
disables i nterrupts, selects mast e r or slave mode and tra nsmission or reception, enables or disables
acknowledgem ent, confirms t he I2C bus interface bus status, issues start/stop conditions, and
performs interrupt flag confirm at ion.
ICCR is initialized t o H'01 by a rese t.
Bit 7I2C Bus Interfac e Enable (ICE): Selects whether or not the I2C bus interf ace is to be
used. W hen ICE i s set to 1, port pins function as SCL and SDA input/out put pins and transfer
operations are enabled. When ICE is cleared to 0, the IIC stops and its internal status is initialized.
The SAR and SARX registers can be ac cessed when ICE is 0. The ICMR and ICDR re gisters ca n
be accessed when ICE is 1.
Bit 7
ICE Description
0I2C bus interface module disabled, with SCL and SDA signal pins set to port function
The inte rnal stat us of the IIC is init ia liz e d
SAR and SARX can be accessed (I nitial value)
1I
2C bus interface module enabled for transfer operations (pins SCL and SCA are
driving the bus)
ICMR and ICDR can be accessed
Bit 6I2C Bus Interface Interr upt Enabl e (IEIC) : Enables or disables interrupts from the I2C
bus interface to the CPU.
Bit 6
IEIC Description
0 Int errupts disabled (Init ial value)
1 Int errupts enabled
Rev. 1.0, 02/00, page 474 of 1141
Bits 5 and 4Master/ Sl ave Sele ct (MST) and Tra nsmit/Recei ve Selec t (TRS) : MST selects
whether the I2C bus interface operates in master mode or slave mode.
TRS selects whether the I2C bus interface operates in transmit mode or receive mode.
In master mode with the I2C bus format, when arbitration is lost, MST and TRS are both reset by
hardware, causing a t ransition to slave receive mode . In slave receive mode with t he addressing
format (FS = 0 or FSX = 0), hardware automatically selects transmit or re cei ve mode acc ording to
the R/W bit in the first frame after a start condition.
Modification of the TRS bit duri ng transfer i s deferred until transfer of the frame containing the
acknowledge bit is completed, and the changeover is made after completion of the transfer.
MS T an d TR S select the op er ating mo de as fo llows.
Bit 5 Bit 4
MST TRS Description
0 Slave receive mode ( I nitial value)0
1 Slave transmit mode
0 Master receive mode1
1 Master transmi t mode
Bit 5
MST Description
0 Slave mode (Init ial value)
[Clearing condit ions]
1. When 0 is written by software
2. When bus arbitration is lost after transmission is started in I2C bus format master
mode
1 Master mode
[Setting condition s]
1. When 1 is written by software (in cases other than clear ing condition 2)
2. When 1 is writt en in M ST af t er reading MST = 0 (in case of clearing condition 2)
Rev. 1.0, 02/00, page 475 of 1141
Bit 4
TRS Description
0 Receive mode (Init ial value)
[Clearing condit ions]
1. When 0 is written by software (in cases other than setting condition 3)
2. When 0 is writt en in TRS after reading TRS = 1 (in case of setting condition 3)
3. When bus arbitration is lost after transmission is started in I2C bus format master
mode
4. When the SW bit in DDCSWR changes from 1 to 0
1 Transmit mode
[Setting condition s]
1. When 1 is written by software (in cases other than clear ing conditions 3)
2. When 1 is writt en in TRS after reading TRS = 0 (in case of clearing conditions 3)
3. When a 1 is received as the R/W bit of the first frame in I2C bus f ormat slave mode
Bit 3Acknowle dge Bit Judge ment Se lection (ACKE): Specifies whether the value of the
acknowledge bit returned from the receiving device when using the I2C bus format is to be ignored
and cont i nuous t ransfer is performed, or tra nsfer i s to be aborted a nd error handli ng, etc. ,
performed if the acknowledge bit is 1. When the ACKE bi t is 0, the value of the re ceived
acknowledge bit is not indicated by the ACKB bit, which is always 0.
When the ACKE bit is 0, the T DRE, IRIC, and IRT R flags are set on completion of data
transmission, regardless of the val ue of the acknowl e dge bit. When the ACKE bit is 1, the TDRE,
IRIC, and IRTR flags are set on completion of data transmi ssion when the acknowledge bit is 0,
and the IRIC flag alone is se t on com pletion of data transmission when the acknowledge bit is 1.
Depending on the receiving device, the acknowledge bit may be significant, in indicating
completion of processing of the received data, for i nstance, or may be fixed at 1 a nd have no
significance.
Bit 3
ACKE Description
0 The value of the acknowledge bit is ignored, and cont inuous transfer is performed
(Init ial value)
1 If the acknowledge bit is 1, cont inuous transfer is interr upted
Rev. 1.0, 02/00, page 476 of 1141
Bit 2Bus Busy (BB SY) : The BBS Y fl ag can b e r ead to che ck whether the I2C bu s ( SCL, SDA)
is busy or free. In master mode, thi s bit is also used to issue start and stop conditions.
A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting
BBSY to 1. A low-to-high tra nsition of SDA while SCL is high is recognized a s a stop condit i on,
clear ing BBS Y to 0.
To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit
start condit ion is issued in t he same way. To issue a stop condition, use a MOV instruction to
write 0 in BBSY and 0 in SCP.
It is not possible to write to BBSY in slave mode; the I2C bus interface must be set to master
transmit mode before issuing a start condition. MST and TRS should bot h be set to 1 before
writing 1 in BBSY and 0 in SCP.
Bit 2
BBSY Description
0Bus is free (Init ial value)
[Clearing condition]
When a stop condition is det ected
1 Bus is busy
[Setting condition]
When a start condition is det ected
Bit 1I2C Bus Interface Interr upt Reque st Flag (IRIC): Indicates that the I2C bus interfa ce has
issued an interrupt reque st to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave
address or general call addre ss is detected i n slave re ceive mode, when bus arbitration is lost in
master transmit mode, and when a stop condition is detected. IRIC is set at different times
depending on the FS bit in SAR and the W AIT bit in ICMR. See section 23.3.6, IRIC Se tting
Timing and SCL Control. The conditions unde r which IRIC is set also di ffer depending on t he
setting of the ACKE bit in ICCR.
IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 i n IRIC.
When the DTC i s used, IRIC is cleared a utomatically and tra nsfer can be performed continuously
without CPU intervention.
Rev. 1.0, 02/00, page 477 of 1141
Bit 1
IRIC Description
0 Waiting for t ransfer, or transfer in progress (I nit ial value)
[Clearing condition]
When 0 is written in IRIC after reading IRIC = 1
(1) Int errupt requested
[Setting condition s]
• I2C bus forma t maste r mode
1. When a start condition is detected in the bus line state after a start condition is
issued
(when the TDRE flag is set t o 1 because of first frame transmission)
2. When a wait is inser t ed between the data and acknowledge bit when W AIT = 1
3. At the end of dat a transfer
(when the TDRE or RDRF flag is set to 1)
4. When a slave address is received af ter bus arbitration is lost
(when the AL f lag is set to 1)
5. When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
• I2C bus format slave m ode
1. Whe n the slave address (SVA, SVAX) matche s
(when the AAS and AASX flags are set to 1)
and at t he end of data transfer up to the subsequent retransm ission start condition
or stop condition detection
(when the TDRE or RDRF flag is set to 1)
2. When the general call address is detected
(when the ADZ f lag is set to 1)
and at t he end of data transfer up to the subsequent retransm ission start condition
or stop condition detection
(when the TDRE or RDRF flag is set to 1)
3. When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
4. When a stop condition is detected
(when the STO P or ESTP flag is set to 1)
• Synchronous ser ial format
1. At the end of dat a transfer
(when the TDRE or RDRF flag is set to 1)
2. When a star t condition is detected with serial format select ed
• When a condition, other than the above, that sets the TDRE or RDRF flag to 1 is
detected
Rev. 1.0, 02/00, page 478 of 1141
Whe n , with the I 2C bus forma t selected, IRIC i s set to 1 and an interrupt is gene rated, othe r flags
must be checked in order to ident i fy the source that set IRIC to 1. Alt hough e ach source has a
corresponding flag, ca ution is needed at t he end of a tra nsfer.
When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. The
IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a
retransmi ssi o n sta rt con ditio n or stop co nditi o n after a slave add ress ( SVA) or general call a ddre ss
match in I2C bus format slave mode.
Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set.
The IRIC and IRTR flags are not cleared at the end of the specified numbe r of transfers in
continuous t ransfer using t he DT C. The TDRE or RDRF flag i s cleared, however, since the
specified number of ICDR reads or writes have been completed.
Table 23.3 shows the relationship between the flags and the transfer states.
Note: * This LSI does not incorpora t e DT C.
Rev. 1.0, 02/00, page 479 of 1141
Table 23. 3 Flags and Transfer States
MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB State
1/01/0000000000Idle state (flag clearing
required)
11000000000Start condit ion
issuance
11100100000Start condit ion
established
11/0100000000/1Master mode wait
11/0100100000/1
Master mo de
transmi t/r eceive end
0010001/011/01/00Arbitration lost
00100000100SAR match by first
frame in slave mode
00100000110General call address
match
00100010000SARX match
01/0100000000/1Slave mode
transmi t/r eceive end
(except after SARX
match)
0
01/0
11
10
00
01
01
10
00
00
00
1Slave mo de
transmi t/r eceive end
(after SARX match)
01/001/01/0000000/1
Stop condition
detected
Bit 0Start Co ndi ti on/Stop Conditi on Pr o hibit (SCP ) : Controls the issuing of start and st op
conditions in master mode. To issue a st a rt condi tion, wri te 1 in BBSY and 0 in SCP. A
retransmit start c ondition is issued in t he same way. T o issue a stop condition, writ e 0 in BBSY
and 0 in SCP. This bit is always read a s 1. If 1 i s written, the data is not stored.
Bit 0
SCP Description
0 Wr it ing 0 issues a start or stop condition, in combination with the BBSY flag
1Reading always returns a value of 1 (I nitial value)
Wr iting is ignor ed
Rev. 1.0, 02/00, page 480 of 1141
23.2.6 I2C Bus Status Register ( ICSR)
7
ESTP
0
R/(W)*
6
STOP
0
R/(W)*
5
IRTR
0
R/(W)*
4
AASX
0
R/(W)*
3
AL
0
R/(W)*
0
ACKB
0
R/W
2
AAS
0
R/(W)*
1
ADZ
0
R/(W)*
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
ICSR is a n 8-bit readable/wri table regi ster that performs flag confirmation and ac knowledge
confirmation and control.
ICSR is initialized to H'00 by a reset.
Bit 7Error Stop Conditi on Detection Fl ag (ESTP): Indicates t hat a stop condition ha s been
detected during frame transfer in I2C bus format slave mode.
Bit 7
ESTP Description
0 No e rr or st o p condit io n (Initial value)
[Clearing condition]
1. When 0 is written in ESTP after reading ESTP = 1
2. When the IRIC flag is cleared to 0
1• In I2C bus format slave mode: Er r or stop condition detected
[Setting condition]
When a stop condition is det ected dur ing frame transfer
• In other modes: No meaning
Rev. 1.0, 02/00, page 481 of 1141
Bit 6Normal Stop Condition Detection Flag (STOP): Indic ates that a st op condition has been
detected after completion of frame transfer in I2C bus format sl ave mode.
Bit 6
STOP Description
0 No normal stop condition (Init ial value)
[Clearing condition]
1. When 0 is written in STO P after reading STOP = 1
2. When the IRIC flag is cleared to 0
1• In I2C bus format slave mode: Er r or stop condition detected
[Setting condition]
When a stop condition is det ected af t er complet ion of frame transfer
• In other modes:No me aning
Bit 5I2C Bus Interface Conti nuo us Tra nsmissi o n/ Rec e ptio n Interr upt Request Fla g
(IRTR): Indicates that the I2C bus interface has issue d an int errupt request to the CPU, a nd the
source is c ompletion of reception/transmi ssion of one fram e in continuous transmission/reception
for whi c h DTC activation is possible . Whe n the IRT R flag is set to 1, the IRIC fla g is also set to 1
at the same time.
IRTR fla g setting is performed when the TDRE or RDRF flag i s set to 1. IRTR is cleared by
reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared automatically
when the IRIC flag is cleared to 0.
Note: * This LSI does not incorpora t e DT C.
Bit 5
IRTR Description
0 Waiting for t ransfer, or transfer in progress (I nit ial value)
[Clearing condition]
1. When 0 is written in I RTR after reading IRTR = 1
2. When the IRIC flag is cleared to 0
1 Continuous transfe r state
[Setting condition]
• In I2C bus interfa ce s lave mode: When the TDRE or RDRF f la g is set to 1 when
AASX = 1
• In other m odes: When th e TDRE or RDRF flag is se t to 1
Rev. 1.0, 02/00, page 482 of 1141
Bit 4Second Slav e Addr e ss Recognition Fl ag (AASX): In I2C bus format slave receive mode,
th i s flag is set to 1 if the first fr am e foll o wing a start conditi o n match es bits SVAX6 to SVAX0 in
SARX.
AASX is cl eared by readi n g AASX afte r it has been set to 1, then writin g 0 in AASX. AASX i s
also cleared aut omatically when a start condition is detected.
Bit 4
AASX Description
0 Second slave address not recognized ( I nit ial value)
[Clearing condition]
1. Whe n 0 is written in AASX aft er reading AASX = 1
2. When a star t condition is detected
3. In maste r mo de
1 Second slave address r ecognized
[Setting condition]
When the second slave address is detected in slave receive mode
Bit 3Arbitrat ion Los t (AL): This flag indicates that arbitration was lost in master mode. The
I2C bus interface monitors the bus. When two or more master devices attempt to seize the bus at
nearly the same ti me, if the I 2C bus interfa ce detects data differing from the da ta it sent, it se ts AL
to 1 to indicate that the bus has been taken by another master.
AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is
reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 3
AL Description
0 Bus arbitration won (Initial value)
[Clearing condit ions]
1. When ICDR data is written (transmit mode) or r ead (receive mode)
2. When 0 is writt en in AL after reading AL = 1
1 Arbit ra tion lost
[Setting condition s]
1. If the inter nal SDA and SDA pin disagree at the rise of SCL in mast er transmit
mode
2. If the inter nal SCL line is high at the fall of SCL in master transmit mode
Rev. 1.0, 02/00, page 483 of 1141
Bit 2Sla ve Addre ss Recogni t ion Fla g (AAS): In I2C bus format slave receive mode, this flag is
set to 1 if the first fr am e following a sta rt con diti on matc hes bits SVA6 to SVA0 in SAR, or if the
general call address (H'00) is detected.
AAS is cl ea red by readi n g AAS after it has bee n set to 1, then wri ti ng 0 in AAS. In add it i o n, AAS
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 2
AAS Description
0 Slave addr ess or general call address not recognized ( Initial value)
[Clearing condit ions]
1. When ICDR data is written (transmit mode) or r ead (receive mode)
2. When 0 is written in AAS after reading AAS = 1
3. In maste r mo de
1 Slave addr ess or general call address recognized
[Setting condition]
When the slave addr ess or gener al call address is detected when FS = 0 in slave
rece i v e mode
Bit 1Genera l Call Address Rec o gnition Flag (ADZ): In I2C bus format slave receive mode,
this f lag is se t to 1 if the fir s t fra me fo llo wing a start cond ition is the gen e r al call address (H'00) .
ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition,
ADZ is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in
rec eive mod e.
Bit 1
ADZ Description
0 General call addr ess not recognized (Init ial value)
[Clearing condit ions]
1. When ICDR data is written (transmit mode) or r ead (receive mode)
2. When 0 is writt en in ADZ after reading ADZ = 1
3. In maste r mo de
1 General call addr ess recognized
[Setting condition]
If the gener al call address is detected when FSX = 0 or FS = 0 is selected in the
slave receive mode .
Rev. 1.0, 02/00, page 484 of 1141
Bit 0Acknowle dge Bit (ACK B): Sto res acknow l edge data. In transmit mode, aft er the
receiving device receives data, i t returns acknowledge dat a, and thi s data is loa ded into ACKB. In
receive mode, after data has been received, the acknowledge data set in this bit is sent to the
transmitting device.
When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line
(returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal
so ftware is r ead.
Bit 0
ACKB Description
0 Receive mode: 0 is output at acknowledge out put tim ing (Initial value)
Transmit m ode: Indicat es that the receiving device has acknowledged the data
(signal is 0)
1 Receive mode: 1 is output at acknowledge out put tim ing
Transmit mode: Indicat es that the r eceiving device has not acknowledged t he dat a
(signal is 1)
23.2.7 Serial/Timer Control Register (STCR)
7
—
0
—
6
IICX1
0
R/W
5
IICX0
0
R/W
4
—
0
—
3
FLSHE
0
R/W
0
—
0
—
2
OSROME
0
R/W
1
—
0
—
Bit :
Initial value :
R/W :
STCR is an 8-bit re adable/writa ble register that controls t he IIC operating mode.
STCR is initialized to H'00 by a reset.
Bit 7Reserved: This bit cannot be m odified a nd is always read as 0.
Bits 6 and 5I2C Transfer Select 1, 0 (IICX1, 0): These bits, together with bits CKS2 to CKS0
in ICMR of IIC, select the transfer rate in master mode. For details, see section 23.2.4, I2C Bus
Mode Register (ICM R).
Bit 3Flash Memory Control Resister Enable (FLSHE): This bit selects the control resister of
the flash memory. For details, refer to section 7.3.5, Serial Timer Control Resister (STCR).
Bit 2OSD ROM Enable (OSROME): Thi s bi t cont rol s th e OSD ROM. For detail s, r e fe r to
section 7, ROM.
Bits 4 and 2 to 0Reserved: These bits cannot be modifi ed and are always rea d as 0.
Rev. 1.0, 02/00, page 485 of 1141
23. 2. 8 DDC Switc h Register ( DDCSWR)
7
SWE
0
R/W
6
SW
0
R/W
5
IE
0
R/W
4
IF
0
R/(W)*
1
3
CLR3
1
W*
2
0
CLR0
1
W*
2
2
CLR2
1
W*
2
1
CLR1
1
W*
2
Notes: 1.
2. Only 0 can be written to clear the flag.
Always read as 1.
Bit :
Initial value :
R/W :
DDCSWR is an 8-bit read/writ e register that controls aut omatic format switching for IIC cha nnel
0 and IIC int ern al latch clearing. DDCSWR is initialized to H'0F by a reset or in hardware standby
mode.
Bit 7DDC Mode Switch E nable (SWE ): Enables or disables automatic switching from
formatless transfer to I2C bus format transfer for IIC cha nnel 0.
Bit 7
SWE Description
0 Disables aut omatic switching from formatless transfer to I2C bus forma t trans fer for
II C channel 0. (Init ial value)
1Enables aut omatic switching from format less transfer to I2C bus format transfer for IIC
channel 0.
Bit 6DDC Mode Switch ( SW): Selects formatless transfer or I2C bus format transfer for IIC
channel 0.
Bit 6
SW Description
0I
2C bus format is select ed for IIC channel 0. (I nitial value)
[Clearing condit ions]
1. When 0 is written by software
2. When an SCL f alling edge is detected when SWE = 1
1 Formatless t r ansfer is selected for IIC channel 0.
[Setting condition]
When 1 is written after SW = 0 is read
Rev. 1.0, 02/00, page 486 of 1141
Bit 5DDC Mode Switch Int errupt Enable Bit (IE) : Enabl e s or disables an i nterrupt request to
the CPU when the format for IIC channel 0 is automatically switched.
Bit 5
IE Description
0 Disables an interrupt at automatic format switching (Initial value)
1 Enables an interr upt at autom atic format switching
Bit 4DDC Mode Switch Int errupt Flag (IF) : Indicates t he interrupt request t o the CPU when
the format for IIC channel 0 is automatically switched.
Bit 4
IF Description
0 Int errupt has not been r equested (Init ial value)
[Clearing condition]
When 0 is written after IF = 1 is read
1 Int errupt has been r equested
[Setting condition]
When an SCL falling edge is detected when SW E = 1
Bits 3 to 0IIC Clear 3 to 0 (CLR3 to CLR0): Control the IIC0 and IIC1 initialization. These
are write-only bits and are always read as 1.
Writing to these bits generates a clearing signal for the internal latch circuit which initializes the
IIC status.
The data written to t hese bits a re not held. W hen ini tializing the IIC, be sure to use the MOV
instruction to write to all the CLR3 to CLR0 bits at the same time; do not use bit manipulation
instructions such as BCLR.
When reinitializing the module status, the CLR3 to CLR0 bits must be rewritten.
Rev. 1.0, 02/00, page 487 of 1141
Bit 3 Bit 2 Bit 1 Bit 0
CLR3 CLR2 CLR1 CLR0 Description
0This setting m ust not be used
0 This set t ing m ust not be used0
1 IIC0 internal latch cleared
0 IIC1 internal latch cleared
01
1
1 II C 0 and IIC1 int er nal latc hes cleared
1This settin g is invalid
Rev. 1.0, 02/00, page 488 of 1141
23. 2. 9 Modul e Sto p Contr ol Regi ster (MSTP CR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
MSTPCR comprises two 8-bit readable/writable regist e rs, and is used to perform module stop
mode control .
When the corresponding bit in MSTPCR is set to 1, operation of the c orresponding IIC channel is
halted at the end of the bus cycle, and a transition is made to module st op mode. For details, see
section 4.5, Module Stop Mode .
MSTPCR is initialized to H'FFFF by a reset. It is not ini tiali zed in standby m ode.
MSTPCRL Bit 7Module Stop (MSTP7) : Specifies the module stop mode for IIC channel 0.
MSTPCRL
Bit 7
MSTP7 Description
0 Module stop m ode for IIC channel 0 is cleared
1 Module stop m ode for IIC channel 0 is set (I nitial value)
MSTPCRL Bit 6Module Stop (MSTP6) : Specifies the module stop mode for IIC channel 1.
MSTPCRL
Bit 6
MSTP6 Description
0 Module stop m ode for IIC channel 1 is cleared
1 Module stop m ode for IIC channel 1 is set (I nitial value)
Rev. 1.0, 02/00, page 489 of 1141
23.3 Operation
23.3.1 I2C Bus Data Format
The I2C bus inter f ac e has se rial and I2C bus formats.
The I2C bus formats are addressing forma ts wit h an ac knowledge bit. These a re shown i n figures
23.3(1) a nd (2). The first frame following a start condition a l ways consists of 8 bits. Formatless
transfer can be selected onl y for IIC channel 0. The forma tless transfer data is shown in figure
23.3 (3).
The serial format is a non-addressing form at with no acknowledge bi t. T hi s is shown in figure
23.4.
Figure 23. 5 shows the I2C bus ti ming.
The symbols used in figures 23.3 to 23.5 a re explained in ta ble 23.4.
SASLA
7n
R/W DATA A
1
1m
111A/A
1P
1Transfer bit count
(n = 1 to 8)
Transfer frame count
(m = 1 or above)
S SLA
7n1 7
R/W A DATA
11
1m1
1A/A
1S
1SLA R/W
1
1m2
A
1DATA
n2 A/A
1P
1
Upper: Transfer bit count (n1 and N2 = 1 to 8)
Lower: Transfer frame count (m1 and m2 = 1 or above)
(1) FS = 0 or FSX = 0
An
DATADATA A
1m
181 A/A
1Transfer bit count
(n = 1 to 8)
Transfer frame count
(m = 1 or above)
(3) Formatless (IIC channel 0 only, FS = 0 or FSX = 0)
(2) Start condition transmission, FS = 0 or FSX = 0
Figure 23.3 I2C Bus Data Form ats (I2C Bus Formats)
Rev. 1.0, 02/00, page 490 of 1141
S DATA
8n
DATA
1
1m
P
1Transfer bit count
(n = 1 to 8)
Transfer frame count
(m = 1 or above)
FS = 1 and FSX = 1
Figure 23.4 I2C Bus Data Format (Serial Format)
SDA
SCL
S SLA R/ A
981-7 981-7 981-7
DATA A DATA A/ P
Figure 23.5 I2C Bus Timing
Table 23. 4 I2C Bus Data Format Symbols
Symbol Description
S Start condition. The master device dr ives SDA f rom high t o low while SCL is hig
SLA Slave address, by which the master device selects a slave device
R/
:
Indicates the direction of data transfer: from the slave device to the master device
when R/
:
is 1, or from the master device to the slave device when R/
:
is 0
AAcknowledge. The receiving device (the slave in master transmit m ode, or the
master in master r eceive mode) dr ives SDA low to acknowledge a transfer
DATA Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first
or LSB-first format is selected by bit MLS in ICMR
P Stop condition. The master device drives SDA f rom low t o high while SCL is high
23.3.2 Master Transmit Operati on
In master transmit mode, the master device outputs the transmit clock and transmit data, and the
slave device ret urns an acknowledge signal. The transmit proc e dure and ope rations in master
transmit mo d e are described be lo w .
1. Set bit ICE in ICCR to 1. Set bits MLS, WAIT , and CKS2 to CKS0 in ICMR, and bit IICX in
STCR, accordi ng to the oper ating mod e.
2. Read the BBSY flag in ICCR , check that the bus is fr ee, th en set MST and TRS to 1 in ICCR
to select master transmit mode. After that, write 1 in BBSY and 0 in SCP. This generates a
start condit ion by causing a high-t o-low transition of SDA while SCL i s high. As a resul t, the
Rev. 1.0, 02/00, page 491 of 1141
TDRE internal flag is set to 1 and the IRIC and IRTR flags are also set to 1. If IEIC is set to 1
in ICCR, a CPU i nterrupt i s requested.
3. If bit FS is 0 in SAR or bit FSX is 0 in SARX, the first frame following the start condition
contains a 7-bit slave address and indicates the transmit/receive direction. Write data (slave
address + R/
:
) to ICD R. A t th is time , the TDRE in terna l flag is cleared to 0. Th e written
address dat a is transferred to ICDRS, and the TDRE i nternal fla g is set to 1 again. Cl ear IRIC
flag to 0 so th at the en d of tr ansfer c an b e de termined. The master de vice o utp uts the written
data together with a sequence of transmit clock pulses at the timing shown in figure 23.6. The
sel ec te d sla ve device (the devic e with the matc hing slave address) drives SDA low at the ninth
transmit clock pulse to acknowledge the da ta.
4. When one frame of dat a has been transm itted, the IRIC flag is set to 1 in ICCR at the ri se of
the ninth transmit clock pulse. After one frame has been transferred, if the TDRE internal flag
is 1, SCL is automatically brought to the low level in synchronization wit h the i nternal cloc k
and held low.
5. When another data is to be sent, write it in ICDR. After making sure that the data has been
sent to ICDRS and the T DRE flag i s set to 1, clear the IRIC flag to 0. Transmission of the ne xt
frame is turned on in synchronization wi th the inter n al clock.
Steps 4 and 5 can be repeated t o transmit data continuously. To end the tra nsmission, clear IRIC,
write dummy data in ICDR after making sure that the last data has been sent (the next
transmission date is not present on ICDRT yet). Then, write 0 in BBSY and 0 in ICCR when IRIC
is set agai n . This generat es a stop condi ti on by causing a lo w-to-hi g h tran sit i on of SDA while
SCL is high.
Rev. 1.0, 02/00, page 492 of 1141
SDA
(Master output)
SDA
(Slave output)
21 214365879
Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
ICDRT
ICDRS
TDRE
SCL
(Master output)
Start condition
issuance
Interrupt
request
generated
Interrupt request
generated
Data 1
Address + RW
Data 1
Address + RW
Write BBSY=1 and
SCP=0 (Start
condition issuance)
User processing
Slave address Data 1
R/W [4]
A
[2] Write ICDR
[3] Clear IRIC
[3] Write ICDR
[5] Clear IRIC
[5]
Figure 23.6 Example of Ti ming in Master Transmit Mode (MLS = WAIT = 0)
Rev. 1.0, 02/00, page 493 of 1141
When continuously transmi tting data,
6. Clear IRIC flag to 0 before startup of the 9th transmit clock of the data being transmitted, and
then write the next transmit data in ICDR.
7. 1 frame data transmission ends, a nd upon startup of t he 9th t ransmit cloc k, IRIC fl ag in ICCR
is set t o 1. At the same time, the next t ransmit data written in ICDR (ICDRT) is transferred t o
ICDRS, the flag in TDRE is set to 1, then the next frame transmission is executed, being
synchronized with the internal cl ock.
Steps 6 and 7 can be repeated t o transmit data continuously. (See figure 23.7.)
SDA
(Master output)
SDA
(Slave output)
21 2314365879
Bit 7 Bit 6 Bit 5 Bit 7 Bit 6 Bit 5Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
ICDRT
ICDRS
TDRE
SCL
(Master output)
Interrupt
request
generated
Data 2Data 1
[6] Write ICDR
Write ICDR [6] Write ICDR[6] Clear IRIC
[6] Clear IRIC
User processing
Data 1
Data 1 Data 2 Data 3
Data 2
[7]
[7]
A
Figure 23.7 Example of Continuous Transmission Timing i n Master Transmit Mode
(MLS = WAIT = 0)
Rev. 1.0, 02/00, page 494 of 1141
23.3.3 Master Receive Operation
In master receive mode , the master device outpu ts the rec eive clock, r eceiv es dat a, and returns an
acknowledge signal. The slave device transmits the data. The receive procedure and operations in
master rec eive mode a re described below.
1. Clear TRS to 0 in ICCR to switch from transmit mode t o receive mode.
2. Read ICDR to start receiving (dummy data read). When ICDR is read, a receive clock is
output in synchronization with the internal clock, and data is received.
At the ninth c lock pul se the master device drive s SDA low to acknowledge the da ta.
3. When one frame of dat a has been received, t he IRIC flag is set to 1 in ICCR at the rise of the
ninth receive c l ock pulse. If IEIC i s set to 1 in ICCR, a CPU interrupt is reque sted. If the
RDRF int e rnal fl ag is 0 at this t ime, it is set to 1, and conti nuous reception is performed. If
reception of the ne xt frame is completed before t he ICDR read a nd IRIC flag c learing in step 4,
SCL is aut omatically brought to the low level in synchronization with the internal clock and
held low.
4. Read ICDR and clear IRIC to 0 in ICCR. At this time , RDRF flag is cleared to 0.
Steps 3 and 4 can be repeated to receive data continuously. At the time the mode is first switched
from master trans mi t mode to master receiv e mod e and receptio n has just started, RDRF internal
flag is cleared to 0, therefore data reception of the next frame is automatically started. To stop
receiving, TRS bit must be set to 1 before startup of the next frame receive clock.
To stop receiving, set TRS to 1, read ICDR, then writ e 0 in BBSY and 0 in SCP i n ICCR. T his
gen e ra tes a stop condi ti on by causi n g a low-to-hi g h tran sition of SDA while SCL is high.
Rev. 1.0, 02/00, page 495 of 1141
SDA
(Master output)
SDA
(Slave output)
21 2143658799
Bit 7 Bit 6 Bit 5 Bit 7 Bit 6Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
ICDRS
ICDRR
RDRF
SCL
(Master output)
Interrupt
request
generated
Interrupt
request
generated
Master transmit
mode Master receive
mode
Data 2
[1]Clear TRS to 0 [2]Read ICDR
(dummy read) [4] Read ICDR [4] Clear IRIC
Clear
IRIC
User
processing
Data 1
Data 1
Data 2
[3]
A
A
Figure 23.8 Example of Ti ming in Master Receive Mode (MLS = WAIT = ACKB = 0)
Rev. 1.0, 02/00, page 496 of 1141
23.3.4 Slave Receive Operation
In sl av e receive mo de, the master d evice ou tp uts the transmi t clock an d tr an smit d ata, and the
slave device ret urns an acknowledge signal. The receive procedure and operations in slave receive
mode are described below.
1. Set bit ICE in ICCR to 1. Set bits MLS in ICMR and bits MST and T RS in ICCR according to
the operating mode.
2. A start condition output by the master device sets the BBSY flag to 1 in ICCR.
3. After the slave device detects the start condition, if the first frame matches its slave address, it
functions a s the slave device designated as the master de vice. If the 8th bit da t a (R/
:
) is 0,
TRS bit in ICCR remains 0 and executes slave receive operation.
4. At the ninth cloc k pulse of the receive frame, the slav e devic e driv e s SDA low to ac knowle dg e
the transfer. At the same ti me, the IRIC flag i s set to 1 in ICCR. If IEIC is 1 in ICCR, a CPU
interrupt is requested. If t he RDRF i nternal flag is 0, it is set to 1 and continuous reception is
performed. If the RDRF internal fla g is 1, the slave device hol ds SCL low from the fall of the
receive clock until it has read the data in ICDR.
5. Rea d ICDR and clear IRIC to 0 in ICCR. At this time, the RDFR fla g is c leared to 0.
Steps 4 and 5 can be repeated to receive data continuously. When a stop condition is detected (a
low- t o -hi g h transit i o n of SDA while SCL is high), the BBSY flag is cleare d to 0 in ICCR.
Rev. 1.0, 02/00, page 497 of 1141
SDA
(Master output)
SDA
(Slave output)
21 214365879
Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
ICDRS
ICDRR
RDRF
SCL
(Master output)
Start condition
issurance
SCL
(Slave output)
Interrupt request
generated
Address + R/W
Address + R/W
[5] Read ICDR [5] Clear IRIC
User processing
Slave address Data 1
[4]
A
R/W
Figure 23.9 Example of Ti ming in Sl ave Receive Mode (MLS = ACKB = 0)
Rev. 1.0, 02/00, page 498 of 1141
SDA
(Master output)
SDA
(Slave output)
214365879879
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 1 Bit 0
IRIC
ICDRS
ICDRR
RDRF
SCL
(Master output)
SCL
(Slave output)
Interrupt
request
generated
Interrupt
request
generated
Data 2
Data 2
Data 1
Data 1
[5] Read ICDR [5] Clear IRIC
User processing
Data 2
Data 1 [4] [4]
A
A
Figure 23.10 Example of Timing in Slave Re ceive Mode (MLS = ACK B = 0)
Rev. 1.0, 02/00, page 499 of 1141
23.3.5 Slave Transmit O peration
In slave transmit mode, the slave device outputs the transmit data, and the master device outputs
the transmi t clock and returns an acknowle dge si gnal. The transmit proce dure and operations in
slave tr ansmit mo de are describ ed be low.
1. Set bit ICE in ICCR to 1. Set bits MLS in ICMR and bits MST and T RS in ICCR according to
the operating mode.
2. After the sl ave devi ce detects a start condition, if the first frame ma tches its slave address, a t
the ninth clock pul se the slave device drives SDA low to acknowle dge the transfer. At the
same time, the IRIC flag is set to 1 i n ICCR, and if the IEIC bit in ICCR is set to 1 at this time,
an interrupt request is se nt to t he CPU. If the eighth data bit (R/
:
) is 1, the TRS bit is set to 1
in ICCR, automatically causing a transition to slave transmit mode. The slave device holds
SCL low from the fall of the transmit clock until data is written in ICDR.
3. Clear the IRIC flag to 0, then write data in ICDR. The written data is transferred to ICDRS,
and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. Clear IRIC to 0,
then write the next data in ICDR. The slave device outputs the written data serially in step
with the clock output by the master device, with the timing shown in figure 23.11.
4. When one frame of data has been transmitted, at the rise of the ninth transmit clock pulse IRIC
is set t o 1 in ICCR. If the TDRE internal flag is 1, the sla ve device holds SCL low from the
fa l l of the tran smi t clo c k until data is writ te n in ICDR. The master device dri ves SDA lo w at
the ninth clock pulse to acknowledge t he data. T he acknowledge signal i s stored in the ACKB
bit in ICSR, and can be used to check whether the transfer was carried out normally. If TDRE
int er n al flag is se t to 0 , th e d ata writ ten in IC D R is tr an s ferred to ICD R S, then tr ansmis s io n
starts and TDRE internal flag and IRIC and IRTR flags are all set to 1 again.
5. To continue transmitting, clear IRIC to 0, then write the next transmit data in ICDR. At this
time, the TDRE internal flag is cleared to 0.
Steps 4 and 5 can be repeated t o transmit continuously. To e nd t he transmission, write H'FF in
ICDR. When a stop condition is detected (a low-to-high transition of SDA while SCL is high), the
BBSY fla g will be cleared to 0 in ICCR.
Rev. 1.0, 02/00, page 500 of 1141
SDA
(Slave output)
SDA
(Master output)
SCL
(Slave output)
21 21436587998
Bit 7 Bit 6 Bit 5 Bit 7 Bit 6Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
ICDRS
ICDRT
TDRE
SCL
(Master output)
Interrupt
request
generated
Interrupt
request
generated
Interrupt
request
generated
Slave receive mode Slave transmit mode
Data 1 Data 2
[3] Clear IRIC [5] Clear IRIC[3] Write ICDR [3] Write ICDR [5] Write ICDR
User
processing
Data 1
Data 1 Data 2
Data 2
A
R/W
A
[3]
[2]
Figure 23.11 Example of Timing in Slave Transmit Mode (MLS = 0)
23. 3. 6 IRIC Setting Timing and SCL Contr ol
The interrupt reque st flag (IRIC) is se t at different t imes depending on the W AIT bi t in ICMR, the
FS bit i n SAR, and the FSX bit in SARX. If the TDRE or RDRF internal fla g is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figure 23.12 shows the IRIC set timing and SCL control .
Rev. 1.0, 02/00, page 501 of 1141
SCL
SDA
IRIC
User
processing Clear
IRIC Write to ICDR (transmit) or
read ICDR (receive)
1A87
1987
SCL
SDA
IRIC
User
processing Clear IRIC Write to ICDR (transmit) or
read ICDR (receive)
1A8
198
Clear IRIC
SCL
SDA
IRIC
User
processing Clear IRIC Write to ICDR (transmit) or
read ICDR (receive)
187
187
(a) When WAIT = 0, and FS = 0 or FSX = 0 (I
2
C bus format, no wait)
(b) When WAIT = 1, and FS = 0 or FSX = 0 (I
2
C bus format, wait inserted)
(c) When FS = 1 and FSX = 1 (synchronous serial format)
Fi g ure 23.12 IRIC Setting Timing and SCL Control
Rev. 1.0, 02/00, page 502 of 1141
23.3.7 Automatic Switching from For matless Transfe r to I2C Bus Format Transfer
Setting the SW bit in DDCSWR to 1 selects the IIC0 formatless transfer operation. When an SCL
falling edge is detected, the operating mode automatically switches from formatless transfer to I2C
bus format transfer (slave m ode). For automatic swi tching to be possible, the following four
conditions must be observed:
1. The same dat a pin ( SDA) is use d in common fo r format le ss t ra nsf er an d I2C bus format
transfer.
2. Separate clock pins are used for formatless transfer and I2C bus format transfer (SYNC1 for
formatless, a nd SCL for I2C bus format)
3. The SCL pi n is ke pt high during forma tless transfer.
4. Regi ster bit s other tha n the TRS bit in ICCR are set to appropriate values so t hat I2C bus
format tra nsfer can be perform ed.
The operating mode is automatically switched from formatless transfer to I2C bus format transfer
when an SCL falling edge is detected and the SW bit in DDCSWR is automatically cleared to 0.
To switch the mode from I2C bus format transfer to formatless transfer, set the SW bit to 1 by
software.
During formatless transfer, do not modify the bits that control the I2C bus inte rface opera ting
mode, such as the MSL or TRS bit. When switching from the I2C bus format transfer to formatless
transfer, specify the formatless transfer direction (transmit or receive) by setting or clearing the
TRS bit, then set the SW bit to 1. After the automatic switching from formatless transfer to I2C bus
format tra nsfer (sla ve mode), the TRS bit is aut omatically cleared to 0 to enter the sla ve addre ss
receive wait state.
If an SCL falling edge is det ected during formatless transfer, the IIC does not wait for the stop
condition but switches t he operating m ode immediately.
Rev. 1.0, 02/00, page 503 of 1141
23.3.8 Noise Canceler
The logic leve l s at the SCL and SDA pins a re route d through noise canc elers before bei ng latched
internally. Figure 23. 13 shows a bloc k diagram of the noise canceler circuit.
Th e noise canceler con sists of two cascad ed la tc hes an d a match dete ct o r. The SCL (or SDA)
input signa l is sampled on the system cloc k, but i s not passed forward to t he next circuit unless the
outputs of both latches a gree. If they do not agree , the previous value is held.
SCL or SDA
input signal Internal SCL
or SDA signal
Sampling clock
Sampling
clock
System clock
period
C
Latch
QD
C
Latch
QD Match
detector
Figure 23.13 Block Diagram of Noise Canceler
23.3.9 Sample Flowcharts
Figures 23.14 to 23. 17 show sampl e flowcharts for using the I2C bus interface in each mode.
Rev. 1.0, 02/00, page 504 of 1141
Start
End
Initialize
Read BBSY flag in ICCR
Read IRIC flag in ICCR
Read ACKB bit in ICSR
Read ACKB bit in ICSR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Write transmit data in ICDR
Master receive mode
Write transmit data in ICDR
Set MST=1 and
TRS=1 in ICCR
Write BBSY=0 and
SCP=0 in ICCR
Write BBSY=1 and
SCP=0 in ICCR
BBSY=0?
No
IRIC=1?
ACKB=0?
No
No
Yes
Yes
Yes
Transmit
mode?
IRIC=1?
End of transmission
(ACKB = 1)?
No
No
No
Yes
Yes
Yes
[1]
[2]
[3]
[4]
[7]
[5]
[6]
[8]
[9]
[10]
Clear IRIC flag in ICCR
Test the status of the SCL and SDA lines.
Select master transmit mode.
Generate a start condition.
Set transmit data for the first byte (slave
address +R/W)
Wait for 1 byte to be transmitted.
Test for acknowledgement by the
designated slave device.
Set transmit data for the second and
subsequent bytes.
Wait for 1 byte to be transmitted.
Test for end of transfer.
Generate a stop condition.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
Figure 23.14 Flowchar t for Master Transmit Mode (Example)
Rev. 1.0, 02/00, page 505 of 1141
End
Set TRS=0 in ICCR
Clear IRIC flag in ICCR
Set ACKB=1 in ICSR
Set TRS=1 in ICCR
Read ICDR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Set ACKB=0 in ICSR
Write BBSY=0 and
SCP=0 in ICCR
Last receive?
IRIC=1?
No
No
Yes
Yes
Read ICDR
Read ICDR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
IRIC=1?
No
Yes
[3]
[1]
[2]
[5]
[6]
[4]
[7]
[8]
[9]
[10 ]
Master receive mode
Select receive mode.
Set acknowledge data.
Start receiving. The first read is a dummy
read.
Wait for 1 byte to be received.
Set acknowledge data for the last receive.
Start the last receive.
Wait for 1 byte to be received.
Select transmit mode.
Read the last receive data (if ICDR is read
without selecting transmit mode, receive
operations will resume).
Generate a stop condition.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
Figure 23.15 Flowchar t for Master Receive M ode (Example)
Rev. 1.0, 02/00, page 506 of 1141
Start
End
Initialize
Read IRIC flag in ICCR
Read AAS and ADZ flags in ICSR
Read TRS bit in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read ICDR
Read ICDR
Read ICDR
Set ACKB=0 in ICSR
General call address processing
*Description omitted
Set MST=0 and
TRS=0 in ICCR
IRIC=1?
No
Yes
Read IRIC flag in ICCR
Set ACKB=0 in ICSR
IRIC=1?
No
Yes
TRS=0?
IRIC=1?
No
No
Yes
Yes
Yes
AAS=1 and
ADZ=0?
[2]
[1]
[3]
[8]
[5]
[6]
[4]
[7]
Slave transmit mode
Last receive?
No
No
Yes
Select slave receive mode.
Wait for 1 byte to be received (slave
address)
Start receiving. The first read is a dummy
read.
Wait for the transfer to end.
Set acknowledge data for the last receive.
Start the last receive.
Wait for the transfer to end.
Read the last receive data.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Figure 23.16 Flowchar t for Sl ave Transmit Mode (Example)
Rev. 1.0, 02/00, page 507 of 1141
End
Write transmit data in ICDR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read ACKB bit in ICSR
Set TRS=0 in ICCR
Read ICDR
Read IRIC flag in ICCR
IRIC=1?
Yes
Yes
No
No
[1]
[4]
[5]
[2]
[3]
Slave transmit mode
End of transmission
(ACKB=1)?
Clear IRIC in ICCR
Set transmit data for the second and
subsequent bytes.
Wait for 1 byte to be transmitted.
Test for end of transfer.
Select slave receive mode.
Dummy read (to release the SCL line).
[1]
[2]
[3]
[4]
[5]
Figure 23.17 Flowchar t for Sl ave Receive Mode (Example)
23.3.10 Initializing Internal Status
The IIC can forcibly initialize the IIC internal status when a dead lock occurs during
communication. Initialization is enabled by (1) se tting the CLR3 to CL R0 bits in DDCSWR, or (2)
clearing the ICE bit. For details on CLR3 to CLR0 settings, re fer to section 23.2.8, DDC Switch
Register (DDCSWR).
(1) Ini tialized St atus
This function i nitializes the following:
• TDRE and RDRF internal flags
• Transmi t/receive sequen cer and in ternal clock counter
• Internal la tches (wait, c lock, or data output ) which holds the levels out put from the SCL and
SDA pin s
This function doe s not initialize the following:
• Register conte nts (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, and STCR)
Rev. 1.0, 02/00, page 508 of 1141
• Internal la tches which holds the re gister re ad inform ation to set or clear the flags i n ICMR,
ICCR, ICSR, and DDCSWR
• Bit counter (BC2 to BC0) value i n ICMR
• Sources of interrupts generated (interrupts t hat has be en transferred to t he interrupt
controller)
(2) Notes o n I n itiali zation
• Interrupt flags and interrupt source s are not cl eared; clear them by soft ware if necessary.
• Other register flags cannot be assumed to be cleared, either; clear them by software if
necessary.
• When initialization is specified by the DDCSWR settings, the data written to the CLR3 to
CLR0 bit s are not held. Whe n initializing the IIC, be sure to use t he MOV instruction to
write to all the CLR3 to CLR0 bits at the same time; do not use bit manipulation
instructions such as BCLR. When reinitializing the module status, all the CLR3 to CLR0
bits must be rewritten to at the same time.
• If a flag is cleared during transfer, the IIC module stops transfer immediately, and releases
the control of t he SCL and SDA pins. Be fore starting again, set t he regist ers to appropri ate
values to make a correct communication if necessary.
This module initializing function does not modify the BBSY bit value, but in some cases,
depending on the SCL and SDA pin sta tus and the release timing, the signal waveform s at the
SCL and SDA pins may i ndica te t he stop con diti on, and acc o rdi n gly the BBSY bit may be
cleared. Other bits or flags may be affe cted in the same way by module i nitialization.
To avoi d these problems, take the following procedure to ini t ialize the IIC:
1. Initialize the IIC by setting the CLR3 to CLR0 bits or the ICE bit.
2. Execute a stop condition issuing instruction to clear the BBSY bit to 0 (writing 0 to BBSY and
SCP), and wait for two cycles of the transfer clock.
3. Initialize the IIC again by setting the CLR3 to CLR0 bits or the ICE bit.
4. Set the registers i n IIC to appropriate values.
Rev. 1.0, 02/00, page 509 of 1141
23.4 Usage Notes
1. In mas ter mod e, if an in s tr uction to generate a start cond ition is immediately fol lo w ed by an
instruction to generate a stop condition, ne ither condit ion will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read t he relevant port s, check that SCL and SDA are both l ow, then issue the
instruction that generates the stop condition. Note that the SCL may briefly remain at a high
level immediately after BBSY is cleared to 0.
2. Ei ther of t he following two conditions wil l start t he next transfer. Pa y attention to these
conditions when reading or writing t o ICDR.
a. Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
ICDRT to ICDRS)
b. Rea d access to ICDR whe n ICE = 1 and TRS = 0 (including automatic transfe r from
ICDRS to ICDRR)
3. Table 23.5 shows the tim ing of SCL and SDA output in synch r oniza ti on with the int ern al
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
Table 23. 5 I2C Bus Timi ng ( SCL and SDA Output)
It em Symbol O utput Timing Uni t Not es
SCL out put cycle time tSCLO 28tcyc to 256tcyc ns
SCL out put high pulse width t SCLHO 0.5tSCLO ns
SCL out put low pulse widt h t SCLLO 0.5tSCLO ns
SDA output bus free time t BUFO 0.5tSCLO-1tcyc ns
Start condition output hold time t STAHO 0.5tSCLO-1tcyc ns
Retrans missi on sta rt condition
output setup time tSTASO 1tSCLO ns
Stop condition outpu t setup time tSTOSO 0.5tSCLO+2tcyc ns
Data output setup time (master) 1tSCLLO-3tcyc ns
Data output setup time (slave)
tSDASO 1tSCLL - (6tcyc or 12tcyc*) ns
Data output hold time tSDAHO 3tcyc ns
Figure 30.9
(reference)
Note: * 6tcyc when IICX is 0, 12tcyc when 1.
4. SCL and SDA input i s sampled in sync h roniz at i o n with the inte r n al cloc k. The AC tim ing
therefore depends on the system clock cycle tcyc, as shown in table 30.6 in section 30, Electrical
Characteristics. Note that the I2C bus interface AC timing specifications will not be met with a
system clock frequency of less than 5 MHz.
Rev. 1.0, 02/00, page 510 of 1141
5. The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for high-
sp eed mo d e). In master mo de, the I2C bus interfac e monitors the SCL line a nd synchronizes
one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) ex ceeds
the time determined by the input cl ock of the I2C bus interface, the hi gh period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 23.6.
Table 23. 6 Permissible SCL Ri se Time (tsr) Values
Time Indication [ns]
IICX tcyc Indication
I2C Bus
Specification
(Max.) φ = 8 MHz φ = 10 MHz
Normal mode 1000 937 75007.5t
cyc
High-speed mode 300 ←←
Normal mode 1000 ←←
1 17.5tcyc
High-speed mode 300 ←←
6. The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I2C b us inte rfa ce SCL and SDA output tim i n g is pre scribed by tScyc, as shown
in table 23.5. However, because of the rise and fall times, the I2C b u s in terface s p ecifications
may not be satisfied at the maximum transfer rate. Table 23.7 shows output timing
calculations for different operating frequencies, including the worst-case influence of rise and
fal l times.
tBUFO fa ils to meet the I2C bus interface specifications at any frequency. The solution is either
(a) to provide coding to secure the ne cessary inte rval (a pproximately 1 µs) betwee n is s u an ce of
a stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I2C bus.
tSCLLO in h igh-speed mode and tSTASO in standar d mo de f ail to satisf y th e I2C bus interface
specifications for worst-case ca lculations of tSr/tSf. Possible solutions that sh oul d be
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices
whose i nput timing pe rmits this output timing for use as slave devices connected to the I2C
bus.
Rev. 1.0, 02/00, page 511 of 1141
7. Precautions on reading ICDR at the end of master receive mode
When terminating the master rec eive mode , set TRS bit to 1, and select "wri te" for ICCR
BBSY = 0 and SCP = 0. T his fo rces to m o ve SDA from low to high level when SCL is at high
level, thereby generating the stop condition.
Now you can read receive d data from ICDR. If, however, any dat a is rem aining on the buffer,
received data on ICDRS i s not t ransferred t o ICDR, thus you won't be able to read the second
byte data.
When it is required to read the second byte data, issue the stop condition from the master
receive state (TRS bit is 0).
Before reading data from ICDR register, ma ke sure tha t BBSY bi t on ICCR register is 0, stop
condition is generated a nd bus is made free.
If you try to rea d received data afte r the stop condition issue instruction (setting ICCR' s BBSY
= 0 and SCP = 0 to write) has been executed but before the a ctual stop condition is genera ted,
clock may not be a ppropriately signaled when the next maste r sending mode is t urned on.
Thus, reasonable care is needed for determining when to read the received data.
After the master receive is complete, if you want to re-write IIC control bit (such as clearing MST
bit) for switching t he sending/ receiving m ode or modifying set tings, it must be done during period
(a) indi cated in fi gure 23.18 (after ma king sure ICCR register BBSY bit is cleared to 0).
SDA
SCL
Internal clock
BBSY bit
Bit 0 A
(a)
89
Stop condition Start
condition
Start condition
is issued
Generation of the stop
condition is checked
(BBSY = 0 is set to read)
The stop condition
issue instruction
(BBSY = 0 and SCP = 0
set to write) is executed
Master receive mode
ICDR read
inhibit period
Figure 23.18 Precautions on Re ading the Master Rec eive Data
Rev. 1.0, 02/00, page 512 of 1141
Table 23. 7 I2C Bus Timi ng ( with Maxim um Influence of tSr/tSf)
Time Indication (at Maximum Transfer Rate) [ns]
Item tcyc Indication
tSr/tSf
Influence
(Max.)
I2C Bus
Specification
(Min.) φ = 8 MHz φ = 10 MHz
Normal mode −1000 4000 ←←
tSCLHO 0.5tSCLO
(-tSr)High-speed
mode −300 600 ←←
Normal mode −250 4700 ←←
tSCLLO 0.5tSCLO
(-tSf)High-speed
mode −250 1300 ←←
Normal mode −1000 4700 3875*1 3900*1
tBUFO 0.5tSCLO-1tcyc
(-tSr)High-speed
mode −300 1300 825*1 850*1
Normal mode −250 4000 4625 4650tSTAHO 0.5tSCLO-1tcyc
(-tSf)High-speed
mode −250 600 875 900
Normal mode −1000 4700 9000 9000tSTASO 1tSCLO
(-tSr)High-speed
mode −300 600 2200 2200
Normal mode −1000 4000 4250 4200tSTOSO 0.5tSCLO+2tcyc
(-tSr)High-speed
mode −300 600 1200 1150
Normal mode −1000 250 3325 3400tSDASO
(master) 1tSCLLO*3-3tcyc
(-tSr)High-speed
mode −300 100 625 700
Normal mode −1000 250 2200 2500tSDASO
(slave) 1tSCLL*3-12tcyc*2
(-tSr)High-speed
mode −300 100 −500*1 −200*1
Normal mode 0 0 375 300tSDAHO 3tcyc High-speed
mode 00↑↑
Notes: 1. Does not meet the I2C bus interface specif ication. Remedial act ion such as the
following is necessary: (a) secure a star t/stop condition issuance interval; (b) adjust t he
rise and fall times by means of a pull-up r esistor and capacitive load; (c) reduce the
transfer rate; (d) select slave devices whose input timing perm its this output t im ing.
The values in the abov e table will vary depending on the sett ings of the I ICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve t he
maximum transfer rate; therefore, whether or not the I2C bus int erface specifications are
met must be determined in accordance with t he actual setting conditions.
2. Value when the I ICX bit is set to 1. When the I I CX bit is cleared to 0, the value is (tSCLL -
6tcyc).
3. Calculated using t he I2C bus specificat ion values (standard mode: 4700 ns min.; high-
speed mode: 1300 ns min.).
Rev. 1.0, 02/00, page 513 of 1141
Section 24 A/D Converter
24.1 Overview
This LSI i ncorporates a 10-bit successive-approxima t ions A/D converter that allows up to 12
ana lo g input ch an nels to be selecte d .
24.1.1 Features
A/D convert er has the followi ng features.
• 10-bit re solution
• 12 input channels
• Sample and hold function
• Choice of soft ware, ha rdware (int ernal signal) t riggering or ext ernal triggering for A/D
conversion start.
• A/D conversion end interrupt re quest generation
Rev. 1.0, 02/00, page 514 of 1141
24.1.2 Block Diagram
Figure 24. 1 shows a bloc k diagram of the A/D conve rter.
φ/2
φ/4
ADTRG
Interrupt request
AN0 Vref
AVCC
AVSS
Reference Voltage
Sample-and-
hold circuit
Chopper type
comparator
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
ANA
ANB
DFG
ADTRG
(HSW timing generator)
Internal data bus
[Legend]
ADR
AHR : Software trigger A/D result register
: Hardware trigger A/D result register ADTRG, DFG
ADTRG : Hardware trigger
: A/D external trigger input
ADCR
ADCSR: A/D control register
: A/D control/status register
ADTSR: A/D trigger selection register
-
+
10-bit
D/A
Hardware
control
circuit
Control circuit
Analog multiplexer
Successive
approximation register
A
D
R
A
H
R
A
D
C
S
R
A
D
C
R
A
D
T
S
R
Figure 24.1 Block Diagr am of A/D Converter
Rev. 1.0, 02/00, page 515 of 1141
24.1.3 P i n Confi guration
Table 24.1 summarizes the input pins used by the A/D converter.
Tabl e 24. 1 A/D Co nver ter Pins
Name Abbrev. I/O Function
Analog power supply pin AVCC Input Analog block power supply and A/D
conversion reference volt age
Analog gr ound pin AVSS Input Analog block ground and A/D conversion
reference voltage
Analog input pin 0 AN0 I nput Analog input channel 0
Analog input pin 1 AN1 I nput Analog input channel 1
Analog input pin 2 AN2 I nput Analog input channel 2
Analog input pin 3 AN3 I nput Analog input channel 3
Analog input pin 4 AN4 I nput Analog input channel 4
Analog input pin 5 AN5 I nput Analog input channel 5
Analog input pin 6 AN6 I nput Analog input channel 6
Analog input pin 7 AN7 I nput Analog input channel 7
Analog input pin 8 AN8 I nput Analog input channel 8
Analog input pin 9 AN9 I nput Analog input channel 9
Analog input pin A ANA Input Analog input channel A
Analog input pin B ANB Input Analog input channel B
A/D external tr igger input pin
$'75*
Input External trigger input for starting A/D
conversion
Rev. 1.0, 02/00, page 516 of 1141
24.1.4 Regi ster Configur ati on
Table 24.2 summarizes the registers of the A/D converter.
Tabl e 24. 2 A/D Co nver ter Re gist ers
Name Abbrev. R/W Si z e Initi al Value Addr ess*2
Software trigger A/D
result register H ADRH R Byte H'00 H'D130
Software trigger A/D
result register L ADRL R Byte H'00 H'D131
Har d ware tr ig g er A/D
result register H AHRH R Byte H'00 H'D132
Har d ware tr ig g er A/D
result register L AHRL R Byte H'00 H'D133
A/D contr ol register ADCR R/W Byte H'40 H'D134
A/D c ontro l/ st atu s
register ADCSR R (W)*1 Byte H'01 H'D135
A/D trigger selection
register ADTSR R/W Byte H'FC H'D136
Port mode register 0 PMR0 R/W Byt e H'00 H'FFCD
Notes: 1. O nly 0 can be wr itten in bits 7 and 6, to clear the f lag. Bits 3 t o 1 are read-only.
2. Lower 16 bits of the address .
Rev. 1.0, 02/00, page 517 of 1141
24.2 Regi ster Descri pt i on s
24.2.1 Software -Triggered A/D Result Register (ADR)
ADRH ADRL
1 03254 ——————
——————
7
0
R
6
0
R
9
0
R
8
0
R
11
0
R
10
0
R
0
R
0
R
0
R
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
0
R
12131415
000000
Bit :
Initial value :
R/W :
The softwa re-triggered A/D result register (ADR) is a re gister that store s the result of an A/D
con ver si o n starte d by software.
The A/D-c onverted data is 10-bit data. Upon compl etion of software-triggered A/D conversion,
the 10-bit resul t data is transferred t o ADR and the data is retained until the next software-
triggered A/D conversion completion. The upper 8 bits of the data are stored in the upper bytes
(bits 15 to 8) of ADR, and the lower 2 bits are stored in the lower bytes (bits 7 and 6). Bits 5 to 0
are always read as 0.
ADR can be read by t he CPU at any time, but the ADR va lue duri ng A/D conversion is not fixe d.
The upper bytes can always be read directly, but the data in the lower bytes is transferred via a
temporary re gister (T EMP). For details, see section 24. 3, Interfac e to Bus Master.
ADR is a 16-bit read-onl y register whi c h is i nitialized t o H'0000 at a reset , and i n module stop
mode, stan db y mo d e, w atch mod e, subactive mod e and su bsleep mode.
24. 2. 2 Har dware-Trigg ered A/D Result Register (AHR)
AHRH AHRL
1 03254 ——————
——————
7
0
R
6
0
R
9
0
R
8
0
R
11
0
R
10
0
R
0
R
0
R
0
R
AHR9 AHR8 AHR7 AHR6 AHR5 AHR4 AHR3 AHR2 AHR1 AHR0
0
R
12131415
000000
Bit :
Initial value :
R/W :
The hardware-triggered A/D result register (AHR) is a register that stores the result of an A/D
con ver si o n starte d by hard ware (int ern al signal : ADT R G and DFG) or by exte rnal t rig ger inp ut
(
$'75*
).
The A/D-c onverted data is 10-bit data. Upon compl etion of hardware- or external-triggered A/D
conversion, the 10-bit result data is transferred to AHR and the data is retained until the next
hardware- or external- triggered A/D conversion completion. The upper 8 bits of the data are
stored in the upper byte s (bits 15 to 8) of AHR, and the lower 2 bit s are stored in the lower bytes
(bits 7 and 6). Bits 5 to 0 are always read as 0.
Rev. 1.0, 02/00, page 518 of 1141
AHR can be read by t he CPU at any time, but the AHR va lue duri ng A/D conversion is not fixe d.
The upper bytes can always be read directly, but the data in the lower bytes is transferred via a
temporary re gister (T EMP). For details, see section 24. 3, Interfac e to Bus Master.
AHR is a 16-bit read-onl y register whi c h is i nitialized t o H'0000 at a reset , and i n module stop
mode, stan db y mo d e, w atch mod e, subactive mod e and su bsleep mode.
24. 2. 3 A/D Contro l Regist er (ADCR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
—
—
1
7
R/WR/WR/W
HCH1
0
R/W
CK HCH0 SCH3 SCH2 SCH1 SCH0
Bit :
Initial value :
R/W :
ADCR is a register that sets A/D conversion speed and selects analog input channel. When
executing ADCR setting, make sure that the SST and HST flags in ADCSR is set to 0.
ADCR is an 8-bit readable/writable register that is initialized to H'40 by a reset, and in module
stop mode, standby mode, watc h mode, subactive m ode and subsleep mode.
Bit 7Clock Select (CK): Sets A/D conversion speed.
Bit 7
CK Description
0 Conversion freq uency is 266 states (Initial value)
1 Conversion freq uency is 134 states
Note: A/D conversion starts when 1 is written in SST, or when HST is set to 1. The conver sion
period is the time from when this start flag is set unt il the flag is cleared at the end of
conversion. Actual sample-and-hold takes place (r epeatedly) dur ing the conversion
frequency shown in figure 24.2.
Rev. 1.0, 02/00, page 519 of 1141
Conversion frequency
Note: IRQ sampling;
Conversion period (134 or 266 states)
Interrupt request flag
IRQ sampling
(CPU)
States
Instruction execution MOV.B
WRITE
Start flag
When conversion ends, the start flag is cleared and the interrupt request flag is
set. The CPU recognizes the interrupt in the last execution state of an instruction,
and executes interrupt exception handling after completing the instruction.
Figure 24.2 Inter nal Operation of A/D Conver ter
Bit 6Reserved: This bit cannot be m odified a nd is always read as 1.
Bits 5 and 4Hardware Channel Select (H CH1, HCH0): These bits select the analog input
channel that is convert ed by hardware tri ggering or t riggering by an external input. Only channels
AN8 to ANB are available for hardware- or external-triggered conversion.
Bit 5 Bit 4
HCH1 HCH0 Ana log Input Channel
0 AN8 (Init ial value)01AN9
0ANA11ANB
Rev. 1.0, 02/00, page 520 of 1141
Bits 3 to 0Software Channel Selec t (SCH 3 to SCH0): These bits select the analog input
channel that is convert ed by software triggering.
When channels AN0 to AN7 are used, appropri ate pin settings must be made in port mode re gi ster
0 (PMR0). For pi n set tings, see section 24. 2.6, Port Mode Register 0 (PMR0).
Bit 3 Bit 2 Bit 1 Bit 0
SCH3 SCH2 SCH1 SCH0 Analog Input Channel
0 AN0 (Init ial value)0
1AN1
0AN2
0
1
1AN3
0AN40
1AN5
0AN6
0
1
11AN7
0AN801AN9
0ANA
0
1
1ANB
1
1 * * No channel select ed for software-triggered conversion
Notes: 1. If conversion is start ed by softwar e when SCH3 to SCH0 are set to 11**, the conversion
result is undetermined. Hardwar e- or ext e rnal-triggered conversion, however, will be
performed on the channel selected by HCH1 and HCH0.
2. * Don't care.
Rev. 1.0, 02/00, page 521 of 1141
24. 2. 4 A/D Contro l / Status Register (ADCSR)
0
—
—
0
1
0
R
2
0
R
3
0
4
0
R/W
5
0
67
R/(W)* RR/W
ADIE
0
R/(W)*
SEND SST HST BUSY SCNLHEND
1
Bit :
Initial value :
R/W :
Note: * Only 0 can be written to bits 7 and 6, to clear the flag.
The A/D status register (ADCSR) is an 8-bit register that can be used to start or stop A/D
conversion, or check the status of the A/D converter.
A/D conversion starts when 1 is written in SST flag. A/D conversion can also sta rt by setting HST
flag to 1 by hardware- or external-triggeri ng.
For ADTRG start by HSW timing ge nerator in hardware triggeri ng, see sec t ion 26.4, HSW (Head-
switch) Timing Generator.
When conversion ends, the converted data is stored in the software-triggered A/D result register
(ADR) or hardware-triggered A/D result register (AHR), and the SST or HST bit is cleared to 0.
If softwa re-triggering a nd hardware- or external -triggering are genera ted at the same time, priority
is given t o hardware- or external-triggering.
ADCSR is an 8-bit register which is initialized to H'01 by a reset, and in module stop mode,
standby mode, watch m ode, subactive mode and subsleep mode.
Bit 7Softwar e A/D End Fl ag (SEND): Indicates the e nd of A/D conversion.
Bit 7
SEND Description
0 [Clearing Conditions] (Init ial value)
0 is wr itten after reading 1
1[Setting Conditions]
Software-triggered A/D conver sion has ended
Bit 6Hardware A/ D End Flag (HEND): Indicates tha t hardware - or external-triggere d A/D
conversion ha s ended.
Bit 6
HEND Description
0 [Clearing Conditions] (Init ial value)
0 is wr itten after reading 1
1[Setting Conditions]
Hardware- or external-triggered A/D conversion has ended
Rev. 1.0, 02/00, page 522 of 1141
Bit 5A/D Interr upt Enable ( ADIE) : Selects enable or disable of interrupt (ADI) ge neration
upon A/ D conversion end.
Bit 5
ADIE Description
0 Int errupt (ADI) upon A/D conver sion end is disabled ( I nit ial value)
1 Int errupt (ADI ) upon A/D conver sion end is enabled
Bit 4Softwar e A/D Start Fl ag (SST): Indicates or controls the start and end of software-
triggered A/D conversion. This bit remains 1 during software-triggered A/D conversion.
When 0 is written in t his bit, softwa re-triggered A/D conversion ope ration can forcibly be abort e d.
Bit 4
SST Description
Read: Indicates t hat software-triggered A/ D conver sion has ended or been stopped
(Init ial value)
0
Write: Soft ware-triggered A/D conversion is aborted
Read: Indicates t hat software-triggered A/D conversion is in progress1
Write: Starts sof tware- trigge red A/D conver sion
Bit 3Hardware A/D Status Fl ag (HST): Indicates the status of hardware- or external-trigge red
A/D conversion. Whe n 0 is wri tten in thi s bit , A/D conversion is aborted regardless of whether it
was hardware-triggered or external-triggered.
Bit 5
HST Description
Read: Hardware- or external-triggered A/D conver sion is not in progress(Initial value)
0
Write: Hardwar e- or exter nal-triggered A/D conversion is abor ted
1 Hardware- or external-triggered A/D conversion is in progress
Rev. 1.0, 02/00, page 523 of 1141
Bit 2Busy Flag (BUS Y ): During hardwar e- or extern al- trigger ed A/D conversion, if software
attempts to start A/D conversion by writing to the SST bit, the SST bit is not modified and instead
the B USY fla g is set to 1.
This flag is cleared when the hardware-triggered A/D result register (AHR) is read.
Bit 2
BUSY Description
0 No contention for A/ D conver sion (Initial value)
1 Indicates an attempt t o execut e software-triggered A/D conversion while hardware- or
external-triggered A/D conversion was in progress
Bit 1Software-Triggered Conversion Cance l Flag (SCNL): Indicates that software-triggered
A/D conversion was c anceled by the sta rt of hardware -triggered A/D conversion.
This flag is cleared when A/D conversion is started by software.
Bit 1
SCNL Description
0 No contention for A/ D conver sion (Initial value)
1 Indicates that software-triggered A/D conversion was canceled by the st art of
hardware-triggered A/D conversion
Bit 0Reserved: This bit cannot be m odified a nd is always read as 1.
Rev. 1.0, 02/00, page 524 of 1141
24. 2. 5 T r igger Selec t Register (ADTSR)
0123
0
4
R/W
567 ——————
——————
TRGS1
0
R/W
TRGS0
111111
Bit :
Initial value :
R/W :
The trigger select register (ADTSR) selects hardware- or external-triggered A/D conversion start
factor.
ADTSR is an 8-bit readable/writable register that is initialized to H'FC by a reset, and in module
stop mode, standby mode, watc h mode, subactive m ode and subsleep mode.
Bits 7 to 2Reserved: Thes e bits canno t be mo d ified an d are always r ead as 1.
Bits 1 and 0Trigger Select (TRGS1, TRGS0): These bits select hardware- or external-
triggered A/D conversion start factor. Set the se bits when A/D conve rsion is not in progress.
Bit 1 Bit 0
TRGS1 TRGS0 Description
0Hardware- or ext ernal-triggered A/D conversion is disabled
(Init ial value)
0
1 Hardware-triggered (ADTRG ) A/D conver sion is selected
0 Hardware-triggered (DFG) A/D conversion is selected1
1 External-trigger ed (
$'75*
) A/ D conversion is selected
24.2. 6 Port M od e Regis ter 0 (P MR0)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PMR04 PMR03 PMR02 PMR01 PMR00
0
R/W
PMR07
R/WR/WR/W
PMR06 PMR05
Bit :
Initial value :
R/W :
Port mode register 0 (PMR0) controls switching of each pin function of port 0. Switching is
specified for each bit.
PMR0 is an 8-bit readable/writable register and is initialized to H'00 by a reset.
Rev. 1.0, 02/00, page 525 of 1141
Bits 7 to 0P07/AN7 to P00/AN0 Pin Switching (PM R07 to PMR00): These bits set the
P0n/ANn pin as the input pin for P0n or as the ANn pin for A/D conversion analog input channe l.
Bit n
PMR0n Description
0 P0n/ANn func t ions as a general-purpose input port ( Initial value)
1 P0n/ANn func t ions as an analog input channel
(n = 7 to 0)
24. 2. 7 Modul e Sto p Contr ol Regi ster (MSTPCR)
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Bit :
Initial value :
R/W :
MSTPCR consists of 8-bit readable/writable re gisters and pe rforms m odule stop mode control.
When the MSTP2 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus
cycle and a transition is made to module stop mode. For details, see section 4.5, Module Stop
Mode.
MSTPCR is ini tial iz e d to H'FFFF by a reset
Bit 2Module Stop (MST P2): Specifies the A/D converter module stop mode.
MSTPCRL
Bit 2
MSTP2 Description
0 A/D converter module stop mode is cleared
1 A/D converter module stop mode is set (Initial value)
Rev. 1.0, 02/00, page 526 of 1141
24.3 In t erf ace t o Bu s Mast er
ADR and AHR are 16-bit registers, but t he data bus to the bus master is only 8 bits wide.
Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is
accessed via a temporary register (TEMP).
A data reading from ADR and AHR is performed a s follows. When the upper byte is read, t he
upper byte val ue is tra nsferred to the CPU and the lower byte va l ue is transfe rred to TEMP. Next,
when the lower byte is read, the TEMP contents are transferred to the CPU.
When reading ADR and AHR, always read the upper byte before the lower byte. It is possible to
read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 24. 3 shows the data flow for ADR access. The data fl ow for AHR access is the same.
Bus master
(H'AA)
ADRH
(H'AA) ADRL
(H'40)
Lower byte read
Bus master
(H'40)
ADRH
(H'AA) ADRL
(H'40)
TEMP
(H'40)
TEMP
(H'40)
Module data bus
Module data bus
Bus
interface
Bus
interface
Upper byte read
Fi g ure 24.3 ADR Acce ss Operatio n ( Readi ng H'AA40 )
Rev. 1.0, 02/00, page 527 of 1141
24.4 Operation
The A/D c onverter operates by successive approxim ations with 10-bit resolution.
24.4.1 Software-Tri ggered A/D Conversion
A/D conversion starts when software sets the software A/D start flag (SST bit) to 1. T he SST bit
remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends.
Conversion can be software-triggere d on a ny of the 12 channels provided by analog input pins
AN0 to ANB. Bits SCH3 to SCH0 in ADCR select the analo g input pi n used for software-
triggered A/D conversion. Pins AN8 to ANB are also available for hardware- or external-
triggered conv ersion .
When conversion ends, SEND flag in ADCSR bit is set to 1. If ADIE bit in ADCSR is also set to
1, an A/D conversion end interrupt occurs .
If the conversion time or input channel selection in ADCR needs to be changed during A/D
conversion, to avoid malfunctions, first clear the SST bit to 0 to halt A/D conversion.
If softwa re writes 1 in the SST bi t to start software-triggered conve rsion whi le hardware- or
external-trigge red conversion is in progress, the hardware- or external-trigge red conversion has
prior it y an d the software -t r igg e re d co nve r sion is not exe c ut e d. At this tim e, B USY fla g in
ADCSR i s set to 1. The BUSY fla g is cleared to 0 when the hardware-tri gge red A/D result
register (AHR) i s read. If conversion is tri ggered by hardware while software -triggere d
conversion i s in progress, the software-triggered conve rsion is imm e diately ca nceled and the SST
flag is cleared to 0, and SCNL flag in ADCSR is set to 1. The SCNL flag is cleared when
software writes 1 in t he SST bit to start conversion after the hardware -t riggered conversion e nds.
Rev. 1.0, 02/00, page 528 of 1141
24.4.2 H ar dware- or Exter nal-Triggered A/D Conversion
The system cont ains the hardware trigger function that a l lows to turn on A/D conve rsion at a
spe c ified timi n g by use of the har dware trigger (i nternal si gnal s: ADTRG and DFG) and the
incoming external trigger (
$'75*
). This function can be used to measure an analog signal that
varies i n synchronization with an e xternal signal at a fixe d timing.
To execut e hardware - or e xternal-triggered A/D conversion, select a ppropriate start factor in
TRGS1 and TRGS0 bits in ADTSR. When the selected triggering occurs, HST flag in ADCSR is
set to 1 and A/D conversion starts. The HST flag remains 1 during A/D conversion, and is
automatically cleared to 0 when conversion ends. For ADTRG start by HSW timing generator in
hardware triggering, se e section 26.4, HSW Ti ming Gene rator. Setting of the ana log input pins on
four channels from AN8 to ANB ca n be modified wi t h the hardware trigger or the incoming
external trigger. Set ting is done from HCH1 and HCH0 bit s on ADCR. Pins AN8 to ANB are
also ava i lable for software-triggered conversion.
Wh en con ver si o n ends, HE ND flag in ADCSR is set to 1. If ADI E bit in ADCSR is also set to 1,
an A /D conv ersion end interrup t occurs.
If the conversion time or input channel selection in ADCR needs to be changed during A/D
conversion, to avoid malfunctions, first clear the HST flag to 0 to halt A/D conversion.
If softwa re writes 1 in the SST bi t to start software-triggered conve rsion whi le hardware- or
external-trigge red conversion is in progress, the hardware- or external-trigge red conversion has
prior it y an d the software -t r igg e re d co nve r sion is not exe c ut e d. At this tim e, B USY fla g in
ADCSR i s set to 1. The BUSY fla g is cleared to 0 when the hardware-tri gge red A/D result
register (AHR) i s read.
If conversi on is t riggered by hardware while software -triggered conversion is in progress, the
software-triggered conversion is immediately ca nceled and t he SST flag i s cleared to 0, and SCNL
flag in ADCSR is set to 1 (the SCNL flag is cleared when software writes 1 in the SST bit to start
conversion after the hardware-triggered conversion ends). The analog input channel changes
automatically from the channel that was undergoing software-triggered conversion (selected by
bits SCH3 to SCH0 in ADCR) to the channel selected by bits HCH1 and HCH0 in ADCR for
hardware- or external-triggered conversion. After the hardware- or external-triggered conversion
ends, the channel reverts to the channel selected by the software-triggered conversion channel
select bits in ADCR.
Hardware- or external-trig ger ed conversi on has prior ity over software-t rig ger ed conv ersio n, so the
A/D interrupt-handling routine should check t he SCNL and BUSY fl ags when it proc e sse s the
converted data.
Rev. 1.0, 02/00, page 529 of 1141
24.5 Int erru p t So urces
When A/D conversion e nds, SEND or HEND fla g in ADCSR is set t o 1. T he A/D conversion end
interrupt (ADI) can be ena bled or di sabled by ADIE bit in ADCSR.
Figure 24. 4 shows the bl ock dia gram of A/D conversion end interrupt.
A/D conversion end
interrupt (ADI)
To interrupt controller
A/D control/status register (ADCSR)
SEND HEND ADIE
Fi g ure 24.4 Block Diag r am of A/D Conversion E nd Interr upt
Rev. 1.0, 02/00, page 531 of 1141
Section 25 Address Trap Controller (ATC)
25.1 Overview
The address trap c ontroller (ATC) is capable of generating i nterrupt by setting an address to trap,
when the address se t appears during bus cycle.
25.1.1 Features
Address to trap can be set independently at t hree points.
25.1.2 Block Diagram
Figure 25. 1 shows a bloc k diagram of the addre ss trap controller.
TRCR
[Legend]
TAR0 to 2
Interrupt request
Modules bus
Internal bus
ATCR TAR0 TAR1 TAR2
Trap condition comparator
Bus
interface
: Trap control register
: Trap address register 0 to 2
Figure 25.1 Block Diagram of ATC
Rev. 1.0, 02/00, page 532 of 1141
25.1.3 Regi ster Configur ati on
Table 25. 1 Register List
Name Abbr ev. R/W I nit i al Value Address *
Address t r ap control register ATCR R/W H'F8 H'FFB9
Trap address r egister 0 TAR0 R/ W H'F00000 H'FFB0 to H'FFB2
Trap address r egister 1 TAR1 R/ W H'F00000 H'FFB3 to H'FFB5
Trap address r egister 2 TAR2 R/ W H'F00000 H'FFB6 to H'FFB8
Note: * Lower 16 bits of the address.
25.2 Register Descript i on s
25. 2. 1 Addre ss Trap Co ntro l Regist er (ATCR)
0
0
1
0
R/W
2
0
R/W
3
1
4
1
5
1
6
1
7
—————
————— R/W
TRC2 TRC1 TRC0
1
Bit :
Initial value :
R/W :
Bits 7 to 3Reserved: Th ese bits cannot be mod ified an d are always read as 1.
Bit 2Trap Control 2 (TRC2): Sets ON/OFF operati on of the address trap funct ion 2.
Bit 2
TRC2 Description
0 Address trap function 2 disabled (Initial value)
1 Address trap function 2 enabled
Rev. 1.0, 02/00, page 533 of 1141
Bit 1Trap Control 1 (TRC1): Sets ON/OFF operati on of the address trap funct ion 1.
Bit 1
TRC1 Description
0 Address trap function 1 disabled (Initial value)
1 Address trap function 1 enabled
Bit 0Trap Control 0 (TRC0): Sets ON/OFF operati on of the address trap funct ion 0.
Bit 0
TRC0 Description
0 Address trap function 0 disabled (Initial value)
1 Address trap function 0 enabled
Rev. 1.0, 02/00, page 534 of 1141
25. 2. 2 T r a p Addre ss Regi ster 2 to 0 (TAR2 to TAR0)
0
0
1
0
R/W
2
0
R/W
34567
R/W
A18 A17 A16
00
R/W
0
R/W R/W
A23 A22 A21
00
R/W R/W
A20 A19
0
0
1
0
R/W
2
0
R/W
34567
R/W
A10 A9 A8
00
R/W
0
R/W R/W
A15 A14 A13
00
R/W R/W
A12 A11
0
—
—
1
0
R/W
2
0
R/W
34567
A2 A1
00
R/W
0
R/W R/W
A7 A6 A5
00
R/W R/W
A4 A3
0
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
The TAR is composed of thre e 8-bit readable/writable re gisters (TARnA, B, and C)(n = 2 to 0)
The TAR sets the address to trap. The function of the TAR2 to T AR0 is the same.
The TAR is initialized to H'00 by a reset.
TARA bi t s 7 t o 0: Addresses 23 to 16 (A23 to A16)
TARB bits 7 to 0: Addresses 15 to 8 (A15 to A8)
TARC bits 7 to 0: Addresses 7 to 1 (A7 t o A1)
If the value installed in this register and internal address buses A23 to A1 match as a result of
comparison, a n inte rruption occ urs.
For th e add ress to tr ap, set to the ad dr es s w here the fir s t b y te of an in s tr uctio n ex is ts. In the case
of other addres s es, it may not be considered that the cond ition has been s atis fied.
Bit 0 of this register i s fixed at 0. T he addre ss to t rap becomes an even address.
The range wher e comparison is made is H'000000 t o H'FFFFFE.
Rev. 1.0, 02/00, page 535 of 1141
25.3 P recau t ion s in Usage
Address tra p interrupt arises 2 st ates after prefetching t he trap address. Trap interrupt ma y occur
after the trap instruction has been executed, depending on a combination of instructions
immediately preceding the setting up of the address trap.
If the instruction to trap immediately follows the branch instruction or the conditional branch
instruction, operation m ay differ, depe nding on whether the condition was satisfied or not, or the
address to be stacked ma y be loc ated at the branc h. Figures 25. 2 to 25.22 show specific
operations.
For information as to where the next instruction prefetch occurs during the execution cycle of the
instruction, see appendix A. 5 of this ma nual or section 2.7 Bus State duri ng Execution of
Instruction of the H8S/2600 and H8S/2000 Series Programming Manual. (R:W NEXT is the next
instruction pref et ch.)
25.3.1 Basic Oper ations
After terminating the execution of the instruction being executed in the second state from the trap
address prefe tch, the a ddre ss trap interrupt exc e ption handling is started.
1. Figure 25.2 shows the operation when the inst ruction i mmediately preceding the tra p address
is that of 3 states or more of the execution cycle and the next instruction prefetch occurs in the
state before the last 2 states. The address to be stacked is 0260.
φ
Address bus
Interrupt
request
signal
MOV
execution
MOV
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
Internal
opera-
tion
Data
read Start of exception
handling
Immediately
preceding
Instruction
Address
025E MOV.B @ER3+,R2L
0260 NOP
(ER3 = H'0000)
0262 NOP
0264 NOP
025E 0260 0000 0262
*
→
* Trap setting address
The underlines address is the
one to be actually stacked.
Note: I n the figur e above, the NOP instruction is used as the typical example of instruction with
execution cycle of 1 state. O ther instructions with the execut ion cycle of 1 stat e also apply
(Ex. MOV.B, Rs, Rd).
Figure 25.2 Basic Operations (1)
Rev. 1.0, 02/00, page 536 of 1141
2. Figure 25.3 shows the operation when the inst ruction i mmediately preceding the tra p address
is that of 2 states or more of the execution cycle and the next instruction prefetch occurs in the
second state from the last. The a ddress to be stacked is 0268.
φ
Address bus
Interrupt
request
signal
MOV
execution NOP
execution
Start of exception
handling
Immediately
preceding
instruction
Address
0266 MOV.B
R2L, @0000
0268 NOP
026A NOP
026C NOP
*
0266 026A0268 0000 026C
Data
read
→
MOV
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Figure 25.3 Basic Operations (2)
3. Figure 25.4 shows the operation when the inst ruction i mmediately preceding the tra p address
is that of 1 state or 2 states or more and the prefetch occurs in the last state. The address to be
stacked is 025C.
φ
Address bus
Interrupt
request
signal
NOP
execu-
tion
NOP
execu-
tion
NOP
execu-
tion
Start of
exception
handling
Immediately
preceding
instruction
Address
0256 NOP
0258 NOP
025A NOP
025C NOP
025E NOP
*
0256 025C0258 025A 025E
→
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Figure 25.4 Basic Operations (3)
Rev. 1.0, 02/00, page 537 of 1141
25.3.2 Enabling
The address trap function becomes valid after executing one instruction following the setting of
the enable bit of the a ddress trap control register (TRCR) to 1.
029C BSET #0, @TRCR
*029E MOV.W R0, R1
02A0 MOV.B R1L, R3H
02A2 NOP
02A4 CMP.W R0, R1
02A6 NOP
After executing the MOV instruction,
the address trap interrupt does not
arise, and the next instruction is
executed.
Note: * Trap setting address
Figure 25.5 Enabling
25. 3. 3 B c c Instruc tion
1. When the condition is satisfie d by Bcc i nstruction (8-bit displac ement)
If the trap address is the next instruction to the Bcc instruction and the condition is satisfied by
the Bcc i nstruction and then branc he d, tra nsition is made to the address trap interrupt a fter
executing the instruction at the branch. The address to be stacked is 02A8.
φ
Address bus
Interrupt
request
signal
BEQ
execu-
tion
CMP
execu-
tion
029C 02A8029E 02A6 02AA
029C BEQ NEXT:8
029E NOP
02A0 NOP
02A2 NOP
02A4 NOP
02A6 CMP.W R0, R1
02A8 NOP
(NEXT = H'02A6)
*
Start of
exception
handling
BEQ
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
CMP
instruc-
tion
pre-fetch
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Fig ure 25.6 When the Condi ti on Satisfied by Bcc Instr uction (8-bit Displacement)
Rev. 1.0, 02/00, page 538 of 1141
2. When the condition is not satisfied by Bcc instruction (8-bit displacement)
If the trap address is the next instruction to the Bcc instruction and the condition is not satisfied
by the Bcc i nstruction and thus it fai l s to branch, tra nsition is made to the address trap interrupt
aft er executin g th e trap ad dress instruction and pr ef etchin g the next instr uction. Th e add r es s to
be stacked i s 02A2.
φ
Address bus
Interrupt
request
signal
029E 02A202A0 02A8 02A4
029E BEQ NEXT:8
02A0 NOP
02A2 NOP
02A4 NOP
02A6 NOP
02A8 CMP.W R0, R1
02AA NOP
(NEXT = H'02A8)
*
BEQ
execu-
tion
NOP
execu-
tion
Start of
exception
handling
BEQ
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
CMP
instruc-
tion
pre-fetch
NEXT:
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Fig ure 25.7 When the Condi ti on Not Satisfied by Bcc Instruction (8-bit Displacement)
Rev. 1.0, 02/00, page 539 of 1141
3. When condition is not satisfied by Bcc inst ruction (16-bit di splacement)
If the trap address is the next instruction to the Bcc instruction and the condition is not satisfied
by the Bcc i nstruction and thus it fai l s to branch, tra nsition is made to the address trap interrupt
after executing the trap address instruction (if the trap address instruction is that of 2 states or
more. If the instruction is that of 1 state, after executing two instructions). The address to be
stacked is 02C0.
φ
Address bus
Interrupt
request
signal
Start of
exception handling
02B8 02C002BC 02BE 02C202BA
02B8 BEQ NEXT:16
02BC NOP
02BE NOP
02C0 NOP
02C2 NOP
02C4 NOP
(NEXT = H'02C4)
*
BEQ
execution NOP
execu-
tion
NOP
execu-
tion
Data
fetch Internal
opera-
tion
BEQ
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NEXT:
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Fig ure 25.8 When the Condi ti on Not Satisfied by Bcc Instruction (16-bit Displacement)
Rev. 1.0, 02/00, page 540 of 1141
4. When the condition is not satisfied by Bcc instruct ion (Trap address at branch)
When the trap address is at the branch of the Bcc instruction and the condition is not satisfied
by the Bcc instruction and thus it fails to branch, transition is made into the address trap
interrupt after executing the next instruction (if the next instruction is that of 2 states or more.
If the next i nstruction is that of 1 state, after executing two instructions). The a ddress to be
stacked is 0262.
φ
Address bus
Interrupt
request
signal
Start of
exception
handling
025C 02620266025E 0260 0264
025C BEQ NEXT:8
025E NOP
0260 NOP
0262 NOP
0264 NOP
0266 CMP.W R0, R1
0268 NOP
(NEXT = H'0266)
BEQ
execution NOP
execu-
tion
NOP
execu-
tion
*
BEQ
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
CMP
instruc-
tion
pre-fetch
NEXT:
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Fi g ure 25.9 When the Condi tion Not Satisfie d by Bcc Instruction
(Trap Address at Br anch)
Rev. 1.0, 02/00, page 541 of 1141
25. 3. 4 B SR Inst r uc tio n
1. BSR Instruction (8-bi t displacement)
When the trap address is the next instruction to the BSR instruction and the addressing mode is
an 8-bit displacement, transition is made to the address trap interrupt after prefe tching t he
instruction at the branch. The address to be stacked is 02C2.
φ
Address bus
Interrupt
request
signal
BSR execution
Stack
saving
0294 SP-402C20296 SP-2 02C4
0294 BSR @ER0
0296 NOP
0298 NOP
02C2 MOV.W R4, @OUT
02C4 NOP
: :
(@ER0 = H'02C2)
*
Start of
exception handling
BSR
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
MOV
instruc-
tion
pre-fetch
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Fig ure 25.10 BSR Instruction (8-bit Displace m e nt)
Rev. 1.0, 02/00, page 542 of 1141
25. 3. 5 J SR Inst r uc t ion
1. JSR Instructi on (Registe r indirect)
When the trap address is the next instruction to the JSR instruction and the addressing mode is
a register indirect, transition i s ma de to t he address trap interrupt a fter prefetching the
instruction at the branch. The address to be stacked is 02C8.
φ
Address bus
Interrupt
request
signal
JSRexecution
Stack
saving Start of
exception
handling
029A SP-402C8029C SP-2 02CA
029A JSR @ER0
029C NOP
029E NOP
02C8 MOV.W R4, @OUT
02CE NOP
: :
(@ER0 = H'02C8)
*
JSR
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
MOV
instruc-
tion
pre-fetch
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Fi g ure 25.11 JSR Instr ucti o n (Regist er Indir ec t)
Rev. 1.0, 02/00, page 543 of 1141
2. JSR Instructi on (Memory indirect)
When the trap address is the next instruction to the JSR instruction and the addressing mode is
memory indi rect, tra nsition is made to the address trap interrupt after prefetching the
instruction at the branch. The address to be stacked is 02EA.
φ
Address bus
Interrupt
request
signal
JSR execution
Stack
saving
Start of
exception
handling
0294 SP-2 SP-4 02EA006C0296 006E 02EC
0294 JSR @@H'6C:8
0296 NOP
0298 NOP
02EA NOP
02EC NOP
: :
006C H'02EA
: :
*
Data
fetch
JSR
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Fi g ure 25.12 JSR Instr ucti o n (Memory Indire c t )
Rev. 1.0, 02/00, page 544 of 1141
25. 3. 6 J M P Instructi on
1. JMP Instru ct ion (Re gister indi rect )
Wh en the t rap ad dre ss is the next i n st ruct i o n to the JMP instr uct io n and t he add ressi n g mode i s
a register indirect, transition i s ma de to t he address trap interrupt a fter prefetching the
instruction at the branch. The address to be stacked is 02AA.
φ
Address bus
Interrupt
request
signal
JMP
execution MOV.L
execution
Data
fetch Start of
exception
handling
029A 02A8 02AA02A4029C 02A6 02AC
029A JMP @ER0
029C NOP
029E NOP
02A0 NOP
02A2 NOP
02A4 MOV.L #DATA, ER1
02AA NOP
(@ER0 = H'02A4)
*
JMP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
MOV
instruc-
tion
pre-fetch
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Fi g ure 25.13 JMP Instruc tio n (Register Indire c t )
Rev. 1.0, 02/00, page 545 of 1141
2. JMP Inst ruction (Memory indirect)
Wh en the t rap ad dre ss is the next i n st ruct i o n to the JMP instr uct io n and t he add ressi n g mode i s
memory indi rect, tra nsition is made to the address trap interrupt after prefetching the
instruction at the branch. The address to be stacked is 02E4.
φ
Address bus
Interrupt
request
signal
JMP execution
Start of
exception
handling
0294 006C 02E4006C0296 006E 02E6
0294 JMP @@H'6C:8
0296 NOP
0298 NOP
02E4 NOP
02E6 NOP
: :
006C H'02E4
: :
*
Data
fetch Internal
opera-
tion
JMP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Fi g ure 25.14 JMP Instruc tio n (Memory Indirec t )
25. 3. 7 RT S Inst r uc tio n
When the trap address is the next instruction to the RTS instruction, transition is made to the
address tra p interrupt after reading t he CCR and PC from the stack a nd prefetching the instruct ion
at the return location. The address to be stacked is 0298.
φ
Address bus
Break interrupt
request signal
RTS execution
Start of
exception
handling
02AC SP 0298SP02AE SP+2 029A
Stack
saving
0296 BSR SUB
0298 NOP
029A NOP
02AC RTS
(@ER0 = H'02C8)
02AE NOP
*
: :
Internal
opera-
tion
RTS
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Fi g ure 25.15 RTS Instr ucti o n
Rev. 1.0, 02/00, page 546 of 1141
25.3.8 SLEEP Instruction
1. SLEEP Instruction 1
When the trap address is the SLEEP instruction and the instruction execution cycle
immediately preceding the SLEEP instruction is that of 2 states or more and prefetch does not
occur in the last state, the SLEEP instruction is not executed and transition is made to the
address tra p interrupt without going i nto SL EEP mode . The address to be stacked is 0274.
φ
Address bus
Interrupt
request
signal
Start of
exception
handling
0272 FFF90274 SP-4SP-20276
0272 MOV.B R2L, @FFF8
0274 SLEEP
0276 NOP
0278 NOP
: :
*
Data
write
MOV
execution SLEEP
cancel
MOV
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
SLEEP
instruc-
tion
pre-fetch
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Fi g ure 25 .16 SL E EP Inst r uct i o n (1)
Rev. 1.0, 02/00, page 547 of 1141
2. SLEEP Instruction 2
When the trap address is the SLEEP instruction and the instruction execution cycle
immediately preceding the SLEEP instruction is that of 1 state 2 states or more and prefetch
occurs in the last state, this puts in the SLEEP mode after execution of the SLEEP instruction,
and the SLEEP mode is ca ncelled by the address trap i nterrupt and tra nsition is made to the
exception handling. T he address to be stacked is 0264.
φ
Address bus
Interrupt
request
signal
Start of
exception
handling
0260 0262 SP-2 SP-40264
0260 NOP
0262 SLEEP
0264 NOP
0266 NOP
: :
*
NOP
execution SLEEP
execution SLEEP
mode
NOP
instruc-
tion
pre-fetch
SLEEP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Fi g ure 25 .17 SL E EP Inst r uct i o n (2)
Rev. 1.0, 02/00, page 548 of 1141
3. SLEEP Instruction 3
When the trap address is the next instruction to the SLEEP instruction, this puts in the SLEEP
mode after ex ecutio n of th e S LEEP ins tructio n, and th e S LEEP mode is can celled b y th e
address trap interru pt and transitio n is mad e to the exception handling . The address to be
stacked is 0282.
φ
Address bus
Interrupt
request
signal
Start of
exception
handling
0280 SP-2 SP-40282
027E NOP
0280 SLEEP
0282 NOP
0284 NOP
: :
*
SLEEP
execution SLEEP mode
SLEEP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
Note: * Trap setting address
The underlines address is the one to be actually stacked.
Fi g ure 25 .18 SL E EP Inst r uct i o n (3)
Rev. 1.0, 02/00, page 549 of 1141
4. SLEEP Instruction 4 (Standby or Watc h Mode Setting)
When the trap address is the SLEEP instruction and the instruction immediately preceding the
SLEEP instruction is that of 1 state or 2 states or more and prefetch occurs in the last state, this
puts in the standby (wa t ch) mode after execution of the SLEEP instruction. Afte r that, if the
standby (watch) mode is cancell ed by the NMI interrupt , transit ion is made to NMI interru pt
following t he CCR and PC (at the address of 0266) stack saving and vector reading. However,
if the addre ss trap interrupt arise s before starting execution of the NMI interrupt processing,
transition is made to the address trap e xception handling. The address to be stacked is the
starting address of t he NMI interrupt processing.
φ
Address bus
Interrupt
request
signal
Address trap
interruption
0262 0264 0266 SP-2SPCASP-2
0262 NOP
0264 SLEEP
0266 NOP
*
SLEEP
execution
NMI
interrupt
Standby
mode
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
SLEEP
instruc-
tion
pre-fetch
Note: * Trap setting address
Fi g ure 25.19 SLEEP Instr uction (4) (Standby or Watch Mode Set ting )
Rev. 1.0, 02/00, page 550 of 1141
5. SLEEP Instruction 5 (Standby or Watc h Mode Setting)
When the trap address i s the next instruction to the SLEEP instruction, this puts in t he standby
(watch) mode after execution of the SLEEP instruction. After that, if the standby (watch)
mode is cancelled by the NMI interruption, transition is made to the NMI interrupt following
the CCR and PC (at the address of 0266) stack saving and vector reading. However, if the
address tra p interrupt arises be fore starting e xecution of the NMI interrupt processing,
transition is made to the address trap e xception handling. The address to be stacked is the
starting address of t he NMI interrupt processing.
φ
Address bus
Interrupt
request
signal
Address trap
interrupt
0280 0282 0284 SP-2SPCASP-2
0280 NOP
0282 SLEEP
0284 NOP
*
SLEEP
execution
NMI
interruption
Standby
mode
NOP
instruc-
tion
pre-fetch
SLEEP
instruc-
tion
pre-fetch
Note: * Trap setting address
Fi g ure 25.20 SLEEP Instr uction (5) (Standby or Watch Mode Set ting )
25.3.9 Competing Interrupt
1. General Interrupt (Interrupt othe r than NMI)
When the ATC interrupt request is ma de at the ti ming in (1) (A) against the general interrupt
request, the interruption appears to take place in the ATC at the timing earlier than usual,
because highe r priority is assigned t o the ATC interrupt proce ssing (Simul taneous interrupt
with the general interrupt has no effect on processing). T he addre ss to be stacked is 029E.
For comparison, the case where the trap address is set at 02A0 if no general interrupt request
was made is shown i n (2). The addre ss to be stacked is 02A4.
Rev. 1.0, 02/00, page 551 of 1141
φ
Address bus
General Interrupt
request signal
Interrupt
request signal
MOV execution
Data
write
Data
write
Start of general
interrupt processing
Range of start of ATC
interrupt processing
(1)
029C NOP
0296 MOV.B R2L, @Port
029A NOP
029E NOP
02A0 NOP
02A2 NOP
02A4 NOP
0296 Port 029E SP-2 SP-4
Vector Vector
0298
NOP
execu-
tion
NOP
execu-
tion
MOV execution
NOP
execu-
tion
NOP
execu-
tion
NOP
execu-
tion
NOP
execu-
tion
NOP
execu-
tion
029A 029C 02A0
φ
Address bus
Interrupt
request
signal
Data
read
Data
read
Start of ATC interrupt
processing
Set one of these to the
trap address
(2)
029C NOP
0296 MOV.B R2L, @Port
029A NOP
029E NOP
02A0 NOP Trap address
02A2 NOP
02A4 NOP
0296 Port 029E0298 02A0 02A2 02A4 SP-2029A 029C 02A6
(A)
MOV
instruc-
tion
pre-fetch
MOV
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
Address
to be
stacked
Figure 25.21 Competing Interrupt (General Inter rupt)
Rev. 1.0, 02/00, page 552 of 1141
2. In case of NMI
When the NMI inte rruption re quest is made at the ti ming in (1) (A) a gainst t he ATC interrupt
request, the interrupt a ppears to take place in NMI at the timing earlier than usual, because
higher priority is assigned t o the NMI interrupt processing. The ATC interrupt proc essing
starts after fetching the instruction at the starting address of the NMI interrupt processing. The
address to be stacked is 02E0 for the NMI and 340 for the ATC.
When the ATC interrupt request is ma de at the ti ming in (2) (B) against t he NMI interrupt
request, the ATC int e rrupt processing starts after fetching the instruction at the st a rting a ddress
of the NMI interrupt processing. The a ddress to be stacked i s 02E6 for the NMI and 0340 for
the ATC.
Rev. 1.0, 02/00, page 553 of 1141
φ
Address bus
NMI interrupt
request signal
ATC interrupt
request signal
Start of ATC inter-
rupt processing
(1)
02E0 NOP
02DC NOP
02DE NOP
02E2 NOP
02E4 NOP
02E6 NOP
02E8 NOP
02DC SP-4 0340 SP-6 SP-8
VectorVector VectorVector
02DE
NMI vector
read
02E0 0342SP-202E2
(2) Set one of these to
the trap address
(1) Set to the trap address
*
NMI interrupt
processing Start of ATC interrupt processing
φ
Address bus
NMI interrupt
request signal
ATC interrupt
request signal
Start of ATC
Interrupt processing
(2)
02DC 02E2 02E4 SP-4SP-2 0340
Vector Vector Vector
02DE 02E0 034202E6 02E8
(B)
(A)
NMI interrupt
processing
: :
0340 The starting address of NMI
interrupt
: :
NOP
execu-
tion
NOP
execu-
tion
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
NOP
instruc-
tion
pre-fetch
Figure 25.22 Competing Interrupt (In Case of NMI)
Rev. 1.0, 02/00, page 555 of 1141
Section 26 Servo Circuits
26.1 Overview
26.1.1 Functions
Servo circuits for a video cassette record er are inc luded on-chip.
The functions of the servo circuits ca n be divided into four groups, as listed in table 26.1.
Table 26. 1 Servo Circ uit Functions
Group Function Description
CTL I/O amplifier Gain variable input amplifier
Outp ut a mp lifier w it h r ewrite m od e
CF GDuty compen sation
input Duty accuracy: 50±2%
(Zero cross type comparator)
DFG, DPG
separation/overl ap inpu t Overlap input available: Three-level input method, DFG
nois e mask func t i o n
Reference signal
generators V compensation, field detection, external signal sync, V
sync in REC mode, REF30 sign al output to outside
HSW timin g gener at or Hea d-sw itch in g sign als, FIFO 2 0 sta ges
Compatible with DFG counter soft-reset
Four-head high-speed
switching circuit for special
playback
Chroma-rotary/head-amplifier switching output
12-bit PWM Improved speed of carrier frequency
Freq uency divi sion circuit Wi th CFG mask, no CFG for ph ase or CTL mask
(1) Input and ou t p ut
circuits
Sync detection circuit No ise count, fie ld discrimination, Hsync com pensation,
Hsync detection noise mask
Drum speed error detector Lock detector function, pause at the counter overflow,
R/W error latch register, limiter function
Drum phase error detector Latch signal selectable, R/W error latch register
Caps t an s peed er r or
detector Lock detector function, pause at the counter overflow,
R/W error latch register, limiter function
Caps t an phas e er r or
detector R/W error latch register
(2) Error detectors
X-v alue ad jus tment and
tra cking adju stment circuit (Separate setting available)
(3) Phase and gain
compensation Digital filter computation
circuit Computations performed automatically by hardware
Output gain variable: × 2 to × 64 (exponen ts of 2)
(Partial write in Z-1 (high-order 8 bits) available)
Additional V signal circuit Valid in special playback(4) Other circuits
CT L cir cuit Duty discri minatio n circui t, CTL he ad R/W control,
compatible with wide aspect
Rev. 1.0, 02/00, page 556 of 1141
26.1.2 Block Diagram
Figure 26. 1 shows a bloc k diagram of the servo c ircuits.
4-head
special
playback
controller
- +
SV1(P30)
EXCAP(P81)
( )
SV2(P31)
( )
EXCTL(P82)
)
+
+
+
+
+
- +
- +
-
CTL
Head
CTL Amp
CTL
Head
CFG
CAP
PWM
DRM
PWM
DFG
DPG(P87)
VIDEOFF
AUDIOFF
Vpulse
H.Amp SW(P84)
C.ROTARY(P83)
COMP(P85)
Csync
EXTTRG(P86)
OSCH
REC:ON
ADTRIG
(HSW)
Ep
PWM
Es
Es
Ep
REC
REC
PB.ASM
CTLFB
PB.CTL
PB.
ASM
(NTSC)
DVCTL
Gain control
by register
setting
REF30,REF30X,CREF,
CTLMONI,DVCFG,
DFG,DPG,DFG,etc
Internal signal
monitor
controller
(PAL)REF30X
REC-CTL
DutyI/O
(Duty deter-
minator) (Assemble
recording)
DVCFG
DVCFG2
Gain up.
XE:ON
VD
RP0 to 7/
(P60 to 67,
P74 to 77)
Sync
separator
REC-CTL
generator
VISS
circuit
Noise
Det.
A/D
converter
Timer X1
Timer L
Timer R
AN pins
PWM
X-value
adjustment
Gain up.
RP0 to 7/
(P60 to 67,
P74 to 77)
PPG0 to 7/
(P70 to 77)
PPG0 to 7/
(P70 to 77)
REF30P(PB:30Hz,REC:1/2VD)
CREF
Res
System
clock
Additional
V pulse
generator
Head-switch
timing
generator
Drum system
reference
signal
Capstan
system
reference
signal
Phase
error
detector
Phase
error
detector
Digital
filter
Digital
filter
Digital
filter
Digital
filter
Frequency
divider
Frequency
divider
Speed
error
detector
Speed
error
detector
Figure 26.1 Block Diagr am of Servo Circuits
Rev. 1.0, 02/00, page 557 of 1141
26.2 Servo Port
26.2.1 Overview
This LSI i s equi pped with seve nteen pins dedicated to the servo circuit and twenty-five pins
multiplexed with general-purpose ports. It also has an input amplifier to amplify CTL signals, a
CTL output amplifier, a CTL Schmitt comparator, and a CFG zero cross type comparator. The
CT L inpu t amplifie r all o ws gain adjustment b y softwa re . DFG and DPG signal s, whic h co ntr o l
the drum, can be input as separate signa l s or an overlapped signal.
SV1 and SV2 pins allow internal signals of the se rvo circuit to be output for monitoring. T he
signals to be output can be selected out of eight kinds of signals. See the descript i on of Servo
Monitor Cont rol Register (SVMCR) in section 26.2.5, Register Description.
26.2.2 Block Diagram
1. DFG and DPG Input Circuit
The DFG and DPG input pin s have on-chi p Schmit cir c uit s. Figu re 26.2 sho ws the input
ci rcu it of DFG and DPG.
DPG SW
DFG
DPG
DFG
DPG
DPG SW
Res+LPM
Fi g ure 26.2 Input Circuit of DFG and DPG
Rev. 1.0, 02/00, page 558 of 1141
2. CFG Input Circuit
The CFG input pin ha s an amplifier and a zero cross type c om parator. Figure 26.3 shows the
input circuit of CFG.
+
-
+
-
+
-
CFGCOMP
CFGCOMP
P250
REF
M250 S
R
F/F
O
stp
VREF
VREF
CFG
BIAS
CFG Res+ModuleSTOP
Fi g ure 26.3 CFG Input Circuit
Rev. 1.0, 02/00, page 559 of 1141
3. CTL Input Ci rcuit
The CTL input pin has an amplifier. Figure 26.4 shows t he input circuit of CTL.
-
+
+
-
CTLFB
CTLSMT(i)CTLFBCTLREF CTLBias
CTLGR0CTLGR3 to 1
AMPSHORT
(REC-CTL)
PB-CTL(+)
Note: Be sure to connect a capacitor between CTLAmp (o) and CTLSMT (i)
Note
PB-CTL(-)
AMPON
(PB-CTL)
- +
CTLAmp(o)CTL(+)CTL(
-
)
Fi g ure 26.4 CTL Input Circ ui t
Rev. 1.0, 02/00, page 560 of 1141
26.2.3 P i n Confi guration
Table 26. 2 shows the pi n configuration of the servo circuit. P30, P31, and P81 t o P87 are general-
purpose ports. As for P3, P6, P7, and P8, see section 10, I/ O Port.
Table 26. 2 Pin Configuration
Name Abbrev. I/O Function
Servo Vcc pin SVCC Input Po wer source pin for servo circuit
Servo Vss pin SVSS Input Po wer source pin for servo circuit
Audio head switching pin Audio FF Output Audio head switching signal output
Video head switching pin Video FF Output Video head switching signal output
Capstan mix pin CAPPWM Output 12-bit PWM square wave output
Drum mix pin DRMPWM Output 12-bit PWM square wave output
Additional V pulse pin Vpulse Output Additional V signal output
Color rotary signal output pin P83/C.Rotary I/O,
Output General-purpose port/control signal output
port for processing color signals
Head amplifier switching pin P84/H.Amp
SW I/O,
Output Gen era l- p ur p os e port/pr e- ampl ifier o utp ut
selection signal inp ut
Compare signal input pin P85/COMP I/O, Input G en er a l-pur p os e port/pr e- ampl ifier o utp ut
resul t signal input
CTL (+) I/O pin CTL (+) I/O CTL signal input/output
CTL (−) I/O pin CTL (-) I/O CTL signal input/output
CTL Bias input pin CTLBias Input CTL primary amplifier bias supply
CTL Amp (O) output pin CTLAMP (O) Output CTL amplifier output
CTL SMT (i) input pin CTLSMT (I) Input CTL Schmitt amplifier input
CTL FB input pin CTLFB Input CTL a mplifier high-r a ng e ch ar ac t er is t ic s
control
CTL REF output pin CTLREF Output CTL amplifier reference voltage output
Capsta n FG amplifie r input pin CFG Input CFG signal ampli fier input
Drum FG input pin DFG Input DFG signal input
Drum PG input pin P87/DPG I/O, Input General-purpose port/DPG signal input
External CTL signal input pin P82/EXCTL I/O, Input General-purpose port/external CTL signal
input/
Composite sync signal input pin Csync Input Composite sync signal input
External refe rence signal input
pin P86/EXTTRG I/O, input General-purpose port/external reference
signal in put
External capstan signal input pin P81/EXCAP I/O, input General-purpose port/external capstan
signal in put
Servo monitor signal output pin
1P30/SV1 I/O, output General-purpose port/servo monitor signal
output
Servo monitor signal output pin
2P31/SV2 I/O, output General-purpose port/servo monitor signal
output
PPG output pin P7n/PPGn I/O, output General-purpose port/PPG output
RTP output pin P6n/RPn,
P7n/RPn I/O, output General-purpose port/RTP output
Rev. 1.0, 02/00, page 561 of 1141
26.2.4 Register Configurati on
Table 26. 3 shows the re gister c onfiguration of the servo port section.
Table 26. 3 Register Configurati on
Name Abbrev. R/ W Si z e Initi al Value Address
Servo port mode regist er SPMR R/W Byte H'5F H'D0A0
Servo monitor control regist er SVMCR R/W Byte H'C0 H'D0A3
CTL gain control register CTLGR R/W Byte H'C0 H'D0A4
26.2.5 Register Description
Servo Port Mode Register (SPMR)
0
1
1
1
2
1
3
1
4
1
0
R/W
56
7
0
R/W
CTLSTOP
CFGCOMP
1
Bit :
Initial value :
R/W :
SPMR is an 8-bit read/write register that switches the CFG i nput system.
It is ini tialized to H'5F by a reset or in stand-by mode.
Bit 7CTLSTO P Bit (CTLSTOP) : Controls whether the CTL circuit is ope rated or stopped.
Bit 7
CTLSTOP Description
0 CTL circuit operates (Init ial value)
1 CTL circuit stops oper ation
Bit 6Reserved: Cannot be modified and is always read as 1.
Bit 5CFG Input Sy stem Switching Bit (CFGCOMP) : Selects whether the CFG input signal
system is set to the zero cross type comparator system or digital signal input system.
Bit 5
CFGCOMP Description
0CFG signal input syst em is set t o the zero cross type comparator system.
(Init ial value)
1 CFG signal input system is set to the digital signal input system.
Bits 4 to 0Reserved: Cannot be mod ifi ed and are always re ad as 1.
Rev. 1.0, 02/00, page 562 of 1141
Ser v o Monit or Contro l Regi ster (SVM CR)
0
0
1
0
2
0
3
0
4
0
567 ——
——
SVMCR4 SVMCR3 SVMCR2 SVMCR1 SVMCR0
11 R/WR/WR/W
0
SVMCR5
R/W R/WR/W
Bit :
Initial value :
R/W :
SVMCR is an 8-bit read/write register that selects the monitor signal output from the SV1 and
SV2 pins when the P30/SV1 pin is used as the SV1 monitor out put pin or when the P31/SV2 pin i s
used as the SV2 m onitor output pin. It is initialized to H'C0 by a re set or in stand-by mode.
Bits 7 and 6Reserved: Cannot be modified and are always read as 1.
Bits 5 to 3SV2 Pin Servo Monit or Output Co ntro l(SVM CR5 to SVMCR3) : select the servo
monitor signal output from the SV2 pin.
Bit 5 Bit 4 Bit 3
SVMCR5 SVMCR4 SVMCR3 Description
0 Outputs REF30 signal to SV2 output pin. ( I nit ial value)01 O utputs CAPREF30 signal to SV2 output pin.
0 Outputs CREF signal to SV2 output pin.
0
1
1 Outputs CTLMONI signal to SV2 output pin.
0 Outputs DVCFG signal to SV2 output pin.0
1 Outputs CFG signal t o SV2 output pin.
0 Outputs DFG signal t o SV2 output pin.
1
1
1 Outputs DPG signal to SV2 out put pin.
Rev. 1.0, 02/00, page 563 of 1141
Bits 2 to 0SV1 Pin Servo Monitor O utput Control (SVMCR2 to SVMCR0): Select the
servo monit or signal output from the SV1 pin.
Bit 2 Bit 1 Bit 0
SVMCR2 SVMCR1 SVMCR0 Description
0 Outputs REF30 signal to SV1 output pin. ( I nit ial value)01 O utputs CAPREF30 signal to SV1 output pin.
0 Outputs CREF signal to SV1 output pin.
0
1
1 Outputs CTLMONI signal to SV1 output pin.
0 Outputs DVCFG signal to SV1 output pin.0
1 Outputs CFG signal t o SV1 output pin.
0 Outputs DFG signal t o SV1 output pin.
1
1
1 Outputs DPG signal to SV1 out put pin.
CTL Gain Control Register (CTLGR)
0
0
1
0
2
0
3
0
4
0
567 ——
——
CTLFB CTLGR3 CTLGR2 CTLGR1 CTLGR0
1
1R/WR/WR/W
0
CTLE/A
R/W R/WR/W
Bit :
Initial value :
R/W :
CTLGR is an 8-bit read/write registe r that turns on or off the CTLFB switch in the CT L amplifier
circuit and specifying the CTL amplifier gain. It is initialized to H'C0 by a reset or in stand-by
mode.
Bits 7 and 6Reserved: Cannot be modified and are always read as 1.
Bit 5CTL Selection Bit (CTLE/
$
$
): Cont rol s whether the amplifier output or EXCTL is used
as the CTLP signal supplied to the CTL circuit.
Bit 5
CTLE/
$
$
Description
0 AMP output (Init ial value)
1 EXCTL
Rev. 1.0, 02/00, page 564 of 1141
Bit 4SW Bit of the Feedback Sec tion o f CTL Amplifie r (CT LFB): Turns on or off the swi tch
of the feedback section to adjust the gain. See figure 26.4.
Bit 4
CTLFB Description
0 Turns off CTLFB SW (Init ial value)
1 Turns on CTLFB SW
Bits 3 to 0CTL Ampl ifier Gain Setting Bits (CTLGR3 to CTLG R0): Set the output gain of
the C TL amp lifier .
Bit 3 Bit 2 Bit 1 Bit 0
CTLGR3 CTLGR2 CTLGR1 CTLGR0 CT L Ou tp ut Gain
0 35.0 dB (Initial value)01 37.5 dB
0 40.0 dB
0
1
1 42.5 dB
0 45.0 dB0
1 47.5 dB
0 50.0 dB
0
1
1
1 52.5 dB
0 55.0 dB0
1 57.5 dB
0 60.0 dB
0
11 62.5 dB
0 65.0 dB*01 67.5 dB*
0 70.0 dB*
1
1
1
1 72.5 dB*
Note: * With a setting of 65.0 dB or more, t he CTLAMP is in a very sensitive status. When
configuring the set board, take a countermeasure against noise around the cont r ol head
signal input port. Also, consider well t he setting of the filter between the CTLAMP and
the CTLSMT.
Rev. 1.0, 02/00, page 565 of 1141
26.2.6 DFG/DPG Input Signals
DFG an d DPG signa ls can be input either as sepa ra te signa l s or as an ove rlappe d sig nal. When th e
la tt er is select ed ( PMR87 = 1), take care to contr o l the in put level s o f DFG and DPG. Figure 26.5
shows DFG/ DPG i nput si g nal s.
DPG DPG Schmitt level
3.45/3.55
V
IL
/V
IH
DFG Schmitt level
1.85/1.95
V
IL
/V
IH
DFG
(1) DPG/DFG separate input (PMR87=0)
DPG Schmitt level
DFG/DPG
(2) DPG/DFG overlapped input (PMR87=1)
DFG Schmitt level
Fi g ure 26.5 DFG/DPG Input Si g nals
Rev. 1.0, 02/00, page 566 of 1141
26.3 Ref erence S i gnal Gen erat ors
26.3.1 Overview
The refere nce signa l generators consist of a REF30 signal gene rator a nd a CREF signal gene rator
and create the reference signals (REF30 and CREF signals) used in phase comparison, etc. The
REF30 signal is used to control the phase of the drum and capstan. The CREF signal is used if
REF30 signal cannot be used as the reference signal to control the phase of the capstan in REC
mode. Each signa l generator consists of a 16-bi t counter which uses the servo clock φ s/2 (or φ
s/4) as its clock source, a refe rence period register, a nd a comparator.
The value set in the reference peri od register should be 1/2 of the desire d refere nce signal peri od.
26.3.2 Block Diagram
Figure 26. 6 shows the bl ock dia gram of RE F30 signal gene rator. Figure 26.7 shows that of CRE F
signal ge nerator.
Rev. 1.0, 02/00, page 567 of 1141
φs = fosc/2
φs/2
φs/4
Dummy read
External
frequency
signal
(EXTTRG)
Field
detection
signal
W W R/W W W
WW
PB→REC
PB ↑,↓
ASM
REC/PB V noise detection signal
REF30
REF30P
Video FF
VD
Match
Mask Clear
WR/W W
Internal bus
R/W
Internal bus
Toggle
RCS
REF30 counter register (16 bits)
OD/EV VST
FDS VEG
Edge
detec-
tion
↑ Edge
detec-
tion
VNA CVSREX TBC
Reference period buffer 1 (16 bits)
Reference period register 1 (16 bits)
Comparator (16 bits)
Counter (16 bits)
Figure 26.6 REF 30 Signal Generator
Rev. 1.0, 02/00, page 568 of 1141
φ
s/2
φ
s/4
WW
CREF
DVCFG2
PB(ASM)
↓
REC
Match
Clear
Counter clear
Toggle
Edge
detection
CRD
W
RCS
Reference period register 2 (16 bits)
Reference period buffer 2 (16 bits)
Comparator (16 bits)
Counter (16 bits)
Internal bus
S
R
Q
Dummy read
φ
s = fosc/2
↑
Figure 26.7 Block Diagr am of CREF Signal Gener ator
26.3.3 Register Configurati on
Table 26. 4 shows the re gister c onfiguration of the refe rence signal genera tors.
Table 26. 4 Register Configurati on
Name Abbrev. R/W Si z e Initi al Value Addr ess
Reference period mode
register RFM W Byte H'00 H'D096
Refer ence period regist er 1 RFD W Word H'FFFF H'D090
Refer ence period register 2 CRF W Word H'FFFF H'D092
REF30 count er register RFC R/ W W or d H'0000 H'D094
Reference period mode
register 2 RFM2 R/W Byte H'FE H'D097
Rev. 1.0, 02/00, page 569 of 1141
26.3.4 Register Description
Ref erence Perio d Mo d e Register (RFM)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7REX CRD OD/EV VST VEG
0
W
RCS
WWW
VNA CVS
Bit :
Initial value :
R/W :
RFM is an 8-bit write-only register which determines the operational state of the reference signal
generators. If a read is attempted, an undetermined value is read out.
It is initia lized to H'00 by a reset and in stand-by and mod ul e stop mod es.
RFM is acce ssible in byte units only. If accessed by a word, correct opera tion is not guaranteed.
Bit 7Clock So urce Sel ec tion Bit (RCS): Selects the c l ock source supplied to the counte r.
(φs = fosc/2)
Bit 7
RCS Description
0φs/2 (Initial value)
1φs/4
Bit 6Mode Sele c tio n Bit (VNA): Selects the mode for controlling transition t o fre e -run
operation when the RE F30 signal is generated synchronously with the VD signal in REC mode :
automatic mode which controls the transition by the V noise detection signal detected by the sync
signal de tection circuit, or ma nual mode which cont rol s the transition by software.
Bit 6
VNA Description
0 Manual mode (Init ial value)
1 Automatic mode
Rev. 1.0, 02/00, page 570 of 1141
Bit 5Manual Sele c ti on Bit (CVS): Selects whe t her the REF30 signal is generated sync hrously
with VD or it is operated i n free-run state in t he manual mode (VNA = 0). (T his selection is
ignored in P B mode except in TBC mode.)
Bit 5
CVS Description
0 Synchronous with VD (Init ial value)
1 Free-run oper ation
Bit 4External Signals Sync Selection Bit (REX): Selects whether the REF30 signal is
generated synchronously with VD, in free-run st ate or sync hronously with the external signa l.
(Valid in both PB and REC modes.)
Bit 4
REX Description
0 VD signal or free-run (Initial value)
1 Synchronous with external signal
Bit 3DVCFG2 Sy nc Selec tion Bit (CRD) : Selects whether the reset timing in the CREF signal
generation is immediately aft er swit c hing the mode or it is synchronous with the DVCFG2 signal
immediately aft er th e mode swi tching .
Bit 3
CRD Description
0 On switching the mode (Init ial value)
1 Synchronous with DVCFG2 signal
Bit 2ODD/EVEN Edge Switching Se lection Bit (OD/ EV): Selects whether the REF30P signal
is generated by the rising edge (even) or falling edge (odd) of the field signal in REC m ode.
Bit 2
OD/EV Description
0 Generated at t he rising edge of the field signal (I nit ial value)
1 Generated at t he falling edge of the field signal
Rev. 1.0, 02/00, page 571 of 1141
Bit 1Video F F Counter Se t (VST): Selects whether the REF30 counter register value is set on
or off by the Video FF signal when the drum phase is in FIX on in the PB mode.
Bit 1
VST Description
0 Counter set off by Video FF signal (Initial value)
1 Counter set on by Video FF signal
Bit 0Video F F Edge Selection Bit (VEG): Selects the edge at which REF30 counter is set
(VST = 1) by the Video FF signal.
Bit 0
VEG Description
0 Set at the rising edge of Video FF signal (I nit ial value)
1 Set at the falling edge of Video FF signal
Reference Period Register 1 (RF D)
15
1
REF15
W
14
1
REF14
W
13
1
REF13
W
12
1
REF12
W
11
1
REF11
W
10
1
REF10
W
9
1
REF9
W
8
1
REF8
W
7
1
REF7
W
6
1
REF6
W
5
1
REF5
W
4
1
REF4
W
3
1
REF3
W
2
1
REF2
W
1
1
REF1
W
0
1
REF0
W
Bit :
Initial value :
R/W :
The refere nce period regi ster 1 (RFD) i s a buffer register whic h generates the reference signal
(REF30) for playback, VD compe nsation for recording, and the refere nce signa ls for free-running.
It is an 16-bit write-only regi ster accessible in word unit s only. If a read is attempted, an
undetermined val ue is rea d out.
The value set in RFD shoul d be 1/2 of the desired re fe rence signal period. Care is requi red when
VD is unstable, such as when the field is weak (synchronization with VD cannot be acquired if a
value less than 1/2 i s set in REC). Whe n data is written in RFD, it i s stored i n the buffer once , and
then fetched into RFD by a match signal of the comparator. (The data which generates the
reference signal is updated by the match signal.) A forcible write, such as initial setting, etc.,
should be done by a dummy read of RFD.
If a byte-write in RFD is attempted, correct operation is not guaranteed. RFD is initialized to
H'FFFF by a reset, and i n stand-by a nd module stop modes.
Use b it 7 (ASM) and bit 6 (REC/ PB ) in the CTL mode re gist er (CTLM) in the CTL circu it to
switch between record and playback modes. Use bit 4 (CR/RF bit) in the capstan phase error
detection cont rol register (CPGCR) to swi tch between RE F30 and CREF for capstan phase
control.
Rev. 1.0, 02/00, page 572 of 1141
Reference Period Register 2 (CRF)
15
1
CRF15
W
14
1
CRF14
W
13
1
CRF13
W
12
1
CRF12
W
11
1
CRF11
W
10
1
CRF10
W
9
1
CRF9
W
8
1
CRF8
W
7
1
CRF7
W
6
1
CRF6
W
5
1
CRF5
W
4
1
CRF4
W
3
1
CRF3
W
2
1
CRF2
W
1
1
CRF1
W
0
1
CRF0
W
Bit :
Initial value :
R/W :
The refere nce period regi ster 2 (CRF) is an 16-bit write-only buffer re gister which generates the
reference signals to c ontrol t he capstan phase (CREF). CRF is accessible i n word units only. If a
read is attempted, an undetermined value is read out. The value set in CRF should be 1/2 of the
desired reference signal pe ri od.
When data is written in CRF, it is stored in the buffer once, and then fetched into CRF by a match
signal of the comparator. (The data which generates the reference signal is updated by the match
signal.) A forcible write, such as initial set t ing, etc., should be done by a dummy read of CRF.
If a byt e-write i n CRF i s attempted, correct operation i s not gua ranteed. CRF i s initialized to
H'FFFF by a reset and in stand-by and module stop modes.
Use bit 4 (CR/RF bit) i n the capstan phase error detection control register (CPGCR) to switch
between REF30 and CREF for capst an phase control. See section 26.9, Capstan Phase Error
Detector.
REF3 0 Counter Regi ster (RFC)
15
0
RFC15
14
0
RFC14
13
0
RFC13
12
0
RFC12
11
0
RFC11
10
0
RFC10
9
0
RFC9
8
0
RFC8
7
0
RFC7
6
0
RFC6
5
0
RFC5
4
0
RFC4
3
0
RFC3
2
0
RFC2
1
0
RFC1
0
0
RFC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit :
Initial value :
R/W :
The REF30 counter register (RFC) is a register which determines the initial value of the free-run
counter when it generates REF30 signals in pl ayback. When dat a is written in RFC, its va lue is
written in the counter by a match signal of the comparator. If the bit 1 (VST) of RFM is set to 1,
the counter is set by the Video FF signal when the drum phase is in FIX ON. The counter setting
by the Video FF signal should be done by setting bit 1 (VST) and bit 0 (VEG) of the RFM. Do
not set t he RFC to a value greater than 1/ 2 of the re ference period regi ster 1 (RFD) value.
RFC is a read/write register. If a read is attempted, the value of the counter is read out. If a byte-
access is attempted, correct ope ration is not guara nteed. RFC is ini tialized to H'0000 by a reset
and in sta nd-by and module stop modes.
Rev. 1.0, 02/00, page 573 of 1141
Referenc e Period Mo d e Registe r 2 (RFM2)
0
0
1
1
2
1
3
1
4
1
567 TBC
R/W
FDS
111 R/W
Bit :
Initial value :
R/W :
REM2 is an 8-bit read/write re gister whic h determines t he operational state of the re ference signal
generators.
It is ini tialized to H'FE by a reset a nd in stand-by and module stop m odes. RFM2 i s a byte access-
only register; if accessed by a word, correct operation is not guaranteed.
Bit 7TBC Selection Bit (TBC): Selects whether the reference signal in PB mode is generated
by the VD signal or by the free-run counter.
Bit 7
TBC Description
0 Generated by the VD signal
1 Generated by the free-run counter (I nit ial value)
Bits 6 to 1Reserved: Cannot be modifi ed and are always re ad as 1.
Bit 0Field Sel ec t ion Bit (FDS) : Dete rmi ne s whet her se le c ti o n betwee n ODD or EVE N is made
for the field signal whe n PB mode was switched over t o RE C mode, or these signals are
synchronized with VD signals wit hin a pha se e rror of 90° immediately after the switching over.
Bit 0
FDS Description
0 Gene rated by the VD signal of ODD or EVEN selected (Initial value)
1 Generated by the VD signal within mode transition phase error of 90°
Rev. 1.0, 02/00, page 574 of 1141
26.3.5 Operation
• Operation of REF30 Signal Generator
The REF30 si gnal generator generates the reference signals requi red to cont rol the phase of
the drum and capstan.
To gene rate the RE F30 signa l, set the 1/ 2 the re ference peri od to the reference pe ri od
register 1 (RFD) corresponding to the 50 percent duty cycle. In playba c k m ode, the REF30
signal is generated by free-runni ng the RE F30 signa l generator. The generator ha s the
external si gnal synchronization function, and i f the bit 4 (RE X) of the reference peri od
mode register (RFM) is set to 1, it generates the REF30 signal from the external signal
(EXTTGR).
In record mode, the reference signal is generated from the VD signal generated in the sync
detector. Any VD drop-out ca used by we a k field intensity, etc., is compensated by a value
set in RFD. To cope with the VD noises, the generator automatically masks the VD for a
period a bout 75% of the RFD setting afte r REF30 signal was c hanged due to VD. In
record mode, the generation of the refere nce signal either by VD or free-run ope ration c a n
be controlled automatically using the V noise detection signal detected in the sync signal
de tect ion circu i t or man uall y by so ftwa re . Select which is u sed by setti n g bit 6 (VNA) or 5
(CVS) o f RFM.
The phase of the toggle output of the REF30 signal is cleared to L level when the mode
shif t s fro m PB to REC (ASM). Also the frame servo function can be set, allowin g for
control of the phase of REF30 signals with the field signal detected in the sync signal
detection ci rcuit. Use bit 2 (OD/E V) of RFM for such c ontrol.
See the description of CTL mode register (CTLM) in section 26.13.5, Register Description,
as f or swi tc hing ove r bet ween PB, ASM and REC.
• Operation of the Mask Circuit
The REF30 si gnal generator has a t oggle mask circuit and a c ounter m ask (counter set
signal mask) circuit built-in. Each mask circuit masks irregular VD signals which may
occur when the VD signal is unstable because of weak field intensity, etc., in record mode.
The toggle mask and counter mask circuits mask the VD automatically for about 75% of
double t he period set i n the referenc e period register 1 (RFD) after VD signal was det ected
(see figure 26. 9). If a VD signal dropped out and V was com pensa t ed, the toggl e mask
circuit begins maski ng, but the count er mask circuit does not begin masking for abou t 25%
of the period. If VD signal was detected duri ng such a peri od, the circuit doe s ma sking for
about 75% of the period after the VD detection. If not detected, it does masking for about
75% of the period after V was c ompensated (see figures 26.10 and 26. 11).
Rev. 1.0, 02/00, page 575 of 1141
• Timing of the REF30 Signal Generation
Figures 26.8 to 26.12 show the timing of the generation of REF30 and RE F30P signals.
Counter set Counter set Counter set
Value set in reference
period register 1 (RFD)
Counter
Value set in REF30
counter register (RFC)
REF30
REF30P
Figure 26.8 REF30 Signals in Playback Mode
Rev. 1.0, 02/00, page 576 of 1141
Sampling
Sampling
Sampling
Value set in reference
period register 1 (RFD)
Selected VD
(OD/EV=0)
Counter mask
(clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD
Toggle mask
Field signal
REF30P
HSW
Drum phase counter
T
About 75%
Masking
period
Masking
period
Figure 26.9 Generation of Refe rence Signal in Rec ord Mode (Normal Operation)
Rev. 1.0, 02/00, page 577 of 1141
Sampling
Cleared Cleared Cleared
Drop-out of V
Value set in reference
period register 1 (RFD)
Selected VD
(OD/EV=0)
Counter mask
(clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD
Toggle mask
Field signal
REF30P
HSW
Drum phase counter
Sampling
TSampling
About 75% About 75% About 75%
About 75%
About
25%
Masking
period
Masking
period
Figure 26.10 Generation of the Reference Signal when in REC (V Dropped Out)
Rev. 1.0, 02/00, page 578 of 1141
Sampling
Cleared Cleared Cleared
Dislocation of V
Value set in reference
period register 1 (RFD)
Selected VD
(OD/EV=0)
Counter mask
(clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD
Toggle mask
Field signal
REF30P
HSW
Drum phase counter
Sampling
TSampling
About 75%
About 75% About 75%
About 75%
Masking
period
Masking
period
Figure 26.11 Generation of the Reference Signal when in REC (V Disloc ated)
Rev. 1.0, 02/00, page 579 of 1141
Cleared Cleared
Reset
Value set in reference
period register 1 (RFD)
Counter
Value set in REF30
counter register (RFC)
External sync
signal
REF30
REF30P
Figure 26.12 Generation of REF30 Signal by the External Sync Signal
• CREF Si gnal Generator
The CREF signal generator generates the CREF signal which is the reference signal to
control the phase of ca pstan.
To gene rate the CRE F signa l, set the 1/ 2 the re ference period to t he reference period
register 2 (CRF). If the set val ue matche s the counter value, a toggl e waveform is
generated corresponding to the 50 perc ent duty cycle, and a one-shot pulse is output at each
rising edge of the waveform. The counter of CREF signal generator i s initialized to H'0000
an d the p hase of the tog gle i s cleared to L le vel when the mod e shi ft s f rom PB (ASM) to
REC. The timing of clearing is selectable between immediately after the transition from
PB (ASM) to RE C and t he timing of DVCFG2 after the t r a nsition. Use bit 3 (CRD) of the
reference period mode registe r (RFM) for thi s selection.
In the capstan phase error det ection circuit, either REF30 signal or CREF signa l can be
selected for the re fe rence signal. Use ei ther of them according to the use of the system.
Use the CREF signal to control the phase of the capstan at a period whic h is di fferent from
the period used to control the phase of the drum. For t he switchi ng betwee n REF30 a nd
CREF in the capstan phase control, see the description of capstan phase error detection
control regi ster (CPGCR) i n section 26.9.4, Register Descri ption.
Rev. 1.0, 02/00, page 580 of 1141
• Timing Chart of the CREF Signal Generation
Figures 26.13 to 26. 15 show the genera tion of CRE F signal.
Cleared Cleared Cleared
Value set in reference
period register 2 (CRF)
Counter
Toggle signal
CREF
Figure 26.13 Generation of CREF Signal
Rev. 1.0, 02/00, page 581 of 1141
Cleared Cleared Cleared
Value set in reference
period register 2 (CRF)
Counter
Period set in CRF
RECPB(ASM)
Toggle signal
REC/PB
CREF
Fi g ure 26.14 CREF Signal whe n PB is Switche d to REC (when CRD Bit = 0)
Rev. 1.0, 02/00, page 582 of 1141
Cleared Cleared Cleared
Value set in reference
period register 2 (CRF)
Counter
Period set in CRF
Toggle signal
REC/PB
CREF
DVCFG2
RECPB(ASM)
Fi g ure 26.15 CREF Signal whe n PB is Switche d to REC (when CRD Bit = 1)
Rev. 1.0, 02/00, page 583 of 1141
Figures 26.16 and 26. 17 show REF30 (REF30P) when PB is switched to REC.
Cleared
Cleared
Cleared
Cleared Cleared
Value set in reference
period register 1 (RFD)
Selected VD*
(OD/EV=0)
Note: In the field discrimination mode
Counter mask
(Clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD (except in PB)
REC(ASM)PB
Toggle mask
Field signal
REC/PB
REF30P
About 75%
Masking
period
Masking
period
Figure 26.16 Generation of the Reference Signal when PB i s Switched to REC (1)
Rev. 1.0, 02/00, page 584 of 1141
Value set in reference
period register 1 (RFD)
Selected VD
(OD/EV=0)
Counter mask
(Clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD (except in PB)
REC(ASM)PB
Toggle mask
Field signal
REC/PB
REF30P
About
50%
Cleared
Cleared
Cleared Cleared
Masking
period
Masking
period
Figure 26.17 Generation of the Reference Signal when PB i s Switched to REC (2)
Rev. 1.0, 02/00, page 585 of 1141
Figures 26.18 to 26. 21 show REF30 (REF30P) when PB is switched to REC (where FDS bit = 1).
Cleared Cleared Cleared
Value set in reference
period register 1 (RFD)
FDS bit = 1
Counter mask
(Clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD (except in PB)
REC(ASM)PB
Toggle mask
REC/PB
REF30P
Masking
period
Masking
period
Figure 26.18 Generation of the Reference Signal when PB i s Switched to REC
where RFD Bit is 1 (1)
Rev. 1.0, 02/00, page 586 of 1141
Value set in reference
period register 1 (RFD)
FDS bit = 1
Counter mask
(Clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD (except in PB)
REC(ASM)PB
Toggle mask
REC/PB
REF30P
Masking
period
Masking
period
25% 25% 25%
Figure 26.19 Generation of the Reference Signal when PB i s Switched to REC
wher e RF D Bit is 1 (when VD Signal is Not Detected) (2)
Rev. 1.0, 02/00, page 587 of 1141
Cleared Cleared
Value set in reference
period register 1 (RFD)
FDS bit = 1
Counter mask
(Clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD (except in PB)
REC(ASM)PB
Toggle mask
REC/PB
REF30P
Masking
period
Masking
period
25% max.
Figure 26.20 Generation of the Reference Signal when PB i s Switched to REC
where RFD Bit is 1 (3)
Rev. 1.0, 02/00, page 588 of 1141
Cleared Cleared
Value set in reference
period register 1 (RFD)
FDS bit = 1
Counter mask
(Clear signal mask)
Counter
Value set in REF30
counter register (RFC)
REF30
VD (except in PB)
REC(ASM)PB
Toggle mask
REC/PB
REF30P
Masking
period
Masking
period
25% max.
Figure 26.21 Generation of the Reference Signal when PB i s Switched to REC
where RFD Bit is 1 (4)
Rev. 1.0, 02/00, page 589 of 1141
26.4 HSW (Head- switch) Timing Generator
26.4.1 Overview
The HSW timing gene rator consists of a 5-bit DFG counte r, a 16-bi t timer c ounter, a matc hing
circuit, and two 31-bit 10-stage FIFOs.
Th e 5- bit c oun te r cou nts th e DFG puls e s foll o wi ng a DPG pul se. Each of them d et e rm ine s the
timing to reset the 16-bit time r counter for each field. The 16-bit t imer counter is a timer clocked
by a φ s/4 clock source, and can be use d as a progra mma ble pa t tern generator (PPG) as well as a
free-running counter (FRC). If used as a free-running counte r, it is cle a red by overflow of the 19-
bit FRC. Accordingly, two FRCs operate synchronously. The matching c ircuit com pares the
timing data in the most significant 16 bits of FIFO with t he 16-bit timer counter, and controls t he
output of the pattern dat a set in the least significant 15 bits of FIFO.
26.4.2 Block Diagram
Figure 26. 22 shows a block diagram of the HSW timing generator.
Rev. 1.0, 02/00, page 590 of 1141
RWW
R/WR/W
WR/WR/W
STRIG
IRRHSW2
ISEL2
AudioFF
VideoFF
HSW
NHSW
Mlevel
Vpulse
ADTRG
IRRHSW1
RVD PB
WR/W R/W
Cleared
Cleared
CLK
WR
↑, ↓
NCDFG
FRCOVF
DPG ↑
CKSL
VFF/NFF
Internal bus
W
FPDRA FPDRB
FTPRA FTPRB
W
ISEL1
OFG
FIFO output pattern
register 1 FIFO output pattern
register 2
SOFGLOP
R/WR/WRRWW
CLRA,BOVWA,BEMPA,BFLA,B
R/W R/W
HSM2HSM1
HSLP
EDG
HSW loop stage
number setting
register
Internal bus
FGR20FF
FRTCCLR
Edge
detector
Control
circuit
FIFO 1
(31 bits × 10 stages)
15 bits
P77 to 70
(PPG output)
FIFO timing pattern
register 1 FIFO timing pattern
register 2
16 bits
FIFO2
(31 bits × 10 stages)
15 bits16 bits
FIFO output selector & output buffer
15 bits16 bits
DFCRBDFCRA
DFCRA HSM2 HSM2
Capture HSM2DFCRA DFCRA
DFG reference
register 1
Comparator
(5 bits) Comparator
(5 bits)
DFG reference
register 2
DFCTR
5-bit counter
Compare circuit (16 bits)
FTCTR (16 bits)
16-bit timer counter
φ s/4φ s/8
Figure 26.22 Block Diagram of the HSW Timing Ge nerator
Rev. 1.0, 02/00, page 591 of 1141
26.4.3 HSW Timing Generator Configuration
The HSW timing generator is composed of the elements shown in table 26.5.
Table 26. 5 Configuration of the HSW Timing Generator
Element Function
HSW mode register 1 (HSM1) Confirmation/determination of this circuits' operating
status
HSW mode registe r 2 (HSM2) Confirmat ion/ determination of this circuits' operating
status
HSW loop stage num ber setting regist er
(HSLP) Set t ing of number of loop stages in loop mode
FIFO output pattern register 1 ( FPDRA) O utput pattern register of FIFO1
FIFO output pattern register 2 ( FPDRB) O utput pattern register of FIFO2
FIFO timing patt ern register 1 (FTPRA) O utput timing register of FIFO1
FIFO timing patt ern register 2 (FTPRB) O utput timing register of FIFO2
DFG reference regist er 1 (DFCRA) Setting of reference DFG edge for FIFO1
DFG reference regist er 2 (DFCRB) Setting of reference DFG edge for FIFO2
FIFO timer capt ur e register (FTCTR) Capture r egister of timer counter
DFG reference count register (DFCTR) DFG edge count
FIFO control cir c uit FI FO status control
DFG count com pare circuit (×2) Detection of match bet ween DFCR and DFG counters
16-bit timer counter 16-bit free-run timer counter
31-bit x 20 stage FI FO First In Firs t Out dat a buffer
31-bit FIFO data buffer Data storing buffer for the first stage of FIFO
16-bit com pare circuit Detection of match between timer counter and FIFO
data buffer
FPDRA and FPDRB are intermediate buffe rs; an FTPRA and FTPRB write results in
simultaneous writing of all 31 bits to the FIFO. The FIFO has two 31-bit x 10-stage data buffers;
its operating st atus is contro lled by HSM1 and HSM2. Data is stored in the 31-bit data buffer.
The value s of FTPRA/FTPRB and the timer counter are compared, and if the y match, t he 15-bit
pattern dat a is output to e ach function. AudioFF, VideoFF, and PPG (P70 to P77) are outputs
from the corresponding pins, ADTRG is the A/D convert e r hardwa re start signal, Vpulse and
Mlevel signals are the signals for generating the additional V pulses, and HSW and NHSW signals
are the same as Vide oFF signals used for the pha se control of the drum. The 16-bit timer counter
is initialized by the overflow of the 19-bit fre e-run counter in the free-run mode (FRT bit of HSM2
= 1), or by a si gnal indicating a match betwe en DFCRA/DFCRB a nd the 5-bit DFG counter in
DFG refe rence mode.
Rev. 1.0, 02/00, page 592 of 1141
26.4.4 Regi ster Configur ati on
Table 26. 6 shows the re gister c onfiguration of the HSW timing ge nerator.
Table 26. 6 Register Configurati on
Name Abbr ev. R/W Size I nit i al Value Address
HSW mode register 1 HSM1 R/W Byte H'30 H'D060
HSW mode register 2 HSM2 R/W Byte H'00 H'D061
HSW loop stage num ber setting
register HSLP R/W Byte Undetermined H'D062
FIFO output pattern register 1 FPDRA W Word Undetermined H'D064
FIFO timing patt ern register 1* FTPRA W Word Undetermined H'D066
FIFO output pattern register 2 FPDRB W Word Undetermined H'D068
FIFO timing pat tern register 2 FTPRB W Wor d H'FFFF H'D06A
DFG reference register 1* DFCRA W Byt e Undetermined H'D06C
DFG reference register 2 DFCRB W Byte Undet ermined H'D06D
FIFO timer capture register* FTCTR R Word H'0000 H'D066
DFG reference count register* DFCTR R Byt e H'E0 H'D06C
Note: * FTPRA and FTCTR, as well as DFCRA and DFCTR, are allocated to the same
addresses.
26.4.5 Register Description
HSW Mode Register 1 (H SM1)
0
0
1
0
R/W
2
0
R/(W)*
3
0
4
1
R
1
R
56
0
7EMPA OVWB OVWA CLRB CLRA
0
R
FLB
R/WR/(W)*R
FLA EMPB
Bit :
Initial value :
R/W :
Note: * Only 0 can be written
HSM1 is an 8-bit register which confirms and determines t he operational st ate of the HSW t imi ng
generator.
Bits 7 to 4 are read-only bits, and write is disabled. All the other bits accept both read and write.
It is initialized to H'30 by a reset or in stand-by mode.
Rev. 1.0, 02/00, page 593 of 1141
Bit 7FIFO2 Full Flag (FLB): When the FLB bit is 1, it indicates that the FIFO2 is full of the
timing pattern data and the output pattern data. If a write is attempted in this state, the write
operation be comes invalid, an interrupt is genera ted, the OVWB flag (bit 3) is set to 1, and the
write data is lost. Wait until space becomes available in the FIFO2, then write again.
Bit 7
FLB Description
0 FIFO2 is not full, and can accept data input. ( I nitial value)
1 FIFO2 is full of data.
Bit 6FIFO1 Full Flag (FLA): When the FLA bit is 1, it indicates that the FIFO1 is full of the
timing pattern data and the output pattern data. If a write is attempted in this state, the write
operation be comes invalid, an interrupt is genera ted, the OVWA fla g (bit 2) i s set to 1, and the
write data is lost. Wait until space becomes available in the FIFO1, then write again.
Bit 6
FLA Description
0 FIFO1 is not full, and can accept data input. ( I nitial value)
1 FIFO1 is full of data.
Bit 5FIFO2 Empty Flag (EMPB): Indicates that FIFO2 has no data, or that all the data has
been out put in single mode.
Bit 5
EMPB Description
0 FIFO2 contains data.
1 FIFO2 contains no data. (Init ial value)
Bit 4FIFO1 Empty Flag (EMPA): Indicates tha t FIFO1 has no data, or tha t all the data has
been out put in single mode.
Bit 4
EMPA Description
0 FIFO1 contains data.
1 FIFO1 contains no data. (Init ial value)
Rev. 1.0, 02/00, page 594 of 1141
Bit 3FIFO2 Overwrite Fl ag (OVWB): If a write is attempted when the FIFO2 is full of the
timing pattern data and the output pattern data (FLB bit = 1), the write operation becomes invalid,
an interrupt is genera ted , the OV WB flag is set to 1, and the write data is lost. Wait until space
becomes available in the FIFO2, then write again.
Write 0 to clear the OVWB flag, because it is not cleared automatically.
Bit 3
OVWB Description
0 Normal oper at ion. (Init ial value)
1 Indicates that a write in FIFO2 was attempted when FIFO2 was full of data. Clear
this flag by writing 0 to this bit.
Bit 2FIFO1 Overwrite Flag (OVWA): If a write is attempted when the FIFO1 is full of the
timing pattern data and the output pattern data (FLA bit = 1), the write operation becomes invalid,
an interrupt is gene rated, the OVWA flag is set to 1, and the write data is lost. Wait unt il space
becomes available in the FIFO1, then write again.
Write 0 to clear the OVWA flag, because it is not cleared automatically.
Bit 2
OVWA Description
0 Normal oper at ion. (Init ial value)
1Indicates that a write in FIFO1 was attempted when FIFO1 was full. Clear this
flag by writ ing 0 t o this bit.
Bit 1FI FO2 Pointer Cl ea r (CLRB): Clears the FIFO2 write position pointer. After 1 is
written, the bit immediately reverts to 0. Writing 0 in this bit has no effect.
Bit 1
CLRB Description
0 Normal oper at ion. (Init ial value)
1 Clears the FI FO2 pointer.
Bit 0FI FO1 Pointer Cl ea r (CLRA): Clears the FIFO1 write posi tion point e r. After 1 is
written, the bit immediately reverts to 0. Writing 0 in this bit has no effect.
Bit 0
CLRA Description
0 Normal oper at ion ( I nitial value)
1 Clears the FI FO1 pointer
Rev. 1.0, 02/00, page 595 of 1141
HSW Mode Register 2 (H SM2)
0
0
1
0
R
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7EDG ISEL1 SOFG OFG VFF/NFF
0
R/W
FRT
WR/WR
FGR2OFF LOP
Bit :
Initial value :
R/W :
HSM2 is an 8-bit register which confirms and determines t he operational st ate of the HSW t imi ng
generator.
Bit 1 i s a read-only bit, and write is disable d. Bit 0 is a write-only bit, and if a read i s attempted,
an undetermined value is read out. All the other bits accept both read and write. It is initialized to
H'00 by a rese t or in stand-by mode.
Bit 7Free-run Bit (FRT): Selects whether the matching timing is determined by the DPG
counter and timer, or by the FRC.
Bit 7
FRT Description
0 5-bit DFG counter + 16-bit timer counter (Init ial value)
1 16-bit FRC
Bit 6FRG2 Clear Stop Bit (FGR2OFF): Disable s clear i n g of the counter by the DFG regi ster
2. The FIFO group, including both FIFO1 a nd FIFO2, is available.
Bit 6
FGR2OFF Description
0 Enables clearing of the16-bit t imer counter by DFG register 2 ( Initial value)
1 Disables clearing of the16-bit timer counter by DFG register 2
Bit 5Mode Selection Bit (LOP): Selects the output mode of FIFO. If the loop mode is
selected, LOB3 to LOB0 bits and LOA3 to LOA0 bits become valid. If the LOP bit is modified,
the pointe r which counts t he wri ting posit ion of FIFO is cleared. In this case, the last output data
is kept.
Bit 5
LOP Description
0 Single mode ( Initial value)
1 Loop mode
Rev. 1.0, 02/00, page 596 of 1141
Bit 4DFG Edge Selection Bit (EDG): Select s the edge by which to count DFG pulses.
Bit 4
EDG Description
0 Counts by the r ising edge of DFG (Initial value)
1 Counts by the falling edge of DFG
Bit 3Interrupt Selection Bi t (ISEL1): Selects t he interrupt source. (IRRHSW1)
Bit 3
ISEL1 Description
0Generates an interrupt request by the rising edge of the STRIG signal of FIFO
(Init ial value)
1 Generates an interrupt request by the matching signal of FIFO
Bit 2FIFO Output Group Selection Bit (SOFG): Sel ec t s whether 2 0 stages of FIFO1 +
FIFO2 or only 10 stages of FIFO1 are used.
If 20-st a ge output mode is used in single mode, data must be written to FIFO1 and FIFO2.
Moni t o r the output FIFO g roup flag (OFG) and contr ol dat a writ i ng by softwa re. All the data of
FIFO1 is output, then all the dat a of FIFO2 is out put. These steps a re repeate d. If 10-stage output
mode is used, the data of FIFO2 is not reflected.
Modi f y ing the SOFG bit fr om 0 to 1, then again t o 0 initializes the control signal of the FIFO
output sta ge to t he FIFO1 side.
Bit 2
SOFG Description
0 20-stage out put of FIFO1 + FIFO2 (Initial value)
1 10-stage out put of FIFO1 only
Bit 1Output FIFO Group Flag (OFG): Indicates the FIFO group which is outputting.
Bit 1
OFG Description
0 Patt ern is being output by FIFO1 (Init ial value)
1 Patt ern is being output by FIFO2
Rev. 1.0, 02/00, page 597 of 1141
Bit 0Out put Switching Bit Between Vi deoFF and Narro wFF (VFF/ NFF ): Sw itches th e
signal out put from t he VideoFF pin.
Bit 0
VFF/NFF Description
0 VideoFF out put (Initial value)
1 NarrowFF output
HSW Loop Stage Number Setting Register (HSLP)
0
*
1
*
R/W
2
*
R/W
3
*
4
*
R/W
5
*
6
*
7
R/W R/WR/W
LOB1
R/W
LOB2
*
R/W
LOB3 LOB0 LOA3 LOA2 LOA1 LOA0
Bit :
Initial value :
R/W :
HSLP is an 8-bit read/write register that sets the number of the loop stages when the HSW timing
ge nerator is in loo p mode. It is valid when bit 5 (LOP) of HSM2 is 1. Bits 7 to 4 set the number
of FIFO2 stages. Bits 3 to 0 set the number of FIFO1 stages.
It is not initialized by a reset or in stand-by or module stop mode; accordi ngly be sure to set the
number of the stages when the loop mode is used.
Rev. 1.0, 02/00, page 598 of 1141
Bits 7 to 4FIFO2 Stage Number Setting Bi ts (LOB3 to LOB0): Set the number of FIFO2
stage s in loop mode. T hey are valid only whe n the l oop mode is set (LOP bit of HSM2 is 1).
HSM2 HSLP
Bit 5 Bit 7 Bit 6 Bit 5 Bit 4
LOP LOB3 LOB2 LOB1 LOB0 Description
0****Single mode (Initial value)
0 Only 0th stage of FIFO2 is output0
1 0th and 1st stages of FIFO2 are out put
0 0th to 2nd stages of FIFO2 are out put
0
1
1 0th to 3rd stages of FIFO2 are output
0 0th to 4th stages of FIFO2 are output0
1 0th to 5th stages of FIFO2 are output
0 0th to 6th stages of FIFO2 are output
0
1
11 0th to 7th stages of FIFO2 are output
0 0th to 8th stages of FIFO2 are output
1
1001 0t h to 9th stages of FIFO2 ar e output
01 1
00
1
0
1
1
1
Setting pr ohibited
Note: * Don't care.
Rev. 1.0, 02/00, page 599 of 1141
Bits 3 to 0FIFO1 Stage Number Setting Bi ts (LOA3 to LOA0): Set the number of FIFO1
stage s in loop mode. T hey are valid only whe n the l oop mode is set (LOP bit of HSM2 is 1).
HSM2 HSLP
Bit 5 Bit 3 Bit 2 Bit 1 Bit 0
LOP LOA3 LOA2 LOA1 LOA0 Description
0****Single mode (Initial value)
0 Only 0th stage of FIFO1 is output0
1 0th and 1st stages of FIFO1 are out put
0 0th to 2nd stages of FIFO1 are out put
0
1
1 0th to 3rd stages of FIFO1 are output
0 0th to 4th stages of FIFO1 are output0
1 0th to 5th stages of FIFO1 are output
0 0th to 6th stages of FIFO1 are output
0
1
11 0th to 7th stages of FIFO1 are output
0 0th to 8th stages of FIFO1 are output
1
1001 0t h to 9th stages of FIFO1 ar e output
01 1
00
1
0
1
1
1
Setting pr ohibited
Note: * Don't care.
Rev. 1.0, 02/00, page 600 of 1141
FIFO Output P atter n Register 1 (FPDRA)
8
*
9
*
W
10
*
W
11
*
12
*
W
*
W
1314
*
15
—
—
NarrowFFA
VFFA AFFA VpulseA MlevelA
1WWW
ADTRGA STRIGA
0
*
1
*
W
2
*
W
3
*
4
*
W
*
W
56
*
7PPGA4 PPGA3 PPGA2 PPGA1 PPGA0
*
W
PPGA7
WWW
PPGA6 PPGA5
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
Note : * Don't care
FPDRA is a buffe r register for the FIFO1 out put pattern regi ster. The output pattern data written
in FPDR A is written at the same time to the positio n of the FIFO1 pointe d by the buffe r pointe r.
Be sure to write the out p ut patt er n da ta in FPDRA befo re writing it i n FTPRA.
FPDRA is an 16-bit write-only register. Onl y a word access is valid. If a byte access is
attempted, correct ope ration is not guara nteed. No read is valid. If a read is attempted, an
undetermined val ue is rea d out. It is not initialized by a reset, or in stand-by or module stop mode;
accordingly be sure to write data before use.
Bit 15Reserved: Cannot be read or modifi e d.
Bit 14A/D Trigger A Bit (ADTRG A): Indicates a hardware trigger signal for the A/D
converter.
Bit 13S-TRIGA Bit (STRIGA): Indicates a signa l that generates a n interrupt. W hen the
STRIGA is selected by the ISEL, modifying this bit from 0 to 1 generates an interrupt.
Bit 12NarrowFF A Bit (Nar rowFFA): Cont rols t he narrow video hea d.
Bit 11VideoF FA Bit (VFFA): Controls the video he ad.
Bit 10AudioFFA Bit (AFFA): Contro ls the audio head.
Bit 9VpulseA Bit (Vpulse A): Used for generating an additional V signal. For details, re fer to
section 26.12, Additional V Signal Gene rator.
Bit 8Ml ev elA Bi t (Ml e vel A ) : Used for generating an additional V si gnal. For de tails, refe r to
section 26.12, Additional V Signal Gene rator.
Bits 7 to 0PPG O utput Signal A Bi ts (PPGA7 to PPGA0): Used for outputting a timing
con t rol si gnal fr om port 7 (PPG).
Rev. 1.0, 02/00, page 601 of 1141
FIFO O utput Pattern Re gister 2 (FPDRB)
8
*
9
*
W
10
*
W
11
*
12
*
W
*
W
1314
*
15
—
—
NarrowFFB
VFFB AFFB VpulseB MlevelB
1WWW
ADTRGB STRIGB
0
*
1
*
W
2
*
W
3
*
4
*
W
*
W
56
*
7PPGB4 PPGB3 PPGB2 PPGB1 PPGB0
*
W
PPGB7
WWW
PPGB6 PPGB5
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
Note : * Don't care
FPDRB is a buffer regi ste r for the FIFO2 output pa ttern register. The out put pattern data written
in FPDRB is written a t the same time to the position of t he FIFO2 poin ted by t he buffer pointer.
Be sure to write the output pattern data in FPDRB before writing it in FTPRB.
FPDRB is an 16-bit writ e-only register. Only a word access is valid. If a byte access i s attem pted,
correct ope ration i s not guaranteed. No rea d is valid. If a read is attempted, an undetermined
value is rea d out . It i s not initialized by a reset, or in stand-by or module stop mode; accordingl y
be sure t o writ e data before use.
Bit 15Reserved: Cannot be read or modifi e d.
Bit 14A/D Trigger B Bit (ADTRGB): Indicates a hardware trigger signal for the A/D
converter.
Bit 13S-TRIGB Bit (STRIGB): Indicates a signal that generates an interrupt. When the
STRIGA is selected by the ISEL, modifying this bit from 0 to 1 generates an interrupt.
Bit 12NarrowFF B Bit (NarrowFFB): Cont rols the narrow vi deo head.
Bit 11VideoFF B Bit (VFFB): C o n trols the vid eo h ead.
Bit 10AudioFFB Bit (AFFB): Con trols the audio he ad.
Bit 9VpulseB Bit (Vpul seB): Used for gene rating an addi tional V signal. For details, refe r to
section 26.12, Additional V Signal Gene rator.
Bit 8Mleve lB Bit (Mlevel B): Used for gene rating an additional V signal. For details, refer to
section 26.12, Additional V Signal Gene rator.
Bits 7 to 0PPG O utput Signal B Bits (PPGB7 to PPGB0): Used for outpu tting a timing
con t rol si gnal fr om port 7 (PPG).
Rev. 1.0, 02/00, page 602 of 1141
FIFO Ti mi ng P attern Re gi ster 1 (FTPRA)
8
*
9
*
W
10
*
W
11
*
12
*
W
*
W
1314
*
15 FTPRA12 FTPRA11 FTPRA10 FTPRA9 FTPRA8
*
W
FTPRA15
WWW
FTPRA14 FTPRA13
Bit :
Initial value :
R/W :
0
*
1
*
W
2
*
W
3
*
4
*
W
*
W
56
*
7FTPRA4 FTPRA3 FTPRA2 FTPRA1 FTPRA0
*
W
FTPRA7
WWW
FTPRA6 FTPRA5
Bit :
Initial value :
R/W :
Note : * Don't care
FTPRA is a register to write the timing patter n data of FIFO1. The timing data written in FPDRA
is writte n at the same time to the position of the FIFO1 pointed by the buffer pointer toget he r with
the buffer data of FPDRA.
FTPRA is an 16-bit wri t e-only regi ster. Only a word access is valid. If a byte a ccess is attempted,
correct ope ration i s not guaranteed. It is not initialized by a reset or in stand-by or module stop
mode; accordingl y be sure to write da ta before use.
Note: The same address is assigned to the FTPRA and the FIFO timer capture register (FTCTR).
Accordingly, the value of FTCTR is read out if a read is attempted.
FIFO Ti mi ng P attern Re gi ster 2 (FTPRB)
8
*
9
*
W
10
*
W
11
*
12
*
W
*
W
1314
*
15 FTPRB12 FTPRB11 FTPRB10 FTPRB9 FTPRB8
*
W
FTPRB15
WWW
FTPRB14 FTPRB13
Bit :
Initial value :
R/W :
0
*
1
*
W
2
*
W
3
*
4
*
W
*
W
56
*
7FTPRB4 FTPRB3 FTPRB2 FTPRB1 FTPRB0
*
W
FTPRB7
WWW
FTPRB6 FTPRB5
Bit :
Initial value :
R/W :
Note : * Don't care
FTPR B is a register to writ e the tim ing patt ern data of FIFO2 . The ti mi ng dat a writ te n in FPDRB
is writte n at the same time to the position of the FIFO2 pointed by the buffer pointer toget he r with
the buffer data of FPDRB.
FTPRB i s an 16-bit wri te-only re gister. Only a word access is valid. If a byte access i s attempted,
correct ope ration i s not guaranteed. If a read is attempted, an undetermined value is read out. It is
not initia lized by a reset or in stand-by or module stop mode; accordi ngly be sure to write data
before use .
Rev. 1.0, 02/00, page 603 of 1141
DFG Refe rence Regi ster 1 (DFCRA)
0
*
1
*
W
2
*
W
3
*
4
*
W
0
W
56
0
7DFCRA4 DFCRA3 DFCRA2 DFCRA1 DFCRA0
0
W
ISEL2
WWW
CCLR CKSL
Bit :
Initial value :
R/W :
Note : * Don't care
DFCRA is a register which determines the operation of the HSW timing generator as well as the
starting point of the timing of FIFO1.
DFCRA is an 8-bit writ e-only regi ster. It is not initialized by a reset or i n stand-by or module stop
mode; accordingl y be sure to write da ta before use.
Note: T he same address i s assigned to the DFCRA and th e DFG reference counter register
(DFCTR). Acc ordingly, the va lue of DFCTR is read out in the low-order five bits if a
read is attempted.
Bit 7Interrupt Selection Bi t (ISEL2): Selects th e interrup t source. (IRRHS W2)
Bit 7
ISEL2 Description
0 Generates an interrupt request by the clear signal of the 16-bit timer counter
(Init ial value)
1 Generates an interrupt request by the VD signal in PB m ode
Bit 6DFG Counter Clea r Bit (CCLR): Forcibly clears the 5-bit DFG counter by software.
After 1 is written, the bit immediately reverts to 0. Writing 0 in this bit has no effect.
Bit 6
CCLR Description
0 Normal oper ation (Init ial value)
1 Clears the 5-bit DFG count er
Rev. 1.0, 02/00, page 604 of 1141
Bit 516-bit Timer Counter Cloc k Source Se lection Bit (CKSL): Selects the cl oc k source of
the 16-bit timer counter.
Bit 5
CKSL Description
0φs/4 (Initial value)
1φs/8
Bits 4 to 0FIFO1 O utput Timing Se tti ng Bits (DF CRA4 to DFCRA0): Determines the
starting point of the timing of FIFO1. The initial value is undetermined. Be sure to set a value
af ter a reset or stan d -by. It is valid on ly if bit 7 (FRT bit ) of HSM2 is 0.
DFG Refe rence Regi ster 2 (DFCRB)
0
*
1
*
W
2
*
W
3
*
4
*
W
56
1
7
DFCRB4 DFCRB3 DFCRB2 DFCRB1 DFCRB0
WW
11
Bit :
Initial value :
R/W :
Note : * Don't care
DFCRB is a register which determines the starting point of the timing of FIFO2.
DFCRB is an 8-bit write-only regi ster. If a read is attempted, an undetermined val ue is read out.
Bits 7 to 5 are reserved; they cannot be modified and are always read as 1. It is not initialized by
a reset or in stand-by or module stop mode; accordingly be sure to write dat a before use.
Bits 4 to 0FIFO2 Output Ti ming Se tting Bits (DF CRB4 to DFCRB0): Sets the starting point
of the timing of FIFO2. The value after reset or after st a nd-by m ode is entered is undetermined;
be sure t o writ e data before use.
It is val id onl y if bit 7 (FRT bit) of HSM2 is 0.
Rev. 1.0, 02/00, page 605 of 1141
FIF O Timer Capture Register (F T CTR)
8
0
9
0
R
10
0
R
11
0
12
0
R
0
R
1314
0
15 FTCTR12 FTCTR11 FTCTR10 FTCTR9 FTCTR8
0
R
FTCTR15
RRR
FTCTR14 FTCTR13
Bit :
Initial value :
R/W :
0
0
1
0
R
2
0
R
3
0
4
0
R
0
R
56
0
7FTCTR4 FTCTR3 FTCTR2 FTCTR1 FTCTR0
0
R
FTCTR7
RRR
FTCTR6 FTCTR5
Bit :
Initial value :
R/W :
FTCRT is a register to display the count of the 16-bit timer counter.
FTCRT is an 16-bit read-only register. It captures the counter value when the VD signal is
detected in PB mode. Only a word access is accepted. If a byte access is attempted, correct
operation i s not gua ranteed. It is i nitialized to H' 0000 by a reset or in stand-by mode.
Note: The same address is assigned to the FTCTR and the FIFO timing pattern register 1
(FTPRA). Accordingly, if a write is attempted, the value is written in FTPRA.
DFG Refe rence Co unt Register ( DFCTR)
0
*
1
*
R
2
*
R
3
*
4
*
R
56
1
7
DFCTR4 DFCTR3 DFCTR2 DFCTR1 DFCTR0
RR
11
Bit :
Initial value :
R/W :
Note : * Don't care
DFCTR is a register to c ount DFG pulses.
DFCTR is an 8-bit read-onl y regis ter . Bits 7 to 5 are reserved; they cannot be modifi ed and are
always re ad as 1. It is ini t ialized t o H'E0 by a reset or i n stand-by mode.
Note: Th e same a ddre ss is assig ned to the DFCTR and the DFG referen ce register 1 (DFCRA).
Accordingly, if a write is attempted, the value is written in DFCRA.
Bits 4 to 0—DFG Pulse Count Bi ts (DFCTR4 to DFCTR0): The se bits count DFG pulse s.
Rev. 1.0, 02/00, page 606 of 1141
26.4.6 Operation
5-Bit DFG Counte r : The 5-bit DFG counter increme nts the count at t he DFG edges selected by
th e E DG bit of HSW Mode Register 2. The DFG co unt e r is clear e d by a DPG risin g edge, or by
writing to the C CLR bi t o f the DFG refere nce regi ste r 1.
16-Bit Timer Counter: The 16-bi t timer c ounter c a n operate in DFG refe re nce m ode or in free-
running mode.
• DFG Refer e nce Mode
The timer counter operates by referencing the DFG signal. When the 5-bit DFG counter value
matches the value specifi ed in the DFG reference register 1 or 2, the 16-bi t timer counter is
initialized; this is the start point of the FIFO output timing.
In DFG ref ere nce mode, the star t poin t specifyin g method can be selected by the FGR2OFF bit
of t he HSW mode register 2: one way is to specify bot h FIFO1 and FIFO2 by only one regi ste r
(DFG re fer e nce register 1), and the other is to specif y FIFO1 and FIFO2 by DFG ref e rence
registers 1 and 2, respect ively. When only the DFG re ference register 1 i s used, the continuous
values must be set to FIFO1 and FIFO2 as the timing patters.
• Free-Running Mode
The timer counter operates in association with the prescaler unit. When the 18-bit free-running
counter in t he prescaler unit overflows, the 16-bit timer counter i n the HSW timing genera t or
is initialized; this is the start point of the FIFO output timing.
Compare Circui t: The c ompare c i rcuit compares the 16-bit time r counte r value with t he FIFO
timing pattern, and when they match, the compare circuit generates a trigger signal for outputting
the next-sta ge FIFO data.
FIFO: The FIFO generates a head switch si gnal for VCR and patterns for servo cont rol. Dat a is
set to FIFO by using the FIFO ti ming pattern registe rs 1 and 2, a nd FIFO output pattern regi ste rs 1
and 2.
The FIFO operates in single mode and loop mode. In these two modes, the number of output
stages can be selected by the FIFO output group selection bit: 20-stage out put using both FIFO1
and FIFO2 or 10-stage out put using only FIFO1.
• Single Mo de
The output pattern data is output when the timing pattern matches the counter value. The data,
once output, is lost, and the internal pointer is decrementd by 1. After the last data is output,
the FIFO stops ope ration until data is written again. When 20-stage output is used, writ i ng in
FIFO1 and FIFO2 must be controlled by software.
Rev. 1.0, 02/00, page 607 of 1141
• Loop Mode
The data output cycle is repeated from stage 0 to the final stage selected in the HSW loop
number setting register. As in single mode, the output pattern data is output when the timing
pattern matches the counter value. In loop mode, the FIFO data is retained.
Data in each FIFO group can be modifie d in loop mode . The FIFO group currently output ting
da ta ca n be checked by the OFG bit of the HSW mode registe r 2; after checking the out p utti n g
FIFO group, clear the FIFO group which is not out putting data, t hen write new data to i t.
Writing new data must be completed before the FIFO group starts operation. The FIFO cannot
be modified partially because the write pointer is outside the loop stages.
Figures 26.23 and 26. 24 show exam ples of the timing waveform a nd operation of the HSW ti ming
generator.
Rev. 1.0, 02/00, page 608 of 1141
DPG
01
tA1
tA2 tB1
tA3 tA1
234567891011 012
V.FF
A.FF
Clear A
Clear B
Example of setting: DFCR=H'02, DFCRB=H'08, HSLP=H'21, DFG falling edge
DFG
Figure 26.23 Example of Timing Waveform of HSW (for 12 DFG Pulses)
Rev. 1.0, 02/00, page 609 of 1141
Output pattern data
φ
s/4
WW
FTPRB
FIFO2
tB0 PB9
tB5 PB4
tB4 PB3
tB3 PB2
tB2 PB1
tB1 PB0
WW
FPDRA
Output select buffer Output data buffer
Comparator
FTPRA
FIFO1
tA0 PA9
tA5 PA4
tA4 PA3
tA3 PA2
tA2 PA1
tA1 PA0
Internal bus
FPDRB
Timer counter
Figure 26.24 Example of O peration of the H SW Timing Gener ator
Rev. 1.0, 02/00, page 610 of 1141
• Example of operation in single mode (20 stages of FIFO used)
1 Set to single mode (LOP = 0)
2 W r it e the out put patte rn data (PA0) to FPDRA.
3 Write the output timing (tA1) to FTPRA. tA1 is written in FIFO1 together with PA0. This
initializes the output pattern data to PA0.
4 Re p eat t he ste p s i n the s am e w ay, un ti l P A1 , P A2, et c., ar e set.
5 Write the out put pattern da ta (PB0) to FPDRB.
6 Write the output timing (tB1) to FTPRB. tB1 is written in FIFO2 together with PB0. This
initializes the output pattern data to PB0.
7 Repeat these steps in the same way, until PB1, PB2, etc., are set.
By step 3, the pattern da ta of PA0 is output.
If tA1 matches with the timer counter, the pattern data of PA1 is output.
If tA2 matches with the timer counter, the pattern data of PA2 is output.
.
.
.
After this sequence is repeated and all the pattern data set in FIFO1 is output, the pattern data of
FIFO2 is output. After the pattern data is output, the pointer is decremented by 1. Care is
required, however, because matching of tA0 is not detected until data is written in FIFO2.
Matching of tB0 also is not detected until data is written in FIFO1 again.
Rev. 1.0, 02/00, page 611 of 1141
• Example of the oper ation in loop mode mode
1 Set the number of loop stages in HSLP register (e.g. HSLP = H'44)
2 W r it e the out put patte rn data (PA0) to FPDRA.
3 Write the output timing (tA1) to FTPRA. tA1 is written in FIFO1 together with PA0. This
initializes the output pattern data to PA0.
4 Re p eat t he ste p s i n the s am e w ay, un ti l P A1 , P A2, et c., ar e set.
5 Write the out put pattern da ta (PB0) to FPDRB.
6 Write the output timing (tB1) to FTPRB. tB1 is written in FIFO2 together with PB0. This
initializes the output pattern data to PB0.
7 Repeat the steps in the same way, until PB1, PB2, etc., are set.
By step 3, the pattern da ta PA0 is output.
If tA1 matches the timer counter, the pattern data PA1 is output.
If tA2 matches the timer counter, the pattern data PA2 is output.
.
.
.
If tA4 matches the timer counter, the pattern data PA4 is output.
If tA5 matches the timer counter, the pattern data PB0 is output.
If tB1 matches the timer counter, the pattern dat a PB1 is output.
.
.
.
If tB4 matches the timer counter, the pattern dat a PB4 is output.
If tB5 matches the timer counter, the pattern dat a PA0 i s output.
.
.
.
Rev. 1.0, 02/00, page 612 of 1141
26.4.7 Interrupts
The HSW timing gene rator ge nerates i nterrupts unde r the fol lowing condit i ons.
1 IRRHSW1 occ urs when pa ttern da t a is written (OVW A, OVWB = 1) while FIFO is full
(FULL).
2 IRRHSW1 occurs when matching is detected while the STRIG bit of FIFO is 1.
3 IRRHSW1 occ urs when the val ue s of the 16-bit timer counter and 16-bit timing pattern
register ma tch.
4 IRRHSW2 occ urs when the 16-bit timer c ounter is cleared.
5 IRRHSW2 occurs when a VD signal (capture signal of the timer capture register) is received in
PB mode.
Condition 2 or 3, as well as 4 or 5, are sel ected by ISEL1 and ISEL 2.
Rev. 1.0, 02/00, page 613 of 1141
26.4.8 Cautions
• When bot h the 5-bit DFG c ounter a nd 16-bit timer c ounter are operating, the l a tter is not
cleared if input of DPG and DFG signals is stopped. T hi s leads t o free-running of the 16-bit
timer counter, and periodical detection of matching by the 16-bit timer counter. In such a case,
the p e rio d of the output from the HSW timin g generator is indepen dent fr om DPG or DFG.
• Spec ify the mode setti ng bit (LOP) of the HSW mode registe r 2 (HSM2) immediat ely bef ore
writing the FIFO data.
• Input the rising edge of DPG and DFG count edge at diffe re nt timings. If they are input at the
sam e ti min g, cou nti ng up DFG and clear i ng the 5- bit DFG c ounte r occu r simu l ta neo us l y. In
this case, the latter will take precedence. This leads to the DFG counter lag by 1. Figure 26.25
shows the input ti ming of DPG and DFG.
• If stop of the drum system is require d when FIFO output is bei ng used in the 20-stage output
mo de, m odi f y the SOFG bit of HSM2 regi ster f rom 0 to 1, th e n again to 0 by softwa re, and be
sure to initialize the FIFO output stage to the FIFO1 side. Also clear and rewrite the data of
FIFO1 a n d FIFO2.
DPG
I ± Tp · FG | >
φ
(1 state)
Tp · FG
DFG
Note: When the 5-bit DFG counter increments count at the rising edge of DFG
Fi g ure 26.25 Input Timi ng of DPG and DFG
Rev. 1.0, 02/00, page 614 of 1141
26.5 High-Speed Switching Circuit for Four-Head Special Playback
26.5.1 Overview
This high-speed switching ci rcuit generates a color rotary signal (C.Rota ry) and head-amplifier
switching signal (H.Amp SW) for use in four-head special playback.
A pre-amplifier output c omparison result signal is input from the COMP pin. The signal output to
the C.Rota ry pin is a chroma signal processing control signal. The signal output at the H.Amp SW
pin is a pre-amplifier output select signal. To reduce the width of noise bars, the C.Rotary and
H.Am p SW sig nal s are synch ronized to the horizo ntal sync si gnal (OSC H) . OSCH is made by
adding supplemented H, which has been separated from Csync signal in the sync signal detector
circuit. For more details of OSCH, see section 26.15, Sync Signal Detector.
If the VCR system does not require this circuit, C.Rotary, H.Amp SW, and COMP pins can be
used as th e I/O por t.
26.5.2 Block Diagram
Figure 26. 26 shows the block diagram of this circuit.
WW
Synchronization
control
CHCR
W
CHCR
RTP0
H.Amp SW
C.Rotary
OSCH
(Synchronization)
COMP
NarrowFF
VideoFF
W
CHCR
Internal bus
Internal bus
HAHCRH
W
CHCR
SIG3 to 0
HSWPOLV/N
Decoding circuit
Figure 26.26 High-Speed Switching Circuit for Four-Head Special Playback
Rev. 1.0, 02/00, page 615 of 1141
26.5.3 Pin Confi guration
Table 26. 7 summarizes the pin c onfiguration of the high-speed switching ci rcuit for four-head
special pla yback. If this circuit is not used, the pi ns can be used as I/O port. See section 26.2,
Servo Port.
Table 26. 7 Pin Configuration
Name Abbrev. I/O Function
Compare input pin COMP Input Input of pr e-amplifier output result signal
Color rotary signal output pin C.Rotary Output Output of chrom a processing control
signal
Head amplifier switch pin H.Amp SW Output Output of pr e-amplifier output select
signal
26.5.4 Register Description
Register Confi g urat i o n
Table 26. 8 shows the re gister c onfiguration of the high-speed swi t ching ci rcuit for four-head
special playback.
Table 26. 8 Register Configurati on
Name Abbrev. R/W Si ze Initi al Value Addr ess
Special playback contr ol
register CHCR W Byte H'00 H'D06E
Rev. 1.0, 02/00, page 616 of 1141
Special Playback Control Register (CHCR)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7HAH SIG3 SIG2 SIG1 SIG0
0
W
V/N
WWW
HSWPOL CRH
Bit :
Initial value :
R/W :
CHCR i s an 8-bit wri te-only re gi ster. It cannot be read. It is initialized t o H'00 by a reset, or in
standby or module st op mode.
Bits 7HSW Signal Select Bit (V/N): Selects the HSW signal to be used at special playback.
Bit 7
V/N Description
0 Video FF signal output (Initial value)
1 Narrow FF signal output
Bit 6COMP Polarity Select Bit (HSWPOL): Selects the polarit y of the COMP sig nal.
Bit 6
HSWPOL Description
0 Pos itive (Initial value)
1 Negative
Bit 5C.Rotary Synchroniz ati on Control Bi t (CRH): Synchronizes C.Rotary si gnal with the
OSCH sig nal.
Bit 5
CRH Description
0 Synchronous (I nitial value)
1 Asynchronous
Rev. 1.0, 02/00, page 617 of 1141
Bit 4H.Am pSW Synchronizati o n Contr ol Bit (HAH) : Sync hronizes H.AmpSW si gnal with
the OSC H signal .
Bit 4
HAH Description
0 Synchronous (I nitial value)
1 Asynchronous
Bits 3 to 0Signal Control (SIG3 to SIG0): These bits, combined with the state of the COMP
input pi n, control t he outputs a t the C. Rotary a nd H.Am pSW pins.
Bit 3 Bit 2 Bit 1 Bit 0 Output pins
SIG3 SI G2 SIG1 SI G0 C.Rot ary H. Am p SW
0 * * L L ( Initial value)
0HSW L0
1HSW H
0L HSW
01
11H
+6:
0 HSW EX-O R
COMP COMP0
1HSW EX-NO R
COMP COMP
0 HSW E-O R RTP0 RTP0
1
11
*
HSW EX-NO R
RTP0 RTP0
Note: * Don't care.
Rev. 1.0, 02/00, page 618 of 1141
26.6 Dru m S peed Error Det ect or
26.6.1 Overview
Drum spe ed error c ontrol hol ds the drum at a consta nt revolution speed, by measuri ng the pe riod
of t he DFG signal. A digita l c ounter dete cts the sp eed er ror agai n st a preset val ue. The speed
error data is processed and added t o phase error data in a digital fil t er. T hi s fil ter controls a pulse-
width modulated (PWM) output, which controls the revol ution speed and phase of the drum.
The DFG input sign al is reshaped into a square wa ve by a reshaping c i rcuit, and sent to t he speed
error detector a s the DFG signal.
Th e spee d er ror dete ct o r use s the syste m clock to mea sure the period of the DFG signal, a n d
detects the error against a preset data value. The preset data is the value that results from
measuring the DFG signal peri od with the c l ock signal when the drum motor is running at the
correct spee d.
The error detector operates by l atching a counter val ue whe n it detects an edge of t he DFG signal.
The latched c ount provide s 16 bit s of speed error data for the digital fil ter to operate on. The
digital filter proce sses and adds the spee d error data to phase error data from t he drum phase
control system, the n sends the result to the PWM as drum error data.
26.6.2 Block Diagram
Figure 26. 27 shows a block diagram of the drum speed error detector.
Rev. 1.0, 02/00, page 619 of 1141
WW R
UDF
OVF
Lock 2 up
Clear
Latch
Preset
DFVCR
DFRLOR
DFVCRDFPRDFVCR
DFVCRDFVCRDFUCRFGCR
DFER
DFRVCR
Error data
(16 bits)
To DFU
ADDFGN
NCDFG
DFRUDR
Internal bus
W R/W
Internal bus
R/W WR/WR/W
R/W R/W (R)/W
Lock 1 up
S
RF/FQ
S
R
F/F
DFRCS1,0
DF-R/UNR
Lock counter
(2 bits)
Q
S
R
F/F
Q
Lock range
detector
Lock range data 1 (16bit)
DPCNT
Error data
limiter
control circuit
DFEFON
DFESS
DRF
Edge
detector
↑, ↓
Error data (16 bits)
Counter (16 bits)
DFOVF
IRRDRM2
IRRDRM1
To DROCKON
DFU
Preset data
(16 bits) Lock range data 2
(16 bits)
DFCS1,0
φs
φs/2
φs/4
φs/8
Figure 26.27 Block Diagram of the Drum Speed Err or Detec tor
Rev. 1.0, 02/00, page 620 of 1141
26.6.3 Regi ster Configur ati on
Table 26. 9 shows the re gister c onfiguration of the drum speed error detector.
Table 26. 9 Register Configurati on
Name Abbrev. R/W Si z e Initi al Value Addr ess
Specified DFG speed
preset data registe r DFPR W Word H'0000 H'D030
DFG speed error dat a
register DFER R/W Word H'0000 H'D032
DFG lock upper dat a
register DFRUDR W Word H'7FFF H'D034
DFG lock lo wer data
register DFRLDR W Word H'8000 H'D036
Drum speed error
detection con trol register DFVCR R/W Byte H'00 H'D038
Rev. 1.0, 02/00, page 621 of 1141
26.6.4 Register Description
Specified DFG Speed Preset Data Register (DFPR)
8
0
9
0
W
10
0
W
11
0
12
0
W
0
W
1314
0
15 DFPR12 DFPR11 DFPR10 DFPR9 DFPR8
0
W
DFPR15
WWW
DFPR14 DFPR13
Bit :
Initial value :
R/W :
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7DFPR4 DFPR3 DFPR2 DFPR1 DFPR0
0
W
DFPR7
WWW
DFPR6 DFPR5
Bit :
Initial value :
R/W :
The DFG speed preset data i s set i n DFPR. Whe n data i s wri tten, the 16-bit pre se t data is sent to
the preset circuit. The preset da ta can be calculated from the following equation by using H'8000*
as the reference value.
φs/n
Specified DFG speed preset data = H'8000 − ( − 2)
DFG fre q uency
φ s: Servo clock frequency (fosc/2) i n Hz
DFG fre q uency: I n Hz
Constant 2 is the presetting int erval (se e Figure 26.28).
φ s/n Clock source of the selected counter
DFPR is a 16-bit write-only register. Onl y a word access i s valid. If a byte access is attempted,
correct ope ration is not guaranteed. DFPR cannot be read. If a rea d is attempted, an
undetermined value is read. DFPR i s initialized to H'0000 by a rese t, and in sta ndby mode and
module stop mode.
Note: The preset data value is calculated so that the count e r will reach H'8000 when the error i s
zero. When the counter val ue is la tched as error data in the DFG speed error data register
(DFER), however, it is converted to a value refe renced to H'0000.
Rev. 1.0, 02/00, page 622 of 1141
DFG Speed Error Data Register (DFER)
8
0
9
0
R*/W
10
0
R*/W
11
0
12
0
R*/W
0
R*/W
1314
0
15 DFER12 DFER11 DFER10 DFER9 DFER8
0
R*/W
DFER15
R*/WR*/WR*/W
DFER14 DFER13
Bit :
Initial value :
R/W :
Note: Note that only detected error data can be read.
0
0
1
0
R*/W
2
0
R*/W
3
0
4
0
R*/W
0
R*/W
56
0
7DFER4 DFER3 DFER2 DFER1 DFER0
0
R*/W
DFER7
R*/WR*/WR*/W
DFER6 DFER5
Bit :
Initial value :
R/W :
DFER is a 16-bit read/write register that store s 16-bit DFG spe e d error data. When the drum
motor spe ed is correct, the data latched in DFE R is H' 0000. Negative data will be l atched if the
speed is faster than the specified speed, and positive data if the speed is slower than the specified
speed. The DFER value is sent to the digital filter either automatically or by software.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed.
DFER i s initialized to H'0000 by a reset, and in standby mode and modul e stop mode.
Ref e r to the note Speci fi e d DFG Speed Preset Data Register (DFPR) in 26. 6. 4 Regi ster
Description.
DFG Lock Upper Data Regi ster (DF RUDR)
8
1
9
1
W
10
1
W
11
1
12
1
W
1
W
1314
1
15
DFRUDR
12
DFRUDR
11
DFRUDR
10
DFRUDR
9
DFRUDR
8
0
W
DFRUDR
15
WWW
DFRUDR
14
DFRUDR
13
Bit :
Initial value :
R/W :
0
1
1
1
W
2
1
W
3
1
4
1
W
1
W
56
1
7
DFRUDR
4
DFRUDR
3
DFRUDR
2
DFRUDR
1
DFRUDR
0
1
W
DFRUDR
7
WWW
DFRUDR
6
DFRUDR
5
Bit :
Initial value :
R/W :
DFRUDR is a 16-bit write-only register used to set the lock ra nge on t he UPPER side when drum
spe e d lock i s dete ct ed, a nd to set the lim it va l ue on the UPPE R side when limi te r fun ct i on is in
use. Set a signed data to DFRUDR (bit 15 is a sign-setting bit).
When lock is being detected, if the drum speed is detected within the lock range, the lock counter
which has been set by DFRCS 1 and 0 bits of DFVCR register decrements the count. If the set
value of DFRCS 1 and 0 matches the number of times of occurrence of locking, the computation
of the digital filter in the drum phase system can be controlled automatically. Also, if the DFG
speed error data exceeds the DFRUDR value within the limiter function is in use, the DFRUDR
value can be used as the data for computation by the digital filter.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. No
read is valid. If a read is attempted, an undetermined value is read out. It is initialized to H'7FFF
by a re set, or i n stand-by or module-stop mode.
Rev. 1.0, 02/00, page 623 of 1141
DFG Lock LOWER Data Register (DFRLDR)
8
0
9
0
W
10
0
W
11
0
12
0
W
0
W
1314
0
15
DFRLDR
12
DFRLDR
11
DFRLDR
10
DFRLDR
9
DFRLDR
8
1
W
DFRLDR
15
WWW
DFRLDR
14
DFRLDR
13
Bit :
Initial value :
R/W :
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7
DFRLDR
4
DFRLDR
3
DFRLDR
2
DFRLDR
1
DFRLDR
0
0
W
DFRLDR
7
WWW
DFRLDR
6
DFRLDR
5
Bit :
Initial value :
R/W :
DFRLDR is a 16-bit write-only register used to set the lock range on the LOWER side when drum
speed lock is detected, and to set the limit value on LOWER side when limiter function is in use.
Set a signed data t o DFRLDR (bit 15 is a sign-setting bit).
When lock is being detected, if the drum speed is detected within the lock range, the lock counter
which has been set by DFRCS 1 and 0 bits of DFVCR register decrements the count. If the set
value of DFRCS 1 and 0 matches the number of times of occurrence of locking, the computation
of the digital filter in the drum phase system can be controlled automatically. Also, if the DFG
speed error data is under the DFRLDR val ue whe n the l imiter function is in use, the DFRLDR
value can be used as the data for computation by the digital filter.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. No
read is vali d. If a read is attempted, an undetermined value is rea d out. It is initialized to H'8000
by a re set, or i n stand-by or module-stop mode.
Drum Spee d Error De tec ti on Contr ol Regi ster (DFVCR)
0
0
1
0
(R)
*2
/W
2
0
R/W
3
0
4
0
R/W
0
R/(W)
*1
56
0
7DFRFON
DF-R/UNR
DPCNT DFRCS1 DFRCS0
0
R/W
DFCS1
(R)
*2
/WRR/W
DFCS0 DFOVF
Notes:
Bit :
Initial value :
R/W :
1. Only 0 can be written.
2. If read-accessed, the counter value is read out.
DFVCR is an 8-bit read/write register that controls the operation of drum speed error detection.
Bit 3 accepts only read, and bit 5 accepts only read and 0 write. It is initialized to H'00 by a reset,
or in stand-by or module-stop m ode.
Rev. 1.0, 02/00, page 624 of 1141
Bits 7 and 6Clock Source Selec t ion Bit s (DFCS1, DFCS0): DFCS1 and DFCS0 select the
clock to be supplied to the counter . (φs = fosc/2)
Bit 7 Bit 6
DFCS1 DFCS0 Description
0φs (I n itial value)01φs/2
0φs/41
1φs/8
Bit 5Cou n t er Overflow Flag (DFOVF): DFOVF flag indica tes the overflow of t he 16-bit
timer counter. It is cleared by writing 0. Write 0 after reading 1. Setting has the highest priority
in this flag. If a flag set and 0 write occurs simultaneously, the latter is invalid.
Bit 5
DFOVF Description
0 Normal state. (Init ial value)
1 Indicates that overflow has occurred in the count er.
Bit 4Error Data Limit Function Selection Bit (DFRFON): Enables t he error data limit
function. (Limit va l ues a re the values set in the lock range data re gisters (DFRUDR and
DFRLDR)).
Bit 4
DFRFON Description
0 Disa bl es limit fun c tion. (In itial value )
1 Enables limit function.
Bit 3Drum Lock Flag (DF-R/UNR): Sets a flag if an underflow occurred in the drum lock
counter.
Bit 3
DF-R/UNR Description
0 Indicates t hat the drum speed system is not locked. (Init ial value)
1 Indicates t hat the drum speed system is locked.
Rev. 1.0, 02/00, page 625 of 1141
Bit 2Drum Phase System Fi l ter Computati on Automatic Start Bit (DPCNT): En ab les the
filter computation of the pha se system if an underfl ow occurred i n the drum lock counte r.
Bit 2
DPCNT Description
0 Disables the filter com putation by detection of the dr um lock. (I nitial value)
1Enables t he filter computation of t he phase system when drum lock is
detected.
Bits 1 and 0Drum Loc k Counter Setting Bits (DF RCS1, DFRCS0): Sets the nu mber of times
to dete ct drum loc k s (which mean s the numbe r of times DFG is det ecte d in t he ran ge set by the
lock range data register). The drum lock flag is set when the specified number of drum locks is
dete ct e d. If the NCDFG sig nal i s detecte d out side t he lock range afte r data i s writt en in DFRC S1
and DFRCS0, the data will be stored in the lock counter.
Note: If DFRCS1 or DFRCS0 i s read-accessed, the c ounter value is read out. If bit 3 (drum loc k
flag) is 1 and the drum lock counter's value is 3, it indicates that the drum speed system is
locked. T he drum lock counter stops until lock i s released after underflow.
Bit 1 Bit 0
DFRCS1 DFRCS0 Description
0 Under f low occurs after lock was detected once. ( I nitial value)0
1 Under f low occurs after lock was detected twice.
0 Under f low occurs after lock was detected three times.1
1 Under f low occurs after lock was detected four times.
Rev. 1.0, 02/00, page 626 of 1141
26.6.5 Operation
The drum speed e rror detector detects the speed e rror based on the reference value set in the DFG
specified speed preset register (DFPR). The reference value set in DFPR is preset in th e counter
by NC DFG sign al , and th e counter decreme nts the count by the selec te d cl ock. The timing of the
counter presetting and the error data latching can be selected between the rising or falling edge of
NCDFG sig n al . See section 26.14 .4, FG Cont r ol Regist er ( FGC R) in 26.14. 4 DFG Noise
Removal Ci rcuit. The error data detected is sent to the digital filter circuit. The error da ta is
signed binaries. The data takes a positive number (+) if the speed is slower than the specified
speed, a negative number (-) if the speed is faster, or 0 if it had no error (revolving at the specified
speed). Figure 26.28 shows an example of operation to detect the drum speed.
• Setting the e rror data limit
A lim it can be set to the err or data sent t o the digita l fil te r ci rcuit using the DFG lock data
register (DFRUDR, DFRLDR). Set the upper limit of the error data in DFRUDR and the
lowe r limit in DFRLDR, a nd write 1 i n DFRFON bit. If the error da ta is outside the limit
range, the DFRLDR value is sent to the digital filter circuit if a negative number is latched, or
the DFRUDR value if a positive number is latched, as a limit value. Be sure to turn off the
limit setting (DFRFON = 0) when you set the limit value. If the limit was set with the limit
set ti ng on (DFRFON = 1), result of computati o n is not assur ed.
• Lock detection
If an e rror data is detecte d within t he lock range set in t he lock data registe r, the drum lock flag
(DF-R/UNR) is set by the num ber of the times of locking set by DFRCS1 a nd DFRCS0 bits,
and an i nterrupt is reque sted (IRRDRM2) at the same t ime. The number of the occ urrence of
locking (once to 4 times) before the flag is set can be specified. Use DFRCS1 and DFRCS0
bits for thi s purpose. The on/off status of the phase system digital filter comput ation can be
co ntrolle d autom a ti ca ll y by the status of lock detec t ion when bit 5 (DPHA bit ) of the drum
system digital filter control register (DFIC) is 0 (phased system digital filter computation off)
and DPCNT bit is 1.
• Drum system speed error detection counter
The drum syst em speed error detection c ounter stops the counter and sets the overflow flag
(DFOVF) when an ove rflow occurs. At the same ti me, it generates an interrupt request
(IRRDRM1). To c lea r DFOVF, write 0 after reading 1. If setting t h e flag and writing 0 take
pla ce sim u ltaneou s ly, th e la tter is inv alid.
Rev. 1.0, 02/00, page 627 of 1141
• Interrupt request
IRRDRM1 is generated by the NCDFG signal latch and the overflow of the e rror detection
counter. IRRDRM2 is generated by detection of lock (after the detection of the specified
number of times of locking).
–value+value
Specified speed value
Latch data 0
(no error)
Preset value
Preset period
(2 counts)
Counter
NCDFG signal
Error data latch
signal (DFG ↑)
Preset data
load signal
Figure 26.28 Example of the Drum Spee d Error Detection
(When the Rising Edge of DFG is Selected)
Rev. 1.0, 02/00, page 628 of 1141
26.6.6 fH Correction in Tri ck Play Mode
In trick play mode, the tape speed relative to the video head changes. This change alters the
horizontal sync signal (fH), causing skew. To correct the skew, the drum motor speed must be
shifted to a different speed in each trick play mode, so as to obtain the normal horizontal sync
frequency. To shift the drum motor speed, software should modify the value written in the
spe c ified DFG speed p reset data register in the spee d er ror dete ct o r.
This fH c orrection ca n be expre ssed i n terms of the ba sic freque ncy fF of the drum as follows.
N0
fF = × fF0
N0 + αH (1−n)
Legend:
n: Speed multiplier (FWD = positive, REV = negative)
αH: H alignment (1.5H in standa rd mode, 0.75H in 2x mode, and 0.5H in 3x mode for VHS
and β systems; 1H for an 8-mm VCR)
N0: Standard H numbers within field
fF0: Field frequency
NTSC: N0 = 262.5, fF0 = 59.94
PAL: N0 = 312.5, fF0 = 50.00
Rev. 1.0, 02/00, page 629 of 1141
26.7 Dru m P h ase Error Det ect or
26.7.1 Overview
The drum phase control system must start after the drum motor has reached the specified
revolution speed by the speed c ontrol system. Drum phase control works as follows in record and
playback mo de.
• Record Mode: Phase is controlled so that the vertical blanking intervals of the video signal to
be recorded will line up along the bottom edge of the tape.
• Playback Mode: Phase is controlled so as to trace the recorded tracks accurately.
A counter detects the phase error against a preset value. T he phase error dat a is proce ssed and
added to sp eed error data in a digital filter . This filter controls a pulse-wid th modu la ted
(PWM) out put, whi ch control s the revol ution phase and spee d of t he drum.
The DPG signal from the drum motor is re shaped into a square wa ve by a reshaping c ircuit,
and sent t o the phase error detector.
The phase error detector compares the phase of the DPG pulse (tach pulse), which contains
video head phase information, with a reference signal. In the actual circuit, the comparison is
carried out by c omparing the he ad-switching (HSW) signal, which is delayed by a counte r that
is r e set by DPG, wit h a refere nce si g nal val ue. The ref ere nc e signal i s the REF3 0 sig nal,
which differs between record and playback as follows:
• Record: Vsync signal extracted from the video signal to be re corded (frame ra te signal,
actually 1/2 Vsync).
• Playback: 30 Hz or 25 Hz signal divided from the system clock.
Rev. 1.0, 02/00, page 630 of 1141
26.7.2 Block Diagram
Figure 26. 29 shows a block diagram of the drum phase error detector.
R/W R/W R/W R/W R/W
R/W
REF30P
HSW
(Video FF)
NHSW
(Narrow FF)
DPGCR
DPGCR DPGCR DFUCR
DPGCRDPPR1 DPPR2
R/(W)
S
R
F/F
Q
WW
Internal bus
Internal bus
OVF
LSBMSB
DPER1 DPER2
LSBMSB
DPOVF
DFEPS
HSWES
N/V
Latch
Preset
Error data (20 bits)
To DFU
Edge
detector
Sequence
controller
↑, ↓
Error data
(16 bits)
Error data
(4 bits)
Preset data
(16 bits)
Preset data
(4 bits)
Counter (20 bits)
IRRDRM3
DPCS1,0
φs
φs/2
φs/4
φs/8
φs = fosc/2
Figure 26.29 Block Diagram of Drum Phase Er ror Detector
Rev. 1.0, 02/00, page 631 of 1141
26.7.3 Regi ster Configur ati on
Table 26. 10 shows the re gister c onfiguration of the drum phase error detector.
Table 26. 10 Register Configurati on
Name Abbrev. R/W Si ze Initi al Value Addr ess
Specified drum phase
preset data registe r 1 DPPR1 W Byte H'F0 H'D03C
Specified drum phase
preset data registe r 2 DPPR2 W Word H'0000 H'D03A
Drum phase error dat a
register 1 DPER1 R/W Byte H'F0 H'D03D
Drum phase error dat a
register 2 DPER2 R/W Word H'0000 H'D03E
Drum phase error
detection con trol register DPGCR R/W Byte H'07 H'D039
Rev. 1.0, 02/00, page 632 of 1141
26.7.4 Register Description
Drum Phase Preset Data Registers (DPPR1, DPPR2)
DPPR1
0
0
1
0
W
2
0
W
3DPPR16DPPR17DPPR18DPPR19
0
4
1
5
1
6
1
7————
———— WW
1
Bit :
Initial value :
R/W :
DPPR2
8
0
9
0
W
10
0
W
11 DPPR8DPPR9DPPR10DPPR11
0
12
0
13
0
14
0
15 DPPR12DPPR13DPPR14DPPR15
WWWW WW
0
Bit :
Initial value :
R/W :
0
0
1
0
W
2
0
W
3DPPR0DPPR1DPPR2DPPR3
0
4
0
5
0
6
0
7DPPR4DPPR5DPPR6DPPR7
WWWW WW
0
Bit :
Initial value :
R/W :
The 20-bit pre set data that defines the specified drum phase is se t in DPPR1 and DPPR2. The 20
bi t s are wei ght e d as foll ows: b it 3 of DPPR1 is the MSB, and bit 0 of DPPR2 is the LSB . When
data is written to DPPR2, the 20-bit preset data, including DPPR1, is loaded i nt o the preset circuit.
Wr ite t o DPPR1 fir st, an d DPPR2 next . The preset data can be calcu late d from the fo ll owing
equation by using H' 8000* a s the refe rence value.
Target phase difference = (reference signal frequency/2) − 6.5H
Drum phase preset da ta = H'80000 - (φs/n × target phase differ ence)
φs: Servo clock frequency in Hz (fosc/2)
φs/n: Clock sourc e of selected counter
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. No
read is valid. If a read is attempted, an undetermined value is read out. DPPR1 and DPPR2 are
initialized to H'F0 and H'0000 by a reset, and in standby mode.
Note: The preset data value is calculated so that the count e r will reach H'80000 when the error
value is zero. W hen the counte r value is latched as error data in the drum phase error data
registers (DPER1 and DPE R2), however, it is converted to a value re ferenced to H'00000.
Rev. 1.0, 02/00, page 633 of 1141
Drum P hase Error Data Registers (DPER1, DP ER2)
DPER1
0
0
1
0
R*/W
2
0
R*/W
3DPER16DPER17DPER18DPER19
0
4
1
5
1
6
1
7————
———— R*/WR*/W
1
Bit :
Initial value :
R/W :
DPER2
8
0
9
0
R*/W
10
0
R*/W
11 DPER8DPER9DPER10DPER11
0
12
0
13
0
14
0
15 DPER12DPER13DPER14DPER15
R*/WR*/WR*/WR*/W R*/WR*/W
0
Bit :
Initial value :
R/W :
Note: * Note that only detected error data can be read.
0
0
1
0
R*/W
2
0
R*/W
3DPER0DPER1DPER2DPER3
0
4
0
5
0
6
0
7DPER4DPER5DPER6DPER7
R*/WR*/WR*/WR*/W R*/WR*/W
0
Bit :
Initial value :
R/W :
DPER1 a nd DPER2 constitute a 20-bit drum phase error data register. T he 20 bit s are weighted a s
follows: bit 3 of DPER1 is the MSB, and bit 0 of DPER2 is the LSB. When the rotational phase is
correct, the da ta H'00000 is latched. Negative data will be latched if the drum leads the correct
phase, and positive data if it lags. Values in DPER1 and DPER 2 are transferred to the digital
filter circuit.
DPER1 a nd DPER a re 20-bit read/write regi sters. Whe n writing da ta to DPER 1 a nd DPER2,
write to DPER1 first, and the n write to DPER2. Only a word access is valid. If a byte access is
attempted, correct ope ration is not guara nteed. DPER1 and DPER2 are initialized to H'F0 and
H'0000 by a reset, and i n sta ndby mode.
See the note on t he drum phase preset data registers (DPPR1 and DPPR2).
Rev. 1.0, 02/00, page 634 of 1141
Drum Phase Error Detection Control Register (DPGCR)
0
1
12 ———
———
1
3
0
4
0
R/W R/W
5
0
6
0
7
R/(W)*
DPOVF
R/W
DPCS0
0
R/W
DPCS1 N/V HSWES
1
Bit :
Initial value :
R/W :
Note: Only 0 can be written.
DPGCR is an 8-bit read/write register that controls the operation of drum phase error detection.
Bits 2-0 are reserved, bit 5 accepts only read a nd 0 wri te.
It is initialized to H'07 by a reset or in stand-by mode.
Bits 7 and 6Cloc k Source Se l ection Bi t (DPCS1, DPCS0): These bits select the clock
supplied to the counter . (φs = fosc / 2)
Bit 7 Bit 6
DPCS1 DPCS0 Description
0φs (Initial value)0
1φs/2
0φs/41
1φs/8
Bit 5Cou n t er Overflow Flag (DPOVF): DPOVF flag indica tes the overflow of t he 20-bit
counter. It is cl eared by writing 0. W rite 0 a fter re a ding 1. Setting has the highest priority in thi s
flag. If a flag set and 0 write occurs simultaneously, the latter is invalid.
Bit 5
DPOVF Description
0 Normal state (Initial value)
1 Indicates that a overflow has occur r ed in t he counter
Bit 4Error Data Latch Signal Selection Bit (N/V): Selects t he latch signal of e rror da ta.
Bit 4
N/V Description
0 HSW (VideoFF) signal ( Initial value)
1 NHSW (NarrowFF) signal
Rev. 1.0, 02/00, page 635 of 1141
Bit 3Edge Sel ection Bit (HSWES): Selects the edge of the error dat a latch signa l (HSW or
NHSW).
Bit 3
HSWES Description
0 Latches at the rising edge (I nitial value)
1 Latches at the falling edge
Bits 2 to 0Reserved: Cannot be modifi ed and are always re ad as 1.
26.7.5 Operation
The drum phase error det ector detects the phase error based on the re ference val ue set in the drum
specified pha se pre set data regist e rs 1 a nd 2 (DPPR1 and DPPR2). The reference va l ues set in
DPPR1 a n d DPPR2 are preset in the counte r by REF30P signal , a nd counte d up by the clock
selected. The latch of the error data can be selected between the rising or falling edge of HSW
(NHSW). The error data detecte d in the e r ror data automatic transmission mode (DFEPS bit of
DFUCR = 0) is sent to the digital filter circuits automatically. In soft transmission mode (DFEPS
bi t of DFUCR = 1), the data wri tt en in DPER1 an d DPER2 is sent to t he digita l fi lt er circ uit . The
error data is signed bina ry. It takes a positive numbe r (+) if t he phase i s behind the specified
phase, a nega tive number (-) if in a dvance of the specifie d phase, or 0 if it had no phase error
(revolving at the spe cified phase). Fi gures 26.30 and 26.31 show examples of operation t o detect
a drum phase error.
Drum Phase E rro r Detect i o n Counter: The drum phase error detection counter stops counting
when an overflow or latch occurs. At the sam e time, it generates an interrupt re quest
(IRRDRM3), and sets the overflow flag (DPOVF) if an ove rflow occurred. T o clear DPOVF,
write 0 after reading 1. If setting the flag and writing 0 take place simultaneously, the latter is
invalid.
Interr upt Reque st : IRRDRM3 is generated by t he HSW (NHSW ) signal latch and the overflow
of the error detection c ounter.
Rev. 1.0, 02/00, page 636 of 1141
Latch Latch
Preset value
Counter
HSW (NHSW)*
REF30P
Preset value
Preset
Note: Edge selectable
Preset
Fi g ure 26.30 Drum Phase Contro l i n Playback Mode (H SW Rising Edge Sele cte d)
Latch Latch
Preset value
Counter
HSW (NHSW)*
VD
REF30P
Preset value
Preset
Note: Edge selectable
Preset
Reset Reset
Figure 26.31 Drum Phase Control in Record Mode (HSW Rising Edge Selected)
Rev. 1.0, 02/00, page 637 of 1141
26.7.6 P hase Comparison
The phase comparison circuit measures the difference of time between the reference signal and the
comparing signal with a digital counter. REF30 signal is used for the reference signal, and HSW
sign a l (VideoFF) or NHSW signal (Na r rowFF) fr om the HSW timin g generator is used for the
comparing signal. In rec ord mode, however, the phase of RE F30 signal is the same as that of the
vertical sync signal (Vsync) bec ause the reference si gnal generat or (RE F30 generator) is reset by
the vertical sync signal (Vsync) in t he video signals.
The error detection c ounter latches data at the rising or falling edge of HSW signal. The di gital
filter circuit performs computation using this data as 20-bit pha se error data. After processing and
adding t he phase e rror data and the speed error dat a from t he drum spee d control system, the
digital filter ci rc uit sends the dat a as the error da ta of the drum system to the PWM modulation
circuit.
Rev. 1.0, 02/00, page 638 of 1141
26.8 Cap st an Sp eed Error Det ect or
26.8.1 Overview
Capstan spee d control holds the ca pstan motor at a constant revolution speed, by measuring the
period of the CFG signal . A digital counter det ects the speed error against a preset value. T he
speed error data is added to phase error data in a digital filter. This filter controls a pulse-wi dth
modulated (PWM) output, which controls the revolution speed and phase of the capstan motor.
The CFG input signal is downl oaded by the comparator circuit, then reshaped into a square wave
by a re shaping circuit, divided by t he CFG di vider, and sent to the speed error detector a s the
DVCFG sig n al .
The speed error detector uses the system clock to measure the period of the DVCFG signal, and
detects the error against a preset data value. The preset data is the value that results from
measuring the DVCFG signal period wit h the c lock signal when the capstan motor is running at
the c o rr ect sp eed .
The error detector operates by l atching a counter val ue whe n it detects an edge of t he DVCFG
signal. The latche d count provides 16 bit s of speed error data for the digital fi l ter to operate on.
The digital filter adds the spe ed error data to pha se error data from the capstan pha se c ontrol
system, then sends the result to the PWM as capstan error data.
Rev. 1.0, 02/00, page 639 of 1141
26.8.2 Block Diagram
Figure 26. 32 shows a block diagram of the capsta n speed error detector.
WW R
UDF
OVF
Lock 2 up
Clear
Latch
Preset
CFVCR
CFRLDR
CFVCRCFPRCFVCR
CFVCRCFVCRCFUCR
CFER
CFRVCR
Error data
(16 bits)
To DFU
DVCFG
CFRUDR
Internal bus
R/W
Internal bus
R/W WR/WR/W
R/W R/W (R)/W
Lock 1 up
S
RF/FQ
S
R
F/F
CFRCS1,0
CF-R/UNR
Lock counter
(2 bits)
Q
S
R
F/F
Q
Lock range
detector
Lock range data (16 bits)
Lock range data (16 bits)
CPCNT
Error data
limiter
control
circuit
CFRFON
CFESS
Error data
(16 bits)
Counter (16 bits)
CFOVF
IRRCAP2
IRRCAP1
CROCKON
To DFU
Preset data (16 bits)
CFCS1,0
φs
φs/2
φs/4
φs/8
Figure 26.32 Block Diagram of Capstan Speed Error Dete ctor
Rev. 1.0, 02/00, page 640 of 1141
26.8.3 Regi ster Configur ati on
Table 26. 11 shows the re gister c onfiguration of the capstan spee d error detector.
Table 26. 11 Register Configurati on
Name Abbrev. R/W Si z e Initi al Value Addr ess
Specified CFG speed
preset data registe r CFPR W Word H'0000 H'D050
CFG speed error dat a
register CFER R/W Word H'0000 H'D052
CFG lock upper dat a
register CFRUDR W Word H'7FFF H'D054
CFG lock lo wer data
register CFRLDR W Word H'8000 H'D056
Capstan speed error
detection con trol register CFVCR R/W Byte H'00 H'D058
Rev. 1.0, 02/00, page 641 of 1141
26.8.4 Register Description
Specified CFG Speed Preset Data Register (CFPR)
8
0
9
0
W
10
0
W
11
0
12
0
W
0
W
1314
0
15
CFPR
12
CFPR
11
CFPR
10
CFPR
9
CFPR
8
0
W
CFPR
15
WWW
CFPR
14
CFPR
13
Bit :
Initial value :
R/W :
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7
CFPR
4
CFPR
3
CFPR2 CFPR
1
CFPR
0
0
W
CFPR
7
WWW
CFPR
6
CFPR
5
Bit :
Initial value :
R/W :
The 16-bit pre set data that defines the specified CFG speed i s set in CFPR. When data is written,
the 16-bit pre set data is sent to the preset c ircuit. T he preset data can be calculate d from the
following e quation by usi ng H'8000* as the refe rence value.
φs/n
CFG speed preset data = H'8000 − ( − 2)
DVCFG frequency
φs: Servo c lock fre quency in Hz (fOSC/2)
DVCFG fre quency: In Hz
The constant 2 is the preset interval (se e figure 26.33).
φs/n: Clock source of the selected counte r
CFPR is a 16-bit write-only register. Onl y a word acces is valid. If a byte access is attempted,
correct ope ration i s not guaranteed. CFPR is initialized to H' 0000 by a reset.
Note: The preset data value is calculated so that the count e r will reach H'8000 when the error i s
zero. When the counter val ue is la tched as error data in the CFG spee d error data regi ster
(CFER), however, it i s conve rted to a val ue referenced to H'0000.
Rev. 1.0, 02/00, page 642 of 1141
CFG Speed Error Data Register (CFER)
8
0
9
0
R*/W
10
0
R*/W
11
0
12
0
R*/W
0
R*/W
1314
0
15 CFER12 CFER11 CFER10 CFER9 CFER8
0
R*/W
CFER15
R*/WR*/WR*/W
CFER14 CFER13
Bit :
Initial value :
R/W :
Note: Note that only detected error data can be read.
0
0
1
0
R*/W
2
0
R*/W
3
0
4
0
R*/W
0
R*/W
56
0
7CFER4 CFER3 CFER2 CFER1 CFER0
0
R*/W
CFER7
R*/WR*/WR*/W
CFER6 CFER5
Bit :
Initial value :
R/W :
CFER is a 16-bit re ad/write regi ster that stores 16-bit CFG speed error data. W hen the speed of
the capsta n motor is c orrect, the data latched i n CFE R is H' 0000. Negat i ve data will be latched if
the speed is faster than the specified speed, and positive data if the speed is slower than the
specified speed. The CFER value is sent to the digital filter either automatically or by software.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed.
CFER is initialized t o H'0000 by a re set, and in module stop mode and standby mode.
See the note on the specified CFG speed preset data register (CFPR) in section 26.8.4.
CFG Lock UPPE R Data Register ( CFRUDR)
8
1
9
1
W
10
1
W
11
1
12
1
W
1
W
1314
1
15
CFRUDR
12
CFRUDR
11
CFRUDR
10
CFRUDR
9
CFRUDR
8
0
W
CFRUDR
15
WWW
CFRUDR
14
CFRUDR
13
Bit :
Initial value :
R/W :
0
1
1
1
W
2
1
W
3
1
4
1
W
1
W
56
1
7
CFRUDR
4
CFRUDR
3
CFRUDR
2
CFRUDR
1
CFRUDR
0
1
W
CFRUDR
7
WWW
CFRUDR
6
CFRUDR
5
Bit :
Initial value :
R/W :
CFRUDR is a 16-bit writ e -only register used to set the loc k range on the UPPE R side when
ca p sta n speed lock is dete ct e d, and to set the limi t val ue on the UPPER side when l imit er functio n
is in use.
When lock is being detected, if the capstan speed is detected within the lock range, the lock
counter which ha s been set by CFRCS1 and CFRCS0 bit s of CFVCR regi ster decrements the
count. If the set value of CFRCS1 and CFRCS0 matc he s the numbe r of times of occ urrence of
locking, the computation of the digital filter in the capstan phase system can be controlled
automatically. Also, if the CFG speed error data exceeds the CFRUDR value when the limiter
function is in use, the DFRUDR value ca n be used as the data for computation by the digital filter.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. A
read is i nvalid. If a read is attempted, an undet ermined val ue is rea d out . It i s initialized t o
H'7 FFF by a reset, or in stand -by or module - stop mo de.
Rev. 1.0, 02/00, page 643 of 1141
CFG Lock LOWER Data Register (CFRLDR)
8
0
9
0
W
10
0
W
11
0
12
0
W
0
W
1314
0
15
CFRLDR
12
CFRLDR
11
CFRLDR
10
CFRLDR
9
CFRLDR
8
1
W
CFRLDR
15
WWW
CFRLDR
14
CFRLDR
13
Bit :
Initial value :
R/W :
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7
CFRLDR
4
CFRLDR
3
CFRLDR
2
CFRLDR
1
CFRLDR
0
0
W
CFRLDR
7
WWW
CFRLDR
6
CFRLDR
5
Bit :
Initial value :
R/W :
CFRLDR i s a 16-bit write-only register used t o set the lock ra nge on the LOWE R side when
capstan speed lock is detected, and to set the limit value on LOWER side when limiter function is
in use.
When lock is being detected, if the drum speed is detected within the lock range, the lock counter
that has been set by CFRCS 1 and 0 bits of CFVCR register decrements the count. If the set value
of CFRCS 1 and 0 matches the number of times of occurrence of locking, the computation of the
digital filter in the drum phase system can be controlled automatically. Also, if the CFG speed
error data is under the CFRLDR val ue when the limiter funct i on i s in use , the CFRLDR value can
be used as the data for computation by the digital filter.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. No
read is vali d. If a read is attempted, an undetermined value is rea d out. It is initialized to H'8000
by a re set, or i n stand-by or module-stop mode.
Capstan Spee d Error Detect i o n Control Register (CFVCR)
0
0
1
0
(R)
*2
/W
2
0
R/W
3
0
4
0
R/W
0
R/(W)
*1
56
0
7CFRFON CF-R/UNR CPCNT CFRCS1 CFRCS0
0
R/W
CFCS1
(R)
*2
/WRR/W
CFCS0 CFOVF
Notes:
Bit :
Initial value :
R/W :
1. Only 0 can be written.
2. If read-accessed, the counter value is read out.
CFVCR is an 8-bit read/write registe r that controls t he opera tion of capstan spe ed error detection.
Bit 3 accepts only read, and bit 5 accepts only read and 0 write. It is initialized to H'00 by a reset,
or in stand-by or module-stop m ode.
Rev. 1.0, 02/00, page 644 of 1141
Bits 7 and 6Clock Source Selec t ion Bit s (CFCS1, CFCS0): CFCS1 and CFCS0 se lect the
clock to be supplied to the counter . (φs = fosc/2)
Bit 7 Bit 6
CFCS1 CFCS0 Description
0φs (Initial value)01φs/2
0φs/41 1φs/8
Bit 5Cou n t er Overflow Flag (CFOVF): CFOVF flag indica te s ove r flo w of the 16-bit cou nte r.
It is cleared by writing 0. Write 0 after reading 1. Setting has the highest priority in this flag. If a
flag set and 0 write occurs simultaneously, the latter is invalid.
Bit 5
CFOVF Description
0 Normal st ate. ( I nit ial value)
1 Indicates that a overflow has occur r ed in t he counter.
Bit 4Error Data Limit Function Selection Bit (CFRFON): Enables t he error data limit
function. (Limit va l ues a re the values set in the lock range data re gister (CFRUDR, CFRLDR)).
Bit 4
CFRFON Description
0 Disa b le s limit func tion. (In itial value )
1 Enables limit function.
Bit 3Capstan Lock Flag (CF-R/UNR): Sets a flag if an underflow occurred in the capstan lock
counter.
Bit 3
CF-R/UNR Description
0 Indicates that the capstan speed system is not locked. ( I nitial value)
1 Indicates that the capstan speed system is locked.
Rev. 1.0, 02/00, page 645 of 1141
Bit 2Capstan Phase System Fi lter Computation Automati c Start Bit (CPCNT): Enables the
filter computation of the pha se system if an underfl ow occurred i n the capstan lock counte r.
Bit 2
CPCNT Description
0 Disables the filter com putation by detection of the capstan lock. ( I nit ial value)
1Enables t he filter computation of t he phase system when capstan lock is
detected.
Bits 1 and 0Capstan Lock Counte r Setting Bits (CFRCS1, CFRCS0): Sets the number of
times to detect caps tan locks (D V C F G h as b een det ec ted in the rag e set b y the lo ck range data
register). The capstan lock flag is set when the specified number of capstan lock is detected. If the
DVCFG signal is detected outside the lock range after data is written in CFRCS1 and CFRCS0,
the data will be stored in the lock counter.
Note: If CFRCS1 or CFRCS0 is read-accessed, the counter value is read out. If bit 3 (capstan
lock flag) i s 1 and the c apstan l oc k counter's value is 3, it indicates t hat the capstan spee d
system is locked. The capst a n lock counter stops until l ock is released after underflow.
Bit 1 Bit 0
CFRCS1 CFRCS0 Description
0 Underflow occur s after lock was detected once(I nit ial value)
0
1 Underflow occur s after lock was detected twice
0 Underflow occur s after lock was detected three times11 Underflow occur s after lock was detected four times
Rev. 1.0, 02/00, page 646 of 1141
26.8.5 Operation
The capsta n speed error detector de tects the spee d error based on the re ference val ue set in the
CFG specified speed preset register (CFPR). The reference value set in CFPR is preset in the
counter by the DVCFG signal, and the c ounter de crements the count by the sel ected cl ock. T he
timing of t he counter presetting and the error data latching can be selected be t ween the rising or
falling edge of DVCFG signal. See DVCFG Control Regi ster (CDVC) in se ction 26.14.3, CFG
Frequency Divider. The error data detected is sent to digital filter circuit. The error data is signed
binaries. The data takes a positive number (+) if the speed is slower than the specified speed, a
negative number (-) if the speed is faster, or 0 if it had no error (revolving at the specified speed).
Figure 26. 33 shows an exa m ple of operation to detect t he capstan speed.
Setting the Error Data Limit: A limit can be set to the error data sent to the di gital filter circuit
using the CFG lock data regi ster (CFRUDR, CFRL DR). Se t the upper limit of t he error data in
CFRUDR and the lower limit in CFRLDR, and write 1 in CFRFON bit. If the error dat a is outside
the limit range, the CFRLDR value is sent to the digital filter circuit if a negative number is
latched, or the CFRUDR value if a positive number is latched, as a limit value. Be sure to turn off
the limit setting (CFRFON = 0) when you set the limit value. If the limit was set with the limit
set ti n g on (CFRFON = 1), re sult of comp utatio n is not assu red.
Lock De tection: If an error data is det ected within the l ock range set in the loc k data register, the
capstan lock flag (CF-R/UNR) is set by the number of the times of locking set by CFRCS1 and
CFRCS0 bit s, and a n interrupt is requested (IRRCAP2) at the sa me time. The number of the
occurrence of locking (once to 4 times) before the flag is set can be specified. Use CFRCS1 and
CFRCS0 bit s for t hi s purpose. The on/off sta te of t he phase system digital filter com putation ca n
be contr oll ed automat ic ally by the status o f loc k detec ti o n when bit 5 (CPHA bit ) of the cap sta n
system digi tal filter control re gi ster (CFIC) is 0 (phased system digital fil ter computation off) and
DPCNT bit i s 1.
Capstan Sy st e m Speed Err or Detect ion Co unter : The capstan system speed error detection
counter stops the counter and set s the overflow flag (CFOVF) whe n an overflow occ urs. At the
same time, it generates an interrupt request (IRRCAP1). T o clear CFOVF, writ e 0 after rea ding 1.
If setting the flag and writing 0 take place simultaneously, the latter is invalid.
Interr upt Reque st : IRRCAP1 i s generated by the DVCFG signal latch and the ove rflow of the
error detection c ounter. IRRCAP2 is generated by dete c tion of l ock (after the detection of t he
specified number of times of locking).
Rev. 1.0, 02/00, page 647 of 1141
–value +value
Specified speed value
Latch data 0
(no error)
Preset value
Preset period
(2 counts)
Counter
Error data
latch signal
(DVCFG)
Preset data
load signal
Figure 26.33 Example of the Capstan Speed Error Detection
Rev. 1.0, 02/00, page 648 of 1141
26.9 Capstan P hase Error Detector
26.9.1 Overview
The capstan phase control system must start operation after the capstan motor has reached the
specified spee d by t he speed c ontrol system. The capstan pha se control system ope rates as
follows in record/playba ck mode:
• Record m ode: Control s the tape runni ng so that it ma y run at a specified speed together wi t h
the sp eed contr ol syste m.
• Playback mode: Controls the tape running so that t he rec orded track ma y be tra ced correctly.
Any error deviated from the re ference phase is detected by the digi tal counter. This phase error
data and the speed error dat a is proce ssed and added by the digital fi lter circuit to control the
PWM out put. The pha se and speed of the capstan, in turn, is control this PWM output.
The control signal of t he capsta n phase cont rol in t he record mode differ from that in playback
mode. In record mode, the c ontrol i s perform e d by t he DVCFG2 signal which is gene rated by
dividing the frequencies of t he refe rence signal (RE F30P or CREF) a nd the CFG signal. In
playback m ode, it is performed by divided rising signal (DVCTL) of the reference signal
(CAPREF30) a nd t he playback c ont rol pulse (PB-CTL ).
The refere nce signa l in rec ord and playback modes a re as follows:
• Record m ode: 1/2Vsync signal extracted from the video signal to be re corded.
• Playback mode: Signal ge nerated by dividing the PB-CTL signal (DVCTL ) at its rising edge.
26.9.2 Block Diagram
Figure 26. 34 shows the block diagram of the capstan phase error detector.
Rev. 1.0, 02/00, page 649 of 1141
R/W R/W R/W R/W R/W
R/W
CREF
REF30P
CAPREF30
RECREF
DVCFG2
DVCTL
CPGCR
R/W
CR/RF
CPGCR DFUCR
CPGCRCPPR1 CPPR2
R/(W)
S
R
F/F
Q
WW
Internal bus
Internal bus
OVF
LSBMSB
CPER1 CPER2
LSBMSB
CPOVF
CFEPS
SELCFG2
R/W
CTLM
R/P ASM
Latch
Preset
Error data (20 bits)
To DFU
Sequence
controller
Error data
(16 bits)
Error data
(4 bits)
Preset data
(16 bits)
Preset
PB: X value + TRK value = CAPREF30
REC: REF30P or CREF
Latch
PB : DVCTL
REC : DVCFG2Ê
Preset data
(4 bits)
Counter (20 bits)
IRRCAP3
CPCS1,0
φs
φs/2
φs/4
φs/8
φs = fosc/2
Figure 26.34 Block Diagram of Capstan Phase Error Detector
Rev. 1.0, 02/00, page 650 of 1141
26.9.3 Regi ster Configur ati on
Table 26. 12 shows the re gister c onfiguration of the capstan phase error de tector.
Table 26. 12 Register Configurati on
Name Abbrev. R/W Si z e Initi al Value Addr ess
Specified Capstan phase
preset data registe r 1 CPPR1 W Byte H'F0 H'D05C
Specified Capstan phase
preset data registe r 2 CPPR2 W Word H'0000 H'D05A
Capstan phase error data
register 1 CPER1 R/W Byte H'F0 H'D05D
Capstan phase error data
register 2 CPER2 R/W Word H'0000 H'D05E
Capstan phase error
detection con trol register CPGCR R/W Byte H'07 H'D059
Rev. 1.0, 02/00, page 651 of 1141
26.9.4 Register Description
Specified Capstan Phase Preset Data Registers (CPPR1, CPPR2)
CPPR1
0
0
1
0
W
2
0
W
3
0
4
1
5
1
6
1
7—CPPR19 CPPR18 CPPR17 CPPR16———
———— WW
1
Bit :
Initial value :
R/W :
CPPR2
8
0
9
0
W
10
0
W
11 CPPR8CPPR9CPPR10CPPR11
0
12
0
13
0
14
0
15 CPPR12CPPR13CPPR14CPPR15
WWWW WW
0
Bit :
Initial value :
R/W :
0
0
1
0
W
2
0
W
3CPPR0CPPR1CPPR2CPPR3
0
4
0
5
0
6
0
7CPPR4CPPR5CPPR6CPPR7
WWWW WW
0
Bit :
Initial value :
R/W :
The 20-bit pre set data that defines the specified c apstan pha se is set in CPPR1 and CPPR2. The
20 bits are weighted as follows: bit 3 of CPPR1 is the MSB. Bit 0 of CPPR2 is the LSB. When
CPPR2 is written to, the 20-bit pre set data, i ncluding CPPR1, is loade d into t he preset circuit.
Write to CPPR1 first, and CPPR2 next. The preset data can be calculated from the following
equation by using H' 80000* a s the refe rence value.
Target phase difference = Reference signal frequency/2
Capstan pha se preset data = H'80000 − (φs/n × targ et ph ase diff erence)
φs: Servo clock frequency in Hz (fosc/2)
φs/n: Clock sourc e of selected counter
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. No
read is valid. If a read is attempted, an undetermined value is read out. CPPR1 and CPPR2 are
initialized to H'F0 and H'0000 by a reset, and in standby mode.
Note: The preset data value is calculated so that the count e r will reach H'80000 when the error is
zero. When the counter val ue is la tched as error data in the capstan phase error data
registers (CPER1 and CPER2), however, it is converted to a value refe renced to H'00000.
Rev. 1.0, 02/00, page 652 of 1141
Capstan P hase Er r or Data Registers (CPER1, CPER2)
0
0
1
0
R*/W
2
0
R*/W
3
0
4
1
5
1
6
1
7————
———— R*/WR*/W
1
Bit :
Initial value :
R/W :
CPER19 CPER18 CPER17 CPER16
8
0
9
0
R*/W
10
0
R*/W
11 CPER8CPER9CPER10CPER11
0
12
0
13
0
14
0
15 CPER12CPER13CPER14CPER15
R*/WR*/WR*/WR*/W R*/WR*/W
0
Bit :
Initial value :
R/W :
Note: Note that only detected error data can be read.
0
0
1
0
R*/W
2
0
R*/W
3CPER0CPER1CPER2CPER3
0
4
0
5
0
6
0
7CPER4CPER5CPER6CPER7
R*/WR*/WR*/WR*/W R*/WR*/W
0
Bit :
Initial value :
R/W :
CPER1 and CPER2 constitute a 20-bit c apstan phase error data re gister. The 20 bi t s are weighted
as follows: bit 3 of CPER1 is the MSB. Bit 0 of CPER2 is the LSB. When the rotational phase is
correct, the da ta H'00000 is latched. Negative data will be latched if the pha se leads t he corre ct
phase, and positive data if it lags. Values in CPER1 and CPER 2 are transferred to the digital
filter circuit.
CPER1 and CPER are 20-bit read/write registers. When writing data to CPER 1 and CPER2,
write to CPER1 first, and then write to CPER2. Only a word access is valid. If a byte access is
attempted, correct ope ration is not guara nteed. CPER1 and CPER2 are initialized t o H'F0 and
H'0000 by a reset, and i n sta ndby mode.
See the note on the capstan phase preset data registers (CPPR1 and CPPR2) in section 26.9.4.
Rev. 1.0, 02/00, page 653 of 1141
Capstan Phase Err or Detect ion Co ntro l Regist er (CPGCR)
0
1
12 ———
———
1
3
0
4
0
R/W
5
0
6
0
7
R/WR/(W)*
CPOVF
R/W
CPCS0
0
R/W
CPCS1 CR/RF SELCFG2
1
Note: Only 0 can be written
Bit :
Initial value :
R/W :
CPGCR is an 8-bit read/write registe r that controls t he opera tion of capstan phase error detection.
Bits 2-0 are reserved, and bit 5 accepts only read a nd 0 write.
It is initialized to H'07 by a reset or in stand-by mode.
Bits 7 and 6Cloc k Source Se l ection Bi t (CPCS1, CPCS0): These bits select the clock
supplied to the counter . (φs = fosc / 2)
Bit 7 Bit 6
CPCS1 CPCS0 Description
0φs (Initial value)0
1φs/2
0φs/41 1φs/8
Bit 5Cou n t er Overflow Flag (CPOVF): CPOVF flag indicates t he overflow of the 20-bit
counter. It is cl eared by writing 0. W rite 0 a fter re a ding 1. Setting has the highest priority in thi s
flag. If a flag set and 0 write occurs simultaneously, the latter is invalid.
Bit 5
CPOVF Description
0 Nor ma l sta te (Initial value )
1 Indicates that a overflow has occur r ed in t he count er
Bit 4Preset Signal Selection Bit (CR/RF): Se lects the preset signal.
Bit 4
CR/RF Description
0 Presets REF30P (Initial value)
1 Presets CREF signal
Rev. 1.0, 02/00, page 654 of 1141
Bit 3Latch Signal Selection Bit (SELCFG2): Selects the counter preset signal and the error
da ta lat c h sig nal dat a in PB (ASM) mode .
Bit 3
SELCFG2 Description
0 Presets CAPREF30 signal; latches DVCTL signal (I nit ial value)
1 Presets REF30P (CREF) signal; latches DVCFG2 signal
Bits 2 to 0Reserved: Cannot be modifi ed and are always re ad as 1.
26.9.5 Operation
The capsta n phase error det ector detects the phase error based on the re ference value set in the
capstan speci fied phase preset data registers 1 and 2 (CPPR1 and CPPR2). The reference values
set in CPPR1 and CPPR2 are preset in the counter by REF30P (CREF) signal or CAPREF signal,
and count ed up by the cl oc k selected. The latching of the error data is performed by DVCTL or
DVCFG2.
The error data detected in the error data automatic transmission mode (CFEPS bit of DFUCR = 0)
is se nt to the digit al filter circui t automat ic al l y. In soft transmi ssi o n mode (CFEPS bit of DFUCR
= 1), the da ta written in CPER1 and CPPR2 is sent to the digital filt e r circuit. The error data is
signed binary. It takes a positive number (+) if the phase is behind the specified phase, a negative
number (-) if in a dvance of the specified pha se, or 0 if it ha d no phase error (revolving at the
specified pha se). Figures 26.35 and 26.36 show examples of operation to detect a capstan phase
error.
Capstan Phase Err or Detect ion Co unter : The capstan phase error detection counter stops
counting when an overflow or latch occurs. At the same time, it generates an i nterrupt request
(IRRCAP3), and sets the overflow flag (CPOVF) if overflow occurred. To clear CPOVF, write 0
after reading 1. If setting the flag and writing 0 take place simultaneously, the latter is invalid.
Interr upt Reque st : IRRCAP3 is generated by the DVCTL or DVCFG2 signal latch and the
overflow of the error dete ction counter.
Rev. 1.0, 02/00, page 655 of 1141
Latch Latch
Preset value
Counter
PB-CTL
CAPREF30
DVCTL
or
DVCFG2
Preset Preset
Figure 26. 35 Cap stan Ph a s e C o n t rol in Playback Mo d e
Latch Latch
Preset value
Counter
DVCFG2
REF30P
or
CREF
Preset Preset
Figure 26. 36 Cap stan Ph a s e C o n t rol in Record Mode
Rev. 1.0, 02/00, page 656 of 1141
26.10 X- Value and Tracking Adjustment Circuit
26.10.1 Overview
To maintain c ompatibility wit h ot he r VCRs, an on-chi p adjustm ent circuit adj usts the phase of the
reference signal (internal re ference signal (REF30) or external re ference si gnal (EXCAP)) during
playback. Bec ause of manufacturing tolerances, the physical distance between the video head and
control hea d (the X-value: 79. 244 mm) may va ry from set t o set, so when a tape that was recorde d
on a different set is played back, the phase of the reference signal may need to be adjusted. The
adjustment can be made by a register setting. The same setting can adjust the rotational phase of
the capstan motor to maintain positional alignment (tracking alignment) of the video head with the
recorded tracks in autotracking, or when tracks that were recorded with an EP head are traced by a
wider head. These t racking adjustments can be made by the acquisition of the envel ope signal by
the A/D converter.
26.10.2 Block Diagram
The adjustm ent circuit consists of a 10-bit counter c l ocked by the system clock (φs or φs/2), a nd
two down-c ounters with l oad regi sters. Individual se tting of X-value adjustment can be made by
X-value data register (XDR) and tracking adjustment by TRK data register (TRDR). The
reference signal clears the 10-bi t counter and sets the load re gister va lue in t he down-counte r with
two load registers. After the adjuste d refere nce signal is generated, clock supply stops and the
circuit halts unt il the next reference si gnal is i nput. RE F30 signa l can be divided a s nec e ssary.
Figure 26. 37 shows a block diagram.
Rev. 1.0, 02/00, page 657 of 1141
R*/W
Note: When DVREF1 and DVREF0 are read, values in the down counter (2 bits) are readout.
φs = fosc/2
φs
φs /2
EXCAP
REF30P
XTCR
W W
XCS
XTCR
W
AT/MU
ASM REC/PB
XTCR
W
TRK/X
S
R
Q
S
RQ
Internal bus
Internal bus
DVREF1, 0
CAPRF
EXC/REF
WW
XTCRXTCR
Down counter
Edge
selection
,
(2 bits)
Counter
(10bit)
CAPREF30
REF30X
W
X-value data
register
XDR
(12 bits)
TRK value data
register
TRDR
(12 bits)
Down counter
(12 bits)
(12 bits)
Down counter
Figure 26.37 Block Diagram of X-Val ue Adjustment Circuit
Rev. 1.0, 02/00, page 658 of 1141
26.10.3 Register Description
Register Confi g urat i o n
Table 26. 13 shows the re gister c onfiguration of X-value correction and t racking correc tion
circuits.
Table 26. 13 Register Configurati on
Name Abbrev. R/W Si z e Initi al Value Addr ess
X-value and TRK-value
control register XTCR R/W Byte H'80 H'D074
X-value data register XDR W Word H'F000 H'D070
TRK-value data regist er TRDR W Word H'F000 H'D072
X-Val ue and TRK-Value Control Regi ster (XTCR)
0
0
1
0
R*/W
2
0
W
3
0
4
0
W
5
0
6
0
7
—
—R*/WWW
AT/MU
W
CAPRF TRK/X EXC/REF XCS DVREF1 DVREF0
1
Bit :
Initial value :
R/W :
XTCR is an 8-bit re gister to determine the X-val ue and TRK-value correction circuits. Bits 6 to 2
are write-only bits. No read is valid. If a read is attempted, an undetermined value is read out.
Bits 1 and 0 are read/write bits. Only a byte access is valid for XTCR. If a word access is
attempted, correct ope ration is not guara nteed.
It is ini tialized to H'80 by a reset, or in stand-by or module stop m ode.
Bit 7Reserved: Cannot be modified and is always read as 1.
Bit 6External Sync Signal Edge Selection Bit (CAPRF): Selects the EXCAP edge when a
selection is made to generate external sync signals.
Bit 6
CAPRF Description
0 Signal generated at the rising edge of EXCAP. (I nitial value)
1 Signal generated at both edges of EXCAP.
Rev. 1.0, 02/00, page 659 of 1141
Bit 5Capstan Phase Corr ection Auto/Manual Sel ection Bit (AT/
08
08
): Selects whether the
generation of the c orrection refe rence signal (CAPREF30) for c apstan pha se control is c ontrolled
au t omat ic al l y or manually depen ding on th e stat u s of the ASM and REC/
3%
bits of CTL m ode
register.
Bit 5
AT/
08
08
Description
0 Manual mode (Init ial value)
1 Auto mode
Bit 4Capstan Phase Corr ection Regi ster Se lection Bit (TRK/
;
;
): De ter min es the method to
generate the CAPREF30 signal when AT/
08
bit i s 0.
Bit 4
TRK/
;
;
Description
0 Generates CAPREF30 only by the set value of XDR. ( I nit ial value)
1 Generates CAPREF30 by the set value of XDR and TRDR.
Bit 3Reference Signal Selection Bit (EXC/REF): Selects the reference signal to generate the
correction refere nce signal (CAPREF30).
Bit 3
EXC/REF Description
0 Generates the signal based on REF30P. (I nit ial value)
1 Generates the signal based on the external ref erence signal.
Bit 2Clock So urce Sel ec tion Bit (XCS): Selects the c l ock source to be supplied t o the 10-bit
counter.
Bit 2
XCS Description
0φs (Initial value)
1φs/2
Rev. 1.0, 02/00, page 660 of 1141
Bits 1 and 0REF30P Divisi o n Ratio Selec tion Bit ( DVREF1, DVREF0 ): Se lects th e d iv is ion
value of REF30P. If it is read-accessed, the counter value is read out. (The selected division
value is set by the UDF of the counter.)
Bit 1 Bit 0
DVREF1 DVREF0 Description
0 Division in 1 (I n itial value)01 Division in 2
0 Division in 31
1 Division in 4
X-Value Data Re gi ster (XDR)
1
13
1
14
1
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
1
WWWWWW
12
————
————
XD1 XD0XD3 XD2XD5 XD4XD7 XD6XD9 XD8
XD11 XD10
000000
Bit :
Initial value :
R/W :
The X-va lue data register (XDR) is an 16-bit writ e-only re gister. No read is valid. If a read is
attempted, an undetermined value is read out. Only a word access is valid. If a byte access is
attempted, correct ope ration is not guara nteed.
Set an X-value correction data to XDR, except a value which is beyond the cycle of the CT L
pulse. If AT/
08
= 0, TRK/
;
= 0 is set, CAPREF30 can be generated only by setting the XDR.
Set an X-value and TRK correction value in PB mode, and X- value in REC mode.
It is ini tialized to H'F000 by a reset, or in stand-by or modul e stop mode.
TRK- Va l ue Data Regi ster (T RDR)
1
13
1
14
1
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
1
WWWWWW
12
————
————
TRD1 TRD0TRD3 TRD2TRD5 TRD4TRD7 TRD6TRD9 TRD8
TRD11 TRD10
000000
Bit :
Initial value :
R/W :
The TRK-value data regist e r (TRDR) is an 16-bit write-only register. No read is val id. If a read is
attempted, an undetermined value is read out. Only a word access is valid. If a byte access is
attempted, correct ope ration is not guara nteed.
Set an T RK-value correc tion data to TRDR, except a value which is beyond the cycle of the CTL
pulse. It is initialized to H'F000 by a reset, or in stand-by or module st op mode.
Rev. 1.0, 02/00, page 661 of 1141
26.11 Digital Filters
26.11.1 Overview
The digital filters required in servo control make extensive use of multiply-accumulate operations
on signed integers (error data) and coefficients. A filter computation circuit (digital filter
computation circuit) is provided in on-chip ha rdware to reduce the load on software, and to
improve proce ssing efficiency. Figure 26.38 shows a block diagram of the fi lter circuit
configuration.
The filter circuit includes a high-sp ee d 24-bi t × 16- b it multip lier-accumulato r, an ari thmetic
buffer, and an I/O proce ssor. T he digital filter computations are ca rried out by the high-speed
multiplier-accumulator. The arithmetic buffer stores coefficients and gain constants needed in the
filter computations, whi ch are refere nced by t he high-speed multiplier-accumulator.
The I/O processor is activated by a fre quency gene rator signa l, and dete rmines what operation i s
carried out . Whe n activated, i t reads t he spe e d error and phase error from the speed and phase
error detectors and sends them t o the accumulator.
When the filter computation is completed, the I/O processor reads the result from the accumulator
and sends it to a 12-bit PWM. At this time, the accumulation result gain can be controlled.
Rev. 1.0, 02/00, page 662 of 1141
26.11.2 Bloc k Diagram
Data bus
Accumulator
End
Start
Error latch signal
Error data
(from the error detector) Motor control data
(to PWM circuit)
Buffer/
register
select &
R/W
Address bus
Error check Accumulation
controller
LA (16 bits),
lower accumulator
UA (32 bits),
upper accumulator
MD (32 bits),
multiplied data
Data
shifter
Accumulation
sequence circuit
Buffer circuit
A, B, G, etc.
Write-only
Read-only
Accumu-
lator
Calculation
buffer
Coefficient
register
Constant
register
Sign
controller
Figure 26.38 Block Diagram of Digital Fi l ter Circ uit
Rev. 1.0, 02/00, page 663 of 1141
16
24 8
Z -1
-+
*
Usn-1 GKs
+
+
Ofs
+
-
+
+
24 8
Ws
24 8
VBs
14 4
24 8
XAs
24 8
XSn 24 8
VSn 24 8
DFUout 12
24 8
αEs
Error detector
á Add 0s to 8 bits after the decimal point
á Add the same 8-bit value as MSB
Right-bit shift of the decimal point
along with Go PWM
Note: Go = ×64, ×32 are optional.
Go = ×64, ×32, ×16, ×8,×4, ×2
24 8
Usn
16
DZs11 to 0
CZs11 to 0
DBs15 to 0
CBs15 to 0
16
DGKs15 to 0
CGKs15 to 0 DOfs15 to 0
COfs15 to 0
DFIC
CFIC
DFER15 to 0
CFER15 to 0
DAs15 to 0
CAs15 to 0
BsAs
GS KS Go
16
Es PWM
Digital filter
control
register
Speed
system
24 8
Z -1
-+
*
1
Upn-1 GKp
+
+
OfP
+
-
24 8
Tp
24 8
VBp
24 8
XAp
24 8
VPn
24 8
Y
Phase direct test output
Notes 1. See figure 26.42, Z
-1
initialization circuit.
12
24 8
αEp
Error detector
á Add 0s to 8 bits after the decimal point
á Add the same 8-bit value as MSB
PWM
24 8
Upn
DZp11 to 0
CZp11 to 0
DBp15 to 0
CBp15 to 0
16
16
DGKp15 to 0
CGKp15 to 0 DOfp15 to 0
COfp15 to 0
DPER19 to 0
CPER19 to 0
DAp15 to 0
CAp15 to 0
BPAP
GP KP
20
16 16
Ep PWM
PION
*2
á DFUCR
á OPTION
CP/DP
Phase
system
Overflows during accumulation are ignored, and
values below the decimal point are always omitted.
2. Gain control is disabled during phase output.
Figure 26.39 Digital Filter Repr esentation
Rev. 1.0, 02/00, page 664 of 1141
26.11.3 Arithmetic Buffer
This buffe r stores c omputational data used i n the di gital filters. See table 26.14. Write access is
limited to the gain and coefficient data (Z-1). T he other data is use d by hardware. None of the da ta
can be read.
Table 26. 14 Arithmetic Buffer Re gister Confi guration
Buffer Data Length
Arithmetic
Data Gain or
Coefficient Processing
Data 16 bit s 16 bits 16 bit s
Phase
system Ep
Upn
Upn-1 (Zp-1)
Vpn
Tp
Y
Ap
Bp
GKp
Ofp
Ap × Epn
Bp × Vpn
Speed
system Es
Xsn
Usn
Usn-1 (Zs-1)
Vsn
Ws
As
Bs
GKs
Ofs
As × Xsn
Bs × Vsn
Error
output PWM
Legend: Valid bits ↑
Non-existent bit s Decimal point
Rev. 1.0, 02/00, page 665 of 1141
26.11.4 Register Configur ati on
Table 26.15 shows the register configuration of the digital circuit.
Table 26. 15 Register Configurati on
Name Abbrev. R/W Si z e Initi al Value Address
Capstan phase gain
constant CGKp W Word Undetermined H'D010
Capstan speed gain
constant CGKs W Word Undetermined H'D012
Capstan phase coef ficient A CAp W Word Undetermined H'D014
Capstan phase coef ficient B CBp W Word Undetermined H'D016
Capstan speed coef ficient A CAs W Wor d Undet ermined H'D018
Capstan speed coef ficient B CBs W Wor d Undet ermined H'D01A
Capstan phase offset COf p W W or d Undetermined H'D01C
Capstan speed offset COfs W W or d Undetermined H'D01E
Drum phase gain constant DGKp W Word Undet ermined H'D000
Drum speed gain constant DGKs W Word Undetermined H'D002
Drum phase coeff icient A DAp W W or d Undet ermined H'D004
Drum phase coeff icient B DBp W W or d Undet ermined H'D006
Drum speed coeff icient A DAs W Word Undetermined H'D008
Drum speed coeff icient B DBs W Word Undetermined H'D00A
Drum phase offset DO f p W Word Undet ermined H'D00C
Drum speed offset DO fs W Word Undetermined H'D00E
Drum system speed delay
init ializ a tion regist er DZs W Word H'F000 H'D020
Drum system phase delay
init ializ a tion regist er DZp W Word H'F000 H'D022
Capstan system speed delay
init ializ a tion regist er CZs W Word H'F000 H'D024
Capstan system phase delay
init ializ a tion regist er CZp W Word H'F000 H'D026
Dru m system digita l filt er
control register DFIC R/W Byte H'80 H'D028
Capstan system digital filter
control register CFIC R/W Byte H'80 H'D029
Digit al filt er contr o l regist er DFUCR R/ W Byte H'C0 H'D02A
Rev. 1.0, 02/00, page 666 of 1141
26.11.5 Register Description
Gain Constants (DGKp, DGKs, CGKp, CGKs)
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
Bit :
Initial value :
R/W :
Note: * Initial value is uncertain.
These registers a re 16-bit write-only buffers that set accumulation gain of t he digital filter. Only a
word access i s valid. Ac c umulation ga i n can be set to ga in 1 val ue as ma ximum value. If a byte
access is attempted, correct ope ration is not guara nteed. If a read is attempted, an undetermined
value is read out.
These registers are not initialized by a reset or in standby mode. Be sure to write data in them
before processing starts.
In the digital filter, output gain and accumulation gain can be adjusted separately. Take output
gain into account when setting accumulation gain.
Coe ff ic ie nt s (DAp, DB p, DAs, DB s, CAp, CB p, CAs, CBs)
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
Bit :
Initial value :
R/W :
Note: * Initial value is uncertain.
These registers a re 16-bit write-only buffers that determine the cut off frequency f1 and f2. Only a
word access is valid. If a byt e access is atte mpt ed, correct opera tion is not guar ant eed. If a read is
attempted, an undetermined value is read out.
These registers are not initialized by a reset or in standby mode. Be sure to write data in them
before processing starts.
In the digital filter, output gain and accumulation gain can be adjusted separately. Take output
gain into account when setting accumulation gain.
Rev. 1.0, 02/00, page 667 of 1141
Offset (DOfp, DOfs, COfp, COfs)
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
Bit :
Initial value :
R/W :
Note: * Initial value is uncertain.
These registers a re 16-bit write-only buffers that set offset level of digital filter output . Only a
word access i s valid. If a byte a ccess is attempted, correct operat ion is not guaranteed. If a read i s
attempted, an undetermined value is read out.
These registers are not initialized by a reset or in standby mode. Be sure to write data in them
before processing starts.
In this digital filter, output gain adjustment (×1, 2, 4, 8 ,16, 32, 64) after offset adding is ena bled.
Take output gain into a ccount whe n setting accumulation gain.
Del a y Initializa tion Register (CZp, CZ s, DZp, DZs)
131415 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
WWWWWWW
12
000000
1111 ————
Bit :
Initial value :
R/W :
The delay initialization register is a 16-bit writ e -only register. Only a word access is vali d. If a
byte access is attempted, correct operation is not guaranteed. If a read is attempted, an
undetermined val ue is rea d out.
It is ini tialized to H'F000 by a reset, or in stand-by or modul e stop mode. The MSB of 12-bit da ta
(bit 11) is a sign bit.
Loading to Z-1 is performe d automa ti call y by bits 4 and 3 of CFIC and DFIC (CZ PON, CZSON,
DZPON, DZSON). Writin g in re gist er is alwa y s avail abl e, bu t loa din g in Z -1 is not possible when
the digital filter is perform ing computation in relation t o such register. In suc h a ca se, loading to
Z-1 wil l be done the next time c omputation begins.
Rev. 1.0, 02/00, page 668 of 1141
Drum Sy stem Digita l Fil ter Cont rol Regist e r ( DFIC)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
—
—R/WR/WR/(W)
DPHA
R/(W)*
DROV DZPON DZSON DSG2 DSG1 DSG0
1
Note: * Only 0 can be written
Bit :
Initial value :
R/W :
DFIC is an 8-bit read/wri te register that controls t he status of the drum digital filter a nd ope rating
mode. Only a byte access is valid. If a word access is attempted, correct ope ration is not
guaranteed. DFIC is initialized to H' 80 by a reset, a nd in standby mode a nd module stop m ode.
Bit 7Reserved: Cannot be modified and is always read as 1.
Bit 6Drum System Range Over Flag (DRO V) : This flag is set to 1 when the result of a filter
computation exceeds 12 bits in width. To clear this flag, write 0 after reading 1.
Bit 6
DROV Description
0 Indicates that the f ilter comput ation result did not exceed 12 bits (I nit ial value)
1 Indicates that the f ilter comput ation result exceeded 12 bits
Bit 5Drum Phase System Filter Computation Start Bit (DPHA): Starts or stops fi lter
processing for drum phase system.
Bit 5
DPHA Description
0 Phase system filter com putations ar e disabled
Phase computation result (Y) is not added t o Es (see f igur e 26.34) (Initial value)
1 Phase syste m filter compu ta tions are enabled
Rev. 1.0, 02/00, page 669 of 1141
Bit 4Drum Phase Sy stem Z-1 Initialization Bit (DZPO N): Refl ec ts the DZp value o n Z-1 of the
phase system when com putation proce ssing of the drum phase syst em begins. If 1 is written, it is
reflected on the computation, and then cleared to 0. Set this bit after writing data to DZp.
Bit 4
DZPON Description
0 DZp value is not reflected on Z-1 of the phase system ( I nit ial value)
1 DZp value is re flected on Z-1 of the phase system
Bit 3Drum Speed Sy stem Z-1 Initialization Bit (DZSON): Reflects the DZs value on Z-1 of the
speed syst em when computation processing of the drum speed system begins. If 1 is written, it is
reflected on the computation, and then cleared to 0. Set this bit after writing data to DZs.
Bit 3
DZSON Description
0 DZs value is not reflected on Z-1 of the speed syst em ( Initial value)
1 DZs value is reflected on Z-1 of the speed system
Bits 2 to 0Drum System Out put Gain Contro l Bits ( DSG2 to DSG0): Control the gain output
to DR MPWM.
Bit 2 Bit 1 Bit 0
DSG2 DSG1 DSG0 Description
0× 1 (Initial value)0
1× 2
0× 4
0
1
1× 8
0× 160
1(× 32)*
0(× 64)*
1
11 Invalid (Do not use this setting)
Note: * Setting optional.
Rev. 1.0, 02/00, page 670 of 1141
Capstan Sy st e m Digit a l Filter Co ntro l Regist er (CFIC)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
—
—R/WR/WR/(W)
CPHA
R/(W)*
CROV CZPON CZSON CSG2 CSG1 CSG0
1
Note: * Only 0 can be written
Bit :
Initial value :
R/W :
CFIC is an 8-bit read/write register that controls the status of the capstan digital filter and
operating mo de. Onl y a b yte acces s is v alid. If a wo r d access is at tempted, correct operatio n is no t
guaranteed. CFIC is initialized t o H'80 by a re set, and in standby mode a nd module stop m ode.
Bit 7Reserved: Cannot be modified and is always read as 1.
Bit 6Capsta n Sy stem Range Over Fl ag (CROV): This flag is set to 1 when the result of a
filter computation exceeds 12 bits in width. To clear this flag, write 0 after reading 1.
Bit 6
DROV Description
0 Indicates that the f ilter comput ation result did not exceed 12 bits. ( I nit ial value)
1 Indicates that the f ilter comput ation result exceeded 12 bits.
Bit 5Capstan Phas e System Filte r Start (CPHA): Starts or stops fil ter proce ssing for capstan
pha se system.
Bit 5
CPHA Description
0Phase filter computations are disabled.
Phase computation result (Y) is not added t o Es (see figure 26. 39). (Initial value)
1 Phase filter comput ations are enabled.
Rev. 1.0, 02/00, page 671 of 1141
Bit 4Capsta n Phase Syst e m Z-1 Initialization Bit (CZPON): Reflects the CZp value on Z-1 of
the capsta n phase system when computation proce ssing of t he phase system begins. If 1 is
written, it is reflected on the computation, and then cleared to 0. Set this bit after writing data to
CZp.
Bit 4
CZPON Description
0 CZp value is not reflected on Z-1 of the phase system ( I nit ial value)
1 CZp value is re flected on Z-1 of the phase system
Bit 3Capsta n Spee d Syste m Z-1 Initialization Bi t (CZSON): Reflects the CZs value on Z-1 of
the capstan speed system when computation processing of the speed system begins. If 1 is
written, it is reflected on the computation, and then cleared to 0. Set this bit after writing data to
CZs.
Bit 3
CZSON Description
0 CZs value is not reflected on Z-1 of the speed syst em ( Initial value)
1 CZs value is reflected on Z-1 of the speed system
Bits 2 to 0Capsta n Syste m Gain Contr ol Bits (CSG2 to CSG0) : Control the gai n output to
CAPPWM.
Bit 1 Bit 2 Bit 0
CSG2 CSG1 CSG0 Description
0× 1 (Initial value)0
1× 2
0× 4
0
11× 8
0× 1601(× 32)*
0(× 64)*
1
1
1 Invalid (Do not use this setting)
Note: * Setting optional
Rev. 1.0, 02/00, page 672 of 1141
Digital Filt er Co ntro l Regi ster (DF UCR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
67 ——
—— R/WR/WR/W
PTON CP/DP CFEPS DFEPS CFESS DFESS
11
Bit :
Initial value :
R/W :
DFUCR is an 8-bit read/write register which controls the operation of the digital filter. Only a byte
access is valid. If a wo r d access is attempted, cor rect op eration is not guar anteed. It is initialized
to H'00 by a reset , or in stand-by or module stop mode.
Bits 7 and 6Reserved: Cannot be modified and are always read as 1.
Bit 5Phase System Computation Result PWM O utput Bi t (PTON): Outputs the computation
results of only the phase system to PWM. (The computation results of the drum phase system is
output to CAPPWM pin, and that of the capstan phase system is output to DRMPWM pin.)
Bit 5
PTON Description
0 Outputs t he results of ordinary computation of t he filter t o PWM pin (Initial value)
1 Outputs t he computation results of only the phase system to PWM pin
Bit 4PWM Output Selection Bit (CP/
'3
'3
): Selects whether the phase system computation
results when PTON was set to 1 is output to the drum or capstan. The PWM of the selected side
outputs ordinary filter comput ation results (spee d system of MIX).
Bit 4
CP/
'3
'3
Description
0 Outputs t he drum phase system computation r esults (DRMPWM) (Init ial value)
1 Outputs t he capstan phase system computation results (CAPPWM)
Rev. 1.0, 02/00, page 673 of 1141
Bit 3Capstan Phase System Err or Data Transfe r Bit (CFEP S): Transfers the capst an phase
system error data to t he digital filter when the data write is enforced.
Bit 3
CFEPS Description
0 Error data is transferred by DVCFG2 signal latching. (Initial value)
1 Error data is transferred when the data is written.
Bit 2Drum Phase System Error Data Transfer Bit (DFEPS): Transfers the drum phase
system error data to t he digital filter when the data write is enforced.
Bit 2
DFEPS Description
0 Error data is transferred by HSW (NHSW) signal lat c hing. (Initial value)
1 Error data is transferred when the data is written.
Bit 1Capsta n Spee d Syste m Error Data Transf er Bit (CFESS): Transfers the capstan phase
system error data to t he digital filter when the data write is enforced.
Bit 1
CFESS Description
0 Error data is transferred by DVCFG signal latching. ( Initial value)
1 Error data is transferred when the data is written.
Bit 0Drum Speed Sy stem Error Dat a Transfe r Bit (DFESS) : Transfers the drum speed
system error data to t he digital filter when the data write is enforced.
Bit 0
DFESS Description
0 Err or data is transferred by NCDFG signal latching. (Initial value)
1 Error data is transferred when the data is written.
Rev. 1.0, 02/00, page 674 of 1141
26.11.6 Filter Characteristics
• Lag-Lead Filter
A filter required for a servo loop is built in the hardware. This fi lter uses IIR (infinite impulse
response) type digital filter (another t ype of the digital filter is FIR, i.e. fi nite impulse response
type). This digital filter circuit implements a lag-lead filter, as shown in figure 26.40.
R1
R2
C
+
INPUT OUTPUT
Figure 26.40 Lag-Lead Filter
The transfer function is expressed by the following equation:
S
1+
2πf2
Transfer function G (S) =
S
1+
2πf1
f1 =1/2πC (R1+ R2)
f2 =1/2πCR2
Rev. 1.0, 02/00, page 675 of 1141
• Frequency Characteristics
The computation circuit repeats computation of the function, which is obtained by s-z
conversion acc ording to bi -linear approximation of the tra nsfer function on the s-plane. Figure
26.41 shows the frequency characteristics of the lag-lead filter.
f1
0
f2 Frequency (Hz)
20log(f1/f2)
gain(dB)phase(deg)
Figure 26.41 Frequenc y Characteristics of the Lag-Lead Filter
The pulse transfer function G (Z) is obtained by the bi-linear approximation of the transfer G (S).
In the transfer G (S),
S = ·
2
Ts 1–Z
–1
1+Z
–1
Where, ass u med that Z-1 = e-jωTs,
G (Z) = G ·· 2
Ts 1+AZ
–1
1+BZ
–1
G (Z) = Ts + 1
f
2
Ts + 1
f
1
A = Ts – 1
f
2
Ts + 1
f
2
B = Ts – 1
f
1
Ts + 1
f
1
Ts: Sampling cycle (sec)
Rev. 1.0, 02/00, page 676 of 1141
26.11.7 Operations in Case of Transient Response
In case of transient response when the motor is activated, the digital filter computation circuit
must prevent computation due to a large error. The convergence of the computations becomes
slow and servo retraction deteriorates if a large error is input to the filter circuit when it is
performing repeated com putations. To prevent them from occurring, ope rate the filter (set
constants A and B) after pulling in the speed and phase within a certa in rang e of error, initializ e
the Z-1 (set initial values in CZp, CZs, DZp, DZs)(see section 26.11.8, Initialization of Z-1), or use
the error data limit funct i on (see section 26. 6, Drum Speed Error Detector, and section 26. 8,
Capstan Speed Error Detector).
26.11.8 In itialization of Z -1
Z-1 can be initialized by its delay initialization register (CZp, CZs, DZp, DZs). Loading to Z-1 is
performed a u t omatically by bits 4 and 3 of CFIC and DFIC (CZPON, CZ SON, DZPON,
DZSON) . Wr it i n g in regi ste r is alwa ys avail a ble, but load ing in Z-1 is not possible when the
digital filter is performing computation in relation to such register. In such a case, loading to Z-1
will be done when the next time computation begins. Figure 26.42 shows the initialization circuit
of Z-1.
The delay initialization register sets 12-bit data. The MSB (bit 11) i s a si gn bit. Z-1 has 24 bits for
integrals a nd 8 bi t s for decimals. Accordingly, the sam e value as the sign bit should be set in t he
13 bits on the MSB side of Z-1, and 0 in the entire decimal section.
Example: Value set for the delay initializ ation reg ister Value set for Z-1
MSB
0MSB
Set here the value in the
sign bit Fixed
1 0000000000 1111111111111 00000000000 00000000
Rev. 1.0, 02/00, page 677 of 1141
WW
Internal bus
Z
-1
initiali-
zation bit
DZSON
DZPON
CZSON
CZSON
W
16 16
12
24 8
W
Delay initialization
register
Z
-1
USn
-+
Res
Note: MSB of 12-bit data to be written in the delay initialization register is a sign bit.
Usn-1
+
+
Xn Vn
DBs15 to 0
DBp15 to 0
CBs15 to 0
CBp15 to 0
DZs11 to 0
DZp11 to 0
CZs11 to 0
CZp11 to 0
DAs15 to 0
DAp15 to 0
CAs15 to 0
CAp15 to 0
AB
Figure 26.42 Z-1 Initia lizatio n Circui t
Rev. 1.0, 02/00, page 678 of 1141
26.12 Addit ional V Signal Generator
26.12.1 Overview
The additional V signal generator output s an additional vertical sync signal to take the place of
Vsync in special playback. It is activated at both edges of the HSW signal output by the head-
switch timing generator. The head-switch timing generator also outputs a V pulse signal
containing the additional vertical sync pulse itself, and an M level signal that defines the width of
the additional vertical sync signal including the equalizing pulses.
The additional V signal is output at a three-level output pin (V pulse).
Figure 26. 43 shows the additi onal V signal cont rol circuit.
Csync
Additional V pulse
OSCH
Vpulse signal
Mlevel signal
Sync signal detector
HSW timing
generator
Additional V
pulse generator
Fi g ure 26.43 Additi o nal V Pulse Contr ol Circui t
HSW T iming Genera t o r: This circuit generates signals that are synchronized with head
switching. It should be programmed to generate the Mlevel and Vpulse signals at edges of the
HSW signal (VideoFF). For details, see section 26.4, HSW (Head-switch) Timing Generator.
Sync Signal Detec tor: This circuit detects pulses of the width specified by VTR or HTR from the
signal input at the Csync pin and generates an int ernal horizontal sync signal (OSCH). The sync
signal de tector has an interpolation function, so OSCH has a regular peri od even i f there are
horizontal sync dropouts in the signal received at the pin. For details, see section 26.15, Sync
Signal Detector.
Rev. 1.0, 02/00, page 679 of 1141
26.12.2 Pin Configuration
Table 26.16 summarizes the pin configuration of the additional V signal.
Table 26. 16 Pin Configuration
Name Abbrev. I/O Function
Additional V pulse pin Vpulse O utput Output of additional V signal synchronized to
video FF
26.12.3 Register Configuration
Table 26.17 summarizes the register that controls the additional V signal.
Table 26. 17 Register Configurati on
Name Abbrev. R/ W Size I nit i al Value Address
Additional V control regist er ADDVR R/W Byt e H'E0 H'D06F
26.12.4 Register Description
Addi ti on al V Control Reg i ste r (ADDVR)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
1
67 ———
——— R/WR/W
HMSK HiZ CUT VPOM POL
11
Bit :
Initial value :
R/W :
ADDVR is an 8-bit read/write register. It is i nitialized to H'E0 by a re set, and in sta ndby mode.
Bits 7 to 5Reserved: Cannot be modifi ed and are always re ad as 1.
Bit 4OSCH Mask ( HMSK): Masks t he OSCH si gnal in the add it i o nal V signal .
Bit 4
HMSK Description
0 OSCH is added in (I nitial value)
1 OSCH is not added in
Rev. 1.0, 02/00, page 680 of 1141
Bit 3High Impedance (HiZ): Set to 1 when the intermediate level is generated by an external
circuit.
Bit 3
HiZ Description
0 Vpulse is a three-level output pin (Init ial value)
1 Vpulse is a three-state output pin (high, low, or high-impedance)
Bits 2 to 0Addi tio nal V Output Contr ol ( CUT, VPON, POL ) : These bits control the output
at the additional V pin.
Bit 2 Bit 1 Bit 0
CUT VPON POL Description
0 * Low leve l (Initial value)
0 Negative polari ty (see figure 26.46 )
01
1 Positive polarity ( see figure 26.45)
0 Int ermediate level ( high impedance if HiZ bit = 1)1*1 High le v e l
Note: * Don't care.
Rev. 1.0, 02/00, page 681 of 1141
26. 1 2.5 Addi tiona l V Pulse Sig nal
Figure 26. 44 shows the additi onal V pulse signal. The M level a nd V pulse signals are generated
by the head-switch timing generator. The OSCH signal is combined with these to produce
equalizing pulses. The polarity can be selected by the POL bit in the additional V control register
(ADDVR). V pulse pin outputs a low level by a reset, and in standby mode and module stop
mode.
R/WR/W
á ADDVR á ADDVR
R/W
Internal bus
R/W R/W
CUTVPON HMSK POL HiZ STBY
V
CC
V
CC
V
SS
V
SS
Rs
Rs
V pulse pin
OSCH
V pulse
M level
Note:
STBY : Power-down mode
V pulse, M level : Signal from the HSW timing generator
Rs : Voltage division resistance (20 kΩ: reference value)
Fi g ure 26 .44 Additional V Pulse Pin
Rev. 1.0, 02/00, page 682 of 1141
Additiona l V Pulse s When Sync Signal is Not Detected: With additional V pulses, the pulse
signal (OSCH) detected by the sync signal detector is superimposed on the V pulse and Mlevel
signals generated by the head-switch timing generator. If there is a lot of noise in the input sync
signal (Csync), or a pulse is missing, OSCH will be a complementary pulse, and therefore an H
pulse of the period set in HRTR and HPWR will be superimposed. In this case, there may be
slight timing drift compared with the normal sync signal, depending on the HRTR and HPWR
setting, with resultant discontinuity.
If no sync signal is input, the additional V pulse is generated as a complementary pulse. Set the
sync signal detector registers and activate the sync signal detector by manipulating the SYCT bit
in the syn c si gnal con tro l register ( SYNCR). See sectio n 26. 15. 7, Ac tiva t ion of the Sync Sign al
Detector.
Figures 26.45 and 26. 46 show the additional V pulse timing chart s.
HSW signal edge
OSCH
VPON=1, CUT=0, POL=1
Additional
V pulse
Vpulse
signal
Mlevel
signal
Fi g ure 26.45 Additi o nal V Pulse when Posi tiv e Polarity Is Speci fie d
Rev. 1.0, 02/00, page 683 of 1141
HSW signal edge
OSCH
VPON=1, CUT=0, POL=0
Additional
V pulse
V pulse
signal
M level
signal
Fi g ure 26 .46 Additional V Pulse Whe n Negati ve Po lar ity Is Specif ie d
Rev. 1.0, 02/00, page 684 of 1141
26.13 CTL Circuit
26.13.1 Overview
The CTL circuit includes a Schmitt amplifier that amplifies and reshapes the CTL input, then
outputs it as the PB-CT L signal to the servo, linear time counter, a nd other circuits.
The PB-CTL signal is also sent to a duty discriminator in the CTL circuit that detects and records
VISS, ASM, a nd VASS marks. A REC-CTL am pli f ie r is incl u ded in the recor d circ ui t s.
Detection and rec ording whether the CTL pul se pattern is long or short ca n also be enabled to
correspond to the wi de-aspect.
The following ope rating modes can be selected by settings in the CTL mode register:
• Duty discrimination
VISS de te ct , ASM dete ct , VASS dete ct , L/ S bit pat te r n detec t
• CTL re cord
VISS record, ASM record, VASS record, L / S bit pa tte rn record
• Rewrite
Trapezoid waveform generator
Rev. 1.0, 02/00, page 685 of 1141
26.13.2 Bloc k Diagram
Figure 26. 47 shows a block diagram of the CT L circuit.
+ -
PB-CTL
FW/RV
CTL(-)CTL(+)
Schmitt
amplifier
CTL mode
CTL
detector
Duty dis-
criminator
Bit pattern
register
VISS detect
VISS
control circuit
VISS write
Duty I/O flag
Write control
circuit
REC-
CTL amplifier
Internal bus
REF30X
IRRCTL
Figure 26.47 Block Diagram of CTL Circuit
Rev. 1.0, 02/00, page 686 of 1141
26.13.3 Pi n Confi guration
Table 26.18 summarizes the pin configuration of the CTL circuit.
Table 26. 18 Pin Configuration
Name Abbrev. I/O Function
CTL (+) I/O pin CTL (+) I/O CTL signal input/output
CTL (–) I/O pin CTL (–) I/O CTL signal input/output
CTL bias input pin CTL Bias Input CTL primar y amplifier bias supply
CTL Am p (O) out put pin CTLAmp (O) Output CTL am plifier output
CTL SMT (i) input pin CTLSM T (i) In p ut CTL Schmitt amplifier input
CTL FB input pin CTL FB I nput CTL amplifier high-range characteristics
control
CTL REF output pin CTL REF Output CTL amplifier reference voltage output
26.13.4 Register Configuration
Table 26. 19 shows the re gister c onfiguration of the CTL circuit.
Table 26. 19 Register Configurati on
Name Abbrev. R/W Size Initi al Value Address
CTL control r egist er CTCR R/ W Byte H'30 H'D0 80
CTL m ode register CTLM R/W Byt e H'00 H'D081
REC-CTL d uty data
register 1 RCDR1 W Word H'F000 H'D082
REC-CTL d uty data
register 2 RCDR2 W Word H'F000 H'D084
REC-CTL d uty data
register 3 RCDR3 W Word H'F000 H'D086
REC-CTL d uty data
register 4 RCDR4 W Word H'F000 H'D088
REC-CTL d uty data
register 5 RCDR5 W Word H'F000 H'D08A
Duty I/O register DI/O R/W Byte H 'F1 H'D08C
Bit pattern r egister BTPR R/W Byte H'FF H'D08D
Rev. 1.0, 02/00, page 687 of 1141
26.13.5 Register Description
CTL Cont rol Re gist er ( CT CR)
0
0
1
0
R
2
0
W
3
0
4
1
W
5
1
6
0
7
WW W
FSLB
W
FSLC
0
W
NT/PL FSLA CCS LCTL UNCTL SLWM
Bit :
Initial value :
R/W :
CTCR is an 8-bit read/write register that controls PB-CTL rewrite and sets the slow mode. When
CTL pul se cannot be de tected with the input a mplifier ga in set at the CTL gain control register
(CTLGR) in PB-CTL circuit, bit 1 (UNCTL) of CTCR is set to 1. It is automatically cleared to 0
when CTL pulse is detected.
Bit 1 i s read-only, and the rest are writ e-only. If a read is a ttempted t o a write-only bit, an
undetermined val ue is rea d out.
CTCR is initialized to H'30 by a reset, and in standby and module stop mode.
Bit 7NTSC/PAL Select (NT/PL): Selects the period of the rewrite circuit.
Bit 7
NT/PL Description
0 NTSC mode (frame rate: 30 Hz) (Initial value)
1 PAL mode (frame rate: 25 Hz)
Bits 6 to 4Frequency Select (FSLA, FSLB, FSLC); These bits select the operating frequency
of the CTL write circui t. They should be set according to fOSC.
Bit 1 Bit 0 Bit 0
FSLC FSLB FSLA Description
0 Reserved (do not use this setting)0
1 Reserved (do not use this setting)
0 fosc = 8 MHz
0
1
1 fosc = 10 MHz (Initial value)
1 * * Reserved (do not use this setting)
Note: * Don't care.
Rev. 1.0, 02/00, page 688 of 1141
Bits 3Clock Source Select Bit (CCS): Selects clock source of CTL.
Bit 3
CCS Description
0φs (Initial value)
1φs/2
Bit 2Long CTL Bit (LCTL): Sets the long CTL detection mode.
Bit 2
LCTL Description
0 Clock sour ce (CCS) operates at the setting value (Initial value)
1Clock source (CCS) operates for further 8-division after operating at the setting
value
Bit 1CTL Undetected Bit (UNCTL): Indicates the CTL pul se detection status at the CTL
input ampl ifier sensit i vity set at the CTL gain control register.
Bit 1
UNCTL Description
0 Detected (Init ial value)
1 Undetected
Bit 0Mode Select Bit (SLWM): Selects CT L mo de.
Bit 0
SLWM Description
0 Normal m ode (Init ial value)
1 Slow mode
Rev. 1.0, 02/00, page 689 of 1141
CTL Mode Re gister ( CTLM)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/W
FW/RV
R/W
REC/PB
0
R/W
ASM MD4 MD3 MD2 MD1 MD0
Bit :
Initial value :
R/W :
CTLM is an 8-bit read/write register that controls the operating state of the CTL circuit. If 1 is
written in bits MD3 and MD2, they will be cleared to 0 one cycle (φ) later.
CTLM is initialized to H'00 by a reset, and in standby mode and module stop mode. When CTL is
being stoppe d, only bits 7, 6 and 5 operate.
Note: Do not set a ny value other than the setting va lue for each mode (see table 26. 20, CTL
Mode Func tions).
Bits 7 and 6Recor d/Pla y back Mode Bits (ASM, REC/
3%
3%
): These bits switch between record
and playback. Com bined with bits 4 to 0 (MD4 to MD0), they support the VISS, VASS, and
ASM mark function s.
Bit 7 Bit 6
ASM REC/
3%
3%
Description
0 Playback mode ( I nitial value)01 Record mode
0 Assemble mode1
1 Invalid (do not set)
Bit 5Direction (FW/RV): Selects the direction i n playba ck. Cl ear thi s bit to 0 during record.
Figure 26. 48 shows the PB-CTL signal.
Bit 5
FW/RV Description
0 Forward (Init ial value)
1 Reverse
Rev. 1.0, 02/00, page 690 of 1141
CTL input
PB-CTL
FWD
REV
Figure 26.48 Internal PB-CTL Signal i n Forward and Reverse
Bits 4 to 0CTL Mode Select (MD4 to MD0): These bits select the detect, record, and rewrite
mo des for VISS, VASS, and ASM marks. If 1 is wri tt e n in bits MD3 and MD2, th ey will be
cleared to 0 o n e cy cle (φ) later.
The 5 bits from MD4 to MD0 are used in combination with bits 7 and 6 (ASM and REC/
3%
).
Table 26. 20 describes t he modes.
Table 26. 20 CTL M ode Functions
Bit
ASM R/
3
3
F/R MD4 MD3 MD2 MD1 MD0 Mode Description
000/100000VASS
detect
(duty
detect)
PB-CTL duty discrimination
(Initial value)
•Duty I/O flag is set to 1 if duty ≥
44% is detected
•Duty I/O flag is cleared to 0 if
duty < 44% is de tec ted
•Interrupt request is generated
when one CTL pulse has been
detected
01000000VASS
record •If 0 is written in the duty I/O flag,
REC -C TL is ge nerated an d
recorded with the duty cycle set
by register RCDR2 or RCDR3
•If 1 is written in the duty I/O flag,
REC -C TL is ge nerated an d
recorded with the duty cycle set
by register RCDR4 or RCDR5
00010010VASS
rewrite Same as above (VASS record);
trapezoid waveform circuit
operation
Rev. 1.0, 02/00, page 691 of 1141
Bit
ASM R/
3
3
F/R MD4 MD3 MD2 MD1 MD0 Mode Description
000/101001VISS
detect
(index
detect)
•The duty I/O flag is set to 1 at
the point of write a ccess to
register CTLM
•The 1 pulses recognized by the
duty discrimination circuit are
counted in the VISS control
circuit
•The duty I/O flag is cleared to 0,
indicating VISS detection, when
the value se t at VC TR regi ster is
repeated ly detected
•An interrupt request is
generated when VISS is
detected
01000101VISS
record
(index
record)
•64 pulse data with 0 pulse data
at bot h ed ge ar e wr itten ( in dex
record)
•The index bit string is writte n
through the duty I/O flag
•An interrupt request is
generated at the end of VISS
recording
00000101VISS
rewrite Same as above (VISS record;
trapezoid waveform circuit
operation)
00010000VISS
initialize VISS write is forcibly aborted
100/100000ASM
mark
detect
ASM mark detecti on
•The duty I/O flag is cleared to 0
when PB-CTL du ty ≥ 66% is
detected
•An interrupt request is
ge ner ated w he n an AS M mar k is
detected
01010000ASM
mark
record
•An ASM mark is recorded by
writing 0 in the duty I/O flag
•An interrupts is requested for
every one CTL pulse
•REC -C TL is ge nerated an d
recorded with the duty cycle set
by register RCDR3
Rev. 1.0, 02/00, page 692 of 1141
REC-CTL Dut y Data Register 1 (RCDR1)
131415 103254769811 10
CMT11
W
12
1111
————
———— 0
CMT10
W
0
CMT13
W
0
CMT12
W
0
CMT15
W
0
CMT14
W
0
CMT17
W
0
CMT16
W
0
CMT19
W
0
CMT18
W
0
CMT1B
W
0
CMT1A
W
0
Bit :
Initial value :
R/W :
RCDR1 i s a 12-bit wri te-only re gister that set s the REC-CTL risi ng timing. This setting i s valid
only for recording and rewriting, and i s not used in de tection.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. If a
read is attempted, an undetermined value is read out. Bits 15 to 12 are reserved and are not
affected by write ac ces s.
RCDR1 i s initialized to H'F000 by a reset, and i n standby mode, m odule stop mode a nd CTL stop
mode.
The value to set in RCDR1 can be calculated from the transition timing T1 and the servo clock
frequency φs by the equation given below. Se e figure 26.60, REC-CTL Signal Generation
Timing. Any transition timing can be set. The timing should be selected with attention to
playback tracking compensation and the latch timing for phase control.
RCDR1 = T1 × φs/64
φs is the servo clock frequency (= fOSC/2) in H z, and T1 is the set ti ming (s) .
Note: 0 cannot be set to RCDR1. Se t a va l ue 1 or above.
Rev. 1.0, 02/00, page 693 of 1141
REC-CTL Dut y Data Register 2 (RCDR2)
1111
131415 103254769811 10
CMT21
W
12
————
———— 0
CMT20
W
0
CMT23
W
0
CMT22
W
0
CMT25
W
0
CMT24
W
0
CMT27
W
0
CMT26
W
0
CMT29
W
0
CMT28
W
0
CMT2B
W
0
CMT2A
W
0
Bit :
Initial value :
R/W :
RCDR2 i s a 12-bit wri te-only re gister that set s 1 pul se (short) falling timing of REC-CTL at
recording and rewriting, and detects long/ short pulses at detecti ng.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. If a
read is attempted, an undetermined value is read out. Bits 15 to 12 are reserved and are not
affected by write ac ces s.
RCDR2 i s initialized to H'F000 by a reset, and i n standby mode, m odule stop mode, and CTL stop
mode.
At recording, the value to set in RCDR2 can be calculated from the transition timing T2 and the
servo clock frequen cy φs by the equation given below, and the set value should be 25% of the duty
obtained by the equation. See figure 26.60, REC-CTL Si gnal Gene ration Timing.
RCDR2 = T2 × φ s/ 6 4
φs is the servo clock frequency (= fOSC/2) in H z, and T2 is the set tim ing (s) .
At bit pattern detection, set t he 1 pulse long/short t hreshold value at FWD. See figure 26.56, Dut y
Discriminator.
RCDR2 = T2' × φ s/6 4
φs is the servo clock frequency (= fOSC/2) in Hz, and T2' is the 1 pulse long/short threshold value at
FWD (s).
Rev. 1.0, 02/00, page 694 of 1141
REC-CTL Dut y Data Register 3 (RCDR3)
1111
131415 103254769811 10
CMT31
W
12
————
———— 0
CMT30
W
0
CMT33
W
0
CMT32
W
0
CMT35
W
0
CMT34
W
0
CMT37
W
0
CMT36
W
0
CMT39
W
0
CMT38
W
0
CMT3B
W
0
CMT3A
W
0
Bit :
Initial value :
R/W :
RCDR3 i s a 12-bit wri te-only re gister that set s 1 pul se (long) and assemble mark falling timing of
REC-CTL at recording and rewriting, and detects long/short pulses at detecting.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. If a
read is attempted, an undetermined value is read out. Bits 15 to 12 are reserved and are not
affected by write ac ces s.
RCDR3 i s initialized to H'F000 by a reset, and i n standby mode, m odule stop mode, and CTL stop
mode.
At recording, the value to set in RCDR3 can be calculated from the transition timing T3 and the
servo clock frequen cy φs by the equation gi ven below. The set value should be 30 pe rcent of the
duty when the RCDR3 is used for REC-CTL 1 pulse, and 67 to 70 percent when used for assemble
mark. The set va lue must not exc eed the frequency of REF30X. See figure 26.60, REC-CTL
Signal Ge neration Timing.
RCDR3 = T3 × φs/64
φs is the servo clock frequency (= fOSC/2) in H z, and T3 is the set ti ming (s) .
At bit pattern detection, set t he 0 pulse long/short t hreshold value at FWD. See figure 26.56, Dut y
Discriminator.
RCDR3 = T3' × φs/64
φs is the servo clock frequency (= fOSC/2) in Hz, and T3' is the 0 pulse long/short threshold value at
FWD (s).
Rev. 1.0, 02/00, page 695 of 1141
REC-CTL Dut y Data Register 4 (RCDR4)
1111
131415 103254769811 10
CMT41
W
12
————
———— 0
CMT40
W
0
CMT43
W
0
CMT42
W
0
CMT45
W
0
CMT44
W
0
CMT47
W
0
CMT46
W
0
CMT49
W
0
CMT48
W
0
CMT4B
W
0
CMT4A
W
0
Bit :
Initial value :
R/W :
RCDR4 i s a 12-bit wri te-only re gister that set s the ti ming of falling edge of t he 0 pulse (short) of
REC-CTL in record or rewrite mode. In detection mode, it is used to detect the long/short pulse.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. If a
read is attempted, an undetermined value is read out. Bits 15 to 12 are reserved, and no write in
the m is valid.
It is ini tialized to H'F000 by a reset, stand-by or module stop.
In record mode, set a value with the 57.5 percent duty cycle obtained from the set time T4
correspondin g to th e frequenc y φs acco r d ing to the follow in g equat ion. See fi gu re 26.60, R EC-
CTL Signa l Genera tion Timing.
RCDR4 = T4 × φ s/ 6 4
φ is the servo cloc k fre quency (= fOSC/2) in Hz, and T4 is the set timing (s).
At bit pattern detection, set t he 0 pulse long/short t hreshold value at REV. See figure 26. 56, Duty
Discriminator.
RCDR4 = H'FFF − (T4' × φ s/80)
φs is the servo clock frequency (= fOSC/2) in Hz, and T4' is the 0 pulse long/short threshold value at
REV (s).
Rev. 1.0, 02/00, page 696 of 1141
REC-CTL Dut y Data Register 5 (RCDR5)
1111
131415 103254769811 10
CMT51
W
12
————
———— 0
CMT50
W
0
CMT53
W
0
CMT52
W
0
CMT55
W
0
CMT54
W
0
CMT57
W
0
CMT56
W
0
CMT59
W
0
CMT58
W
0
CMT5B
W
0
CMT5A
W
0
Bit :
Initial value :
R/W :
RCDR5 i s a 12-bit wri te-only re gister that set s the ti ming of falling edge of t he 0 pulse (short) of
REC-CTL in record or rewrite mode. In detection mode, it is used to detect the long/short pulse.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. If a
read is attempted, an undetermined value is read out. Bits 15 to 12 are reserved, and no write in
the m is valid.
It is ini tialized to H'F000 by a reset, stand-by or module stop.
In record mode, set a value with the 62.5 percent duty cycle obtained from the set time T5
correspondin g to th e frequenc y φs acco r d ing to the follow in g equat ion. See fi gu re 26.60, R EC-
CTL Signa l Genera tion Timing.
RCDR5 = T5 × φ s/ 6 4
φ is the servo cloc k fre quency (= fOSC/2) in Hz, and T5 is the set timing (s).
At bit pattern detection, set t he 1 pulse long/short t hreshold value at REV. See figure 26. 56, Duty
Discriminator.
RCDR5 = H'FFF − (T5' × φ s/80)
φs is the servo clock frequency (= fOSC/2) in Hz, and T5' is the 1 pulse long/short threshold value at
REV (s).
Rev. 1.0, 02/00, page 697 of 1141
Duty I/ O Regi st er (DI/O)
0
1
1
0
R/(W)*
2
0
W
3
0
4
—
—
5
1
67
R/WWW
VCTR0
1
W
VCTR1
1
W
VCTR2 BPON BPS BPF DI/O
1
Note: * Only 0 can be written
Bit :
Initial value :
R/W :
DI/O is an 8-bit register that confirms and determines the operating status of the CTL circuit.
It is ini tialized to H'F1 by a reset, a nd in standby mode, module stop m ode, a nd CTL stop mode.
Bits 7 to 5VISS Inter r upt Set ting Bit (VCTR2 to VCTR0): Combination of VCTR2, VCTR1
and VCTR0 sets number of 1 pulse detection in VISS detection mode. Detecting the set number
of pulse detection is considered as VISS detection, and an int e rrupt reque st is generated.
Note: W hen changing the detection pul se num ber during VISS detection, initialize VISS first,
then resume the VISS detection setting.
Bit 7 Bit 6 Bit 5
VCTR2 VCTR1 VCTR0 Number of 1-Pulse for Detection
020
1 4 ( SYNC mark)
06
0
1
1 8 ( mark A , short )
0 12 (mark A, long)0116
0 24 (mark B)
1
1132
Bit 4Reserved: Cannot be modified and is always read as 1.
Rev. 1.0, 02/00, page 698 of 1141
Bit 3Bit Pa ttern Det ection ON/OF F Bit (BPON): Determi nes ON or OFF of bit pattern
detection.
Note: W hen writing 1 to BPON bit, be sure to set appropriate data to RCDR 2 to 5 beforehand.
Bit 3
BPON Description
0 Bit pattern detection off (Initial value)
1 Bit pattern detection on
Bit 2Bit P attern Detection Start Bit (BPS): Starts 8-bit bit pattern detection. When 1 is
written to this bit, it ret urns to 0 after one cycle. Writing 0 to this bit does not affect ope ration.
Bit 2
BPS Description
0 Normal status (Init ial value)
1 Starts 8-bit bit patt ern detection
Bit 1Bit P attern Detection Fl ag (BPF): Sets flag every time 8-bit PB-CTL is detected in PB or
ASM mo de. To clea r fl ag, wr it e 0 after readi ng 1.
Bit 1
BPF Description
0 Bit pattern (8-bit) is not detected (Initial value)
1 Bit pattern (8-bit) is detected
Bit 0Duty I/O Regist er (DI/O ) : This flag has di fferent functions for record and pla yback.
In VI SS dete ct mode, VASS dete ct mode, and ASM mark detec t m ode, this flag ind icates the
detection result.
In VISS record or rewrite mode, this flag controls the write control circuit so as to write an index
code, opera ting according to a control signal from the VISS control circuit .
In VASS record or rewrite mode a nd ASM mark record mode, t hi s flag i s used for write control,
one CTL p ulse at a time.
This bit can always be written to, but this does not affect the write control circuit in modes other
than VISS record, rewrite, and ASM reco rd.
Rev. 1.0, 02/00, page 699 of 1141
• VISS Detect Mo de and VASS Detect Mode: T he duty I/O fla g indicates the result o f duty
dis cr imination . The du ty I /O f lag is 1 when the duty cycl e of the PB-CTL signal is above 44%
(a 0 pulse in the CTL signal). The duty I/O flag is 0 when the duty cycle of the PB-CTL signal
is below 44% (a 1 pulse in the CTL signal).
• ASM Mark Detect Mod e: The duty I/ O flag indica tes the r e sult of dut y discrimi n ation. Th e
duty I/O flag is 0 when the duty cycle of the PB-CTL signal is above 66% (when an ASM
mark is detected).
• VISS Record Mode and VISS Re write Mode: The dut y I/O fl ag opera tes according t o a cont rol
signal from the VISS control circuit, and controls the write control circuit so as to write an
index c ode. The writ e timing i s set i n the REC-CTL duty dat a regi ste rs (RCDR1 to RCDR5).
For VISS recording, re gisters RCDR1 to RCDR5 are set with reference to REF30X. For VISS
rewrite, RCDR2 to RCDR5 are set with reference to the low-to-high transition of the
previously recorded CTL signa l, and the wri te is ca rried out through the trapezoid wa veform
generator.
Set the duty timing for a 1 pulse (short) in RCDR2, for a 1 pulse (long) in RCDR3, for a 0
pulse (short) in RCDR4, and for a 0 pul se (l ong) in RCDR5.
While an index code is being written, the value of the bit being written can be read by reading
the duty I/O flag. If the CTL signal currently being written is a 0 pulse, the duty I/O flag will
read 1. If the CTL signal curre ntly being written is a 1 pulse, the duty I/O fla g will read 0.
• VASS Rec ord Mode and VASS Rewrit e Mode: The duty I/O flag is used for write cont rol, o ne
CTL pul se at a time. The write timing is set i n the REC-CTL duty dat a registers (RCDR1 to
RCDR5). For VASS recording, regi sters RCDR1 to RCDR5 are set with reference to
REF30X. For VASS rewrite, RCDR2 to RCDR5 are set with re fe rence to the low-to-high
transition of the pre viously rec orded CTL signal, and the write is carried out through the
trapezoid waveform generator.
Set the duty timing for a 1 pulse (short) in RCDR2, for a 1 pulse (long) in RCDR3, for a 0
pulse (short) in RCDR4, and for 0 pulse (long) in RCDR5.
If 0 is written in the duty I/O flag, a CTL pulse will be written with a duty cycle set in RCDR2
and RCDR3, referenced to the immediately following REF30X. If 1 is written in the duty I/O
flag, a CTL pulse will be written with a duty cycle set in RCDR4 and RCDR5, referenced to
the immediately following REF30X.
• ASM Recor d Mode: The duty I/O flag is used for write control, one CTL pulse at a time. The
write timing is set in the REC-CT L duty da ta regi ste rs (RCDR1 and RCDR3). If 0 is written
in the duty I/O flag, a CTL pulse will be written with a duty cycle of 67% to 70% as set in
RCDR3, refe renced to the immediate l y following RE F30X.
Rev. 1.0, 02/00, page 700 of 1141
Bit Pattern Register (BTPR)
0
1
1
1
R/W*
2
1
R/W*
3
1
45
1
67
R/W*R/W*R/W*
LSP5
1
R/W*
LSP4
1
R/W*
LSP6
1
R/W*
LSP7 LSP3 LSP2 LSP1 LSP0
Note: * Write is prohibited when bit pattern detection is selected.
Bit :
Initial value :
R/W :
BTPR is an 8-bit shift register which detects and records the bit pattern of the CTL pulses. If a
CT L pulse i s dete ct ed in PB or ASM mode, the regist er is shifte d lef t ward at the risi n g edge of
PB-CTL, and reflects the determined result of long/ short on the bit 0 (l ong pulse = 1, short pul se =
0).
If BPON bit i s set to 1 in PB mode, the register start s dete ct i on of bit patter n immed iate l y after the
CT L pulse. To exit the bit patt ern dete ct i on, se t the BPON bit at 0.
If 1 was written in the BPS bit when the bit pattern is being detected, the BPF bit is set at 1 when
an 8-bit bit pattern was detected. If continuous detection of 8-bits is required, write 0 in the BPF
bit , and then w r ite 1 in BPS bit.
At the t ime o f VISS dete ction, the bit patt e r n detec ti o n is disable d . Set the BPON bit to 0 at the
time of VISS detection.
In REC mode, the register rec ord the long/shorts in the bit pa ttern set in BTPR. T he pulse i n
record mode i s determined a lways by bit 7 (L SP7) of BTPR. BTPR records one pul se, shifts
leftward, and stores the data of bit 7 to bit 0.
BTPR is initialized t o H'FF by a reset, in stand-by, m odule stop, or CTL stop mode.
Rev. 1.0, 02/00, page 701 of 1141
26.13.6 Operation
CTL Circuit Ope rati on: As shown in fi gure 26.49, the CTL discrim i nation/record circuit is
composed of a 16-bi t up/down count er and 12-bit regi sters (×5).
In playba c k (PB) mode, the 16-bit up/ down c ounter count s on a φs/4 clock when the PB-CTL
pulse is hi gh, and on a φs/5 c l ock when low. In record or slow mode, thi s counter i ncrements the
count on a φs/ 4 c l ock. In ASM mode, this counter inc rements the count on a φs/8 clock when the
pulse is hi gh, and on a φs/4 clock when low.
This count er alwa ys counts up in re cord and slow modes.
In playback or slow mode, it is cleared on the rise of PB-CTL signal. In record mode, it is cleared
on the rise of REF30X signal.
φs/4
(φs/8)
φs/5
(φs/4)
REC-CTL↓(L0)
RCDR5
REC-CTL↓(S0)
RCDR4
REC-CTL↓(L1and ASM)
RCDR3
REC-CTL↓(S1)
RCDR2
REC-CTL↑
Match
detection
Match
detection
Match
detection
Match
detection
Match
detection
RCDR1
12-bit register
UDF:
DOWN
UDF
Upper 12 bits
UP
UP/DOWN counter (16 bits) Duty
detection
Counter clear signal
REF30X ↑ (REC)
PB-CTL ↑ (PB, ASM)
Up/Down control signal
REC: UP
PB, ASM:
UP when PB-CTL is high
Down when PB-CTL is low
Underflows when PB-CTL
duty is 44% or less
Figure 26.49 CTL Discrimination/Record Circuit
CTL Mode Re gister ( CTLM) Switcho ver Timing: CTLM is enabled immediately after data is
written to the register. Care must be taken with changes in the operating state.
Capstan pha se control is performed by the VD sync REF30X (X-value + t racking value) and PB-
CT L in ASM mode, and by the REF30P or CRE F and CFG division sig nal (DVC FG2 ) in REC
mode. If CAPREF30 signal to be used for ca pstan phase c ontrol is always gene rated by XDR, the
value of XDR must be overwritten when switching between PB and REC modes. Figures 26.50
and 26.51 show examples of switch timing of CTLM and XDR.
Rev. 1.0, 02/00, page 702 of 1141
VD
DVCFG2
REF30X
16bit
UP/DOWN
counter
HSW
CTL
Tx
Latch Preset
The X-value is updated by REF30P. Modification of XDR must be performed
before REF30P in the cycle in which the X-value is changed.
X-value
X-value
after
change
RCDR3RCDR1 RCDR2
REF30P
Ta
PB-CTL
Tb
1 pulseUDF
0 pulse 0 pulse
CDIVR2
Register write
Ta is the interval calculated from RDCR3.
Tb is the interval in which switchover is performed
from ASM mode to REC mode.
Tx is the cycle in which the REF30X period is
shortened due to the change of XDR.
1 pulse
X-value (XDR) is
rewritten in this
cycle
RCDR1
Capstan phase control
ASM mode, PB mode : REF30X-PB-CTL
REC mode : REF30P-DVCFG2
φ/4 φ/5 φ/4
REC-CTL
Notes: 1.
2.
3.
Figure 26.50 Example of CTLM Switc hover Timi ng
(Whe n Phase Cont r ol Is Perf ormed by REF30P and DVCFG 2 in REC Mode)
Rev. 1.0, 02/00, page 703 of 1141
VD
CREF
REF30X
16bit
UP/DOWN
counter
HSW
CTL
Tx
Latch Preset
The X-value is updated by REF30P. Modification of XDR must be performed
before REF30P in the cycle in which the X-value is changed.
X value
X-value after
change
RCDR3RCDR1 RCDR2
REF30P
Ta
PB-CTL
Tb
1 pulse0 pulse 0 pulse
ASM-REC
switchover
Ta is the interval calculated from RDCR3.
Tb is the interval in which switchover is
performed from ASM mode to REC mode.
Tx is the cycle in which the REF30X period
is shortened due to the change of XDR.
With CREF and DVCFG2 phase alignment,
the frequency need not be 25 Hz or 30 Hz.
1 pulse
X-value (XDR) is
rewritten in this
cycle
DVCFG2
RCDR1
Capstan phase control
ASM mode, PB mode: REF30X-PB-CTL
Capstan phase control
REC mode : CREF30P-DVCFG2
φ/4 φ/5 φ/4
REC-CTL
CDIVR2
Register write
UDF
Notes: 1.
2.
3.
4.
Figure 26.51 Example of CTLM Switc hover Timi ng
(Whe n Phase Cont r ol Is Perf ormed by CREF and DVCFG2 in Rec Mode)
Rev. 1.0, 02/00, page 704 of 1141
26. 1 3.7 CTL Input Sec t ion
The CTL input section c onsists of an input ampl ifier of which gain can be controlled by t he
register setting and a Schmitt amplifier. Figure 26.52 shows a block diagram of the CTL input
section.
Trivial CTL pulse signal is received from the CTL head, amplified by the input amplifier,
reshaped into a square wave by the Schmitt amplifier, and sent to the servo circuits, and the Timer
L as the PB-CTL signal. Control the CTL i nput am plifier gain by bits 3 to 0 in CTL gain control
register (CTL GR) of the servo port.
Ð
+
+
Ð
CTLFB
CTLSMT(i)CTLFBCTLREF CTLBias
CTLGR0CTLGR3 to 1
AMPSHORT
(REC-CTL)
PB-CTL(+)
Note : Be sure to set a capacitor between CTLAmp (o) and CTLSMT (i).
Note
PB-CTL(-)
AMPON
(PB-CTL)
Ð +
CTLAmp(o)CTL(+)CTL(-)
Fi g ure 26.52 Block Diag ram of CTL Input Ampli fier
Rev. 1.0, 02/00, page 705 of 1141
CTL Detector: If the CTL detector fails to detect a CTL pulse, it sets the CTL control register
(CTCR) bit 1 to 1 indicating that the pulse has not been detected. If a CTL pulse is detected after
that, the bit is automatically cleared to 0. Duration used for det ermining detection or non-
detection of the pulse depends on magnitude of phase shift of the last detected pulse from the
reference phase (phase difference between REF30 and CTL signal). Typically, detection or non-
detection is determined within 3 to 4 cycles of the reference period.
If settings of the CTL gain control register are maintained in a table format, you can refer to it
when the CTL detector failed to detect CTL pulses. From the table, you can control amplifier gain
of the CTL according to state of UNCTL bit, thereby selecting an optimum CTL amplifier gain
depending on state of the pulse recorded.
Figure 26. 53 illustrates c oncept of gain control for det ecting the CTL input pulse.
*
V+TH (fixed)
*
V-TH (fixed)
Note: * CTL input sensitivity is variable depending on CTL
gain control register (CTLGR) setting.
Fi g ure 26.53 CTL Input Pul se Gain Control
Rev. 1.0, 02/00, page 706 of 1141
PB-CTL Waveform Shaper in Sl ow Mode Oper ation: If bit 0 i n CTL c ontrol register (CT CR)
is set to slow mode, slow reset function is activated. In slow mode, if falling edge is not detected
within the specified time from rising edge detection, PB-CTL is forcibly shut down (slow reset).
The time TFS (s) until the signal falls is the following interval after the rising edge of the internal
CTL signal is detected:
TFS = 16384 × 4/φ s(φs = fOSC/2)
When fOSC = 10 MH z, TFS = 13.1 ms.
Figure 26. 54 shows the PB-CTL waveform in slow mode.
CTL
waveform
Internal
CTL signal
1 frame 1 frame
Slow tracking delaySlow tracking delay
Acceleration AccelerationDeceleration Deceleration
Slow
reset
Stop Stop
CTLP↑CTLP↑
Figure 26.54 PB-CTL Wav efor m in Slow Mode Operation
Rev. 1.0, 02/00, page 707 of 1141
26.13.8 Duty Discriminator
The duty discri minator ci rc uit me a sures the period of the control signal rec orded on the tape (PB-
CT L sig nal) an d discr im i nate s it s d uty cycle . In VISS or VASS detecti o n, the d uty I/O flag is set
or cleared according to the result of duty discrimination. The duty I/O flag is set to 1 when the
duty cycle of the PB-CTL signal is above 44%, and is cleared to 0 when the duty cycle is below
44%.
In ASM dete ct i o n, an ASM mark is reco gnized (and the duty I/O flag is clea red to 0) whe n the
dut y c ycle is above 6 6%. When the duty cycle is below 6 6%, no ASM mark is reco g nize d and the
duty I/O flag is set to 1.
The detection direction can be switched between forward and reverse by bit 5 (FW/RV) in t he
CTL mode register.
Long or short pulse can be detected by comparing REC-CTL duty data register (RCDR2 to
RCDR5) a nd UP/DOWN count e r. Long or short pulse i s discriminated at PB-CTL signa l falling.
Discrimination result is stored in bit 0 of bit pattern register (BTPR). At the same time, BTPR is
shifted to the left. LSP0 indicates 0 when short pulse is detected, and 1 when long pulse is
detected.
Set the thre shold value of long/ short pul se in RCDR2 to RCDR5. See the de scription on the
detection of the long/ short pul se.
Figure 26. 55 shows the dut y cycle of the PB-CTL signal.
Rev. 1.0, 02/00, page 708 of 1141
Input signal
Short 1 pulse
25±0.5%
PB-CTL
Input signal
Long 1 pulse
30±0.5%
PB-CTL
Input signal
Short 0 pulse
57.5±0.5%
62.5±0.5%
PB-CTL
Input signal
Long 0 pulse
PB-CTL
Input signal
ASM mark
67 to 70%
PB-CTL
Figure 26.55 PB-CTL Signal Duty Cyc le
Rev. 1.0, 02/00, page 709 of 1141
Figure 26. 56 shows the dut y discrimination c ircuit. A 44% dut y cycle is discriminated by
counting with the 16-bi t up/down counter, using a φs/4 clock for the up-count and a φs/5 clock for
the down-c ount. An up-count is performed when the PB-CTL signal is high, and a down-count
when low. Long or short pulse is discriminated by comparing with RCDR2 to RCDR5.
Counter
PB-CTL
1 pulse
PB-CTL↑
PB-CTL
φ s/4 φ s/5
Counter
PB-CTL
0 pulse
φ s/4
φ s/5
Counter
FWD
PB-CTL
Short pulse
(0 pulse)
φ s/4
φ s/5
RCDR3
RCDR2
0 pulse L/S threshold value
1 pulse L/S threshold value
Counter
REV
PB-CTL
Long pulse
(1 pulse)
φ s/5
φ s/4
RCDR4
RCDR5
0 pulse L/S threshold value
1 pulse L/S threshold value
UP/DOWN
Comparison of upper
12-bit
UP/DOWN counter (16 bits)
* RCDR2or4 (12bit)
* FWD : Discriminated by RCDR2 and RCDR3
REV : Discriminated by RCDR4 and RCDR5
* RCDR3or5 (12bit)
0/1
discrimination
UDF
Clear
R
SQ
φ s/4
φ s/5
L/S
discrimination
Figure 26.56 Duty Discriminator
Rev. 1.0, 02/00, page 710 of 1141
VISS (Index ) Detec t Mode: VISS detection is carr ied out by the VISS control cir cuit, which
counts 1 pulses in the PB-CTL signa l. If the pulse count de t ects any value set i n the VISS
interrupt set ting bit s (bits 5, 6, or 7 in the duty I/ O register), an i nterrupt request is generated a nd
the duty I/O flag is cleared to 0.
At VISS record or rewrite, INDEX c ode is automatically wri t ten. INDEX code is composed of 0
continuous 62-bit data with 0 pulse data at both e dge.
Examples of bit strings and the duty I/O flag at VISS detection/record is illustrated in figure 26.57.
0Tape direction
Duty I/O flag
(a) VISS detection (INDEX: Thirty-two 1 pulse setting)
1111
61±3 bits
Thirty-two 1 pulses
detected
IRRCTL
63±3 bits
Start
11110
0Tape direction
Duty I/O flag
(b) VISS record
1111
62 bits
IRRCTL
64 bits
Start
11110
1 2 3 62 63 64
Fig ure 26.57 Exampl e s of VISS Bit Strings and Duty I/O Flag
Rev. 1.0, 02/00, page 711 of 1141
Duty De tection Mode (VASS): VASS det ec ti on i s ca rried out by the dut y di scrim i nator.
Software c an detect index sequences by reading the duty I/O flag at each CTL pulse.
At each CTL pulse, the duty discriminator sends the result of duty discrimination to the duty I/O
flag, and simultaneously generates an interrupt request. The duty I/O flag is cleared to 0 if the
CTL pul se is a 1 (dut y cycle bel ow 44%), and is set to 1 if the CTL pulse i s a 0 (duty c ycle above
44%).
The duty I/O flag is modi fied a t each CTL pulse. It should be read by the interrupt-ha ndling
routi ne within the perio d of the PB-CTL signal . VASS detect ion for mat i s illu st rate d in figure
26.58.
1
Tape direction Written three times
1111111111
M
S
BL
S
BL
S
B
M
S
BM
S
BL
S
BL
S
B
M
S
B
ThousandsHeader (11 bits) Hundreds
Data (16 bits: 4 digits of 4-bit BCD)
Tens Ones
Fi g ure 26.58 VASS (Index ) Form at
Assemble (ASM ) Mark Detec t Mo de : ASM mark detection is carrie d out by the duty
discriminator. If the duty discriminator de tects that the duty cycle of the PB-CTL signa l is 66% or
higher, it generates an interrupt request, and simultaneously clears the duty I/O flag to 0.
The duty I/O flag is updated at e very CTL pulse. It should be read by the i nterrupt-handling
routine within the pe riod of the PB-CTL signal.
Rev. 1.0, 02/00, page 712 of 1141
Detection of the Long/Short Pulse: The long/short pul se is dete cted in PB mode by the L/S
determination based on the com parison of the REC-CTL duty regi ster (RCDR2 t o RCDR5) with
the up/down counter and the results of the duty I/O flag. The results of the determination is stored
in bit 0 (LSP0) of the bit pattern register (BT PR) a t the ri sing edge of PB-CT L, shifting at the
same time BTPR leftward.
RCDR2-5 set the L/ S threshol ds for e ach of FWD/REV. Set to RCDR2 a thre shold of 1 pulse L /S
for FW D, to RCDR3 a threshold of 0 pulse L /S for FWD, to RCDR4 a threshold of 0 pulse L/S for
REV, and to RCDR5 a threshold of 1 pulse L/S for REV. Fi gure 26.59 shows the detection of
long/short pul se.
Also, the bit pattern of 8-bit can be det ected by BTPR. Chec k that an 8-bit detection has been
done by bit 1 (BPF bit) of the duty I/O register, and then read BTPR.
Bit patter register (8 bits)
Up/Down counter (16-bit)
RCDR2 (12bit)
High-order 12-bit data
L/S is determined at the rising edge of PB-CTL.
After the determination, bit pattern register is
shifted leftward, and the results of the determination
is stored in the LSB.
RCDR3 (12bit)
Internal bus
LSB
FW/RV DI/O
Shift left-wardBTPR
R
R
SQ
RCDR4 (12bit)
RCDR5 (12bit) R
SQ
φs/4
Note:
Figure 26.59 Detection of Long/Short Pulse
Rev. 1.0, 02/00, page 713 of 1141
26.13.9 CTL Output Sec ti on
An on-chip control head amplifier is provide d for writing the REC-CTL signal genera ted by the
write control circuit onto the tape.
The write control circuit controls the duty cycle of the REC-CTL signal in the writing of VISS and
VASS sequ e nces and ASM marks and the rewriting of VISS and VASS seque nce s. The duty
cycle of t he REC-CTL signal is set in REC-CTL duty data regist ers 1 t o 5 (RCDR1 t o RCDR5).
Times calc u la ted in terms o f φs (= fOSC/ 2) should be converted to appropriate data to be set in t hese
re gister s. In VISS or VASS mode, set RCDR 2 for a duty cy cle of 25% ±0.5%, RCD R3 for a duty
cycle of 30% ±0.5%, RCDR4 for a duty cycle of 57.5 ±0.5%, and RCDR5 for a dut y cycle of 62.5
±0.5%. When 1 is written in the duty I/O flag, the REC-CTL signal will be written on the tape
with a 25% ±0.5% duty cycle when 0 is written in bit 7 (LSP7) in the bit pattern register (BTPR)
and with a 30 ±0.5% duty cycle when 1 is written. Table 26.21 shows the relationship between
the REC-CTL duty re gister and CTL out puts.
In ASM ma rk write mo de, se t RC DR3 for a duty cycle o f 67% to 70%. An ASM mark wil l be
written when 0 is written in the duty I/O flag.
An interrupt reque st is generated a t the rise of the reference signal after one CTL pulse has been
written. T he refe rence signal i s derived from the output signal (RE F30X) of the X-value
adjustment circ uit, and has a period of one fram e.
Figure 26. 60 shows the timi ngs that ge nerate the REC-CTL signa l.
Table 26. 21 REC-CTL Duty Register and CTL Outputs
MODE D/IO LSP7 Pulse RCDR Duty
0 S1 RCDR2 25 ±0.5%
0
1 L1 RCDR3 30 ±0.5%
0 S0 RCDR4 57.5 ±0.5%
VISS, VASS modes
11 L0 RCDR5 65.5 ±0.5%
ASM mode 0 * RCDR3 60 to 7 0%
Note: * Don't care.
Rev. 1.0, 02/00, page 714 of 1141
W
Internal bus
RCDR2or4
(12 bits)
W
RCDR1
(12 bits)
UP/DOWN counter (12 bits)
Counter
REF30X
REC-CTL
Counter
reset
Match detection
Match detection
End of writing of one CTL
pulse (except VISS) IRRCTL
RCDR2 (VISS/VASS S1 pulse)
RCDR3 (VISS/VASS L1 pulse, or ASM)
RCDR4 (VISS/VASS S0 pulse)
RCDR5 (VISS/VASS L0 pulse)
RCDR1
Clear
Upper 12 bits
REC-CTL 0 pulse fall
timing
REC-CTL rise timing REC-CTL1 pulse,
ASM fall timing
RESET
REF30X↑W
RCDR3or5
(12 bits)
φs/4
Compare Compare Compare
Figure 26.60 REC-CTL Signa l Gen eration Tim ing
Rev. 1.0, 02/00, page 715 of 1141
The 16-bit counter in the REC-CTL circuit continues c ounting on a clock deri ved by divi ding the
system clock φs (= fOSC/2) by 4 . The co un ter is cleared o n th e rise of R EF 3 0 X in r eco rd mode, and
on the rise of PB-CTL in rewrite mode. REC-CTL match detection is carried out by comparing
the counter value with each RCDR value.
RCDR1 t o RCDR5 can be written to by software at all times. If RCDR i s changed be fore the
respective match detection i s performed, ma tch det ection is performed using the ne w value. The
value changed after match detection becomes valid on the rise of REF30X following the change.
Figure 26. 61 shows examples of RCDR c hange ti ming.
REF30X
REC-CTL RCDR1 RCDR2 RCDR1
1 pulse (Short) 0 pulse (Short) Rewritten 0 pulse
(Short)
RCDR1 RCDR1
Counter RCDR4
RCDR2
RCDR1
RCDR4 RCDR4
RCDR4
Interval in which
RCDR4 can be
written to
Fig ure 26.61 Exampl e of RCDR Change Ti mi ng (Example Showi ng RCDR4)
Rev. 1.0, 02/00, page 716 of 1141
26.13.10 Trapezoid Wave form Circuit
In rewriting, t he trapezoid wa veform c i rcuit l eaves the rising edge of the already-recorded PB-
CTL signal intact, but changes the duty cycle.
In rewriting, the CTL pulse is written with reference to the rise of PB-CTL. The CTL duty cycle
for a re write is set in the REC-CTL duty data regi sters (RCDR2 to RCDR5). T ime values T2 to
T5 are referenced to the rise of PB-CTL.
Figure 26. 62 shows the rewrite wa veform.
W
Internal bus
RCDR3or5
(12 bits)
W
Not used when
rewriting
RCDR2or4
(12 bits)
Up/Down counter (16 bits)
Clear
Upper 12 bits
REC-CTL 0 pulse
fall timing
REC-CTL 1 pulse
fall timing
RESET
PB-CTL↑W
T
2
to T
5
Eliminated
pulse
High-impedance
interval
End of writing of one
CTL pulse (except
VISS) IRRCTL
RCDR1
(12 bits)
φs/4
Compare Compare
RCDR2 (BISS/VASS S1 pulse)
RCDR3 (VISS/VASS L1 pulse)
RCDR4 (VISS/VASS S0 pulse)
RCDR5 (VISS/VASS L0 pulse)
PB-CTL
REC-CTL when
rewriting
New pulse
Fi g ure 26.62 Relati o nshi p betwee n REC-CTL and RCDR2 to RCDR5 when Rewriting
Rev. 1.0, 02/00, page 717 of 1141
26.13.11 Note on CTL Interrupt
After a reset, the CTL circuit is in the VISS discrimination input mode.
Depending on the CTL pin states, a false PB-CTL input pulse may be recognized and an interrupt
request ge nerated. If the interrupt request will be e nabled, first clear the CTL i nterrupt re quest
flag.
Rev. 1.0, 02/00, page 718 of 1141
26.14 F requency Dividers
26.14.1 Overview
On-chip fre quency divi ders are provi ded for the pulse signal pi c ked up from the control t rack
during pla yback (t he PB-CTL signa l ), and the pul se signal re ceived from the c apstan mot or (CFG
signal). The CTL freque ncy divider gene rates a CTL divided control si gnal (DVCTL) from the
PB-CTL signal, for use in capstan phase control duri ng high-speed sea rch, for example. The CFG
frequency divider generates two divided CFG signals (DVCFG for speed control and DVCFG2 for
phase control) from the CFG signal. The DFG noise c anceller i s a circuit which considers si gnal
less than 2φ as noise and mask it.
26.14.2 CTL Fr equency Divider
Block Diagram: Figure 26.63 shows a block diagram of t he CTL frequency divi der.
EXCTL
PB-CTL↑↑, ↓DVCTL
UDF
R/W W
(8 bits)
R/W Internal bus
CEX
CTL division register
Down counter (8 bits)
CEG
Edge
detector
CTVC CTLR
CTVC
Figure 26.63 CTL Frequency Divider
Register Descr i ptio n
− Regist er conf igur at ion
Table 26. 22 shows the re gister c onfiguration of the CTL freque ncy dividers.
Table 26. 22 Register Configur ation
Name Abbrev. R/W Si z e Initi al Value Addr ess
DVCTL control r egister CTVC R/W Byte Undef ined H'D098
CTL frequency division
register CTLR W Byte H'00 H'D099
Rev. 1.0, 02/00, page 719 of 1141
DVCTL Cont rol Re gist e r (CT VC)
0
*
1
*
R
2
*
R
345
67
R
CFG HSW
0
W
0
W
CEX CEG CTL
111
Bit :
Initial value :
R/W :
CTVC consists of the ext e rnal input signal selection bit s and the fl ags whic h show the CFG,
HS W, and CTL levels.
Note: It has an undet ermined val ue by a reset or in stand-by mode.
Bit 7DVCTL Signa l Gener ati on Selection Bit (CEX) : Select s whic h of the PB-CTL signal or
the external input signal is used to gene rate the DVCTL signal.
Bit 7
CEX Description
0 Generates DVCTL signal with PB-CTL signal (Init ial value)
1 Generates DVCTL signal with external input signal
Bit 6External Sync Signal Edge Selection Bit (CEG): Selects the edge of the external signal
at which the frequency division is made when the external signal was selected to generate DVCTL
signal.
Bit 6
CEG Description
0 Rising edge (Initial value)
1 Falling edge
Bits 5 to 3Reserved: Cannot be modifi ed and are always re ad as 1.
Bit 2CFG Flag (CFG): Shows t he CFG level.
Bit 2
CFG Description
0 CFG is at low level (Init ia l value)
1 CFG is at high level
Rev. 1.0, 02/00, page 720 of 1141
Bit 1HSW Flag (HSW): Shows the level of the HSW signal sel ecte d by the VFF/ NFF bit of the
HSW m ode register 2 (HSM2).
Bit 1
HSW Description
0 HSW is at low lev e l ( Initial value )
1 HSW is at high level
Bit 0CTL Flag (CTL): Sho w s the CT L leve l.
Bit 0
CTL Description
0 REC or PB- CTL is at low leve l (I n itial value)
1 REC or PB-CTL is at high level
CTL Frequency Division Re gister (CTLR)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7CTL4 CTL3 CTL2 CTL1 CTL0
0
W
CTL7
WWW
CTL6 CTL5
Bit :
Initial value :
R/W :
CTLR i s an 8-bit wri te-only register to set the frequency dividing value (N-1 if di vided by N) for
PB-CTL. If a read is attempted, a n undetermine d value is read out.
PB-CTL is divided by N at its rising edge. If the register val ue is 0, no division ope ration is
performed, a nd the DVCTL signal with the same cycle with PB-CT L is output. It is initialized by
a reset or in stand-by mode.
Rev. 1.0, 02/00, page 721 of 1141
Operation: Duri ng playback, c ontrol pul ses recorded on the tape are picked up by the cont rol
head and input to the CTL pin. The control pulse signal is amplified by a Schmitt amplifier,
reshaped, then input t o the CT L frequenc y divide r as t he PB-CTL signa l.
This circuit is employed when the control pulse (PB-CTL signal) is used for pha se control of the
capstan motor. The divided signal is sent as the DVCTL signal to the capstan phase system in the
servo circuits and timer R.
The CTL frequency di vider i s an 8-bit re l oad timer consisting of a reload regi ste r a nd a down-
counter. Frequency di vision is obtained by setting frequency-division data in bits 7 t o 0 i n the
CTL frequency division register (CTLR), whic h is the re l oad regi ster. W hen a frequency di vision
value is written in this reload register, it is also written into the down-counter. The down-counter
is decremented on rising edges of the PB-CTL signal.
Figure 26. 64 shows examples of the PB-CTL and DVCTL waveforms.
CTL input signal
CTLR: CTL frequency division register
PB-CTL or external
sync signal
CTLR=00
CTLR=01
CTLR=02
Figure 26.64 CTL Frequency Division Wavefor ms
Rev. 1.0, 02/00, page 722 of 1141
26.14.3 CFG Frequency Divider
Block Diagram: Figure 26.65 shows a block diagram of t he 7-bit CFG fre quency divi de r and it s
mask timer.
WR/WW
W
WWWR
W
Internal bus
CMN
CRF
UDF
UDF
UDF
CFG DVCFG
DVCFG2
↑, ↑↓
MCGin
Internal bus
CPS1,
CPS0
CTMR(6 bits)
CDIVR2(7 bits)
DVTRG
PB(ASM)→REC
φs = fosc/2
φs/1024
φs/512
φs/256
φs/128
Down counter (6 bits)
CDIVR(7 bits)
CMK
S
R
Edge
select
CDVC
CDVC CDVC
CDVC
CDVC
Down counter (7 bits)
Down counter (7 bits)
Figure 26.65 CFG Frequency Divider
Rev. 1.0, 02/00, page 723 of 1141
Register Descr i ptio n:
• Register configuration
Table 26. 23 shows the re gister c onfiguration of the CFG frequency division circuit.
Table 26. 23 Register Configurati on
Name Abbrev. R/W Si ze Initi al Value Addr ess
DVCFG control register CDVC R/W Byte H'60 H'D09A
CFG frequen cy divi sion
register 1 CDIVR1 W Byte H'80 H'D09B
CFG frequen cy divi sion
register 2 CDIVR2 W Byte H'80 H'D09C
DVCFG mask period
register CTMR W Byte H'FF H'D09D
DVCFG Contr ol Regi ster (CDVC)
0
0
1
0
W
2
0
W
34
0
W
5
1
6
—
—
1
7
WR
CMK CMN
W
DVTRG
0
R/W*
MCGin CRF CPS1 CPS0
0
Note: * Only 0 can be written
Bit :
Initial value :
R/W :
CDVC is an 8-bit registe r to cont rol the capsta n frequency division circuit.
It is ini tialized to H'60 by a reset, or in stand-by or module stop m ode.
Bit 7Mask CFG F lag (MCGin): MCGin is a flag to indicate occurrence of a frequency
division signal during the mask t imer's mask peri od. To clear i t by softwa re, write 0 after reading
1. Also, setting has the highe st pri ority in this fla g. If a condition set t ing the flag and 0 write
occur simultaneously, the latter is invalid.
Bit 7
MCGin Description
0 CFG is in normal oper ation (In itial value)
1 Shows tha t DVCF G was detecte d during ma ski ng ( runaway detected )
Bit 6Reserved: Cannot be modified and is always read as 1.
Rev. 1.0, 02/00, page 724 of 1141
Bit 5CFG M ask Status Bit (CMK): Indicates the status of the ma sk. It is initialized t o 1 by a
reset, or in stand-by or module stop mode.
Bit 5
CMK Description
0 Indicates that the capstan mask timer has released m asking
1 Indicates that the capstan mask timer is currently masking (I nitial value)
Bit 4CFG Mask Selection Bit (CMN): Selects th e turning on/off of the mas k function.
Bit 4
CMN Description
0 Capstan mask timer function on. (Initial value)
1 Capstan mask time r function of f.
Bit 3PB (ASM) → REC Transition Timing Sync ON/OFF Selection Bit (DVTRG): Selects
the On / Of f of the timing sync of the tra nsit ion from PB (ASM) to REC when the DVCFG2 signal
is generated.
Bit 3
DVTRG Description
0 PB ( ASM) → REC transition timing sync on. (Init ial value)
1 PB ( ASM) → REC transition timing sync off.
Bit 2CFG Freque ncy Divi sion E dge Selec tio n Bit (CRF ) : Selects the edge of the CFG signal
t o be divided.
Bit 2
CRF Description
0 Performs frequency division at the rising edge of CFG. ( I nit ial value)
1 Performs frequency division at both edges of CFG.
Rev. 1.0, 02/00, page 725 of 1141
Bits 1 and 0CFG Mask Ti mer Cloc k Selection Bi ts (CPS1, CPS0): Selects the clock sourc e
for the CFG ma sk timer. (φs = fosc/2)
Bit 1 Bit 0
CPS1 CPS0 Description
0φs/ 1024 (Init ial value)01φs/512
0φs/25611φs/128
CFG Fre que ncy Division Regi ster 1 (CDIVR1)
0
0
1
0
W
2
0
W
34
0
W
5
0
67
—
—WW
CDV15 CDV14
0
W
CDV16
0
W
CDV13 CDV12 CDV11 CDV10
1
Bit :
Initial value :
R/W :
CDIVR1 is an 8-bit write-only register to set the division value. If a read is attempted, an
undetermined val ue is rea d out. Bit 7 i s reserved.
The frequency division value is written in the reload register and the down counter at the sam e
time.
CFG's frequency is divided by N at its rising edge or both edges If the register value is 0, no
division operation is performed, and the DVCFG signal with the same input cycle with CFG
signal is output. The DVCFG signal is sent t o the capstan spee d error detector. It i s initialized to
H'80 by a rese t or in stand-by mode togeth er with the capstan frequ en cy div ision regist er and the
down counter .
Rev. 1.0, 02/00, page 726 of 1141
CFG Fre que ncy Division Regi ster 2 (CDIVR2)
0
0
1
0
W
2
0
W
34
0
W
5
0
67
—
—WW
CDV25 CDV24
0
W
CDV26
0
W
CDV23 CDV22 CDV21 CDV20
1
Bit :
Initial value :
R/W :
CDIVR2 is an 8-bit write-only register to set the division value. If a read is attempted, an
undetermined val ue is rea d out. Bit 7 i s reserved.
The frequency division value is written in the reload register and the down counter at the sam e
time.
CFG's fre quency is di vided by N at its ri sing e dge or both edges If the register va l ue wa s 0, no
division operation is performed, and the DVCFG signal with the same input cycle with CFG is
output. The DVCFG2 signal is sent to the capstan speed e rror de t ector and the Timer L.
The DVCFG2 circuit has no mask timer function.
The frequency division counter starts its division operation at the point data was written in
CDIVR2. If synchronization is required for phase ma tching, for example, do it by writing i n
CDIVR2. If the DVTRG bit of t he CDVC register is 0, the regi ste r synchronizes wit h the
switching timing from PB (ASM) to REC.
It is initialized to H'80 by a reset or in stand-by mode together with the capstan frequency division
register and the down counter.
DVCFG Mask Period Register (CTMR)
0
1
1
1
W
2
1
W
34
1
W
5
1
67 ——
—— WW
CPM5 CPM4
1
W
CPM3 CPM2 CPM1 CPM0
11
Bit :
Initial value :
R/W :
CTMR is an 8-bit write-only register. If a read is at tempted, an undetermined value is rea d out.
CTMR is a reload register for the mask timer (down counter). Set in i t the mask peri od of CFG.
The mask period is determined by the clock specified by the bits 1 and 0 of CDVC and the set
value (N - 1). If data is written in CTMR, it is written also in the mask timer at the same time.
It is ini tialized to H'FF by a reset, or i n stand-by or module stop mode.
Mask per i od = N × clock cy cle
Rev. 1.0, 02/00, page 727 of 1141
Operation:
• Fr equency divider
The CFG pulses output from the capstan motor are sent to internal circuitry as the CFG signal
via the z ero-cross t ype com parator. The CFG signal, shaped i nto a rectangular waveform by a
reshaping circ uit, is divided by the CFG freque ncy dividers, and used in servo control. The
rising edge or both edges of the CFG signal can be selected for the frequency divide r.
The CFG frequency di vider consists of a 7-bit frequenc y divider with a mask timer for capsta n
speed cont rol (DVCFG signal generator) a nd a 7-bit frequency divider for capstan phase
control (DVCFG2 signal generator).
The DVCFG signal generator consists of a 7-bit re load regi ster (CFG frequency division
register1: CDIVR1), a 7-bit down-counter, and a 6-bit mask timer (with settable mask
interval). Frequency division is performed by setting the frequenc y-division value in 7-bit
CDIVR1. When the fre quency-division val ue is written in CDIVR1, it is also written in the
down-counter. Afte r fre quency-division of a CFG signal for which the edge has been selected,
the signal is sent via the m a sk timer to the capstan spee d error detector as the DVCFG signal.
The DVCFG2 signal generator consists of a 7-bit reload register (CFG fre quency divi sion
register 2: CDIVR2) and a 7-bit down-counter. The 7-bi t frequency divi der does not have a
mask timer. Freque ncy divisi on is pe rformed by setting the fre quency-di vision value in
CDIVR2. When the fre quency-division val ue is written in CDVIR2, it is also written in the
down-counter. Afte r fre quency di vi sion of a CFG signal for which the edge ha s bee n selected,
the signal is sent to t he capstan speed error det ector and ti mer L as the DVCFG2 signal.
Frequency di vision starts when the frequenc y-division value is written.
When DVTRG bit in CDVC register is set to 0, reloading is executed with the switch over
ti mi n g from PB (ASM) mode to REC mode. To switc h from REF3 0 to CREF, change the
settings of bit 4 (CR/RF bit) in the capstan phase error detection c ontrol re gister (CPGCR). If
synchronization is necessary for phase c ontrol, this ca n be provide d by writing the frequency-
division va lue in CDIVR2.
The down-c ounters are decremented on rising edge s of t he CFG signal when the CRF bit is 0
in the DVCFG control regi ster (CDVC), and on both edges when t he CRF bit is 1.
Figure 26. 66 shows examples of CFG frequency division waveforms.
Rev. 1.0, 02/00, page 728 of 1141
CFG
CRF bit=1
CDIVR=00
CRF bit=0
CDIVR=00
CRF bit=0
CDIVR=01
CRF bit=0
CDIVR=02
Figure 26.66 CFG F requency Division Waveforms
Rev. 1.0, 02/00, page 729 of 1141
• Mask time r
The capsta n mask timer is a 6-bit reload ti mer tha t uses a prescale d clock as a clock source .
The mask timer is used for ma sking DVCFG signa l intended for controlling the capstan spe e d.
The capstan mask timer prevents edge detection to be carried out for an unnecessarily long
duration by masking the edge detecti on for a certain peri od. The above trouble can result from
abnormal re volution (runout) of t he capstan mot or be cause its revolution ha s to cover a wide
range speeds from the low/still up to the high speed search.
The capstan mask timer is started by a pulse edge in the divided CFG signal (DVCFG). While
the timer is running, a mask signal disabl e s the output of further DVCFG pulses. The mask
signal is shown in figure 26.67.
The mask timer status can be monitored by reading the CMK flag in the DVCFG control
register (CDVC).
Mask
DVCFG
Mask timer
underflow
Figure 26.67 Mask Signal
Rev. 1.0, 02/00, page 730 of 1141
Figures 26.68 and 26. 69 show exam ples of CFG mask ti mer operations.
CFG (racing)
Edge detect
Cleared by wiring 0
after reading 1
Capstan motor
mask timer Mask interval Mask interval
DVCFG
MCGin flag
Figure 26.68 CFG Mask Timer Operation (When Capstan Motor is Racing)
CFG
Edge detect
Capstan motor
mask timer Mask interval Mask interval
Figure 26.69 CFG M ask Timer Oper ation (When Capstan Motor is Operating Normally)
Rev. 1.0, 02/00, page 731 of 1141
26.14.4 DFG Noise Removal Circuit
Block Diagram: Figure 26.70 shows t he block diagram of t he DFG noise removal circui t.
Rising edge
detection
Delay circuit
DFG SQ
R
NCDFG
delay = 2φ
Falling edge
detection
Figure 26.70 DFG Noise Removal Circuit
Register Descr i ptio n: Table 26.24 shows the register configuration of the DFG mask circuit.
Table 26. 24 Register Configurati on
Name Abbrev. R/W Si ze Initi al Value Addr ess
FG control register FGCR W Byte H'FE H'D09E
FG Control Register (FGCR)
0
0
1
1
2
1
3
1
4
1
5
1
6
1
7
———————
——————— W
DRF
1
Bit :
Initial value :
R/W :
FGCR se le ct s the edge of the DFG noi se removal sign al (NCDFG) to be sent to the drum speed
error detector. If a re ad is attempted, an undetermined value is read out.
It is ini tialized to H'FE by a reset, or in stand-by or module stop mode.
The edge selection circuit is located in the drum speed error detector, and outputs the register
output to the drum speed error det ector.
Bits 7 to 1Reserved: Cannot be modifi ed and are always re ad as 1.
Rev. 1.0, 02/00, page 732 of 1141
Bit 0DFG Edge Selection Bit (DRF): Selects the edge of the NCDFG signal used in the drum
speed error detector.
Bit 0
DRF Description
0 Select s the r ising edge of NCDFG signal (I nit ial value)
1 Select s the falling edge of NCDFG signal
Operation
The DFG n oise remo val cir cui t generates a signal (NCDFG sig nal ) as a result of removi ng noise
(signal fluctuation smaller than 2 φ) from the DFG si gnal. The resulted NCDFG si gnal is behind
the ti me when the DFG signal wa s dete cted b y 2 φ. Fi g ure 26.71 shows the NC DFG si gnal.
DFG
NCDFG
Noise
2φ2φ2φφ = fosc
Fi g ure 26 .71 NCDFG Sig nal
Rev. 1.0, 02/00, page 733 of 1141
26.15 Sync Signal Detector
26.15.1 Overview
This bloc k performs detection of the horizontal sync signal (Hsync) and vertical sync signal
(Vsync) from the com posite sync signal (Csync), noise counting, and field detection.
It detects the horizontal a nd vertical sync signals by setting threshold in the register and based on
the serv o clock ( φs = fosc/2). Noise masking is possible during the detection of the horizontal
sy nc signa ls , and if an y Hs y nc pulse is mis sing, it can b e su pplement ed. Als o , if to tal vol u me of
the noise detected i n one frame of Csync amounted over a speci fied volume, the detector generates
a noise detection interrupt.
Note: This circuit detects a pulse with a specific width set by the threshold register. It does not
classify or restore the sync signal to a formal one.
Rev. 1.0, 02/00, page 734 of 1141
26.15.2 Bloc k Diagram
Figure 26. 72 shows the block diagram of the sync signal det ector.
W
H threshold
register
W
V threshold
register
(6 bits) (4 bits)
HTRVTR
WW
H complement
start time
register Complementary
H pulse width
register
(8 bits) (4 bits)
HPWRHRTR
WW
(6 bits) (8 bits)
NDR
R/W R/WR/(W) R
NOIS
H counter (8 bits)
Noise detector
Complement control &
nozzle mask control circuit
Up/Down
counter (6 bits)
SEPH
Selection of
polarity Noise detection
window
Noise detection interrupt
VD interrupt
Csync
Sync signal detector
H reload counter (8 bits)
Field detector
Noise counter (10 bits)
Toggle
circuit
Clear
FLD SYCT
VD(SEPV)
FIELD
NOISE
IRRSNC
OSCH
NIS/VD
SYNCR
NWR
Internal bus
φs = fosc/2
φs/2
Noise detection
window
register Noise
detection
register
Figure 26.72 Block Diagram of the Sync Signal Dete ctor
Rev. 1.0, 02/00, page 735 of 1141
26.15.3 Pi n Confi guration
Table 26. 25 shows the pi n configuration of the sync signal dete ctor.
Table 26. 25 Pin Configuration
Name Abbrev. I/O Function
Composite sync signal input pin Csync Input Composite sync signal input
26.15.4 Register Configuration
Table 26. 26 shows the re gister c onfiguration of the sync signal detector.
Table 26. 26 Register Configurati on
Name Abbrev. R/W Si ze Initi al Value Addr ess
Vertical sync signal
threshold regis ter VTR W Byte H'C0 H'D0B0
Horizontal sync signal
threshold regis ter HTR W Byte H'F0 H'D0B1
H com plement st art time
setting register HRTR W Byte H'00 H'D0B2
Complem ent H pulse
width setting r egister HPWR W Byte H'F0 H'D0B3
Noise det ection window
setting register NWR W Byte H'C0 H'D0B4
Noise det ector NDR W Byte H'00 H'D0B5
Sync signal control
register SYNCR R/W Byte H'F8 H'D0B6
Rev. 1.0, 02/00, page 736 of 1141
26.15.5 Register Description
Vertical Sync Signal Threshold Regi ster (VTR)
0
0
1
0
W
2
0
W
3
0
4
0
W
5
0
6
1
7——
—— WWW
VTR5 VTR4 VTR3 VTR2 VTR1 VTR0
1
Bit :
Initial value :
R/ W :
VTR is an 8-bit write-only register that sets the threshol d for the vertical sync signal when the
signal is detected from the composite sync signal. The threshold is set by bits 5 to 0 (VTR5 to
VTR0). Bits 7 and 6 are reserved. If a read is attempted, an undetermined value is read out. It is
initialized to H'C0 by a reset, or in stand-by or module stop mode.
Rev. 1.0, 02/00, page 737 of 1141
Hori zontal Sync Signa l Thre shold Register (HT R)
0
0
1
0
W
2
0
W
3
0
456
1
7————
———— WW
HTR3 HTR2 HTR1 HTR0
111
Bit :
Initial value :
R/W :
HTR is an 8-bit write-only register that sets the threshol d for the horizontal sync signal when the
signal is detected from the composite sync signal. The threshold is set by bits 3 to 0 (HTR3 to
HTR0). Bits 7 and 4 are reserved. If a read is attempted, an undetermined value is read out. It is
initialized to H'F0 by a reset , or in stand-by or m odule stop mode.
Figure 26. 73 shows the threshold values a nd sepa rated sync signals.
[Legend]
TH
Hpuls
T H
SEPV
Hpuls : Period of the horizontal sync signal (NTSC: 63.6, PAL: 64 [µs])
: Pulse width of the horizontal sync signal (NTSC, PAL: 4.7 [µs])
VVTH
HVTH : Value set as the threshold of the vertical sync signal
: Value set as the threshold of the horizontal sync signal
SEPV
SEPH : Detected vertical sync signal
: Detected horizontal sync signal (before complement)
T H
SEPH
Csync
H'00
Counter value
1/2 Hpuls
VD interrupt
Hpuls
VVTH
HVTH
Fi g ure 26.73 Threshold Values and Separa ted Sy nc Si gnals
Rev. 1.0, 02/00, page 738 of 1141
Example
The values set to detect the vertical and horizontal sync signals (SEPV, SEPH) from Csync
ar e requ i re d to meet the f oll o wing co ndi ti o ns. Assumed that the set valu e s in VTHR
reg i ste r were VVTH and HVTH,
(VVTH-1) × 2/φs > Hpu l se
(HVTH-2) × 2/φs ≤ Hpulse/2 < (HVTH-1) × 2/φs
Where, Hpulse is pulse width (µs) of the hori zontal sync signal, and φs is servo clock
(fosc/2).
Thus, if φs = 5 MHz, NTSC sy ste m is use d,
(VVTH-1) × 0.4µs > 4.7µs
∴VVTH ≥ H'D
(VVTH-2) × 0.4µs ≤ 2. 35µs < (HVTH-1) × 0.4µs
∴VVTH ≥ H'7
Note: This circuit detects the pulse with the width set in VTHR. If a noise pulse with the width
greater than the set val ue is input, the circuit regards it as a sync signal.
Rev. 1.0, 02/00, page 739 of 1141
H Complem e nt Star t Time Setti ng Regist er (HRTR)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7HRTR4 HRTR3 HRTR2 HRTR1 HRTR0
0
W
HRTR7
WWW
HRTR6 HRTR5
Bit :
Initial value :
R/W :
HRTR is an 8-bit write-only register that sets the timing to gene rate a complement ary pulse if a
pulse of t he horizontal sync signal is m i ssing.
If a read is attempted, an undetermined value is read out. It is initialized to H'00 by a reset, or in
stand-by or module stop mode.
((Value of HRTR7- 0) + 1) × 2/φs = TH
where, TH is the period of the horizontal sync signal (µs), an d φs is the servo cl oc k (fosc/ 2).
Whether the horizontal sync signal exists or not is determined one clock before the
complementary pulse is generated. Accordingly, set to HRTR7 to HRTR0 a value obtained from
the equation shown a bove plus one.
Also, HRTR7-HRTR0 set s the noise ma sk period. If the horizontal sync signal has the normal
pulses, it is masked in the mask period.
The start and the end of the mask period are computed frm the rising edge of OSCH and SEPH,
respectively. Se e figure 26.75.
Com p lementary H Pulse Widt h S et t in g Registe r ( HPWR)
0
0
1
0
W
2
0
W
3
0
456
1
7————
———— WW
HPWR3 HPWR2 HPWR1 HPWR0
111
Bit :
Initial value :
R/W :
HRWR is an 8-bit write-only register that sets the pulse width of the complementary pulse which
is generated if a pulse of the horizonta l sync signal is missing. Bits 7 to 4 are re served.
If a read is attempted, an undetermined value is read out. It is initialized to H'F0 by a reset or in
stand-by mod e.
((Value of HPWR3-0) + 1) × 2/φs = Hp ulse
Where, Hpuls is the pulse width of the horizontal sync signal (µs), and φs is the servo clock
(fosc/2).
Rev. 1.0, 02/00, page 740 of 1141
Noise Detect ion Window Sett i ng Regist er (NWR)
0
0
1
0
W
2
0
W
3
0
4
0
W
5
0
6
1
7——
—— WWW
NWR5 NWR4 NWR3 NWR2 NWR1 NWR0
1
Bit :
Initial value :
R/W :
NWR is an 8-bit write-only register that sets the period (window) when the drop-out of the
horizontal sync signal pulse is de tected and the noi se is counted. Set the timing of the noise
detection window in bits 5 to 0. Bits 7 a nd 6 are rese rved.
If a read is attempted, an undetermined value is read out. It is initialized to H'C0 by a reset, or in
stand-by or module stop mode.
Set the val ue of the noise detection window timing ac cording to the following equation.
((Value of NWR5- 0) + 1) × 2/φs = 1/4 × TH
Where, T H is the pulse width of the horizontal sync signal (µs), and φs is the se rvo clock (fosc / 2).
It is recommended that this timing value is set at about 1/4 of the cycle of the horizontal sync
signal.
Noise Detect ion Regi ster (NDR)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7NDR4 NDR3 NDR2 NDR1 NDR0
0
W
NDR7
WWW
NDR6 NDR5
Bit :
Initial value :
R/W :
NDR is an 8-bit write-only register that sets the noise detection level when the noise of the
horizontal sync signal i s detected (when NW R is set). Set the noise detection level in bits 7 t o 0.
No read is valid. If a read is attempted, an undetermined value is read out. It is initialized to H'00
by a re set, or i n stand-by or module stop mode.
The noise det ector takes c ounts of the drop-outs of the horizontal sync signal pulses and the noi se
within t he pulses, and if they a m ount to a count greater tha n four times of the value set in NDR7-
NDR0, the detector sets the NOIS flag in the sync signal control register (SYNCR). Set the noise
detection level at 1/4 of the noise counts in one frame.
The noise counter is cleared whenever Vsync is detected twice.
See section 26.15. 6, Noise Detection for the details of the noise detection window and the noise
detection level.
Rev. 1.0, 02/00, page 741 of 1141
Sync Signal Co ntrol Regi ster (SYNCR)
0
0
1
0
R
2
0
R/(W)*
3
1
456
1
7————
———— R/WR/W
NIS/VD NOIS FLD SYCT
111
Note: * Only 0 can be written
Bit :
Initial value :
R/W :
SYNCR is an 8-bit register that controls the noise detection, field detection, polarity of the sync
signal input, etc.
It is ini tialized to H'F8 by a reset, or in stand-by mode. Bits 7 t o 4 a re reserve d. No write is valid.
Bit 1 i s read-only.
Bits 7 to 4Reserved: Cannot be modifi ed and are always re ad as 1.
Bit 3Interrupt Selec tio n Bit (NIS/ VD) : Selects whether an interrupt request is generated by
noise level detection or VD si gnal detection.
Bit 3
NIS/VD Description
0 Int errupt at the noise level
1 Int errupt at VD ( I nitial value)
Bit 2Noise Detection Flag (NOIS): NOIS is a status fla g indicating that the noi se counts
reached a t more t han four times of t he val ue set i n NDR. T he flag is cleared only by writing 0
after reading 1. Care is required because it is not cleared automatically.
Bit 2
NOIS Description
0 Noise count is smaller than four times of the value set in NDR ( I nit ial value)
1 Noise count is the same or greater than four times of the value set in NDR
Rev. 1.0, 02/00, page 742 of 1141
Bit 1Field Detection Flag (FLD): Indicates whether the field curre ntly bei ng scanned is even
or odd. See figure 26.74.
Bit 1
FLD Description
0 Odd field (Init ial value)
1 Even field
Bit 0Sync Signal Polarity Se lection Bi t (SYCT): Se lects the polarity of the sync signal
(Csync) to be input.
Bit 0
SYCT Description Polarity
0(Init ial value) Positive
1Negative
Rev. 1.0, 02/00, page 743 of 1141
Field detection
flag (FLD)
SEPV
Noise detection
window
Composite sync
signal
Even field
(a) Even field
Field detection
flag (FLD)
SEPV
Noise detection
window
Composite sync
signal
Odd field
(b) Odd field
Figure 26.74 Field Detection
Rev. 1.0, 02/00, page 744 of 1141
26.15.6 Noise Detection
If a pulse of the horizontal sync signal is missing, a complementary pulse is set at the timing set in
HPWR and with the set pulse wi dth .
Set the noise detection wi ndow wit h HWR of about 1/ 4 of the horizontal sync signa l, and the pulse
with equal high and low periods will be obtained.
Example of Setting: Assumed th at a compleme ntary pulse i s set whe n fosc = 10MHz under the
conditions φs = 5 MHz, NTSC :TH = 6 3.6 (µs) and Hpuls = 4.7 (µs), the set values of the
complementa ry pulse timing (HRTR7-0), complementary pulse wi dth (HPWR3-0), and noise
detection window timing (NWR5-0) are expressed by the following equa tions.
(Value of HRTR7-0) × 2/ φs = TH
((Value of HPW R3-0) + 1) × 2/ φs = Hpuls
((Value of NWR5-0) + 1) × 2/φs = 1/4 × TH
Where, TH is the cycle of the horizontal sync signal (µs), Hpuls is the pulse widt h of t he
horizontal sync signal (µs) an d φs is the servo cloc k (Hz) (fosc/2).
Accordingly,
(Value of HRTR7-0) × 0.4 (µs) = 63.6 (µs)
∴HRTR7-0=H'9F
((Value of HPW R3-0) + 1) × 0. 4 (µs) = 4.7 ( µs)
∴HRTR3-0=H'B
((Value of NWR5-0) + 1) × 0.4 (µs) = 16 (µs)
∴NWR5-0=H'27
Also, the noise mask period is computed as follows.
((Value of HRTR7-0) + 1) − 24) × 2/φs = 54 (µs)
Where, 24 i s a constant required for a structural reason.
Figure 26. 75 shows the set period for HRTR, HPWR, and NWR.
Rev. 1.0, 02/00, page 745 of 1141
[Legend]
SEPH
Noise detection
window
Noise mask for
OSCH
OSCH
Noise mask for
H counter
H reload
counter
H counter
SEPH
c
OSCH : Horizontal sync signal after detection
: Horizontal sync signal after complement
a
b : Value set for the noise detection window (NWR5 to NWR0)
: Value set for the pulse width of the horizontal sync signal (NPWR3 to NPWR0)
c
a, b, c : Value set for complement timing (HRTR7 to HRTR0)
: Complements of 1 of a,b,c, respectively
H ' E 8
TH
:Complement of 2 of multiplier 24 in the equation for the noise mask period
(The noise mask period ends 24 counts before the overflow of H reload counter.)
: Cycle of the horizontal sync signal
(NTSC:63.6 [ms], PAL:64[ms])
TM : Timing at which the noise mask period ends.
A horizontal sync
pulse is missing The pulse in the mask
period is ignored
TH
a
b
H'00
OVF
H'E8
c
a
Mask
period
Period determined
by NWR5 to NWR0
Mask
period
TM
Mask
period Mask
period
Mask
period Mask
period Mask
period Mask
period
TH
Don't mask
immediately
after
complement.
period deter-
mined
by a and a
Period determined
by HRTR7 to HRTR0
period determined
by c and H'E8
Period determined
by HPWR3 to HPER0
period
determined
by b
Do mask also im-
mediately after
complement.
Figure 26.75 Set Pe riod for H RTR, HPWR, and NWR
Rev. 1.0, 02/00, page 746 of 1141
Noise Detection Operation: The noise detector considers an irregular pulse of the composite sync
signal (Csync) and a chip of a horizontal sync signal pulse within a frame as noise. The noise
counter ta kes counts of the irregular pul ses during the high peri od of the noi se detection window
and the chips and drop-outs of the horizontal sync signal pulses during the l ow period. The noi se
detector counts more than one irregul ar pulses as one. The noise count er is cleared at every fra me
(Vsync is detected twice).
The equalizing pulse contained in 9H of the vertical sync signal is counted also as an irregular
pulse.
The noise det ection flag (NOIS) in the sync signal control register (SYNCR) is set to 1 if the count
of the irregular pulse s + t he count of the pulse chips a nd drop-outs of the horizontal sync signal >
4 × (value of NDR7 to 0).
See the description on the sync signal control register (SYNCR) is section 26.15.5, Register
Description, for the NOIS bit.
Figure 26. 76 shows the ope ration of the noise detection.
Csync
Noise detection
window
Noise detection
flag (NOIS)
Noise counter
Noise detection
level
Noise detection
flag is set.
NOIS : Bit 3 of the sync signal control register (SYNCR)
Noise
Figure 26.76 Operation of the Noise Detection
Rev. 1.0, 02/00, page 747 of 1141
26.15.7 Activation of the Sync Signal Detector
After release of reset or transition from the power down mode to the active mode, the sync signal
detector starts operation by a sync signal input after release of module stop. The pulse of the
polarity spec ified by the SYCT bit of t he sync signal c ontrol re gister (SYNCR) is i nput to t he
detector. The detector starts operation even if this pulse is a noise pulse with a width smaller than
the regular width. The minimum pulse width which can activate the detector is not constant
depending on the int ernal ope ration of the input circuit. Accordi ngly, if the assure d activation of
the detector is required, input a pulse with a width greater than 4/φs (φs = fosc/ 2 (Hz)). In such a
case, care is requir ed to no ise, because even a pulse with a wid th s maller th an 4 φ/s may cause
activation.
Rev. 1.0, 02/00, page 748 of 1141
26.16 Servo Int errupt
26.16.1 Overview
The interrupt exception processing of the se rvo module is started by one of ten factors, i. e. the
drum spee d error detector (×2), drum phase e rror detector, capst a n speed error detector ( ×2),
capstan phase error detector, HSW timing generator (×2), sync det ector, and CT L circui t. For
these interrupt factors, see each of their circuit sections of this ma nual.
For details of exception processing, see section 5, Exception Handling.
26.16.2 Register Configuration
Table 26. 27 shows the list of t he registers whi ch control the interrupt of the servo se ction.
Table 26.27 Registers which Control the Interrupt of the Servo Section
Name Abbrev. R/W Si z e Initi al Value Addr ess
Servo interrupt
enable register 1 SIENR1 R/W Byte H'00 H'D0B8
Servo interrupt
enable register 2 SIENR2 R/W Byte H'FC H'D0B9
Servo inter r upt request
register 1 SIRQR1 R/W Byte H'00 H'D0BA
Servo inter r upt request
register 2 SIRQR2 R/W Byte H'FC H'D0BB
26.16.3 Register Description
Ser v o Interr upt Enabl e Regist er 1 (SIE NR1 )
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7IECAP3 IECAP2 IECAP1 IEHSW2 IEHSW1
0
R/W
IEDRM3
R/W R/WR/W
IEDRM2 IEDRM1
Bit :
Initial value :
R/W :
SIENR1 i s an 8-bit read/wri t e registe r that enabl e s or di sables interrupts in the servo section. It is
initialized to H'00 by a reset, or in stand-by or modul e stop mode.
Rev. 1.0, 02/00, page 749 of 1141
Bit 7Drum Phase Error Dete ction Interrupt Enabl e Bit (IEDRM 3)
Bit 7
IEDRM3 Description
0 Disables the request of the interrupt by IRRDRM3 (Init ial value)
1 Enables the request of the interrupt by IRRDRM3
Bit 6Drum Speed Err or Detec tio n (Loc k Detec tio n) Interr upt E nable Bi t (IEDRM2)
Bit 6
IEDRM2 Description
0Disables the request of the interrupt by IRRDRM2 (I nitial value)
1 Enables the request of the interrupt by IRRDRM2
Bit 5Drum Speed Err or Detec tio n (OVF, La tch) Int er r upt Enable Bit (IEDRM1)
Bit 5
IEDRM1 Description
0Disables the request of the interrupt by IRRDRM1 (I nitial value)
1 Enables the request of the interrupt by IRRDRM1
Bit 4Capstan Phase Error Detection Interrupt Enable Bit (IECAP3)
Bit 4
IECAP3 Description
0 Disables the request of the interrupt by IRRCAP3 (I nitial value)
1 Enables the request of the interrupt by I RRCAP3
Bit 3Capsta n Spee d Error De tecti o n (Lock Detect i o n) Interr upt Enable Bit (IECAP2 )
Bit 3
IECAP2 Description
0Disables the request of the interrupt by IRRCAP2 (I nitial value)
1 Enables the request of the interrupt by I RRCAP2
Rev. 1.0, 02/00, page 750 of 1141
Bit 2Capstan Speed Err or Detection (OVF, Latch) Inte rrupt Enable Bit (IECAP 1)
Bit 2
IECAP1 Description
0Disables the request of the interrupt by IRRCAP1 (I nitial value)
1 Enables the request of the interrupt by I RRCAP1
Bit 1HSW Timing Generation (counter clear, capture) Interrupt Enable Bit (IEHSW2)
Bit 1
IEHSW2 Description
0Disables the request of the interrupt by IRRHSW2 ( Initial value)
1 Enables the request of the interrupt by IRRHSW2
Bit 0HSW Timing Ge ner a tio n (OVW, Ma tching, ST RIG) Interr upt E nable Bit (IEHSW1)
Bit 0
IEHSW1 Description
0 Disables the request of the interrupt by IRRHSW1 (Initial value)
1 Enables the request of the interrupt by IRRHSW1
Rev. 1.0, 02/00, page 751 of 1141
Ser v o Interr upt Enabl e Regist er 2 (SIE NR2 )
0
0
1
0
R/W
23456
1
7——————
—————— R/W
IESNC IECTL
11111
Bit :
Initial value :
R/W :
SIENR2 i s an 8-bit read/wri t e registe r that enabl e s or di sables interrupts in the servo section. It is
initialized to H'FC by a reset , stand-by or module stop.
Bits 7 to 2Reserved: Cannot be modifi ed and are always re ad as 1.
Bit 1Vertic a l Sync Si gnal Interr upt Ena ble Bi t (IESNC)
Bit 1
IESNC Description
0Disables the request of the interrupt (int errupt to t he vertical sync signal) by
IRRSNC (Init ial value)
1 Enables the request of the int errupt by I RRSNC
Bit 0CTL Interrupt Enable Bit (IECTL)
Bit 0
IECTL Description
0 Disables the request of the interrupt by IRRCTL (Initial value)
1 Enables the request of the interrupt by IRRCTL
Rev. 1.0, 02/00, page 752 of 1141
Ser v o Interr upt Reque st Register 1 (SIRQR1)
0
0
1
0
R/(W)*
2
0
R/(W)*
3
0
4
0
R/(W)*
0
R/(W)*
56
0
7IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1
0
R/(W)*
IRRDRM3
R/(W)*R/(W)*R/(W)*
IRRDRM2 IRRDRM1
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
SIRQR1 is an 8-bit read/write registe r that indicates interrupt request in t he servo section. If the
interrupt re quest has occ urred, the corre sponding bit i s set to 1.
Only 0 can be writ ten to clear the flag. It is initialized to H'00 by a reset , or in stand-by or module
stop mode.
Bit 7Drum Phase Erro r Detecto r Inter r upt Reque st Bit (IRRDRM3)
Bit 7
IRRDRM3 Description
0 No inter r upt request f r om the drum phase error detect or. ( I nitial value)
1 Interrupt requested from the drum phase error detector.
Bit 6Drum Speed Error Detector (Lock Detection) Interrupt Request Bit (IRRDRM2)
Bit 6
IRRDRM2 Description
0No interrupt request from the drum speed error detector (lock detection).
(Init ial value)
1 Interrupt requested from the drum speed error detector ( lock detection).
Bit 5Drum Speed Err or Detec t or (OVF, Latch) Interr upt Re quest Bit (IRRDRM 1)
Bit 5
IRRDRM1 Description
0 No interrupt request from the drum speed err or detector (OVF, latch).
(Init ial value)
1 Interrupt requested from the drum speed error detector ( OVF, lat ch).
Rev. 1.0, 02/00, page 753 of 1141
Bit 4Capsta n Phase Err or Detec tor Int er r upt Reque st Bit ( IRRCAP3)
Bit 4
IRRCAP3 Description
0 No interrupt request from the capstan phase error detector. (Init ial value)
1 Interrupt requested from the capstan phase error det ector.
Bit 3Capsta n Spee d Error De tector ( Lock Detec t i o n) Interr upt Request Bit (IRRCAP 2)
Bit 3
IRRCAP2 Description
0No interrupt request from the capstan speed error detector (lock detection).
(Init ial value)
1 Interrupt requested from the drum speed error detector ( lock detection).
Bit 2Drum Speed Err or Detec t or (OVF, Latch) Interr upt Re quest Bit (IRRCAP 1)
Bit 2
IRRCAP1 Description
0No interrupt request from the capstan speed error detector (OVF, latch).
(Init ial value)
1 Interrupt requested from the capstan speed err or detector (OVF, latch).
Bit 1HSW Timi ng Gener a to r (Co unter C lea r, Capture) Interrup t Permissi o n Bit
(IRRHSW2)
Bit 1
IRRHSW2 Description
0 No interrupt request from the HSW timing gener ator (counter clear, capture).
(Init ial value)
1 Interrupt requested from the HSW timing gener ator (counter clear, capture).
Rev. 1.0, 02/00, page 754 of 1141
Bit 0HSW Timing Generator (OVW, Matching, STRIG) Interrupt Permission Bit
(IRRHSW1)
Bit 0
IRRHSW1 Description
0 No interrupt request from the HSW timing gener ator (OVW, matching, STRIG).
(Init ial value)
1 Interrupt requested from the HSW timing gener ator (OVW , matching, STRIG).
Rev. 1.0, 02/00, page 755 of 1141
Ser v o Interr upt Reque st Register 2 (SIRQR2)
0
0
1
0
R/(W)*
23456
1
7——————
—————— R/(W)*
IRRSNC IRRCTL
11111
Note: * Only 0 can be written to clear the flag.
Bit :
Initial value :
R/W :
SIRQR2 is an 8-bit read/write registe r that indicates interrupt request in t he servo section. If the
interrupt re quest has occ urred, the corre sponding bit i s set to 1.
Writing 0 after reading 1 is allowed; no other writing is allowed. It is initialized to H'FC by a
reset, or in stand-by or module stop mode.
Bits 7 to 2Reserved: Cannot be modifi ed and are always re ad as 1.
Bit 1Vertic a l Sync Si gnal Interr upt Re quest Bit (IRRSNC)
Bit 1
IRRSNC Description
0 No interrupt request from the sync signal detector ( VD, noise) (Initial value)
1 Interrupt requested from the sync signal detector (VD, noise)
Bit 0CTL Signal Int er r upt Request Bit (IRRCTL)
Bit 0
IRRCTL Description
0 No interrupt request from CTL (Init ial value)
1 Int errupt requested from CTL
Rev. 1.0, 02/00, page 757 of 1141
Section 27 Sync Separator fo r OSD and Data Slicer
27.1 Overview
The sync se parator separates the horizontal sync si gnal and vertical sync signal from the
composite video signal input from the CVin2 terminal and sends the sync signals to the on screen
display (OSD) module and data sli cer.
The sync separator has an automatic frequency controller (AFC), which generates a reference
clock at 576 or 448 times t he horizontal sync signal frequency. T his reference clock is used to
separate the horizontal sync signal from the composite video signal. The AFC receives the Hsync
sign al pr o cessed b y the H complement an d mas k co unter . The H co mplement and mask counter
removes noi se and equalizing pul ses from the Hsync signal a nd interpolates necessary pulses for
the Hsync signal.
The sync se parator separates the vertical sync signal from the composite video signal through the
counting operation of the V complement and mask counter. The V c omplement and mask counter
increments the c ount at double t he frequency of t he horizontal sync signal t o mask the Vsync
noise and to generate complementary pulses for the Vsync signal according to the register settings.
Through the above functions, the sync signals ca n be separated correctly a gainst noi se input to the
CVin2 terminal, motor skew due to VCR tape playback or special-function playback, a nd
abnormal noi se in a weak fiel d.
In addition, the sync separator provides the field detection function ne cessary for the data slicer,
and the noise det ection funct ion nec essary for tuner detection (detecting the tuning status).
As th e AFC refer ence cl ock is al so use d as the dot clock of the OSD, swi tch ing the ref e renc e clo c k
ca n cha nge the dot width of the displa y. When the text di spla y mo de of the OSD is used, ref e r to
section 27.3.6, Automatic Frequency Controller (AFC).
In addition to the CVin2 video signal, the following signals can be selected as sources of sync
separation t hrough t he external circuit and regi ster settings: the Csync com posite sync signal input
from the Csync/Hsync te rminal, a nd the sepa rate Vsync a nd Hsync signal s input from the
VLPF/Vsync and Csync/Hsync terminals, respectively.
Rev. 1.0, 02/00, page 758 of 1141
27.1.1 Features
• Horizontal sync signal separation: Stable separation is provided by the AFC, and complement
and ma sk functions are available.
• AFC refe rence c l ock freque ncy: 576 or 448 times the frequency of the horiz ontal sync signal
can be selected.
• Vertical sync signal sepa ration: The masking and complement funct i ons are available through
the V c omplement and ma sk counter.
• The source for sync sepa ration c a n be selected from three signa ls (five methods).
1. Composite video signal input from the CVin2 terminal (two methods)
2. Csync signal i nput from the Csync/Hsync t erminal (two methods)
3. Vsync and Hsync signals that are input from the VLPF/Vsync and Csync/Hsync terminals,
respectively (one method)
• Csync separation comparator: The slice level can be selected by register settings.
• Polarity of the Csync/Hsync terminal input: The signal detection polarity can be selected.
• Polarity of the VLPF/Vsync terminal input: The signal detection polarity can be selected.
• Noise detection: Noise during one frame is count ed and a noise detection interrupt is
generated when the c ount rea ches the spe c ified va lue.
• Noise detection counter: The count is readable and is reset every other vertical sync signal
input.
• Field detection: The odd or even field for interlace scanning is distinguished.
• Reference Hsync signa l for the AFC: The re fe rence Hsync signal can be selected.
• V complement and mask counter: The source for the counter cloc k (twice the frequency of the
horizontal sync signal) can be selected.
• Internal Csync generator: The clock source for the internal Csync generator can be selected.
27.1.2 Block Diagram
Figure 27. 1 shows the bl ock dia gram of t he sync separator.
Rev. 1.0, 02/00, page 759 of 1141
Slicing voltage
control Separation
method
Digital H
separation
counter
Vvth register
Selecting 576 or 448
as the division ratio
Digital
LPF ON
Switching
Switching
Reference
Hsync
Internally generated
Hsync
External
Hsync
Switching Switching
Frequency-dividing
counter
Complement and
mask setting register
Switching
Switching
Reset
for V
Reset
for H
TV format
in H
(Self-
running)
Internal Csync
generator
AFC error output
circuit
(comparator)
When the data slicer is used and the text
display mode is selected in the OSD,
the AFC clock is selected; the clock is
also used as the dot clock.
When the data slicer is not used
and the text display mode is
selected in the OSD, the
self-running signal is selected.
Switching
Switching
Switching
Switching
Switching
Reference clock
Masking
Complement
and mask
Complement enable bit
(Self-running)
Field detection window Field detection
Field detection
window register
Hvth register Noise
detection
Noise detection
window
Noise
counter Noise detection
interrupt
: Register
V complement enabled:
Complemented and
masked V
V complement disabled:
Masked V
External Vsync (data
slicer)
External Vsync interrupt
Field signal (data slicer)
External Hsync
(data slicer)
Detection window
signals for data slicer
(data slicer)
Internally generated
sync signal (OSD)
Clock run-in period and start bit period
AFCH
Dot clock (OSD)
Noise detection level register
Csync
separation
comparator
I/O
switching
Polarity
switching
Polarity
switching
CVin2 Hsync
Vsync
Si/TEXT
HCKSEL (TE)
(0)
(1)
(Si)
SEPH
1/2
U/D
inV
HHK
C
H complement and
mask counter
(complement and
mask functions)
ROSCH
AFCV
Si/TEXT
SEPV
OSC2H
C
R
C
C
R
Digital V
separation
counter
U/D
C
φ/2
φ/2
φ/2
Csync/Hsync
Vsync/VLPF
(1)
(0)
(TE)
OSDFLD
OSDV (OSD)
Si = AFCV
TEXT = inV
OSDH (OSD)
Field signal (OSD)
Si = AFCFLD
TEXT = inFLD
(TE)
(0)
(1)
inFLD
AFCFLD
(Si)
(Si)
Si/TEXT
HCKSEL
VCKSL
AFC2H 2 × fh
4/2fsc
Si/TEXT
AFCosc
AFCpc
AFCLPF
AFC
(Si)
AFCH
AFC oscillator
HSEL
(TE)
V complement and
mask counter
(complement and
mask functions)
R
C
Figure 27.1 Sync Separator Block Diagram
Rev. 1.0, 02/00, page 760 of 1141
27.1.3 Pin Confi guration
Table 27. 1 shows the pi n configuration of the sync separator.
Table 27. 1 Sync Separator Pin Configuration
Name Abbrev. I/O Function
Sync signal
input/output Csync/Hsync Input/output Com posite sync signal input/output or
horizontal sy nc signal input
VLPF/Vsync Input Pin for connecting external LPF for
vertical sync signal or input pin f or
vertical sync signal
AFCosc Input/ output AFC oscillation signal
AFC oscilla tion
signals AFCpc I nput/output AFC by- pass capacitor connecting pin
LPF for AFC AFCLPF Input/ output Ext ernal LPF connecting pin for AFC
Composi te video
signal CVi n2 Input Composi te video signal input (2 Vpp,
with a sync tip clam p circuit)
27.1.4 Register Configuration
Ta ble 27. 2 shows t he sync separ ato r re giste rs.
Table 27. 2 Sync Separator Registe rs
Name Abbrev. R/W Size Initial
Value Address*1
Sync separation input mode register SEPIMR R/ W Byte H'00 H'D240
Sync separation control regist er SEPCR R/ (W)*2Byte H'00 H'D241
Sync separation AFC control register SEPACR R/(W)*2Byte H'10 H'D242
Horizontal sync signal threshol d regis ter HVTHR W Byte H'E0 H'D243
Vertical sync signal thr eshold register VVTHR W Byt e H'00 H'D244
Field detection window regist er FWIDR W Byt e H'F0 H'D245
H com plement and mask register HCMMR W Word H'0000 H'D246
Noise detection counter NDETC R Byte H'00 H'D248
Noise det ection level register NDETR W Byt e H'00 H'D248
Data slicer detection window register DD ETWR W Byte H'00 H'D 249
Int ernal sync signal frequency regist er I NFRQR W Byte H'10 H'D24A
Notes: 1. Lower 16 bits of the address .
2. O nly 0 can be written to clear the flag.
Rev. 1.0, 02/00, page 761 of 1141
27.2 Register Descript i on
27. 2. 1 Sy nc Separatio n Input Mode Re gist er (SEP IMR)
0
0000000
7
R/W
FRQSEL
0
R/W
CCMPV1 6
R/W
CCMPV0 5
R/W
COMPSL 4
R/W
SYNCT 3
R/W
VSEL 2
R/W
DLPFON 1
—
—
Bit :
Initial value :
R/W :
The SEPIMR is an 8-bit read/write register for selecting the source signals for sync separation. In
addition to the internal switches controlled by this register setting, the external circuits are used to
select the sources of the Hsync and Vsync signals to be supplied to the digital H separation
counter and the digital V se pa ration counte r, respec t ively. Figure 27.2 and table 27.3 show the
source signa l selection. The SEPIMR also specifies t he sl icing voltage of the Csync separation
comparator, switches the polarity of the signals input from the Csync/Hsync and VLPF/Vsync
terminals, turns on or off the digita l LPF, and switches the refe rence cloc k frequenc y for t he AFC.
For details on the source signals for sync separation, refer to section 27. 3.1, Selecting Source
Signals for Sync Separation. When reset, the SEPIMR is initialized to H'00.
CVin2
Csync
a
1
1
0
0
b
a
b
Hsync
Vsync
VLPF VLPF/Vsync
Csync/Hsync
Hsync
Vsync
DLPFON
External
SW3
Internal
SW5
Internal
SW6
External
SW2
External
SW1
Reference
voltage switch
Register
control
I/O
switch
I/O
switch Polarity
switch
Sync tip
clamp
Digital V
separation
counter
Csync polarity
Schmitt circuit
Vsync polarity
Schmitt circuit
External circuit Inside LSI
Csync
separation
comparator
External
SW4
CVin2 –
+
CCMPSL
CCMPV0, 1
SYNCT
VSEL
SEPV
SEPH
Digital H
separation
counter
Polarity
switch
Figure 27.2 Di agram of the Circuit for Selecting the Source Signals for Sync Separation
Rev. 1.0, 02/00, page 762 of 1141
Table 27. 3 Source Signals for Sync Separation
Input
Source Vsync
Detector External
SW1 External
SW2 External
SW3 External
SW4
CCMPSL
(Internal
SW5)
VSEL
(Internal
SW6)
Csync/
Hsync
Terminal
CVin2
input Vsync
Schmitt OffOnaa00Output
Csync
Schmitt Off Off Open Input
fixed to
OVss
01Output
Csync
input Vsync
Schmitt On On a a 1 0 Input
Csync
Schmitt On Off a Input
fixed to
OVss
11Input
Hsync/
Vsync
input
Vsync
Schmitt OffOffbb10Input
Bits 7 and 6Csync Separation Comparator Slicing Voltage Select
(CCMPV1 and CCMPV0): Select the slicing voltage for the Csync separation comparator. The
value set by these bits is the slicing level against the sync tip level (–40 IRE). Note that this slicing
level is used only for referenc e.
Bit 7 Bit 6
CCMPV1 CCMPV0 Description
0 0 The Csync slicing level is 10 IRE ( I nitial value)
1 Th e Cs ync slicing le v e l is 5 IRE
1 0 The Csync slicing le v e l is 15 IRE
1 Th e Cs ync slicing le v e l is 20 IRE
Rev. 1.0, 02/00, page 763 of 1141
Bit 5Csync Sepa rat i o n Comparat or Input Select (CCMPSL) : Controls internal switch SW5
to select whether to use the Csync separation comparator input or Csync Schmitt input. Writing 0
to this bit selects the Csync separation c omparator input, and writing 1 selects the Csync Schmitt
input. Thi s bit al so controls the input/out put status of the Csync/ Hsync terminal. Writing 0 to this
bit makes the Csync/Hsync an output terminal, and writing 1 makes it an input terminal. Note that
the Csync /Hsync t e rminal enters a high-impedance state at reset and i n sleep, suba ctive, subslee p,
watch, standby, and m odule stop modes.
Bit 5
CCMPSL Description
0The Csync separation comparat or input is selected
The Csync/Hsync terminal oper ates as an output terminal ( Initial value)
1 Th e Cs ync Schmit t in p ut is se le cte d
The Csync/Hsync terminal oper ates as an input terminal
Bit 4Sync Sig nal Pol arity Selec t (SYNCT ): This bit selects the polarity of the Csync/Hsync
and VLPF/ Vsync i nput signal s. When using the CVin2 input signal, be sure to write 0 to thi s bit to
select the positive polarity.
Bit 4
SYNCT Description
0
(Init ial value)
1
Bit 3Vsync Input Signal Select (VSEL): Controls internal switch SW6 to select the Vsync
input signa l. Writing 0 to this bit selects the Vsync Schm itt input, and writing 0 selects t he Csync
Schmitt input.
Bit 3
VSEL Description
0 Vs y n c Schmitt input ( Initial value )
1 Csync Schmitt input
Rev. 1.0, 02/00, page 764 of 1141
Bit 2Digital LPF Control (DLPFO N): Sp ecifies the dig ital LPF function, which mas ks noise
components of the Vsync signal in a weak field. The digital LPF logically ORs the Csync signal
(Vsync signal) and the SEPH signal that is separated by the digital H separation counter, then
inputs the ORed result t o the di gital V se paration counter. This function prevents Vsync detection
delay and Vsync detection miss in a weak field. For the timing, refer to section 27.2.5, Vertical
Sync Si gnal Threshold Re gister (VVTHR).
Bit 2
DLPFON Description
0 The digital LPF does not operate (Init ial value)
1 The digital LPF operates
Bit 1Reserved: Cannot be modified and is always read as 0. When 1 is written to this bit,
correct ope ration i s not guaranteed.
Bit 0Refere nce Cloc k Frequency Selec t (FRQSEL): Selects the frequency of the referenc e
clock for the AFC: 576 tim e s or 448 times the horizontal sync signal fre quency. To obtain a
desired reference cloc k frequency, connect an e xternal circuit of a value suit able for the desired
frequency to the AFCosc and AFCpc termi nals, and select the division rat io of the frequency
di viding coun ter wit h this bit. This AFC refe ren ce cloc k is al so use d as the dot clock for the OSD;
change this frequency to adjust the dot width of the display characters. Note, however, that the
data slicer will not operate when 448 times t he horizontal sync frequency is selected. For details,
refer to section 27. 3.6, Automatic Frequency Cont roller (AFC).
Bit 0
FRQSEL Description
0 576 times the horizontal sync frequency (Initial value)
1 448 times the horizontal sync frequency
Rev. 1.0, 02/00, page 765 of 1141
27. 2. 2 Sy nc Separatio n Contro l Re gister ( SEPCR)
0
0000000
7
R
FLD
0
R/W
AFCVIE 6
R/(W)*
AFCVIF 5
R/W
VCKSL 4
R/W
VCMPON 3
R/W
HCKSEL 2
R/W
HHKON 1
—
—
Bit :
Initial value :
R/W :
Note: * Only 0 can be written to clear the flag.
The SEPCR i s an 8-bit read/write register for cont rolling t he external Vsync i nterrupt, ena bling or
disabling the V complement function, selecting the clock source for the V complement and mask
counter, sel ecting the clock source for t he internal Csync generator, and indicating the field
detected by the AFC. When reset, the SEPCR is initialized to H'00.
Bit 7External Vsync Interrupt Enable (AFCVIE): Enables or disables the external Vsync
interrupt to be requested when the AFCVIF is set to 1.
Bit 7
AFCVIE Description
0 The external Vsync interrupt is disabled (Initial value)
1 The external Vsync interrupt is enabled
Bit 6External Vsync Inter r upt Flag (AF CVIF): This flag is set to 1 when the V complement
and mask counter detects the external Vsync signal (the AFCV signal). For the Vsync interrupt
ge nerated i n the OSD, refer to section 29, On Screen Displa y (OSD).
Bit 6
AFCVIF Description
0[Clearing condition]
1 is rea d, the n 0 is written (Initial value )
1 [Setting condition]
The V complement and mask counter detects the external Vsync signal (AFCV
signal)
Rev. 1.0, 02/00, page 766 of 1141
Bit 5V Compleme nt and Mask Counter Cl ock So urce Sel ect (VCK SL ): Selects the clock
source for t he V complement a nd m a sk counter: double the frequency of the horizontal sync signal
for the AFC (AFCH signal) or that for the H comple ment and ma sk counter (OSCH signal). Whe n
the te xt display mode is select ed for the OSD and inte r nall y gener at ed Hsync sign al is selec ted as
the reference Hsync signal for the AFC by setting the HSEL bit (bit 5) of the SEPACR, setting this
VCKSL bit to 1 enables the external Vsync signal to be detected irrespectively of the text display
mode operation.
Bit 5
VCKSL Description
0Double the frequency of the horizontal sync signal ( AFCH signal) for the AFC
(Init ial value)
1 Double the f requency of the hor izontal sy nc signal (OSCH signal) for the H
complement and mask counter
Bit 4V Compleme nt Function Control (VCMPO N) : Enables or disables the V complement
function of the V compl ement and mask count er. The V complement function prevent s the Vsync
detection being delayed and missed in a weak field. For the timing, refer to section 27.2. 5, Vertical
Sync Si gnal Threshold Re gister (VVTHR).
Bit 4
VCMPON Description
0 The V complement function is disabled (Initial value)
1 The V complement function is enabled
Bit 3Internal Csync Gene rator Clock Source Select (HCKSEL): Selects the clock source for
the internal Csync generator: the 4/2 fsc clock or the AFC reference clock. When the text display
mod e i s select ed for the OSD and the exter nal Hsync si g nal is select e d as the referen ce Hsy nc
signal for the AFC, set this HCKSEL bit to 1 to generate the internal Csync signal from the AFC
reference clock. In this case , however, the Hsync a nd Vsync signals must be dedicated sepa ration
inputs, wi th both signals having equal cycles and pul se wi dt hs. When set ting the HCKSEL bit to
1, clear the FRQSEL bit and set the AFC circuit reference clock frequency to 576 times the
horizontal cycle signal. Note that the OSD module will not operate if the HCKSEL bit and
FRQSEL bit are both set to 1.
Bit 3
HCKSEL Description
0 4/2 fsc clock (Initial value)
1 AFC refer ence clock
Rev. 1.0, 02/00, page 767 of 1141
Bit 2HHK Forcibly Tu rn ed On (H HKON): Forci bly ope rates the hal f Hsync killer (HHK)
function when the H complement and mask counter interpolates complementary pulses three
successive times. When the HVTHR is set within t he range from 2.35 µs to 4.7 µs to remove
equalizing pulses by using the digital H separation counter, the HHK function prevents Hsync-
Vsync pha se-difference errors during the V blanking period. For the timing, refer to section
27.2.4, Horiz ontal Sync Signal Threshold Register (HVT HR).
Bit 2
HHKON Description
0The HHK is not operated when complement ary pulses ar e interpolated three
successive times (Initial value)
1 The HHK is forcibly oper ated when complementary pulses are interpolated three
successi ve times
Bit 1Reserved: Cannot be modified and is always read as 0. When 1 is written to this bit,
correct ope ration i s not guaranteed.
Bit 0Field Detection Flag (FLD): Indicates the field status determined by the status of the field
detection window signal generated by the AFC when the external Vsync signal (AFCV signal)
rises. This flag is invalid when the internally generated Hsync signal is selected as the AFC
reference Hsync signal. For the timing, refer t o section 27.2.6, Fie ld Detection Window Re gister
(FWIDR).
Bit 0
FLD Description
0 Even field (Initial value)
1 Odd field
Rev. 1.0, 02/00, page 768 of 1141
27. 2. 3 Sy nc Separatio n AFC Control Re gist er ( SEPACR)
0
0000100
7
—
—
0
R/W
NDETIE 6
R/(W)*
NDETIF 5
R/W
HSEL 4
—
—3
—
—2
R/W
ARST 1
—
—
Bit :
Initial value :
R/W :
Note: * Only 0 can be written to clear the flag.
The SEPACR is an 8-bit read/write register for controlling the AFC. The AFC generates a
reference clock of 576 or 448 times the frequency of the horizont al sync signal. From this
reference clock, seve ral signals suc h as the hori z ontal sync signal (AFCH si gnal), clock run-in
detection window signal, or start bit detection window signal are generated. The referenc e clock is
al so used as the dot cloc k for the OSD. The AFC reference Hsync signal can be switch ed bet wee n
the external Hsync signal and the internally generated Hsync signal. In addition, the SEPACR has
a function for control ling the noise det ection int errupt and enabling or disabling the AFC reset
function. W hen reset , the SEPACR is initialized to H'10.
Bit 7Noise Detection Interrupt Enable (NDETIE): Enables or disables the noise detection
interrupt to be requested when the NDETIF is set to 1.
Bit 7
NDETIF Description
0 The noise detection interrupt is disabled ( I nitial value)
1 The noise detection interrupt is enabled
Bit 6Noise Detection Interrupt Flag (NDETIF): This flag is set to 1 when the noise detection
counter val ue matches the noise detection le vel regi ster val ue.
Bit 6
NDETIF Description
0 [Clearing condit ion]
1 is rea d, the n 0 is written (Initial value )
1[Setting condition]
The noise detection counter value matches the noise detection level register value
Rev. 1.0, 02/00, page 769 of 1141
Bit 5Reference Hsync Signal Select (HSEL): Selects the reference Hsync signal for the AFC:
the external Hsync signal or the internally generated Hsync signal. When using the data slicer,
select the external Hsync signal. When not using the data slicer but using the text display mode for
the OSD, select the in ternally generated Hsync signal. Before this bit se tti ng is modi fied, the OSD
display shoul d be turned off.
Bit 5
HSEL Description
0 The external Hsync signal is selected (Init ial value)
1 The internally generated Hsync signal is selected
Bit 4Blank Bit: Cannot be read or modified.
Bit 3Reserved: Cannot be modified and is always read as 0. When 1 is written to this bit,
correct ope ration i s not guaranteed.
Bit 2AFC Reset Contro l (ARST ): Enables or disables the AFC reset function. When a VCR
motor skew occurs or the channel is switched, and if the Hsync signal (AFCH signal) output from
the AFC differs in phase from the reference Hsync signal i nput to the AFC, the AFC i s reset to
eliminate th e ph as e d iff eren ce an d to lo ck the AFC H signal p hase to that of the r ef erence signal.
Bit 2
ARST Description
0 The reset function is disabled (Init ial value)
1 The reset function is enabled
Bits 1 and 0Reserved: Cannot be modified and are always read as 0. When 1 is written to these
bits, correc t operation i s not guaranteed.
Rev. 1.0, 02/00, page 770 of 1141
27. 2. 4 Hori z o ntal Sync Signa l Thre shold Register (HVTHR)
0
0000011
7
W
HVTH0
1
—
—6
—
—5
—
—4
W
HVTH4 3
W
HVTH3 2
W
HVTH2 1
W
HVTH1
Bit :
Initial value :
R/W :
The HVTHR is a 5-bit writ e -only regi ster for specifying the threshol d value for the digital H
separation counter; this value is used to generate the SEPH signal from the Csync signal. The
SEPH si g nal is set to 1 when the digita l H separati o n counter value matc hes t he HVTHR value
while the Csync is high, and is reset to 0 when the digital H separation counter value becomes 00
while the Csync is low. When reset, the HVTHR is initialized to H'E0.
Figures 27.3 and 27. 4 show the HVTHR value a nd the SEPH signal generation timing.
Csync
HVTH
SEPH
Digital H separation
counter
About
1.6 µs to 2.0 µs
Fi g ure 27.3 HVTHR Value and SEPH Gener atio n Tim i ng
When Equalizing Pulses Are Detected
Rev. 1.0, 02/00, page 771 of 1141
Csync
HVTH
SEPH
Digital H separation
counter
About
3.2 µs to 2.0 µs
Figure 27.4 HVTH Value and SEPH Generation Timing
When Equalizing Pulses Are Not Detected
The f oll o wing shows e xample s of HVTHR settin g s.
Condition: (HVTHR – 1) × (2/O S C) > 1.6 µs or 3. 2 µs
System clock OSC = 10 MHz
2/ OSC = 5 MHz = 0.2 µs
Example 1: To detec t equal iz ing pulses
Hs ync detection thr eshold v a lue : 1.6 µs
1.6 µs / 0.2 µs = 8
HVTHR value = H'8 (8)
Example 2: To not detect equalizing pulses
Hs ync detection thr eshold v a lue : 3.2 µs
3.2 µs / 0.2 µs = 16
HVTHR val ue = H'10 (16)
In general, to detect Hsync pulses continuously, set the HVTHR value so that 2.35-µs equalizing
pulses can be detected. However, if an equalizing pulse at an Hsync pulse position is lost in a
weak fie l d, a Hsync-Vsync phase -difference e rror wil l occur, and the field will not be de tected
correctly. In such a weak fi e ld, this error can be prevented by eliminating 2. 35-µs equalizing
pulses. Figure 27.5 shows the t iming whe n a phase-difference error occurs.
Rev. 1.0, 02/00, page 772 of 1141
Csync
HVTH
SEPH
HHK
OSCH
HC
Digital H separation
counter
Hsync-Vsync
phase-difference
error
Pulse
lost
H complement
and mask counter
Comple-
ment Comple-
ment
Figure 27.5 Timing of Hsync-Vsyn c Phase-Difference Error
When Equalizing Pulse Lost at Hsync Pulse Position
Note: When 2.35-µs equalizing pul ses are eliminated, the complement funct i on ope rates for the
eliminated period. Accordingly, the ri sing edge of the Vsync signal for the even field is
detected as an Hsync pulse. Therefore, to not generate an Hsync pulse at this position, set
the HHKON bit (bit 2) of th e SEPCR to 1 so that the HHK function is forc ibly operate d
when complementary pulses are inserted three successive times. Figures 27.6 and 27.7
show thi s timing.
Csync
HVTH
SEPH
HHK
OSCH
HC
Digital H separation
counter
Comple-
ment Comple-
ment Comple-
ment Comple-
ment
Phase-difference
error
H complement and
mask counter
Comple-
ment Comple-
ment Comple-
ment
Figure 27.6 Timing of Hsync-Vsyn c Phase-Difference Error
When Equalizing Pulse Not Detected
Rev. 1.0, 02/00, page 773 of 1141
Csync
HVTH
SEPH
HHK
OSCH
HC
Digital H separation
counter
H complement and
mask counter
Forcible HHK
operation
Forcible HHK
operation
Comple-
ment Comple-
ment Comple-
ment
Comple-
ment Comple-
ment
Comple-
ment
Figure 27.7 Timing of HHK Operation
When Complementary Pulses Inserted Three Successive Times While HHKON = 1
27.2.5 Vertical Sync Signal Threshold Register (VVTH R)
0
0000000
7
W
VVTH0
0
W
VVTH7 6
W
VVTH6 5
W
VVTH5 4
W
VVTH4 3
W
VVTH3 2
W
VVTH2 1
W
VVTH1
Bit :
Initial value :
R/W :
The VVTHR is an 8-bit writ e -only regi ster for specifying the threshol d value for t he digital V
separation counter; this value is used to generate the SEPV signal from the Csync signal. The
SEPV si g nal is set to 1 when the digita l V separati o n counter value matc hes t he VVTHR value
while the Csync is high, and reset to 0 when the digital V separation counter value becomes 00
while the Csync is low. Set the VVTHR value so that the SEPV signal goes high 1/2H or more
after the Vsync start point. When reset, the VVTHR is initialized to H'E0.
Figure 27. 8 shows the VVTHR val ue and t he SEPV signa l generation timing.
Csync
1/2 H or more
VVTH
H
SEPV
Digital V separation
counter
Figure 27.8 VVTHR Value and SEPV Generation Timing
Rev. 1.0, 02/00, page 774 of 1141
The following shows an example of VVTHR settings.
Condition: (VVTHR – 1) × (2/ OSC) > (Hsync pe riod / 2 – 4.7 µs) × 1. 5 = 41 µs
System clock OSC = 10 MHz
2/ OSC = 5 MHz = 0.2 µs
Example 1: To detec t 41-µs pulses
Vs ync detection thr eshold v a lue : 41 µs
41 µs / 0.2 µs = 205
HVTHR val ue = H'CE (206)
The noise component of the Csync signal in a weak field is usually large, and will cause the Vsync
de tect ion delay or miss. I n suc h a ca se, se t t he DLPFON (bit 2) of the SEPI MR to 1; the SEPH
signal detected by the digital H separation counter is logically ORed with the Csync signal
(Vsync), then the result is input to the digital V separation counter. This will prevent the Vsync
detection delay or miss in a weak field. Figure 27.9 shows this timing.
Csync + SEPH
HVTH
SEPH
SEPV
VVTH
Digital H separation
counter
Digital V separation
counter
Figure 27.9 VVTHR Value and SEPV Generation Timing
When Digi tal LPF Is Enabled
Alternatively, set the VCMPON (bit 4) of the SE PC R to 1 when the Vsync dete ct ion delay or mi ss
may occur in a weak field; the external Vsync detection signal (AFCV signal) will be generated by
the V c omplement and ma sk counter. Figure 27.10 shows t his timing.
Rev. 1.0, 02/00, page 775 of 1141
Csync
VVTH
SEPV
521 522 523 524 0 1 2 3 4 5 6 7 8
AFCV
1/2 AFCH
(V sampling clock)
Digital H separation
counter
V complement and
mask counter
Figure 27.10 AFCV Generation Timing When V Complement Function Is Enabled
(for NTSC)
27. 2. 6 Fi eld Detec t ion Window Register (FWIDR)
0
0000111
7
W
FWID0
1
—
—6
—
—5
—
—4
—
—3
W
FWID3 2
W
FWID2 1
W
FWID1
Bit :
Initial value :
R/W :
The FWIDR is a 4-bit write-only re gister for specifying the field detection window timing in units
of 16 × fh (fh: horizontal sync signal frequency). T he field detection window signa l is reset to 0
when th e AFC dividing co unter v alue matches the FWIDR value, an d th e s ig nal is aga in set to 1
when 1/2 the Hsync signal period has passed. At a rising edge of the AFCV signal whil e the field
detection window signal is 1, the field is determined as an odd one, and the field detection flag
(FLD) i s set to 1. At a risi ng edge of the AFCV signal while the field detection window signa l is 0,
the field is determined as an even one, and the FLD is cleared to 0. The value set to the FWIDR
dep end s o n the setti ng of the V comple me nt fu ncti on co ntr ol (VC MPON) bit (bi t 4) of the
SEPC R. When the VCMPON is clear e d to 0, that is, when the V complement funct i o n is not
operating, the FWIDR must be set so that the rising edge of the SEPV signal, which is generated
when the V separation counter value reaches the specified threshol d va l ue, comes to the cent er of
th e fie l d detec ti o n win dow perio d. When the VCMPON is set to 1, that is, when the V
complement function is operating, the FWIDR must be set so that the dividing counter overflow
timing comes to the center of the field detection window period. When re set, the FWIDR is
initialized to H'F0.
(1) Bit 0 of SEPACR Register
Rev. 1.0, 02/00, page 776 of 1141
Bit 0Field Detection Flag (FLD): Indicates the field determined by the status of the field
detection window signal generated by the AFC when the external Vsync signal (AFCV signal)
rises. This flag is invalid when the internally generated Hsync signal is selected as the AFC
reference Hsync signal. For the timing, refer t o section 27.2.6, Fie ld Detection Window Re gister
(FWIDR).
Bit 0
LD Description
0 Even field (Initial value)
1 Odd field
Csync
SEPV
AFCV
FLD
AFCV T
F
*
T
F
*
Note: * T
F
: Field detection window register value
FLD
Digital V separation
counter
V complement and
mask counter clock
When V complement
function is not operating:
AFC frequency-
dividing counter
H/2 µs
Field detection
window signal
Field detection
window signal
Odd field
Odd field timing Even field timing
When V complement
function is operating:
Even field
Figure 27.11 Field Detection Timing
Rev. 1.0, 02/00, page 777 of 1141
27. 2. 7 H Compleme nt and Mask Timing Register (H CMMR)
15
0
HC8 HC7 HC6 HC5 HC4 HC3 HC2 HC1 HC0 HM6 HM5 HM4 HM3 HM2 HM1 HM0
W
14
0
W
13 12
0
W0
W
11
0
W
10
0
W
9
0
W
8
0
W
7
0
W
6
0
W
5
0
W
4
0
W
3
0
W
2
0
W
1
0
W
0
0
W
Bit :
Initial value :
R/W :
The HCMMR is a 16-bi t write-only regi ster for specifying the timing (Th: Hsync frequency) for
generating a complementary pulse when a pulse in the Hsync signal is lost, and the timing (Tm
and Tm2) for clearing the HHK (masking per iod) .
The HC8 to HC0 bits specify the timing for generating a complementary pulse; if no Hsync pulse
is input within this specified time, a complementary pulse is generated from the H complement
and mask counter. When a supplem entary pulse is g en erated, the HHK function, provided for
resetting the H supplement mask count er, remains c leared, and the H supplement mask counter is
synchronized wi t h the Hsync signal at the next Hsync pul se input. The HHK2 operation for
generating the Hsync signa l (OSCH) for the AFC circuit is pe rformed when a supplementary pulse
is generated.
The HM6 to HM0 bits specify the timing for clearing the HHK function. Set the HHK clearing
timing to about 85% of the Hsync period sta rting from the SEPH rising edge to eliminate
equalizing pulses and copy-guard signals.
Figure 27.12 shows t he complement and ma sk timing. The HHK signal is set to 1 a bout 5 µs after
th e SE PH risi ng edg e, an d the HHK2 signal is set to 1 immediat el y aft e r the H compleme nt a nd
mask counter is reset. The HHK signal is also used for t he noise detection window. For de tails on
the noise detection, refer to section 27.2.8, Noise Detection Counte r (NDET C).
When reset, the HCMMR is initialized to H'0000.
Rev. 1.0, 02/00, page 778 of 1141
Csync
HVTH
SEPH
OSCH
Tm2
Tm
Th
5 µs
HC
HM
Digital H separation
counter
Noise
Killer Killer Killer Killer
Killer Killer Killer Killer
Pulse
lost
Comple-
mentary
pulse
H complement and
mask counter
HHK
(for counter reset)
HHK2
(for OSCH generation)
Figure 27.12 Complement and M ask Timi ng of the H Complement and Mask Counter
Bits 15 to 7H Comple mentary Pulse Setting (HC8 to HC0): Specify the timing for
generating a complementary pulse when an Hsync pulse is lost. If no Hsync pulse is input within
the specified ti me, a com plementary pulse is ge ne rated from the H complement and mask counter
and interpolated to the OSCH signal.
The following shows examples of HC8 to HC0 settings.
Condition: (HC + 1) × (2/OSC) > 63.5 µs (PAL: 64 µs)
System clock OSC = 10 MHz
2/OSC : 5 MHz (0. 2 µs)
Example 1: To set the timing for NTSC
NTSC: 63.5 µs
63.5 µs / 0. 2 µs = 317.5
HC8 to HC0 value = H'13E (318)
Example 2: To set the timing for PAL
PAL: 64 µs
64 µs / 0.2 µs = 320
HC8 to HC0 value = H'141 (321)
Rev. 1.0, 02/00, page 779 of 1141
Bits 6 to 0HHK Period Se tting (HM6 to HM0): Specify the ti ming for clearing t he HHK
(masking period) for the Hsync signal. The H complement and mask counter starts counting at a
rising edge of the SEPH sig nal; the HHK perio d speci f ied by these bits sta r t s at this timing . Thi s
value is also used as the t iming for resetting t he noise detection wi ndow signal. Note that the
setting precision is the upper six bits of the H complement and mask counter: the lower two bits of
the counte r are ignored.
The f oll o wing shows a n example of HM6 to HM0 settings.
Condition: (HM + 1) × (8/OSC) > 54 µs (about 85% of the Hsync period)
System clock OSC = 10 MHz
8/OSC : 1.25 MHz (0.8 µs)
Example: To set the timing to 54 µs
54 µs / 0.8 µs = 67.5
HM6 to HM0 value = H'44 (67)
27.2.8 Noise De tection Counter (NDETC)
0
0000000
7
R
NC0
0
R
NC7 6
R
NC6 5
R
NC5 4
R
NC4 3
R
NC3 2
R
NC2 1
R
NC1
Bit :
Initial value :
R/W :
The NDET C is a 10-bit read-only counter of which the upper eight bits can be rea d. This c ounter
counts the number of Hsync cycles in which an Hsync pulse (noise H) is input while the noise
detection window signal is 1, and counts the numbe r of Hsync cycles in which no Hsync pulse is
input whil e the noise de tection window signal is 0. When t his counter value matches the noi se
detection le vel, the noi se de tection i nterrupt request flag is set. The counter is reset a t every other
vertical sync signal (AFCV signal) input; that is, the noise status for one field can be monitored.
The NDETC value can be read by the CPU; the noise status can be monitored by the read value.
When reset, the NDETC is initialized to H'00. The NDETC is assigned to the same address as the
NDETR. Figure 27.13 shows the timing for noise detection.
Rev. 1.0, 02/00, page 780 of 1141
27.2.9 Noise De tection Le vel Registe r (NDETR)
0
0000000
7
W
NR0
0
W
NR7 6
W
NR6 5
W
NR5 4
W
NR4 3
W
NR3 2
W
NR2 1
W
NR1
Bit :
Initial value :
R/W :
The NDET R is a n 8-bit write-only register for specifying the noise detection l e vel. The set value
must be 1/4 of the actual noise detection level. The noise detection window signal is set to 1 at a
fallin g edge of the OSCH signal, and reset to 0 afte r the time specifie d by the HHK period setti n g
bits has passed. The OSCH signal falls about 5 µs aft er a ri sing edge of the SEPH signal .
When the noise detection counter value matches the specified noise detection level, the noise
detection int errupt reque st flag is set to 1. When reset, the NDETR i s initialized t o H'00. The
NDETR is assigned to the same address as the NDETC.
Figure 27. 13 shows the timi ng for noise de tection.
Csync
AFCV
NDETC
NDETR
SEPH
OSCH
NDETIF
HM
H complement and
mask counter
Cleared to 0 by CPU
Noise detection window
Noise
Noise
Noise Noise
Noise counter
cleared
Noise
Comple-
ment
Comple-
ment
Noise Pulse
lost
Pulse
lost
Fi g ure 27.13 Noise Detect i o n Windo w Setting and Noi se Counting Tim i ng
Rev. 1.0, 02/00, page 781 of 1141
27.2.10 Data Slicer Detection Wi ndow Register (DDETWR)
0
0000000
7
W
CRWDS0
0
W
SRWDE1 6
W
SRWDE0 5
W
SRWDS1 4
W
SRWDS0 3
W
CRWDE1 2
W
CRWDE0 1
W
CRWDS1
Bit :
Initial value :
R/W :
The DDET WR is an 8-bit write-only re gi ster for specifying t he timing of the clock run-in
detection window signal and start bit detection window signa l supplied to the data slicer. Figure
27.14 shows the timing of the signals. When reset, the DDETWR is initialized to H'00.
These detection window signals can be monitored through terminals. For details, refer to section
29.7.3, Digi tal Output Specification Registe r.
C.video
32 × fh = 2 µs 32 × fh = 2 µs
10.5 µs±0.5 µs
±0.5 µs
±0.5 µs
±0.5 µs
23.5 µs
23.5 µs
29.5 µs
Clock run-in
detection
window signal
Start bit detection
window signal
Fi g ure 27 .14 T iming for Gener a ting Cloc k Run-i n Detec t i o n Window Sig nal and
Start Bit Detection Wind ow Signal
Rev. 1.0, 02/00, page 782 of 1141
Bits 7 and 6Start Bit Detection Window Si gnal Falli ng Timing Se tti ng
(SRWDE1 and SRWDE0): Specifies the falling timing (end timing) of the start bit detection
window signal.
Bit 1 Bit 0
SRWDE1 SRWDE0 Description
0 0 The detection ends about 29.5 µs after the slicer start point
(Init ial value)
1 The detection ends about 29.0 µs after the slicer start point
1 0 The detection ends about 30.0 µs after the slicer start point
1 This setting m ust not be used
Bits 5 and 4Start Bit Detec tion Windo w Signa l Rising Timing Set ting
(SRWDS1 a nd SRW DS0) : Specifies the rising timing (start timing) of the start bit detection
window signal.
Bit 1 Bit 0
SRWDS1 SRWDS0 Description
0 0 The detection starts about 23.5 µs after the slicer start point
(Init ial value)
1 The detection starts about 23.0 µs after the slicer start point
1 0 The detection starts about 24.0 µs aft er the slicer start point
1 This setting m ust not be used
Bits 3 and 2Clock Run-i n Detec tio n Window Signa l Fal ling Timi ng Set ting
(CRWDE1 and CRWDE0): Speci fies the falling ti min g (end timing) of the clock run-in
detection window signal.
Bit 1 Bit 0
CRWDE1 CRWDE0 Description
0 0 The detection ends about 23.5 µs after the slicer start point
(Init ial value)
1 The detection ends about 23.0 µs after the slicer start point
1 0 The detection ends about 24.0 µs after the slicer start point
1 This setting m ust not be used
Rev. 1.0, 02/00, page 783 of 1141
Bits 1 and 0Clock Run-i n Detec tio n Window Signa l Ri si ng Timing Setti ng
(CRWDS1 a nd CRW DS0): Specifies the ri sing timing (start timing) of the clock run-in detection
window signal.
Bit 1 Bit 0
CRWDS1 CRWDS0 Description
0 0 The detection starts about 10.5 µs after the slicer start point
(Init ial value)
1 The detection starts about 10.0 µs after the slicer start point
1 0 The detection starts about 11.0 µs aft er the slicer start point
1 This setting m ust not be used
27. 2. 11 Int e r na l Sync Fre quency Registe r (INF RQR)
0
0000100
7
—
—
0
W
VFS2 6
W
VFS1 5
W
HFS 4
—
—3
—
—2
—
—1
—
—
Bit :
Initial value :
R/W :
The INFRQR is an 8-bi t write-onl y registe r for m odifying t he internal ly generated Hsync and
Vsync frequency t o reduce the c olor-bleeding or jitter of OSD in PAL, MPAL, or NPAL m ode or
when the non-interlaced text display mode is selected in the OSD. When reset, the INFRQR is
initialized to H'10.
Bits 7 and 6Vsync Freque ncy Selec ti on ( VFS2 and VFS1): Select the Vsync frequency. Here,
fh indicates the Hsync frequency in each TV format.
Bit 7 Bit 6 Description
VFS2 VFS1 PAL MPAL NPAL
0 0 fh/313 (Initial value) fh/263 (Initial value) fh/313 (Initial value)
1 fh/314 fh/266 fh/314
1 0 fh/310 fh/262 fh/310
1 fh/312 fh/264 fh/312
Rev. 1.0, 02/00, page 784 of 1141
Bit 5Hsync Frequency Selection (HFS): Selects the Hsync frequency. Here, fsc indicates the
color subc arrier signa l freque ncy in e ach TV format. Note that this sett ing is ignored when the
HCKSEL bit (bit 3) of the SEPCR is set to 1 to select the AFC clock as the internal Csync
generator clock source and when the FSCIN bi t (bit 12) of the DFORM in the OSD is set to 1 to
select the 2fsc clock.
Bit 5 Descri ption
HFS PAL MPAL NPAL
0 fsc/283.75 (Initial value) f s c/227.25 (Initial value) fs c/229.25 (Initial value)
1 fsc/283.5 fsc/227.5 fsc/229.5
Bit 4Blank Bit: Cannot be read or modified.
Bits 3 to 0Reserved: Cannot be modifi ed and are always re ad as 0. When 1 is wr itten to these
bits, correc t operation i s not guaranteed.
27.3 Operation
27.3.1 Selecting Source Signals for Sync Separation
The sourc e for sync separation can be selected from t hree signa ls (five methods):
1. Composite video signal input from the CVin2 terminal (two methods)
2. Csync signal i nput from the Csync/Hsync t erminal (two methods)
3. Vsync and Hsync signals that are input from the VLPF/Vsync and Csync/Hsync terminals,
respectively (one method)
For the composite vide o signa l and t he Csync signal, two methods are available for processing t he
Vsync compone nt .
(1) Input ting the Composite Video Signal as t he Source
When the composite video signal is sel ected as the source, the Vsync component ca n be
processed in two methods: using the Vsync Schmitt circuit or using the Csync Schmitt circuit.
(a) Using the Vsync Schmitt Circ uit
The co mpo sit e vid eo signal in put to the CV in 2 terminal is selected as th e source, an d th e
Csync separation comparator separates the composite sync signal from the source signal.
Of the composite sync signal, the Hsync component is input to the digital H separation
counter, a nd the Vsync com ponent is output from the Csync/ Hsync termi nal, goes through
the external LPF circuit, then is input again through the Vsync/VLPF terminal and the
Vsync Schmit t circui t to the digital V separa tion count er . The ini tial value of the S EPIM R
specifies this method. Figure 27.15 shows this method.
Rev. 1.0, 02/00, page 785 of 1141
CVin2
Csync
a
1
1
0
0
b
a
b
Hsync
Vsync
VLPF Vsync/VLPF
Csync/Hsync
Hsync
Vsync
External
SW3
Internal
SW5
Internal
SW6
External
SW2
External
SW1
Reference
voltage switch
Register
control
I/O switch
I/O
switch
Polarity
switch
Polarity
switch
Digital H
separation
counter
DLPFON
Digital V
separation
counter
Csync polarity
Schmitt circuit
Vsync polarity
Schmitt circuit
External circuit Inside LSI
Csync
separation
comparator
External
SW4
CVin2
CCMPSL
CCMPV0, 1
SYNCT
VSEL
SEPV
SEPH
–
+
Sync tip
clamp
Figure 27.15 Sync Source Selection When Using the CVin2 Signal and
the Vsy nc Sc hmit t Circuit
Source
Signal Vsync
Detection External
SW1 External
SW2 External
SW3 External
SW4
CCMPSL
(Internal
SW5)
VSEL
(Internal
SW6)
Csync/
Hsync
Terminal
I/O
CVin2
input Vsync
Schmitt OffOnaa00Output
Rev. 1.0, 02/00, page 786 of 1141
(b) Using the Csync Schmitt Circuit
The Hsync component is processed in t he sa me way a s descri bed in (a ), but t he Vsync
component is processed diffe rently; the Csync/Hsync terminal is le ft open and the
separated Vsync com ponent is i nput through the Csync Schmit t circuit to the digital V
separation coun ter . Figure 27.16 shows this method .
CVin2
Csync
a
1
1
0
0
b
a
b
Hsync
Vsync
VLPF Vsync/VLPF
Csync/Hsync
Hsync
Vsync
External
SW3
Internal
SW5
Internal
SW6
External
SW2
External
SW1
Reference
voltage switch
Register
control
I/O switch
I/O
switch
Polarity
switch
Polarity
switch
Digital H
separation
counter
Digital V
separation
counter
DLPFON
Csync polarity
Schmitt circuit
Vsync polarity
Schmitt circuit
External circuit Inside LSI
Csync
separation
comparator
External
SW4
CVin2 –
+
CCMPSL
CCMPV0, 1
SYNCT
VSEL
SEPV
SEPH
Sync tip
clamp
Figure 27.16 Sync Source Selection When Using the CVin2 Signal and
the Csy nc Sc hmit t Circuit
Source
Signal Vsync
Detection External
SW1 External
SW2 External
SW3 External
SW4
CCMPSL
(Internal
SW5)
VSEL
(Internal
SW6)
Csync/
Hsync
Terminal
I/O
CVin2
input Csync
Schmitt Off Off Open Fixed to
0 or 1 01Output
Rev. 1.0, 02/00, page 787 of 1141
(2) Input ting the Csync Signal as the Source
Whe n the Csy nc si g n al is select ed as th e source, the Vs y nc comp o nent can be processed in two
methods: using the Vsync Schmitt circuit or using the Csync Schmitt circuit.
(a) Using the Vsync Schmitt Circ uit
The C sync sign al having the polari ty sel ec te d by the SYNCT bit (bit 4) of the SEPIMR is
input to the Csync/Hsync termina l. The Hsync com ponent is i nput through the Csync
Schmitt circuit to t he digital H separation counter; the Vsync c omponent goes through the
external LPF circuit, then is input through the Vsync/VLPF terminal and the Vsync
Schmitt circuit to t he digital V separation counter. Figure 27. 17 shows this method.
CVin2
Csync
a
1
1
0
0
b
a
b
Hsync
Vsync
VLPF Vsync/VLPF
Csync/Hsync
Hsync
Vsync
External
SW3
Internal
SW5
External
SW2
External
SW1
Reference
voltage switch
Register
control
I/O switch
I/O
switch Polarity
switch
Polarity
switch
Digital H
separation
counter
Digital V
separation
counter
DLPFON
Csync polarity
Schmitt circuit
Vsync polarity
Schmitt circuit
External circuit Inside LSI
Csync
separation
comparator
External
SW4
CVin2 –
+
CCMPSL
CCMPV0, 1
SYNCT
VSEL
SEPV
SEPH
Sync tip
clamp
Internal
SW6
Fi g ure 27 .17 Sy nc Source Sele c tio n When Using t he Csync Signal and
the Vsy nc Sc hmit t Circuit
Source
Signal Vsync
Detection External
SW1 External
SW2 External
SW3 External
SW4
CCMPSL
(Internal
SW5)
VSEL
(Internal
SW6)
Csync/
Hsync
Terminal
I/O
Csync
input Vsync
Schmitt On On a a 1 0 Input
Rev. 1.0, 02/00, page 788 of 1141
(b) Using the Csync Schmitt Circuit
The Hsync component is processed in t he sa me way a s descri bed in (a ), but t he Vsync
component is processed diffe rently; the Vsync c omponent is i nput through the Csync
Schmitt circuit to t he digital V separation counter. Figure 27. 18 shows this method.
CVin2
Csync
a
1
1
0
0
b
a
b
Hsync
Vsync
VLPF Vsync/VLPF
Csync/Hsync
Hsync
Vsync
External
SW3
Internal
SW5
Internal
SW6
External
SW2
External
SW1
Reference
voltage switch
Register
control
I/O switch
I/O
switch Polarity
switch
Polarity
switch
Digital H
separation
counter
Digital V
separation
counter
DLPFON
Csync polarity
Schmitt circuit
Vsync polarity
Schmitt circuit
External circuit Inside LSI
Csync
separation
comparator
External
SW4
CVin2 –
+
CCMPSL
CCMPV0, 1
SYNCT
VSEL
SEPV
SEPH
Sync tip
clamp
Fi g ure 27 .18 Sy nc Source Sele c tio n When Using t he Csync Signal and
the Csy nc Sc hmit t Circuit
Source
Signal Vsync
Detection External
SW1 External
SW2 External
SW3 External
SW4
CCMPSL
(Internal
SW5)
VSEL
(Internal
SW6)
Csync/
Hsync
Terminal
I/O
Csync
input Csync
Schmitt On Off a Fixed to
0 or 1 11Input
Rev. 1.0, 02/00, page 789 of 1141
(3) Input ting the Hsync a nd Vsync Signals Separa tely as Sourc e s
The Hsy nc si gna l havi ng the pola rit y selecte d by the SYNCT bit (bit 4) of the SEPIMR is
input to the Csync/Hsync termina l, and is input through the Csync Schmitt ci rc uit to the digital
H separation counter; th e Vsync signal having the pola rity selected by the SYNCT bit is input
to the Vsync/VLPF terminal, and is sent through the Vsync Schmitt circuit to the digital V
separation coun ter . Figure 27.19 shows this method .
CVin2
Csync
a
1
1
0
0
b
a
b
Hsync
Vsync
VLPF Vsync/VLPF
Csync/Hsync
Hsync
Vsync
External
SW3
Internal
SW5
Internal
SW6
External
SW2
External
SW1
Reference
voltage switch
Register
control
I/O switch
I/O
switch Polarity
switch
Polarity
switch
Digital H
separation
counter
Digital V
separation
counter
DLPFON
Csync polarity
Schmitt circuit
Vsync polarity
Schmitt circuit
External circuit Inside LSI
Csync
separation
comparator
External
SW4
CVin2 –
+
CCMPSL
CCMPV0, 1
SYNCT
VSEL
SEPV
SEPH
Sync tip
clamp
Fi g ure 27.19 Sync Source Selec tio n When Using t he Hsync and Vsync Signals Separ a tel y
Source
Signal Vsync
Detection External
SW1 External
SW2 External
SW3 External
SW4
CCMPSL
(Internal
SW5)
VSEL
(Internal
SW6)
Csync/
Hsync
Terminal
I/O
Hsync
and
Vsync
input
Vsync
Schmitt OffOffbb10Input
Rev. 1.0, 02/00, page 790 of 1141
27. 3. 2 Vsy nc Separat ion
The Hsync separator separates the Vsync signal from the Csync signal by using the digital V
separation c ounter, which is an 8-bit up-/down-counte r, and t he VVTHR register, which holds the
threshold value. The digital V separation counter increments the count when the Csync signal is
high, and de crements th e coun t when th e Csy nc is low . Wh en the cou n t reaches th e VVTHR value
while the count is incremented, the SEPV signal is set to 1 and the counter stops until the Csync
signal goe s low. Whe n the Csync signal goe s low, the counter sta rts to decrement the count. W hen
the count reaches H'00, the SEPV signal is reset to 0 and the counter stops until the Csync signal
goes high. Set the VVTHR val ue so t hat the SEPV signal goes hi gh 1/2 or more aft er the Vsync
start position to correctly separate the Vsync signal against the signal disturbance in a weak field
or the motor skew during video tape pla yback.
The obtained SEPV signal is sent to t he V compleme nt and mask counter. The V c omplem e nt and
mask counter is reset to 0 when the SEPV signal is i nput, and increment s the count at twice the
frequency (2 × fh) of the horizontal sync signal for the Vsync signal (SEPV signal) cycle period.
This count er masks the reset signal (SEPV) for about 85% (NTSC) or 72% (PAL) of the pe riod
from a reset to the next re set; even if a SEPV signal genera ted by noise is input to the counter
during thi s period, the c ounter i s not re set. If no SEPV signal is i nput after the mask period ends,
the mask is left c leared; the next SEPV signal input resets the c ounter, and the counter i s
synchronized with the SEPV si gnal. When the counter is reset by the SEPV signal, t he external
Vsync de tection signa l (AFCV) is generated and the e xternal Vsync interrupt fla g is set to 1.
The Vsync separation function includes the digital LPF function and the Vsync complement
function, which reduc e the chance of the Vsync detection be i ng delayed or missed due to the
Vsync disturbance in a weak field.
(1) Digi tal LPF Function
This function l ogically ORs the Csync (Vsync) signal and the SEPH signa l separa ted by the
digital H counter to mask the noise component due to loss of a Vsync pulse. The digital V
separation counter increment the count when the resultant signal is input. Loss of a Vsync
pulse in a weak field causes SEPV signal detection to be delayed or missed, which will result
in inc orrec t d etec ti o n of fiel d s or line s. To ena bl e thi s funct i o n, set the DL PFON bit (bit 2) of
the SEPIMR to 1. For the timing, refer to figure 27.9.
(2) Vsync Complement Function
This function m akes the V c omplement and ma sk counter incre ment the count at a clock
having t wice the frequency (2 × fh) of the horizontal sync signal (AFCH), and generates the
AFCV si gnal (Vsync signa l) from the count if a Vsync pulse is l ost.
The count value is decoded in different ways depending on the TV format. The source of the
clock for the V complement and mask counter can be switched between the AFC or the H
complement a nd m a sk counter. This function can reduce the chance of the SEPV signal
detection being de l ayed and m i ssed in a weak field. To enable this funct i on, set t he VCMPON
bit (bit 4) of the SEPCR to 1. For the timing, refer to figure 27.10.
Rev. 1.0, 02/00, page 791 of 1141
27.3.3 Hsync Se paration
The Hsync separator separates the Hsync signal from the Csync signal by using the digital H
separation c ounter, which is a 5-bit up-/down-counte r, and t he HVTHR register, which holds the
threshold value. The digital H separation counter increments the count when the Csync signal is
high, and de crements th e coun t when th e Csy nc is low . Wh en the cou n t reaches th e HVTHR value
while the count is incremented, the SEPH signal is set to 1 and the counter stops until the Csync
signal goe s low. Whe n the Csync signal goe s low, the counter sta rts to decrement the count. W hen
the count reaches H'00, the SEPH signal is reset to 0 and the counter stops until the Csync signal
goes high. Set the HVTHR val ue so t hat 2.35-µs equalizing pulses can be detected; that is, that the
Hsync pul ses can be continuously detected.
The obtained SEPH signal is sent to t he H compleme nt and mask counter. The H c omplem e nt and
mask counter is reset to 0 when the SEPH signal is i nput, and increment s the count at a frequency
of φ/2 for the SEPH signal cycle pe riod to ge ne rate the OSCH signal, HHK signal, and noise
de tect ion window signal . The HHK per i od is spec i fied by the HM6 to HM0 bit s of the HCMMR.
Even if a SEPH signal is input to the counter during this HHK period, the SEPH signal is masked
and the counter is not reset; noise pulses and equalizing pulses during the V blanking period are
eliminated by this function.
The H c omplement and ma sk counter has t he com plement func tion. If no SEPH signal is i nput
during the period specified by the HC8 to HC0 bi ts of t he HCMMR, the c omplement function
generates a complementary pulse and inserts the pulse into the OSCH signal. In this case, the
counter is re set by the complementary pul se, but no HHK signal is generat e d; the ne xt SEPH
signal input resets the counter, and the counter is sync hronized with the SEPH signal. For the
timing, refer to figure 27.12.
Note: In a weak field, equalizing pul ses are not detected in some cases be cause the pulses have a
short durat ion of 2.35 µs. If equalizing pulses, which are input at the same timing as the
Hsync pulses, are not detected, a phase-difference error between the Hsync and Vsync
occurs at a ri sing edge of the Vsync signa l. Such a n error will cause incorrect field
detection in the sync separator and i ncorrect li ne detection by the OSD or data slicer. In
such a weak field, adjust the HVTHR value so that equalizing pulses are not detected.
Note that while equalizing pulses are not detected, complementary pulses are inserted
repeatedly and an Hsync-Vsync phase-differenc e error occurs at a rising edge of the
Vsync sig nal , e ve n in a field that is not weak. T o avoid this, set th e HHKON bit (bit 2) of
the SE PC R to 1 to operate the HHK functio n when compl ementa r y pul ses are gene rate d
three successive times. For the timing, refer to figure 27. 6.
Rev. 1.0, 02/00, page 792 of 1141
27.3.4 Field Detection
The sync separator detects whether the current field is an even field or an odd field from the 1/2H
phase difference between t he Hsync and Vsync by using the AFCV signal ge nerated by the V
complement a nd m a sk counter and the field det ection wi ndow signa l generated by the AFC. The
timing of t he field det ection window signal can be adjusted by the FWIDR setting so that it is
suitable for comparison with the AFCV signal. When a rising edge of the AFCV signal is detected
while the field detection window signal is high, the current field is determined as an odd field;
when a rising edge of the AFCV signal is detected while the field detection window signal is low,
the current field is determined as an even field. The field detection status can be monitored from
the CPU by reading t he FL D bit (bit 0) of the SEPACR. Thi s function wil l not ope rate when the
internally gene rated Hsync signa l is selected as the refe rence Hsync signal for the AFC, because
the AFC is not synchronized with the external Hsync signal in this case. For the timing, refer to
figure 27.11.
27.3.5 Noise De tection
The noise detection function is necessary for tuned status detection. The sync separator detects
noise by using the Csync signal a nd the noi se detection window signal ge nerated by the H
complement a nd m a sk counter. The noise detection wi ndow signal is set to 1 at a fa lling e dge of
the OSCH signal generated by the H complement and mask counter, and reset to 0 at the HHK
clearing timing specified by bits 6 to 0 of the HCMMR. Noise is detected by comparing the noise
counter val ue with the noise detection level register value. The noise counter counts the numbe r of
Hsync c ycles in which a n Hsync signa l is input (noise H) while the noi se detection wi ndow signa l
is high and the number of Hsync c ycles i n which no Hsync signal is input whil e the noise
detection window signal is low. When the counted value reaches the noise detection level, the
noise detection i nterrupt request flag is set. The noi se counter can be rea d from the CPU, and t he
noise detection status can be monitored. The noise detection counter is reset every other Vsync
signal input. Accordingly, the noi se input during one field can be detected. When the i nternally
generated Hsync signal is selected a s the refe rence Hsync signal for the AFC and the text di splay
mode is used in t he OSD, the noise counter reset operati on can be enabled by setting the VCKSL
bit (bit 5) of the SEPCR to 1. For the timing, refer to figure 27.13.
Rev. 1.0, 02/00, page 793 of 1141
27.3.6 Automatic Frequency Controller (AFC)
The AFC averages the Hsync signal fluctuation of the video signal. Figure 27.20 shows the AFC
configuration. The AFC generates a reference clock ha ving 576 or 448 times the frequency (576 ×
fh or 448 × fh) of the Hsync signal. From this clock, several clocks are generated, such as the
horizontal sync signal (AFCH si gnal), clock run-in detection window signal, start bit detection
window signal, V complement a nd mask counter clock when the V complement function is
selected, and the fi eld detection wi ndow signal. T he reference cl ock is also used as the dot clock
for the OSD; modifying t he referenc e clock fre quency can change the dot width of the chara c ter
display. To change the frequency, connect a circuit having a value suitable for the desired
frequency to the AFCosc and AFCpc termi nals, and select the division rat io for the frequency-
dividing counter through the set ting of t he FRQSEL bit in SEPIMR. Note that the da ta slicer wil l
not operate whe n 448 × fh is selected as the reference clock.
AFCLPF
R
C
VCO
AFCpc
AFCosc
HHK
HSEL
HCKSEL
Masking H
FSC
AFCH
AFC error output circuit
(comparator)
Internal Csync
generator
H complement
and mask
counter External Hsync
Error signal
Switching
Switching
Reference clock
FRQSEL
Masking and
complementing H
Reference
Hsync signal
Internally generated
Hsync
External Hsync
Signals such
as dot clock
Low pass
filter
Frequency-
dividing counter
(Divided by
576 or 448)
R
Figure 27.20 AFC Configurati on
Rev. 1.0, 02/00, page 794 of 1141
(1) AFC Oscilla t o r
The AFCosc terminal, which is the oscillation signal terminal of the voltage controlled
oscillator (VCO), oscillates at 576 times the fre quency (576 × fh) of the Hsync signal when the
Hsync signal is input at a certain phase and frequency. The difference in phase or frequency is
detected between the reference Hsync signal and the Hsync signal (AFCH signal) obtained by
dividing the 576 × fh signa l, the error signa l is converte d to a voltag e by a low pass filter
through the AFC error output circuit , and the vol tage is used to control t he VCO.
The VCO control vol tage (the AFCLPF t erminal vol tage) is within a range from about 1.0 V to
4.0 V. T he oscillating capacitance should be set so that the AFCosc oscillating fre quency
becomes 576 × fh at the center (about 2.5 V) of the c ontrol vol tage range. To set the oscill a ting
frequency to 448 × fh, change the values of the external circuits connected to the AFCpc and
AFCosc terminals and modify the FRQSEL bit in SEPIMR.
(2) AFCLPF
The AFC error output c i rcuit de tects the differe nce in phase or fre quency between t he
reference Hsync signal and the Hsync signal (AFCH signal) obt ained by dividing the 576 × fh
or 448 × fh signal, and gene rates a pulse corresponding to the error. Connect a l ow pass filter
(LPF) to the AFCLPF terminal t o average the se error pulses. If the cut-off frequency is too
low, the oscillation stabilizing time (the pull-in time) needed to reach 576 × fh or 448 × fh
becomes long when a la rge error i s detected or after the power is turned on; a high cut -off
frequency will cause jitter or an unstabl e display.
Connect a suitable LPF by refe rring to t he external circuit examples shown i n figures 27. 21
and 27.22. W hen the Hsync signal includes a large di sturbance, for example during spe cial
playback operation, the AFC circuit may operate incorrectly.
(3) Re ference Hsync Signal for AFC
The AFC reference clock i s also used as t he dot clock for the OSD. Accordingly, select t he
re ference Hsyn c si gna l depe ndi n g on whether the OSD opera tes in the sup er- im po sed mode or
text display mode. Refe r to ta ble 27. 4, Reference Hsync Signal for AFC.
Rev. 1.0, 02/00, page 795 of 1141
Table 27. 4 Reference H sync Signal for AFC
AFC
Reference
Hsync
Signal Data Slicer
Operation OSD
Operation Field
Detection
V Comple-
ment and
Mask
Counter HCKSEL HSEL VCKSL
External
Hsync
signal
Operates/
Stops Super-
imposed
mode
Operates Twice th e
frequency of
the AFCH
000
Internally
generated
Hsync
signal
Stops Text
display
mode
Stops Twice th e
frequency of
the OSCH
011
External
Hsync
signal*
Operates Text
display
mode
Operates Twice th e
frequency of
the AFCH
100
Note: *In this case, the Hsync and Vsync signals must be dedicated separation inputs, with both
signals having equal cycles and pulse widths. The FRQSEL bit in the SEPIMR register
m ust be cle ared t o 0.
(4) Extern al Circu it Examples
Figures 27.21 and 27. 22 show exte rnal circuit examples of the AFC.
10pF
AFCosc
AFCpc
AFCLPF
6.8µH
0.01µF
1/2OVcc
VCO
0.01µF
4.7µF
+
+
470Ω
2.4kΩ
Note: Reference values are shown.
Phase error signal
Reset, active,
or sleep
Figure 27.21 Circuit Example for a 576 × fh Reference Cloc k
Rev. 1.0, 02/00, page 796 of 1141
12pF
AFCosc
AFCpc
AFCLPF
12µH
0.01µF
1/2OVcc
VCO
0.01µF4.7µF
+
+
470Ω
2.4kΩ
Note: Reference values are shown.
Phase error signal
Reset, active,
or sleep
Figure 27.22 Circuit Example for a 448 × fh Reference Cloc k
Rev. 1.0, 02/00, page 797 of 1141
27. 3. 7 Modul e Sto p Contr ol Regi ster (MSTPCR)
7
1
R/W
6
1
R/W
54
1
R/W 1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Bit :
Initial value :
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
R/W :
MSTPCRH MSTPCRL
The MSTPCR is a 16-bit read/write register for controlling the module stop mode. Writing 0 to the
MSTP9 bit starts the sync separator; setting the MSTP9 bit to 1 stops the sync separator at the end
of a bus cy cle and th e mo dule stop mode is ent er ed.
The AFC oscillator operates in reset, active, and sleep modes. Accordingly, after the reset state is
cleared, the AFC osci llator operates but the AFC error output circuit (compa rator) does not
operate. Clear the module stop mode of the sync sepa rator and set the sync separator regi sters to
the desired va lues. The AFC error output ci rcuit (comparator) will stop in standby, sleep, watch,
subactive, subsle e p, and module stop mode s. When t he se m odes are cleared, wait for the
oscillation to stabilize, that is, for the AFC fre quency t o reach 576 × fh or 448 × fh.
The registers cannot be read or written to in module stop mode. For details, refer to section 4.5,
Module Stop Mode.
Bit 9Module Stop (MST P9): Specifies the module stop mode of the sync separator.
Bit 9
MSTP9 Description
0 Clears the module stop mode of the sync separ ato r
1 Specifies the module stop mode of the sync separator (Initial value)
Rev. 1.0, 02/00, page 799 of 1141
Section 28 Data Slicer
28.1 Overview
The data slicer extracts signals for closed caption signal in the U.S. This function can be used to
extract caption data superimposed on the vertical blanking interval of TV video signals.
A high-performance internal sync separator enables reliable caption data extraction.
The data slicer will not opera te when 448 times the horizontal sync frequency is selected for the
AFC reference clock frequency. For details, refer to section 27.3.6, Automatic Frequency
Controller (AFC).
28.1.1 Features
• Slice lines: 4 lines
• Slice levels: 7 levels
• Sampling clock: Generated by AFC
• Slice interrupt: A slice completion interrupt is genera ted at the end of all slices in a field
• Error det ection: Cloc k run-in, st art bit, a nd data end
Rev. 1.0, 02/00, page 800 of 1141
28.1.2 Block Diagram
Figure 28. 1 shows the bl ock dia gram of t he data sl icer.
Sync separator
Sync signal
generation
Field determination circuit
Slice voltage
generator
Clock run-in
detector
Start bit
detector
Data sampling
clock generator
Shift register
Slice data
register
Data end flag
Slice
completion
interrupt
Start bit
detection flag
Clock run-in
detection flag
Slice line specification circuit
Line counting
Field
Line
counter
Reference clock
CVin2 +
–
H complement
and mask AFC
V
H
HOSD
V
Dot clock
Sync tip
clamp
Figure 28.1 Data Slicer Bloc k Diagr am
Rev. 1.0, 02/00, page 801 of 1141
28.1.3 Pin Confi guration
Table 28. 1 shows the pi n configuration for the data slicer.
Table 28. 1 Data Sli cer Pin Configuration
Block Name Abbrev. I/O Function
Csync/Hsync Input/output Composite sync signal input/output
or horizont al sync signal input
Sync signal
input/output VLPF/Vsync I nput Pin for connecting external LPF for
vertical sync signal or input pin f or
vertical sync signal
AFCosc Input/output AFC osc illat ion signal
AFC
oscillation AFCpc Input/output AFC by-pass capacitor connecting
pin
LPF for AFC AFCLPF I nput/ output External LPF connecting pin for
AFC
4fsc/2fscin Input 4f sc or 2f sc input
Sync
separator
fs c osc illa tion 4f sc/2fscout O utput 4fsc or 2fsc output
Data slicer Composite
video signal Cvi n2 Input Composite video signal input
(2 Vp p, with a sync t i p cl amp
circuit)
Rev. 1.0, 02/00, page 802 of 1141
28.1.4 Register Configurati on
Table 28.2 shows the data slicer registers.
Table 28. 2 Register Configurati on
Name Abbrev. R/W Si ze Initial Value Address*3
Slice even-field mode register SEVFD R/(W)*1Word/byte H'2000 H'D220
Slice odd-field mode register SO DFD R/(W)*1Word/byte H'2000 H'D222
Slice line setting register 1 SLINE1 R/W Word/byte H'20 H'D224
Slice line setting register 2 SLINE2 R/W Word/byte H'20 H'D225
Slice line setting register 3 SLINE3 R/W Word/byte H'20 H'D226
Slice line setting register 4 SLINE4 R/W Word/byte H'20 H'D227
Slice detection register 1 SDTCT1 R/(W)*2Word/byte H'10 H'D228
Slice detection register 2 SDTCT2 R/(W)*2Word/byte H'10 H'D229
Slice detection register 3 SDTCT3 R/(W)*2Word/byte H'10 H'D22A
Slice detection register 4 SDTCT4 R/(W)*2Word/byte H'10 H'D22B
Slice data register 1 SDATA1 R Wor d/byte Undefined H'D22C
Slice data register 2 SDATA2 R Wor d/byte Undefined H'D22E
Slice data register 3 SDATA3 R Wor d/byte Undefined H'D230
Slice data register 4 SDATA4 R Wor d/byte Undefined H'D232
Notes: 1. O nly 0 can be wr itten to clear the flag ( bit 14).
2. Bits 7 to 0 are clear ed when 1 is written to bit 7 of the cor responding slice line setting
register.
3. Lower 16 bits of the address .
28.1.5 Data Sli cer Use Conditions
Table 28.3 indicates the conditions of use of the data slicer.
Table 28. 3 Data Sli cer Use Conditions
Sync Signal Input for Sync Separ ation Data Slicer
Sync separation signal input from CVin2 Usable
Sync separation signal input from Csync Usable
Hsync or Vsync separation signals Usable
Rev. 1.0, 02/00, page 803 of 1141
28.2 Register Descript i on
28. 2. 1 Sli ce Eve n- (O dd-) Fiel d Mode Regist er (SEVFD, SODFD)
(1) Slice even-fi eld mode regist er
8
0
9
STBE1
R/W
0
10
STBE2
R/W
0
11
STBE3
R/W
0
12
STBE4
R/W
01
13
—
—
0
15 14
EVNIF
R/(W)*R/W
STBE0
0
R/W
EVNIE
Bit:
Initial value:
R/W:
0
0
1
DLYE1
R/W
0
2
DLYE2
R/W
0
3
DLYE3
R/W
0
4
DLYE4
R/W
00
5
SLVLE0
R/W
0
76
SLVLE1
R/W R/W
DLYE0
0
R/W
SLVLE2
Bit:
Initial value:
R/W:
(2) Sli ce odd-fie ld mode register
8
0
9
STBO1
R/W
0
10
STBO2
R/W
0
11
STBO3
R/W
0
12
STBO4
R/W
01
13
—
—
0
15 14
ODDIF
R/(W)*R/W
STBO0
0
R/W
ODDIE
Bit:
Initial value:
R/W:
0
0
1
DLYO1
R/W
0
2
DLYO2
R/W
0
3
DLYO3
R/W
0
4
DLYO4
R/W
00
5
SLVLO0
R/W
0
76
SLVLO1
R/W R/W
DLYO0
0
R/W
SLVLO2
Bit:
Initial value:
R/W:
Note: * Only 0 can be written to clear the flag.
The SE VFD and SODFD cont r ol the start bit detec ti on sta rti n g posit ion, sli ce vol ta ge level, data
sam p li n g delay tim e, and interrupts. The SEVFD holds set ti n gs for even fiel d s, and the SODFD
holds se t tings for odd fields. When re set, when the m odule is stopped, in sleep mode, in standby
mod e, i n watc h mode, in subacti ve mod e, or in subsleep mode, the SE VFD and SODFD are both
initialized to H'2000.
The SEVFD and SODFD are 16-bi t read/ write register s; however, rewritin g of SEVFD or SODFD
should be performed after output of an even- (odd-) field slice completion i nterrupt. During data
slice operations, if SEVFD or SODFD is rewritten, a malfunction wi ll result; do not pe rform
rewriting during data slice operation.
Rev. 1.0, 02/00, page 804 of 1141
Bit 15Even- (Odd- ) Field Sli ce Completion Interr upt E na ble Flag (EVNIE, ODDIE) :
Enables or disables the generation of even- (odd-) field sli ce comple tion interrupts.
Bit 15
EVNIE
ODDIE Description
0 Disables even- (odd-) field slice completion interr upt (Initial value)
1 Enables even- (odd-) field slice completion interrupt
Bit 14Even- (Odd- ) Field Sli ce Interrupt Co mple tio n Fl ag (EVNIF, O DDIF): Se t whe n da ta
slicing for all specified lines of even (odd) field is completed.
Bit 14
EVNIF
ODDIF Description
0 [Clearing condit ion]
When 0 is written after reading 1 (Init ial value)
1 [Setting condition]
When dat a slicing is completed for all specif ied lines of even (odd) field
Bit 13Reserved: Cannot be mo dified an d is always r ea d as 1 .
Bits 12 to 8Start Bit Detection Starting Position Bits:
(STBE4 to STBE0) (STBO 4 to STBO 0): Set the starting position for start bit detection in even
(odd) fields.
The base point for the data slicer is the falling edge of the horizontal sync signal (slicer base point
H) synchronized within the LSI; the starti ng position for start bit detection can be set using STBE4
to STBE 0 (STBO4 to STBO0) in 288 × fh (where fh is the hori z ontal sync signal frequency)
clock units from approxi mate ly 23.5 µs after the data slicer base point.
The start bit detection e nd posit i on is at approximately 29.5 µs after the data slicer base point.
In start bit detection, the presence of the rising edge of start bits in the interval between these
starting and ending positions is detected. Furt her, the start bit detection window si gnal, whi ch
becomes the base point for the start bit detection starting position, can be adjusted by means of the
data slicer det ection window register of the sync separator. For details, refer t o section 27.2. 10,
Data Slicer Detection Window Register (DDETWR).
Figure 28. 2 shows the data slicer base point a nd sta rt bit detection starting posit ion.
Rev. 1.0, 02/00, page 805 of 1141
Clock run-in
Data slicer base point
Clock run-in detection
window signal
Start bit detection
window signal
Data slicer
base point Base point for start bit
detection starting position
Approx. 23.5 µs
Start bit detectable
period
TS
Te = Approx. 29.5 µs
1
288 × fh
TS = 23.5 µs + µs × (Set by STB4 to STB0)
C.video
S1 S2 S3
Start
bit
Set by STB
Figure 28.2 Data Slicer Base Point and Start Bit Detection Starting Posi tion
Bits 7 to 5—Slice Le vel Setting Bi ts (SLVLE2 to SLVLE0) (SLVLO2 to SLVLO0): Specify
the even (odd) field data slice le vel.
The data slice level is c ommon t o clock line detection, sta rt bit detection, a nd 16-bit data slicing.
Bit 7 Bit 6 Bit 5
SLVLE2
SLVLO2 SLVLE1
SLVLO1 SLVLE0
SLVLO0 Description
0 Slic e lev e l is 0 IRE ( Initial value )0
1 Slic e lev e l is 5 IRE
0 Slic e lev e l is 15 IRE
0
11 Slic e lev e l is 20 IRE
0 Slic e lev e l is 25 IRE01 Slic e lev e l is 35 IRE
0 Slic e lev e l is 40 IRE
1
1
1 Must not be specified
Note: All slice levels are with reference to t he pedestal level (5 IRE). Slice level values ar e
provided for reference.
Rev. 1.0, 02/00, page 806 of 1141
Bits 4 to 0Data Sampling Delay Ti me Setting Bits (DLYE4 to DLYE0) (DLYO4 to
DLYO0): Set the even (odd) fie ld data sampling cl ock del ay time.
Figure 28. 3 explains the data sampling cl ock.
The data sampling clock is a clock with period 32×fh, used for slicing 16-bit closed caption dat a.
The data sampling clock is generated after the rising edge of the start bit is detected and the time
set by the DLY bit is passed. The delay time setting can be adjusted in units of 576 × fh, so that
sampling is possible at a phase optimal for the slice data. The data sampling delay time (TD)
should be set based on the c alculation indicated be low. Eighteen pulses of data sam pling cl ock are
output in total for start bit detection, slice data, and end data detection. In order to make the
sampling ph ase even mo re opt imal, the sl ice data (an alo g comp arator output ) and sampling clock
can be output from t he port. For details of monitor output, refer t o section 28.2.6, Monit or Output
Setting Register (DOUT).
TD = 111.1 ns (1/ 576 × fh ) × [setting in bits DLY4 to DLY0 + 2]
fh: Horiz ontal sync signal frequency
Start
bit
Slice data
1st character
S1 S2
32 × fh
S3
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
LSB
2nd character
Detected start
bit
Data sampling
clock
32 × fh
TD: Data sampling delay time specified by DLYE4 to DLYE0 (DLYO4 to DLYO0)
TD = ns × [setting in bits DLY4 to DLY0 + 2]
MSB
1
576 × fh
Figure 28.3 Data Sampling Clock De scription
Rev. 1.0, 02/00, page 807 of 1141
28.2.2 Slice Line Setting Re gisters 1 to 4 (SLINE1 to SLINE4)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
1
—
56
0
7SLINEn4 SLINEn3 SLINEn2 SLINEn1 SLINEn0
0
R/W
SENBLn
R/WR/WR/W
SFLDn —
Bit:
Initial value:
R/W:
The slice line setting registers 1 to 4 (SLINE1 to SLINE4) specify slice fields and lines. Up to four
slice lines can be specified; these are specified in the slice line setting registers 1 to 4 respectively.
These a re 8-bit read/write registers. Rewrites of SLINE should be performed after an eve n (odd)
field slice completion interrupt is output, or after module stop mode has been set, registers have
been initi alized, and module stop mode has been cleared agai n. If SLINE i s rewrit ten during a data
slice opera tion, a malfunction will result; do not perform rewriting during data sli ce operation.
When reset, when the module is stopped, in sleep mode, in standby mode, in watch mode, in
subactive mode, or in subsleep mode, the registers are initialized to H'20.
Bit 7Slice Enable Bit (SENBLn n=1 to 4): Enables or disables data slice operations for the
line specified by SFLDn and SLINEn4 to SLINEn1.
When data slicing for a given line is completed, this bit is reset to 0, and slicing is not again
performed until it is set to 1. This bit is se t at the ri sing e dge of the Vsync signal; henc e data
slicing settings become valid from the rising edge of the next Vsync signal after this bit has been
set. When 1 i s written t o this bit , the correspondi ng slice detection register is cleared, and so
caution should be exercised.
Bit 7
SENBLn Description
0 When read: Disables data slice operation f or the specified lines
[Clearing condition]
When the data slice operation f or the line has been com pleted
1 Enables data slice operat ion for the specified lines
Bit 6Field Setti ng Bit (SFLDn n=1 to 4): Specifies the fi eld of t he slice line. For i nformation
on field discrimination, refer to section 27.2. 6, Field Detection Window Re gi ster (FWIDR).
Bit 6
SFLDn Description
0 Even field (Initial value)
1 Odd field
Rev. 1.0, 02/00, page 808 of 1141
Bit 5Reserved: Cannot be modified and is always read as 1.
Bits 4 to 0Slice Li ne Setting Bits (SLINE4 to SLINE0): Spec if y t he d at a s lic e lin e. S lic e lin es
up to H'1F (31) c an be specified.
Figure 28.4 expla ins the line count .
9-line vertical sync pulse period
Pre-equalizing
period
Sync separation
base point
01
12345678910 192021
H'11
23456 15161718
Line count
Clear
Post-equalizing
period
Vertical synchro-
nization period
Line count specified by
SLINEn4 to SLINEn0
(n = 1 to 4)
Fi g ure 28.4 Line Co unt
28. 2. 3 Sli ce Detec t ion Regi st er s 1 to 4 (SDTCT1 to SDTCT4)
0
0
1
0
R
2
0
R
3
0
4
1
—
0
R
56
0
7— CRICn3 CRICn2 CRICn1 CRICn0
0
R
CRDFn
RRR
SBDFn ENDFn
Bit:
Initial value:
R/W:
The slice detection registers 1 to 4 (SDTCT1 to SDTCT4) store information on data slice results.
Data slice result information incl udes the clock run-in det ection flag, start bit detection fla g, dat a
end detection fl ag, and run-in pul se count for the c l ock run-in period.
This information is useful for optimal positioning of the data slicer slice level, start bit detection
timing, and sampling clock generation timing.
There are four slice detection registers; data slice information results are stored in them on
completion of data slicing for each line specified by the slice line setting registers 1 to 4. Data is
stored not in slicing order, but in the corresponding registers. For information on the slice line
sequence, re fer to section 28.3.2, Slice Sequence.
Rev. 1.0, 02/00, page 809 of 1141
Slice line setting register n
Line m
Slice detection register n
Data slice result information
for line m
Fi g ure 28.5 Rel ati onship between Sli ce Li ne Setti ng Reg ister a nd Slice De tecti on Regist er
SDTCT is an 8-bit read-only re gister. SDTCT rea d operations shoul d be perform ed after an e ven
(odd) field slice completion interrupt. If SDTCT is read during a data slice opera tion, an
indeterminate val ue may be re ad; the register should not be read during operation.
If 1 is written to bit 7 (SENBL) of slice line setting registers 1 to 4, the c orresponding slice
detection register is automatically cleared, so caution should be exercised.
When reset, when the module is stopped, in sleep mode, in standby mode, in watch mode, in
subactive mode, or in subsleep mode, the registers are initialized to H'10.
Bit 7Clock Run- In Detec tion Flag (CRDFn n=1 to 4): Set when, duri ng the c lock run-in
period, the count is concluded in the range 3 to 7 pulses, and clock run-in is detected. When 16 or
more pulses are c ounted, further input pulses are not counted in order to prevent errone ous
detection, a nd an overflow st ate is maintained. Furt her, the clock run-i n detection window signal
indicating the clock run-in period can be adj usted using the DDETWR re gi ster of the sync
separator. For details, refer to section 27.2. 10, Data Slicer Detection Window Registe r
(DDETWR).
Bit 7
CRDFn Description
0 Clock run-in not detected for line for data slicing (Initial value)
1 Clock run-in detected f or line for dat a slicing
Bit 6Start Bi t Dete c tion Flag (SBDFn, n=1 to 4): Set when the start bit for a line for data
slicing is detected.
Bit 6
SBDFn Description
0 Start bit not detected for line for data slicing (Initial value)
1 Start bit detected for line for data slicing
When the start bit is not detected, the data sampling clock is generated after the time set as the
data sampling delay time (DLY4 to DLY0) has elapsed from the phase of the start bit detection
end position.
Rev. 1.0, 02/00, page 810 of 1141
Data slicer base
point
Data sampling
clock
Start bit detection starting position
Start bit detection end position
C.video
Delay
Start
bit
Figure 28.6 Data Sampling Clock Whe n Start Bit is not Detected
Bit 5Data End Detection F lag (ENDF n n=1 to 4): Shows whet her or not slice data is input at
the 18th sampling clock pulse. This flag is set when the slice data is 0, that is, when data slicing is
regarded as having been completed normally.
Bit 5
ENDFn Description
0 Data end not det ected for line for data slicing (Init ial value)
1 Data end dete cted for line for data slicing
Bit 4Reserved: Cannot be modified and is always read as 1.
Bits 3 to 0Clock Run-in Co unt Val ue (CRICn3 to CRICn0): Count result for run-in pulses
during the clock run-in period. When 16 or mor e pulses are input, furthe r input pulses ar e not
counted in order to prevent erroneous detection, and a n overflow state i s maintained. Further, the
clock run-in detection window signal indicating the clock run-in period can be adjusted using the
DDETWR register of the sync separator. For details, refer to section 27.2.10, Data Slicer
Detection Window Register (DDETWR).
Rev. 1.0, 02/00, page 811 of 1141
28. 2. 4 Sli ce Da ta Regi ster s 1 to 4 (SDATA1 to SDATA4)
15
*
R
14
*
R
13
*
R
12
*
R
11
*
R
10
*
R
9
*
R
8
*
R
7
*
R
6
*
R
5
*
R
4
*
R
3
*
R
2
*
R
1
*
R
0
*
R
Bit:
Initial value:
R/W:
*: Unefined
The sl ic e data reg i ste rs 1 to 4 (SDATA1 to SDATA4) are register s in which the slice re sult s are
stored. The da ta is store d in LSB-first fashion, i n order from the LSB side nea r the start bit. Figure
28.7 shows how to store t he sl ice data.
15
b20
14
b21
13
b22
12
b23
11
b24
10
b25
9
b26
8
b27
7
b10
6
b11
5
b12
4
b13
3
b14
2
b15
1
b16
0
b17
b17S3S2S1 b16 b15 b14 b13 b12 b11 b10 b27 b26 b25 b24 b23 b22 b21 b20
LSB MSB
Bit
Slice data
register
Slice data
Fi g ure 28.7 Rel ati onship between Sli ce Data and Slice Data Regi ster
There are four slice data registers, in which are stored slice results when data slicing is completed
for each line specified by the sli ce line setting registers. At this time dat a is stored in the
corresponding registers, rather t han in the slicing order.
Slice line setting register n
Line m
Slice data register n
Data slice result for line m
Fi g ure 28.8 Rel ati onship between Sli ce Li ne Setti ng Reg ister a nd Slice Dat a Regist er
These are 16-bit read-only registers. SDATA read operations should be performed after an even
(odd) field slice completion interrupt. If an SDATA regi st er is read during a data slice opera t ion,
an indeterminate value may be read; the register should not be read during operation.
Rev. 1.0, 02/00, page 812 of 1141
When reset, when the module is stopped, in sleep mode, in standby mode, in watch mode, in
subactive mode, or in subsleep mode, the SDATA register values are indeterminate.
28. 2. 5 Modul e Sto p Contr ol Regi ster (MSTPCR)
7
1
R/W
MSTP
15 MSTP
14 MSTP
13 MSTP
12 MSTP
11 MSTP
10 MSTP
9MSTP
8MSTP
7MSTP
6MSTP
5MSTP
4MSTP
4MSTP MSTP
1MSTP
0
6
1
R/W
54
1
R/W
MSTPCRH MSTPCRL
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Bit:
Initial value:
R/W:
The MSTPCR consists of two 8-bit read/wri te regist e rs for c ontrolling the module stop mode.
Writing 0 to the MSTP3 bit starts the data slicer; setting the MSTP3 bit to 1 stops the data slicer at
the end of a bus c ycle a nd the m odule stop mode i s entered. Before writing 0 to this bit , set the
MSTP9 bit to 0, to operate the sync separator.
The registers cannot be read or written to in module stop mode. For details, refer to section 4.5,
Module Stop Mode.
Bit 3Module Stop (MST P3): Specifies the module stop mode for the data slicer.
Bit 3
MSTP3 Description
0 Clears the module stop mode for the data slicer
1 Specifies the module stop mode for the data slicer (Initial value)
Rev. 1.0, 02/00, page 813 of 1141
28.2.6 Monitor O utput Se tting Register (DOUT)
0
1
1
1
—
2
0
R/W
3
0
4
1
R/W
0
R/W
56
0
7DOBC DSEL CRSEL — —
0
—
—
—R/WR/W
RGBC YCOC
Bit:
Initial value:
R/W:
The internal signals used by the data slicer can be monitored through the R, G, B, YCO, and YBO
pins. For the bits other than bits 2 and 3, refer to section 29.7.3, Digital Output Specification
Reg i ste r (DOUT ).
Bit 3Bit to Select Functions for R, G, B, YCO, YBO Pins (DSEL): Selects whether the
digital output pi ns output R, G, B, YCO, and YBO signals, or output data slicer int ernal monitor
signals.
Bit 3
DSEL Description
0 R, G, B, YCO, and YBO signals selected (Init ial value)
1 Data slicer monitor signals selec ted
Pin R: Signal selected by bit 2 ( CRSEL)
Pin G: Slice data signal analog-com pared with Cvin2
Pin B: Sampling clock generated within data slicer
Pin YCO: Ex t ernal Hsync signal (AFCH) synchronized in the LSI
Pin YBO: External Vsync signal (AFCV) synchronized in the LSI
Bit 2Monitor Signal Select Bi t (CRSEL): Selects whether the clock run-in detection window
signal is output, or the start bit detection window signal i s output. This bit is valid whe n DSEL is
set to 1 to select data slicer internal monitor signal output.
Bit 2
CRSEL Description
0 Clock run-in detection window signal output selected (Initial value)
1 Start bit dete ction window si gnal ou tpu t selected
Rev. 1.0, 02/00, page 814 of 1141
28.3 Operation
28.3.1 Slice Line Specification
Up to four slice l ines can be specified using the sli ce line setting registers 1 to 4. For i nformation
on field discrimination, refer to section 27.2. 6, Field Detection Window Re gi ster (FWIDR).
After completion of data sl icing for all lines specified by registers, a slice completion i nterrupt is
output; the slice result s and slice informa tion should then be read.
Slice inform ation i ncludes clock run-in detection, start bit detection, and data end detection to
determine whether data sampling was performed normally; this information is stored in slice
detection regi sters 1 to 4.
After completion of slicing for specified lines, the slice enable bit for the slice line setting register
is reset to 0. The next time the data slicer is operated, the slice enable bit of the slice line setting
register should be set to 1. At t his time, the corresponding slice detec tion register i s cleared. T he
slice enable bit is sampled at the rising edge of the Vsync signal. Hence enabling of slice operation
is valid until the next Vsync signal after reset of the slice enable bit.
Figures 28.9 and 28. 10 show examples of slice line specification and operation. For details, refer
to section 28.2.2, Slice Line Setting Registers 1 to 4.
Rev. 1.0, 02/00, page 815 of 1141
The data slicer initialization and operation for one specification example are shown in figure 28.9.
Reset the slice enable bit
Reset the slice enable bit
Generate an even field slice completion
interrupt
Contents of slice line setting registers
Slice Line Setting Register
Register No.
1
2
3
4
1
1
1
0
Even
Odd
Even d > c
b > aOdd
Enable Field Line
Start
Initialize the data slicer
Reset the slice enable bit
Generate an odd field slice completion
interrupt
Even field
Odd field
Line c
Line b
Line d
Line a
Set the slice (even and odd)
field mode registers
Set the slice line setting
registers 1 to 4
(except the enable bits)
An external Vsync interrupt
occurs
Execute slicing for line b
An external Vsync interrupt
occurs
Execute slicing for line d
Execute slicing for line c
An external Vsync interrupt
occurs
Set the enable bits of
the slice line setting
registers 1 through 3 to 1
Note: Data slice operation is not performed for line a, because the enable bit = 0. Further, when the same line
is specified within the same field, erroneous operation results; do not specify the same line in the same
field. For details on the external Vsync interrupt, refer to section 27.2.2, Sync Separation Control
Register (SEPCR).
Figure 28.9 Example of Slice Line Specification and Operation (1)
Rev. 1.0, 02/00, page 816 of 1141
Operation for data slicer resetting for a second specification is shown in figure 28.10.
a < b < c < d
Start
Respecification
Even field
Contents of slice line setting registers
Slice Line Setting Register
Register No.
1
2
3
4
1
1
1
1
Even
Even
Even
Even
Enable Field Line
Line a
Line b
Line d
Line c e < f < g < h
Contents of slice line setting registers
Slice Line Setting Register
Register No.
1
2
3
4
1
1
1
1
Odd
Odd
Odd
Odd
Enable Field Line
Line e
Line h
Line f
Line g
An external Vsync interrupt
occurs
Execute slicing for line a
Execute slicing for line b
Reset the slice enable bit
Reset the slice enable bit
Execute slicing for line c Reset the slice enable bit
Execute slicing for line d Reset the slice enable bit
Generate an even field slice completion
interrupt
Read each slice detection
register and slice data register.
Respecify slice lines and
set the slice enable bit.
Odd field
An external Vsync interrupt
occurs
Execute slicing for line e
Execute slicing for line f
Reset the slice enable bit
Reset the slice enable bit
Execute slicing for line g Reset the slice enable bit
Execute slicing for line h Reset the slice enable bit
Generate an odd field slice completion
interrupt
Read each slice detection
register and slice data register.
Respecify slice lines and
set the slice enable bit.
An external Vsync interrupt
occurs
Figure 28.10 Example of Slice Line Specification and Operation (2)
Rev. 1.0, 02/00, page 817 of 1141
28.3.2 Slice Sequence
Figure 28. 11 shows the slice sequence.
Yes
No
Is it the last
line in the field to be
sliced?
• Line detection
The specified slice line and field match the line
count and detected field
• Clock run-in detection
Count the number of clock run-in pulses in clock
run-in period
• Start bit detection
Initiate start bit detection according to the start
bit detection starting position specified by
the register
• Data sampling
Data is stored in the 16-bit shift register at a data
sampling clock of 32xfh generated after the time
specified by the register from the start bit
detection
Store data in the
16-bit shift register
to the slice data
register
• Data end detection
Detect whether or
not slice data is input
at the 17th data
sampling clock pulse
Set the clock run-in count
Set the start bit detection flag
(Enable the start bit detection)
Set clock run-in detection flag
(Enable the clock run-in detection)
Set the slice completion interrupt
flag
Read the slice detection register
and slice data register
Write the slice line setting
register
Set the slice line enable bit
Set the data end detection flag
(Data end: No data detected at
the 17th data sampling clock
pulse)
Reset the slice enable bit
Fi g ure 28.11 Slice Se que nce
Rev. 1.0, 02/00, page 819 of 1141
Section 29 On-Screen Display (OSD)
29.1 Overview
OSD (on-screen di splay) is a function for superimposing arbitrary characters or di splay patterns on
a TV image signal.
The display screen consists of up to 32 characters × 12 rows; a single character consists of 12 dots
× 18 lines. Up to 384 different charac ter types can be regi stered, and each character display can be
connected to the top, bottom, right, and left of another character. Hence in addition to
alphanumerics and kanji characters, graphics can also be displayed.
Text display and superimposed di splay are supported, and there are c omposite video signal output
and digital outputs.
There are a we alth of orname ntal features as well, including blinking displa y, borde rs, cursors,
halftone di splay, but tons, and e nlarged display.
Analog functions (video amp, analog switch) peripheral to OSD are also incorporated. The sync
separator has an AFC circuit built-in, for sta ble displa y.
OSD ca n be used in data encodin g in the U.S. clo sed ca pti on format.
29.1.1 Features
• Screen conf igur ation: 32 charact ers × 12 rows
• Character size: 12 dots × 18 lines
• Character types: 384 types*1
• Supports t ext displa y and superimpose d display
• Display enlargement: 1×1, 2×2 (line units, vertical × horizontal)
• Blinking: Can be set in single character units
Blinking peri od can be set to either 32/fV or 64/ fV (for the entire sc reen)
(fV: vert ical sync signal freque ncy)
• Border function: Single-dot borders in each of eight directions
Border color: In text mode, white or black, and brightness fixed
In superimposed mode , black, and brightness fixed
• Support ed TV form ats : NTSC, PAL, SECAM
• Display position: Horizontal and vertical direction leading positions are set, and line intervals
can be set
• Digital output s: R, G, B; output of YCO (character da ta bit strings) a nd YBO (character
display positions)
Rev. 1.0, 02/00, page 820 of 1141
• Background colors: Eight hues*2
Background brightness, chroma saturation: Four brightness levels, two chroma levels
• Character colors: Text display: Eight hues (character units)*2
Superimposed display: Whi te
Character brightne ss, chroma sa turation: Four bright ness levels, two chroma l evels
• Cursor: Character background c olored duri ng text display (c haracter units)
• Cursor colors : Eight hues (line units)*2
Cursor brightness, chroma saturation: Two brightness levels, t wo chroma l evels
• Halftone display: Feature for reducing the brightness/chroma saturation of the image signal in
the text background during superimposed di splay to re nder it semi-transparent, so that
characters appe ar to float above the backgrou nd (ch ara ct er units)
• Halftone gray shades: Two le vels (row units)
• Button display: Two types
Notes: 1. Includes bl ank ch aract er as chara ct er code H'000.
2. Background colors, charact er colors, cursor colors: the background, chara cter, and
cursor colors in text displa y include bla c k a nd white. In SECAM, only black and white
are support ed. For details, refe r to section 29.1.5, TV Forma ts and Displ a y Mode s.
Rev. 1.0, 02/00, page 821 of 1141
29.1.2 Block Diagram
A block dia gram of t he OSD appears in figure 29.1.
Sync separator
TV format
4/2fsc Dot
clock
4/2fsc in
CVin1
4/2fsc out
HV
Horizontal
display
position
control
Display data RAM
Vertical
display
position
control
Button control
Shift register
Border control
4/2fsc
oscillator
CVout
Halftone
control
Sync tip
clamp
SECAM
character
control
Switch-
ing
Color burst
Character, back-
ground, and cursor
color generation
Display control
Character, border,
cursor, button, and
background
R
G
B
YCO
YBO
Character data ROM
Figure 29.1 OSD Block Diagra m
Rev. 1.0, 02/00, page 822 of 1141
29.1.3 Pin Confi guration
Th e OSD pin con fig u rati o n is sh own in table 2 9.1. Even when not u si ng the dat a slice r , the
composite video signal should be input to Cvin2 in order to perform sync sepa ration from the
composite video signal.
Tabl e 29. 1 OSD Pi n Config ur ati o n
Block Name Abbrev. I/O Function
Csync/Hsync Input/output Composite sync signal input/output or
horizontal sy nc signal input
Sync signal
input/output VLPF/Vsync Input Pin for connect ing external LPF for
vertical sync signal or input pin for
vertical sync signal
AFCosc Input/ output AFC oscillation signalAFC
oscillation AFCpc Input/output AFC by- pass capacitor connecting pin
Sync
separator
LPF for AFC AFCLPF Input/output Ext ernal LPF connecting pin for AFC
OSD analog
power OVcc Input Analog power for OSD, dat a slicer,
and sync separator
OSD analog
ground OVss Input Analog gr ound for OSD, data slicer,
and sync separator
Composite
video signal
input
CVin1 Inpu t Composi te video si gnal inpu t (2 Vpp,
with a sync tip clam p circuit)
Composite
video signal
output
CVout Output Composite video signal output (2 Vpp)
4fsc/2fscin Input 4fsc or 2fsc inputfs c osc illa tion
4fsc/2fscout Output 4f sc or 2f sc output
R Output Color signal output (R) for character,
border, cur sor, background, and
button, or a port
G Output Color signal output (G) for chara cte r ,
border, cur sor, background, and
button, or a port
Color signal
output
B Output Color signal output ( B) for character,
border, cur sor, background, and
button, or a port
YCO Output Character data output (digital output),
or a por t
OSD
Character
data output
YBO Output Character display position output
(digital output), or a port
Rev. 1.0, 02/00, page 823 of 1141
Block Name Abbrev. I/O Function
Data
slicer Composite
video signal Cvin2 Input Co mposi te video si gnal inpu t (2 Vpp,
with a sync tip clam p circuit)
29.1.4 Register Configurati on
Ta ble 29. 2 shows t he OSD registe rs.
Table 29. 2 Register Configurati on
Name Abbrev. R/W Size Initial
Value Address*1
Character dat a ROM O SDROM — 24576 bytes — H'040000
Display dat a RAM (Master) OSDRAM R/W 768 bytes Undefined H'D800
Display d ata RAM (Slav e) — 768 bytes Undefined —
Row re g ister 1 CLINE1 R/W Byte H'00 H'D200
Row re g ister 2 CLINE2 R/W Byte H'00 H'D201
Row re g ister 3 CLINE3 R/W Byte H'00 H'D202
Row re g ister 4 CLINE4 R/W Byte H'00 H'D203
Row re g ister 5 CLINE5 R/W Byte H'00 H'D204
Row re g ister 6 CLINE6 R/W Byte H'00 H'D205
Row re g ister 7 CLINE7 R/W Byte H'00 H'D206
Row re g ister 8 CLINE8 R/W Byte H'00 H'D207
Row re g ister 9 CLINE9 R/W Byte H'00 H'D208
Row re g ister 1 0 CLINE10 R/W Byte H'0 0 H'D209
Row re g ister 1 1 CLINE11 R/W Byte H'0 0 H'D20A
Row re g ister 1 2 CLINE12 R/W Byte H'0 0 H'D20B
Ver tical displa y position
register VPOS R/W Word H'F000 H'D20C
Horizontal display position
register HPOS R/W Byte H'00 H'D20E
Digit a l o utput sp ecif ic a tion
register DOUT R/W Byte H'02 H'D20F
Screen control register DCNTL R/W W ord H'0000 H'D210
OSD format register DFORM R/(W)*2Word H'00F8 H'D212
Notes: 1. Lower 16 bits of the address. (excluding character data ROM)
2. O nly 0 can be written to bits 8 and 0 to clear t he flags.
Rev. 1.0, 02/00, page 824 of 1141
29. 1. 5 T V F orm ats and Displ ay Modes
Table 29. 3 indicates support for diffe rent TV formats in each display mode. Opera tion is not
guaranteed if a frequency resulting from division by 4 or 2 from the 4fsc/2fsc input pin is not one
of those listed in table 29.3.
Table 29. 3 TV Formats and Display Modes
TV Format fsc (MHz) Text Display Superimposed M ode
M/NTSC 3.579545 8 colors Supported
4.43-NTSC 4.43361875 8 colors Supported
M/PAL 3.57561149 8 colors Supported
N/PAL 3. 58205625 8 colors Supported
B.G. H/PAL, I/PAL,
D.K/PAL 4.43361875 8 colors Supported
SECAM 4.43361875 White/black Supported
29.2 Description of Display Funct ions
29.2.1 Superimposed Mode and Text Display Mode
There are two types of OSD display: super im po sed and text displ ay.
(1) Superimposed Mode
In supe rimposed m ode, the state of operation of a VCR, the curre nt tim e, and other text and
graphics a re displa ye d on an ordina ry TV image. In doing so, there is no mixing of the background
image and the display character colors. There is an internal AFC circuit, enabling reliable text
display. In addition, a halftone function, in which the brightness and chroma saturation of the
background scree n in the charac ter displa y area is redu ced to make chara ct ers appear to “float ”
above t he background, is also ava ilable. Other fe atures include a character border funct ion.
(2) Text Display M ode
In text display mode , characters and gra phic data can be displaye d in synchronous with t he
internal sync signal generated by the internal Csync generator circuit in the sync separator. The
background color for display can be selected from among eight hues. There are plentiful
ornamenta l func tions , includ ing functio ns for displaying cursors and buttons; cursor and text
colors can be selected from am ong eight hues, ma king this function i deal for use in programming
VCR recording and setting modes.
Rev. 1.0, 02/00, page 825 of 1141
29.2.2 Character Configuration
Displayed characters and patterns consist of 12 dots × 18 lines per character. There are notes on
creation of OSD font s. For de tails, refer to se cti on 29.8, Notes on OSD Font Cr eat ion.
An example of a character c onfiguration appears in figure 29.2. An example of a n enlarge d
character appears in figure 29.3.
12 dots
18 lines
Characters Borders
(1) Character configuration example (2) Character configuration example
(with borders outside character)
Figure 29.2 Character Confi guration Examples
Rev. 1.0, 02/00, page 826 of 1141
12 dots
24 dots
18 lines
36 lines
(1) Standard character size (2) Enlarged character size
Figure 29.3 Enlarged Character Example
29. 2. 3 On-Sc re e n Displ ay Config ur a tion
The on-sc reen displa y area consists of 12 horizontal rows each containing up to 32 characters.
The correspondence between display data RAM and the screen display is indicated in figure 29.4.
The starting position for display can be set freely by using the display position registers to set the
horizontal starting display position, vertical starting displa y position, and row interval. Even when
the frequenc y of the AFC reference cl ock (dot clock) is modified, the di splay confi guration (12
horizontal rows each containing 32 characters) wil l not c hange; characters i n the region prot ruding
outside the display area should be blank characters.
For informa tion on the displa y position registers, refe r to section 29.5.1, Display Positions, and
sec ti on 29.5 . 8, Disp lay Posi ti on Re giste rs ( HPOS, VPOS) .
Rev. 1.0, 02/00, page 827 of 1141
Row 1
Row 2
Row 11
Row 12
1st
character
D800
D840
DA80
DAC0 DA82
DAC2 DA84
DAC4 DA86
DAC6 DABE
DAFE
D802
D842 D804
D844 D806
D846 D83E
D87E
Note: D800 to DAFF indicate the lower 16 bits of addresses in the on-screen display RAM.
32nd
character
2nd
character 3rd
character 4th
character
Fi g ure 29.4 Corre spo nde nce betwee n Displa y Data RAM and On-Scre e n Displ ay
29.3 S et ti ngs in Character Units
The following items can be set in character units by using the display data RAM.
29.3.1 Character Configuration
Characters c an be set freely by writing, to the display da ta RAM, the character da ta ROM address
(character code) at which th e ch aracter to b e displayed is stored .
For explanations of the c haracter da ta ROM and displa y data RAM, refer t o section 29.3.6,
Cha racter Data ROM (OSDR OM), and sectio n 29.3.7, Displ ay Data RAM (OSDRAM).
29.3.2 Character Colors
Character colors in text display mode can be set i n character units through the character col or
specification bit in display data RAM.
Table 29. 4 shows the c orrespondence between cha racter col or code settings and color out put
signals.
For det ai l s on displa y data RAM, ref er to secti o n 29.3.7, Displa y Data RAM (OSDRAM).
In the SECAM TV format, only black and white can be used in text display mode, and in
superimposed mode c ha racters are white, with a fai nt background color.
Rev. 1.0, 02/00, page 828 of 1141
Tabl e 29. 4 Cor respo nde nce bet ween Characte r Col or Code Sett i ng s and Color Out put
Signals
R 111 10000
G 110 01100
B
Display
Dat a RAM
Settings*101 01010
R, G, or B port
output White Yellow Magenta Red Cyan Green Blue Black
C.Video output
(NTSC) White Same
phase 3π/4 π/2 3π/2 7π/4 πBlack
C.Video output
(PAL) White ±0 ±3π/4 ±π/2 ±3π/2 ±7π/4 ±πBlack
Note: *Can be specified in character unit s.
29.3.3 Halftones/Cursors
(1) Halftones
The halftone function reduces the bright ness and chroma satura t ion of the image signal in the
character bac kground t o make it semi-transparent, so that chara cters appear to float above the
background. By specifying hal ft one in t he display data RAM, halft one can be toggled in cha racter
units. Here the halftone levels are specified in the row register.
In the SECAM format, use of halftones is recommende d.
(2) Cursors
The cursor function col ors the background area of a c haracter. By specifying the cursor in display
data RAM, cursor display c a n be toggl ed in character units. The cursor color a nd brightne ss are
specified in the row register; within a given row, the same color and brightness are used. The
chroma saturation can be set for the entire screen.
Note: Cursor display is a funct ion for use in text display m ode only; halftones are a functi on for
use in superimposed mode only. The display data RAM halftone/cursor specification bit is
dual-purpose, so that depending on the di splay mode , function ma y switch aut omatically
between halftone/cursor.
Figure 29. 5 shows exam ples of hal ftone a nd cursor display. For det ails on display dat a RAM, refe r
to sec tio n 29.3 .7 , Di sp la y Data RAM (OSDR AM). For an ex pla nati o n of eac h regi ste r, re fer to
section 29.4. 5, Row Registers (CLINEn, n= rows 1 to 12).
Rev. 1.0, 02/00, page 829 of 1141
18 lines
12 dots
Cursor
(1) Halftone display
(Supported in superimposed mode) (2) Cursor display
(Supported in text display mode)
Background Character
12 dots
Halftone Background Character
18 lines
Figure 29.5 Halftone and Cur sor Display Examples
29.3.4 Blinking
Blinking is a function in which displayed characters are displayed intermittently. By specifying
blinking in display da ta RAM, text can be made to bli nk in character units. T he blinking peri od
can be chosen from two values through the screen control register. Blinking i s supported both in
superimpose d mod e and text display mode.
Digital output s (YCO, R, G, and B) ca n be made to bl ink or not blink t hrough t he digital output
specification register. The YBO di gital output cannot be made to blink.
For det ai l s on displa y data RAM, ref er to secti o n 29.3.7, Displa y Data RAM (OSDRAM).
For an explanation of each register, re fer to section 29.5.9, Screen Control Re gister (DCNTL), and
sec ti on 29.7 . 3, Digit al Outp ut Speci fic at i o n Registe r (DOUT ).
Buttons cannot be made to blink.
For notes on blinking, refer to sec tion 29.8.3, Not e 3 on Font Cre ation (Blinking).
Rev. 1.0, 02/00, page 830 of 1141
29.3.5 Button Display
Button di splay is a function in whic h a frame is dra wn around a cha racter string; butt ons ca n be set
in character units in display data RAM. There are two types of button: one type of button appears
to be ra i sed or floating, and the other type appears to be lowered or sunke n. By switching from the
raised button type to the lowered button type, the button appears to have been depressed; such
displays are ideal for screens on which various settings are to be made.
Button di splays can be used si multaneously with the blinki ng function, but blinking can only be
used f or ch aracte r s ; b u ttons cannot be made to bl in k.
When used with enlarged characters, the button width is enlarged to two dots by two lines.
Buttons are horiz ontal rectangles; vert ical-rectangle butt ons cannot be create d.
In order to create a button with three or more characters, a button display (start) character and a
button display (end) character should be specified.
Multiple buttons can be created in a single row, but the button pattern in a given row is the same
for all buttons in that row.
The button pa ttern can be set i n row uni ts; whi te brightness is 75IRE, and bl ack brightness is 15
IRE. Both are values relative to the pede stal (5 IRE). T hese bright ness val ue s are for reference.
Figure 29. 6 shows exam ples of butt on display.
For d et ai l s on displa y dat a RAM, ref er to sect i o n 29.3.7 , Displa y Data RAM (OSDRAM). Fo r an
explanation of each re gister, refer to section 29. 4.5, Row Re gi sters (CLINEn, n= rows 1 to 12).
In a but ton display, the button pattern re places t he oute r periphery of the 12 dot × 18 line character
region; this should be born in mind when creating chara c ter fonts. Refer to sec tion 29.8.4, Not e 4
on Font Creation (Buttons).
Rev. 1.0, 02/00, page 831 of 1141
BPTn
BON1
BON0
BPTn
BON1
BON0
0
0
0
0
0
1
0
1
0
0
0
0
0
0/1*
0/1*
0
1
1
Note: * Do not set (start) or (end).
1
0
0
1
0
0
1
0
0
1
0
1
1
1
0
1
1
1
Figure 29.6 Button Display Example s
29. 3. 6 Cha r a c ter Dat a ROM (OSDROM)
Th e c haract e r dat a ROM (OSDROM) co nta ins 3 8 4 chara cter types, eac h co nsist ing of 12 dots by
18 lines. User programs ca n write i ndividual cha racter dat a sets. However, charac t er code H'000 i s
fixed as a blank cha racter, a nd a new character pattern for this code cannot be set by t he user.
The c haract e r dat a ROM (OSDROM) is refe rence d by charact e r code s in the display data R AM,
and dots of display c haracter data are read for e ach scanning li ne.
This cha racter dat a ROM c an be a ccessed by the CPU as part of user ROM. For de tails, refe r to
sec ti on 29.1 1, C harac te r Data ROM (OSDR OM) Acce ss by CPU.
The memory map a ppears in figure 29. 7. An example of configuration for a single character
appears in figure 29.8.
Rev. 1.0, 02/00, page 832 of 1141
Memory map
Bit data for character
code H'000
(blank character display)*
Note: Character code H'000 is reserved for blank character display and is not available for the user. All bit data
of this character code must be 0, as shown below.
Line 1,
bits 11 to 8
OSD ROM
Internal I/O registers
Internal I/O registers
OSD RAM
000000
040000
040040
040041
040042
040043
040044
040045
040062
040063
040064
04007F
04013F
045FC0
045FFF
04003F
040040
04007F
040080
0400BF
0400C0
0400FF
040100
040000
045FFF
CPU program
FFFFFF
H' F
H' F
H' F
H' F
H' FF
H' FF
040000 : FH'F0
040001 : FH'00
040002 : FH'F0
040003 : FH'00
040022 : FH'F0
040023 : FH'00
040024 : FH'FF
04003F : FH'FF
:
:
:
:
Bit data for character
code H'001
Bit data for character
code H'002
Bit data for character
code H'003
Bit data for character
code H'004
Bit data for character
code H'17F
Line 1,
bits 7 to 0
Line 2,
bits 7 to 0
Line 3,
bits 7 to 0
Line 2,
bits 11 to 8
Line 3,
bits 11 to 8
Line 18,
bits 7 to 0
Line 18,
bits 11 to 8
) Line 1
) Line 2
) Line 18
Figure 29.7 OSD ROM Map
Rev. 1.0, 02/00, page 833 of 1141
Line number Data
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
32
F000
F000
F3FC
F3FC
F300
F300
F300
F300
F3F0
F3F0
F300
F300
F300
F300
F300
F300
F000
F000
FFFF
FFFF
1110987654321
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
0
Line
12 dots
18 dots
32 words
16 bits
Bit
Unused area
Fi g ure 29.8 OSDROM Data Confi g urat i o n (for the letter “F”)
Note: OSDROM c o nsists of 12 dots × 18 lines per character. When character data is written to
flash me m ory, addre sses are written in a 16-bit × 32-word a rea as shown in fi gure 29.8.
Data in the unused area should be set to 1. In addition, characte r data for blank display
should always be set to 0.
29. 3. 7 Displ ay Data RAM (OSDRAM)
8
*
9
*
R/W
10
*
R/W
11
*
12
*
R/W
*
R/W
1315 BON0 CR CG CB C8
*
R/W
BLNK 14
*
R/W
HT/CR
R/WR/W
BON1
Bit:
Initial value:
R/W:
0
*
1
*
R/W
2
*
R/W
3
*
4
*
R/W
*
R/W
57 C4 C3 C2 C1 C0
*
R/W
C7 6
*
R/W
C6
R/WR/W
C5
Bit:
Initial value:
R/W:
*: Undefined
Displa y data RAM for OSD (OSDRAM) contain s 12 rows of 32 characte r s each, or 384 characte rs
(384 words), and consists of master RAM and slave RAM. Master RAM can be re ad and written
by the CPU; slave RAM is accessed by the OSD.
Rev. 1.0, 02/00, page 834 of 1141
The OSD disp lay chang e s when the data writte n to master RAM is transferred to the slave RAM.
Data is transferred from the master RAM to the slave RAM by setting the LDREQ bit in the OSD
format register to 1. At t his time, when the DTMV bit is 0, t ransfer is performed a t the moment the
LDREQ bit is set t o 1; when the DTMV bit is 1, transfer i s performed i n sync hronous with the
Vsync signal after the LDREQ bit is set to 1. After transfer, the LDREQ bit is cleared to 0. During
transfer, the LDREQ bit remains set to 1; master RAM should be accessed only after confirm ing
that the LDREQ bit has been cleared to 0. If the CPU accesses master RAM during transfer, the
acc e ss is inval i d and the VACS bit in the OSD format registe r is set to 1. The master RAM can be
accessed by the CPU e ve n in the module stop m ode.
After power-down mode is cancelle d, the OSDRAM must be initialized. For details on the OSD
format register, refer to section 29.6.6, OSD Format Re gi ster (DFDRM).
Bit 15Blinking Specification Bit (BLNK): Turns blinking (intermittent displa y) on and off for
characters in character units. Blinking for digital outputs (YCO, R, G, and B) is set by the digital
output spec ification register. Digi tal output (YBO) ca nnot be set to bli nk.
OSDRAM
Bit 15 Description
BLNK C.Video Output
0 Blin k ing is off
1 Blin k ing is o n
DOUT OSDRAM
Bit 4 Bit 15 Description
DOBC BLNK Digital Output (YCO, R, G, B)
0 Blin k ing is off0
1 Blin k ing is off
0 Blin k ing is off11 Blin k ing is o n
Rev. 1.0, 02/00, page 835 of 1141
Bit 14Half tone / Cursor Di spl a y Speci fic a tio n Bit (HT/CR) : Turns halftone/cursor display on
and off in character unit s. The superimposed/text displa y mode switching bi t of the screen control
register is used for switching between halftone and cursor display.
In digital outputs (R, G, and B), when the RGBC bit of the digi tal output spec i fication register i s
set to 1 in either superimposed or text display mode to select output of display data for all of
characters/borders/c ursor/background/ button display, the c ursor c olor data spe cified by the cursor
color specification bit of the row register is output. In SECAM TV format, it is recommended that
halftone di splay be used.
DCNTL OSDRAM
Bit 14 Bit 14 Description
DISPM HT/CR C.Video Output
0 Halftone is off0
1 Halftone is on
0 Cursor display is off1
1 Cursor display is on
DOUT OSDRAM
Bit 6 Bit 14 Description
RGBC HT/CR Digital Output (R, G, B )
0 0/1 Character is output (half tone/cursor specification invalid)
0 Character is output (halftone/ cursor display off)11Cur s or color dat a specified by the curs or colo r sp ecificatio n b it of ro w
register is output
Rev. 1.0, 02/00, page 836 of 1141
Bits 13 and 12Button Specification Bi ts (BO N1 and BO N0): Set buttons in character units in
conjunction with the BPTNn bit of the row register. To create a button with three or more
characters, no-but ton display characters or button di splay (one characte r) must be specified
between a button display (start) character and a button display (end) character. For details, refer to
figure 29.6, Button Display Exa m ple.
CLINEn OSDRAM
Bit 7 Bit 13 Bit 12
BPTNn BON1 BON0 Description Display
0 No button is displayed0
1 Button is displayed (start)
0 Butt on is displayed (end)
0
1
1 Butt on is displayed (one character)
0 No button is displayed0
1 Button is displayed (start)
0 Butt on is displayed (end)
1
1
1 Butt on is displayed (one character)
Rev. 1.0, 02/00, page 837 of 1141
Bits 11 to 9Character Colo r Specific a tio n Bit s (CR, CG, and CB): Spe cify characte r co lor s
in characte r un its.
In superimposed mode, the only character color is white, and register settings are invalid.
For digital outputs (R, G, and B), character color data specified by the character color
specification bits for both superimposed a nd text display m odes is output.
Character Color
Bit 11 Bit 10 Bit 9 C.Video Output
CR CG CB NTSC PAL R,G,B Outputs
0 Black Black Black0
1π±πBlue
07π/4 ±7π/4 Green
0
1
13π/2 ±3π/2 Cyan
0π/2 ±π/2 Red013π/4 ±3π/4 Magenta
0 Same phase ±0 Yellow
1
11 White White White
Bits 8 to 0Charac ter Codes (C8 to C0): Set character codes (H'000 to H'17F) to be displayed.
Note: Cha racter code H'000 i s defined as blank (nothing displa yed).
Character display is not guaranteed if character codes from H'180 to H'1FF are specified.
Rev. 1.0, 02/00, page 838 of 1141
29.4 S et ti ngs in Row Units
The following i tems can be set in row units by using the row re gisters.
29.4.1 Button Patterns
Characters can be set freely by writing, to display data RAM, the character data ROM address
(character code) at which th e ch aracter to b e displayed is stored .
For information on character data ROM and display data RAM, refer to section 29.3.6, Character
Dat a R OM (OSDROM), a nd sec ti on 29.3 .7 , Di splay Data RAM (OSDRAM).
The button pattern specification bit of the row registers can be used to select the button pattern
(raised or lowered pattern) in row units.
29.4.2 Display Enlargement
The size of characters can be selected in row units by using the character size specification bit of
the row register. When sele cting enlarged chara cters, the bord er width and button width also
change to accommodate the character size.
29.4.3 Character Brightness
Character brightness can be set in row units using the character brightness specification bit of the
row registe r. Four different c haracter bri ghtnesses can be selected.
29. 4. 4 Cursor Colo r, Brig ht ne ss, Hal f tone Le vel s
(1) Cursor Color
Cursor c ol ors can be set in row units usi ng the cursor color specification bi t of the row register.
Table 29. 5 shows the c orrespondence between cursor color code settings and color out put si gnals.
Cursor display func tio ns in text displ ay mod e only.
For details on row regist e rs, refer t o section 29.4. 5, Row Regi sters (CL INEn, n=rows 1 to 12).
Rev. 1.0, 02/00, page 839 of 1141
Tabl e 29. 5 Cor respo nde nce bet ween Cursor Color Co de Setti ng s and Color Output Signa l s
R1 0
G10 10
B
Row
Register
Settings*101 01010
R, G, or B port
output White Yellow Magenta Red Cyan Green Blue Black
C.Video output
(NTSC) White Same
phase 3π/4 π/2 3π/2 7π/4 πBlack
C.Video output
(PAL) White ±0 ±3π/4 ±π/2 ±3π/2 ±7π/4 ±πBlack
Note: *Can be set in display block units.
(2) Cursor Brightness
Cursor brightness can be set in row units usi ng the c ursor bri ghtness specification bit of the row
register. Two different brightness levels can be selected.
For details on row regist e rs, refer t o section 29.4. 5, Row Regi sters (CL INEn, n=rows 1 to 12).
(3) Halftone Leve ls
Halftone le vels can be set in row units using the cursor bri ghtness specification bit of the row
register. Two different halftone levels can be selected.
Figure 29. 9 shows exam ples of a halftone level.
Halftone settings functi on only in superimposed mode.
For details on row regist e rs, refer t o section 29.4. 5, Row Regi sters (CL INEn, n = rows 1 to 12).
Rev. 1.0, 02/00, page 840 of 1141
100IRE
0IRE
–40IRE
100IRE
0IRE
–40IRE
100IRE
0IRE
–40IRE
White character
50% halftone
Cursor region
Cursor region
Cursor region
(b) 50% halftone
(a) No halftone
(c) 30% halftone
30% halftone
White character
White character
Figure 29.9 Halftone Level Examples (C.Video)
29.4.5 Row Registers (CLINEn, n = rows 1 to 12)
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
57 CLUn2 KRn KGn KBn KLUn
0
R/W
BPTNn 6
0
R/W
SZn
R/WR/W
CLUn1
Bit:
Initial value:
R/W:
There are a total of 12 row registers (CLINEn), for use with rows 1 to 12.
Row register n is used in conjunction with display data RAM to set the character size, button
pattern, cursor color, etc., for the nth row . Each of these is an 8-bit read/wri te register.
When reset, when the module is stopped, in sleep mode, in standby mode, in watch mode, in
subactive mode, or in subsleep mode, the registers are initialized to H'00.
Rev. 1.0, 02/00, page 841 of 1141
All of the row regi sters 1 t o 12 have the same spec i fiable format.
When the OSD display updat e timin g co ntrol bit (DTMV) is 1, the OSD displ ay is upda te d to the
row register settings in sync hronous with the Vsync signal (OSDV).
Bit 7Button P attern Specification Bi t (BPTNn n=1 to 12): Sets the button pattern for the nth
row. For button specific ation, refer to section 29.3.7, Displ ay Data RAM (OSDRAM).
Bit 7
BPTNn Description
0 Patt ern causing buttons in t he nth r ow to appear to be r aised
AA
(Init ial value)
1 Patt ern causing buttons in t he nth r ow to appear to be lowered
AA
Bit 6Characte r Size Specification Bit (SZn, n =1 to 12): Sets th e si ze of ch ar acters . The
border widt h and button width al so change according to the character size. These sett i ngs are
common to superimposed and text displa y modes and to C.Video output and di gital output s.
Bit 6
SZn Description
0 Character display size: single height × single width (Initial value)
1 Character display size: double height × doubl e wid th
Rev. 1.0, 02/00, page 842 of 1141
Bits 5 and 4Character Brightness Specification Bits (CLUn1 and CLUn0, n = 1 to 12): Set
the character brightness. The character brightness differs with the character color.
In superimposed mode, white is the only character color.
This sett i ng has no effec t on digi tal outputs (YCO, YBO, R, G, a nd B).
Bit 5 Bit 4
CLUn1 CLUn0 Character Color Character Brightness Level
0 0 IRE (Initial value)0
1 10 IRE
0 20 IRE11
Black
30 IRE
0 25 IRE (Initial value)01 45 IRE
0 55 IRE1
1
Blue, green, cyan, red,
yellow, magenta
65 IRE
0 45 IRE (Initial value)0
1 70 IRE
0 80 IRE1
1
White
90 IRE
Note: All brightness levels ar e with r eference to t he pedestal level (5 IRE). Brightness levels are
reference values.
Rev. 1.0, 02/00, page 843 of 1141
Bits 3 to 1Cursor Color Specification Bits (KRn, KGn, and KBn, n = 1 to 12): Set the
cursor color in row units. C.Vi deo output in superimpose d mode uses halftone displa y, so that
cursor color specifications are invalid.
• Cursor Col ors in Text Displ a y Mode
Cursor Color
Bit 3 Bit 2 Bit 1 C.Video Output
KRn KGn KBn NTSC PAL R, G, B Outputs
0 Black Black Black (Init ial value)0
1π±πBlue
07π/4 ±7π/4 Green
0
113π/2 ±3π/2 Cyan
0π/2 ±π/2 Red013π/4 ±3π/4 Magenta
0Same
phase ±0 Yellow
1
1
1 White White White
• Cursor Col ors in Superimposed Mode
Bit 3 Bit 2 Bit 1 Cur sor Col or
KRn KGn KBn C.Vid e o Output R, G, B Outpu t s
0 Black (Initial value)01Blue
0Green
0
11 Cyan
0Red0
1 Magenta
0 Yellow
1
1
1
Specific ation inva lid
(Halftone display in
superimpose d mode )
White
Rev. 1.0, 02/00, page 844 of 1141
Bit 0Cursor Brightness/Halftone Level Specification Bi t (KLUn, n = 1 to 12): Sets the
cursor brightness/halftone level in row units. Cursor brightness differs for differe nt cursor colors.
This sett i ng has no effec t on digi tal outputs (YCO, YBO, R, G, a nd B).
• Cursor Bri ghtness i n Text Displ ay Mode
Bit 0
KLU Cursor Col or Cursor Bright ness Level
0 0 IRE (Initial value)
1Black 25 I RE
0 25 I RE (Initial value)
1
Blue, green, cyan, red,
yellow, magenta 45 I RE
0 45 I RE (Initial value)
1
White
55 IRE
Note: All brightness levels ar e with r eference to the pedestal level (5IRE). Brightness levels are
reference values.
• Halftone Levels in Superimposed Mode
Bit 0
KLU Description (Ha lftone Levels)
0 50% halftone (Init ial value)
1 30% halftone
Rev. 1.0, 02/00, page 845 of 1141
29.5 Sett i n gs i n Screen Un its
The following i tems can be set in screen units by using ve rtical displa y posi tion regi ste r,
horizontal display posit i on re gi ster, a nd screen c ont rol register.
29.5.1 Display Positions
(1) Vertical Display Start Position
The vertical display start position can be set in single scanning line units using the vertical
position specification bits of the vertical display position register.
In setting display positions, the fol l owing should be noted.
• Settings should be chosen to ensure that the display does not overlap with the vertical retrace
line.
• When t he display protrudes outside the screen, cha racters i n the protruding re gion should be
blank c ha racters (chara cter code H' 000).
The base point for display sta rt positions i s shown in figure 29.10.
Pre-equalizing
period Post-equalizing
period
Vertical synchro-
nization period
Line counter
0123456
Figure 29.10 Base Poi nt for Vertical Display Start P ositions
(2) Vertical Display Interval
The vertical display interval c a n be set in single scanning line units using the line interval
specification bit of the vertical display position register.
• When t he display protrudes outside the screen, cha racters i n the protruding re gion should be
blank c ha racters (chara cter code H' 000).
(3) Horizontal Display Start Position
The horizontal di splay start position can be set i n units equal to double the dot clock cycle using
the horizontal position spec i fication bi t of the horizontal display position registe r.
The base point for the hori zontal displa y sta rt position is the center of the hori z ontal sync signal.
Rev. 1.0, 02/00, page 846 of 1141
Note the following when choosing display position set t ings.
• Settings should be chosen such that the display does not overlap with the color burst.
• When t he display protrudes outside the screen, cha racters i n the protruding re gion should be
blank c ha racters (chara cter code H' 000).
The base point for the hori zontal displa y sta rt position is shown in figure 29.11.
Horizontal display
start position
Set by the display
position specification
register
OSD display
base point
Figure 29.11 Base Poi nt for Horizontal Display Start Position
29. 5. 2 T ur ning the OSD Displa y On and Off
Th e OSD displa y can be turned on and off usi ng the displa y on/of f bit of the sc reen con tro l
register.
29.5.3 Display Method
Display can be switched between text display mode and superimposed mode, and while in text
display mode the display can be switched between interlaced and noninterlaced display, using the
display mode specification bit of the screen control register.
29. 5. 4 B l inki ng Period
A blinking period of either approximately 0.5 sec (32/fV) or approximately 1 sec (64/fV) can be
selected using the blinking period specification bit of the screen control register.
Rev. 1.0, 02/00, page 847 of 1141
29.5.5 Borders
Borders on the peri phery of characters can be set usi ng the border specification bit of t he screen
control regi ster. For an exam ple of borde r di splay, see figure 29.2, Charac t er Configuration
Examples.
The border col or can be set in scree n units using the border c olor specification bit of t he screen
control regi ster. In text display m ode, the border color c a n be selected from either white or black.
In supe rimposed m ode, all borders are black only.
The horizontal size of borde rs is one dot (t he same as one dot i n a cha racter), but for enlarged
characters is two dots.
The vertical size of borders is one line (the same as one line in a character), but for enlarged
characters is two lines.
For an explanation of the scre e n control register, re fer to section 29.5.9, Screen Cont rol Register
(DCNTL).
The re are notes on borders; refer to section 29.8, Notes on OSD Font Creation.
Bordering is recommended with t he SECAM T V format.
29. 5. 6 B a c kg round Color and Bright ne ss
In text display mode , the background color c an be selected from among eight hues, and the
brightness from among four leve l s, usi ng the ba ckground color spe cification bit s and background
brightness select bits of the scre en control regi ster.
29. 5. 7 Cha r a c ter, Cursor, and Backgro und Chrom a Saturat i o n
In text display mode , the chroma saturation of the cha racter, cursor, and background can each be
selected from am ong two levels using the character chroma specification bit, cursor chroma
specification bit, and background chroma specification bit of the screen cont rol register,
respectively.
Rev. 1.0, 02/00, page 848 of 1141
29.5.8 Display P osition Re gisters (HPOS and VPO S)
The HPOS and VPOS inclu de the hori zonta l di splay position register and the vertica l di splay
position register.
(1) Horizontal Display Position Register (HPOS)
01
R/W
2
R/W
34
R/WR/W
57 HP4
0
HP3
0
HP2
0
HP1
0
HP0
0
R/W
HP7
0R/WR/WR/W
HP6
0
HP5
0
6
Bit:
Initial value:
R/W:
The horizontal di splay position register is used to set t he horizont al display start position for
characters. It is an 8-bit read/wri te register. Whe n reset, whe n the m odule is stopped, in sleep
mode, in standby mode, in watch mode, in subactive mode, or in subsleep mode , the horizontal
display position register is initialized to H'00. When the OSD display update timing c ontrol bit
(DT MV) is 1, th e OSD displa y is updat ed to th e ho riz onta l di sp la y posit i o n regi ste r sett ings
synchronously with th e Vsync signal (OSDV).
Bits 7 to 0Horizontal Display Start Positi on Spe cification Bits (HP7 to HP0): Set th e
display start position in the horizontal direction. Setting units are twice the dot clock cycle. Refer
to the base point for the hori zontal displa y sta rt position in figure 29.11.
If the horizont al display start posi tion is Hs (µs), then Hs is given by 2 × tc × (value of HP7 t o
HP0), where tc is the dot clock cycle.
(2) Vertical Display Position Register (VPOS)
89
R/W
10
R/W
1112
——
1315 —
1
VSPC2
0
VSPC1
0
VSPC0
0
VP8
0
—
—
1R/WR/W—
—
1
—
1
14
Bit:
Initial value:
R/W:
01
R/W
2
R/W
34
R/WR/W
57 VP4
0
VP3
0
VP2
0
VP1
0
VP0
0
R/W
VP7
0R/WR/WR/W
VP6
0
VP5
0
6
Bit:
Initial value:
R/W:
The vertical display position re gi ster is a 16-bit read/write re gister used to set the cha racter size,
vertical display start position, and vertical-direction row interval. When reset, when the module is
stopped, in sleep mode, in st a ndby mode, in watch mode, in subact i ve mode , or in subsleep mode,
th e ve rt ical disp la y posit ion regi ste r is init ia li ze d to H'F00 0. When the OSD displa y upda te tim i n g
control bit (DTMV) i s 1, the OSD display i s updated to the verti cal display position regi ster
settings synchronously with t h e Vsync signal (OSDV).
Rev. 1.0, 02/00, page 849 of 1141
Bits 15 to 12Reserved: Cannot be modified and are always read as 1.
Bits 11 to 9Vertical Row Int erv al Spec ifi cat i o n Bit s (VSPC2 to VSPC0): Set the row
interval in the vertical direction. They can be set in single scanning line units.
Bit 11 Bit 10 Bit 9
VSPC2 VSPC1 VSPC0 Description
0 No row interval (Init ial value)01 Row interval: One scanning line
0 Row interval: Two scanning lines
0
11 Row interval: Three scanning lines
0 Row interval: Four scanning lines0
1 Row interval: Five scanning lines
0 Row interval: Six scanning lines
1
1
1 Row interval: Seven scanning lines
Bits 8 to 0Vertical Di splay Start Position Specifi c ation Bits (VP8 to VP0): Set the display
start position in the vertical direction. The vertical display start position can be set in single
scanning line units. The base point of the display start position is the vertical sync signal. Refer to
the base point for the vertical display start position in figure 29.10.
If the vertical displa y start position is Vs (µs) , t hen Vs is give n by Vs = tH × (value of VP8 to
VP0), whe re tH is the horiz ontal sync signal period (µs), corresponding to a single horizontal
scanning line.
Rev. 1.0, 02/00, page 850 of 1141
29. 5. 9 Scr een Co ntro l Regist er (DCNTL )
89
R/W
10
—
1112
R/WR/W
1315 BLKS
0
OSDON
0
—
0
EDGE
0
EDGC
0
R/W
CDSPON
0R/WR/WR/W
DISPM
0
LACEM
0
14
Bit:
Initial value:
R/W
01
R/W
2
R/W
34
R/WR/W
57 BLU1
0
BLU0
0
CAMP
0
KAMP
0
BAMP
0
R/W
BR
0R/WR/WR/W
BG
0
BB
0
6
Bit:
Initial value:
R/W
The DCNTL is a 16-bit read/write register used to switch between superimposed and t ext displa y
modes, se t the background and col or for text display mode in screen unit s, and turn OSD display
on and off.
When reset, when the module is stopped, in sleep mode, in standby mode, in watch mode, in
subactive m ode, or i n subsleep mode, the DCNTL is i nitialized to H'0000.
When the OSD display updat e timin g co ntrol bit (DTMV) is 1, the OSD displ ay is upda te d to the
screen control registe r settings e xcept the set ting in bit 13 (LACEM bit) sync hronously with the
Vsync sign al (OSDV).
Bit 15OSD C. Video Displ a y Enable Bit (CDSPO N) : Turns OSDC C. Video display out p ut on
and off.
Bit 15
CDSPON Description
0 OSD C.Video disp lay is off (In itial value)
1 OSD C.Video display is on
Bit 14Superi m posed/ T ext Displa y Mode Selec t Bit (DISPM ) : Selects superimposed mode or
text display mode.
When selecting a display mode, the dot clock also serves as the AFC circuit reference clock, and
so the AFC circuit reference Hsync signal must be switched. For details, refer t o section 27.3. 6,
Automatic Frequency Controller (AFC).
Bit 14
DISPM Description
0 Superimposed mode is selected ( I nit ial value)
1 Text display mode is selected
Rev. 1.0, 02/00, page 851 of 1141
Bit 13Interlaced/Noninterlaced Display Select Bit (LACEM): Selects interlaced or
noninterlaced text di splay mode . When noninterlaced text display is selected, the internally
generated Hsync and Vsync frequency can be modified. For details, refer to section 27.2.11,
Internal Sync Frequency Re gi ster (INFRQR).
Bit 13
LACEM Description
0 Noninterlaced display is select ed (Init ial value)
1 Interlace d disp la y is selecte d
Bit 12Blinking Period Se lect Bit (BLKS): Se lects th e ch aracter b linking per iod. Th e du ty is
50%. The bli nking peri od differs somewhat depe nding on the TV format selected by the TVM2 bit
of the OSD format re giste r (either a 525-l ine system or a 625-line system).
DFORM DCNTL
Bit 15 Bit 12
TVM2 BLKS Description (Blinking Period)
0 Approx. 0.5 sec (32/fv = 0.53 sec) (Initial value)0
1 Approx. 1.0 sec (64/fv = 1.07 sec)
0 Approx. 0.5 sec (32/fv = 0.64 sec) (I nit ial value)1
1 Approx. 1.0 sec (64/fv = 1.28 sec)
Note: fv is the vert ical sync signal frequency.
Bit 11OSD Displ ay Start Bi t (OSDON) : Starts OSD display. When the OSD display start bit
is 0, the OSD inter n al disp la y circ uit st op s operati o n. In conjunction wit h the OSD C.Video
display enable bit (bit 15), c ha nges ope ration as follows. When acce ssing character data ROM
(OSDROM) fr om th e CPU, thi s bi t sho uld al way s be cleared to 0. If th i s bit is set to 1, acce ss by
the CPU is not guaranteed.
Bit 15 Bit 11
CDSPON OSDON Description
0/1 0 O SD display is stopped ( C.Video output and digital output both off)
(Init ial value)
0 1 OSD display is start e d (d igita l o utp ut only)
1 1 O SD display is started (both C.Video output and digital output
enabled)
Rev. 1.0, 02/00, page 852 of 1141
Bit 10Reserved: Cannot be mod ified an d is always read as 0. When 1 is written to th is b it,
correct ope ration i s not guaranteed.
Bit 9Border Specification Bi t (EDGE): Sets the border for c haracters for the entire screen.
Bit 9
EDGE Description
0 No character border (Init ial value)
1 Character border
Bit 8Border Color Specification Bit (EDGC): Selects the border color. Border col or
specifications for C.Vi de o out put are invalid in supe rimposed m ode.
Border bri ghtness l e vels are 0 IRE for black and 90 IRE for white.
Note: Brightness levels are with reference to the pedestal level (5IRE). Brightness levels are
reference values.
• Border Color in Te xt Displ a y Mode
Bit 8 Border Color
EDGC C.Vid e o Output R, G, B Ou tputs
0 Bla c k Black (Initial value)
1White White
• Border Color in Superim posed Mode
Bit 8 Border Color
EDGC C.Vid e o Output R, G, B Ou tputs
0 Black ( I nitial value)
1
Specification invalid (black)
White
Rev. 1.0, 02/00, page 853 of 1141
Bits 7 to 5Background Color Specification Bits (BR, BG, and BB): U sed to sel e ct the
background color in te xt display mode. Bac kground color specifications for C.Video output are
invalid in superimposed mode.
• Background Colors in Te xt Displ a y Mode
Background Color
Bit 7 Bit 6 Bit 5 C.Video Output
BR BG BB NTSC PAL R, G, B Outputs
0 Black Black Black (I nitial value)0
1π±πBlue
07π/4 ±7π/4 Green
0
113π/2 ±3π/2 Cyan
0π/2 ±π/2 Red013π/4 ±3π/4 Magenta
0Same
phase ±0 Yellow
1
1
1 White White White
• Background Colors in Superimpose d Mode
Bit 7 Bit 6 Bit 5 Background Color
BR BG BB C.Vid e o Output R, G, B Ou tp uts
0 Black ( Initial value)01Blue
0Green
0
11 Cyan
0Red0
1 Magenta
0 Yellow
1
1
1
Specific ation inva lid
White
Rev. 1.0, 02/00, page 854 of 1141
Bits 4 and 3Background Brightness Select Bits (BLU1 and BLU0): Select the background
brightness in text displa y mode. These settings have no e ffect on digit al outputs (YCO, YBO, R,
G, and B).
Bit 4 Bit 3
BUL1 BUL0 Background Brightness
0 10 IRE (Init ial value)0
1 30 IRE
0 50 IRE1
1 70 IRE
Note: Brightness levels are with reference to t he pedestal level (5IRE). Brightness levels are
reference values.
Bit 2Character Chroma Select Bit (CAMP): Selects the character chroma amplitude in text
display mode. This setting has no effect on di gital output s (YCO, YBO, R, G, and B).
Bit 2
CAMP Description
0 Character chroma amplitude: 60 IRE (Initial value)
1 Character chroma amplitude: 80 IRE
Note: Amplitudes are r eference values.
Bit 1Cursor Chrom a Sele ct Bit (KAMP): Selects the c ursor chroma amplitude in text display
mode. Thi s setting ha s no effect on digital output s (YCO, YBO, R, G, and B).
Bit 1
KAMP Description
0 Cursor chroma amplitude: 60 IRE (Initial value)
1 Cursor chroma amplitude: 80 IRE
Note: Amplitudes are r eference values.
Bit 0Background Chrom a Select Bit (B AMP): Selects t he bac kground chroma ampli tude in
text display mode. Thi s setting ha s no effect on digital outputs (YCO, YBO, R, G, and B).
Bit 0
BAMP Description
0 Background chroma am plitude: 60 IRE (Initial value)
1 Background chroma am plitude: 80 IRE
Note: Amplitudes are r eference values.
Rev. 1.0, 02/00, page 855 of 1141
29.6 O th er Set tings
29.6.1 TV Format
The OSD su pports M/NTSC, 4. 43-NT SC, M/PAL, N/PAL, B, G, H/PAL, I/PAL, D, K/PAL, and
SECAM formats. See table 29.3, TV Formats and Display Modes.
29. 6. 2 Displ ay Data RAM Control
Th e OSD displa y data RAM co ns i st s of master RAM and slave RAM. The ma ste r RAM can be
read and writte n by the CPU; the slave RAM is accessed by the OSD.
The data written to master RAM is transferred to slave RAM to switch the OSD display.
The DTMV bit can be used to switch between timing the transfer of data to occur when the
LDREQ bit is set t o 1, or to occur synchronously wi th the Vsync signal after LDREQ is set t o 1.
For d et ai l s, ref er to sec ti o n 29.6.6 , OSD Fo rmat Register (DFOR M).
29. 6. 3 T i m i ng of OSD Displa y Update s Using Register Rewr iti ng
It is possible to switch the timing of OSD display updates to occur simultaneously with register
rewrites, or to oc c ur synchronously with the Vsync signal (OSDV) after a re gi ster rewrite. For
details, r efer to section 29 .6.6 , OSD Format Register ( DFORM).
29.6.4 4fsc/2fsc
For a 4fsc/2fsc signal, either an external clock signal is input, or a crystal oscillator can be
connected. If an e xternal clock signal is input, the signal must be a mplified using a dedicated
amplifier circuit; this is set using the register.
Either 4fsc or 2fsc input can be selected.
If a 2fsc si gnal is input, some colors cannot be displayed. For de t ail s, see table 29.7, OSD Display
Colors for 2fsc Signal Input.
29. 6. 5 OSDV Inter r upt s
Interrupts triggered by t he Vsync si gnal input to the OSD (OSDV interrupts) ca n be ge nerated. In
superimposed mode, int errupts are triggere d by the e xternal Vsync signal, and in text display
mode, they are triggered b y the in ternal Vs ync sign al gen erated in the sync separator.
Rev. 1.0, 02/00, page 856 of 1141
29.6.6 OSD Format Regi ster (DFORM)
89
R/W
10
R/W
1112
R/WR/W
1315 FSCIN
0
FSCEXT
0
—
0
OSDVE
0
OSDVF
0
R/W
TVM2
0R/(W)*R/WR/W
TVM1
0
TMV0
0
14
Bit:
Initial value:
R/W:
01
R/W
2
R/W
34
——
57 —
1
—
1
DTMV
0
LDREQ
0
VACS
0
—
—
1R/(W)*——
—
1
—
1
6
Bit:
Initial value:
R/W:
Note: * Only 0 can be written to clear the flag.
The DFORM is us ed to s et the TV format and con trol display data RAM.
The DFORM is a 16-bit read/write register. When reset, when the module is stopped, i n sleep
mode, in standby mode, in watch mode, in subactive mode, or in subsleep mode , it is initialized to
H'00F8.
Rev. 1.0, 02/00, page 857 of 1141
Bits 15 to 13TV Format Select Bits (TVM2 to 0): Select the T V forma t. The specified clock
signal should always be input.
Bit 15 Bit 14 Bit 13 Bi t 12 Description
TVM2 TVM1 TVM0 FSCI N TV Format 4f s c (MHz) 2f s c (MHz)
0 14.31818 — Initial value0001M/NTSC — 7.15909
0 0 1 0 4.43-NTSC 17.734475
(17.734476) —
1—
8.8672375
(8.867238)
0 1 0 0 M/PAL 14.302446
(14.302444) —
1 — 7.15122298
0110/1 Must not be specified.
014.328225
(14.328224) —100
1
N/PAL
— 7.1641125
1010/1 Must not be specified.
017.734475
(17.734476) —110
1
B, G, H /PAL,
I/PAL, D, K/PAL — 8.8672375
(8.867238)
017.734475
(17.734476) —111
1
B, G,
H/SECAM,
L/ SECAM, D,
K, K1/SECAM — 8.8672375
(8.867238)
Note: The 4fsc and 2fsc frequencies for SECAM do not conf orm to the SECAM TV format
specifications.
Bit 124/2fsc Input Sel ec t Bit (FSCIN) : Selects 4fs c or 2fsc inpu t.
Bit 12
FSCIN Description
0 4fs c input is selected (I nit ial value)
1 2fsc input is selected
Rev. 1.0, 02/00, page 858 of 1141
Bit 114/2fsc Ex ternal Input Selec t Bit (FSCEXT ) : Se lects 4fsc or 2fsc input.
Bit 11
FSCEXT Description
0 4 /2fs c osc illa tor uses a crystal osc illator ( Initial value )
1 4/2fsc uses a dedicat ed amplifier circuit f or external clock signal input
Bit 10Reserved: Always read as 0. When 1 is written to this bit, correct operation is not
guaranteed.
Bit 9OSDV Interr upt Enable Bit (OSDVE) : Enables or disable s OSDV interrupts.
Bit 9
OSDVE Description
0 The OSDV interrupt is disabled (Initial value)
1 The OSDV interrupt is enabled
Bit 8OSDV Interr upt Flag (OSDVF ) : Set when the OSD detect s the Vsync sign al. The timi ng
for setting this flag differs de pending on the OSD display mode. In superimposed mode, it is set
on the external Vsync signal; in text display mode it is set on the internally generated Vsync
signal.
Bit 8
OSDVF Description
0 [Clearing condit ion]
When 0 is written after reading 1 (Init ial value)
1 [Setting condition]
When OSD detects the Vsync signal
Bits 7 to 3Reserved: Always read as 1. When 0 is written to these bits, correct operation is not
guaranteed.
Rev. 1.0, 02/00, page 859 of 1141
Bit 2OSD Displ a y Update Timi ng Control Bit (DTMV): Selects the timing for transfer of
data from master RAM to slave RAM and for OSD display update by register ove rwriting.
Bit 2
DTMV Description
0 After the LDREQ bit is written to 1, data is transferred from master RAM to slave
RAM regardless of the Vsync signal (OSDV). The OSD display is updat ed
simultaneously wit h register* rewriting.
Note: * When transferring dat a using this setting, do not have t he OSD display data
(Init ial value)
1After the LDREQ bit is written to 1, data is transferred from master RAM to slave
RAM synchronously with the Vsync signal (O SDV). After r ewriting t he register, t he
OSD display is updated synchronously with the Vsync signal (OSDV).
Note: The register s and register bits whose settings ar e reflect ed in the OSD display are t he row
registers (CLINE), vert ical display position r egister ( VPOS), hor izontal display position
regist er (HPOS), screen c ontro l register (DCNTL) except bit 13, and the RGBC, YCOC, and
DOBC bit s of the digital output specification r egister (DOUT).
Bit 1Master -Slave RAM Transfer Re que st and State Bi t (LDREQ) : Reque sts tran sfer of
data from master RAM to slave RAM. After this bit is written to 1, a transfer request is issued
with timing selected by the DTMV bit. When read, this bit indicates the state of data transfer from
master RAM to slave RAM.
Note: To abort data transfer after writing this bit to 1, write it to 0. However, once data transfer
begins it cannot be a borted.
• Writing
Bit 1
LDREQ Description
0 Requests abort of dat a transfer from master RAM to slave RAM
1 Requests transfer of data from master RAM to slave RAM. After transfer is
completed, this bit is cleared to 0
• Reading
Bit 1
LDREQ Description
0 Data is not being t r ansferr ed from master RAM to slave RAM ( Initial value)
1 Data is being transferred fr om master RAM to slave RAM, or is being prepared for
transfer. After transfer is completed, this bit is cleared to 0
Rev. 1.0, 02/00, page 860 of 1141
Bit 0Master -Slave RAM Transfer Sta te Bit (VACS): Is set to 1 if the CPU accesses
OSDRAM during tra nsfer of data from master RAM to slave RAM; the access is invalid. This bi t
is not cleared automatically, and so should be cleared by writing 0.
Bit 0
VACS Description
0 The CPU did not access OSDRAM during data transfer (I nitial value)
1 The CPU accessed OSDRAM during data transfer; the access is invalid
29.7 Digital Output
29. 7. 1 R, G, and B Output s
R, G, a nd B outputs consist of display dat a in dot units for characters, background, cursors and
other display elements.
Either of t wo output methods can be selected by the R, G, B digi tal output specification bit:
characters only, or output of display data for all el ements, including characters, borders, cursors,
background, and but tons. Here da ta for borders and buttons is output as white-equivalent (R=1,
G=1, B=1) or as black-equivalent (R= 0, G=0, B=0) dat a.
The digital output blink control bit is used to select blinking for R, G, and B. The R, G, and B
outputs are mul tiplexed wit h port 8 inputs/out puts. For det ails on pin functi on selection, refe r to
section 10.9, Port 8.
Display data RAM and the scre en control regi ster settings are output a s displa y data output for
characters, cursors and background in superimpose d mode; this differs from the output data from
the CVout pin.
Examples of R, G, B out put are shown in fi gures 29. 12 and 29.13.
Rev. 1.0, 02/00, page 861 of 1141
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0
RAM DOUT
BLNK DOBC RGBC
0R
G
B
(Low)
(Low)
(Low)
(Low)
(Low)
R
G
B
R
G
B
R
G
B
R
(Blinking)
G
(Blinking)
B
(Blinking)
R
(Blinking)
G
(Blinking)
B
(Blinking)
1
0
0/1
1
0
1
0
11
1
11
Background
Output Example 1
Character color: Yellow (CR = 1, CG = 1, CB = 0)
Cursor color: Cyan (KR = 0, KG = 1, KB = 1)
Background color: Green (BR = 0, BG = 1, BB = 0)
Border: None (EDGE = 0)
Button: Displayed (pattern 1)
Button
Cursor
Border
Character
Border
Cursor
Button
Background
Figure 29.12 RGB Output Example (1)
Rev. 1.0, 02/00, page 862 of 1141
0
RAM DOUT
BLNK DOBC RGBC
0R
G
B
(Low)
(Low)
(Low)
(Low)
(Low)
(Low)
(High)
(Low)
(Low)
(Low)
(Low)
(Low)
R
G
B
R
G
B
R
G
B
R
(Blinking)
G
(Blinking)
B
(Blinking)
R
(Blinking)
G
(Blinking)
B
(Blinking)
1
0
0/1
1
0
1
0
11
1
11
Output Example 2
Character color: Yellow (CR = 1, CG = 1, CB = 0)
Cursor color: None (HT/CR = 0)
Background color: Green (BR = 0, BG = 1, BB = 0)
Border: Black (EDGE = 1, EDGC = 0)
Button: None
Button
Cursor
Border
Character
Border
Cursor
Button
Background
Background
Figure 29.13 RGB Output Example (2)
Rev. 1.0, 02/00, page 863 of 1141
29. 7. 2 YCO and YBO Output s
YCO output consists of character and borde r data in dot units. E ither of two YCO output methods
can be selected by the YCO digital output specification bit: output of characters only, or
combined outpu t of chara cter and border data. The digi tal outpu t blink cont rol bit can be used to
select blinking for YCO output. The YCO data output specificat i on bi t must be reset to 0 when
bordering is not performed, and must be set to 1 when borderi ng is pe rformed. YBO output is dat a
for the character displa y area. 32 characters’ worth of data is output starting from the start posit ion
set by the horizontal-direction start position specification bit of the display position register. Here
blank-character intervals have no character display, and so there is no output. In addition, YBO
output cannot be made to blink.
The YCO and YBO outputs are m ultiplexed with port 8 inputs/outputs. For details on pin function
selection, refer to section 10.9, Port 8.
An example of YCO output and that of YBO output appear in figure s 29.14 and 29. 15,
respectively.
0
RAM DOUT
BLNK DOBC YCOBC
0
1
0
1
0
1
YCO
YCO
YCO
YCO
YCO
(Blinking)
YCO
(Blinking)
(Low)
(Low)
0/1
0
1
1
Output Example
Character color: Yellow (CR = 1, CG = 1, CB = 0)
Cursor color: None (HT/CR = 0)
Background color: Green (BR = 0, BG = 1, BB = 0)
Border: Black (EDGE = 1, EDGC = 0)
Button: None
Button
Cursor
Border
Character
Border
Cursor
Button
Background
Background
Figure 29.14 YCO Output Example
Rev. 1.0, 02/00, page 864 of 1141
Horizontal display position Display block
Character display
position
Blank character
Row 1
YBO
1234567 29 32....................................................................... .....
Figure 29.15 YBO Output Example
29.7.3 Digital Output Specification Register (DOUT)
01
—
2
R/W
34
R/WR/W
57 DOBC
0
DSEL
0
CRSEL
0
—
1
—
0
—
—
0—R/WR/W
RGBC
0
YCOC
0
6
Bit:
Initial value:
R/W:
The DOUT is used to choose sett ings for digital output.
Th e DOUT is an 8-bit rea d / write re gist er. When reset, when the modul e i s stop ped, in slee p mode,
in standby mode, in watch mode, in subactive mode, or in subsleep mode, it is initialized to H'02.
When the OSD display updat e timin g co ntrol bit i s 1, the OSD displa y is updated to the RGBC,
YCOC and DOBC bit settings sync hronously with the Vsync signal (OSDV).
The R, G, B, YCO, and YBO output s are mul tiplexed wit h port 8 input s/outputs. For details on pin
function se lection, refe r to section 10.9, Port 8.
Bit 7Reserved: Always read as 0. When 1 is written to this bit, correct operation is not
guaranteed.
Bit 6R, G, B Digital Output Specification Bit (RGBC): Specifies the R, G, B digital out put
format.
Bit 6
RGBC Description
0 Cha racte r out put is specif ie d (Initial value)
1 Combined char acter, border, cursor, background, and button out put is specified
Rev. 1.0, 02/00, page 865 of 1141
Bit 5YCO Digita l Output Spec i ficatio n Bit (YCOC): Specifies the YCO digital output
format. T his bit m ust be reset to 0 when bordering is not performed, and must be set to 1 when
bordering is performe d.
Bit 5
YCOC Description
0 Cha racte r out put is specif ie d (Initial value)
1 Combined char acter and border output is specified
Bit 4Digit a l Output Bli nk Co ntrol Bit (DOB C) : Turns blinking on and off for dig it al outputs
(YCO, R, G, and B). Digital output YBO c annot be made to bli nk.
OSDRAM DOUT
Bit 15 Bit 4
BLNK DOBC Description
0 Does not blink (Initial value)01 Does not blink
0 Does not blink11 Blinks
Bit 3R, G, B, YCO, YBO Pi n Func ti on Sel ec t Bi t (DSE L): Selects the R, G, B, YCO, and
YBO pins to function either as digital output pins, or as data slicer internal monitor signal pins.
Bit 3
DSEL Description
0 R, G, B, YCO, YBO output function is select ed (I nit ial value)
1 Data slicer monitor out put function is selected
R pin = Signal selected by bit 2 (CRSEL)
G pin = Slice data signal analog-compared with Cvin2
B pin = Sampling clock generat ed within data slicer
YCO pin = External Hsync signal (AFCH) sy nchronized within t he LSI
YBO pin = External Vsync signal (AFCV) synchronized within the LSI
Rev. 1.0, 02/00, page 866 of 1141
Bit 2Monitor Signal Switching Bit (CRSEL): Selects whether a clock run-i n detection
window signal or a start bit detection window signal is output. Thi s bit setting is valid when DSEL
is 1, so that pins are used as data slicer internal monitor signal outputs.
Bit 2
CRSEL Description
0 Clock run-in detection window signal output is select ed (I nitial value)
1 Start bit detection window signal output is selected
For informa tion on slice data and the sampl i ng clock, refer to section 28.2.2, Slice Line Setting
Registers 1 to 4. For details on the clock run-i n de tection window signal, start bit de tection
window signal, external Hsync signal (AFCH), and exte rnal Vsync signal (AFCV), refer t o section
27, Syn c Se parat o r for OSD and Data Slicer.
Bit 1Reserved: Cannot be modified and is always read as 1.
Bit 0Reserved: Always read as 0. When 1 is written to this bit, correct operation is not
guaranteed.
29.7.4 Module Stop Control Register (MTSTPCR)
7
1
R/W
MSTP
15 MSTP
14 MSTP
13 MSTP
12 MSTP
11 MSTP
10 MSTP
9MSTP
8MSTP
7MSTP
6MSTP
5MSTP
4MSTP
3MSTP
2MSTP
1MSTP
0
6
1
R/W
54
1
R/W
MSTPCRH MSTPCRL
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Bit:
Initial value:
R/W:
The MSTPCR consists of two 8-bit read/wri te regist e rs for c ontrolling the module stop mode.
Writing 0 to the MSTP0 bit starts the OSD module; setting the MSTP0 bit to 1 stops the OSD
module at the end of a bus cycle and the module stop mode is entered. At this time, the CVout and
digital outputs also stop. Before writing 0 to this bit, set the MSTP9 bit to 0, to operate the sync
separator.
The registe rs cannot be read or written to in module stop mode. Howe ve r, cha racter dat a ROM
(OSDROM) and display data RAM (OSDRAM) can be read and writ ten. For details, refer to
section 4.5, Module Stop Mode .
Rev. 1.0, 02/00, page 867 of 1141
Bit 0Module Stop (MST P0): Spec i fies the module stop mode for the OSD module.
Bit 0
MSTP0 Description
0 Clears the module stop mode for the OSD modul e
1 Specifies the module stop mode for the OSD module (Initial value)
Rev. 1.0, 02/00, page 868 of 1141
29.8 Not es on OSD Font Creat ion
29.8.1 Note 1 on Font Creati on (Font Wi dth)
In OSD disp la y, ver ti ca l a nd dia g onal li nes in fon t s that are one dot wide may ap pear to be na rrow
due to a shift of 0.5H. Display fonts should be created with liberal thicknesses.
29.8.2 Note 2 on Font Creati on (Border s)
Borders exte nd beyond the character displ a y fra me in the X-direction, but no borders e xtend
beyond the display frame in the Y-direction. More over, when borders are to the right or left of
blank c ha racters (H'000), borders extend beyond the displ ay frame, but for the first and the 32nd
characters in a displayed row (16th character whe n the character siz e is enl arged to double he ight
× double width), no borders ext end beyond t he display frame.
Examples of borders which ext e nd be yond the di splay frame appear in figures 29.16 through
figure 29.18.
X-direction
Y-direction
12 dots
Characters
Borders
18 dots
Figure 29.16 Border Extending beyond the Display Fr ame (Example)
Rev. 1.0, 02/00, page 869 of 1141
12 dots
Characters
Borders
18 dots
Blank display
Figure 29.17 Border Neighboring a Blank Char ac ter (Example)
12 dots
(a) 1st character (b) 32nd character
12 dots
Characters
Borders
Figure 29.18 Examples of Char acters at the Star ti ng and Ending Positions in a Row
Rev. 1.0, 02/00, page 870 of 1141
29.8.3 Note 3 on Font Creati on (Blinking)
Blinking involves intermittent display within a specified display frame only. When blinking is
necessary, font data should not be set t o the fi rst or t welfth dot s in the X-direction.
Figure 29. 19 shows an exa m ple of blinking for characters with borders e xtending beyond the
display frame.
12 dots
X-direction
Y-direction
12 dots
18 dots
Characters
Borders
Figure 29.19 Example of Blinking wi th Borde rs Extending beyond the Display Frame
Rev. 1.0, 02/00, page 871 of 1141
29.8.4 Note 4 on Font Creati on (Buttons)
Buttons replace the outermost perimeter of the character display area with a button pattern. It
should be remembered that the button pattern display takes priori ty over display of the font and
border, if any.
Figure 29. 20 shows an exa m ple of button pattern display that take s priority over font a nd border.
12 dots
Button pattern: White
12 dots
18 dots
Characters
Borders
Button pattern: White
Button pattern: Black
Button pattern: Black
Figure 29.20 Example of Button Pattern Display Taking Pr iority ove r Font and Bor der
Rev. 1.0, 02/00, page 872 of 1141
29.9 OSD Oscillator, AFC, and Dot Clock
In order t o use t he OSD, sync signals a nd a 4/2fsc clock signal are required.
29.9.1 Sync Signals
The sync signal for text displ ay mod e is a s igna l created from a 4/2fsc clock or an AFC refe ren ce
clock. In superimposed mode, sync signals may be selected from one of the following thre e types.
1. Horizontal/vertical sync signals separated by the sync separator from the composite video
signal (Cvi n2)
2. Horizontal/vertical sync signals separated by the sync separator from the composite sync signal
(Csync)
3. Hsync and Vsync signals input separately
For det ai l s, ref er to secti o n 27, Sync Separat o r for OSD and Data Slice r.
29.9.2 AFC Circuit
The AFC circuit averages the “fluctuation” in the horizontal sync signal (Hsync) during normal
VCR playba ck, r edu ci n g OSD di spl a y jitt e r. In addi t ion , the AFC ci rcu it gene r at e s the dot clo ck.
Be sure that an external circuit is connected. For details, refer to section 27.3.6, Automatic
Frequency Controller (AFC).
29.9.3 Dot Cloc k
The dot c l ock is a clock used for X-direction (horizontal direction) OSD display; it is
synchronized with the hori zontal sync signal generated by the AFC c ircuit. T he dot c lock
frequency is 576 or 448 times the horizontal sync signal frequency (576 × fh or 448 × fh). The size
of one dot in the horizontal direction of the OSD display appeari ng on the screen is the equivalent
of one dot clock cycle. Accordingly, modifying the FRQSEL bit in the sync separator to change
the horizontal sync signal frequency can adjust the dot size. The dot clock cycle is the same in
superimposed mode a nd text display mode; it is also the same for both interlaced and
noninterlaced displ a ys. It cha nges som ewhat depe nding on the TV format. The relation between
TV format and dot clock cycle is shown in table 29.6.
Rev. 1.0, 02/00, page 873 of 1141
Table 29. 6 Dot Cloc k Cycle
Dot Clock Cycle
TV Format Refere nce Cl ock:
576 × fh Ref er ence Clock:
448 × fh
M/NTSC, 4.43-NTSC, M/PA L, N/PAL 110 ns (9.0 6 MHz ) 142 ns (7.06 MHz)
B, G, H/PAL, I/ PAL, D, K/PAL, SECAM 111 ns (9. 00 MHz) 143 ns (7.00 M Hz)
29.9.4 4/2fsc
1. 4/2fsc Oscillator
The 4/2fsc oscillator generates color signals for text display mode, and also generates the
internal sync signal. A crystal oscillator can be c onnected, or an external cl oc k can be input.
The 4/2fsc freque ncy should be appropria te for t he TV forma t. If an inappropriate frequency is
use d, o r if no 4/2fs c sig nal i s inp ut, OSD ope ration is not gua ra ntee d .
Circuit constants should be chosen such that frequency deviation, including temperature
effects, is within ±30 ppm .
An example of connection of a crystal oscillator appears in figure 29.21; an example of input
of an e xternal clock is shown in figure 29.22.
Power-down
mode controller
4/2fsc in
Rf Crystal
C2
C1
Note: Rf = 1 MΩ typ.
Crystal should be at a frequency appropriate for the TV format.
C1, C2 should be specified such that frequency deviation, including temperature effects, is less than
±30 ppm.
Figure 29.21 Example of Connection of a 4/2fsc Crystal Oscillator
Rev. 1.0, 02/00, page 874 of 1141
Power-down
mode controller External clock
Duty: 47 to 53%
4/2fsc in
CR
(OPEN)
Note: C = 1000 pF typ
When the external clock amplitude is 1 Vp-p or larger, connect a resistor in series with capacitor C.
External clock select
Figure 29.22 Exampl e of Input of a 4/2fsc External Clock
2. For i nformation on OSD display c ol ors for a 2fsc signal input, refer to table 29.7. In NTSC
format, some colors cannot be displayed. In PAL forma t, because alt ernating display is used,
color muddiness, flickering and othe r problems may arise.
Tabl e 29. 7 OSD Di splay Color s for 2fsc Signal Input
Character, Cursor,
and Background
Color Settings NTSC PAL*RGB
Digital Output
Yellow ( Same phase) Yello w (Same phase) Yellow (3π/2, –π/2) Yellow
Cyan (3π/2) Cyan (3π/2) Cyan (π, 0) Cyan
Green (7π/4) Cannot be specif ied G r een (–π/2, 0) Gree n
Magenta (3π/4) Cannot be specified Magenta ( +π/2, –π) Magenta
Red (π/2) Red (π/2) Red ( +π/2, –π/2) Red
Blue (π) Blue (π) Blue (π/2, –3 π/2) Blue
White White White White
Black Black Black Black
Note: *The PAL color burst phase angle is ±π/4 rad for 4fsc input, but is 0 rad or –π/2 rad for 2fsc,
so that colors may differ fr om the color sett ings.
Rev. 1.0, 02/00, page 875 of 1141
29.10 OSD Operat ion in CPU Operation Modes
Ta ble 29. 8 shows t he OSD CVout pin statu s for diffe rent CPU operati ng modes.
During a t ransition to power-down mode, registers are initialized, and so regi ster settings must be
restored on return t o active m ode.
Table 29.8 OSD Operation for Different CPU Operating Modes
Operating Mode Module Stop Bit DISPM Bit CVout Pin
Reset 1 0 No out put
0Chroma-through and
OSD d isplay
Active 0
1 Text display
Module stop 1 0 No output
Sleep, standby , watch ,
subactive, or subsleep Retained 0 No output
Rev. 1.0, 02/00, page 876 of 1141
29.11 Character Dat a ROM (OSDROM) Access by CPU
The chara cter data ROM can be accessed by the CPU a s part of user ROM. Before ac cessing the
characte r data R OM by the CPU, cle ar the OSDON bit in the scree n co ntrol reg i ste r to 0 to stop
OSD disp la y, the n set the OSROME bit in the serial timer regist er to 1. The charac ter data ROM
can be accessed even in the module stop mode.
If the OSROME bit is set to 1 during OSD display, the cha racter data ROM cannot be a cce ssed
correctly by CPU.
For details on OSROME bit setting, refer to section 29.5.9, Screen Control Register (DCNTL).
29.11.1 Serial Timer Control Register (STCR)
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
—OSROMEFLSHE—IICX0IICX1—
—R/WR/W—R/WR/W— —
—
0
Bit :
Initial value :
R/W :
Bit 2OSD ROM Enable (OSROME): Co ntr ols the OSD chara cter data ROM (OSDROM)
acc e ss. When this bit i s set to 1, the OSDROM can be accesse d by the CPU, and whe n this bit i s
cl ea red to 0, the OSDROM can n ot be accesse d by the CPU but acce sse d by the OSD module .
Bef o re writi ng to or erasin g the OSDROM in the F-ZTAT ve rsion, be sure to set this bit to 1.
Not e : Du ring OSD di splay, the OSDROM cann ot be accessed by the CPU. Bef ore acce ssing the
OSDROM by the C PU, be sure to clear the OSDON bit in the scree n cont rol re gist e r to 0
then set the OSROME bit to 1. If the OSROME bit is set to 1 during OSD display , the
character data ROM cannot be accessed correctly by CPU.
Bit 2
OSROME Description
0 OSDROM is accessed by the OSD ( I nitial value)
1 OSDROM is accessed by the CPU
Rev. 1.0, 02/00, page 877 of 1141
Section 30 Electrical Ch aracteristics
30.1 Absolute Maximum Ratings
Table 30.1 lists the absolute maximum ratings.
Tabl e 3 0.1 Absolute Ma xim um Rati ng s
Item Symbol Value Unit
Power supply voltage Vcc −0.3 to +7.0 V
Input voltage (port s other than port 0) Vin −0.3 t o V c c+0.3 V
Input voltage (port 0) Vin −0.3 to A Vcc+ 0.3 V
A/D converter power supply voltage AVcc −0.3 to +7.0 V
A/D c onverter input vo ltage AVin −0.3 t o A Vcc+0.3 V
Servo power supply voltage SVcc −0.3 to +7.0 V
Servo am plifier input voltage Vin −0.3 t o SV cc + 0.3 V
OSD power su pply v o ltag e O Vc c −0.3 to +7.0 V
Operating temperature Topr −20 to +75 °C
Operating temperature (At Flash memory
program/erase) Topr 0 t o +75 °C
Storage temperature Tstr −55 to +125 °C
Notes: 1. Permanen t damage may occur to the chip if absolu te maximum ra tings are exceeded .
Normal operat ion should be under the condit ions specified in Electrical Characteristics.
Exceeding these values can result in incor r ect operation and reduced reliabilit y.
2. All voltages are relative to Vss = SVss = OVss = AVss = 0.0 V.
Rev. 1.0, 02/00, page 878 of 1141
30.2 Electrical Characteristics of HD6432199, HD6432198, HD6432197,
and HD6432196
30.2.1 DC Chara cteristi cs of HD6432199, HD6432198, HD6432197, and HD6432196
Table 30. 2 DC Char acteristics of HD6432199, HD6432198, HD6432197, and H D6432196
(Conditions: Vcc = AVcc = 4.0 V t o 5.5 V*1, Vss = 0.0 V, Ta = – 2 0 to + 75°C unless otherwise
specified.)
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
M D0 Vcc= 2.5 V to
5.5V 0.9 Vcc Vcc+0.3
0.8 Vcc Vcc+0.3
5(6
, FWE, IC, IRQ0
to IRQ5 Vcc= 2.5 V to
5.5V 0.9 Vcc Vcc+0.3
SCK1, SI1, FTIA,
FTIB, FTIC, FTID,
TRIG, TM BI,
$'75*
0.8 Vcc Vcc+0.3
Vcc–0.5 Vcc+0.3OSC1
Vcc=2.5 V to
5.5V Vcc–0.3 Vcc+0.3
0.7 Vcc Vcc+0.3P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P60 to P67,
P70 to P77,
P80 to P87
Vcc=2.5 V to
5.5V 0.8 Vcc Vcc+0.3
Input hi gh
voltage VIH
Csyn c 0.7 V cc Vcc+0.3
V
Rev. 1.0, 02/00, page 879 of 1141
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
M D0 Vcc=2.5 V to
5.5 V –0.3 0.1 Vcc
−0.3 0.2 Vcc
5(6
, FWE, IC,
IRQ0 to IRQ5 Vcc= 2.5 V to
5.5 V −0.3 0.1 Vcc
SCK1, SI1, FTIA, FTIB,
FTIC, FTID, TRIG,
TMBI,
$'75*
−0.3 0.2 Vcc
−0.3 0.5
OSC1
Vcc=2.5 V to
5.5 V −0.3 0.3
−0.3 0.3 Vcc
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P60 to P67,
P70 to P77,
P80 to P87
Vcc=2.5 V to
5.5 V −0.3 0.2 Vcc
Input low
voltage VIL
Csync −0.3 0.2 Vcc
V
Rev. 1.0, 02/00, page 880 of 1141
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
−IOH=1.0mA Vcc–1.0  V
−IOH=0.5mA Vcc–
0.5 VRefer-
ence
value
Output
high
voltage
VOH SO1, SCK1, PWM1,
PWM2, PWM3,
PWM4, PWM14,
BUZZ, TMO, TMOW,
FTOA, FTOB, PPG0 to
PPG7,
RP0 to RP7,
RP8 to RPB,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P60 to P67,
P70 to P77,
P80 to P87,
SV1, SV2, R, G, B,
YCO, YBO
−IOH=0.1mA
Vcc=2.5V to
5.5V
Vcc–0.5  V
IOL=1.6mA 
0.6 VSO1, SCK1, PWM1,
PWM2, PWM3,
PWM4, PWM14,
BUZZ, TMO, TMOW,
FTOA, FTOB, PPG0 to
PPG7,
RP0 to RP7,
RP8 to RPB,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P70 to P77,
P80 to P87, SV1, SV2,
R, G, B, YCO, YBO
IOL=0.4mA
Vcc=2.5 V to
5.5V

0.4 V
IOL=20mA 
1.5 V
IOL=1.6mA 
0.6 V
Output
low
voltage
VOL
P60 to P67,
IOL=0.4mA
Vcc=2.5 V to
5.5V

0.4 V
Rev. 1.0, 02/00, page 881 of 1141
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
MD0, FWE Vin=0.5 to
Vcc–0.5V 
1.0
5(6
,
,54
to
,54
,
,&
Vin=0.5 to
Vcc–0.5V 1.0
SCK1, SI1, SDA0,
SCL0, SDA1, SCL1,
FTIA, FTIB, FTIC, FTID,
TRIG, TM BI,
$'75*
Vin=0.5 to
Vcc–0.5V 1.0
OSC1 Vin=0.5 to
Vcc−0.5V 1.0
Input
/output
leakage
current
IIL
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P60 to P67,
P70 to P77,
P80 to P87,
Vin=0.5 to
Vcc–0.5V 1.0
µA
P00 to P07,
AN8 to ANB Vin=0.5 to
AVcc–0.5V 1.0
Pull-up
MOS
current
−Ip P10 to P17,
P20 to P27,
P30 to P37
Vcc=5.0V,
Vin=0V 50 300 µA*2
Input
capacity Cin All input pins except
power supply pins
P23, P24, P25, and
P26, and analog pins
fin=1 MHz ,
Vin=0V,
Ta=25°C
15 pF
P23, P24, P25, P26 fin =1 MH z ,
Vin=0V,
Ta=25°C
20 pF
Rev. 1.0, 02/00, page 882 of 1141
Values
Item Symbol Applicable
Pins Test
Conditions Min Typ Max Unit Notes
Vcc=5V,
fOSC=10 MHz ,
High-speed
mode
TBD mA *3
Active
mode
current
dissipa-
tion (CPU
operating)
IOPE Vcc
Vcc=5V,
fOSC=10 MHz ,
Medium-speed
mode (1/64)
TBD mA Reference value
Active
mode
current
dissipa-
tion
(reset)
IRES Vcc Vcc=5V,
fOSC=10 MHz —TBD mA *3
Sleep
mode
current
dissipa-
tion
ISLEEP Vcc Vcc=5V,
fOSC=10 MHz
High-speed
mode
TBD mA *3
Vcc=2.5V,
32kHz
With crystal
oscillator
(φ su b=φw/2)
TBD *3
Subactive
mode
current
dissipa-
tion
ISUB Vcc
Vcc=2.5V,
32kHz
With crystal
oscillator
(φ su b=φw/8)
TBD
µA
Reference value*3
Vcc=2.5V,
32kHz
With crystal
oscillator
(φ su b=φw/2)
TBD *3
Subsleep
mode
current
dissipa-
tion
ISUBSLP Vcc
Vcc=2.5V,
32kHz
With crystal
oscillator
(φ su b=φw/8)
TBD
µA
Reference value*3
Rev. 1.0, 02/00, page 883 of 1141
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
Vcc=2.5V,
32kHz
With crystal
oscillator

TBD µA*3
Watch
mode
current
dissipa-
tion
IWATCH Vcc
Vcc=5.0V,
32kHz
With crystal
oscillator
TBD µ
AReference
value*3
Standby
mode
current
dissipa-
tion
ISTBY Vcc X1=V
CL
, 32k Hz
Without crystal
oscillator

5µA*3
RAM data
retaining
voltage in
standby
mode
VSTBY 2.0 V
Notes: 1. Do not open the AVcc and Avss pin even when the A/D converter is not in use.
2. Cur rent value when th e releva nt b it of the pull-up MOS selec t r egister (PUR1 to PUR3)
is set to 1.
3. The current on t he pull-up MOS or the output buffer excluded.
Tabl e 30. 3 Pi n Status a t Curre nt Dissi pa t ion Mea sure ment
Mode
5(6
5(6
pin Internal State Pin Oscillator Pin
Active mode
High-speed , medium -
speed
Vcc Operating Vcc
Sleep mode
High-speed , medium -
speed
Vcc O n ly CPU and
servo circuit s
halted
Vcc
Reset Vss Reset Vcc
Standby m ode Vcc All circuits halted Vcc
Main clock:
Cry sta l o scillator
Sub clock:
X1 pin = VCL
Subactive mode Vcc O nly CPU and
timer A operating Vcc
Subsleep mode Vcc Only timer A
operating Vcc
Watch mode Vcc Only ti mer A
operating Vcc
Main clock:
Cry sta l o scillator
Sub clock:
Cry sta l o scillator
Rev. 1.0, 02/00, page 884 of 1141
Table 30.4 Bus Drive Chara cterist ics of HD6432199, HD6432198, HD6432197, and
HD6432196
(Conditions: Vc c = AVcc = 4.0 V t o 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C)
Appl ic a ble pin: SCL0, SCL1, SDA0, SDA1
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
VT−0.3Vcc  V
VT+
0.7Vcc V
Schmitt
trigger
input VT+
–VT−
SCL0, SDA0,
SCL1, SDA1
0.05Vcc  V
Input hi gh
level
voltage
VIH SCL0, SDA0,
SCL1, SDA1 0.7Vcc Vcc+0.5 V
Input low
level
voltage
VIL SCL0, SDA0,
SCL1, SDA1 −0.5 0.3Vcc V
IOL=8mA 
0.5
Output
low lev e l
voltage
VOL SCL0, SDA0,
SCL1, SDA1 IOL=3mA 
0.4
V
SCL and
SDA
output fall
time
tof SCL0, SDA0,
SCL1, SDA1 20+
0.1Cb 250 ns
Rev. 1.0, 02/00, page 885 of 1141
30.2.2 All owable Output Cur rents of HD6432199, HD6432198, H D6432197, and
HD6432196
The specifications for the digital pins are shown below.
Table 30. 5 Allowable Output Currents of HD6432199, HD6432198, HD6432197, and
HD6432196
(Conditions: Vcc = 2.5 V to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C)
Item Symbol Value Unit Notes
Allow able input current (to chip) IO2mA1
Allow able input current (to chip) IO22 mA 2
Allow able input current (to chip) IO10 mA 3
Allowable output current (from chip) −IO2mA4
Total allowable input cur r ent (to chip) ΣIO80 mA 5
Total allowable output cur r ent (from chip) −ΣIO50 mA 6
Notes: 1. The allowable input current is t he maximum value of the current flowing from each I/O
pin to VSS (exc ept for port 6, SCL0, SDA0, SCL1 and SDA1).
2. The allowable input current is the maximum value of the current flowing f r om each I/O
pin to VSS. This applies to port 6.
3. The allowable input current is the maximum value of the current flowing f r om each I/O
pin to VSS. This applies to SCL0, SDA0, SCL1 and SDA1.
4. The allowable out put cur r ent is t he maximum value of the current flowing f rom VCC to
each I/O pin.
5. The total allowable input current is the sum of the curr ents flowing from all I/O pins to
VSS simultaneously.
6. The total allowable out put current is the sum of the cur r ents flowing from VCC to all I/O
pins.
Rev. 1.0, 02/00, page 886 of 1141
30.2.3 AC Chara cte ristics of HD6432199, HD64321 98, HD6432197, and HD6432196
Table 30. 6 AC Char acteristics of HD6432199, HD6432198, HD6432197, and H D6432196
− Preliminary −
(Conditions: Vc c = AVcc = 4.0 V t o 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C unless otherwise
specified.)
Values
Item Symbol Applicable
Pins Test
Conditions Min Typ Max Unit Notes
Clock oscillation
frequency fOSC OSC1, OSC2 8 10 MHz
Cl ock cycle time tcyc OSC1 , OSC2 100 125 ns Figure 30.1
Subclock
oscillation
frequency
fXX1, X2 Vcc = 2.5 V to
5.5 V 32.768 kHz
Subclock cycle
time tsubcyc X1, X2 Vcc = 2.5 V to
5.5 V 30.518 µ
s Figure 30.2
OSC1, OSC2 Crystal oscillator  10 ms
Oscillation
st abi liz a tion time trc
X1, X2 32kHz crystal
oscillator  2s
External clock high
width tCPH OSC1 40 
ns
External clock low
width tCPL OSC1 40 
ns
Ext ernal clo ck rise
time tCPr OSC1  10 ns
Ext ernal clo ck fall
time tCPf OSC1  10 ns
Figure 30.1
External clock
st abi liz a tion de lay
time
tDEXT OSC1 500 µ
s Figure 30.3
Subclock input low
level pulse width tEXCLL X1 Vcc = 2.5 V to
5.5 V 15.26 µ
s
Subclock input
high lev el pulse
width
tEXCLH X1 Vcc = 2.5 V to
5.5 V 15.26 µ
s
Subclock input rise
time tEXCLr X1 Vcc = 2.5 V to
5.5 V  10 ns
Subclock input fall
time tECXLf X1 Vcc = 2.5 V to
5.5 V  10 ns
Figure 30.2
Rev. 1.0, 02/00, page 887 of 1141
Values
Item Symbol Applicable
Pins Test
Conditions Min Typ Max Unit Figure
5(6
pin low level
width tREL
5(6
Vcc = 2.5 V to
5.5 V 20 
tcyc Figure
30.4
Inp ut pi n hi gh lev el
width tIH
,54
to
,54
,
,&
,
$'75*
,
TMBI, FTIA,
FTIB, FTIC,
FTID,
RPTRIG
Vcc = 2.5 V to
5.5 V 2
tcyc
tsubcyc
Input pi n low lev e l
width tIL
,54
to
,54
,
,&
,
$'75*
,
TMBI, FTIA,
FTIB, FTIC,
FTID,
RPTRIG
Vcc = 2.5 V to
5.5 V 2
tcyc
tsubcyc
Figure
30.5
t
cyc
t
CPH
V
IL
V
IH
OSC1
t
CPL
t
CPf
t
CPr
Fi g ure 30.1 System Clock Timing
t
EXCLf
t
subcyc
t
EXCLH
t
EXCLL
t
EXCLr
V
IL
V
IH
X1 Vcc × 0.5
Fi g ure 30.2 Subclock Input Timing
Rev. 1.0, 02/00, page 888 of 1141
Vcc
OSC1
t
DEXT
*
φ (Internal)
4.0V
The t
DEXT
includes the pin Low level width 20 t
cyc
.
Note:
Figure 30.3 External Clock Stabilization De l ay Ti ming
V
IL
t
REL
Fi g ure 30.4 Rese t Input Timing
t
IL
t
IH
V
IH
to ,
, ,
TMBI, FTIA,
FTIB, FTIC,
FTID, RPTRIG
V
IL
Fi g ure 30.5 Input Timing
Rev. 1.0, 02/00, page 889 of 1141
30.2.4 Serial Interface Timing of HD6432199, HD6432198, HD6432197, and HD6432196
Table 30.7 Serial Interface Timing of HD6432199, HD6432198, HD6432197, and
HD6432196 − Preliminary −
(Conditions: Vc c = AVcc = 4.0 V t o 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C unless otherwise
specified.)
Values
Item Symbol Applicable
Pins Test
Conditions Min Typ Max Unit Figure
Asynchroniza-
tion 4
Input clock cycle tscyc SCK1
Clock
synchronization 6
tcyc
Input clock pulse
width tSCKW SCK1 0.4 0.6 tscyc
Input clock rise time tSCKr SCK1  1.5 tcyc
Input clock fall time tSCKf SCK1  1.5 tcyc
Figure
30.6
Transmit data delay
time (clock sync) tTXD SO1  100 ns
Recei v e data setup
time (clock sync) tRXS SI1 100 
ns
Recei v e data hold
time (clock sync) tRXH SI1 100 
ns
Figure
30.7
tSCKf
tSCKr
VIL or VOL
VIH or VOH
SCK1
tSCKW tscyc
Fi g ure 30.6 SCK1 Clock Timing
Rev. 1.0, 02/00, page 890 of 1141
V
IL
V
IH
t
TXD
SCK1
SO1
SI1
t
RXS
t
RXH
V
OH
V
OL
Figure 30.7 SCI I/O Ti mi ng/Cloc k Synchronization Mode
LSI output pin
Timing reference level
V
OH
: 2.0 V
V
OL
: 0.8 V
30 pF 12 kΩ
2.4 kΩ
Vcc
Figure 30.8 Output Load Cond itions
Rev. 1.0, 02/00, page 891 of 1141
Table 30. 8 I2C Bus Inter face Timi ng of H D6432199, HD6432198, HD6432197, and
HD6432196
(Conditions: Vc c = AVcc = 4.0 V t o 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C unless otherwise
specified.)
Values
Item Symbol Test
Conditions Min Typ Max Unit Figure
SCL inpu t cycle time tSCL 12  tcyc
SCL input high pulse width tSCLH 3 tcyc
SCL input low pulse width tSCLL 5 tcyc
SCL, SDA input rise time tsr 
7.5*tcyc
SCL, SDA input fall time tsf 
300 ns
SCL, SDA input spike pulse
removal time tsp 
1t
cyc
SD A input b us free ti me tBUF 5 tcyc
Start conditi on input hold time tSTAS 3 tcyc
Re-transmit start condition
input setup time tSTAH 3 tcyc
Stop condition input setup
time tSTOS 3 tcyc
Data input setup time tSDAS 0.5  tcyc
Data input hold time tSDAH 0 ns
SCL, SDA c apaci ty load Cb
400 pF
Figure 30.9
Note: Can also be set t o 17.5 tcyc depending on the selection of clock to be used by t he I2C
module.
Rev. 1.0, 02/00, page 892 of 1141
t
STAH
t
Sr
t
SDAH
t
SCL
t
SCLL
t
SCLH
t
Sf
t
STAS
t
SP
t
STOS
t
SDAS
V
IL
V
IH
SDA
SCL
P* S* Sr* P*
S, P and Sr denote the following:
S : Start conditions
P : Stop conditions
Sr: Re-transmit start conditions
Note:
t
BUF
Figure 30.9 I2C Bus Inte rfa ce I/O Timi ng
Rev. 1.0, 02/00, page 893 of 1141
30.2.5 A/D Converter Characteristi cs of HD6432199, HD6432198, HD6432197, and
HD6432196
Table 30. 9 A/D Conver ter Char acteristics of H D6432199, HD6432198, HD6432197, and
HD6432196
(Conditions: Vc c = AVcc = 4.0 V t o 5.5 V, Vss = AVss = 0.0 V, Ta = –20 t o +75°C unless
otherwise specified.)
Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Note
Ana lo g power
supply voltage AVcc AVcc Vcc−
0.3 Vcc Vcc+
0.3 V
Analog inpu t
voltage AVIN AN0 to AN7,
AN8 to ANB AVss AVcc V
AICC AVcc AVcc = 5.0V  2.0 mAAna lo g power
supply current AISTOP AVcc Vcc = 2.5 V to
5.5 V
At reset and in
pow er -d own mo de
 10 µA
Analog inpu t
capacitance CAIN AN0 to AN7,
AN8 to ANB  30 pF
Allowable si gnal
sour c e im p ed anc e RAIN AN0 to AN7,
AN8 to ANB  10 kΩ
Resolution  10 Bit
Absolute accuracy Vcc = AVcc =
5.0 V  ±
4LSB
Vcc = AV cc =
4.0 V t o 5.0 V ±
4LSB Reference
value
Conversion time 13.4 26.6 µs
Note: Do not open the AVcc and AVss pin even when the A/D converter is not in use. Set AVcc =
Vcc and AVss = Vss.
Rev. 1.0, 02/00, page 894 of 1141
30.2.6 Ser vo Section Ele ctrical Characteristics of HD6432199, HD6432198, H D6432197,
and HD6432196
Table 30. 10 Servo Sec tion Electrical Char acteristics of HD6432199, HD6432198,
HD6432197, and HD6432196 (reference values)
(Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25°C unless otherwise specified.)
Reference Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Note
CTLGR3 = 0, CTLRG2 = 0, CTLRG1 =
0, CTLRG0 = 0, f = 10kHz 33.0 35.0 37.0
CTLGR3 = 0, CTLRG2 = 0, CTLRG1 =
0, CTLRG0 = 1, f = 10kHz 35.5 37.5 39.5
CTLGR3 = 0, CTLRG2 = 0, CTLRG1 =
1, CTLRG0 = 0, f = 10kHz 38.0 40.0 42.0
CTLGR3 = 0, CTLRG2 = 0, CTLRG1 =
1, CTLRG0 = 1, f = 10kHz 40.5 42.5 44.5
CTLGR3 = 0, CTLRG2 = 1, CTLRG1 =
0, CTLRG0 = 0, f = 10kHz 43.0 45.0 47.0
CTLGR3 = 0, CTLRG2 = 1, CTLRG1 =
0, CTLRG0 = 1, f = 10kHz 45.5 47.5 49.5
CTLGR3 = 0, CTLRG2 = 1, CTLRG1 =
1, CTLRG0 = 0, f = 10kHz 48.0 50.0 52.0
CTLGR3 = 0, CTLRG2 = 1, CTLRG1 =
1, CTLRG0 = 1, f = 10kHz 50.5 52.5 54.5
CTLGR3 = 1, CTLRG2 = 0, CTLRG1 =
0, CTLRG0 = 0, f = 10kHz 53.0 55.0 57.0
CTLGR3 = 1, CTLRG2 = 0, CTLRG1 =
0, CTLRG0 = 1, f = 10kHz 55.5 57.5 59.5
CTLGR3 = 1, CTLRG2 = 0, CTLRG1 =
1, CTLRG0 = 0, f = 10kHz 58.0 60.0 62.0
CTLGR3 = 1, CTLRG2 = 0, CTLRG1 =
1, CTLRG0 = 1, f = 10kHz 60.5 62.5 64.5
CTLGR3 = 1, CTLRG2 = 1, CTLRG1 =
0, CTLRG0 = 0, f = 10kHz 63.0 65.0 67.0
CTLGR3 = 1, CTLRG2 = 1, CTLRG1 =
0, CTLRG0 = 1, f = 10kHz 65.5 67.5 69.5
CTLGR3 = 1, CTLRG2 = 1, CTLRG1 =
1, CTLRG0 = 0, f = 10kHz 68.0 70.0 72.0
PB-CTL
input
amplifier
voltage
gain
CTL (+)
CTLGR3 = 1, CTLRG2 = 1, CTLRG1 =
1, CTLRG0 = 1, f = 10kHz 70.5 72.5 74.5
dB
V+TH AC coupling,
C = 0.1 µF Typ (non pol) 250
PB-CTL
Schmitt
input V−TH
CTLSMT (i)
AC coupling,
C = 0.1 µF Typ (non pol) −
250
mVp
Analog
switch ON
resistance
REB CTLFB 150 Ω
CTL (+) 12
REC-CTL
output
current
ICTL CTL (−)Series resistance = 0 Ω12 mA
REC-CTL
pin-to-pin
resistance
RCTL 10 kΩ
CTL
reference
output
voltage
CTLREF 1/2
SVcc V
Rev. 1.0, 02/00, page 895 of 1141
Reference Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Note
CFG pin bias
voltage CFG 1/2
SVCC
V
CFG input level CFG AC coupling,
C = 1 µF Typ 1.0 
Vpp
CFG input
impedance CFG 10 kΩ
V+THCF Rise threshold
level 2.25
CFG input
th reshold value
V−THCF
CFG
Fall threshol d level 2.75
V
V+THDF Rising ed ge
Schm itt level 1.95
DFG S c hmitt inpu t
V−THDF
DFG
Falling edge
Schm itt level 1.85
V
V+THDP Rising edge
Schm itt level 3.55
DP G Schmitt inpu t
V−THDP
DPG
Falling edge
Schm itt level 3.45
V
VOH −IOH = 0.1 mA 4.0 
VOM No load, Hiz = 1 2.5
3-l ev el ou tput
voltage
VOL
Vpulse
IOL = 0.1 mA  1.0
V
3-l ev el ou tput pin
divided voltage
resistance
Vpulse 15 kΩ
Digital input high
level VIH 0.8
Vcc Vcc+
0.3
Digital input lo w
level VIL
COMP,
EXCTL,
EXCAP,
EXTTRG −0.3 0.2
Vcc
V
Digit al output high
level VOH −IOH = 1 mA Vcc
–1.0 
Digital output low
level VOL
H.AmpSW,
C.Rotary,
VIDEOFF,
AUDIOFF,
DRMPWM,
CAPPWM,
SV1, SV2
IOL = 1.6 mA  0.6
V
Curr e nt dis s ipatio n ICCSV SVcc At no load 510mA
Rev. 1.0, 02/00, page 896 of 1141
30.2.7 OSD El ectrical Characteristics of HD6432199, HD6432198, HD6432197, and
HD6432196
Table 30. 11 OSD El ectrical Characteristics of HD6432199, H D6432198, HD6432197, and
HD6432196 (Reference Value )
(Conditions: Vc c = OVcc = 5.0 V, Vss = OVss = 0.0 V, Ta = 25°C unless otherwise specified)
Values
Item Symbol Applicable
Pins Test
Conditions Min Typ Max Unit Note
Composi te video inpu t
voltage VCVIN CVin1
CVin2
2V
PP
VCL1 CVin1 1.2 1.4 1.6Clamp voltage
VCL2 CVin2 1.8 2 2.2
V
C.Video gain GCVC CVin1
CVout
At chroma-
through
f = 3. 58 MHz
VIN=500 mVpp
−3−20 dB
Pedestal bias VPED CVout 45 IRE *1
Color burst bias VBST 40 IRE *1
VBL1 10
VBL2 30
VBL3 50
Background
bias Black, blue,
green,
cyan, red,
magenta,
yellow, white VBL4 70
IRE *2
VKBL1 0
Black
VKBL2 25
VKOL1 25
Blue, green,
cyan, red,
magenta,
yellow
VKOL2 45
VKCL1 45
Cursor bias
White
VKCL2 55
IRE *2
Rev. 1.0, 02/00, page 897 of 1141
Values
Item Symbol Applicable
Pins Test
Conditions Min Typ Max Unit Note
VCBL1 CVout 0
VCBL2 10
VCBL3 20
Black
VCBL4 30
VCOL1 25
VCOL2 45
VCOL3 55
Blue, green,
cyan, red,
magenta,
yellow VCOL4 65
VCCL1 45
VCCL2 70
VCCL3 80
Character
bias
White
VCCL4 90
IRE *2
VEDG1 0Edge brightness level VEDG2 90 IRE
IRE *2
VBTN1 15Button br ightness level VBTN2 75 IRE *2
Color burst chroma
amplitude VBSTA 40 IRE
VCRA1 60
Chroma
amplitude
(background,
cursor,
character)
Blue, green,
cyan, red,
magenta,
yellow
VCRA2 80
IRE
Colorburst φ BSTN 0
Blue φ BL UN π
Green φ GRNN 7 π/4
Cyan φ CYNN 3 π/2
Red φ REDN π/2
Magenta φ M ZTN 3 π/4
Chroma hue
angle
(background,
cursor,
character)
(NTSC)
Yellow φ YETN 0
rad *3
Rev. 1.0, 02/00, page 898 of 1141
Values
Item Symbol Applicable
Pins Test
Conditions Min Typ Max Unit Note
Colorburst φ BSTP CVout ± π/4
Blue φ BL UP ± π
Green φ GRNP ± 7π/4
Cyan φ CYNP ± 3π/2
Red φ REDP ± π/2
Magenta φ M ZTP ± 3π/4
Chroma hue
angle
(background,
cursor,
character)
(PAL)
Yellow φ YELP 0
rad *3
CCMP1 CVin2 5
CCMP2 10
CCMP3 15
Csync sepa ration
comparator
CCMP4 20
IRE *1
ECMP1 CVin2 0
ECMP2 5
ECMP3 15
ECMP4 20
ECMP5 25
ECMP6 35
EDS separ at ion
comparator
ECMP7 40
IRE *2
ViH⊥0.85
OVcc OVcc
+0.3 V
Input high level
ViHT
Csync/Hsync
VLPF/Vsync
0.7
OVcc OVcc
+0.3 V
ViL⊥−0.3 0.3
OVcc VInput lo w level
ViLT
Csync/Hsync
VLPF/Vsync
−0.3 0.15
OVcc V
Output high level VOH Csync/Hsync −IOH=0.4mA OVcc
−1.4 V
Outp u t low le vel VOL Csync/Hsync IOL=0.4mA 1.4 V
Rev. 1.0, 02/00, page 899 of 1141
Values
Item Symbol Applicable
Pins Test
Conditions Min Typ Max Unit Note
Oscillation
stabilizing time trc 4/2fscin
4/2fscout Crystal
oscillator 40 ms
M/NTSC 14.31818 MHz4/2fscin
4/2fscout B,G,H/PAL
I/PAL
D,K/PAL
4.43-NTSC
B,G,H/SECAM
L/SECAM
D,K,K1/SECAM
17.734475
(17.734476) MHz
N/PAL 14.328225 MHz
4fsc
M/PAL 14.30244596 MHz
2fsc M/NTSC 7.15909 MHz4/2fscin
4/2fscout B,G,H/PAL
I/PAL
D,K/PAL
4.43-NTSC
B,G,H/SECAM
L/SECAM
D,K,K2/SECAM
8.8672375
(8.867238) MHz
N/PAL 7.1641125 MHz
Oscillating
frequency
M/PAL 7.15122298 MHz
Vfsc 4/2fscin
4/2fscout AC coupling
C=1µF typ 0.3 Vcc+0.3 Vpp
VIH 4/2fscin 0.7Vcc Vcc+0.3
External clock
input level
VIL −0.3 0.3Vcc V
External clock
duty 4/2fscin
4/2fscout 47 50 53 %
6.3 9 11.7 MHzAFC reference
clock ( dot clock) AFCOSC AFCOSC LC o s c illa tion
4.9 79.1
Current
dissipation ICCOSD OVcc At no signal TBD mA
Notes: •IRE: Units for video amplitude; 0.714 V video level is specified as 100 IRE
•4fsc and 2fsc must be adjusted within ± 30 ppm, including tempe rature dependency .
1. Bi as f rom the sync tip cl amp level ( referen ce val ue after −6 dB ).
2. Bias from t he pedestal level ( r eference value after −6 dB).
3. At 4fsc input.
Rev. 1.0, 02/00, page 900 of 1141
30.3 Electrical Charact eristics of HD64F 2199
30.3.1 DC Characteristics of HD64F2199
Table 30. 12 DC Characteri stics of HD64F2199
(Conditions: Vcc = AVcc = 4. 0 V t o 5.5 V*1, Vss = 0. 0 V, Ta = –2 0 to + 75°C unless otherwise
specified.)
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
MD0 Vcc=2.7 V to
5.5V 0.9 Vcc Vcc+0.3
0.8 Vcc Vcc+0.3
5(6
, FWE, IC, IRQ0
to IRQ5 Vcc= 2.7 V to
5.5V 0.9 Vcc Vcc+0.3
SCK1, SI1, FTIA,
FTIB, FTIC, FTID,
TRIG, TM BI,
$'75*
0.8 Vcc Vcc+0.3
Vcc–0.5 Vcc+0.3OSC1
Vcc=2.7 V to
5.5V Vcc–0.3 Vcc+0.3
0.7 Vcc Vcc+0.3
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P60 to P67,
P70 to P77,
P80 to P87
Vcc=2.7 V to
5.5V 0.8 Vcc Vcc+0.3
Input hi gh
voltage VIH
Csyn c 0.7 V cc Vcc+0.3
V
Rev. 1.0, 02/00, page 901 of 1141
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
M D0 Vcc=2.7 V to
5.5 –0.3 0.1 Vcc
−0.3 0.2 Vcc
5(6
, FWE, IC,
IRQ0 to IRQ5 Vcc= 2.7 V to
5.5 −0.3 0.1 Vcc
SCK1, SI1, FTIA, FTIB,
FTIC, FTID, TRIG,
TMBI,
$'75*
−0.3 0.2 Vcc
−0.3 0.5
OSC1
Vcc=2.7 V to
5.5 −0.3 0.3
−0.3 0.3 Vcc
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P60 to P67,
P70 to P77,
P80 to P87
Vcc=2.7 V to
5.5 −0.3 0.2 Vcc
Input low
voltage VIL
Csync −0.3 0.2 Vcc
V
Rev. 1.0, 02/00, page 902 of 1141
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
−IOH=1.0mA Vcc–1.0  V
−IOH=0.5mA Vcc–
0.5 VRefer-
ence
value
Output
high
voltage
VOH SO1, SCK1, PWM1,
PWM2, PWM3,
PWM4, PWM14,
BUZZ, TMO, TMOW,
FTOA, FTOB, PPG0 to
PPG7,
RP0 to RP7,
RP8 to RPB,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P60 to P67,
P70 to P77,
P80 to P87,
SV1, SV2, R, G, B,
YCO, YBO
−IOH=0.1mA
Vcc=2.7 V to
5.5V
Vcc–0.5  V
IOL=1.6mA 
0.6 VSO1, SCK1, PWM1,
PWM2, PWM3,
PWM4, PWM14,
BUZZ, TMO, TMOW,
FTOA, FTOB, PPG0 to
PPG7,
RP0 to RP7,
RP8 to RPB,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P70 to P77,
P80 to P87, SV1, SV2,
R, G, B, YCO, YBO
IOL=0.4mA
Vcc=2.7 V to
5.5V

0.4 V
IOL=20mA 
1.5 V
IOL=1.6mA 
0.6 V
Output
low
voltage
VOL
P60 to P67,
IOL=0.4mA
Vcc=2.7 V to
5.5V

0.4 V
Rev. 1.0, 02/00, page 903 of 1141
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
MD0, FWE Vin=0.5 to
Vcc–0.5V 
1.0
5(6
,
,54
to
,54
,
,&
Vin=0.5 to
Vcc–0.5V 
1.0
SCK1, SI1, SDA0,
SCL0, SDA1, SCL1,
FTIA, FTIB, FTIC, FTID,
TRIG, TM BI,
$'75*
Vin=0.5 to
Vcc–0.5V 
1.0
OSC1 Vin=0.5 to
Vcc−0.5V 
1.0
Input
/output
leakage
current
IIL
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P60 to P67,
P70 to P77,
P80 to P87,
Vin=0.5 to
Vcc–0.5V 
1.0
µA
P00 to P07,
AN8 to ANB Vin=0.5 to
AVcc–0.5V 
1.0
Pull-up
MOS
current
−Ip P10 to P17,
P20 to P27,
P30 to P37
Vcc=5.0V,
Vin=0V 50 300 µA*2
Input
capacity Cin All input pins except
power supply pins
P23, P24, P25, and
P26, and analog pins
fin=1 MHz ,
Vin=0V,
Ta=25°C

15 pF
P23, P24, P25, P26 fin =1 MH z ,
Vin=0V,
Ta=25°C

20 pF
Rev. 1.0, 02/00, page 904 of 1141
Values
Item Symbol Applicable
Pins Test
Conditions Min Typ Max Unit Notes
Vcc=5V,
fOSC=10 MHz ,
High-speed
mode
TBD mA *3
Active
mode
current
dissipa-
tion (CPU
operating)
IOPE Vcc
Vcc=5V,
fOSC=10 MHz ,
Medium-speed
mode (1/64)
TBD mA Reference value
Active
mode
current
dissipa-
tion
(reset)
IRES Vcc Vcc=5V,
fOSC=10 MHz —TBD mA *3
Sleep
mode
current
dissipa-
tion
ISLEEP Vcc Vcc=5V,
fOSC=10 MHz
High-speed
mode
TBD mA *3
Vcc=2.7V,
32kHz
With crystal
oscillator
(φ su b=φw/2)
TBD *3
Subactive
mode
current
dissipa-
tion
ISUB Vcc
Vcc=2.7V,
32kHz
With crystal
oscillator
(φ su b=φw/8)
TBD
µA
Reference value*3
Vcc=2.7V,
32kHz
With crystal
oscillator
(φ su b=φw/2)
TBD *3
Subsleep
mode
current
dissipa-
tion
ISUBSLP Vcc
Vcc=2.7V,
32kHz
With crystal
oscillator
(φ su b=φw/8)
TBD
µA
Reference value*3
Rev. 1.0, 02/00, page 905 of 1141
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
Vcc=2.7V,
32kHz
With crystal
oscillator

TBD µA*3
Watch
mode
current
dissipa-
tion
IWATCH Vcc
Vcc=5.0V,
32kHz
With crystal
oscillator
TBD µ
AReference
value*3
Standby
mode
current
dissipa-
tion
ISTBY Vcc X1=V
CL
, 32k Hz
Without crystal
oscillator

5µA*3
RAM data
retaining
voltage in
standby
mode
VSTBY 2.0 V
Notes: 1. Do not open the AVcc and AVss pin even when the A/D conver ter is not in use.
2. Cur rent value when th e releva nt b it of the pull-up MOS selec t r egister (PUR1 to PUR3)
is set to 1.
3. The current on t he pull-up MOS or the output buffer excluded.
Tabl e 30. 13 P i n Status a t Curre nt Dissi pa tion Me a surement
Mode
5(6
5(6
pin Internal State Pin Oscillator Pin
Active mode
High-speed , medium -
speed
Vcc Operating Vcc
Sleep mode
High-speed , medium -
speed
Vcc O n ly CPU and
servo circuit s
halted
Vcc
Reset Vss Reset Vcc
Standby m ode Vcc All circuits halted Vcc
Main clock:
Cry sta l o scillator
Sub clock:
X1 pin = VCL
Subactive mode Vcc CPU and timer A
operating Vcc
Subsleep mode Vcc Timer A operating Vcc
Watch mode Vcc Timer A operating Vcc
Main clock:
Cry sta l o scillator
Sub clock:
Cry sta l o scillator
Rev. 1.0, 02/00, page 906 of 1141
Table 30. 14 Bus Drive Characteristics of HD64F2199
(Conditions: Vc c = AVcc = 4.0 V t o 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C.)
Appl ic a ble pin: SCL0, SCL1, SDA0, SDA1
Values
Item Symbol Applicable Pins Test
Conditions Min Typ Max Unit Notes
VT−0.3Vcc  V
VT+
0.7Vcc V
Schmitt
trigger
input VT+
–VT−
SCL0, SDA0,
SCL1, SDA1
0.05Vcc  V
Input hi gh
level
voltage
VIH SCL0, SDA0,
SCL1, SDA1 0.7Vcc Vcc+0.5 V
Input low
level
voltage
VIL SCL0, SDA0,
SCL1, SDA1 −0.5 0.3Vcc V
IOL=8mA 
0.5
Output
low lev e l
voltage
VOL SCL0, SDA0,
SCL1, SDA1 IOL=3mA 
0.4
V
SCL and
SDA
output fall
time
tof SCL0, SDA0,
SCL1, SDA1 20+
0.1Cb 250 ns
Rev. 1.0, 02/00, page 907 of 1141
30.3.2 Allowable Output Currents of HD64F2199
The specifications for the digital pins are shown below.
Table 30.15 Allowable Output Currents of HD64F2199
(Conditions: Vcc = 2.7 V to 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C)
Item Symbol Value Unit Notes
Allow able input current (to chip) IO2mA
*1
Allow able input current (to chip) IO22 mA *2
Allow able input current (to chip) IO10 mA *3
Allowable output current (from chip) −IO2mA
*4
Total allowable input cur r ent (to chip) ΣIO80 mA *5
Total allowable output cur r ent (from chip) −ΣIO50 mA *6
Notes: 1. The allowable input current is t he maximum value of the current flowing from each I/O
pin to VSS (exc ept for port 6, SCL0, SDA0, SCL1 and SDA1).
2. The allowable input current is the maximum value of the current flowing f r om each I/O
pin to VSS. This applies to port 6.
3. The allowable input current is the maximum value of the current flowing f r om each I/O
pin to VSS. This applies to SCL0, SDA0, SCL1 and SDA1.
4. The allowable out put cur r ent is t he maximum value of the current flowing f r om VCC to
each I/O pin.
5. The total allowable input current is the sum of the curr ents flowing from all I/O pins to
VSS simultaneously.
6. The total allowable out put current is the sum of the cur r ents flowing from VCC to all I/O
pins.
Rev. 1.0, 02/00, page 908 of 1141
30.3.3 AC Characteristics of HD64F2199
Table 30. 16 AC Char acteristics of HD64F 2199
(Conditions: Vc c = AVcc = 4.0 V t o 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C unless otherwise
specified.)
Values
Item Symbol Applicable
Pins Test
Conditions Min Typ Max Unit Notes
Clock oscillation
frequency fOSC OSC1, OSC2 8 10 MHz
Cl ock cycle time tcyc OSC1 , OSC2 100 125 ns Figure
30.10
Subclock
oscillation
frequency
fXX1, X2 Vcc = 2.7 V to
5.5 V 32.768 kHz
Subclock cycle
time tsubcyc X1, X2 Vcc = 2.7 V to
5.5 V 30.518 µ
sFigure
30.11
OSC1, OSC2 Crystal oscillator  10 msOscillation
st abi liz a tion time trc
X1, X2 32kHz crystal
oscillator  2s
External clock high
width tCPH OSC1 40 
ns
External clock low
width tCPL OSC1 40 
ns
Ext ernal clo ck rise
time tCPr OSC1  10 ns
Ext ernal clo ck fall
time tCPf OSC1  10 ns
Figure
30.10
External clock
st abi liz a tion de lay
time
tDEXT OSC1 500 µ
sFigure
30.12
Subclock input low
level pulse width tEXCLL X1 Vcc = 2.7 V to
5.5 V 15.26 µ
s
Subclock input
high lev el pulse
width
tEXCLH X1 Vcc = 2.7 V to
5.5 V 15.26 µ
s
Subclock input rise
time tEXCLr X1 Vcc = 2.7 V to
5.5 V  10 ns
Subclock input fall
time tECXLf X1 Vcc = 2.7 V to
5.5 V  10 ns
Figure
30.11
Rev. 1.0, 02/00, page 909 of 1141
Values
Item Symbol Applicable
Pins Test
Conditions Min Typ Max Unit Figure
5(6
pin low level
width tREL
5(6
Vcc = 2.7 V to
5.5 V 20 
tcyc Figure
30.13
Inp ut pi n hi gh lev el
width tIH
,54
to
,54
,
,&
,
$'75*
,
TMBI, FTIA,
FTIB, FTIC,
FTID,
RPTRIG
Vcc = 2.7 V to
5.5 V 2
tcyc
tsubcyc
Input pi n low lev e l
width tIL
,54
to
,54
,
,&
,
$'75*
,
TMBI, FTIA,
FTIB, FTIC,
FTID,
RPTRIG
Vcc = 2.7 V to
5.5 V 2
tcyc
tsubcyc
Figure
30.14
t
cyc
t
CPH
V
IL
V
IH
OSC1
t
CPL
t
CPf
t
CPr
Fi g ure 30.10 Syste m Clock Timing
t
EXCLf
t
subcyc
t
EXCLH
t
EXCLL
t
EXCLr
V
IL
V
IH
X1 Vcc × 0.5
Fi g ure 30.11 Subcl ock Input Tim i ng
Rev. 1.0, 02/00, page 910 of 1141
Vcc
OSC1
t
DEXT
*
RES
φ (Internal)
4.0V
The t
DEXT
includes the RES pin Low level width 20 t
cyc
.
Note: *
Figure 30.12 External Clock Stabilization Delay Timing
RES V
IL
t
REL
Fi g ure 30.13 Rese t Input Timi ng
t
IL
t
IH
V
IH
V
IL
to ,
, ,
TMBI, FTIA,
FTIB, FTIC,
FTID, RPTRIG
Fi g ure 30.14 Input Timi ng
Rev. 1.0, 02/00, page 911 of 1141
30.3.4 Serial Interface Timing of HD64F2199
Table 30.17 Serial Interface Timing of HD64F2199
(Conditions: Vc c = AVcc = 4.0 V t o 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C unless otherwise
specified.)
Values
Item Symbol Applicable
Pins Test
Conditions Min Typ Max Unit Figure
Asynchroniza-
tion 4
Input clock cycle tscyc SCK1
Clock
synchronization 6
tcyc
Input clock pulse
width tSCKW SCK1 0.4 0.6 tscyc
Input clock rise time tSCKr SCK1  1.5 tcyc
Input clock fall time tSCKf SCK1  1.5 tcyc
Figure
30.15
Transmit data delay
time (clock sync) tTXD SO1  100 ns
Recei v e data setup
time (clock sync) tRXS SI1 100 
ns
Recei v e data hold
time (clock sync) tRXH SI1 100 
ns
Figure
30.16
t
SCKf
t
SCKr
V
IL
or V
OL
V
IH
or V
OH
SCK1
t
SCKW
t
scyc
Fi g ure 30.15 SCK1 Clock Timi ng
Rev. 1.0, 02/00, page 912 of 1141
V
IL
V
IH
t
TXD
SCK1
SO1
SI1
t
RXS
t
RXH
V
OH
V
OL
Fi g ure 30.16 SCI I/O Timi ng/Cl ock Sy nchro niz ati on Mode
LSI output pin
Timing reference level
V
OH
: 2.0V
V
OL
: 0.8V
30pF 12kΩ
2.4kΩ
Vcc
Figure 30.17 Output Load Conditions
Rev. 1.0, 02/00, page 913 of 1141
Table 30. 18 I2C Bus Interface Timing of HD64F2199
(Conditions: Vc c = AVcc = 4.0 V t o 5.5 V, Vss = 0.0 V, Ta = –20 to +75°C unless otherwise
specified.)
Values
Item Symbol Test
Conditions Min Typ Max Unit Figure
SCL inpu t cycle time tSCL 12  tcyc
SCL input high pulse width tSCLH 3 tcyc
SCL input low pulse width tSCLL 5 tcyc
SCL, SDA input rise time tsr 
7.5*tcyc
SCL, SDA input fall time tsf 
300 ns
SCL, SDA input spike pulse
removal time tsp 
1t
cyc
SD A input b us free ti me tBUF 5 tcyc
Start conditi on input hold time tSTAS 3 tcyc
Re-transmit start condition
input setup time tSTAH 3 tcyc
Stop condition input setup
time tSTOS 3 tcyc
Data input setup time tSDAS 0.5  tcyc
Data input hold time tSDAH 0 ns
SCL, SDA c apaci ty load Cb
400 pF
Figure
30.18
Note: Can also be set t o 17.5 tcyc depending on the selection of clock to be used by t he I2C
module.
Rev. 1.0, 02/00, page 914 of 1141
t
STAH
t
Sr
t
SDAH
t
SCL
t
SCLL
t
SCLH
t
Sf
t
STAS
t
SP
t
STOS
t
SDAS
V
IL
V
IH
SDA
SCL
P* S* Sr* P*
S, P and Sr denote the following:
S : Start conditions
P : Stop conditions
Sr: Re-transmit start conditions
Note: *
t
BUF
Figure 30.18 I2C Bus Interface I/O Timing
Rev. 1.0, 02/00, page 915 of 1141
30.3.5 A/D Converter Characteristics of HD64F2199
Table 30.19 A/D Converter Characteristics of HD64F2199
(Conditions: Vc c = AVcc = 4.0 V t o 5.5 V, Vss = AVss = 0.0 V, Ta = –20 t o +75°C unless
otherwise specified.)
Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Note
Ana lo g power
supply voltage AVcc AVcc Vcc−
0.3 Vcc Vcc+
0.3 V
Analog inpu t
voltage AVIN AN0 to AN7,
AN8 to ANB AVss AVcc V
AICC AVcc AVcc = 5.0V  2.0 mA
Ana lo g power
supply current AISTOP AVcc Vcc = 2.7 V to 5.5 V
At reset and in
pow er -d own mo de
 10 µA
Analog inpu t
capacitance CAIN AN0 to AN7,
AN8 to ANB  30 pF
Allowable si gnal
sour c e im p ed anc e RAIN AN0 to AN7,
AN8 to ANB  10 kΩ
Resolution  10 Bit
Absolute accuracy V cc = AVcc =
5.0 V  ±
4LSB
Vcc = AV cc =
4.0 V t o 5.0 V ±
4LSB Reference
value
Conversion time 13.4 26.6 µs
Note: Do not open the AVcc and AVss pin even when the A/D converter is not in use. Set AVcc =
Vcc and AVss = Vss.
Rev. 1.0, 02/00, page 916 of 1141
30.3.6 Servo Section Electrical Characteristics of HD64F2199
Table 30.20 Servo Section Electrical Characteristics of HD64F2199 (reference values)
(Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25°C unless otherwise specified.)
Reference Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Note
CTLGR3 = 0, CTLRG2 = 0, CTLRG1 =
0, CTLRG0 = 0, f = 10kHz 33.0 35.0 37.0
CTLGR3 = 0, CTLRG2 = 0, CTLRG1 =
0, CTLRG0 = 1, f = 10kHz 35.5 37.5 39.5
CTLGR3 = 0, CTLRG2 = 0, CTLRG1 =
1, CTLRG0 = 0, f = 10kHz 38.0 40.0 42.0
CTLGR3 = 0, CTLRG2 = 0, CTLRG1 =
1, CTLRG0 = 1, f = 10kHz 40.5 42.5 44.5
CTLGR3 = 0, CTLRG2 = 1, CTLRG1 =
0, CTLRG0 = 0, f = 10kHz 43.0 45.0 47.0
CTLGR3 = 0, CTLRG2 = 1, CTLRG1 =
0, CTLRG0 = 1, f = 10kHz 45.5 47.5 49.5
CTLGR3 = 0, CTLRG2 = 1, CTLRG1 =
1, CTLRG0 = 0, f = 10kHz 48.0 50.0 52.0
CTLGR3 = 0, CTLRG2 = 1, CTLRG1 =
1, CTLRG0 = 1, f = 10kHz 50.5 52.5 54.5
CTLGR3 = 1, CTLRG2 = 0, CTLRG1 =
0, CTLRG0 = 0, f = 10kHz 53.0 55.0 57.0
CTLGR3 = 1, CTLRG2 = 0, CTLRG1 =
0, CTLRG0 = 1, f = 10kHz 55.5 57.5 59.5
CTLGR3 = 1, CTLRG2 = 0, CTLRG1 =
1, CTLRG0 = 0, f = 10kHz 58.0 60.0 62.0
CTLGR3 = 1, CTLRG2 = 0, CTLRG1 =
1, CTLRG0 = 1, f = 10kHz 60.5 62.5 64.5
CTLGR3 = 1, CTLRG2 = 1, CTLRG1 =
0, CTLRG0 = 0, f = 10kHz 63.0 65.0 67.0
CTLGR3 = 1, CTLRG2 = 1, CTLRG1 =
0, CTLRG0 = 1, f = 10kHz 65.5 67.5 69.5
CTLGR3 = 1, CTLRG2 = 1, CTLRG1 =
1, CTLRG0 = 0, f = 10kHz 68.0 70.0 72.0
PB-CTL
input
amplifier
voltage
gain
CTL (+)
CTLGR3 = 1, CTLRG2 = 1, CTLRG1 =
1, CTLRG0 = 1, f = 10kHz 70.5 72.5 74.5
dB
V+TH AC coupling,
C = 0.1 µF Typ (non pol) 250
PB-CTL
Schmitt
input V−TH
CTLSMT (i)
AC coupling,
C = 0.1 µF Typ (non pol) −
250
mVp
Analog
switch ON
resistance
REB CTLFB 150 Ω
CTL (+) 12
REC-CTL
output
current
ICTL CTL (−)Series resistance = 0 Ω12 mA
REC-CTL
pin-to-pin
resistance
RCTL 10 kΩ
CTL
reference
output
voltage
CTLREF 1/2
SVcc V
Rev. 1.0, 02/00, page 917 of 1141
Reference Values
Item Symbol Applicable
Pins Test Conditions Min Typ Max Unit Note
CFG pin bias
voltage CFG 1/2
SVCC
V
CFG input level CFG AC coupling,
C = 1 µF Typ 1.0 
Vpp
CFG input
impedance CFG 10 kΩ
V+THCF Rise threshold
level 2.25
CFG input
th reshold value
V−THCF
CFG
Fall threshol d level 2.75
V
V+THDF Rising ed ge
Schm itt level 1.95
DFG S c hmitt inpu t
V−THDF
DFG
Falling edge
Schm itt level 1.85
V
V+THDP Rising edge
Schm itt level 3.55
DP G Schmitt inpu t
V−THDP
DPG
Falling edge
Schm itt level 3.45
V
VOH −IOH = 0.1 mA 4.0 
VOM No load, Hiz = 1 2.5
3-l ev el ou tput
voltage
VOL
Vpulse
IOL = 0.1 mA  1.0
V
3-l ev el ou tput pin
divided voltage
resistance
Vpulse 15 kΩ
Digital input high
level VIH 0.8
Vcc Vcc+
0.3
Digital input lo w
level VIL
COMP,
EXCTL,
EXCAP,
EXTTRG −0.3 0.2
Vcc
V
Digit al output high
level VOH −IOH = 1 mA Vcc
–1.0 
Digital output low
level VOL
H.AmpSW,
C.Rotary,
VIDEOFF,
AUDIOFF,
DRMPWM,
CAPPWM,
SV1, SV2
IOL = 1.6 mA  0.6
V
Curr e nt dis s ipatio n ICCSV SVcc At no load 510mA
Rev. 1.0, 02/00, page 918 of 1141
30.3.7 OSD El ectrical Characteristics of HD64F2199
Table 30. 21 OSD El ectrical Characteristics of HD64F2199 (Reference Value)
(Conditions: Vc c = OVcc = 5.0 V, Vss = OVss = 0.0 V, Ta = 25°C unless otherwise specified)
Values
Item Symbol Applicable
Pins Test
Conditions Min Typ Max Unit Note
Composi te video inpu t
voltage VCVIN CVin1
CVin2
2V
PP
VCL1 CVin1 1.2 1.4 1.6Clamp voltage VCL2 CVin2 1.8 2 2.2
V
C.Video gain GCVC CVin1
CVout
At chroma-
through
f = 3. 58 MHz
VIN=500 mVpp
−3−20 dB
Pedestal bias VPED CVout 45 IRE *1
Color burst bias VBST 40 IRE *1
VBL1 10
VBL2 30
VBL3 50
Background
bias Black, blue,
green,
cyan, red,
magenta,
yellow, white VBL4 70
IRE *2
VKBL1 0
Black
VKBL2 25
VKOL1 25
Blue, green,
cyan, red,
magenta,
yellow
VKOL2 45
VKCL1 45
Cursor bias
White
VKCL2 55
IRE *2
Rev. 1.0, 02/00, page 919 of 1141
Values
Item Symbol Applicable
Pins Test
Conditions Min Typ Max Unit Note
VCBL1 CVout 0
VCBL2 10
VCBL3 20
Black
VCBL4 30
VCOL1 25
VCOL2 45
VCOL3 55
Blue, green,
cyan, red,
magenta,
yellow VCOL4 65
VCCL1 45
VCCL2 70
VCCL3 80
Character
bias
White
VCCL4 90
IRE *2
VEDG1 0Edge brightness level VEDG2 90 IRE
IRE *2
VBTN1 15Button br ightness level VBTN2 75 IRE *2
Color burst chroma
amplitude VBSTA 40 IRE
VCRA1 60
Chroma
amplitude
(background,
cursor,
character)
Blue, green,
cyan, red,
magenta,
yellow
VCRA2 80
IRE
Colorburst φ BSTN 0
Blue φ BL UN π
Green φ GRNN 7 π/4
Cyan φ CYNN 3 π/2
Red φ REDN π/2
Magenta φ M ZTN 3 π/4
Chroma hue
angle
(background,
cursor,
character)
(NTSC)
Yellow φ YETN 0
rad *3
Rev. 1.0, 02/00, page 920 of 1141
Values
Item Symbol Applicable
Pins Test
Conditions Min Typ Max Unit Note
Colorburst φ BSTP CVout ± π/4
Blue φ BL UP ± π
Green φ GRNP ± 7π/4
Cyan φ CYNP ± 3π/2
Red φ REDP ± π/2
Magenta φ M ZTP ±3π/4
Chroma hue
angle
(background,
cursor,
character)
(PAL)
Yellow φ YELP 0
rad *3
CCMP1 CVin2 5
CCMP2 10
CCMP3 15
Csync sepa ration
comparator
CCMP4 20
IRE *1
ECMP1 CVin2 0
ECMP2 5
ECMP3 15
ECMP4 20
ECMP5 25
ECMP6 35
EDS separ at ion
comparator
ECMP7 40
IRE *2
ViH⊥0.85
OVcc OVcc
+0.3 V
Input high level
ViHT
Csync/Hsync
VLPF/Vsync
0.7
OVcc OVcc
+0.3 V
ViL⊥−0.3 0.3
OVcc VInput lo w level
ViLT
Csync/Hsync
VLPF/Vsync
−0.3 0.15
OVcc V
Output high level VOH Csync/Hsync −IOH=0.4mA OVcc
−1.4 V
Outp u t low le vel VOL Csync/Hsync IOL=0.4mA 1.4 V
Rev. 1.0, 02/00, page 921 of 1141
Values
Item Symbol Applicable
Pins Test
Conditions Min Typ Max Unit Note
Oscillation
stabilizing time trc 4/2fscin
4/2fscout Crystal
oscillator 40 ms
M/NTSC 14.31818 MHz4/2fscin
4/2fscout B,G,H/PAL
I/PAL
D,K/PAL
4.43-NTSC
B,G,H/SECAM
L/SECAM
D,K,K1/SECAM
17.734475
(17.734476) MHz
N/PAL 14.328225 MHz
4fsc
M/PAL 14.30244596 MHz
2fsc M/NTSC 7.15909 MHz4/2fscin
4/2fscout B,G,H/PAL
I/PAL
D,K/PAL
4.43-NTSC
B,G,H/SECAM
L/SECAM
D,K,K2/SECAM
8.8672375
(8.867238) MHz
N/PAL 7.1641125 MHz
Oscillating
frequency
M/PAL 7.15122298 MHz
Vfsc 4/2fscin
4/2fscout AC coupling
C=1µF typ 0.3 Vcc+0.3 Vpp
VIH 4/2fscin 0.7Vcc Vcc+0.3
External clock
input level
VIL −0.3 0.3Vcc V
External clock
duty 4/2fscin
4/2fscout 47 50 53 %
6.3 9 11.7 MHzAFC reference
clock ( dot clock) AFCOSC AFCOSC LC o s c illa tion
4.9 79.1 MHz
Current
dissipation ICCOSD OVcc At no signal TBD mA
Notes: •IRE: Units for video amplitude; 0.714 V video level is specified as 100 IRE
•4fsc and 2fsc must be adjusted within ± 30 ppm, including tempe rature dependency .
1. Bi as f rom the sync tip cl amp level ( referen ce val ue after −6 dB ).
2. Bias from t he pedestal level ( r eference value after −6 dB).
3. At 4fsc input.
Rev. 1.0, 02/ 00, page 923 of 1141
Appendix A Instruction Set
A.1 Instructions
Operation Notation
Rd General r egister (destination) *1
Rs Gener al r egister ( s our ce) *1
Rn General r egister *1
ERn General r egister (32-bit r egist er )
MAC Multiplication-Addition register (32-bit r egist er ) *2
(EAd) Destination operand
(EAs) Sour ce oper and
EXR Extend register
CCR Condition code register
N N (negat ive f lag) in CCR
Z Z (zer o) flag in CCR
V V (ove rf lo w) flag in CCR
C C (carry) flag in CCR
PC Pr ogr am count er
SP Stack pointer
#IMM I m m ediat e dat a
disp Displacement
+ Addition
−Subtraction
×Multiplication
÷Division
∧Logical AND
∨Logical OR
⊕Exclusive logical OR
→Move from the left to the right
∼Logical complement
( ) <> Contents of oper and
:8/ : 16/ : 24/ : 32 8/16/ 24/ 32 bit lengt h
Notes: 1. G ener al register is 8- bit ( R0H to R7H, R0L t o R7L), 16- bit ( R0 to R7) or 32- bit ( ER0 to
ER7).
2. M AC register cannot be used in this LSI.
Rev. 1.0, 02/ 00, page 924 of 1141
Condition Code Notation
Symbol Description
Modified according to t he instr uct ion result
* Not fixed (value not guar ant eed)
0 Always cleared to 0
1 Always set to 1
−Not aff ect ed by t he instr uct ion execut ion result
Rev. 1.0, 02/ 00, page 925 of 1141
Table A.1 Data Transfer Instr uct i on
MOV.B #xx:8,Rd
MOV.B Rs,Rd
MOV.B @ERs,Rd
MOV.B @(d:16,ERs),Rd
MOV.B @(d:32,ERs),Rd
MOV.B @ERs+,Rd
MOV.B @aa:8,Rd
MOV.B @aa:16,Rd
MOV.B @aa:32,Rd
MOV.B Rs,@ERd
MOV.B Rs,@(d:16,ERd)
MOV.B Rs,@(d:32,ERd)
MOV.B Rs,@-ERd
MOV.B Rs,@aa:8
MOV.B Rs,@aa:16
MOV.B Rs,@aa:32
MOV.W #xx:16,Rd
MOV.W Rs,Rd
MOV.W @ERs,Rd
MOV.W @(d:16,ERs),Rd
MOV.W @(d:32,ERs),Rd
MOV.W @ERs+,Rd
MOV.W @aa:16,Rd
MOV.W @aa:32,Rd
MOV.W Rs,@ERd
MOV.W Rs,@(d:16,ERd)
MOV.W Rs,@(d:32,ERd)
MOV.W Rs,@-ERd
MOV.W Rs,@aa:16
MOV.W Rs,@aa:32
MOV.L #xx:32,ERd
MOV.L ERs,ERd
MOV.L @ERs,ERd
MOV.L @(d:16,ERs),ERd
MOV.L @(d:32,ERs),ERd
MOV.L @ERs+,ERd
MOV.L @aa:16,ERd
MOV.L @aa:32,ERd
MOV.L ERs,@ERd
MOV.L ERs,@(d:16,ERd)
MOV.L ERs,@(d:32,ERd)
MOV.L ERs,@-ERd
MOV.L ERs,@aa:16
MOV.L ERs,@aa:32
POP.W Rn
POP.L ERn
PUSH.W Rn
PUSH.L ERn
LDM @SP+,(ERm-ERn)
STM (ERm-ERn),@-SP
MOVFPE @aa:16,Rd
MOVTPE Rs,@aa:16
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
W
W
W
W
W
W
W
W
W
W
W
W
W
W
L
L
L
L
L
L
L
L
L
L
L
L
L
L
W
L
W
L
L
L
2
4
6
2
2
2
2
2
2
2
4
4
4
8
4
8
4
8
4
8
6
10
6
10
2
2
2
2
4
4
2
4
6
2
4
6
4
6
4
6
6
8
6
8
MOV
POP
PUSH
LDM
STM
MOVFPE
MOVTPE
Mnemonic
Size
Addressing Mode and Instruction Length (Bytes)
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
#xx:8→Rd8
Rs8→Rd8
@ERs→Rd8
@(d:16,ERs)→Rd8
@(d:32,ERs)→Rd8
@ERs→Rd8,ERs32+1→ERs32
@aa:8→Rd8
@aa:16→Rd8
@aa:32→Rd8
Rs8→@ERd
Rs8→@(d:16,ERd)
Rs8→@(d:32,ERd)
ERd32-1→ERd32,Rs8→@ERd
Rs8→@aa:8
Rs8→@aa:16
Rs8→@aa:32
#xx:16→Rd16
Rs16→Rd16
@ERs→Rd16
@(d:16,ERs)→Rd16
@(d:32,ERs)→Rd16
@ERs→Rd16,ERs32+2→ERs32
@aa:16→Rd16
@aa:32→Rd16
Rs16→@ERd
Rs16→@(d:16,ERd)
Rs16→@(d:32,ERd)
ERd32-2→ERd32,Rs16→@ERd
Rs16→@aa:16
Rs16→@aa:32
#xx:32→ERd32
ERs32→ERd32
@ERs→ERd32
@(d:16,ERs)→ERd32
@(d:32,ERs)→ERd32
@ERs→ERd32,ERs32+4→ERs32
@aa:16→ERd32
@aa:32→ERd32
ERs32→@ERd
ERs32→@(d:16,ERd)
ERs32→@(d:32,ERd)
ERd32-4→ERd32,ERs32→@ERd
ERs32→@aa:16
ERs32→@aa:32
@SP→Rn16,SP+2→SP
@SP→ERn32,SP+4→SP
SP-2→SP,Rn16→@SP
SP-4→SP,ERn32→@SP
(@SP→ERn32,SP+4→SP)
Repeat for the number of returns
(SP-4→SP,ERn32→@SP)
Repeat for the number of returns
Operation Condition
Code
No of
Execution
States
*1
IHNZVC
Advanced Mode
2
4
2
4
4
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
1
1
2
3
5
3
2
3
4
2
3
5
3
2
3
4
2
1
2
3
5
3
3
4
2
3
5
3
3
4
3
1
4
5
7
5
5
6
4
5
7
5
5
6
3
5
3
5
7/9/11 [1]
7/9/11 [1]
[2]
[2]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Cannot be used in this LSI
—
—
—
—
—
Rev. 1.0, 02/ 00, page 926 of 1141
Tabl e A.2 Arithm e t i c Inst r ucti o ns
ADD.B #xx:8,Rd
ADD.B Rs,Rd
ADD.W #xx:16,Rd
ADD.W Rs,Rd
ADD.L #xx:32,ERd
ADD.L ERs,ERd
ADDX #xx:8,Rd
ADDX Rs,Rd
ADDS #1,ERd
ADDS #2,ERd
ADDS #4,ERd
INC.B Rd
INC.W #1,Rd
INC.W #2,Rd
INC.L #1,ERd
INC.L #2,ERd
DAA Rd
SUB.B Rs,Rd
SUB.W #xx:16,Rd
SUB.W Rs,Rd
SUB.L #xx:32,ERd
SUB.L ERs,ERd
SUBX #xx:8,Rd
SUBX Rs,Rd
SUBS #1,ERd
SUBS #2,ERd
SUBS #4,ERd
DEC.B Rd
DEC.W #1,Rd
DEC.W #2,Rd
DEC.L #1,ERd
DEC.L #2,ERd
DAS Rd
MULXU.B Rs,Rd
MULXU.W Rs,ERd
MULXS.B Rs,Rd
MULXS.W Rs,ERd
DIVXU.B Rs,Rd
DIVXU.W Rs,ERd
DIVXS.B Rs,Rd
DIVXS.W Rs,ERd
CMP.B #xx:8,Rd
CMP.B Rs,Rd
CMP.W #xx:16,Rd
CMP.W Rs,Rd
CMP.L #xx:32,ERd
CMP.L ERs,ERd
NEG.B Rd
NEG.W Rd
NEG.L ERd
EXTU.W Rd
EXTU.L ERd
EXTS.W Rd
EXTS.L ERd
TAS @ERd
MAC @ERn+,@ERm+
CLRMAC
LDMAC ERs,MACH
LDMAC ERs,MACL
STMAC MACH,ERd
STMAC MACL,ERd
B
B
W
W
L
L
B
B
L
L
L
B
W
W
L
L
B
B
W
W
L
L
B
B
L
L
L
B
W
W
L
L
B
B
W
B
W
B
W
B
W
B
B
W
W
L
L
B
W
L
W
L
W
L
B
2
4
6
2
4
6
2
2
4
6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
2
2
4
4
2
2
2
2
2
2
2
2
2
2
ADD
ADDX
ADDS
INC
DAA
SUB
SUBX
SUBS
DEC
DAS
MULXU
MULXS
DIVXU
DIVXS
CMP
NEG
EXTU
EXTS
TAS
MAC
CLRMAC
LDMAC
STMAC
Mnemonic Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Rd8+#xx:8→Rd8
Rd8+Rs8→Rd8
Rd16+#xx:16→Rd16
Rd16+Rs16→Rd16
ERd32+#xx:32→ERd32
ERd32+ERs32→ERd32
Rd8+#xx:8+C→Rd8
Rd8+Rs8+C→Rd8
ERd32+1→ERd32
ERd32+2→ERd32
ERd32+4→ERd32
Rd8+1→Rd8
Rd16+1→Rd16
Rd16+2→Rd16
ERd32+1→ERd32
ERd32+2→ERd32
Rd8 10 Decimal adjust →Rd8
Rd8-Rs8→Rd8
Rd16-#xx:16→Rd16
Rd16-Rs16→Rd16
ERd32-#xx:32→ERd32
ERd32-ERs32→ERd32
Rd8-#xx:8-C→Rd8
Rd8-Rs8-C→Rd8
ERd32-1→ERd32
ERd32-2→ERd32
ERd32-4→ERd32
Rd8-1→Rd8
Rd16-1→Rd16
Rd16-2→Rd16
ERd32-1→ERd32
ERd32-2→ERd32
Rd8 10 Decimal adjust →Rd8
Rd8×Rs8→Rd16(Multiplication w/o sign)
Rd16×Rs16→ERd32
(Multiplication w/o sign)
Rd8×Rs8→Rd16(Multiplication w/o sign)
Rd16×Rs16→ERd32
(Multiplication w/o sign)
Rd16÷Rs8→Rd16 (RdH: Remainder, RdL:
Quatient)(Division w/o sign)
ERd32÷Rs16→ERd32 (Ed:Remainder,
Rd: Quatient)(Division with sign)
Rd16÷Rs8→Rd16(RdH: Remainder, RdL:
Quatient)(Division w/o sign)
ERd32÷Rs16→ERd32 (Ed:Remainder,
Rd: Quatient)(Division with sign)
Rd8-#xx:8
Rd8-Rs8
Rd16-#xx:16
Rd16-Rs16
ERd32-#xx:32
ERd32-ERs32
0-Rd8→Rd8
0-Rd16→Rd16
0-ERd32→ERd32
0→(<Bits 15 to 8> of Rd16)
0→(<Bits 31 to 16> of ERd32)
(<Bit7> of Rd16)→
(<Bits 15 to 8> of Rd16)
(<Bit15> of ERd32) →
(<Bits31 to 16> of ERd32)
@ERd-0→CCR set, (1)→
(<Bit7> of @ERd)
Operation Condition
Code
IHNZVC Advanced Mode
4
—
—
—
*
1
1
2
1
3
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
3
1
1
1
1
1
1
1
1
1
1
1
1
12
20
13
21
12
20
13
21
1
1
2
1
3
1
1
1
1
1
1
1
1
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
[3]
[3]
[4]
[4]
—
—
—
—
—
—
—
—
*
[3]
[3]
[4]
[4]
—
—
—
—
—
—
—
—
*
—
—
—
—
—
—
—
—
[3]
[3]
[4]
[4]
—
—
—
—
—
—
—
—
—
—
—
—
—
[6]
[6]
[8]
[8]
0
0
[5]
[5]
—
—
—
[5]
[5]
—
—
—
—
—
[7]
[7]
[7]
[7]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
*
—
—
—
—
—
—
—
—
0
0
0
0
0
—
—
—
—
—
Cannot be used in this LSI [2]
Addressing Mode and Instruction Length (Bytes)
No of
Execution
States
*1
Rev. 1.0, 02/ 00, page 927 of 1141
Tabl e A.3 Log i c O pe r a t i o ns Instruc tions
AND.B #xx:8,Rd
AND.B Rs,Rd
AND.W #xx:16,Rd
AND.W Rs,Rd
AND.L #xx:32,ERd
AND.L ERs,ERd
OR.B #xx:8,Rd
OR.B Rs,Rd
OR.W #xx:16,Rd
OR.W Rs,Rd
OR.L #xx:32,ERd
OR.L ERs,ERd
XOR.B #xx:8,Rd
XOR.B Rs,Rd
XOR.W #xx:16,Rd
XOR.W Rs,Rd
XOR.L #xx:32,ERd
XOR.L ERs,ERd
NOT.B Rd
NOT.W Rd
NOT.L ERd
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
W
L
2
4
6
2
4
6
2
4
6
2
2
4
2
2
4
2
2
4
2
2
2
AND
OR
XOR
NOT
Mnemonic
Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Rd8∧#xx:8→Rd8
Rd8∧Rs8→Rd8
Rd16∧#xx:16→Rd16
Rd16∧Rs16→Rd16
ERd32∧#xx:32→ERd32
ERd32∧ERs32→ERd32
Rd8∨#xx:8→Rd8
Rd8∨Rs8→Rd8
Rd16∨#xx:16→Rd16
Rd16∨Rs16→Rd16
ERd32∨#xx:32→ERd32
ERd32∨ERs32→ERd32
Rd8⊕#xx:8→Rd8
Rd8⊕Rs8→Rd8
Rd16⊕#xx:16→Rd16
Rd16⊕Rs16→Rd16
ERd32⊕#xx:32→ERd32
ERd32⊕ERs32→ERd32
~Rd8→Rd8
~Rd16→Rd16
~ERd32→ERd32
Operation Condition
Code
IHNZVC
Advanced Mode
1
1
2
1
3
2
1
1
2
1
3
2
1
1
2
1
3
2
1
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Addressing Mode and Instruction Length (Bytes)
No of
Execution
States
*1
Rev. 1.0, 02/ 00, page 928 of 1141
Tabl e A.4 Shif t Instruc tions
SHAL.B Rd
SHAL.B #2,Rd
SHAL.W Rd
SHAL.W #2,Rd
SHAL.L ERd
SHAL.L #2,ERd
SHAR.B Rd
SHAR.B #2,Rd
SHAR.W Rd
SHAR.W #2,Rd
SHAR.L ERd
SHAR.L #2,ERd
SHLL.B Rd
SHLL.B #2,Rd
SHLL.W Rd
SHLL.W #2,Rd
SHLL.L ERd
SHLL.L #2,ERd
SHLR.B Rd
SHLR.B #2,Rd
SHLR.W Rd
SHLR.W #2,Rd
SHLR.L ERd
SHLR.L #2,ERd
ROTXL.B Rd
ROTXL.B #2,Rd
ROTXL.W Rd
ROTXL.W #2,Rd
ROTXL.L ERd
ROTXL.L #2,ERd
ROTXR.B Rd
ROTXR.B #2,Rd
ROTXR.W Rd
ROTXR.W #2,Rd
ROTXR.L ERd
ROTXR.L #2,ERd
ROTL.B Rd
ROTL.B #2,Rd
ROTL.W Rd
ROTL.W #2,Rd
ROTL.L ERd
ROTL.L #2,ERd
ROTR.B Rd
ROTR.B #2,Rd
ROTR.W Rd
ROTR.W #2,Rd
ROTR.L ERd
ROTR.L #2,ERd
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
SHAL
SHAR
SHLL
SHLR
ROTXL
ROTXR
ROTL
ROTR
Mnemonic
Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation Condition
Code
IHNZVC
Advanced Mode
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
C
0
MSB LSB
CMSB LSB
CMSB LSB
C
MSB LSB
C
MSB LSB
C
0
MSB LSB
C
0
MSB LSB
C
MSB LSB
Addressing Mode and Instruction Length (Bytes)
No of
Execution
States
*1
Rev. 1.0, 02/ 00, page 929 of 1141
Tabl e A.5 Bi t M a ni pul a t i o n Instruc tions
BSET #xx:3,Rd
BSET #xx:3,@ERd
BSET #xx:3,@aa:8
BSET #xx:3,@aa:16
BSET #xx:3,@aa:32
BSET Rn,Rd
BSET Rn,@ERd
BSET Rn,@aa:8
BSET Rn,@aa:16
BSET Rn,@aa:32
BCLR #xx:3,Rd
BCLR #xx:3,@ERd
BCLR #xx:3,@aa:8
BCLR #xx:3,@aa:16
BCLR #xx:3,@aa:32
BCLR Rn,Rd
BCLR Rn,@ERd
BCLR Rn,@aa:8
BCLR Rn,@aa:16
BCLR Rn,@aa:32
BNOT #xx:3,Rd
BNOT #xx:3,@ERd
BNOT #xx:3,@aa:8
BNOT #xx:3,@aa:16
BNOT #xx:3,@aa:32
BNOT Rn,Rd
BNOT Rn,@ERd
BNOT Rn,@aa:8
BNOT Rn,@aa:16
BNOT Rn,@aa:32
BTST #xx:3,Rd
BTST #xx:3,@ERd
BTST #xx:3,@aa:8
BTST #xx:3,@aa:16
BTST #xx:3,@aa:32
BTST Rn,Rd
BTST Rn,@ERd
BTST Rn,@aa:8
BTST Rn,@aa:16
BTST Rn,@aa:32
BLD #xx:3,Rd
BLD #xx:3,@ERd
BLD #xx:3,@aa:8
BLD #xx:3,@aa:16
BLD #xx:3,@aa:32
BILD #xx:3,Rd
BILD #xx:3,@ERd
BILD #xx:3,@aa:8
BILD #xx:3,@aa:16
BILD #xx:3,@aa:32
BST #xx:3,Rd
BST #xx:3,@ERd
BST #xx:3,@aa:8
BST #xx:3,@aa:16
BST #xx:3,@aa:32
BIST #xx:3,Rd
BIST #xx:3,@ERd
BIST #xx:3,@aa:8
BIST #xx:3,@aa:16
BIST #xx:3,@aa:32
BAND #xx:3,Rd
BAND #xx:3,@ERd
BAND #xx:3,@aa:8
BAND #xx:3,@aa:16
BAND #xx:3,@aa:32
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
BSET
BCLR
BNOT
BTST
BLD
BILD
BST
BIST
BAND
Mnemonic
Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
(#xx:3 of Rd8)←1
(#xx:3 of @ERd)←1
(#xx:3 of @aa:8)←1
(#xx:3 of @aa:16)←1
(#xx:3 of @aa:32)←1
(Rn8 of Rd8)←1
(Rn8 of @ERd)←1
(Rn8 of @aa:8)←1
(Rn8 of @aa:16)←1
(Rn8 of @aa:32)←1
(#xx:3 of Rd8)←0
(#xx:3 of @ERd)←0
(#xx:3 of @aa:8)←0
(#xx:3 of @aa:16)←0
(#xx:3 of @aa:32)←0
(Rn8 of Rd8)←0
(Rn8 of @ERd)←0
(Rn8 of @aa:8)←0
(Rn8 of @aa:16)←0
(Rn8 of @aa:32)←0
(#xx:3 of Rd8)←[~(#xx:3 of Rd8)]
(#xx:3 of @ERd)←[~(#xx:3 of @ERd)]
(#xx:3 of @aa:8)←[~(#xx:3 of @aa:8)]
(#xx:3 of @aa:16)←[~(#xx:3 of @aa:16)]
(#xx:3 of @aa:32)←[~(#xx:3 of @aa:32)]
(Rn8 of Rd8)←[~(Rn8 of Rd8)]
(Rn8 of @ERd)←[~(Rn8 of @ERd)]
(Rn8 of @aa:8)←[~(Rn8 of @aa:8)]
(Rn8 of @aa:16)←[~(Rn8 of @aa:16)]
(Rn8 of @aa:32)←[~(Rn8 of @aa:32)]
~(#xx:3 of Rd8)→Z
~(#xx:3 of @ERd)→Z
~(#xx:3 of @aa:8)→Z
~(#xx:3 of @aa:16)→Z
~(#xx:3 of @aa:32)→Z
~(Rn8 of Rd8)→Z
~(Rn8 of @ERd)→Z
~(Rn8 of @aa:8)→Z
~(Rn8 of @aa:16)→Z
~(Rn8 of @aa:32)→Z
(#xx:3 of Rd8)→C
(#xx:3 of @ERd)→C
(#xx:3 of @aa:8)→C
(#xx:3 of @aa:16)→C
(#xx:3 of @aa:32)→C
~(#xx:3 of Rd8)→C
~(#xx:3 of @ERd)→C
~(#xx:3 of @aa:8)→C
~(#xx:3 of @aa:16)→C
~(#xx:3 of @aa:32)→C
C→(#xx:3 of Rd8)
C→(#xx:3 of @ERd)
C→(#xx:3 of @aa:8)
C→(#xx:3 of @aa:16)
C→(#xx:3 of @aa:32)
~C→(#xx:3 of Rd8)
~C→(#xx:3 of @ERd)
~C→(#xx:3 of @aa:8)
~C→(#xx:3 of @aa:16)
~C→(#xx:3 of @aa:32)
C
∧
(#xx:3 of Rd8)→C
C
∧
(#xx:3 of @ERd)→C
C
∧
(#xx:3 of @aa:8)→C
C
∧
(#xx:3 of @aa:16)→C
C
∧
(#xx:3 of @aa:32)→C
Operation Condition
Code
IHNZVC
Advanced Mode
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
4
4
5
6
1
4
4
5
6
1
4
4
5
6
1
4
4
5
6
1
4
4
5
6
1
4
4
5
6
1
3
3
4
5
1
3
3
4
5
1
3
3
4
5
1
3
3
4
5
1
4
4
5
6
1
4
4
5
6
1
3
3
4
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Addressing Mode and Instruction Length (Bytes)
No of
Execution
States
*1
Rev. 1.0, 02/ 00, page 930 of 1141
BIAND #xx:3,Rd
BIAND #xx:3,@ERd
BIAND #xx:3,@aa:8
BIAND #xx:3,@aa:16
BIAND #xx:3,@aa:32
BOR #xx:3,Rd
BOR #xx:3,@ERd
BOR #xx:3,@aa:8
BOR #xx:3,@aa:16
BOR #xx:3,@aa:32
BIOR #xx:3,Rd
BIOR #xx:3,@ERd
BIOR #xx:3,@aa:8
BIOR #xx:3,@aa:16
BIOR #xx:3,@aa:32
BXOR #xx:3,Rd
BXOR #xx:3,@ERd
BXOR #xx:3,@aa:8
BXOR #xx:3,@aa:16
BXOR #xx:3,@aa:32
BIXOR #xx:3,Rd
BIXOR #xx:3,@ERd
BIXOR #xx:3,@aa:8
BIXOR #xx:3,@aa:16
BIXOR #xx:3,@aa:32
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
BIAND
BOR
BIOR
BXOR
BIXOR
Mnemonic
Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
C∧ [~(#xx:3 of Rd8)]→C
C∧ [~(#xx:3 of @ERd)]→C
C∧ [~(#xx:3 of @aa:8)]→C
C∧ [~(#xx:3 of @aa:16)]→C
C∧ [~(#xx:3 of @aa:32)]→C
C∨(#xx:3 of Rd8)→C
C∨(#xx:3 of @ERd)→C
C∨(#xx:3 of @aa:8)→C
C∨(#xx:3 of @aa:16)→C
C∨(#xx:3 of @aa:32)→C
C∨ [~(#xx:3 of Rd8)]→C
C∨ [~(#xx:3 of @ERd)]→C
C∨ [~(#xx:3 of @aa:8)]→C
C∨ [~(#xx:3 of @aa:16)]→C
C∨ [~(#xx:3 of @aa:32)]→C
C⊕ (#xx:3 of Rd8)→C
C⊕ (#xx:3 of @ERd)→C
C⊕ (#xx:3 of @aa:8)→C
C⊕ (#xx:3 of @aa:16)→C
C⊕ (#xx:3 of @aa:32)→C
C⊕ [~(#xx:3 of Rd8)]→C
C⊕ [~(#xx:3 of @ERd)]→C
C⊕ [~(#xx:3 of @aa:8)]→C
C⊕ [~(#xx:3 of @aa:16)]→C
C⊕ [~(#xx:3 of @aa:32)]→C
Operation
IHNZVC
Advanced Mode
2
2
2
2
2
4
4
4
4
4
4
6
8
4
6
8
4
6
8
4
6
8
4
6
8
1
3
3
4
5
1
3
3
4
5
1
3
3
4
5
1
3
3
4
5
1
3
3
4
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Condition
Code
Addressing Mode and Instruction Length (Bytes)
No of
Execution
States
*1
Rev. 1.0, 02/ 00, page 931 of 1141
Tabl e A.6 Br a nc h Inst r uc t i o ns
BRA d:8(BT d:8)
BRA d:16(BT d:16)
BRN d:8(BF d:8)
BRN d:16(BF d:16)
BHI d:8
BHI d:16
BLS d:8
BLS d:16
BCC d:8(BHS d:8)
BCC d:16(BHS d:16)
BCS d:8(BLO d:8)
BCS d:16(BLO d:16)
BNE d:8
BNE d:16
BEQ d:8
BEQ d:16
BVC d:8
BVC d:16
BVS d:8
BVS d:16
BPL d:8
BPL d:16
BMI d:8
BMI d:16
BGE d:8
BGE d:16
BLT d:8
BLT d:16
Bcc
Mnemonic
Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation
I
Branch
Condition
HNZVC
Advanced Mode
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
Always
Never
C∨Z=0
C∨Z=1
C=0
C=1
Z=0
Z=1
V=0
V=1
N=0
N=1
N⊕V=0
N⊕V=1
if condition is true then
PC←PC+d
else next;
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Operation
Code
BGT d:8
BGT d:16
BLE d:8
BLE d:16
JMP @ERn
JMP @aa:24
JMP @@aa:8
BSR d:8
BSR d:16
JSR @ERn
JSR @aa:24
JSR @@aa:8
RTS
JMP
BSR
JSR
RTS
PC←ERn
PC←aa:24
PC←@aa:8
PC→@-SP,PC←PC+d:8
PC→@-SP,PC←PC+d:16
PC→@-SP,PC←ERn
PC→@-SP,PC←aa:24
PC→@-SP,PC←@aa:8
PC←@SP+
2
2
4
4
2
4
2
4
2
4
2
22
2
3
2
3
2
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Z∨(N⊕V)=0
Z∨(N⊕V)=1
5
4
5
4
5
6
5
Addressing Mode and Instruction Length (Bytes)
No of
Execution
States
*1
Rev. 1.0, 02/ 00, page 932 of 1141
Tabl e A.7 System Co ntrol Inst r ucti o ns
TRAPA #x:2
RTE
SLEEP
LDC #xx:8,CCR
LDC #xx:8,EXR
LDC Rs,CCR
LDC Rs,EXR
LDC @ERs,CCR
LDC @ERs,EXR
LDC @(d:16,ERs),CCR
LDC @(d:16,ERs),EXR
LDC @(d:32,ERs),CCR
LDC @(d:32,ERs),EXR
LDC @ERs+,CCR
LDC @ERs+,EXR
LDC @aa:16,CCR
LDC @aa:16,EXR
LDC @aa:32,CCR
LDC @aa:32,EXR
STC.B CCR,Rd
STC.B EXR,Rd
STC.W CCR,@ERd
STC.W EXR,@ERd
STC.W CCR,@(d:16,ERd)
STC.W EXR,@(d:16,ERd)
STC.W CCR,@(d:32,ERd)
STC.W EXR,@(d:32,ERd)
STC.W CCR,@-ERd
STC.W EXR,@-ERd
STC.W CCR,@aa:16
STC.W EXR,@aa:16
STC.W CCR,@aa:32
STC.W EXR,@aa:32
ANDC #xx:8,CCR
ANDC #xx:8,EXR
ORC #xx:8,CCR
ORC #xx:8,EXR
XORC #xx:8,CCR
XORC #xx:8,EXR
NOP
—
—
—
B
B
B
B
W
W
W
W
W
W
W
W
W
W
W
W
B
B
W
W
W
W
W
W
W
W
W
W
W
W
B
B
B
B
B
B
—
TRAPA
RTE
SLEEP
LDC
STC
ANDC
ORC
XORC
NOP
Mnemonic
Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
PC→@-SP,CCR→@-SP,
EXR→@-SP,<Vector>→PC
EXR←@SP+,CCR←@SP+,
PC←@SP+
Transition to power-down state
#xx:8→CCR
#xx:8→EXR
Rs8→CCR
Rs8→EXR
@ERs→CCR
@ERs→EXR
@(d:16,ERs)→CCR
@(d:16,ERs)→EXR
@(d:32,ERs)→CCR
@(d:32,ERs)→EXR
@ERs→CCR,ERs32+2→ERs32
@ERs→EXR,ERs32+2→ERs32
@aa:16→CCR
@aa:16→EXR
@aa:32→CCR
@aa:32→EXR
CCR→Rd8
EXR→Rd8
CCR→@ERd
EXR→@ERd
CCR→@(d:16,ERd)
EXR→@(d:16,ERd)
CCR→@(d:32,ERd)
EXR→@(d:32,ERd)
ERd32-2→ERd32,CCR→@ERd
ERd32-2→ERd32,EXR→@ERd
CCR→@aa:16
EXR→@aa:16
CCR→@aa:32
EXR→@aa:32
CCR∧#xx:8→CCR
EXR∧ #xx:8→EXR
CCR∨#xx:8→CCR
EXR∨#xx:8→EXR
CCR⊕#xx:8→CCR
EXR⊕#xx:8→EXR
PC←PC+2
Operation
IHNZVC
Advanced Mode
2
4
2
4
2
4
2
4
2
2
2
2
4
4
4
4
6
6
10
10
6
6
10
10
4
4
4
4
6
6
8
8
6
6
8
8
2
5 [9]
2
1
2
1
1
3
3
4
4
6
6
4
4
4
4
5
5
1
1
3
3
4
4
6
6
4
4
4
4
5
5
1
2
1
2
1
2
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8 [9]
Condition
Code
Addressing Mode and Instruction Length (Bytes)
No of
Execution
States
*1
Rev. 1.0, 02/ 00, page 933 of 1141
Tabl e A.8 Bl o c k T r a nsfer Instruc tions
EEPMOV.B
EEPMOV.W
—
—
EEPMOV
Mnemonic Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
—
Operation
IHNZVC Advanced Mode
4
4
4+2n *2
4+2n *2
—
—
—
—
—
—
—
—
—
—
—
—
Condition
Code
if R4L≠0
Repeat @ER5→@ER6
ER5+1→ER5
ER6+1→ER6
R4L-1→R4L
Until R4L=0
else next;
if R4≠0
Repeat @ER5→@ER6
ER5+1→ER5
ER6+1→ER6
R4-1→R4
Until R4=0
else next;
Addressing Mode and Instruction Length (Bytes)
No of
Execution
States
*1
Notes: 1. The values indicated in the column of number of execut ion st at es apply when
instruction code and oper and exist in the on- chip mem or y.
2. n is t he initial setting value of R4L or R4.
[1] 7 states when the num ber of r et ur n/ r etract r egister s is 2, 9 st at es when the num ber
of regist er s is 3, and 11 st at es when t he num ber of r egister s is 4.
[2] Cannot be used in this LSI.
[3] Set to 1 when a carry or bor r ow occur s at bit 11, ot her wise cleared to 0.
[4] Set to 1 when a carry or bor r ow occur s at bit 27, ot her wise cleared to 0.
[5] Retains the value before com put at ion when the com put at ion result is 0, ot her wise
cleared to 0.
[6] Set to 1 when the divisor is negative, ot her wise cleared to 0.
[7] Set to 1 when the divisor is 0, ot her wise cleared to 0.
[8] Set to 1 when the quot ient is negat ive, ot her wise cleared to 0.
[9] 1 is added to the number of execut ion st at es when EXR is valid.
Rev. 1.0, 02/ 00, page 934 of 1141
A.2 Instruction Codes
Table A.9 Instruction Codes
ADD
ADDS
ADDX
AND
ANDC
BAND
Bcc
ADD.B #xx:8,Rd
ADD.B Rs,Rd
ADD.W #xx:16,Rd
ADD.W Rs,Rd
ADD.L #xx:32,ERd
ADD.L ERs,ERd
ADDS #1,ERd
ADDS #2,ERd
ADDS #4,ERd
ADDX #xx:8,Rd
ADDX Rs,Rd
AND.B #xx:8,Rd
AND.B Rs,Rd
AND.W #xx:16,Rd
AND.W Rs,Rd
AND.L #xx:32,ERd
AND.L ERs,ERd
ANDC #xx:8,CCR
ANDC #xx:8,EXR
BAND #xx:3,Rd
BAND #xx:3,@ERd
BAND #xx:3,@aa:8
BAND #xx:3,@aa:16
BAND #xx:3,@aa:32
BRA d:8 (BT d:8)
BRA d:16 (BT d:16)
BRN d:8 (BF d:8)
BRN d:16 (BF d:16)
BHI d:8
BHI d:16
BLS d:8
BLS d:16
BCC d:8 (BHS d:8)
BCC d:16 (BHS d:16)
BCS d:8 (BLO d:8)
BCS d:16 (BLO d:16)
BNE d:8
BNE d:16
BEQ d:8
BEQ d:16
BVC d:8
BVC d:16
BVS d:8
BVS d:16
Mnemonic Instruction Format
1st byte
B
B
W
W
L
L
L
L
L
B
B
B
B
W
W
L
L
B
B
B
B
B
B
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
0
7
0
7
0
0
0
0
9
0
E
1
7
6
7
0
0
0
7
7
7
6
6
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
rd
8
9
9
A
A
B
B
B
rd
E
rd
6
9
6
A
1
6
1
6
C
E
A
A
0
8
1
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
9
8
rs
1
rs
1
1 ers
0
8
9
rs
rs
6
rs
6
F
4
0 IMM
0 erd
1
3
0
1
2
3
4
5
6
7
8
9
IMM
IMM
IMM
IMM
abs
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
rd
rd
rd
0 erd
0 erd
0 erd
0 erd
0 erd
rd
rd
rd
rd
0 erd
0
1
rd
0
0
0
0
0
0
0
0
0
0
0
0
0
0 IMM
0 IMM 0
0
6
0
7
7
IMM
IMM
abs
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
IMM
IMM
abs
6
6
6
6 0 IMM 0
7
6
0 IMM 0
7
6
2nd byte 3rd byte 4th byte 5th byte 6th byte 7the byte 8th byte 9th byte 10th byte
Size
Instruction
0 ers 0 erd
IMM
Rev. 1.0, 02/ 00, page 935 of 1141
Bcc
(Cont.)
BCLR
BIAND
BILD
BIOR
BIST
BPL d:8
BPL d:16
BMI d:8
BMI d:16
BGE d:8
BGE d:16
BLT d:8
BLT d:16
BGT d:8
BGT d:16
BLE d:8
BLE d:16
BCLR #xx:3,Rd
BCLR #xx:3,@ERd
BCLR #xx:3,@aa:8
BCLR #xx:3,@aa:16
BCLR #xx:3,@aa:32
BCLR Rn,Rd
BCLR Rn,@ERd
BCLR Rn,@aa:8
BCLR Rn,@aa:16
BCLR Rn,@aa:32
BIAND #xx:3,Rd
BIAND #xx:3,@ERd
BIAND #xx:3,@aa:8
BIAND #xx:3,@aa:16
BIAND #xx:3,@aa:32
BILD #xx:3,Rd
BILD #xx:3,@ERd
BILD #xx:3,@aa:8
BILD #xx:3,@aa:16
BILD #xx:3,@aa:32
BIOR #xx:3,Rd
BIOR #xx:3,@ERd
BIOR #xx:3,@aa:8
BIOR #xx:3,@aa:16
BIOR #xx:3,@aa:32
BIST #xx:3,Rd
BIST #xx:3,@ERd
BIST #xx:3,@aa:8
BIST #xx:3,@aa:16
BIST #xx:3,@aa:32
Mnemonic Instruction Format
1st byte
—
—
—
—
—
—
—
—
—
—
—
—
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
4
5
4
5
4
5
4
5
4
5
4
5
7
7
7
6
6
6
7
7
6
6
7
7
7
6
6
7
7
7
6
6
7
7
7
6
6
6
7
7
6
6
A
8
B
8
C
8
D
8
E
8
F
8
2
D
F
A
A
2
D
F
A
A
6
C
E
A
A
7
C
E
A
A
4
C
E
A
A
7
D
F
A
A
A
B
C
D
E
F
0 IMM
0 erd
1
3
rn
0 erd
1
3
1 IMM
0 erd
1
3
1 IMM
0 erd
1
3
1 IMM
0 erd
1
3
1 IMM
0 erd
1
3
disp
disp
disp
disp
disp
disp
abs
abs
abs
abs
abs
abs
0
0
0
0
0
0
rd
0
8
8
rd
0
8
8
rd
0
0
0
rd
0
0
0
rd
0
0
0
rd
0
8
8
7
7
6
6
7
7
7
7
7
7
6
6
disp
disp
disp
disp
disp
disp
2
2
abs
2
2
abs
6
6
abs
7
7
abs
4
4
abs
7
7
abs
0 IMM
0 IMM
rn
rn
1 IMM
1 IMM
1 IMM
1 IMM
1 IMM
1 IMM
1 IMM
1 IMM
0
0
abs
0
0
abs
0
0
abs
0
0
abs
0
0
abs
0
0
abs
7
6
7
7
7
6
2
2
6
7
4
7
0 IMM
rn
1 IMM
1 IMM
1 IMM
1 IMM
0
0
0
0
0
0
7
6
7
7
7
6
2
2
6
7
4
7
0 IMM
rn
1 IMM
1 IMM
1 IMM
1 IMM
0
0
0
0
0
0
2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Size
Instruction
Rev. 1.0, 02/ 00, page 936 of 1141
BIXOR
BLD
BNOT
BOR
BSET
BSR
BST
BIXOR #xx:3,Rd
BIXOR #xx:3,@ERd
BIXOR #xx:3,@aa:8
BIXOR #xx:3,@aa:16
BIXOR #xx:3,@aa:32
BLD #xx:3,Rd
BLD #xx:3,@ERd
BLD #xx:3,@aa:8
BLD #xx:3,@aa:16
BLD #xx:3,@aa:32
BNOT #xx:3,Rd
BNOT #xx:3,@ERd
BNOT #xx:3,@aa:8
BNOT #xx:3,@aa:16
BNOT #xx:3,@aa:32
BNOT Rn,Rd
BNOT Rn,@ERd
BNOT Rn,@aa:8
BNOT Rn,@aa:16
BNOT Rn,@aa:32
BOR #xx:3,Rd
BOR #xx:3,@ERd
BOR #xx:3,@aa:8
BOR #xx:3,@aa:16
BOR #xx:3,@aa:32
BSET #xx:3,Rd
BSET #xx:3,@ERd
BSET #xx:3,@aa:8
BSET #xx:3,@aa:16
BSET #xx:3,@aa:32
BSET Rn,Rd
BSET Rn,@ERd
BSET Rn,@aa:8
BSET Rn,@aa:16
BSET Rn,@aa:32
BSR d:8
BSR d:16
BST #xx:3,Rd
BST #xx:3,@ERd
BST #xx:3,@aa:8
BST #xx:3,@aa:16
BST #xx:3,@aa:32
Mnemonic Instruction Format
1st byte
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
—
—
B
B
B
B
B
7
7
7
6
6
7
7
7
6
6
7
7
7
6
6
6
7
7
6
6
7
7
7
6
6
7
7
7
6
6
6
7
7
6
6
5
5
6
7
7
6
6
5
C
E
A
A
7
C
E
A
A
1
D
F
A
A
1
D
F
A
A
4
C
E
A
A
0
D
F
A
A
0
D
F
A
A
5
C
7
D
F
A
A
1 IMM
0 erd
abs
1
3
0 IMM
0 erd
abs
1
3
0 IMM
0 erd
abs
1
3
rn
0 erd
abs
1
3
0 IMM
0 erd
abs
1
3
0 IMM
0 erd
abs
1
3
rn
0 erd
abs
1
3
disp
0
0 IMM
0 erd
abs
1
3
rd
0
0
0
rd
0
0
0
rd
0
8
8
rd
0
8
8
rd
0
0
0
rd
0
8
8
rd
0
8
8
0
rd
0
8
8
7
7
7
7
7
7
6
6
7
7
7
7
6
6
6
6
5
5
abs
7
7
abs
1
1
abs
1
1
abs
4
4
abs
0
0
abs
0
0
abs
disp
7
7
abs
1 IMM
1 IMM
0 IMM
0 IMM
0 IMM
0 IMM
rn
rn
0 IMM
0 IMM
0 IMM
0 IMM
rn
rn
0 IMM
0 IMM
0
0
abs
0
0
abs
0
0
abs
0
0
abs
0
0
abs
0
0
abs
0
0
abs
0
0
abs
7
7
7
6
7
7
6
6
5
7
1
1
4
0
0
7
1 IMM
0 IMM
0 IMM
rn
0 IMM
0 IMM
rn
0 IMM
0
0
0
0
0
0
0
0
7
7
7
6
7
7
6
6
5
7
1
1
4
0
0
7
1 IMM
0 IMM
0 IMM
rn
0 IMM
0 IMM
rn
0 IMM
0
0
0
0
0
0
0
0
2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Size
Instruction
Rev. 1.0, 02/ 00, page 937 of 1141
BTST
BXOR
CLRMAC
CMP
DAA
DAS
DEC
DIVXS
DIVXU
EEPMOV
EXTS
EXTU
BTST #xx:3,Rd
BTST #xx:3,@ERd
BTST #xx:3,@aa:8
BTST #xx:3,@aa:16
BTST #xx:3,@aa:32
BTST Rn,Rd
BTST Rn,@ERd
BTST Rn,@aa:8
BTST Rn,@aa:16
BTST Rn,@aa:32
BXOR #xx:3,Rd
BXOR #xx:3,@ERd
BXOR #xx:3,@aa:8
BXOR #xx:3,@aa:16
BXOR #xx:3,@aa:32
CLRMAC
CMP.B #xx:8,Rd
CMP.B Rs,Rd
CMP.W #xx:16,Rd
CMP.W Rs,Rd
CMP.L #xx:32,ERd
CMP.L ERs,ERd
DAA Rd
DAS Rd
DEC.B Rd
DEC.W #1,Rd
DEC.W #2,Rd
DEC.L #1,ERd
DEC.L #2,ERd
DIVXS.B Rs,Rd
DIVXS.W Rs,ERd
DIVXU.B Rs,Rd
DIVXU.W Rs,ERd
EEPMOV.B
EEPMOV.W
EXTS.W Rd
EXTS.L ERd
EXTU.W Rd
EXTU.L ERd
Mnemonic Instruction Format
1st byte
Cannot be used in the H8S/2199 Series
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
—
B
B
W
W
L
L
B
B
B
W
W
L
L
B
W
B
W
—
—
W
L
W
L
7
7
7
6
6
6
7
7
6
6
7
7
7
6
6
A
1
7
1
7
1
0
1
1
1
1
1
1
0
0
5
5
7
7
1
1
1
1
3
C
E
A
A
3
C
E
A
A
5
C
E
A
A
rd
C
9
D
A
F
F
F
A
B
B
B
B
1
1
1
3
B
B
7
7
7
7
0 IMM
0 erd
abs
1
3
rn
0 erd
abs
1
3
0 IMM
0 erd
abs
1
3
IMM
rs
2
rs
2
1 ers
0
0
0
5
D
7
F
D
D
rs
rs
5
D
D
F
5
7
rd
0
0
0
rd
0
0
0
rd
0
0
0
rd
rd
rd
0 erd
0 erd
rd
rd
rd
rd
rd
0 erd
0 erd
0
0
rd
0 erd
C
4
rd
0 erd
rd
0 erd
7
7
6
6
7
7
5
5
5
5
3
3
abs
3
3
abs
5
5
abs
IMM
1
3
9
9
0 IMM
0 IMM
rn
rn
0 IMM
0 IMM
rs
rs
8
8
0
0
abs
0
0
abs
0
0
abs
IMM
rd
0 erd
F
F
7
6
7
3
3
5
0 IMM
rn
0 IMM
0
0
0
7
6
7
3
3
5
0 IMM
rn
0 IMM
0
0
0
2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Size
Instruction
Rev. 1.0, 02/ 00, page 938 of 1141
INC
JMP
JSR
LDC
LDM
LDMAC
MAC
MOV
INC.B Rd
INC.W #1,Rd
INC.W #2,Rd
INC.L #1,ERd
INC.L #2,ERd
JMP @ERn
JMP @aa:24
JMP @@aa:8
JSR @ERn
JSR @aa:24
JSR @@aa:8
LDC #xx:8,CCR
LDC #xx:8,EXR
LDC Rs,CCR
LDC Rs,EXR
LDC @ERs,CCR
LDC @ERs,EXR
LDC @(d:16,ERs),CCR
LDC @(d:16,ERs),EXR
LDC @(d:32,ERs),CCR
LDC @(d:32,ERs),EXR
LDC @ERs+,CCR
LDC @ERs+,EXR
LDC @aa:16,CCR
LDC @aa:16,EXR
LDC @aa:32,CCR
LDC @aa:32,EXR
LDM.L @SP+, (ERn-ERn+1)
LDM.L @SP+, (ERn-ERn+2)
LDM.L @SP+, (ERn-ERn+3)
LDMAC ERs,MACH
LDMAC ERs,MACL
MAC @ERn+,@ERm+
MOV.B #xx:8,Rd
MOV.B Rs,Rd
MOV.B @ERs,Rd
MOV.B @(d:16,ERs),Rd
MOV.B @(d:32,ERs),Rd
MOV.B @ERs+,Rd
MOV.B @aa:8,Rd
MOV.B @aa:16,Rd
MOV.B @aa:32,Rd
MOV.B Rs,@ERd
MOV.B Rs,@(d:16,ERd)
MOV.B Rs,@(d:32,ERd)
Mnemonic Instruction Format
Cannot be used in the H8S/2199 Series
1st byte
B
W
W
L
L
—
—
—
—
—
—
B
B
B
B
W
W
W
W
W
W
W
W
W
W
W
W
L
L
L
L
L
—
B
B
B
B
B
B
B
B
B
B
B
B
0
0
0
0
0
5
5
5
5
5
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
0
6
6
7
6
2
6
6
6
6
7
A
B
B
B
B
9
A
B
D
E
F
7
1
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
rd
C
8
E
8
C
rd
A
A
8
E
8
0
5
D
7
F
0 ern
abs
0 ern
abs
IMM
4
0
1
4
4
4
4
4
4
4
4
4
4
4
4
1
2
3
IMM
rs
0 ers
0 ers
0 ers
0 ers
abs
0
2
1 erd
1 erd
0 erd
rd
rd
rd
0 erd
0 erd
0
0
1
rs
rs
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
rd
rd
rd
0
rd
rd
rd
rs
rs
0
abs
abs
0
6
6
6
6
7
7
6
6
6
6
6
6
6
6
6
6
6
7
9
9
F
F
8
8
D
D
B
B
B
B
D
D
D
disp
A
abs
disp
A
IMM
0 ers
0 ers
0 ers
0 ers
0 ers
0 ers
0 ers
0 ers
0
0
2
2
7
7
7
2
A
0
0
0
0
0
0
0
0
0
0
0
0
0 ern+1
0 ern+2
0 ern+3
rd
abs
rs
6
6
disp
disp
B
B
abs
abs
2
2
0
0
abs
abs
disp
disp
disp
disp
2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10 byte
Size
Instruction
Rev. 1.0, 02/ 00, page 939 of 1141
MOV
(Cont.)
MOVFPE
MOVTPE
MULXS
MULXU
NEG
NOP
MOV.B Rs,@-ERd
MOV.B Rs,@aa:8
MOV.B Rs,@aa :16
MOV.B Rs,@aa:32
MOV.W #xx:16,Rd
MOV.W Rs,Rd
MOV.W @ERs,Rd
MOV.W @(d:16,ERs),Rd
MOV.W @(d:32,ERs),Rd
MOV.W @ERs+,Rd
MOV.W @aa:16,Rd
MOV.W @aa:32,Rd
MOV.W Rs,@ERd
MOV.W Rs,@(d:16,ERd)
MOV.W Rs,@(d:32,ERd)
MOV.W Rs,@-ERd
MOV.W Rs,@aa:16
MOV.W Rs,@aa:32
MOV.L #xx:32,Rd
MOV.L ERs,ERd
MOV.L @ERs,ERd
MOV.L @(d:16,ERs),ERd
MOV.L @(d:32,ERs),ERd
MOV.L @ERs+,ERd
MOV.L @aa:16 ,ERd
MOV.L @aa:32 ,ERd
MOV.L ERs,@ERd
MOV.L ERs,@(d:16,ERd)
MOV.L ERs,@(d:32,ERd) *
MOV.L ERs,@-ERd
MOV.L ERs,@aa:16
MOV.L ERs,@aa:32
MOVFPE @aa:16,Rd
MOVTPE Rs,@aa:16
MULXS.B Rs,Rd
MULXS.W Rs,ERd
MULXU.B Rs,Rd
MULXU.W Rs,ERd
NEG.B Rd
NEG.W Rd
NEG.L ERd
NOP
Mnemonic Instruction Format
1st byte
Cannot be used in the H8S/2199 Series
B
B
B
B
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
L
L
L
L
L
L
L
L
L
L
L
L
L
B
B
B
W
B
W
B
W
L
—
6
3
6
6
7
0
6
6
7
6
6
6
6
6
7
6
6
6
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
5
1
1
1
0
C
rs
A
A
9
D
9
F
8
D
B
B
9
F
8
D
B
B
A
F
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
2
7
7
7
0
1 erd
abs
8
A
0
rs
0 ers
0 ers
0 ers
0 ers
0
2
1 erd
1 erd
0 erd
1 erd
8
A
0
1 ers
0
0
0
0
0
0
0
0
0
0
0
0
C
C
rs
rs
8
9
B
0
rs
rs
rs
rd
rd
rd
rd
0
rd
rd
rd
rs
rs
0
rs
rs
rs
0 erd
0 erd
0
0
0
0
0
0
0
0
0
0
0
0
0
0
rd
0 erd
rd
rd
0 erd
0
6
6
6
6
7
6
6
6
6
6
7
6
6
6
5
5
abs
IMM
disp
B
abs
disp
B
abs
9
F
8
D
B
B
9
F
8
D
B
B
0
2
2
A
0 ers
0 ers
0 ers
0 ers
0
2
1 erd
1 erd
0 erd
1 erd
8
A
rs
rs
abs
rd
abs
rs
abs
IMM
0 erd
0 erd
0
0 erd
0 erd
0 erd
0 ers
0 ers
0
0 ers
0 ers
0 ers
rd
0 erd
6
6
disp
B
abs
disp
B
abs
2
A
disp
disp
0 erd
abs
0 ers
abs
disp
disp
2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Size
Instruction
Rev. 1.0, 02/ 00, page 940 of 1141
NOT
OR
ORC
POP
PUSH
ROTL
ROTR
ROTXL
ROTXR
RTE
RTS
NOT.B Rd
NOT.W Rd
NOT.L ERd
OR.B #xx:8,Rd
OR.B Rs,Rd
OR.W #xx:16,Rd
OR.W Rs,Rd
OR.L #xx:32,ERd
OR.L ERs,ERd
ORC #xx:8,CCR
ORC #xx:8,EXR
POP.W Rn
POP.L ERn
PUSH.W Rn
PUSH.L ERn
ROTL.B Rd
ROTL.B #2, Rd
ROTL.W Rd
ROTL.W #2, Rd
ROTL.L ERd
ROTL.L #2, ERd
ROTR.B Rd
ROTR.B #2, Rd
ROTR.W Rd
ROTR.W #2, Rd
ROTR.L ERd
ROTR.L #2, ERd
ROTXL.B Rd
ROTXL.B #2, Rd
ROTXL.W Rd
ROTXL.W #2, Rd
ROTXL.L ERd
ROTXL.L #2, ERd
ROTXR.B Rd
ROTXR.B #2, Rd
ROTXR.W Rd
ROTXR.W #2, Rd
ROTXR.L ERd
ROTXR.L #2, ERd
RTE
RTS
Mnemonic Instruction Format
1st byte
B
W
L
B
B
W
W
L
L
B
B
W
L
W
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
—
—
1
1
1
C
1
7
6
7
0
0
0
6
0
6
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
5
7
7
7
rd
4
9
4
A
1
4
1
D
1
D
1
2
2
2
2
2
2
3
3
3
3
3
3
2
2
2
2
2
2
3
3
3
3
3
3
6
4
0
1
3
IMM
rs
4
rs
4
F
IMM
4
7
0
F
0
8
C
9
D
B
F
8
C
9
D
B
F
0
4
1
5
3
7
0
4
1
5
3
7
7
7
rd
rd
0 erd
rd
rd
rd
0 erd
0
1
rn
0
rn
0
rd
rd
rd
rd
0 erd
0 erd
rd
rd
rd
rd
0 erd
0 erd
rd
rd
rd
rd
0 erd
0 erd
rd
rd
rd
rd
0 erd
0 erd
0
0
6
0
6
6
IMM
4
4
D
D
0 ers
IMM
7
F
IMM
0 erd
0 ern
0 ern
2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Size
Instruction
Rev. 1.0, 02/ 00, page 941 of 1141
SHAL
SHAR
SHLL
SHLR
SLEEP
STC
STM
STMAC
SHAL.B Rd
SHAL.B #2, Rd
SHAL.W Rd
SHAL.W #2, Rd
SHAL.L ERd
SHAL.L #2, ERd
SHAR.B Rd
SHAR.B #2, Rd
SHAR.W Rd
SHAR.W #2, Rd
SHAR.L ERd
SHAR.L #2, ERd
SHLL.B Rd
SHLL.B #2, Rd
SHLL.W Rd
SHLL.W #2, Rd
SHLL.L ERd
SHLL.L #2, ERd
SHLR.B Rd
SHLR.B #2, Rd
SHLR.W Rd
SHLR.W #2, Rd
SHLR.L ERd
SHLR.L #2, ERd
SLEEP
STC.B CCR,Rd
STC.B EXR,Rd
STC.W CCR,@ERd
STC.W EXR,@ERd
STC.W CCR,@(d:16,ERd)
STC.W EXR,@(d:16,ERd)
STC.W CCR,@(d:32,ERd)
STC.W EXR,@(d:32,ERd)
STC.W CCR,@-ERd
STC.W EXR,@-ERd
STC.W CCR,@aa:16
STC.W EXR,@aa:16
STC.W CCR,@aa:32
STC.W EXR,@aa:32
STM.L(ERn-ERn+1) , @-SP
STM.L (ERn-ERn+2) , @-SP
STM.L (ERn-ERn+3) , @-SP
STMAC MACH,ERd
STMAC MACL,ERd
Mnemonic Instruction Format
1st byte
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
—
B
B
W
W
W
W
W
W
W
W
W
W
W
W
L
L
L
L
L
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
C
9
D
B
F
8
C
9
D
B
F
0
4
1
5
3
7
0
4
1
5
3
7
8
0
1
4
4
4
4
4
4
4
4
4
4
4
4
1
2
3
rd
rd
rd
rd
0 erd
0 erd
rd
rd
rd
rd
0 erd
0 erd
rd
rd
rd
rd
0 erd
0 erd
rd
rd
rd
rd
0 erd
0 erd
0
rd
rd
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
6
6
6
6
7
7
6
6
6
6
6
6
6
6
6
9
9
F
F
8
8
D
D
B
B
B
B
D
D
D
1 erd
1 erd
1 erd
1 erd
0 erd
0 erd
1 erd
1 erd
8
8
A
A
F
F
F
0
0
0
0
0
0
0
0
0
0
0
0
0 ern
0 ern
0 ern
6
6
disp
disp
B
B
abs
abs
A
A
0
0
abs
abs
disp
disp
2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Size
Instruction
Cannot be used in this LSI
Rev. 1.0, 02/ 00, page 942 of 1141
SUB
SUBS
SUBX
TAS
TRAPA
XOR
XORC
SUB.B Rs,Rd
SUB.W #xx:16,Rd
SUB.W Rs,Rd
SUB.L #xx:32,ERd
SUB.L ERs,ERd
SUBS #1,ERd
SUBS #2,ERd
SUBS #4,ERd
SUBX #xx:8,Rd
SUBX Rs,Rd
TAS @ERd
TRAPA #x:2
XOR.B #xx:8,Rd
XOR.B Rs,Rd
XOR.W #xx:16,Rd
XOR.W Rs,Rd
XOR.L #xx:32,ERd
XOR.L ERs,ERd
XORC #xx:8,CCR
XORC #xx:8,EXR
Mnemonic Instruction Format
1st byte
B
W
W
L
L
L
L
L
B
B
B
—
B
B
W
W
L
L
B
B
1
7
1
7
1
1
1
1
B
1
0
5
D
1
7
6
7
0
0
0
8
9
9
A
A
B
B
B
rd
E
1
7
rd
5
9
5
A
1
5
1
rs
3
rs
3
1 ers
0
8
9
IMM
rs
E
IMM
IMM
rs
5
rs
5
F
IMM
4
rd
rd
rd
0 erd
0 erd
0 erd
0 erd
0 erd
rd
0
0
rd
rd
rd
0 erd
0
1
7
6
0
IMM
B
IMM
5
5
0 erd
0 ers
IMM
IMM
C
IMM
0 erd
2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte
Size
Instruction
Notes: * Either 1 or 0 can be set to bit 7 in 4th byte of MOV.L Ers, @(d: 32, Erd) instruction.
IMM : Immediate data (2, 3, 8, 16, 32 bits)
abs : Absolute address (8, 16, 24, 32 bits)
disp : Displacement (8, 16, 32 bits)
rs, rd, rn : Register fields (8-bit register or 16-bit register is selected in 4 bits. rs, rd and rn correspond to the operand type Rs, Rd, and Rn respectively.)
ers, erd, ern, erm : Register fields (address register or 32-bit register is selected in 3 bits. ers, erd ern and erm correspond to the operand type ERs,
ERd, ERn and Rm respectively.)
00
Rev. 1.0, 02/ 00, page 943 of 1141
The following table shows the correspondence between the register field and the general
register.
Address Register , 32-bi t
Register 16-bit Regi st er 8-bi t Regist er
Register
Field General
Register Register
Field General
Register Register
Field General
Register
000
001
:
:
:
:
111
ER0
ER1
:
:
:
:
ER7
0000
0001
:
:
:
:
0111
1000
1001
:
:
:
:
1111
R0
R1
:
:
:
:
R7
E0
E1
:
:
:
:
E7
0000
0001
:
:
:
:
0111
1000
1001
:
:
:
:
1111
R0H
R1H
:
:
:
:
R7H
R0L
R1L
:
:
:
:
R7L
Rev. 1.0, 02/ 00, page 944 of 1141
A.3 Operat i on Cod e Map
Table A.10 shows an operat i on code m ap.
Instruction code: 1st byte 2nd byte
AH AL BH BL
BH highest bit is set to 0.
BH highest bit is set to 1
0
NOP
BRA
MULXU
BSET
AH AL
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1
BRN
DIVXU
BNOT
2
BHI
MULXU
BCLR
3
BLS
DIVXU
BTST
STC
STMAC
LDC
LDMAC
4
ORC
OR
BCC
RTS
OR
BORBIOR
6
ANDC
AND
BNE
RTE
AND
5
XORC
XOR
BCS
BSR
XOR
BXOR
BIXOR
BAND
BIAND
7
LDC
BEQ
TRAPA
BST BIST
BLD BILD
8
BVC
MOV
9
BVS
A
BPL
JMP
B
BMI
EEPMOV
C
BGE
BSR
D
BLT
MOV
E
ADDX
SUBX
BGT
JSR
F
BLE
MOV.B
ADD
ADDX
CMP
SUBX
OR
XOR
AND
MOV
ADD
SUB
MOV
MOV
CMP
Table
A.2
**
Note: * Cannot be used in this LSI
Table A.2
Table A.2
Table A.2 Table A.2
Table A.2
Table A.2
TableA.2
Table A.2
Table A.2
Table A.2
Table A.2
Table A.2
Table A.2Table A.2 Table A.2 Table A.2
Table A.10 Operation Code Map
Rev. 1.0, 02/ 00, page 945 of 1141
Instruction code: 1st byte 2nd byte
AH AL BH BL
01
0A
0B
0F
10
11
12
13
17
1A
1B
1F
58
6A
79
7A
0
MOV
INC
ADDS
DAA
DEC
SUBS
DAS
BRA
MOV
MOV
MOV
SHLL
SHLR
ROTXL
ROTXR
NOT
1
LDM
BRN
ADD
ADD
2
BHI
MOV
CMP
CMP
3
STM
NOT
BLS
SUB
SUB
4
SHLL
SHLR
ROTXL
ROTXR
BCC
MOVFPE
OR
OR
5
INC
EXTU
DEC
BCS
XOR
XOR
6
MAC
BNE
AND
AND
7
INC
SHLL
SHLR
ROTXL
ROTXR
EXTU
DEC
BEQ
LDCSTC
8
SLEEP
BVC
MOV
ADDS
SHAL
SHAR
ROTL
ROTR
NEG
SUBS
9
BVS
A
CLRMAC
BPL
MOV
B
NEG
BMI
ADD
MOV
SUB
CMP
C
SHAL
SHAR
ROTL
ROTR
BGE
MOVTPE
D
INC
EXTS
DEC
BLT
E
TAS
BGT
F
INC
SHAL
SHAR
ROTL
ROTR
EXTS
DEC
BLE
BH
AH AL
**
Note: * Cannot be used in this LSI
* *
Table A.2
Table A.2 Table A.2 Table A.2
Table A.2
Rev. 1.0, 02/ 00, page 946 of 1141
Instruction code: 1st byte 2nd byte
AH AL BH BL
3rd byte 4th byte
CH CL DH DL
r is the register specification section.
Absolute address is set at aa.
DH highest bit is set to 0.
DH highest bit is set to 1.
Notes:
AH AL BH BL CH
CL
01C05
01D05
01F06
7Cr06 *
1
7Cr07 *
1
7Dr06 *
1
7Dr07 *
1
7Eaa6 *
2
7Eaa7 *
2
7Faa6 *
2
7Faa7 *
2
0
MULXS
BSET
BSET
BSET
BSET
1
DIVXS
BNOT
BNOT
BNOT
BNOT
2
MULXS
BCLR
BCLR
BCLR
BCLR
3
DIVXS
BTST
BTST
BTST
BTST
4
OR
5
XOR
6
AND
789ABCDEF
1.
2.
BOR
BIOR
BXOR
BIXOR BAND
BIAND
BLDBILD
BSTBIST
BOR
BIOR
BXOR
BIXOR BAND
BIAND
BLDBILD
BSTBIST
Rev. 1.0, 02/ 00, page 947 of 1141
Instruction code: 1st byte 2nd byte
AH AL BH BL
3th byte 4th byte
CH CL DH DL
FH highest bit is set to 0.
FH highest bit is set to 1.
5th byte 6th byte
EH EL FH FL
Instruction code: 1st byte 2nd byte
AH AL BH BL
3rd byte 4th byte
CH CL DH DL
HH highest bit is set to 0.
HH highest bit is set to 1.
Note: * Absolute address is set at aa.
5th byte 6th byte
EH EL FH FL
7th byte 8th byte
GH GL HH HL
6A10aaaa6*
6A10aaaa7*
6A18aaaa6*
6A18aaaa7*
AHALBHBLCHCLDHDLEH
EL 0
BSET
1
BNOT
2
BCLR
3
BTST BOR
BIOR
BXOR
BIXORBAND
BIAND
BLDBILD
BSTBIST
456789ABCDEF
6A30aaaaaaaa6
*
6A30aaaaaaaa7
*
6A38aaaaaaaa6
*
6A38aaaaaaaa7
*
AHALBHBL ... FHFLGH
GL 0
BSET
1
BNOT
2
BCLR
3
BTST BOR
BIOR
BXOR
BIXORBAND
BIAND
BLDBILD
BSTBIST
456789ABCDEF
Rev. 1.0, 02/ 00, page 948 of 1141
A.4 Num ber of Execu t ion S t at es
This section explains execution state and how to calculate the number of execution states for
each instruction of the H8S/2000 CPU.
Table A.12 indicates number of cycles of instruction fetch and data read/write during inst ruction
execution, and table A.11 indicates number of states required for each instruction size.
The number of execution states can be obtained from the equation below.
Number of execution states = I ⋅ SI + J ⋅ SJ + K ⋅ SK + L ⋅ SL + M ⋅ SM + N ⋅ SN
Examples of Execution State Number Calculation
The conditions are as follows: In advanced mode, program and stack areas are set in the on-chip
memory, a wait is inserted every 2 states in the on-chip supporting module access with 8-bit bus
width.
1. BSET # 0 , @FFFFC7 : 8
From Table A.12,
I = L = 2, J = K = M = N = 0
From Table A.11,
SI = 1, SL = 2
Number of execution states = 2 × 1 + 2 × 2 = 6
2. JSR @@3 0
From Table A.12,
I = J = K = 2, L = M = N = 0
From Table A.11,
SI = SJ = SK = 1
Number of execution states = 2 × 1 + 2 × 1 + 2 × 1 = 6
Rev. 1.0, 02/ 00, page 949 of 1141
Table A.11 Number of States Required for Each Execution Status (Cycle)
Target of Access
On- Chi p Suppor ting Module
Execution St at us ( Cycl e) On-Chi p Memor y 8-bit bus 16-bit bus
Instruction fetch SI
Branch address read SJ
Stack operat ion SK
——
Byte data access SL22
Word data access SM
1
4
Int er nal operat ion SN1
Rev. 1.0, 02/ 00, page 950 of 1141
Table A.12 Instr uc ti on Exe c uti on Status (Numbe r of Cy cles)
Instruction
Fetch
Branch
Address
Read Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic IJKLMN
ADD ADD.B #xx:8,Rd
ADD.B Rs, Rd
ADD.W #xx:16,Rd
ADD.W Rs,Rd
ADD L #xx:32,ERd
ADD.L ERs,ERd
1
1
2
1
3
1
ADDS ADDS #1/2/4,ERd 1
ADDX ADDX #xx:8,Rd
ADDX Rs,Rd 1
1
AND AND.B #xx:8,Rd
AND.B Rs,Rd
AND.W #xx.16,Rd
AND.W Rs,Rd
AND L #xx:32,ERd
AND.L ERs,ERd
1
1
2
1
3
2
ANDC ANDC #xx:8,CCR
ANDC #xx:8,EXR 1
2
BAND BAND #xx:3,Rd
BAND #xx:3,@ERd
BAND #xx:3@aa:8
BAND #xx:3@aa:16
BAND #xx:3@aa:32
1
2
2
3
4
1
1
1
1
Bcc BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
BRA d:16 (BT d:16)
BRN d:16 (BF d:16)
BHI d:16
BLS d:16
BCC d:16 (BHS d:16)
BCS d:16 (BLO d:16)
BNE d:16
BEQ d:16
BVC d:16
BVS d:16
BPL d:16
BMI d:16
BGE d:16
BLT d:16
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rev. 1.0, 02/ 00, page 951 of 1141
Instruction
Fetch
Branch
Address
Read Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic IJKLMN
Bcc BGT d:16
BLE d:16 2
21
1
BCLR BCLR #xx:3,Rd
BCLR #xx:3,@ERd
BCLR #xx:3,@aa:8
BCLR #xx:3,@aa:16
BCLR #xx:3,@aa:32
BCLR Rn,Rd
BCLR Rn,@ERd
BCLR Rn,@aa:8
BCLR Rn,@aa:16
BCLR Rn,@aa:32
1
2
2
3
4
1
2
2
3
4
2
2
2
2
2
2
2
2
BIAND BIAND #xx:3,Rd
BIAND #xx:3,@ERd
BIAND #xx:3,@aa:8
BIAND #xx:3,@aa:16
BIAND #xx:3,@aa:32
1
2
2
3
4
1
1
1
1
BILD BILD #xx:3,Rd
BILD #xx:3,@ERd
BILD #xx:3,@aa:8
BILD #xx:3,@aa:16
BILD #xx:3,@aa:32
1
2
2
3
4
1
1
1
1
BIOR BIOR #xx:8,Rd
BIOR #xx:8 ,@ERd
BIOR #xx:8,@aa:8
BIOR #xx:8,@aa:16
BIOR #xx:8,@aa:32
1
2
2
3
4
1
1
1
1
BIST BIST #xx:3,Rd
BIST #xx:3,@ERd
BIST #xx:3,@aa:8
BIST #xx:3,@aa:16
BIST #xx:3,@aa:32
1
2
2
3
4
2
2
2
2
BIXOR BIXOR #xx:3,Rd
BIXOR #xx:3,@ERd
BIXOR #xx:3,@aa:8
BIXOR #xx:3,@aa:16
BIXOR #xx:3,@aa:32
1
2
2
3
4
1
1
1
1
BLD BLD #xx:3,Rd
BLD #xx:3,@ERd
BLD #xx:3,@aa:8
BLD #xx:3,@aa:16
BLD #xx:3,@aa:32
1
2
2
3
4
1
1
1
1
BNOT BNOT #xx:3,Rd
BNOT #xx:3,@ERd
BNOT #xx:3,@aa:8
BNOT #xx:3,@aa:16
BNOT #xx:3,@aa:32
BNOT Rn,Rd
BNOT Rn,@ERd
BNOT Rn,@aa:8
BNOT Rn,@aa:16
1
2
2
3
4
1
2
2
3
2
2
2
2
2
2
2
Rev. 1.0, 02/ 00, page 952 of 1141
Instruction
Fetch
Branch
Address
Read Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic IJKLMN
BNOT BNOT Rn,@aa:32 4 2
BOR BOR #xx:3,Rd
BOR #xx:3,@ERd
BOR #xx:3,@aa:8
BOR #xx:3,@aa:16
BOR #xx:3,@aa:32
1
2
2
3
4
1
1
1
1
BSET BSET #xx:3,Rd
BSET #xx:3,@ERd
BSET #xx:3,@aa:8
BSET #xx:3,@aa:16
BSET #xx:3,@aa:32
BSET Rn,Rd
BSET Rn,@ERd
BSET Rn,@aa:8
BSET Rn,@aa:16
BSET Rn,@aa:32
1
2
2
3
4
1
2
2
3
4
2
2
2
2
2
2
2
2
BSR BSR d:8 2 2
BSR d:16 2 2 1
BST BST #xx:3,Rd
BST #xx:3,@ERd
BST #xx:3,@aa:8
BST #xx:3,@aa:16
BST #xx:3,@aa:32
1
2
2
3
4
2
2
2
2
BTST BTST #xx:3,Rd
BTST #xx:3,@ERd
BTST #xx:3,@aa:8
BTST #xx:3,@aa:16
BTST #xx:3,@aa:32
BTST Rn,Rd
BTST Rn,@ERd
BTST Rn,@aa:8
BTST Rn,@aa:16
BTST Rn,@aa:32
1
2
2
3
4
1
2
2
3
4
1
1
1
1
1
1
1
1
BXOR BXOR #xx:3,Rd
BXOR #xx:3,@E Rd
BXOR #xx:3,@aa:8
BXOR #xx:3,@aa:16
BXOR #xx:3,@aa:32
1
2
2
3
4
1
1
1
1
CLRMAC CLRMAC Cannot be used in this LSI.
CMP CMP.B #xx:8,Rd
CMP.B Rs,Rd
CMP.W #xx:16,Rd
CMP.W Rs,Rd
CMP.L #xx:32,ERd
CMP.L ERs,ERd
1
1
2
1
3
1
DAA DAA Rd 1
DAS DAS Rd 1
Rev. 1.0, 02/ 00, page 953 of 1141
Instruction
Fetch
Branch
Address
Read Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic IJKLMN
DEC DEC.B Rd
DEC.W #1/2,Rd
DEC.L #1/2 ERd
1
1
1
DIVXS DIVXS.B Rs,Rd
DIVXS.W Rs,ERd 2
211
19
DIVXU DIVXU.B Rs,Rd
DIVXU.W Rs,ERd 1
111
19
EEPMOV EEPMOV.B
EEPMOV.W 2
22n+2*2
2n+2*2
EXTS EXTS.W Rd
EXTS.L ERd 1
1
EXTU EXTU.W Rd
EXTU.L ERd 1
1
INC INC.B Rd
INC.W #1/2,Rd
INC.L #1/2,ERd
1
1
1
JMP JMP @ERN
JMP @aa:24 2
21
JMP @@aa:8 2 2 1
JSR JSR @ERn 2 2
JSR @aa:24 2 2 1
JSR @@aa:8 2 2 2
LDC LDC #xx:8,CCR
LDC #xx:8,EXR
LDC Rs,CCR
LDC Rs,EXR
LDC @E Rs,CCR
LDC @ERs,EXR
LDC @(d:16,ERs),CCR
LDC @(d:16,ERs),EXR
LDC @(d:32,ERs),CCR
LDC @(d:32,ERs),EXR
LDC @E Rs+,CCR
LDC @ERs+,EXR
LDC @aa:16,CCR
LDC @aa:16,EXR
LDC @aa:32,CCR
LDC @aa:32,EXR
1
2
1
1
2
2
3
3
5
5
2
2
3
3
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LDM LDM.L
@SP+,(ERn−ERn+1)
LDM.L
@SP+,(ERn−ERn+2)
LDM.L
@SP+,(ERn−ERn+3)
2
2
2
4
6
8
1
1
1
LDMAC LDMAC ERs,MACH
LDMAC ERs,MACL
MAC MAC @ERn+,@ERm+
Cannot be used in this LSI.
Rev. 1.0, 02/ 00, page 954 of 1141
Instruction
Fetch
Branch
Address
Read Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic IJKLMN
MOV MOV.B #xx:8,Rd
MOV.B Rs,Rd
MOV.B @ERs,Rd
MOV.B @(d:16,ERs),Rd
MOV.B @(d:32,ERs),Rd
MOV.B @ ERs+,Rd
MOV.B @aa:8,Rd
MOV.B @aa:16,Rd
MOV.B @aa:32,Rd
MOV.B Rs,@ERd
MOV.B Rs,@(d:16,ERd)
MOV.B Rs,@(d:32,ERd)
MOV.B Rs,@-ERd
MOV.B Rs,@aa:8
MOV.B Rs,@aa:16
MOV.B Rs,@aa:32
MOV.W #xx:16,Rd
MOV.W Rs,Rd
MOV.W @ERs,Rd
MOV.W @(d:16,ERs),Rd
MOV.W @(d:32,ERs),Rd
MOV.W @ERs+,Rd
MOV.W @aa:16,Rd
MOV.W @aa:32,Rd
MOV.W Rs,@ERd
MOV.W Rs,@(d:16,ERd)
MOV.W Rs,@(d:32,ERd)
MOV.W Rs,@-ERd
MOV.W Rs,@aa:16
MOV.W Rs,@aa:32
MOV.L #xx:32,ERd
MOV.L ERs,ERd
MOV.L @ERs,ERd
MOV.L @(d:16,ERs),ERd
MOV.L @(d:32,ERs),ERd
MOV.L @ERs+,ERd
MOV.L @aa:16,ERd
MOV.L @aa:32,ERd
MOV.L ERs,@ERd
MOV.L ERs,@(d:16,ERd)
MOV.L ERs,@(d:32,ERd)
MOV.L ERs,@-ERd
MOV.L ERs,@aa:16
MOV.L ERs,@aa:32
1
1
1
2
4
1
1
2
3
1
2
4
1
1
2
3
2
1
1
2
4
1
2
3
1
2
4
1
2
3
3
1
2
3
5
2
3
4
2
3
5
2
3
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
MOVFPE MOVFPE @:aa:16,Rd
MOVTPE MOVTPE Rs,@:aa:16 Cannot be used in this LSI.
MULXS MULXS.B Rs,Rd 2 11
MULXS . W Rs,ERd 2 19
MULXU MULXU.B Rs,Rd 1 11
MULXU.W Rs,ERd 1 19
Rev. 1.0, 02/ 00, page 955 of 1141
Instruction
Fetch
Branch
Address
Read Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic IJKLMN
NEG NEG.B Rd
NEG.W Rd
NEG.L ERd
1
1
1
NOP NOP 1
NOT NOT.B Rd
NOT.W Rd
NOT.L ERd
1
1
1
OR OR.B #xx:8,Rd
OR.B Rs,Rd
OR.W #xx:16,Rd
OR.W Rs,Rd
OR.L #xx:32,ERd
OR.L ERs,ERd
1
1
2
1
3
2
ORC ORC #xx:8,CCR
ORC #xx:8,EXR 1
2
POP POP.W Rn
POP.L ERn 1
21
21
1
PUSH PUSH.W Rn
PUSH.L ERn 1
21
21
1
ROTL ROTL.B Rd
ROTL.B #2,Rd
ROTL.W Rd
ROTL.W #2,Rd
ROTL.L ERd
ROTL.L #2,ERd
1
1
1
1
1
1
ROTR ROTR.B Rd
ROTR.B #2,Rd
ROTR.W Rd
ROTR.W #2,Rd
ROTR.L ERd
ROTR.L #2,ERd
1
1
1
1
1
1
ROTXL ROTXL.B Rd
ROTXL.B #2,Rd
ROTXL.W Rd
ROTXL.W #2,Rd
ROTXL.L ERd
ROTXL.L #2,ERd
1
1
1
1
1
1
ROTXR ROTXR.B Rd
RPTXR.B #2,Rd
ROTXR.W Rd
ROTXR.W #2,Rd
ROTXR.L ERd
ROTXR.L #2,ERd
1
1
1
1
1
1
RTE RTE 2 2/3*1 1
RTS RTS 2 2 1
Rev. 1.0, 02/ 00, page 956 of 1141
Instruction
Fetch
Branch
Address
Read Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic IJKLMN
SHAL SHAL.B Rd
SHAL.B #2,Rd
SHAL.W Rd
SHAL.W #2,Rd
SHAL.L ERd
SHAL.L #2,ERd
1
1
1
1
1
1
SHAR SHAR.B Rd
SHAR.B #2,Rd
SHAR.W Rd
SHAR.W #2,Rd
SHAR.L ERd
SHAR.L #2,ERd
1
1
1
1
1
1
SHLL SHLL.B Rd
SHLL.B #2,Rd
SHLL.W Rd
SHLL.W #2,Rd
SHLL.L ERd
SHLL.L #2,ERd
1
1
1
1
1
1
SHLR SHLR.B Rd
SHLR.B #2,Rd
SHLR.W Rd
SHLR.W #2,Rd
SHLR.L ERd
SHLR.L #2,ERd
1
1
1
1
1
1
SLEEP SLEEP 1 1
STC STC.B CCR.Rd
STC.B EXR,Rd
STC.W CCR,@ERd
STC.W EXR,@ERd
STC.W CCR,@(d:1 6,ERd)
STC.W EXR,@(d:16,ERd)
STC.W CCR,@(d:3 2,ERd)
STC.W EXR,@(d:32,ERd)
STC.W CCR,@-E Rd
STC.W EXR,@-ERd
STC.W CCR,@aa:16
STC.W EXR,@aa:16
STC.W CCR,@aa:32
STC.W EXR,@aa:32
1
1
2
2
3
3
5
5
2
2
3
3
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
STM STM.L (ERn-ERn+1),
@-Sp
STM.L (ERn-E Rn+2),
@-Sp
STM.L (ERn-E Rn+3),
@-Sp
2
2
2
4
6
8
1
1
1
STMAC STMAC MACH,ERd
STMAC MACL,ERd Cannot be used in this LSI.
SUB SUB.B Rs,Rd
SUB.W #xx:16,Rd
SUB.W Rs,Rd
SUB.L #xx:32,ERd
SUB.L ERs,ERd
1
2
1
3
1
SUBS SUBS #1/2/4,ERd 1
Rev. 1.0, 02/ 00, page 957 of 1141
Instruction
Fetch
Branch
Address
Read Stack
Operation Byte Data
Access Word Data
Access Internal
Operation
Instruction Mnemonic IJKLMN
SUBX SUBX #xx:8,Rd
SUBX Rs,Rd 1
1
TAS TAS @ERd 2 2
TRAPA TRAPA #x:2 2 2 2/3*1 2
XOR XOR.B #xx:8,Rd
XOR.B Rs,Rd
XOR.W #xx:16,Rd
XOR.W Rs,Rd
XOR.L #xx:32,ERd
XOR.L ERs,ERd
1
1
2
1
3
2
XORC XORC #xx:8,CCR
XORC #xx:8,EXR 1
2
Notes: 1. 3 applies when EXR is valid, and 2 applies when invalid.
2. Applies when the transf er dat a is n byt es.
Rev. 1.0, 02/ 00, page 958 of 1141
A.5 Bus Status during Instruction Execution
Table A.13 indicates execution status of each instruction available in this LSI. For the number
of states required for each execution status, see table A.11, Number of States Required for Each
Execution Status (Cycle).
Interpreting the Table
Instruction
JMP@aa:24 R:W 2nd
Internal operation
1 state
R:W EA
12345678
End of instruction
Order of execution
Effective address is read by word.
Read/write not executed
The 2nd word of the instruction currently being
executed is read by word.
R : B Read by byte
R : W Read by word
W : B Write by byte
W : W Write by word
: M Bus not t r ansferr ed imm ediately after t his cycle
2nd Address of t he 2nd word ( 3r d and 4t h byt es)
3rd Address of t he 3r d word ( 5t h and 6t h byt es)
4th Address of t he 4t h word ( 7t h and 8t h byt es)
5th Address of t he 5t h word ( 9t h and 10t h byt es)
NEXT The head address of t he instr uct ion imm ediately after t he instr uct ion
current ly being executed
EA Execut ion addr ess
VEC Vector address
Rev. 1.0, 02/ 00, page 959 of 1141
Table A.13 Instr uc ti on Exe c uti on Status
Instruction123456789
ADD.B #xx:8,Rd R:W NEXT
ADD.B Rs,Rd R:W NEXT
ADD.W #xx:16,Rd R:W 2nd R:W NEXT
ADD.W Rs,Rd R:W NEXT
ADD.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
ADD.L ERs,ERd R:W NEXT
ADDS #1/2/4,ERd R:W NEXT
ADDX #xx:8,Rd R:W NEXT
ADDX Rs,Rd R:W NEXT
AND.B #xx:8,Rd R:W NEXT
AND.B Rs,Rd R:W NEXT
AND.W #xx:16,Rd R:W 2nd R:W NEXT
AND.W Rs,Rd R:W NEXT
AND.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
AND.L ERs,ERd R:W 2nd R:W NEXT
ANDC #xx:8,CCR R:W NEXT
ANDC #xx:8,EXR R:W 2nd R:W NEX T
BAND #xx:3,Rd R:W NEXT
BAND #xx:3,@ERd R:W 2nd R:B EA R:W:M
NEXT
BAND #xx:3,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BAND
#xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BAND
#xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
BRA d:8 (BT d:8) R:W NEXT R:W EA
BRN d:8 (BF d:8) R:W NEXT R:W EA
BHI d:8 R:W NEXT R:W EA
BLS d:8 R:W NEXT R:W EA
BCC d:8 (BHS d:8) R:W NEXT R:W EA
BCS d:8 (BLO d:8) R:W NEXT R:W EA
BNE d:8 R:W NEXT R:W EA
BEQ d:8 R:W NEXT R:W EA
BVC d:8 R:W NEXT R:W EA
BVS d:8 R:W NEXT R:W EA
BPL d:8 R:W NEXT R:W EA
BMI d:8 R:W NEXT R:W EA
BGE d:8 R:W NEXT R:W EA
Rev. 1.0, 02/ 00, page 960 of 1141
Instruction123456789
BLT d:8 R:W NEXT R:W EA
BGT d:8 R:W NEXT R:W EA
BLE d:8 R:W NEXT R:W EA
BRA d:16 (BT d:16) R:W 2nd Internal
operation
1 state
R:W EA
BRN d:16 (BF d:16) R:W 2nd Internal
operation
1 state
R:W EA
BHI d:16 R:W 2nd Internal
operation
1 state
R:W EA
BLS d:16 R:W 2nd Internal
operation
1 state
R:W EA
BCC d:16
(BHS d:16) R:W 2nd Internal
operation
1 state
R:W EA
BCS d:16
(BLO d:16) R:W 2nd Internal
operation
1 state
R:W EA
BNE d:16 R:W 2nd Internal
operation
1 state
R:W EA
BEQ d:16 R:W 2nd Internal
operation
1 state
R:W EA
BVC d:16 R:W 2nd Internal
operation
1 state
R:W EA
BVS d:16 R:W 2nd Internal
operation
1 state
R:W EA
BPL d:16 R:W 2nd Internal
operation
1 state
R:W EA
BMI d:16 R:W 2nd Internal
operation
1 state
R:W EA
BGE d:16 R:W 2nd Internal
operation
1 state
R:W EA
BLT d:16 R:W 2nd Internal
operation
1 state
R:W EA
BGT d:16 R:W 2nd Internal
operation
1 state
R:W EA
Rev. 1.0, 02/ 00, page 961 of 1141
Instruction123456789
BLE d:16 R:W 2nd Internal
operation
1 state
R:W EA
BCLR #xx:3,Rd R:W NEXT
BCLR #xx:3,@ERd R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BCLR #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BCLR
#xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M
NEXT W:B EA
BCLR
#xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M
NEXT W:B EA
BCLR Rn,Rd R:W NEXT
BCLR Rn,@ERd R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BCLR Rn,@aa:8 R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BCLR Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M
NEXT W:B EA
BCLR Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M
NEXT W:B EA
BIAND #xx:3,Rd R:W NE XT
BIAND #xx:3,ERd R:W 2nd R:B EA R:W:M
NEXT
BIAND #xx:3,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BIAND
#xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BIAND
#xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
BILD #xx:3,Rd R:W NEXT
BILD #xx:3,@ERd R:W 2nd R:B EA R:W:M
NEXT
BILD #xx:3,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BILD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BILD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
BIOR #xx:3,Rd R:W NEXT
BIOR #xx:3,@ERd R:W 2nd R:B EA R:W:M
NEXT
BOIR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
Rev. 1.0, 02/ 00, page 962 of 1141
Instruction123456789
BOIR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BOIR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
BIST #xx:3,Rd R:W NEXT
BIST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BIST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BIST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M
NEXT W:B EA
BIST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M
NEXT W:B EA
BIXOR #xx:3,Rd R:W NEXT
BIXOR #xx:3,@ERd R:W 2nd R:B EA R:W:M
NEXT
BIXOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BIXOR
#xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BIXOR
#xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
BLD #xx:3,Rd R:W NEXT
BLD #xx:3,@ERd R:W 2nd R:B E A R:W:M
NEXT
BLD #xx:3,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BLD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BLD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
BNOT #xx:3,Rd R:W NEXT
BNOT #xx:3,ERd R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BNOT #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BNOT
#xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M
NEXT W:B EA
BNOT
#xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M
NEXT W:B EA
BNOT Rn,Rd R:W NEXT
BNOT Rn,@ERd R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BNOT Rn @aa:8 R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
Rev. 1.0, 02/ 00, page 963 of 1141
Instruction123456789
BNOT Rn @aa:16 R:W 2nd R:W 3rd R:B:W EA R:W:M
NEXT W:B EA
BNOT Rn @aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M
NEXT W:B EA
BOR #xx:3,Rd R:W NEXT
BOR #xx:3,ERd R:W 2nd R:B EA R:W:M
NEXT
BOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W NEXT
BSET #xx:3,Rd R:W NEXT
BSET #xx:3,@ERd R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BSET #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BSET #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M
NEXT W:B EA
BSET #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M
NEXT W:B EA
BSET Rn,Rd R:W NEXT
BSET Rn,@ERd R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BSET Rn,@aa:8 R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BSET Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M
NEXT W:B EA
BSET Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M
NEXT W:B EA
BSR d:8 R:W NEXT R:W EA W:W:M
stack(H) W:W
stack(L)
BSR d:16 R:W 2nd Internal
operation
1 state
R:W EA W:W:M
stack(H) W:W
stack(L)
BST #xx:3,Rd R:W NEXT
BST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M
NEXT W:B EA
BST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M
NEXT W:B EA
BST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M
NEXT W:B EA
BTST #xx:3,Rd R:W NEXT
Rev. 1.0, 02/ 00, page 964 of 1141
Instruction123456789
BTST #xx:3,@ERd R:W 2nd R:B EA R:W:M
NEXT
BTST #xx:3,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BTST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BTST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
BTST Rn,Rd R:W NEXT
BTST Rn,@ERd R:W 2nd R:B EA R:W:M
NEXT
BTST Rn,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BTST Rn,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BTST Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
BOXR #xx:3,Rd R:W NEXT
BOXR #xx:3,@ERd R:W 2nd R:B EA R:W:M
NEXT
BOXR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M
NEXT
BOXR
#xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M
NEXT
BOXR
#xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M
NEXT
CLRMAC Cannot be used in this LSI.
CMP.B #xx:8,Rd R:W NEXT
CMP.B Rs,Rd R:W NEXT
CMP.W #xx:16,Rd R:W 2nd R:W NEXT
CMP.W Rs,Rd R:W NEXT
CMP.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
CMP.L ERs,ERd R:W NEXT
DAA Rd R:W NEXT
DAS Rd R:W NEXT
DEC.B Rd R:W NEXT
DEC.W #1 /2,Rd R:W NEXT
DEC.W #1/2,ERd R:W NEXT
DIVXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation 11 state
DIVXS.W Rs,ERd R:W 2nd R:W NEXT Internal operation 19 state
Rev. 1.0, 02/ 00, page 965 of 1141
Instruction123456789
DIVXU.B Rs,Rd R:W NEXT Internal operation 11 state
DIVXU.W Rs,ERd R:W NEXT Internal operation 19 state
EEPMOV.B R:W 2nd R:B EAs *1 R:B EAd *1 R:B EAs *2 W:B EAd *2 R:W NEXT
EEPMOV.W R:W 2nd R:B EAs *1 R:B EAd *1 R:B EAs *2 W:B EAd *2 R:W NEXT
EXTS.W Rd R:W NEXT ← Repeat n times*2 →
EXTS.L ERd R:W NEXT
EXTU.W Rd R:W NEXT
EXTU.L ERd R:W NEXT
INC.B Rd R:W NEXT
INC.W #1/2,Rd R:W NEXT
INC.L #1/2,ERd R:W NEXT
JMP @ERn R:W NEXT R:W EA
JMP @aa:24 R:W 2nd Internal
operation
1 state
R:W EA
JMP @@aa:8 R:W NEXT R:W:M
aa:8 R:W:M
aa:8 Internal
operation
1 state
R:W EA
JSR @ERn R:W NEXT R:W EA W:W:M
stack(H) W:W
stack (L)
JSR @aa:24 R:W 2nd Internal
operation
1 state
R:W EA W:W:M
stack(H) W:W
stack (L)
JSR @@aa:8 R:W NEXT R:W:M
aa:8 R:W aa:8 W:W:M
stack(H) W:W
stack (L) R:W EA
LDC #xx.8,CCR R:W NEXT
LDC #xx.8,EXR R:W 2nd R:W NEXT
LDC Rs,CCR R:W NEXT
LDC Rs,EXR R:W NEXT
LDC @ERs,CCR R:W 2nd R:W NEXT R:W EA
LDC @ERs,EXR R:W 2nd R:W NEXT R:W EA
LDC
@(d:16,ERs),CCR R:W 2nd R:W 3rd R:W NEXT R:W EA
LDC
@(d:16,ERs),EXR R:W 2nd R:W 3rd R:W NEXT R:W EA
LDC
@(d:32,ERs),CCR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA
LDC
@(d:32,ERs),EXR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA
LDC @ERs+,CCR R:W 2nd R:W NEXT Internal
operation
1 state
R:W EA
Rev. 1.0, 02/ 00, page 966 of 1141
Instruction123456789
LDC @ERs+,EXR R:W 2nd R:W NEXT Internal
operation
1 state
R:W EA
LDC @aa:16,CCR R:W 2nd R:W 3rd R:W NEX T R:W EA
LDC @aa:16,EXR R:W 2nd R:W 3rd R:W NEXT R:W EA
LDC @aa:32,CCR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA
LDC @aa:32,EXR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA
LDM.L @SP+,
(ERn-ERn+1) R:W 2nd R:W:M
NEXT Internal
operation
1 state
R:W:M
stack(H) *3 R:W
stack(L) *3
LDM.L @SP+,
(ERn-ERn+2) R:W 2nd R:W:M
NEXT Internal
operation
1 state
R:W:M
stack(H) *3 R:W
stack(L) *3
LDM.L @SP+,
(ERn-ERn+3) R:W 2nd R:W:M
NEXT Internal
operation
1 state
R:W:M
stack(H) *3 R:W
stack(L) *3
LDMAC ERs,MACH Cannot be used in this LSI.
LDMAC ERs,MACL
MAC
@ERn+,@ERm+
MOV.B #xx:8,Rd R:W NEXT
MOV.B Rs,Rd R:W NEXT
MOV.B @ERs,Rd R:W NEXT R:B EA
MOV.B
@(d:16,ERs),Rd R:W 2nd R:W NEXT R:B EA
MOV.B
@(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:B EA
MOV.B @ERs+,Rd R:W NEXT Internal
operation
1 state
R:B EA
MOV.B @aa:8,Rd R:W NEXT R:B EA
MOV.B @aa:16,Rd R:W 2nd R:W NEXT R:B EA
MOV.B @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA
MOV.B Rs,@ERd R:W NEXT W:B EA
MOV.B
Rs,@(d:16,ERd) R:W 2nd R:W NEXT W:B EA
MOV.B
Rs,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W NEXT W:B EA
MOV.B Rs,@-ERd R:W NEXT Internal
operation
1 state
W:B EA
MOV.B Rs,@aa:8 R:W NEXT W:B EA
MOV.B Rs,@aa:16 R:W 2nd R:W NEXT W:B EA
MOV.B Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT W:B EA
MOV.W #xx:16,Rd R:W 2nd R:W NEXT
Rev. 1.0, 02/ 00, page 967 of 1141
Instruction123456789
MOV.W Rs,Rd R:W NEXT
MOV.W @ERs,Rd R:W NEXT R:W EA
MOV.W
@(d:16,ERs),Rd R:W 2nd R:W NEXT R:W EA
MOV.W
@(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA
MOV.W @ERs+,Rd R:W NEXT Internal
operation
1 state
R:W EA
MOV.W @aa:16,Rd R:W 2nd R:W NEXT R:W EA
MOV.W @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT R:B EA
MOV.W Rs,@ERd R:W NEXT W:W EA
MOV.W
Rs,@(d:16,ERd) R:W 2nd R:W NEXT W:W EA
MOV.W
Rs,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA
MOV.W Rs,@-ERd R:W NEXT Internal
operation
1 state
W:W EA
MOV.W Rs,@aa:16 R:W 2nd R:W NEXT W:W EA
MOV.W Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT W:W EA
MOV.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
MOV.L ERs,ERd R:W NEXT
MOV.L @ERs,ERd R:W 2nd R:W:M
NEXT R:W:M EA R:W EA+2
MOV.L
@(d:16,ERs),ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2
MOV.L
@(d:32,ERs),ERd R:W 2nd R:W:M 3rd R:W:M 4th R:W 5th R:W NEXT R:W:M EA R:W EA+2
MOV.L @ERs+,ERd R:W 2nd R:W:M
NEXT Internal
operation
1 state
R:W:M EA R:W EA+2
MOV.L @aa:16,ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2
MOV.L @aa:32,ERd R:W 2nd R:W:M 3rd R:W 4th R:W NEXT R:W:M EA R:W EA+2
MOV.L ERs,@ERd R:W 2nd R:W:M
NEXT W:W:M EA W:W EA+2
MOV.L
ERs,@(d:16,ERd) R:W 2nd R:W:M 3rd R:W NEXT W:W:M EA W:W EA+2
MOV.L
ERs,@(d:32,ERd) R:W 2nd R:W:W 3rd R:W:M 4th R:W 5th R:W NEXT W:W:M EA W:W EA+2
MOV.L ERs,@-ERd R:W 2nd R:W:M
NEXT Internal
operation
1 state
W:W:M EA W:W EA+2
Rev. 1.0, 02/ 00, page 968 of 1141
Instruction123456789
MOV.L ERs,@aa:16 R:W 2nd R:W:M 3rd R:W NEXT W:W:M EA W:W EA+2
MOV.L ERs,@aa:32 R:W 2nd R:W:M 3rd R:W 4th R:W NEXT W:W:M EA W:W EA+2
MOVFPE
@aa:16,Rd Cannot be used in this LSI.
MOVTPE
Rs,@aa:16
MULXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation 11 state
MULXS.W Rs,Rd R:W 2nd R:W NEXT Internal operation 19 state
MULXU.B Rs,Rd R:W NEXT Internal operation 11 state
MULXU.W Rs,Rd R:W NEXT Internal operation 19 state
NEG.B Rd R:W NEXT
NEG.W Rd R:W NEXT
NEG.L ERd R:W NEXT
NOP R:W NEXT
NOT.B Rd R:W NEXT
NOT.W Rd R:W NEXT
NOT.L ERd R:W NEXT
OR.B #xx:8,Rd R:W NEX T
OR.B Rs,Rd R:W NEXT
OR.W #xx:16,Rd R:W 2nd R:W NEXT
OR.W Rs,Rd R:W NEXT
OR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
OR.L ERs,ERd R:W 2nd R:W NEXT
ORC #xx:8,CCR R:W NEXT
ORC #xx:8,EXR R:W 2nd R:W NEX T
POP.W Rn R:W NEXT Internal
operation
1 state
R:W EA
POP.L ERn R:W 2nd R:W:M
NEXT Internal
operation
1 state
R:W:M EA R:W EA+2
PUSH.W Rn R:W NEXT Internal
operation
1 state
W:W EA
PUSH.L ERn R:W 2nd R:W:M
NEXT Internal
operation
1 state
W:W:M EA W:W EA+2
ROTL.B Rd R:W NEXT
ROTL.B #2,Rd R:W NEXT
ROTL.W Rd R:W NEXT
ROTL.W #2,Rd R:W NEXT
ROTL.L ERd R:W NEX T
ROTL.L #2, ERd R:W NEXT
Rev. 1.0, 02/ 00, page 969 of 1141
Instruction123456789
ROTR.B Rd R:W NEXT
ROTR.B #2,Rd R:W NEXT
ROTR.W Rd R:W NEXT
ROTR.W #2,Rd R:W NEXT
ROTR.L ERd R:W NEX T
ROTR.L #2,ERd R:W NEXT
ROTXL.B Rd R:W NEXT
ROTXL.B #2.Rd R:W NEXT
ROTXL.W Rd R:W NEXT
ROTXL.W #2,Rd R:W NEXT
ROTXL.L ERd R:W NEXT
ROTXL.L #2,ERd R:W NEXT
ROTXR.B Rd R:W NEXT
ROTXR.B #2,Rd R:W NEXT
ROTXR.W Rd R:W NEXT
ROTXR.W #2,Rd R:W NEXT
ROTXR.L ERd R:W NEXT
ROTXR.L #2.ERd R:W NEXT
RTE R:W NEXT R:W stack
(EXR) R:W
stack(H) R:W
stack(L) Internal
operation
1 state
R:W *4
RTS R:W NEXT R:W:M
stack(H) R:W
stack(L) Internal
operation
1 state
R:W *4
SHAL.B Rd R:W NEXT
SHAL B #2,Rd R:W NEXT
SHAL.W Rd R:W NEXT
SHAL.W #2,Rd R:W NEXT
SHAL.L ERd R:W NEXT
SHAL.L #2,ERd R:W NEXT
SHAR.B Rd R:W NEXT
SHAR.B #2,Rd R:W NEXT
SHAR.W Rd R:W NEXT
SHAR.W #2,Rd R:W NEXT
SHAR.L ERd R:W NEXT
SHAR.L #2,ERd R:W NEXT
SHLL.B Rd R:W NEXT
SHLL.B #2,Rd R:W NEXT
SHLL.W Rd R:W NEXT
SHLL.W #2,Rd R:W NEXT
SHLL.L ERd R:W NEXT
Rev. 1.0, 02/ 00, page 970 of 1141
Instruction123456789
SHLL.L #2,ERd R:W NEXT
SHLR.B Rd R:W NEXT
SHLR.B #2,Rd R:W NEXT
SHLR.W Rd R:W NEXT
SHLR.W #2,Rd R:W NEXT
SHLR.L ERd R:W NEXT
SHLR.L #2,ERd R:W NEXT
SLEEP R:W NEXT Internal
operation:
M
STC.B CCR,Rd R:W NEXT
STC.B EXR,Rd R:W NEXT
STC.W CCR,@ERd R:W 2nd R:W NEXT W:W E A
STC.W EXR,@ERd R:W 2nd R:W NEXT W:W EA
STC.W
CCR,@(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA
STC.W
EXR,@(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA
STC.W
CCR,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA
STC.W
EXR,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA
STC.W CCR,@-
ERd R:W 2nd R:W NEXT Internal
operation
1 state
W:W EA
STC.W EXR,@-ERd R:W 2nd R:W NEXT Internal
operation
1 state
W:W EA
STC.W
CCR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA
STC.W
EXR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA
STC.W
CCR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA
STC.W
EXR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA
STM.L (ERn-
ERn+1),@-SP R:W 2nd R:W:M
NEXT Internal
operation
1 state
W:W:M
stack (H)
*3
W:W
sta ck (L) *3
STM.L (ERn-
ERn+2),@-SP R:W 2nd R:W:M
NEXT Internal
operation
1 state
W:W:M
stack (H)
*3
W:W
sta ck (L) *3
STM.L (ERn-
ERn+3),@-SP R:W 2nd R:W:M
NEXT Internal
operation
1 state
W:W:M
stack (H)
*3
W:W
sta ck (L) *3
Rev. 1.0, 02/ 00, page 971 of 1141
Instruction12345 6789
STMAC MACH,ERd Cannot be used in this LSI.
STMAC MACL,ERd
SUB.B Rs,Rd R:W NEXT
SUB.W #xx:16,Rd R:W 2nd R:W NEXT
SUB.W Rs,Rd R:W NEXT
SUB.L #xx:32,ERd R:W 2nd R:W 3nd R:W NEXT
SUB.L ERs,ERd R:W NEXT
SUB #1/2/4,ERd R:W NEXT
SUBX #xx:8,Rd R:W NEXT
SUBX Rs,Rd R:W NEXT
TAS @ERd R:W 2nd R:W NEXT R:B:M EA W:B EA
TRAPA #x:2 R:W NEXT Internal
operation
1 state
W:W
stack(L) W:W
stack(H) W:W
stack(EXR) R:W:M
VEC R:W
VEC+2 Internal
operation
1 state
R:W *7
XOR.B #xx:8,Rd R:W NEXT
XOR.B Rs,Rd R:W NEXT
XOR.W #xx:16,Rd R:W 2nd R:W NEXT
XOR.W Rs,Rd R:W NEXT
XOR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT
XOR.L ERs,ERd R:W 2nd R:W NEXT
XORC #xx:8,CCR R:W NEXT
XORC #xx:8,EXR R:W 2nd R:W NEXT
Re set exception
handling R:W:M
VEC R:W
VEC+2 Internal
operation
1 state
R:W *5
Interrupt exception
handling R:W *6 Internal
operation
1 state
W:W
stack(L) W:W
stack(H) W:W
stack(EXR) R:W:M
VEC R:W
VEC+2 Internal
operation
1 state
R:W *7
Notes: 1. EAs is the contents of ER5, and EAd is the contents of ER6.
2. 1 is added t o EAs and EAd after execut ion. n is t he initial value of R4L or R4. When
0 is set to n, R4L or R4 is not execut ed.
3. Repeated twice for 2- unit r etract / r et ur n, thr ee t im es f or 3- unit r et r act/r et ur n, and f our
times for 4-retract/return.
4. Head address af t er r et ur n.
5. St ar t addr ess of t he pr ogr am .
6. Pre- fetch addr ess obt ained by adding 2 to t he PC to be r etract ed.
When ret ur ning fr om sleep m ode, st andby m ode or wat ch m ode, inter nal oper at ion is
executed instead of r ead oper at ion.
7. Head address of t he int err upt process r out ine.
Rev. 1.0, 02/ 00, page 972 of 1141
A.6 Change of Condition Codes
This section explains change of condition codes after instruction execution of the CPU. Legend
of the following tables is as follows.
m = 31: L ongword size
m = 15: W ord size
m = 7: Byte size
Si: Bit i of source opera nd
Di: Bi t i of de stina t ion ope ra nd
Ri: Bit i of result
Dn: Specified bit of destination operand
−: No affection
: Changes depe nding on e xe cut i on result
0: Always cleared to 0
1: Alwa y s se t to 1
*: Value undetermined
Z': Z fla g be fore e xe cut i on
C': C flag before e xe cut i on
Rev. 1.0, 02/ 00, page 973 of 1141
Tabl e A.14 Change o f Co ndi t i o n Co de
Instruc-
tion H N Z V C Definition
ADD H=Sm-4⋅Dm-4+Dm-4⋅
5P
+Sm-4⋅
5P
N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
V=Sm⋅Dm⋅
5P
+
6P
⋅
'P
⋅Rm
C=Sm⋅Dm+Dm⋅
5P
+Sm⋅
5P
ADDS −−−−−
ADDX H=Sm-4⋅Dm-4+Dm-4⋅
5P
+Sm-4⋅
5P
N=Rm
Z=Z'⋅
5P
⋅

⋅
5
V=Sm⋅Dm⋅
5P
+
6P
⋅
'P
⋅Rm
C=Sm⋅Dm+Dm⋅
5P
+Sm⋅
5P
AND −0−N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
ANDC Value in the bit corresponding t o execut ion
result is stor ed.
No flag change when EXR.
BAND −−−− C=C'⋅Dn
Bcc −−−−−
BCLR −−−−−
BIAND −−−− C=C'⋅
'Q
BILD −−−− C=
'Q
BIOR −−−− C=C'+
'Q
BIST −−−−−
BIXOR −−−− C=C'⋅Dn+
&
⋅
'Q
BLD −−−− C=Dn
BNOT −−−−−
BOR −−−− C=C'+Dn
BSET −−−−−
BSR −−−−−
BST −−−−−
BTST −− −−Z=
'Q
BXOR −−−− C=C'⋅
'Q
+
&
⋅Dn
CLRMAC Cannot be used in this LSI .
Rev. 1.0, 02/ 00, page 974 of 1141
Instruc-
tion H N Z V C Definition
CMP H=Sm-4⋅
'P
+
'P
⋅Rm-4+Sm-4⋅Rm-4
N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
V=
6P
⋅Dm⋅
5P
+Sm⋅
'P
⋅Rm
C=Sm⋅
'P
+
'P
⋅Rm+Sm⋅Rm
DAA * *N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
C: Decimal addition carry
DAS * *N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
C: Decimal subtraction borr ow
DEC − − N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
V=Dm⋅
5P
DIVXS −−−N=Sm⋅
'P
+
6P
⋅Dm
Z=
6P
⋅
6P
⋅

⋅
6
DIVXU −−−N=Sm
Z=
6P
⋅
6P
⋅

⋅
6
EEPMOV −−−−−
EXTS −0−N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
EXTU −0 0 −Z=
5P
⋅
5P
⋅

⋅
5
INC − − N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
V=
'P
⋅
5P
JMP −−−−−
JSR −−−−−
LDC Value in the bit cor r esponding t o execut ion
result is stor ed.
No flag change when EXR.
LDM −−−−−
LDMAC
MAC
Cannot be used in this LSI.
MOV −0−N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
Rev. 1.0, 02/ 00, page 975 of 1141
Instruc-
tion H N Z V C Definition
MOVFPE
MOVTPE
Cannot be used in this LSI.
MULXS −−−N=R2m
Z=
5P
⋅
5P
⋅

⋅
5
MULXU −−−−−
NEG H=Dm-4+Rm-4
N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
V=Dm⋅Rm
C=Dm+Rm
NOP −−−−−
NOT −0−N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
OR −0−N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
ORC Value in the bit corr esponding to execut ion
result is stor ed. No flag change when EXR.
POP −0−N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
PUSH −0−N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
ROTL −0N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
C=Dm(In case of 1 bit ) , C=Dm-1( I n case of 2
bits)
ROTR −0N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
C=D0(In case of 1 bit), C=D-1(In case of 2 bits)
ROTXL −0N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
C=Dm(In case of 1 bit), C= Dm -1(In case of 2 bits)
ROTXR −0N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
C=D0(In case of 1 bit), C=D1 (In case of 2 bits)
RTE Value in the bit corresponding t o execut ion
result is stor ed.
RTS −−−−−
Rev. 1.0, 02/ 00, page 976 of 1141
Instruc-
tion H N Z V C Definition
SHAL −N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
V=Dm⋅Dm-1+
'P
⋅
'P
(In case of 1 bit)
V=Dm⋅Dm-1⋅Dm-2⋅
'P
⋅
'P
⋅
'P
(In case of 2bits)
C=Dm(In case of 1 bit), C= Dm -1(In case of 2 bits)
SHAR −0N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
C=D0(In case of 1 bit), C=D1 (In case of 2 bits)
SHLL −0N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
C=Dm(In case of 1 bit), C= Dm -1(In case of 2 bits)
SHLR −0 0 N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
C=D0(In case of 1 bit), C=D1 (In case of 2 bits)
SLEEP −−−−−
STC −−−−−
STM −−−−−
STMAC Cannot be used in this LSI.
SUB H=Sm-4⋅
'P
+
'P
⋅Rm-4+Sm-4⋅Rm-4
N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
V=
6P
⋅Dm⋅
5P
+Sm⋅
'P
⋅Rm
C=Sm⋅
'P
+
'P
⋅Rm+Sm⋅Rm
SUBS −−−−−
SUBX H=Sm-4⋅
'P
+
'P
⋅Rm-4+Sm-4⋅Rm-4
N=Rm
Z=Z'⋅
5P
⋅

⋅
5
V=
6P
⋅Dm⋅
5P
+Sm⋅
'P
⋅Rm
C=Sm⋅
'P
+
'P
⋅Rm+Sm⋅Rm
TAS −0−N=Dm
Z=
'P
⋅
'P
⋅

⋅
'
TRAPA −−−−−
XOR −0−N=Rm
Z=
5P
⋅
5P
⋅

⋅
5
XORC Value in the bit cor r esponding t o execut ion
result is stor ed. No flag change when EXR.
Rev. 1.0, 02/ 00, page 977 of 1141
Appendix B In ternal I/O Registers
B.1 Addresses
Tabl e B .1 Addr e sses
Address*1Register
Name R/W Access Bus
Width76543210Module
Name
H'0000
to
H'CFFF
H'D000 DGKp W 16 16 DGKp15 DGKp14 DGKp13 DGKp12 DGKp11 DGKp10 DGKp9 DGKp8
H'D001 DGKp7 DGKp6 DGKp5 DGKp4 DGKp3 DGKp2 DGKp1 DGKp0
H'D002 DGKs W 16 16 DGKs15 DGKs14 DGKs13 DGKs12 DGKs11 DGKs10 DGKs9 DGKs8
H'D003 DGKs7 DGKs6 DGKs5 DGKs4 DGKs3 DGKs2 DGKs1 DGKs0
H'D004 DAp W 16 16 DAp15 DAp14 DAp13 DAp12 DAp11 DAp10 DAp9 DAp8
H'D005 DAp7 DAp6 DAp5 DAp4 DAp3 DAp2 DAp1 DAp0
H'D006 DBp W 16 16 DBp15 DBp14 DBp13 DBp12 DBp11 DBp10 DBp9 DBp8
H'D007 DBp7 DBp6 DBp5 DBp4 DBp3 DBp2 DBp1 DBp0
H'D008 DAs W 16 16 DAs15 DAs14 DAs13 DAs12 DAs11 DAs10 DAs9 DAs8
H'D009 DAs7 DAs6 DAs5 DAs4 DAs3 DAs2 DAs1 DAs0
H'D00A DBs W 16 16 DBs15 DBs14 DBs13 DBs12 DBs11 DBs10 DBs9 DBs8
H'D00B DBs7 DBs6 DBs5 DBs4 DBs3 DBs2 DBs1 DBs0
H'D00C DOfp W 16 16 DOfp15 DOfp14 DOfp13 DOfp12 DOfp11 DOfp10 DOfp9 DOfp8
H'D00D DOfp7 DOfp6 DOfp5 DOfp4 DOfp3 DOfp2 DOfp1 DOfp0
H'D00E DOfs W 16 16 DOfs15 DOfs14 DOfs13 DOfs12 DOfs11 DOfs10 DOfs9 DOfs8
H'D00F DOfs7 DOfs6 DOfs5 DOfs4 DOfs3 DOfs2 DOfs1 DOfs0
Drum digital
filter
H'D010 CGKp W 16 16 CGKp15 CGKp14 CGKp13 CGKp12 CGKp11 CGKp10 CGKp9 CGKp8
H'D011 CGKp7 CGKp6 CGKp5 CGKp4 CGKp3 CGKp2 CGKp1 CGKp0
H'D012 CGKs W 16 16 CGKs15 CGKs14 CGKs13 CGKs12 CGKs11 CGKs10 CGKs9 CGKs8
H'D013 CGKs7 CGKs6 CGKs5 CGKs4 CGKs3 CGKs2 CGKs1 CGKs0
H'D014 CAp W 16 16 CAp15 CAp14 CAp13 CAp12 CAp11 CAp10 CAp9 CAp8
H'D015 CAp7 CAp6 CAp5 CAp4 CAp3 CAp2 CAp1 CAp0
H'D016 CBp W 16 16 CBp15 CBp14 CBp13 CBp12 CBp11 CBp10 CBp9 CBp8
H'D017 CBp7 CBp6 CBp5 CBp4 CBp3 CBp2 CBp1 CBp0
H'D018 CAs W 16 16 CAs15 CAs14 CAs13 CAs12 CAs11 CAs10 CAs9 CAs8
H'D019 CAs7 CAs6 CAs5 CAs4 CAs3 CAs2 CAs1 CAs0
H'D01A CBs W 16 16 CBs15 CBs14 CBs13 CBs12 CBs11 CBs10 CBs9 CBs8
H'D01B CBs7 CBs6 CBs5 CBs4 CBs3 CBs2 CBs1 CBs0
H'D01C COfp W 16 16 COfp15 COfp14 COfp13 COfp12 COfp11 COfp10 COfp9 COfp8
H'D01D COfp7 COfp6 COfp5 COfp4 COfp3 COfp2 COfp1 COfp0
H'D01E COfs W 16 16 COfs15 COfs14 COfs13 COfs12 COfs11 COfs10 COfs9 COfs8
H'D01F COfs7 COfs6 COfs5 COfs4 COfs3 COfs2 COfs1 COfs0
Capstan
digital filter
H'D020 DZs W 16 16 DZs11 DZs10 DZs9 DZs8
H'D021 DZs7 DZs6 DZs5 DZs4 DZs3 DZs2 DZs1 DZs0
H'D022 DZp W 16 16 DZp11 DZp10 DZp9 DZp8
H'D023 DZp7 DZp6 DZp5 DZp4 DZp3 DZp2 DZp1 DZp0
H'D024 CZs W 16 16 CZs11 CZs10 CZs9 CZs8
H'D025 CZs7 CZs6 CZs5 CZs4 CZs3 CZs2 CZs1 CZs0
H'D026 CZp W 16 16 CZp11 CZp10 CZp9 CZp8
H'D027 CZp7 CZp6 CZp5 CZp4 CZp3 CZp2 CZp1 CZp0
Digital filter
Rev. 1.0, 02/ 00, page 978 of 1141
Address*1Register
Name R/W Access Bus
Width76543210Module
Name
H'D028 DFIC R/W 8 16 DROV DPHA DZPON DZSON DSG2 DSG1 DSG0
H'D029 CFIC R/W 8 CROV CPHA CZPON CZSON CSG2 CSG1 CSG0
H'D02A DFUCR R/W 8 16 PTON CP/
'3
CFEPS DFEPS CFESS DFESS
Digital filter
H'D030 DFPR W 16 16 DFPR15 DFPR14 DFPR13 DFPR12 DFPR11 DFPR10 DFPR9 DFPR8
H'D031 DFPR7 DFPR6 DFPR5 DFPR4 DFPR3 DFPR2 DFPR1 DFPR0
H'D032 DFER R/W 16 16 DFER15 DFER14 DFER13 DFER12 DFER11 DFER10 DFER9 DFER8
H'D033 DFER7 DFER6 DFER5 DFER4 DFER3 DFER2 DFER1 DFER0
H'D034 DFRUDR W 16 16 DFRUDR15 DFRUDR14 DFRUDR13 DFRUDR12 DFRUDR11 DFRUDR10 DFRUDR9 DFRUDR8
H'D035 DFRUDR7 DFRUDR6 DFRUDR5 DFRUDR4 DFRUDR3 DFRUDR2 DFRUDR1 DFRUDR0
H'D036 DFRLDR W 16 16 DFRLDR15 DFRLDR14 DFRLDR13 DFRLDR12 DFRLDR11 DFRLDR10 DFRLDR9 DFRLDR8
H'D037 DFRLDR7 DFRLDR6 DFRLDR5 DFRLDR4 DFRLDR3 DFRLDR2 DFRLDR1 DFRLDR0
H'D038 DFVCR R/W 8 16 DFCS1 DFCS0 DFOVF DFRFON DF-R/UNR DPCNT DFRCS1 DFRCS0
H'D039 DPGCR R/W 8 16 DPCS1 DPCS0 DPOVF N/V HSWES 
H'D03A DPPR2 W 16 16 DPPR15 DPPR14 DPPR13 DPPR12 DPPR11 DPPR10 DPPR9 DPPR8
H'D03B DPPR7 DPPR6 DPPR5 DPPR4 DPPR3 DPPR2 DPPR1 DPPR0
H'D03C DPPR1 W 8 16 DPPR19 DPPR18 DPPR17 DPPR16
H'D03D DPER1 W 8 16 DPER19 DPER18 DPER17 DPER16
H'D03E DPER15 DPER14 DPER13 DPER12 DPER11 DPER10 DPER9 DPER8
H'D03F
DPER2 W 16 16
DPER7 DPER6 DPER5 DPER4 DPER3 DPER2 DPER1 DPER0
Drum error
detector
H'D040
to
H'D04F
H'D050 CFPR W 16 16 CFPR15 CFPR14 CFPR13 CFPR12 CFPR11 CFPR10 CFPR9 CFPR8
H'D051 CFPR7 CFPR6 CFPR5 CFPR4 CFPR3 CFPR2 CFPR1 CFPR0
H'D052 CFER R/W 16 16 CFER15 CFER14 CFER13 CFER12 CFER11 CFER10 CFER9 CFER8
H'D053 CFER7 CFER6 CFER5 CFER4 CFER3 CFER2 CFER1 CFER0
H'D054 CFRUDR W 16 16 CFRUDR15 CFRUDR14 CFRUDR13 CFRUDR12 CFRUDR11 CFRUDR10 CFRUDR9 CFRUDR8
H'D055 CFRUDR7 CFRUDR6 CFRUDR5 CFRUDR4 CFRUDR3 CFRUDR2 CFRUDR1 CFRUDR0
H'D056 CFRLDR W 16 16 CFRLDR15 CFRLDR14 CFRLDR13 CFRLDR12 CFRLDR11 CFRLDR10 CFRLDR9 CFRLDR8
H'D057 CFRLDR7 CFRLDR6 CFRLDR5 CFRLDR4 CFRLDR3 CFRLDR2 CFRLDR1 CFRLDR0
H'D058 CFVCR R/W 8 CFCS1 CFCS0 CFOVF CFRFON CF-R/UNR CPCNT CFRCS1 CFRCS0
H'D059 CPGCR R/W 8 16 CPCS1 CPCS0 CPOVF CR/RF SELCFG2 
H'D05A CPPR2 W 16 16 CPH15 CPH14 CPH13 CPH12 CPH11 CPH10 CPH9 CPH8
H'D05B CPH7 CPH6 CPH5 CPH4 CPH3 CPH2 CPH1 CPH0
H'D05C CPPR1 W 8 16 CPH19 CPH18 CPH17 CPH16
H'D05D CPER1 W 8 16 CPER19 CPER18 CPER17 CPER16
H'D05E CPER2 W 16 16 CPER15 CPER14 CPER13 CPER12 CPER11 CPER10 CPER9 CPER8
H'D05F CPER7 CPER6 CPER5 CPER4 CPER3 CPER2 CPER1 CPER0
Capstan error
detector
H'D060 HSM1 R/W 8 16 FLB FLA EMPB EMPA OVWB OVWA CLRB CLRA
H'D061 HSM2 R/W 8 FRT FGR2OFF LOP EDG ISEL1 SOFG OFG VFF/NFF
H'D062 HSLP R/W 8 16 LOB3 LOB2 LOB1 LOB0 LOA3 LOA2 LOA1 LOA0
H'D063
H'D064 FPDRA W 16 16 ADTRGA STRIGA NarrowFFA VFFA AFFA VpulseA MlevelA
H'D065 PPGA7 PPGA6 PPGA5 PPGA4 PPGA3 PPGA2 PPGA1 PPGA0
H'D066 FTPRA*2W 16 16 FTPRA15 FTPRA14 FTPRA13 FTPRA12 FTPRA11 FTPRA10 FTPRA9 FTPRA8
H'D066 FTCTR*2R 16 FTCTR15 FTCTR14 FTCTR13 FTCTR12 FTCTR11 FTCTR10 FTCTR9 FTCTR8
H'D067 FTPRA*2W 16 16 FTPRA7 FTPRA6 FTPRA5 FTPRA4 FTPRA3 FTPRA2 FTPRA1 FTPRA0
H'D067 FTCTR*2R 16 FTCTR7 FTCTR6 FTCTR5 FTCTR4 FTCTR3 FTCTR2 FTCTR1 FTCTR0
H'D068 FPDRB W 16 16 ADTRGB STRIGB NarrowFFB VFFB AFFB VpulseB MlevelB
H'D069 PPGB7 PPGB6 PPGB5 PPGB4 PPGB3 PPGB2 PPGB1 PPGB0
H'D06A FTPRB W 16 16 FTPRB15 FTPRB14 FTPRB13 FTPRB12 FTPRB11 FTPRB10 FTPRB9 FTPRB8
H'D06B FTPRB7 FTPRB6 FTPRB5 FTPRB4 FTPRB3 FTPRB2 FTPRB1 FTPRB0
HSW timing
generator
Rev. 1.0, 02/ 00, page 979 of 1141
Address*1Register
Name R/W Access Bus
Width76543210Module
Name
H'D06C DFCRA*2W 8 16 ISEL2 CCLR CKSL DFCRA4 DFCRA3 DFCRA2 DFCRA1 DFCRA0
H'D06C DFCTR*2R8 DFCTR4 DFCTR3 DFCTR2 DFCTR1 DFCTR0
H'D06D DFCRB W 8 16 DFCRB4 DFCRB3 DFCRB2 DFCRB1 DFCRB0
HSW timing
generator
H'D06E CHCR W 8 16 V/N HSWPOL CRH HAH SIG3 SIG2 SIG1 SIG0 4 head
special-
effects
playback
H'D06F ADDVR R/W 8 HMSK HIZ CUT VPON POL Additional V
H'D070 XDR W 16 16 XD11 XD10 XD9 XD8
H'D071 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0
H'D072 TRDR W 16 16 TRD11 TRD10 TRD9 TRD8
H'D073 TRD7 TRD6 TRD5 TRD4 TRD3 TRD2 TRD1 TRD0
H'D074 XTCR R/W 8 16 CAPRF AT/
08
TRK/
;
EXC/REF XCS DVREF1 DVREF0
X-value, TRK-
value
H'D075
to
H'D077
H'D078 DPWDR R/W 16 16 DPWDR11 DPWDR10 DPWDR9 DPWDR8
H'D079 DPWDR7 DPWDR6 DPWDR5 DPWDR4 DPWDR3 DPWDR2 DPWDR1 DPWDR0
H'D07A DPWCR W 8 16 DPOL DDC DHIZ DH/L DSF/DF DCK2 DCK1 DCK0
Drum 12-bit
PWM
H'D07B CPWCR W 8 CPOL CDC CHIZ CH/L CSF/DF CCK2 CCK1 CCK0
H'D07C CPWDR R/W 16 16 CPWDR11 CPWDR10 CPWDR9 CPWDR8
H'D07D CPWDR7 CPWDR6 CPWDR5 CPWDR4 CPWDR3 CPWDR2 CPWDR1 CPWDR0
Capstan 12-
bit PWM
H'D07E
to
H'D07F
H'D080 CTCR W 8 16 NT/PL FSLC FSLB FSLA CCS LCTL UNCTL SLWM
H'D081 CTLM R/W 8 ASM REC/
3%
FW/RV MD4 MD3 MD2 MD1 MD0
H'D082 RCDR1 W 16 16 CMT1B CMT1A CMT19 CMT18
H'D083 CMT17 CMT16 CMT15 CMT14 CMT13 CMT12 CMT11 CMT10
H'D084 RCDR2 W 16 16 CMT2B CMT2A CMT29 CMT28
H'D085 CMT27 CMT26 CMT25 CMT24 CMT23 CMT22 CMT21 CMT20
H'D086 RCDR3 W 16 16 CMT3B CMT3A CMT39 CMT38
H'D087 CMT37 CMT36 CMT35 CMT34 CMT33 CMT32 CMT31 CMT30
H'D088 RCDR4 W 16 16 CMT4B CMT4A CMT49 CMT48
H'D089 CMT47 CMT46 CMT45 CMT44 CMT43 CMT42 CMT41 CMT40
H'D08A RCDR5 W 16 16 CMT5B CMT5A CMT59 CMT58
H'D08B CMT57 CMT56 CMT55 CMT54 CMT53 CMT52 CMT51 CMT50
H'D08C DI/O R/W 8 16 VCTR2 VCTR1 VCTR0 BPON BPS BPF DI/O
H'D08D BTPR R/W 8 LSP7 LSP6 LSP5 LSP4 LSP3 LSP2 LSP1 LSP0
CTL circuit
H'D08E
to
H'D08F
H'D090 RFD W 16 16 REF15 REF14 REF13 REF12 REF11 REF10 REF9 REF8
H'D091 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0
H'D092 CRF W 16 16 CRF15 CRF14 CRF13 CRF12 CRF11 CRF10 CRF9 CRF8
H'D093 CRF7 CRF6 CRF5 CRF4 CRF3 CRF2 CRF1 CRF0
H'D094 RFC R/W 16 16 RFC15 RFC14 RFC13 RFC12 RFC11 RFC10 RFC9 RFC8
H'D095 RFC7 RFC6 RFC5 RFC4 RFC3 RFC2 RFC1 RFC0
H'D096 RFM R/W 8 16 RCS VNA CVS REX CRD OD/EV VST VEG
H'D097 RFM2 R/W 8 FDS
Reference
signal
generator
Rev. 1.0, 02/ 00, page 980 of 1141
Address*1Register
Name R/W Access Bus
Width76543210Module
Name
H'D098 CTVC R/W 8 16 CEX CEG CFG HSW CTL
H'D099 CTLR W 8 CTL7 CTL6 CTL5 CTL4 CTL3 CTL2 CTL1 CTL0
H'D09A CDVC R/W 8 16 MCGin CMK CMN DVTRG CRF CPS1 CPS0
H'D09B CDIVR1 W 8 CDV16 CDV15 CDV14 CDV13 CDV12 CDV11 CDV10
H'D09C CDIVR2 W 8 16 CDV26 CDV25 CDV24 CDV23 CDV22 CDV21 CDV20
H'D09D CTMR W 8 CPM5 CPM4 CPM3 CPM2 CPM1 CPM0
H'D09E FGCR W 8 16 DRF
Frequency
divider
H'D09F
H'D0A0 SPMR R/W 8 8 CTLSTOP CFGCOMP 
H'D0A1
to
H'D0A2
H'D0A3 SVMCR R/W 8 8 SVMCR5 SVMCR4 SVMCR3 SVMCR2 SVMCR1 SVMCR0
H'D0A4 CTLGR R/W 8 8 CTLE/
$
CTLFB CTLGR3 CTLGR2 CTLGR1 CTLGR0
Servo port
control
H'D0A5
to
H'D0AF
H'D0B0 VTR W 8 16 VTR5 VTR4 VTR3 VTR2 VTR1 VTR0
H'D0B1 HTR W 8 16 HTR3 HTR2 HTR1 HTR0
H'D0B2 HRTR W 8 16 HRTR7 HRTR6 HRTR5 HRTR4 HRTR3 HRTR2 HRTR1 HRTR0
H'D0B3 HPWR W 8 16 HPWR3 HPWR2 HPWR1 HPWR0
H'D0B4 NWR W 8 16 NWR5 NWR4 NWR3 NWR2 NWR1 NWR0
H'D0B5 NDR W 8 16 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0
H'D0B6 SYNCR R/W 8 16 NIS/VD NOIS FLD SYCT
Sync detector
(servo)
H'D0B7
H'D0B8 SIENR1 R/W 8 16 IEDRM3 IEDRM2 IEDRM1 IECAP3 IECAP2 IECAP1 IEHSW2 IEHSW1
H'D0B9 SIENR2 R/W 8 16 IESNC IECTL
H'D0BA SIRQR1 R/W 8 16 IRRDRM3 IRRDRM2 IRRDRM1 IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1
H'D0BB SIRQR2 R/W 8 16 IRRSNC IRRCTL
H'D0BC
to
H'D0E4
Servo
interrupt
control
H'D0E5 DDCSWR R/W 8 8 SWE SW IE IF 
H'D0E8 ICCR0 R/W 8 8 ICE IEIC MST TRS ACKE BBSY IRIC SCP
H'D0E9 ICSR0 R/W 8 8 ESTP STOP IRTR AASX AL AAS ADZ ACKB
H'D0EE ICDR0*3R/W 8 8 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0
H'D0EE SARX0*3SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX
H'D0EF ICMR0*3MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0
H'D0EF SAR0*3SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS
H'D0F0
to
H'D0FF
I2C interface
H'D100 TIER R/W 8 16 ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE ICSA
H'D101 TCSRX R/W 8 16 ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA
H'D102 FRCH R/W 8/16 16
H'D103 FRCL
H'D104 OCRAH*4R/W 8/16 16
H'D105 OCRAL*4
H'D104 OCRBH*4R/W 8/16 16
H'D105 OCRBL*4
H'D106 TCRX R/W 8 16 IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0
H'D107 TOCR R/W 8 16 ICSB ICSC ICSD OCRS OEA OEB OLVLA OLVLB
H'D108 ICRAH R 8/16 16
H'D109 ICRAL
Timer X1
Rev. 1.0, 02/ 00, page 981 of 1141
Address*1Register
Name R/W Access Bus
Width76543210Module
Name
H'D10A ICRBH R 8/16 16
H'D10B ICRBL
H'D10C ICRCH R 8/16 16
H'D10D ICRCL
H'D10E ICRDH R 8/16 16
H'D10F ICRDL
Timer X1
H'D110 TMB R/W 8 8 TMB17 TMBIF TMBIE TMB12 TMB11 TMB10
H'D111 TCB R 8 8 TCB17 TCB16 TCB15 TCB14 TCB13 TCB12 TCB11 TCB10
H'D111 TLB W 8 8 TLB17 TLB16 TLB15 TLB14 TLB13 TLB12 TLB11 TLB10
Timer B
H'D112 LMR R/W 8 8 LMIF LMIE LMR3 LMR2 LMR1 LMR0
H'D113 LTC R 8 8 LTC7 LTC6 LTC5 LTC4 LTC3 LTC2 LTC1 LTC0
H'D113 RCR W 8 8 RCR7 RCR6 RCR5 RCR4 RCR3 RCR2 RCR1 RCR0
Timer L
H'D114
to
H'D117
H'D118 TMRM1 R/W 8 8 CLR2 AC/BR RLD RLCK PS21 PS20 RLD/CAP CPS
H'D119 TMRM2 R/W 8 8 LAT PS11 PS10 PS31 PS30 CP/SLM CAPF SLW
H'D11A TMRCP1 R 8 8 TMRC17 TMRC16 TMRC15 TMRC14 TMRC13 TMRC12 TMRC11 TMRC10
H'D11B TMRCP2 R 8 8 TMRC27 TMRC26 TMRC25 TMRC24 TMRC23 TMRC22 TMRC21 TMRC20
H'D11C TMRL1 W 8 8 TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10
H'D11D TMRL2 W 8 8 TMR27 TMR26 TMR25 TMR24 TMR23 TMR22 TMR21 TMR20
H'D11E TMRL3 W 8 8 TMR37 TMR36 TMR35 TMR34 TMR33 TMR32 TMR31 TMR30
H'D11F TMRCS R/W 8 8 TMRI3E TMRI2E TMRI1E TMRI3 TMRI2 TMRI1 
Timer R
H'D120 PWDRL W 8 8 PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
H'D121 PWDRU W 8 8 PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0
H'D122 PWCR R/W 8 8 PWMCR0
14-bit PWM
H'D123
to
H'D125
H'D126 PWR0 W 8 8 PW 07 PW06 PW05 PW04 PW03 PW02 PW01 PW00
H'D127 PWR1 W 8 8 PW17 PW16 PW15 PW14 PW13 PW12 PW11 PW10
H'D128 PWR2 W 8 8 PW 27 PW26 PW25 PW24 PW23 PW22 PW21 PW20
H'D129 PWR3 W 8 8 PW 37 PW36 PW35 PW34 PW33 PW32 PW31 PW30
H'D12A PW8CR R/W 8 8 PWC3 PWC2 PWC1 PWC0
8-bit PWM
H'D12B
H'D12C ICR1 R 8 8 ICR17 ICR16 ICR15 ICR14 ICR13 ICR12 ICR11 ICR10
H'D12D PCSR R/W 8 8 ICIF ICIE ICEG NCon/off DCS2 DCS1 DCS0
PSU
H'D12E
to
H'D12F
H'D130 ADRH R 16 8 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2
H'D131 ADRL ADR1 ADR0 
H'D132 AHRH R 16 AHR9 AHR8 AHR7 AHR6 AHR5 AHR4 AHR3 AHR2
H'D133 AHRL AHR1 AHR0 
H'D134 ADCR R/W 8 CK HCH1 HCH0 SCH3 SCH2 SCH1 SCH0
H'D135 ADCSR R/W 8 SEND HEND ADIE SST HST BUSY SCNL
H'D136 ADTSR R/W 8 TRGS1 TRGS0
A/D
H'D137
H'D138 TLK W 8/16 16 TLR27 TLR26 TLR25 TLR24 TLR23 TLR22 TLR21 TLR20
H'D138 TCK R 8/16 TDR27 TDR26 TDR25 TDR24 TDR23 TDR22 TDR21 TDR20
H'D139 TLJ W 8/16 TLR17 TLR16 TLR15 TLR14 TLR13 TLR12 TLR11 TLR10
H'D139 TCJ R 8/16 TDR17 TDR16 TDR15 TDR14 TDR13 TDR12 TDR11 TDR10
H'D13A TMJ R/W 8/16 PS11 PS10 ST 8/16 PS21 PS20 TGL T/R
Timer J
Rev. 1.0, 02/ 00, page 982 of 1141
Address*1Register
Name R/W Access Bus
Width76543210Module
Name
H'D13B TMJC R/W 8/16 16 BUZZ1 BUZZ0 MON1 MON0 EXN TMJ2IE TMJ1IE PS22
H'D13C TMJS R/W 8/16 TMJ2I TMJ1I 
Timer J
H'D13D
to
H'D147
H'D148 SMR1 R/W 8 8 C/
$
CHR PE O/
(
STOP MP CKS1 CKS0
H'D149 BRR1 R/W 8
H'D14A SCR1 R/W 8 TIE RIE TE RE MPIE TEIE CKE1 CKE0
H'D14B TDR1 R/W 8
H'D14C SSR1 R/W 8 TDRE RDRF ORER FER PER TEND MPB MPBT
H'D14D RDR1 R 8
H'D14E SCMR1 R/W 8 SDIR SINV SMIF
Clock
synchronous/
asynchronou
s SCI
H'D14F
to
H'D157
H'D158 ICCR1 R/W 8 8 ICE IEIC MST TRS ACKE BBSY IRIC SCP
H'D159 ICSR1 R/W 8 ESTP STOP IRTR AASX AL AAS ADZ ACKB
H'D15A
to
H'D15D
H'D15E ICDR1*3R/W 8 8 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0
H'D15E SARX1*3R/W 8 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX
H'D15F ICMR1*3R/W 8 MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0
H'D15F SAR1*3R/W 8 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS
I2C interface
H'D160
to
H'D1FF
H'D200 CLINE1 R/W 8/16 16 BPTN1 SZ1 CLU11 CLU12 KR1 KG1 KB1 KLU1 OSD
H'D201 CLINE2 R/W 8/16 16 BPTN2 SZ2 CLU21 CLU22 KR2 KG2 KB2 KLU2
H'D202 CLINE3 R/W 8/16 16 BPTN3 SZ3 CLU31 CLU32 KR3 KG3 KB3 KLU3
H'D203 CLINE4 R/W 8/16 16 BPTN4 SZ4 CLU41 CLU42 KR4 KG4 KB4 KLU4
H'D204 CLINE5 R/W 8/16 16 BPTN5 SZ5 CLU51 CLU52 KR5 KG5 KB5 KLU5
H'D205 CLINE6 R/W 8/16 16 BPTN6 SZ6 CLU61 CLU62 KR6 KG6 KB6 KLU6
H'D206 CLINE7 R/W 8/16 16 BPTN7 SZ7 CLU71 CLU72 KR7 KG7 KB7 KLU7
H'D207 CLINE8 R/W 8/16 16 BPTN8 SZ8 CLU81 CLU82 KR8 KG8 KB8 KLU8
H'D208 CLINE9 R/W 8/16 16 BPTN9 SZ9 CLU91 CLU92 KR9 KG9 KB9 KLU9
H'D209 CLINE10 R/W 8/16 16 BPTN10 SZ10 CLU101 CLU102 KR10 KG10 KB10 KLU10
H'D20A CLINE11 R/W 8/16 16 BPTN11 SZ11 CLU111 CLU112 KR11 KG11 KB11 KLU11
H'D20B CLINE12 R/W 8/16 16 BPTN12 SZ12 CLU121 CLU122 KR12 KG12 KB12 KLU12
H'D20C VPOSH R/W 8/16 16 VSPC2 VSPC1 VSPC0 VP8
H'D20D VPOSL R/W 8/16 16 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0
H'D20E HPOS R/W 8/16 16 HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0
H'D20F DOUT R/W 8/16 16 RGBC YCOC DOBC DSEL CRSEL 
H'D210 DCNTLH R/W 8/16 16 CDSPON DISPM LACEM BLKS OSDON EDGE EDGC
H'D211 DCNTLL R/W 8/16 16 BR BG BB BLU1 BLU0 CAMP KAMP BAMP
H'D212 DFORMH R/W 8/16 16 TVM2 TVM1 TVM0 FSCIN FSCEXT OSDVE OSDVF
H'D213 DFORML R/W 8/16 16 DTMV LDREQ VACS
H'D214
to
H'D21F
H'D220 SEVFD R/W 8/16 16 EVNIE EVNIF STBE4 STBE3 ST BE2 STBE1 STBE0 Data slicer
H'D221 SLVLE2 SLVLE1 SLVLE0 DLYE4 DLYE3 DLYE2 DLYE1 DLYE0
H'D222 SODFD R/W 8/16 ODDIE ODDIF STBO4 STBO3 STBO2 STBO1 STBO0
H'D223 SLVL02 SLVL01 SLVL00 DLYO4 DLYO3 DLYO2 DLYO1 DLYO0
H'D224 SLINE1 R/W 8/16 SENBL1 SFLD1 SLINE14 SLINE13 SLINE12 SLINE11 SLINE10
Rev. 1.0, 02/ 00, page 983 of 1141
Address*1Register
Name R/W Access Bus
Width76543210Module
Name
H'D225 SLINE2 R/W 8/16 16 SENBL2 SFLD2 SLINE24 SLINE23 SLINE22 SLINE21 SLINE20
H'D226 SLINE3 R/W 8/16 SENBL3 SFLD3 SLINE34 SLINE33 SLINE32 SLINE31 SLINE30
H'D227 SLINE4 R/W 8/16 SENBL4 SFLD4 SLINE44 SLINE43 SLINE42 SLINE41 SLINE40
H'D228 SDTCT1 R 8/16 CRDF1 SBDF1 ENDF1 CRIC13 CRIC12 CRIC11 CRIC10
H'D229 SDTCT2 R 8/16 CRDF2 SBDF2 ENDF2 CRIC23 CRIC22 CRIC21 CRIC20
H'D22A SDTCT3 R 8/16 CRDF3 SBDF3 ENDF3 CRIC33 CRIC32 CRIC31 CRIC30
H'D22B SDTCT4 R 8/16 CRDF4 SBDF4 ENDF4 CRIC43 CRIC42 CRIC41 CRIC40
H'D22C SDATA1 R 8/16
H'D22D
H'D22E SDATA2 R 8/16
H'D22F
H'D230 SDATA3 R 8/16
H'D231
H'D232 SDATA4 R 8/16
H'D233
Data slicer
H'D234
to
H'D23F
H'D240 SEPIMR R/W 8 16 CCMPV1 CCMPV0 CCMPSL SYNCT VSEL DLPFON FRQSEL
H'D241 SEPCR R/W 8 AFCVIE AFCVIF VCKSL VCMPON HCKSEL HHKON FLD
H'D242 SEPACR R/W 8 NDETIE NDETIF HSEL ARST 
H'D243 HVTHR W 8 HVTH4 HVTH3 HVTH2 HVTH1 HVTH0
H'D244 VVTHR W 8 VVTH7 VVTH6 VVTH5 VVTH4 VVTH3 VVTH2 VVTH1 VVTH0
H'D245 FWIDR W 8 FWID3 FWID2 FWID1 FWID0
H'D246 HCMMR W 16 HC8 HC7 HC6 HC5 HC4 HC3 HC2 HC1
H'D247 HC0 HM6 HM5 HM4 HM3 HM2 HM1 HM0
NDETC R 8 NC7 NC6 NC5 NC4 NC3 NC2 NC1 NC0H'D248
NDETR W 8 NR7 NR6 NR5 NR4 NR3 NR2 NR1 NR0
H'D249 DDETWR W 8 SRWDE1 SRWDE0 SRWDS1 SRWDS0 CRWDE1 CRWDE0 CRWDS1 CRWDS0
H'D24A INFRQR W 8 VFS2 VFS1 HFS 
Sync
separator
H'D24B
to
H'FFAF
H'FFB0 TAR0 R/W 8 8 A23 A22 A21 A20 A19 A18 A17 A16
H'FFB1 A15 A14 A13 A12 A11 A10 A9 A8
H'FFB2 A7A6A5A4A3A2A1
H'FFB3 TAR1 R/W 8 A23 A22 A21 A20 A19 A18 A17 A16
H'FFB4 A15 A14 A13 A12 A11 A10 A9 A8
H'FFB5 A7A6A5A4A3A2A1
H'FFB6 TAR2 R/W 8 A23 A22 A21 A20 A19 A18 A17 A16
H'FFB7 A15 A14 A13 A12 A11 A10 A9 A8
H'FFB8 A7A6A5A4A3A2A1
H'FFB9 ATCR R/W 8 − TRC2 TRC1 TRC0
ATC
H'FFBA TMA R/W 8 8 TMAOV TMAIE TMA3 TMA2 TMA1 TMA0
H'FFBB TCA R 8 TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0
Timer A
H'FFBC WTCSR R/W 8/16 16 OVF WT/
,7
TME RST/
10,
CKS2 CKS1 CKS0
H'FFBD WTCNT*5R/W 8/16
WDT
H'FFBE
to
H'FFBF
H'FFC0 PDR0 R 8 8 PDR07 PDR06 PDR05 PDR04 PDR03 PDR02 PDR01 PDR00
H'FFC1 PDR1 R/W 8 PDR17 PDR16 PDR15 PDR14 PDR13 PDR12 PDR11 PDR10
H'FFC2 PDR2 R/W 8 PDR27 PDR26 PDR25 PDR24 PDR23 PDR22 PDR21 PDR20
Port da t a
register
Rev. 1.0, 02/ 00, page 984 of 1141
Address*1Register
Name R/W Access Bus
Width76543210Module
Name
H'FFC3 PDR3 R/W 8 PDR37 PDR36 PDR35 PDR34 PDR33 PDR32 PDR31 PDR30
H'FFC4 PDR4 R/W 8
8
PDR47 PDR46 PDR45 PDR44 PDR43 PDR42 PDR41 PDR40
Port da t a
register
H'FFC5
H'FFC6 PDR6 R/W 8 PDR67 PDR66 PDR65 PDR64 PDR63 PDR62 PDR61 PDR60
H'FFC7 PDR7 R/W 8 PDR77 PDR76 PDR75 PDR74 PDR73 PDR72 PDR71 PDR70
H'FFC8 PDR8 R/W 8
8
PDR87 PDR86 PDR85 PDR84 PDR83 PDR82 PDR81 PDR80
H'FFC9
to
H'FFCC
H'FFCD PMR0 R/W 8 8 PMR07 PMR06 PMR05 PMR04 PMR03 PMR02 PMR01 PMR00
H'FFCE PMR1 R/W 8 PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10
Port mode
register
H'FFCF
H'FFD0 PMR3 R/W 8 8 PMR37 PMR36 PMR35 PMR34 PMR33 PMR32 PMR31 PMR30
H'FFD1 PCR1 W 8 8 PCR17 PCR16 PCR15 PCR14 PCR13 PCR12 PCR11 PCR10
H'FFD2 PCR2 W 8 PCR27 PCR26 PCR25 PCR24 PCR23 PCR22 PCR21 PCR20
Port control
register
H'FFD3 PCR3 W 8 PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 PCR30
H'FFD4 PCR4 W 8 PCR47 PCR46 PCR45 PCR44 PCR43 PCR42 PCR41 PCR40
H'FFD5
H'FFD6 PCR6 W 8 8 PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60
H'FFD7 PCR7 W 8 PCR77 PCR76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70
H'FFD8 PCR8 W 8 PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80
H'FFD9 PMRA R/W 8 8 PMRA7 PMRA6 
H'FFDA PMRB R/W 8 PMRB7 PMRB6 PMRB5 PMRB4 
H'FFDB PMR4 R/W 8 PMR47 PMR40
H'FFDC
H'FFDD PMR6 R/W 8 8 PMR67 PMR66 PMR65 PMR64 PMR63 PMR62 PMR61 PMR60
H'FFDE PMR7 R/W 8 PMR77 PMR76 PMR75 PMR74 PMR73 PMR72 PMR71 PMR70
H'FFDF PMR8 R/W 8 PMR87 PMR86 PMR85 PMR84 PMR83 PMR82 PMR81 PMR80
H'FFE0 PMRC R/W 8 PMRC5 PMRC4 PMRC3 PMRC1
Port mode
register
H'FFE1 PUR1 R/W 8 8 PUR17 PUR16 PUR15 PUR14 PUR13 PUR12 PUR11 PUR10
H'FFE2 PUR2 R/W 8 PUR27 PUR26 PUR25 PUR24 PUR23 PUR22 PUR21 PUR20
H'FFE3 PUR3 R/W 8 PUR37 PUR36 PUR35 PUR34 PUR33 PUR32 PUR31 PUR30
Port pull-up
select
register
H'FFE4 RTPEGR R/W 8 RTPEGR1 RTPEGR0
H'FFE5 RTPSR1 R/W 8 RTPSR17 RTPSR16 RTPSR15 RTPSR14 RTPSR13 RTPSR12 RTPSR11 RTPSR10
H'FFE6 RTPSR2 R/W 8 RTPSR27 RTPSR26 RTPSR25 RTPSR24 
Realtime port
H'FFE7
H'FFE8 SYSCR R/W 8 8 INTM1 INTM0 XRST 
H'FFE9 MDCR R 8 MDS0
H'FFEA SBYCR R/W 8 SSBY STS2 STS1 STS0 SCK1 SCK0
H'FFEB LPWRCR R/W 8 DTON LSON NESEL SA1 SA0
H'FFEC MSTPCRH R/W 8 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8
H'FFED MSTPCRL R/W 8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
H'FFEE STCR R/W 8 IICX1 IICX0 FLSHE OSROME 
System
control
register
H'FFEF
H'FFF0 IEGR R/W 8 8 IRQ5EG IRQ4EG IRQ3EG IRQ2EG IRQ1EG IRQ0EG1 IRQ0EG0 IRQ edge
H'FFF1 IENR R/W 8 IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E IRQ enable
H'FFF2 IRQR R/W 8 IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F IRQ status
H'FFF3 ICRA R/W 8 ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 ICRA0
H'FFF4 ICRB R/W 8 ICRB7 ICRB6 ICRB5 ICRB4 ICRB3 ICRB2 ICRB1 ICRB0
H'FFF5 ICRC R/W 8 ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0
IRQ priority
control
H'FFF6 ICRD R/W 8 ICRD7 ICRD6 ICRD5 ICRD4 ICRD3 ICRD2 ICRD1 ICRD0
H'FFF7 
Rev. 1.0, 02/ 00, page 985 of 1141
Address*1Register
Name R/W Access Bus
Width76543210Module
Name
H'FFF8 FLMCR1 R/W 8 8 FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1
H'FFF9 FLMCR2 R/W 8 8 FLER SWE2 ESU2 PSU2 EV2 PV2 E2 P2
H'FFFA EBR1 R/W 8 8 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
H'FFFB EBR2 R/W 8 8 EB15 EB14 EB13 EB12 EB11 EB10 EB9 EB8
Flash
memory
H'FFFC 
H'FFFD 
H'FFFE 
H'FFFF 
Notes: 1. Lower 16bits of the address.
2. Assigned to the same address.
3. Access varies depending on the ICE bit.
4. OCRA and OCRB address are the same, which can be swi tched by the OCSR bit in TOCR.
5. The address is H'FFBC when written to. WTCNT and WTCSR are assigned to the s ame addres s. Refer to section 17.2.4, Notes
on Register Access.
Rev. 1.0, 02/ 00, page 986 of 1141
B.2 Fu n c t i o n Li st
H'D000 to H'D001: Drum Phase Gain Constant DGKp: Dr um Digital Filter
Bit
Initial value
R/W *
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
:
:
:
DGKp15 DGKp14 DGKp13 DGKp12 DGKp11 DGKp10 DGKp9 DGKp8 DGKp7 DGKp6 DGKp5 DGKp4 DGKp3 DGKp2 DGKp1 DGKp0
H'D002 to H'D003: Drum Speed Gain Constant DGKs: Drum Digital Filter
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
DGKs15 DGKs14 DGKs13 DGKs12 DGKs11 DGKs10 DGKs9 DGKs8 DGKs7 DGKs6 DGKs5 DGKs4 DGKs3 DGKs2 DGKs1 DGKs0
Bit
Initial value
R/W
:
:
:
H'D004 to H'D005: Drum Phase Coefficient A DAp: Drum Digi t a l Filter
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
DAp15 DAp14 DAp13 DAp12 DAp11 DAp10 DAp9 DAp8 DAp7 DAp6 DAp5 DAp4 DAp3 DAp2 DAp1 DAp0
Bit
Initial value
R/W
:
:
:
H'D006 to H'D007: Drum Phase Coefficient B DBp: Dr um Digital Filter
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
DBp15 DBp14 DBp13 DBp12 DBp11 DBp10 DBp9 DBp8 DBp7 DBp6 DBp5 DBp4 DBp3 DBp2 DBp1 DBp0
Bit
Initial value
R/W
:
:
:
H'D008 to H'D009: Drum Speed Coefficient A DAs: Drum Di g i t al Filter
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
DAs15 DAs14 DAs13 DAs12 DAs11 DAs10 DAs9 DAs8 DAs7 DAs6 DAs5 DAs4 DAs3 DAs2 DAs1 DAs0
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 987 of 1141
H'D00A to H'D00B: Drum Speed Coefficient B DBs: Drum Digital Filter
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
DBs15 DBs14 DBs13 DBs12 DBs11 DBs10 DBs9 DBs8 DBs7 DBs6 DBs5 DBs4 DBs3 DBs2 DBs1 DBs0
Bit
Initial value
R/W
:
:
:
H'D00C to H'D00D: Drum Phase Offset DOfp: Drum Digital Filter
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
DOfp15 DOfp14 DOfp13 DOfp12 DOfp11 DOfp10 DOfp9 DOfp8 DOfp7 DOfp6 DOfp5 DOfp4 DOfp3 DOfp2 DOfp1 DOfp0
Bit
Initial value
R/W
:
:
:
H'D00E to H'D00F: Capstan Speed Offset DOfs: Drum Digital Filter
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
DOfs15 DOfs14 DOfs13 DOfs12 DOfs11 DOfs10 DOfs9 DOfs8 DOfs7 DOfs6 DOfs5 DOfs4 DOfs3 DOfs2 DOfs1 DOfs0
Bit
Initial value
R/W
:
:
:
H'D010 to H'D011: Capstan Phase Gain Constant CGKp: Capstan Di gital Filter
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
CGKp15 CGKp14 CGKp13 CGKp12 CGKp11 CGKp10 CGKp9 CGKp8 CGKp7 CGKp6 CGKp5 CGKp4 CGKp3 CGKp2 CGKp1 CGKp0
Bit
Initial value
R/W
:
:
:
H'D012 to H'D013: Capstan Speed Gain Constant CGKs: Capstan Digital Filter
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
CGKs15 CGKs14 CGKs13 CGKs12 CGKs11 CGKs10 CGKs9 CGKs8 CGKs7 CGKs6 CGKs5 CGKs4 CGKs3 CGKs2 CGKs1 CGKs0
Bit
Initial value
R/W
:
:
:
H'D014 to H'D015: Capstan Phase Coefficient A CAp: Capsta n Di g i t a l Filter
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
CAp15 CAp14 CAp13 CAp12 CAp11 CAp10 CAp9 CAp8 CAp7 CAp6 CAp5 CAp4 CAp3 CAp2 CAp1 CAp0
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 988 of 1141
H'D016 to H'D017: Capstan Phase Coefficient B CBp: Capstan Di gital Filter
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
CBp15 CBp14 CBp13 CBp12 CBp11 CBp10 CBp9 CBp8 CBp7 CBp6 CBp5 CBp4 CBp3 CBp2 CBp1 CBp0
Bit
Initial value
R/W
:
:
:
H'D018 to H'D019: Capstan Speed Coefficient A CAs: Capsta n Di g i t a l Filter
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
CAs15 CAs14 CAs13 CAs12 CAs11 CAs10 CAs9 CAs8 CAs7 CAs6 CAs5 CAs4 CAs3 CAs2 CAs1 CAs0
Bit
Initial value
R/W
:
:
:
H'D01A to H'D01B: Capstan Speed Coefficient B CBs: Capstan Digital Filter
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
CBs15 CBs14 CBs13 CBs12 CBs11 CBs10 CBs9 CBs8 CBs7 CBs6 CBs5 CBs4 CBs3 CBs2 CBs1 CBs0
Bit
Initial value
R/W
:
:
:
H'D01C to H'D01D: Capstan Phase Offset COfp: Capstan Digital Filter
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
COfp15 COfp14 COfp13 COfp12 COfp11 COfp10 COfp9 COfp8 COfp7 COfp6 COfp5 COfp4 COfp3 COfp2 COfp1 COfp0
Bit
Initial value
R/W
:
:
:
H'D01E to H'D01F: Capstan Speed Offset COfs: Capstan Digital Filter
*
W
13
*
W
14
*
W
15 1032547
*
W
6
*
W
9
*
W
8
*
W
11
*
W
10
*
W
*
WWWWWWW
12
******
COfs15 COfs14 COfs13 COfs12 COfs11 COfs10 COfs9 COfs8 COfs7 COfs6 COfs5 COfs4 COfs3 COfs2 COfs1 COfs0
Bit
Initial value
R/W
:
:
:
H'D020 to H'D021: Drum System Speed Delay Initialization Re gister DZs: Digital filter
1
—
13
1
—
14
1
—
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
1
—
WWWWWW
12
000000
DZs15 DZs14 DZs13 DZs12 DZs11 DZs10 DZs9 DZs8 DZs7 DZs6 DZs5 DZs4 DZs3 DZs2 DZs1 DZs0
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 989 of 1141
H'D022 to H'D023: Drum System Phase Delay Initialization Register DZp: Digital filter
1
—
13
1
—
14
1
—
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
1
—
WWWWWW
12
000000
DZp15 DZp14 DZp13 DZp12 DZp11 DZp10 DZp9 DZp8 DZp7 DZp6 DZp5 DZp4 DZp3 DZp2 DZp1 DZp0
Bit
Initial value
R/W
:
:
:
H'D024 to H'D025: Capstan System Speed Delay Initialization Re gister CZs: Digital filter
1
—
13
1
—
14
1
—
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
1
—
WWWWWW
12
000000
CZs15 CZs14 CZs13 CZs12 CZs11 CZs10 CZs9 CZs8 CZs7 CZs6 CZs5 CZs4 CZs3 CZs2 CZs1 CZs0
Bit
Initial value
R/W
:
:
:
H'D026 to H'D027: Capstan System Phase Delay Initialization Register CZp: Digital
filter
1
—
13
1
—
14
1
—
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
1
—WWWWWW
12
000000
CZp15 CZp14 CZp13 CZp12 CZp11 CZp10 CZp9 CZp8 CZp7 CZp6 CZp5 CZp4 CZp3 CZp2 CZp1 CZp0
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 990 of 1141
H'D028: Drum System Digital Filter Control Register DFIC: Digital Filter
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/(W)
DPHA
R/(W)*
1
DROV DZPON DZSON DSG2 DSG1 DSG0
1
Notes: 1. Only 0 can be written.
2. Optional
Drum system range over flag
0 Filter computation result does not exceed 12 bits. (Initial value)
1 Filter computation result exceeds 12 bits.
Drum phase system filter computation start bit
0 Phase system filter computation is OFF. (Initial value)
Phase system computation result Y is not added to Es.
1 Phase system filter computation is ON
Drum phase system Z
-1
initialization bit
0 Phase system Z
-1
does not reflect DZp value. (Initial value)
1 Phase system Z
-1
reflects DZp value
Drum speed system Z
-1
initialization bit
0 Speed system Z
-1
does not reflect DZs value. (Initial value)
1 Speed system Z
-1
reflects DZs value.
Drum system gain control bit
DSG2 DSG1 DSG0 Description
0 0 0 x 1 (Initial value)
1 x 2
1 0 x 4
1 x 8
1 0 0 x 16
1 (x 32)*
2
1 0 (x 64)*
2
1 Invalid (do not set)
Bit :
Initial value :
R/W :
—
—
Rev. 1.0, 02/ 00, page 991 of 1141
H'D029: Capstan System Digital Filter Control Register CF IC: Digital Filter
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/(W)
CPHA
R/(W)*
1
CROV CZPON CZSON CSG2 CSG1 CSG0
1
Notes: 1. Only 0 can be written.
2. Optional.
Capstan system range over flag
0 Filter computation result does not exceed 12 bits. (Initial value)
1 Filter computation result exceeds 12 bits.
Capstan phase system filter computation start bit
0 Phase system filter computation is OFF. (Initial value)
Phase system computation result Y is not added to Es.
1 Phase system filter computation is ON.
Capstan phase system Z
-1
initialization bit
0 Phase system Z
-1
does not reflect CZs value. (Initial value)
1 Phase system Z
-1
reflects CZs value.
Capstan speed system Z
-1
initialization bit
0 Speed system Z
-1
does not reflect CZs value. (Initial value)
1 Speed system Z
-1
reflects CZs value.
Capstan system gain control bit
CSG2 CSG1 CSG0 Description
0 0 0 x 1 (Initial value)
1 x 2
1 0 x 4
1 x 8
1 0 0 x 16
1 (x 32)*
2
1 0 (x 64)*
2
1 Invalid (do not set)
Bit :
Initial value :
R/W : —
—
Rev. 1.0, 02/ 00, page 992 of 1141
H'D02A: Digital Filter Control Register DFUCR: Digi t a l Filter
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
67
R/WR/WR/W
PTON CP/DP CFEPS DFEPS CFESS DFESS
11
Phase system computation result PWM output bit
0 Output normal filter computation result to PWM pin. (Initial value)
1 Output only phase system computation result to PWM pin.
PWM output select bit
0 Output drum phase system computation result (CAPPWM) (Initial value)
1 Output capstan phase system computation result (DRMPWM)
Drum phase system error data transfer bit
0 Transfer data by HSW (NHSW) signal latch. (Initial value)
1 Transfer data at the time of error data write.
Capstan phase system error data transfer bit
0 Transfer data by DVCFG2 signal latch. (Initial value)
1 Transfer data at the time of error data write.
Capstan speed system error data transfer bit
0 Transfer data by DVCFG signal latch. (Initial value)
1 Transfer data at the time of error data write.
Drum speed system error data transfer bit
0 Transfer data by NCDFG signal latch. (Initial value)
1 Transfer data at the time of error data
write.
Bit :
Initial value :
R/W :
——
——
Rev. 1.0, 02/ 00, page 993 of 1141
H'D030 to H'D031: Specified DFG Speed Preset Data Register
DFPR: Drum Speed Error Detector
0
W
13
0
W
14
0
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
DFPR15 DFPR14 DFPR13 DFPR12 DFPR11 DFPR10 DFPR9 DFPR8 DFPR7 DFPR6 DFPR5 DFPR4 DFPR3 DFPR2 DFPR1 DFPR0
Bit
Initial value
R/W
:
:
:
H'D032 to H'D033: DFG Speed Err or Data Register DF ER: Dr um Spe ed Er ror Dete c t o r
0
*R/W
13
0
*R/W
14
0
*R/W
15 1032547
0
*R/W
6
0
*R/W
9
0
*R/W
8
0
*R/W
11
0
*R/W
10
0
*R/W
0
*R/W *R/W *R/W*R/W *R/W*R/W *R/W
12
000000
DFER15 DFER14 DFER13 DFER12 DFER11 DFER10 DFER9 DFER8 DFER7 DFER6 DFER5 DFER4 DFER3 DFER2 DFER1 DFER0
Bit
Initial value
R/W
:
:
:
Note: * O nly t he det ect ed er r or data can be r ead.
H'D034 to H ' D035: DFG Loc k Uppe r Data Re gi ste r
DFRUDR: Drum Spe ed Er ror De t e cto r
1
W
13
1
W
14
0
W
15 1032547
1
W
6
1
W
9
1
W
8
1
W
11
1
W
10
1
W
1
WWWWWWW
12
111111
DFRUDR15 DFRUDR14 DFRUDR13 DFRUDR12 DFRUDR11 DFRUDR10 DFRUDR9 DFRUDR8 DFRUDR7 DFRUDR6 DFRUDR5 DFRUDR4 DFRUDR3 DFRUDR2 DFRUDR1 DFRUDR0
Bit
Initial value
R/W
:
:
:
H'D036 to H'D037: DFG Loc k Lower Data Register
DFRLDR: Dr um Spe ed Er ror Dete c t o r
0
W
13
0
W
14
1
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
DFRLDR15 DFRLDR14 DFRLDR13 DFRLDR12 DFRLDR11 DFRLDR10 DFRLDR9 DFRLDR8 DFRLDR7 DFRLDR6 DFRLDR5 DFRLDR4 DFRLDR3 DFRLDR2 DFRLDR1 DFRLDR0
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 994 of 1141
H'D038: Drum Speed Error Detec ti on Control Register
DFVCR: Drum Spe ed Er ror De t e cto r
0
0
1
0
(R)/W
*2
2
0
R/W
3
0
4
0
R/W
0
R/(W)
*1
56
0
7DFRFON
DF-R/UNR
DPCNT DFRCS1 DFRCS0
0
R/W
DFCS1
(R)/W
*2
RR/W
DFCS0 DFOVF
Notes:
Clock source select bit
DFCS1 DFCS0
0 0 φs (Initial value)
1 φs/2
1 0 φs/4
1 φs/8
Counter overflow flag
0 Normal status (Initial value)
1 Counter overflows.
Error data limit function select bit
0 Limit function OFF (Initial value)
1 Limit function ON
Drum lock flag
0 Drum speed system is not locked. (Initial value)
1 Drum speed system is locked.
Drum phase system filter computation auto start bit
0 Filter computation by drum lock detection is not excuted. (Initial value)
1 Filter computation of phase system is executed at the time of
drum lock detection.
Drum lock counter setting bit
DFRCS1 DFRCS0 Description
0 0 Underflow by 1 lock detection (Initial value)
1 Underflow by 2 lock detections
1 0 Underflow by 3 lock detections
1 Underflow by 4 lock detections
Description
Bit :
Initial value :
R/W :
1. Only 0 can be written.
2. When read, counter value is read.
Rev. 1.0, 02/ 00, page 995 of 1141
H'D039: Drum Phase Error Dete c tion Control Register
DPGCR: Drum Phase Error Detector
0
1
12
1
3
0
4
0
R/W
5
0
6
0
7
R/WR/(W)*
DPOVF
R/W
DPCS0
0
R/W
DPCS1 N/V HSWES
1
Note: * Only 0 can be written.
Error data latch signal select bit
0 HSW (VideoFF) signal (Initial value)
1 NHSW (NarrowFF) signal
Edge select bit
0 Latch at rising edge (Initial value)
1 Latch at falling edge
Bit :
Initial value :
R/W :
Clock source select bit
DPCS1 DPCS0
0 0 φs (Initial value)
1 φs/2
1 0 φs/4
1 φs/8
Counter overflow flag
0 Normal status (Initial value)
1 Counter overflows.
Description
———
———
Rev. 1.0, 02/ 00, page 996 of 1141
H'D03A to H'D03B: Specified Drum Phase Preset Data Register 2
DPPR2: Drum Phase Error Detector
0
W
13
0
W
14
0
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
DPPR15DPPR14 DPPR13 DPPR12DPPR11 DPPR10 DPPR9 DPPR8 DPPR7 DPPR6 DPPR5 DPPR4 DPPR3 DPPR2 DPPR1 DPPR0
Bit
Initial value
R/W
:
:
:
H'D03C: Specified Drum Phase Preset Data Register 1
DPPR1: Drum Phase Error Detector
0
0
1
0
W
2
0
W
3
0
4
1
5
1
6
1
7
WW
1
Bit :
Initial value :
R/W :
— — — — DPPR19 DPPR18 DPPR17 DPPR16
————
H'D03D: Drum Phase Error Data Register 1 DPER1: Drum Phase Error Dete ctor
0
0
1
0
*R/W
2
0
*R/W
3
0
4
—
—
1
5
—
—
1
6
—
—
1
7
—
—*R/W*R/W
1
DPER19 DPER18 DPER17 DPER16
Bit
Initial value
R/W
:
:
:
Note: * O nly t he det ect ed er r or data can be r ead.
H'D03E to H'D03F: Drum Phase Err or Data Register 2
DPER2: Drum Phase Error Detector
0
*R/W
13
0
*R/W
14
0
*R/W
15 1032547
0
*R/W
6
0
*R/W
9
0
*R/W
8
0
*R/W
11
0
*R/W
10
0
*R/W
0
*R/W *R/W *R/W*R/W *R/W*R/W *R/W
12
000000
DPER15DPER14 DPER13 DPER12DPER11 DPER10 DPER9 DPER8 DPER7 DPER6 DPER5 DPER4 DPER3 DPER2 DPER1 DPER0
Bit
Initial value
R/W
:
:
:
Note: * Only the det ect ed er ror dat a can be r ead.
H'D050 to H'D051: Specified CFG Speed Preset Data Register
CFPR: Capstan Speed Error Detector
0
W
13
0
W
14
0
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
CFPR15 CFPR14 CFPR13 CFPR12 CFPR11 CFPR10 CFPR9 CFPR8 CFPR7 CFPR6 CFPR5 CFPR4 CFPR3 CFPR2 CFPR1 CFPR0
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 997 of 1141
H'D052 to H'D053: CFG Speed Err or Data Register CFER: Capstan Speed Error Detec tor
0
*R/W
13
0
*R/W
14
0
*R/W
15 1032547
0
*R/W
6
0
*R/W
9
0
*R/W
8
0
*R/W
11
0
*R/W
10
0
*R/W
0
*R/W *R/W *R/W*R/W *R/W*R/W *R/W
12
000000
CFER15 CFER14 CFER13 CFER12 CFER11 CFER10 CFER9 CFER8 CFER7 CFER6 CFER5 CFER4 CFER3 CFER2 CFER1 CFER0
Bit
Initial value
R/W
:
:
:
Note: * Only the det ect ed er ror dat a can be r ead.
H'D054 to H ' D055: CFG Loc k Uppe r Data Re gi ste r
CFRUDR: Ca pst an Spee d Err or Det e cto r
1
W
13
1
W
14
0
W
15 1032547
1
W
6
1
W
9
1
W
8
1
W
11
1
W
10
1
W
1
WWWWWWW
12
111111
CFRUDR15 CFRUDR14 CFRUDR13 CFRUDR12 CFRUDR11 CFRUDR10 CFRUDR9 CFRUDR8 CFRUDR7 CFRUDR6 CFRUDR5 CFRUDR4 CFRUDR3 CFRUDR2 CFRUDR1 CFRUDR0
Bit
Initial value
R/W
:
:
:
H'D056 to H'D057: CFG Loc k Lower Data Register
CFRLDR: Ca psta n Spe ed Er ror Dete c t o r
0
W
13
0
W
14
1
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
CFRLDR15 CFRLDR14 CFRLDR13 CFRLDR12 CFRLDR11 CFRLDR10 CFRLDR9 CFRLDR8 CFRLDR7 CFRLDR6 CFRLDR5 CFRLDR4 CFRLDR3 CFRLDR2 CFRLDR1 CFRLDR0
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 998 of 1141
H'D058: Capstan Spee d Err or Dete c tion Control Register
CFVCR: Ca pst an Spee d Err or Det e cto r
0
0
1
0
(R)/W
*2
2
0
R/W
3
0
4
0
R/W
0
R/(W)
*1
56
0
7CFRFON CF-R/UNR CPCNT CFRCS1 CFRCS0
0
R/W
CFCS1
(R)/W
*2
RR/W
CFCS0 CFOVF
Notes:
Capstan phase system filter computation auto start bit
0 Filter computation by capstan lock detection is not excuted. (Initial value)
1 Filter computation of phase system is executed at the time of
drum lock detection.
Bit :
Initial value :
R/W :
Capstan lock counter setting bit
CFRCS1 CFRCS0 Description
0 0 Underflow by 1 lock detection (Initial value)
1 Underflow by 2 lock detections
1 0 Underflow by 3 lock detections
1 Underflow by 4 lock detections
Clock source select bit
CFCS1 CFCS0
0 0 φs (Initial value)
1 φs/2
1 0 φs/4
1 φs/8
Counter overflow flag
0 Normal status (Initial value)
1 Counter overflows.
Error data limit function select bit
0 Limit function OFF (Initial value)
1 Limit function ON
Capstan lock flag
0 Capstan speed system is not locked. (Initial value)
1 Capstan speed system is locked.
Description
1. Only 0 can be written.
2. When read, counter value is read.
Rev. 1.0, 02/ 00, page 999 of 1141
H'D059: Capstan Phase Er ror Dete cti on Control Register
CPGCR: Capstan Phase Error Detector
0
1
12
1
3
0
4
0
R/W
5
0
6
0
7
R/WR/(W)*
CPOVF
R/W
CPCS0
0
R/W
CPCS1 CR/RF SELCFG2
1
Note: * Only 0 can be written.
Preset signal select bit
0 Preset by REF30P signal (Initial value)
1 Preset by CREF signal
Preset, latch signal select bit
0 Preset by CAPREF30 signal and latch by DVCTL signal (Initial value)
1 Preset by REF30P (CREF) signal and latch by DVCFG2 signal
Bit :
Initial value :
R/W :
Clock source select bit
CPCS1 CPCS0
0 0 φs (Initial value)
1 φs/2
1 0 φs/4
1 φs/8
Counter overflow flag
0 Normal status (Initial value)
1 Counter overflows.
Description
———
———
Rev. 1.0, 02/ 00, page 1000 of 1141
H'D05A to H'D05B: Specified Capstan Phase Preset Data Register 2
CPPR2: Capstan Phase Error Detector
0
W
13
0
W
14
0
W
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
WWWWWWW
12
000000
CPPR15CPPR14 CPPR13 CPPR12CPPR11 CPPR10 CPPR9 CPPR8 CPPR7 CPPR6 CPPR5 CPPR4 CPPR3 CPPR2 CPPR1 CPPR0
Bit
Initial value
R/W
:
:
:
H'D05C: Specified Capstan Phase Preset Data Register 1
CPPR1: Capstan Phase Error Detector
0
0
1
0
W
2
0
W
3
0
4
—
—
1
5
—
—
1
6
—
—
1
7
—
—WW
1
CPPR19 CPPR18 CPPR17 CPPR16
Bit
Initial value
R/W
:
:
:
H'D05D: Capstan P hase Err or Data Register 1 CPER1: Capstan Phase Error Dete ctor
0
0
1
0
*R/W
2
0
*R/W
3
0
4
—
—
1
5
—
—
1
6
—
—
1
7
—
—*R/W*R/W
1
Bit
Note: * Only the detected error data can be read.
Initial value
R/W
:
:
:
CPER19 CPER18 CPER17 CPER16
H'D05E to H'D05F: Capstan Phase Error Data Register 2
CPER2: Capstan Phase Err or Detec tor
0
*R/W
13
0
*R/W
14
0
*R/W
15 1032547
0
*R/W
6
0
*R/W
9
0
*R/W
8
0
*R/W
11
0
*R/W
10
0
*R/W
0
*R/W *R/W *R/W*R/W *R/W*R/W *R/W
12
000000
CPER15CPER14 CPER13 CPER12CPER11 CPER10 CPER9 CPER8 CPER7 CPER6 CPER5 CPER4 CPER3 CPER2 CPER1 CPER0
Bit
Note: * Only the detected error data can be read.
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1001 of 1141
H'D060: HSW Mode Register 1 H SM1: HSW Timi ng Ge nerator
0
0
1
0
R/W
2
0
R/(W)*
3
0
4
1
R
1
R
56
0
7EMPA OVWB OVWA CLRB CLRA
0
R
FLB
R/WR/(W)*R
FLA EMPB
Note: * Only 0 can be written.
FIFO2 full flag
0 FIFO2 is not full (Initial value)
1 FIFO2 is full
FIFO1 full flag
0 FIFO1 is not full (Initial value)
1 FIFO1 is full
FIFO2 empty flag
0 Data remains in FIFO2
1 FIFO2 is empty (Initial value)
FIFO1 empty flag
0 Data remains in FIFO1
1 FIFO1 is empty (Initial value)
FIFO2 overwrite flag
0 Normal operation (Initial value)
1 Data is written to FIFO2 while it is full. Write 0 to clear the flag.
FIFO1 overwrite flag
0 Normal operation (Initial value)
1 Data is written to FIFO1 while it is full. Write 0 to clear the flag.
FIFO2 pointer clear
0 Normal operation (Initial value)
1 Clear FIFO2 pointer
FIFO1 pointer clear
0 Normal operation (Initial value)
1 Clear FIFO1 pointer
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1002 of 1141
H'D061: HSW Mode Register 2 H SM2: HSW Timi ng Ge nerator
0
0
1
0
R
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7EDG ISEL1 SOFG OFG VFF/NFF
0
R/W
FRT
R/WR/WR/W
FGR20FF LOP
Free-run bit
0 5-bit DFG counter and 16-bit timer counter (Initial value)
1 16-bit FRC
FRG2 clear stop bit
0 16-bit timer counter clearing by DFG reference register 2 is enabled (Initial value)
1 16-bit timer counter clearing by DFG reference register 2 is disabled
Mode select bit
0 Signal mode (Initial value)
1 Loop mode
DFG edge select bit
0 Calculated by DFG rising edge (Initial value)
1 Calculated by DFG falling edge
Interrupt select bit
0 Interrupt request is generated by rising of FIFO STRIG signal (Initial value)
1 Interrupt request is generated by FIFO match signal
FIFO output group select bit
0 20-stage output by FIFO1 and FIFO2 (Initial value)
1 10-stage output by FIFO1 only
Output FIFO group flag
0 Outputting pattern by FIFO1 (Initial value)
1 Outputting pattern by FIFO2
VideoFF/NallowFF output switchover bit
0 VideoFF output (Initial value)
1 NarrowFF output
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1003 of 1141
H'D062: HSW Loop Stage Setting Register HSLP: H SW Timi ng Gener ator
0
*
1
*
R/W
2
*
R/W
3
*
4
*
R/W
5
*
6
*
7
R/WR/WR/W
LOB1
R/W
LOB2
*
R/W
LOB3 LOB0 LOA3 LOA2 LOA1 LOA0
FIFO1 stage setting bit
HSM2 HSLP Description
Bit 5 Bit 3 Bit 2 Bit 1 Bit 0
LOP LOA3 LOA2 LOA1 LOA0
0 * * * * Single mode (Initial value)
1 0 0 0 0 Output stage 0 of FIFO1
1 Output stage 0 and 1 of FIFO1
1 0 Output stage 0 to 2 of FIFO1
1 Output stage 0 to 3 of FIFO1
1 0 0 Output stage 0 to 4 of FIFO1
1 Output stage 0 to 5 of FIFO1
1 0 Output stage 0 to 6 of FIFO1
1 Output stage 0 to 7 of FIFO1
1 0 0 0 Output stage 0 to 8 of FIFO1
1 Output stage 0 to 9 of FIFO1
1 0 Setting disabled
1
1 0 0
1
1 0
1
Note: * Don't care.
FIFO2 stage setting bit
HSM2 HSLP Description
Bit 5 Bit 7 Bit 6 Bit 5 Bit 4
LOP LOB3 LOB2 LOB1 LOB0
0 * * * * Single mode (Initial value)
1 0 0 0 0 Output stage 0 of FIFO2
1 Output stage 0 and 1 of FIFO2
1 0 Output stage 0 to 2 of FIFO2
1 Output stage 0 to 3 of FIFO2
1 0 0 Output stage 0 to 4 of FIFO2
1 Output stage 0 to 5 of FIFO2
1 0 Output stage 0 to 6 of FIFO2
1 Output stage 0 to 7 of FIFO2
1 0 0 0 Output stage 0 to 8 of FIFO2
1 Output stage 0 to 9 of FIFO2
1 0 Setting disabled
1
1 0 0
1
1 0
1
Note: * Don't care.
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1004 of 1141
H'D064 to H' D065: F IFO O utput Patte r n Regi ste r 1 F P DRA: H SW Timi ng G e ner ator
8
*
9
*
W
10
*
W
11
*
12
*
W
*
W
1314
*
15
NarrowFFA
VFFA AFFA VpulseA MlevelA
1W
MlevelA bit
Used for generating an additional
V signal. For details, refer to section
26.12, Additional V Signal Generator.
VpulseA bit
Used for generating an additional
V signal. For details, refer to section
26.12, Additional V Signal Generator.
AudioFFA bit
Controls the audio head.
VideoFFA bit
Controls the video head.
NarrowFFA bit
Controls the narrow video head.
A/D Trigger A bit
Indicates a hardware trigger signal for the A/D converter.
Reserved
Cannot be read or modified
S-TRIGA bit
Indicates a signal that generates an interrupt.
When the STRIGA is selected by the ISEL,
modifying this bit from 0 to 1 generates an interrupt.
MlevelA bit
Used for generating an additional
V signal. For details, refer to section
26.12, Additional V Signal Generator.
VpulseA bit
Used for generating an additional
V signal. For details, refer to section
26.12, Additional V Signal Generator.
AudioFFA bit
Controls the audio head.
VideoFFA bit
Controls the video head.
NarrowFFA bit
Controls the narrow video head.
A/D Trigger A bi
Indicates a hardware trigger signal for the A/D converter.
Reserved
Cannot be read or modified
S-TRIGA bit
Indicates a signal that generates an interrupt.
When the STRIGA is selected by the ISEL,
modifying this bit from 0 to 1 generates an interrupt.
WW
ADTRGA STRIGA
Bit
Initial value
R/W
Bit
Initial value
R/W
0
*
1
*
W
2
*
W
3
*
4
*
W
*
W
56
*
7PPGA4 PPGA3 PPGA2 PPGA1 PPGA0
*
W
PPGA7
WWW
PPGA6 PPGA5
:
:
:
:
:
:
PPG output signal A bits
Used for outputting a timing
control signal from port 7 (PPG).
Rev. 1.0, 02/ 00, page 1005 of 1141
H'D066 to H'D067: FIFO Ti ming Patte r n Register 1 F TP RA: HSW Timing Gener ator
8
*
9
*
W
10
*
W
11
*
12
*
W
*
W
1314
*
15 FTPRA12 FTPRA11 FTPRA10 FTPRA9 FTPRA8
WWW *
W
FTPRA14FTPRA15 FTPRA13
Bit
Initial value
R/W
:
:
:
0
*
1
*
W
2
*
W
3
*
4
*
W
*
W
56
*
7FTPRA4 FTPRA3 FTPRA2 FTPRA1 FTPRA0
WWW *
W
FTPRA6FTPRA7 FTPRA5
Bit
Initial value
R/W
:
:
:
Note: FTPRA and FTCTR are assigned to the same address.
H'D066 to H'D067: FIFO Ti mer Capture Register 1 FTCTR: HSW Timing Ge ner ator
89101112131415 FTCTR12 FTCTR11 FTCTR10 FTCTR9 FTCTR8FTCTR14FTCTR15 FTCTR13
Bit
Initial value
R/W
:
:
:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
01234567 FTCTR4 FTCTR3 FTCTR2 FTCTR1 FTCTR0FTCTR6FTCTR7 FTCTR5
Bit
Initial value
Note: FTPRA and FTCTR are assigned to the same address.
R/W
:
:
:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Rev. 1.0, 02/ 00, page 1006 of 1141
H'D068 to H'D069: FIFO O utput Pattern Register 2 F P DRB: HSW Timing Gener ator
8
*
9
*
W
10
*
W
11
*
12
*
W
*
W
1314
*
15
—
1
—
NarrowFFB
VFFB AFFB VpulseB MlevelB
WWW
ADTRGB STRIGB
0
*
1
*
W
2
*
W
3
*
4
*
W
*
W
56
*
7PPGB4 PPGB3 PPGB2 PPGB1 PPGB0
*
PPGB7
WWWW
PPGB6 PPGB5
:
:
:
:
:
:
Bit
Initial value
R/W
Bit
Initial value
R/W
PPG output signal B bits
Used for outputting a timing
control signal from port 7 (PPG).
MlevelB bit
Used for generating an additional
V signal. For details, refer to section
26.12, Additional V Signal Generator.
VpulseB bit
Used for generating an additional
V signal. For details, refer to section
26.12, Additional V Signal Generator.
AudioFFB bit
Controls the audio head.
VideoFFB bit
Controls the video head.
NarrowFFB bit
Controls the narrow video head.
A/D Trigger B bit
Indicates a hardware trigger signal for the A/D converter.
Reserved
Cannot be read or modified
S-TRIGB bit
Indicates a signal that generates an interrupt.
When the STRIGA is selected by the ISEL,
modifying this bit from 0 to 1 generates an interrupt.
Rev. 1.0, 02/ 00, page 1007 of 1141
H'D06A to H'D06B: FIFO Ti mi ng Patter n Register 2 FTP RB: HSW Timi ng Gener ator
8
*
9
*
W
10
*
W
11
*
12
*
W
*
W
1314
*
15 FTPRB12 FTPRB11 FTPRB10 FTPRB9 FTPRB8
WWW *
W
FTPRB14FTPRB15 FTPRB13
Bit
Initial value
R/W
:
:
:
8
*
9
*
W
10
*
W
11
*
12
*
W
*
W
1314
*
15 FTPRB12 FTPRB11 FTPRB10 FTPRB9 FTPRB8
WWW *
W
FTPRB14FTPRB15 FTPRB13
Bit
Initial value
R/W
:
:
:
H'D06C: DFG Reference Register 1 DFCRA: HSW Timing Ge ner ator
0
*
1
*
W
2
*
W
3
*
4
*
W
0
W
56
0
7DFCRA4 DFCRA3 DFCRA2 DFCRA1 DFCRA0
0
W
ISEL2
WWW
CCLR CKSL
Interrupt select bit
Note: DFCRA and DFCTR are assigned to the same address.
0 Interrupt request is generated by clear signal of 16-bit timer counter (Initial value)
1 Interrupt request is generated by VD signal in PB mode
DFG counter clear bit
0 Normal operation (Initial value)
1 5-bit DFG counter is cleared
16-bit counter clock source select bit
0 φs/4 (Initial value)
1 φs/8
Bit
Initial value
R/W
:
:
:
FIFO1 output timing setting
bits (DFCRA4 to DFCRA0)
These bits determine the
start point of FIFO1 timing.
Rev. 1.0, 02/ 00, page 1008 of 1141
H'D06C: DFG Reference Count Register DFCTR: HSW Timing Generator
0
*
1
*
R
2
*
R
3
*
4
*
R
56
1
7DFCTR4 DFCTR3 DFCTR2 DFCTR1 DFCTR0
RR
11
———
———
Note: DFCRA and DFCTR are assigned to the same address.
Bit
Initial value
R/W
:
:
:
DFG pulse count bits (DFCTR4 to DFCTR0)
These bits count DFG pulses.
H'D06D: DFG Reference Register 2 DFCRB: HSW Timing Generator
0
*
1
*
W
2
*
W
3
*
4
*
W
56
1
7DFCRB4 DFCRB3 DFCRB2 DFCRB1 DFCRB0
WW
11
———
———
Bit
Initial value
R/W
:
:
:
FIFO2 output timing setting bits (DFCRB4 to DFCRB0)
These bits determine the start point of FIFO2 timing.
Rev. 1.0, 02/ 00, page 1009 of 1141
H'D06E: Special Playback Control Re gister CHCR: 4-Head Special Playback Circuit
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7HAH SIG3 SIG2 SIG1 SIG0
0
W
V/N
WWW
HSWPOL CRH
HSW output signal select bit
0 VideoFF signal output (Initial value)
1 Nallow FF signal output
COMP polarity select bit
0 Positive (Initial value)
1 Negative
C.Rotary synchronization control bit
0 Synchronous (Initial value)
1 Asynchronous
H.AmpSW synchronization control bit
0 Synchronous (Initial value)
1 Asynchronous
Signal control bits
SIG3 SIG2 SIG1 SIG0 Output pin
C.Rotary H.Amp SW
0 0 * * L L
(Initial value)
1 0 0 HSW
L
1 HSW H
1 0 L HSW
1 H HSW
1 0 0 * HSW EX-OR COMP COMP
1 HSW EX-NOR COMP COMP
1 0 HSW EX-OR RTP0 RTP0
1 HSW EX-NOR RTP0 RTP0
Note: * Don't care.
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1010 of 1141
H'D06F : Addi ti onal V Contr ol Re gi ste r ADDVR: Addi ti onal V Si gnal G e ne r ator
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
1
67
R/WR/W
HMSK HiZ CUT VPOM POL
11
Note: * Don't care.
OSCH mask bit
0 OSCH added (Initial value)
1 OSCH not added
High impedance bit
0 3-level output from Vpulse pin (Initial value)
1 Vpulse pin is set as 3-state (H/L/HiZ) pin
Additional V output control bits
CUT VPON POL Description
0 0 * Low level (Initial value)
1 0 Negative polarity
1 Positive polarity
1 * 0 Immediate level
(high-impedance when HiZ bit = 1)
1 High level
———
———
Bit
Initial value
R/W
:
:
:
H'D070 to H'D071: X-Value Data RegisterXDR: X-Val ue , TRK - Va l ue Adj ust ment Circuit
1
13
1
14
1
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
1
WWWWWW
12
XD1 XD0XD3 XD2XD5 XD4XD7 XD6XD9 XD8
XD11 XD10
000000
Bit
Initial value
R/W
:
:
:
————
————
H'D072 to H'D073: TRK-Value Data Register
TRDR: X-Va l ue, T RK - Value Adjust m e nt Circuit
1
13
1
14
1
15 1032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
1
WWWWWW
12
TRD1 TRD0TRD3 TRD2TRD5 TRD4TRD7 TRD6TRD9 TRD8
TRD11 TRD10
000000
:
:
:
Bit
Initial value
R/W
————
————
Rev. 1.0, 02/ 00, page 1011 of 1141
H'D074: X-Value/TRK-Value Control Register
XTCR: X-Value, TRK-Value Adjustment Circuit
0
0
1
0
R/W
2
0
W
3
0
4
0
W
5
0
6
0
7
R/WWW
AT/MU
W
CAPRF TRK/X EXC/REF XCS DVREF1 DVREF0
1
Capstan phase adjustment auto/manual select bit
0 Manual mode (Initial value)
1 Auto mode
External sync signal edge select bit
0 Generated at EXCAP rising edge (Initial value)
1 Generated at EXCAP rising and falling edge
Capstan phase adjustment register select bit
0 CAPREF30 is generated only by XDR setting value (Initial value)
1 CAPREF30 is generated by XDR and TRDR setting values
Reference signal select bit
0 Generated by REF30P signal (Initial value)
1 Generated by external referece signal
Clock source select bit
0 φs (Initial value)
1 φs/2
REF30P frequency division rate select bit
DVREF1 DVREF0 Description
0 0 1-division (Initial value)
1 2-division
1 0 3-division
1 4-division
—
—
Bit
Initial value
R/W
:
:
:
H'D078: Drum 12-Bit PWM Data Register DPWDR: Drum 12-Bit PWM
1
0
R/W
DPWDR1
0
0
R/W
DPWDR0
3
0
R/W
DPWDR3
2
0
R/W
DPWDR2
5
0
R/W
DPWDR5
4
0
R/W
DPWDR4
7
0
R/W
DPWDR7
6
0
R/W
DPWDR6
9
0
R/W
DPWDR9
8
0
R/W
DPWDR8
11
0
R/W
DPWDR11
10
0
R/W
DPWDR10
12
1
13
1
14
1
15
1
:
:
:
Bit
Initial value
R/W
————
————
Rev. 1.0, 02/ 00, page 1012 of 1141
H'D07A: Drum 12-Bit PWM Control Registor DPWCR: Drum 12-Bit PWM
0
0
1
1
W
2
0
W
3
0
4
0
W
0
W
56
1
7DH/L DSF/DF DCK2 DCK1 DCK0
0
W
DPOL
WWW
DDC DHiZ
Positive polarity output (Initial value)
Negative polarity output
0
1
Polarity switchover bit
Fixed output bit, PWM pin output bit
01 0 Low level output from PWM pin (Initial value)
DHiZ DH/LDDC Description
1 High level output form PWM pin
1
0* High impedance from PWM pin
* * PWM modulated signal output
Note: * Don't care.
Modulate error data from digital filter circuit (Initial value)
Modulate data written in data register
0
1
Output data select bit
Note: When PWMs output data from the digital filter circuit, the data consisting of the speed and phase
filtering results are modulated by PWMs and output from the DRMPWM pin.
However, it is possible to output only capstan phase filter result from DRMPWM pin,
by DFUCR settings of the digital filter circuit.
See the section explaining the digital filter computation circuit.
Carrier frequency select bits
Description
00 0 Carrier frequency is φ/2
DCK1 DCK0DCK2
1 Carrier frequency is φ/4
1 0 Carrier frequency is φ/8 (Initial value)
1 Carrier frequency is φ/16
01 0 Carrier frequency is φ/32
1 Carrier frequency is φ/64
1 0 Carrier frequency is φ/128
1 (Do not set)
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1013 of 1141
H'D07B: Capstan 12-Bit PWM Control Registor CPWCR: Capstan 12-Bit P WM
0
0
1
1
W
2
0
W
3
0
4
0
W
0
W
56
1
7CH/L CSF/DF CCK2 CCK1 CCK0
0
W
CPOL
WWW
CDC CHiZ
Positive polarity (Initial value)
Negative polarity output
0
1
Polarity switchover bit
Fixed output bit, PWM pin output bit
01 0 Low level output from PWM pin (Initial value)
CHiZ CH/LCDC Description
1 High level output form PWM pin
1
0* High impedance from PWM pin
* * PWM modulated signal output
Note: * Don't care.
Modulate error data from digital filter circuit (Initial value)
Modulate data written in data register
0
1
Output data select bit
Note: When PWMs output data from the digital filter circuit, the data consisting of the speed and phase
filtering results are modulated by PWMs and output from the CAPPWM pin.
However, it is possible to output only drum phase filter results from CAPPWM pin,
by DFUCR settings of the digital filter circuit.
See the section explaining the digital filter computation circuit.
Carrier frequency select bits Description
00 0 Carrier frequency is φ/2
CCK1 CCK0CCK2
1 Carrier frequency is φ/4
1 0 Carrier frequency is φ/8 (Initial value)
1 Carrier frequency is φ/16
01 0 Carrier frequency is φ/32
1 Carrier frequency is φ/64
1 0 Carrier frequency is φ/128
1 (Do not set)
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1014 of 1141
H'D07C: Capstan 12-Bi t P WM Data Register CPWDR: Capstan 12-Bit PWM
1
0
R/W
CPWDR1
0
0
R/W
CPWDR0
3
0
R/W
CPWDR3
2
0
R/W
CPWDR2
5
0
R/W
CPWDR5
4
0
R/W
CPWDR4
7
0
R/W
CPWDR7
6
0
R/W
CPWDR6
9
0
R/W
CPWDR9
8
0
R/W
CPWDR8
11
0
R/W
CPWDR11
10
0
R/W
CPWDR10
12
1
13
1
14
1
15
1
:
:
:
Bit
Initial value
R/W
————
————
H'D080: CTL Control Register CTCR: CTL Circuit
0
0
1
0
R
2
0
W
3
0
4
1
W
5
1
6
0
7
WW W
FSLB
W
FSLC
0
W
NT/PL FSLA CCS LCTL UNCTL SLWM
NTSC/PAL select bit
0 NTSC mode (frame rate: 30 Hz) (Initial value)
1 PAL mode (frame rate: 25 Hz)
Long CTL bit
0 Clock source (CCS) operates at the setting value (Initial value)
1 Clock source (CCS) operates for further 8-division after
operating at the setting value
CTL undetected bit
0 Detected (Initial value)
1 Undetected
Mode select bit
0 Normal mode (Initial value)
1 Slow mode
Clock source select bit
0 φs (Initial value)
1 φs/2
Operating frequency select bits
FSLC FSLB FSLA Description
0 0 0 Reserved (do not set)
1 Reserved (do not set)
1 0 fosc = 8 MHz
1 fosc = 10 MHz (Initial value)
1 * * Reserved (do not set)
Note: * Don't care.
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1015 of 1141
H'D081: CTL Mode Register CTLM: CTL Circuit
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/W
FW/RV
R/W
REC/
0
R/W
ASM MD4 MD3 MD2 MD1 MD0
Note: * Refer to the description of the CTL mode register in section 26.13.5, Register Description.
ASM REC/ Description
0 0 Playback mode (Initial value)
1 Record mode
1 0 Assemble mode
1 Invalid (do not set)
Direction bit
0 Forward (Initial value)
1 Reverse
CTL mode select bits*
Bit
Initial value
R/W
:
:
:
Record /playback mode bits
Rev. 1.0, 02/ 00, page 1016 of 1141
H'D082 to H' D083: REC-CTL Duty Data Re gi ste r 1 RCDR1: CTL Circuit
1111
131415 103254769811 10
CMT11
W
12
0
CMT10
W
0
CMT13
W
0
CMT12
W
0
CMT15
W
0
CMT14
W
0
CMT17
W
0
CMT16
W
0
CMT19
W
0
CMT18
W
0
CMT1B
W
0
CMT1A
W
0
:
:
:
Bit
Initial value
R/W
————
————
H'D084 to H' D085: REC-CTL Duty Data Re giste r 2 RCDR2: CTL Circuit
1111
131415 103254769811 10
CMT21
W
12
0
CMT20
W
0
CMT23
W
0
CMT22
W
0
CMT25
W
0
CMT24
W
0
CMT27
W
0
CMT26
W
0
CMT29
W
0
CMT28
W
0
CMT2B
W
0
CMT2A
W
0
:
:
:
Bit
Initial value
R/W
————
————
H'D086 to H' D087: REC-CTL Duty Data Re giste r 3 RCDR3: CTL Circuit
1111
131415 103254769811 10
CMT31
W
12
0
CMT30
W
0
CMT33
W
0
CMT32
W
0
CMT35
W
0
CMT34
W
0
CMT37
W
0
CMT36
W
0
CMT39
W
0
CMT38
W
0
CMT3B
W
0
CMT3A
W
0
:
:
:
Bit
Initial value
R/W
————
————
H'D088 to H' D089: REC-CTL Duty Data Re giste r 4 RCDR4: CTL Circuit
1111
131415 103254769811 10
CMT41
W
12
0
CMT40
W
0
CMT43
W
0
CMT42
W
0
CMT45
W
0
CMT44
W
0
CMT47
W
0
CMT46
W
0
CMT49
W
0
CMT48
W
0
CMT4B
W
0
CMT4A
W
0
:
:
:
Bit
Initial value
R/W
————
————
H'D08A to H ' D08B: REC-CTL Duty Data Regi ste r 5 RCDR5: CTL Circuit
1111
131415 103254769811 10
CMT51
W
12
0
CMT50
W
0
CMT53
W
0
CMT52
W
0
CMT55
W
0
CMT54
W
0
CMT57
W
0
CMT56
W
0
CMT59
W
0
CMT58
W
0
CMT5B
W
0
CMT5A
W
0
Bit :
Initial value :
R / W :
————
————
Rev. 1.0, 02/ 00, page 1017 of 1141
H'D08C: Duty I/O Register DI/O: CTL Circuit
0
1
1
0
R/(W)*
1
2
0
W
3
0
45
1
67
R/WWW
VCTR0
1
W
VCTR1
1
W
VCTR2 BPON BPS BPF DI/O
1
Notes: 1. Only 0 can be written.
2. Refer to the description of the duty I/O register in section 26.13.5, Register Description.
Bit pattern detection ON/OFF bit
0 Bit pattern detection OFF (initial value)
1 Bit pattern detection ON
Bit pattern detection start bit
0 Normal status (initial value)
1 Starts 8-bit bit pattern detection
Duty I/O register
*
2
Bit pattern detection flag
0 Bit pattern (8-bit) is not detected (initial value)
1 Bit pattern (8-bit) is detected
VCTR2 VCTR1 VCTR0 Description
0 0 0 Number of 1-pulse for detection = 2
1 Number of 1-pulse for detection = 4 (SYNC mark)
1 0 Number of 1-pulse for detection = 6
1 Number of 1-pulse for detection = 8 (mark A, short)
1 0 0 Number of 1-pulse for detection = 12 (mark A, long)
1 Number of 1-pulse for detection = 16
1 0 Number of 1-pulse for detection = 24 (mark B)
1 Number of 1-pulse for detection = 32 (initial value)
VISS interrupt setting bits
—
—
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1018 of 1141
H'D08D: Bit Pattern Register BTPR: CTL Circuit
0
1
1
1
R*/W
2
1
R*/W
3
1
45
1
67
R*/WR*/WR*/W
LSP5
1
R*/W
LSP4
1
R*/W
LSP6
1
R*/W
LSP7 LSP3 LSP2 LSP1 LSP0
Note: * Writes are disabled during bit pattern detection.
Bit
Initial value
R/W
:
:
:
H'D090 to H'D091: Reference Frequency Register 1 RFD: Reference Signal Generator
15
1
REF15
W
14
1
REF14
W
13
1
REF13
W
12
1
REF12
W
11
1
REF11
W
10
1
REF10
W
9
1
REF9
W
8
1
REF8
W
7
1
REF7
W
6
1
REF6
W
5
1
REF5
W
4
1
REF4
W
3
1
REF3
W
2
1
REF2
W
1
1
REF1
W
0
1
REF0
W
Bit :
Initial value :
R/W :
H'D092 to H'D093: Reference Frequency Register 2 CRF: Reference Signal Generator
15
1
CRF15
W
14
1
CRF14
W
13
1
CRF13
W
12
1
CRF12
W
11
1
CRF11
W
10
1
CRF10
W
9
1
CRF9
W
8
1
CRF8
W
7
1
CRF7
W
6
1
CRF6
W
5
1
CRF5
W
4
1
CRF4
W
3
1
CRF3
W
2
1
CRF2
W
1
1
CRF1
W
0
1
CRF0
W
Bit :
Initial value :
R/W :
H'D094 to H'D095: REF30 Counter Register RFC: Reference Signal Generator
15
0
RFC15
14
0
RFC14
13
0
RFC13
12
0
RFC12
11
0
RFC11
10
0
RFC10
9
0
RFC9
8
0
RFC8
7
0
RFC7
6
0
RFC6
5
0
RFC5
4
0
RFC4
3
0
RFC3
2
0
RFC2
1
0
RFC1
0
0
RFC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1019 of 1141
H'D096: Reference Frequency Mode Register RFM: Reference Signal Generator
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7REX CRD OD/EV VST VEG
0
W
RCS
WWW
VNA CVS
Clock source select bit
0 φs/2 (Initial value)
1 φs/4
Mode select bit
0 Manual mode (Initial value)
1 Auto mode
Manual select bit
0 VD sync (Initial value)
1 Free-run
External signal synchronization select bit
0 VD signal or free-run (Initial value)
1 External signal sync
DVCFG2 synchronization select bit
0 At mode switching (initial value)
1 DVCFG2 signal synchronized
ODD/EVEN edge switchoverselect bit
0 Generated at field signal rising (even) (Initial value)
1 Generated at field signal rising (odd)
VideoFF counter set
0 VideoFF signal turns counter set off (Initial value)
1 VideoFF signal turns counter set on
VideoFF edge select bit
0 Set at VideoFF signal rising (Initial value)
1 Set at VideoFF signal falling
Bit
Initial value
R/W
:
:
:
H'D097: Reference Frequency Mode Register 2 RFM2: Reference Signal Generator
0
0
1
1
2
1
3
1
4
1
567 FDS
111 R/W
Field select bit
0 Generated by selected ODD or EVEN VD
signal (Initial value)
1 Generated by VD signal within mode transition
phase error of 90˚
TBC select bit
0 Reference signal is generated by VD
signal
1 Reference signal is generated by free-running
counter
TBC — — — — — —
R/W — — — — — —
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1020 of 1141
H'D098: DVCTL Contr ol Re gi ste r CTVC: Fr eque nc y Di v i de r
0
*
1
*
R
2
*
R
34567
R
CFG HSW
0
W
0
W
CEX CEG CTL
111
DVCTL signal generation select bit
0 Generated by PB-CTL signal (Initial value)
1 Generated by external input signal
External sync signal edge select bit
0 Rising edge (Initial value)
1 Falling edge
CFG flag
0 CFG level is low (Initial value)
1 CFG level is high
HSW flag
0 HSW level is low (Initial value)
1 HSW level is high
CTL flag
0 REC or PB-CTL level is low (Initial value)
1 REC or PB-CTL level is high
———
———
Bit
Initial value
R/W
:
:
:
H'D099: CTL Frequency Division Register CTLR: Frequency Divider
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7CTL4 CTL3 CTL2 CTL1 CTL0
0
W
CTL7
WWW
CTL6 CTL5
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1021 of 1141
H' D0 9A: DVCF G Cont r o l Re g i st e r CDVC: Freque nc y Di v i de r
0
0
1
0
W
2
0
W
34
0
W
5
1
6
1
7
WR
CMK CMN
W
DVTRG
0
R/W*
MCGin CRF CPS1 CPS0
0
Note: * Only 0 can be written
Mask CFG flag
0 CFG normal operation (Initial value)
1 DVCFG is detected while mask is set (race detection)
CFG mask status bit
0 Mask is released by capstan mask timer
1 Mask is set by capstan mask timer (Initial value)
CFG mask select bit
0 Capstan mask timing function ON (Initial value)
1 Capstan mask timing function OFF
PB (ASM)-to-REC transition timing sync ON/OFF select bit
0 PB (ASM)-to-REC transition timing sync ON (Initial value)
1 PB (ASM)-to-REC transition timing sync OFF
CFG frequency division edge select bit
0 Execute frequency division operation at CFG rising edge
(Initial value)
1 Execute frequency division operation at CFG rising
CFG mask timer clock select bit
CPS1 CPS0 Description
0 0 φs/1024 (Initial value)
1 φs/512
1 0 φs/256
1 φs/128
—
—
Bit
Initial value
R/W
:
:
:
H'D09B: CFG Frequency Division Re gister 1 CDIVR1: Fr e que ncy Di v i de r
0
0
1
0
W
2
0
W
34
0
W
5
0
67
WW
CDV15 CDV14
0
W
CDV16
0
W
CDV13 CDV12 CDV11 CDV10
1
Bit :
Initial value :
R/W :
—
—
H' D0 9C: CF G F r e quenc y Divi si o n Re g i st e r 2 CDIVR2 : Fr e que ncy Di v i der
0
0
1
0
W
2
0
W
34
0
W
5
0
67
WW
CDV25 CDV24
0
W
CDV26
0
W
CDV23 CDV22 CDV21 CDV20
1
Bit :
Initial value :
R/W :
—
—
Rev. 1.0, 02/ 00, page 1022 of 1141
H' D0 9D: DVCF G M ask Int e rva l Re g i st e r CTM R: F r eque nc y Di v i de r
0
1
1
1
W
2
1
W
34
1
W
5
1
67
WW
CPM5 CPM4
1
W
CPM3 CPM2 CPM1 CPM0
11
Bit :
Initial value :
R/W :
——
——
H'D09E: FG Control Register FGCR: Frequency Divider
0
0
1
1
2
1
3
1
4
1
5
1
6
1
7
W
DRF
1
DFG edge select bit
0 NCDFG signal rising edge is selected (Initial value)
1 NCDFG signal falling edge is selected
Bit :
Initial value :
R/W :
———————
———————
H'D0A0: Servo Port Mode Register SPMR: Servo Port
0
1
1
1
—
2
1
—
3
1
4
1
—
0
R/W
567 —————
0
R/W
CTLSTOP
——
CFGCOMP
1
CFG input method switch bit
0 Zero cross type comparator method for CFG signal input (Initial value)
1 Digital signal input method for CFG signal input
CTLSTOP bit
0 CTL circuit operates (Initial value)
1 CTL circuit does not operate
Bit :
Initial value :
R/W :
—
—
Rev. 1.0, 02/ 00, page 1023 of 1141
H'D0A3: Servo Monitor Control Register SVMCR: Servo Port
0
0
1
0
2
0
3
0
4
0
567 SVMCR4 SVMCR3 SVMCR2 SVMCR1 SVMCR0
11 R/WR/WR/W
0
SVMCR5
R/W R/WR/W
SVMCR5 SVMCR4 SVMCR3 Description
0 0 0 REF30 signal is output from SV2 output pin (Initial value)
1 CAPREF30 signal is output from SV2 output pin
1 0 CREF signal is output from SV2 output pin
1 CTLMONI signal is output from SV2 output pin
1 0 0 DVCFG signal is output from SV2 output pin
1 CFG signal is output from SV2 output pin
1 0 DFG signal is output from SV2 output pin
1 DPG signal is output from SV2 output pin
SVMCR2 SVMCR1 SVMCR0 Description
0 0 0 REF30 signal is output from SV1 output pin (Initial value)
1 CAPREF30 signal is output from SV1 output pin
1 0 CREF signal is output from SV1 output pin
1 CTLMONI signal is output from SV1 output pin
1 0 0 DVCFG signal is output from SV1 output pin
1 CFG signal is output from SV1 output pin
1 0 DFG signal is output from SV1 output pin
1 DPG signal is output from SV1 output pin
——
——
SV2 pin servo monitor output control
SV1 pin servo monitor output control
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1024 of 1141
H'D0A4: CTL Gain Control Register CTLGR: Servo Port
0
0
1
0
2
0
3
0
4
0
567 CTLFB CTLGR3 CTLGR2 CTLGR1 CTLGR0
1
1R/WR/WR/W
0
CTLE/A
R/W R/WR/W
CTL select bit
0 AMP output
1 EXCTL
CTL amp feedback SW bit
0 CTLFB SW is OFF
1 CTLFB SW is ON
CTL amp gain setting bit
CTLGR3 CTLGR2 CTLGR1 CTLGR0 CTL outpu gain
0 0 0 0 35.0 dB
(Initial value)
1 37.5 dB
1 0 40.0 dB
1 42.5 dB
1 0 0 45.0 dB
1 47.5 dB
1 0 50.0 dB
1 52.5 dB
1 0 0 0 55.0 dB
1 57.5 dB
1 0 60.0 dB
1 62.5 dB
1 0 0 65.0 dB
1 67.5 dB
1 0 70.0 dB
1 72.5 dB
——
——
Bit
Initial value
R/W
:
:
:
H'D0B0: Vertic al Sync Signal Threshold Value Register VTR: Sync Detector (Servo)
0
0
1
0
W
2
0
W
3
0
4
0
W
5
0
6
1
7
WWW
VTR5 VTR4 VTR3 VTR2 VTR1 VTR0
1
Initial value :
——
——
Bit
R/W
:
:
:
H'D0B1: Horizontal Sync Signal Threshold Value Register HTR: Sync Detector (Servo)
0
0
1
0
W
2
0
W
3
0
456
1
7
WW
HTR3 HTR2 HTR1 HTR0
111
Initial value : ————
————
Bit
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1025 of 1141
H'D0B2: H Pulse Adjustment Start Time Setting Register H RTR: Sync Detector (Ser vo)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7HRTR4 HRTR3 HRTR2 HRTR1 HRTR0
0
W
HRTR7
WWW
HRTR6 HRTR5
Bit :
Initial value :
R/W :
H'D0B3: H Pulse Wi dth Setting Register H PWR: Sync Detector (Ser vo)
0
0
1
0
W
2
0
W
3
0
456
1
7
WW
HPWR3 HPWR2 HPWR1 HPWR0
111
Bit :
Initial value :
R/W :
————
————
H'D0B4: Noise Detecti on Window Setting Register NWR: Sync Detector (Servo)
0
0
1
0
W
2
0
W
3
0
4
0
W
5
0
6
1
7
WWW
NWR5 NWR4 NWR3 NWR2 NWR1 NWR0
1
Bit :
Initial value :
R/W :
——
——
H'D0B5: Noi se De te c ti on Re gi ste r NDR: Sync De te c tor (Se r vo)
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7NDR4 NDR3 NDR2 NDR1 NDR0
0
W
NDR7
WWW
NDR6 NDR5
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1026 of 1141
H'D0B6: Sync Si gnal Contr ol Re gi ste r SYNCR: Sync De te c tor (Se r vo)
0
0
1
0
R
2
0
R/(W)*
3
1
456
1
7
R/WR/W
NIS/VD NOIS FLD SYCT
111
Note: * Only 0 can be written.
Interrupt select bit
0 Noise level interrupt
1 VD interrupt (Initial value)
Noise detection flag
0 Noise count is less than four times of NDR setting value (Initial value)
1 Noise count is equal to or greater than four times of NDR setting value
Field detection flag
0 Odd field (Initial value)
1 Even field
Sync signal polarity select bit
SYCT Description Polarity
0 Positive
1 Negative
Initial value :
————
————
Bit
R/W
:
:
(Initial value)
Rev. 1.0, 02/ 00, page 1027 of 1141
H'D0B8: Servo Interrupt Enable Register 1 SIENR1: Servo Interrupt
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7IECAP3 IECAP2 IECAP1 IEHSW2 IEHSW1
0
R/W
IEDRM3
R/WR/WR/W
IEDRM2 IEDRM1
Drum phase error detection interrupt enable bit
0 Interrupt request is disabled by IRRDRM3
(Initial value)
1 Interrupt request is enabled by IRRDRM3
Drum speed error detection (lock detection)
interrupt enable bit
0 Interrupt request is disabled by IRRDRM2(Initial value)
1 Interrupt request is enabled by IRRDRM2
Drum speed error detection (OVF, latch)
interrupt enable bit
0 Interrupt request is disabled by IRRDRM1 (Initial value)
1 Interrupt request is enabled by IRRDRM1
Capstan phase error detection interrupt enable bit
0 Interrupt request is disabled by IRRCAP3 (Initial value)
1 Interrupt request is enabled by IRRCAP3
Capstan speed error detection (lock detection)
interrupt enable bit
0 Interrupt request is disabled by IRRCAP2 (Initial value)
1 Interrupt request is enabled by IRRCAP2
Capstan speed error detection (OVF, latch)
interrupt enable bit
0 Interrupt request is disabled by IRRCAP1 (Initial value)
1 Interrupt request is enabled by IRRCAP1
HSW timing generation (counter clear, capture)
interrupt enable bit
0 Interrupt request is disabled by IRRHSW2 (Initial value)
1 Interrupt request is enabled by IRRHSW2
HSW timing generator (OVW, match, STRIG)
interrupt enable bit
0 Interrupt request is disabled by IRRHSW1
(Initial value)
1 Interrupt request is enabled by IRRHSW1
Initial value :
Bit
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1028 of 1141
H'D0B9: Servo Interrupt Enable Register 2 SIENR2: Servo Interrupt
0
0
1
0
R/W
23456
1
7
R/W
IESNC IECTL
11111
Vertical sync signal interrupt enable bit
0 Interrupt (vertical sync signal interrupt) request is disabled
by IRRSNC (Initial value)
1 Interrupt (vertical sync signal interrupt) request is enabled
by IRRSNC
CTL interrupt enable bit
0 Interrupt request is disabled by IRRCTL
(Initial value)
1 Interrupt request is enabled by IRRCTL
Initial value :
——————
——————
Bit
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1029 of 1141
H' D0 BA: Se rvo Inter r upt Re que st Re g i st e r 1 SIRQ R1 : Ser vo Int errupt
0
0
1
0
R/(W)*
2
0
R/(W)*
3
0
4
0
R/(W)*
0
R/(W)*
56
0
7IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1
0
R/(W)*
IRRDRM3
R/(W)*R/(W)*R/(W)*
IRRDRM2 IRRDRM1
Note: * Only 0 can be written to clear the flag.
Drum phase error detector interrupt request bit
0 Drum phase error detector interrupt request is not generated (Initial value)
1 Drum phase error detector interrupt request is generated
Drum speed error detector (lock detection) interrupt request bit
0 Drum speed error detector (lock detection) interrupt request is not generated (Initial value)
1 Drum speed error detector (lock detection) interrupt request is generated
Drum speed error detector (OVF, latch) interrupt request bit
0 Drum speed error detector (OVF, latch) interrupt request is not generated (Initial value)
1 Drum speed error detector (OVF, latch) interrupt request is generated
Capstan phase error detector interrupt request bit
0 Capstan phase error detector interrupt request is not generated (Initial value)
1 Capstan phase error detector interrupt request is generated
Capstan speed error detector (lock detection) intrerrupt request bit
0 Capstan speed error detector (lock detection) interrupt request is not generated
(Initial value)
1 Capstan speed error detector (lock detection) interrupt request is generated
Capstan speed error detector (OVF, latch) interrupt request bit
0 Capstan speed error detector (OVF, latch) interrupt request in not generated
(Initial value)
1 Capstan speed error detector (OVF, latch) interrupt request is generated
HSW timing generator (counter clear, capture)
interrupt request bit
0 HSW timing generator (counter clear, capture) interrupt
request is not generated (Initial value)
0 HSW timing generator (counter clear, capture) interrupt
request is generated
HSW timing generator (OVW, match, STRIG)
interrupt request bit
0 HSW timing generator (OVM, match, STRIG)
interrupt request is not generated (Initial value)
1 HSW timing generator (OVM, match, STRIG)
interrupt request is generated
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1030 of 1141
H'D0BB: Servo Interrupt Re quest Re gister 2 SIRQR2 : Se r v o Interrupt
0
0
1
0
R/(W)*
23456
1
7
R/(W)*
IRRSNC IRRCTL
11111
Note: * Only 0 can be written to clear the flag.
Vertical sync signal interrupt request bit
0 Sync signal detector (VD, noise) interrupt
request is not generated (Initial value)
1 Sync signal detector (VD, noise) interrupt
request is generated
CTL interrupt request bit
0 CTL interrupt request is not
generated (Initial value)
1 CTL interrupt request is
generated
——————
——————
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1031 of 1141
H' D0E5: DDC Switch Regi ste r DDCSWR: I 2C Bus Int e rfa c e
0
1
1
1
W*
2
2
1
W*
2
3
1
4
0
R/(W)*
1
0
R/W
57 IF CLR3 CLR2 CLR1 CLR0
0
R/W
SWE 6
0
R/W
SW
W*
2
W*
2
IE
DDC mode switch interrupt enable bit
0 Disables an interrupt at automatic format switching (Initial value)
1 Enables an interrupt at automatic format switching
DDC mode switch
0I
2
C bus format is selected for IIC channel 0. (Initial value)
[Clearing condition]
(1) When 0 is written by software
(2) When an SCL falling edge is detected when SWE = 1
1 Formatless transfer is selected for IIC channel 0.
[Setting condition]
When 1 is written after SW = 0 is read
DDC mode switch enable
0 Disables automatic switching from formatless transfer to I
2
C bus
format transfer for IIC channel 0. (Initial value)
1 Enables automatic switching from formatless transfer to I
2
C bus
format transfer for IIC channel 0.
DDC mode switch interrupt flag
0 Interrupt has not been requested (Initial value)
[Clearing condition]
When 0 is written after IF = 1 is read
1 Interrupt has been requested
[Setting condition]
When an SCL falling edge is detected when SWE = 1
:
:
:
Bit
Initial value
R/W
Notes: 1. Only 0 can be written to clear the flag.
2. Always read as 1.
I
2
C clear control
Rev. 1.0, 02/ 00, page 1032 of 1141
H'D0E8: I2C Bus Control Regi st e r ICCR0: I 2C Bus Int e rface
7
ICE
0
R/W
6
IEIC
0
R/W
5
MST
0
R/W
4
TRS
0
R/W
3
ACKE
0
R/W
0
SCP
1
W
2
BBSY
0
R/W
1
IRIC
0
R/(W)*
Note: * Only 0 can be written to clear the flag.
I
2
C bus interface enable
0 I
2
C bus interface module disabled, with SCL and SDA signal pins (Initial value)
set to port function. SAR and SARX can be accessed.
1 I
2
C bus interface module enabled for transfer operation (pins SCL
and SCA are driving the bus). ICMR and ICDR can be accessed.
I
2
C bus interface interrupt enable
0 Interrupt request is disabled (Initial value)
1 Interrupt request is enabled
Acknowledge bit judgment selection
0 The value of the acknowledge bit is ignored, and continuous transfer is performed (Initial value)
1 If the acknowledge bit is 1, continuous transfer is interrupted
Bus busy
0 Bus is free (Initial value)
[Clearing conditions] When a stop condition is detected
1 Bus is busy
[Setting conditions] When a start condition is detected
I
2
C bus interface interrupt request flag
0 Waiting for transfer, or transfer in progress (Initial value)
[Clearing conditions]
(1) When 0 is written in IRIC after reading IRIC = 1
1 Interrupt requested
[Setting conditions]
• I
2
C bus format master mode
— When a start condition is detected in the bus line state after a start condition is
issued (when the TDRE flag is set to 1 because of first frame transmission)
— When a wait is inserted between the data and acknowledge bit when WAIT = 1
— At the end of data transfer
(when the TDRE or RDRF flag is set to 1)
— When a slave address is received after bus arbitration is lost
(when the AL flag is set to 1)
— When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
• I
2
C bus format slave mode
— When the slave address (SVA, SVAX) matches
(when the AAS and AASX flags are set to 1) and at the end of data transfer up
to the subsequent retransmission start condition or stop condition detection
(when the TDRE or RDRF flag is set to 1)
— When the general call address is detected
(when the ADZ flag is set to 1) and at the end of data transfer up to the
subsequent retransmission start condition or stop condition detection
(when the TDRE or RDRF flag is set to 1)
— When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
— When a stop condition is detected
(when the STOP or ESTP flag is set to 1)
• Synchronous serial format
— At the end of data transfer (when the TDRE or RDRF flag is set to 1)
— When a start condition is detected with serial format selected
— When a condition, other than the above, that sets the TDRE or RDRF flag to 1 is
detected
Start condition/stop condition prohibit
0 Writing 0 issues a start or stop condition, in combination
with the BBSY flag
1 Reading always returns a value of 1 (Initial value)
Writing is ignored
Master/slave select
Transmit/receive select
MST TRS Description
0 0 Slave receive mode (Initial value)
1 Slave transmit mode
1 0 Master receive mode
1 Master transmit mode
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1033 of 1141
H'D0E9: I2C Bus Stat us Re g i st e r ICSR0: I2C Bus Int e rfa c e
7
ESTP
0
R/(W)*
6
STOP
0
R/(W)*
5
IRTR
0
R/(W)*
4
AASX
0
R/(W)*
3
AL
0
R/(W)*
0
ACKB
0
R/W
2
AAS
0
R/(W)*
1
ADZ
0
R/(W)*
Note: * Only 0 can be written to clear the flag.
Error stop condition detection flag
0 No error stop condition (Initial value)
[Clearing conditions]
(1) When 0 is written in ESTP after reading ESTP = 1
(2) When the IRIC flag is cleared to 0
1 •In I
2
C bus format slave mode
Error stop condition detected
[Setting conditions]
– When a stop condition is detected during frame transfer
• In other mode
No meaning
Normal stop condition detection flag
0 No normal stop condition (Initial value)
[Clearing conditions]
(1) When 0 is written in STOP after reading STOP = 1
(2) When the IRIC flag is cleared to 0
1 • In I
2
C bus format slave mode
Normal stop condition detected
[Setting conditions]
– When a stop condition is detected after completion of frame transfer
• In other mode
No meaning
I
2
C bus interface continuous transmission/reception interrupt request flag
0 Waiting for transfer, or transfer in progress (Initial value)
[Clearing conditions]
(1) When 0 is written in IRTR after reading IRTR = 1
(2) When the IRIC flag is cleared to 0
1 Continuous transfer state
[Setting conditions]
• In I
2
C bus interface slave mode
– When the TDRE or RDRF flag is set to 1 when AASX = 1
• In other mode
– When the TDRE or RDRF flag is set to 1
Second slave address recognition flag
0 Second slave address not recognized (Initial value)
[Clearing conditions]
(1) When 0 is written in AASX after reading AASX = 1
(2) When a start condition is detected
(3) In master mode
1 Second slave address recognized
[Setting conditions]
– When the second slave address is detected in slave receive mode
Arbitration lost flag
0 Bus arbitration won (Initial value)
[Clearing conditions]
(1) When ICDR data is written (transmit mode) or read (receive mode)
(2) When 0 is written in AL after reading AL = 1
1 Arbitration lost
[Setting conditions]
(1) If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode
(2) If the internal SCL line is high at the fall of SCL in master transmit mode
Slave address recognition flag
0 Slave address or general call address not recognized (Initial value)
[Clearing conditions]
(1) When ICDR data is written (transmit mode) or read (receive mode)
(2) When 0 is written in AAS after reading AAS = 1
(3) In master mode
1 Slave address or general call address recognized
[Setting conditions]
– When the slave address or general call address is detected when FS = 0 in slave receive mode
General call address recognition flag
0 General call address not recognized (Initial value)
[Clearing conditions]
(1) When ICDR data is written (transmit mode) or read (receive mode)
(2) When 0 is written in ADZ after reading ADZ = 1
(3) In master mode
1 General call address recognized
[Setting conditions]
– When the general call address is detected when FSX = 0 or FS = 0 in slave receive mode
Acknowledge bit
0 Receive mode: 0 is output at acknowledge output timing (Initial value)
Transmit mode: Indicates that the receiving device has acknowldeged the data (signal is 0)
1 Receive mode; 1 is output at acknowledge output timing
Transmit mode: Indicates that the receiving device has not acknowldeged the data (signal is 1)
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1034 of 1141
H'D0EE: I2C Bus Data Registe r ICDR0: I2C Bus Int e rface
7
ICDR7
—
R/W
6
ICDR6
—
R/W
5
ICDR5
—
R/W
4
ICDR4
—
R/W
3
ICDR3
—
R/W
0
ICDR0
—
R/W
2
ICDR2
—
R/W
1
ICDR1
—
R/W
Initial value :
Note: Refer to section 23.2.1, I
2
C Bus Data Register (ICDR).
Bit
R/W
:
:
H' D0EE: Second Sl ave Addr e ss Re gi ste r SARX0: I2C B us Int e r f a c e
7
SVAX6
0
R/W
6
SVAX5
0
R/W
5
SVAX4
0
R/W
4
SVAX3
0
R/W
3
SVAX2
0
R/W
0
FSX
1
R/W
2
SVAX1
0
R/W
1
SVAX0
0
R/W
Format select
Used combined FS bit in SAR.
Initial value :
Note: Refer to section 23.2.3, Second Slave Address Register (SARX), and section 23.2.2, Slave Address Register (SAR).
Bit
R/W
:
:
Rev. 1.0, 02/ 00, page 1035 of 1141
H'D0EF: I2C Bus M o de Re g i st e r ICM R0: I2C B us Inter fa c e
7
MLS
0
R/W
6
WAIT
0
R/W
5
CKS2
0
R/W
4
CKS1
0
R/W
3
CKS0
0
R/W
0
BC0
0
R/W
2
BC2
0
R/W
1
BC1
0
R/W
MSB-first/LSB-first select
Note: * See bit 6 in the serial timer control register (STCR)
0 MSB-first (Initial value)
1 LSB-first
Wait insertion bit
0 Data and acknowledge bits transferred consecutively (Initial value)
1 Wait inserted between data and acknowledge bits
Transfer clock select bits
Bit counter
Bit/frame
BC2 BC1 BC0 Clock sync I
2
C bus format
serial format
0 0 0 8 9 (Initial value)
1 1 2
1 0 2 3
1 3 4
0 0 0 4 5
1 5 6
1 0 6 7
1 7 8
IICX* CKS2 CKS1 CKS0 Clock Transfer rate
φ=8 MHz φ=10 MHz
0 0 0 0 φ/28 286 kHz 357 kHz
1 φ/40 200 kHz 250 kHz
1 0 φ/48 167 kHz 208 kHz
1 φ/64 125 kHz 156 kHz
1 0 0 φ/80 100 kHz 125 kHz
1 φ/100 80.0 kHz 100 kHz
1 0 φ/112 71.4 kHz 89.3 kHz
1 φ/128 62.5 kHz 78.1 kHz
1 0 0 0 φ/56 143 kHz 179 kHz
1 φ/80 100 kHz 125 kHz
1 0 φ/96 83.3 kHz 104 kHz
1 φ/128 62.5 kHz 78.1 kHz
1 0 0 φ/160 50.0 kHz 62.5 kHz
1 φ/200 40.0 kHz 50.0 kHz
1 0 φ/224 35.7 kHz 44.6 kHz
1 φ/256 31.3 kHz 39.1 kHz
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1036 of 1141
H' D0 EF: Sl a v e Addr ess Re giste r SAR0 : I2C B us Interf a c e
7
SVA6
0
R/W
6
SVA5
0
R/W
5
SVA4
0
R/W
4
SVA3
0
R/W
3
SVA2
0
R/W
0
FS
0
R/W
2
SVA1
0
R/W
1
SVA0
0
R/W
Format select bit
DDCSWR SAR SARX Format select
Bit 6 Bit 0 Bit 0
SW FS FX
000I
2
C bus format
• SAR and SARX slave addresses recognized
1I
2
C bus format (Initial value)
• SAR slave address recognized
• SARX slave address ignored
10I
2
C bus format
• SAR slave address ignored
• SARX slave address recognized
1I
2
C bus format
• SAR and SARX slave addresses ignored
1 0 0 Formatless transfer (start and stop conditions
are not detected)
1• With acknowledge bit
0 0 Formatless transfer* (start and stop conditions
are not detected)
1• Without acknowledge bit
Bit
Initial value
R/W
:
:
:
Note: * Do not use this setting when automatically switching the made from
formatless transfer to I
2
C bus format by setting DDCSWR.
Rev. 1.0, 02/ 00, page 1037 of 1141
H'D100: Timer Interrupt Enable Register TIER: Timer X1
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/W
ICICE
R/W
ICIBE
0
R/W
ICIAE ICIDE OCIAE OCIBE OVIE ICSA
ICFA interrupt request (ICIA) is disabled (Initial value)
ICFA interrupt request (ICIA) is enabled
0
1
Input capture A interrupt enable bit
FTIA pin input is selected
for input capture A input
(Initial value)
HSW is selected for input
capture A input
0
1
Input capture input select A bit
ICFB interrupt request (ICIB) is disabled (Initial value)
ICFB interrupt request (ICIB) is enabled
0
1
Input capture B interrupt enable bit
ICFC interrupt request (ICIC) is disabled (Initial value)
ICFC interrupt request (ICIC) is enabled
0
1
Input capture C interrupt enable bit
ICFD interrupt request (ICID) is disabled (Initial value)
ICFD interrupt request (ICID) is enabled
0
1
Input capture D interrupt enable bit
Interrupt request (FOVI) is
disabled (Initial value)
Interrupt request (FOVI) is enabled
0
1
Timeout overflow interrupt enable bit
0 OCFB interrupt request (OCIB) is disabled
(Initial value)
OCFB interrupt request (OCIB) is enabled
1
Output compare interrupt B enable bit
OCFA interrupt request (OCIA) is disabled (Initial value)
OCFA interrupt request (OCIA) is enabled
0
1
Output compare interrupt A enable bit
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1038 of 1141
H'D101: Ti me r Contr ol / Status Regi ste r X TCSRX: Ti me r X1
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
R/ WR/(W)*
ICFB
0
R/(W)*
ICFA
R/(W)*
ICFD
R/(W)*
ICFC
R/(W)*
OCFB
R/(W)*
OCFA CCLRA
R/(W)*
OVF
Note: * Only 0 can be written to bits 7 to 1 to clear the flags.
Output compare flag A
[Clearing conditions]
When 0 is written to OCFA after reading
OCFA = 1 (Initial value)
[Setting conditions]
When FRC = OCRA
0
1
Output compare flag B
[Clearing conditions]
When 0 is written to OCFB after reading
OCFB = 1 (Initial value)
[Setting conditions]
When FRC = OCRB
0
1
Timer overflow
[Clearing conditions]
When 0 is written to OVF after reading
OVF = 1 (Initial value)
[Setting conditions]
When FRC changes from H'FFFF to
H'0000
0
1
Input capture flag D
[Clearing conditions]
When 0 is written to ICFD after reading
ICFD = 1 (Initial value)
[Setting conditions]
When input capture signal is generated
0
1
Input capture flag C
[Clearing conditions]
When 0 is written to ICFC after reading
ICFC = 1 (Initial value)
[Setting conditions]
When input capture signal is generated
0
1
Input capture flag B
[Clearing conditions]
When 0 is written to ICFB after reading
ICFB = 1 (Initial value)
[Setting conditions]
When FRC value is transferred to ICRB by
input capture signal
0
1
Input capture flag A
[Clearing conditions]
When 0 is written to ICFA after reading
ICFA = 1 (Initial value)
[Setting conditions]
When FRC value is transferred to ICRA by
input capture signal
0
1
Counter clearFRC clearing is disabled
(Initial value)
FRC clearing is enabled
0
1
Initial value :
Bit
R/W
:
:
Rev. 1.0, 02/ 00, page 1039 of 1141
H'D102: Free Running Count e r H FRCH: T i m e r X1
H'D103: Free Running Count e r L F RCL : Time r X1
0
3
0
R/W
5
0
R/W
7
0
9
0
R/W
11
0
13
0
15
R/WR/WR/W
0
R/W R/W
1
0
2
0
R/W
4
0
R/W
6
0
8
0
R/W
10
0
12
0
14
FRC
FRCH FRCL
R/WR/WR/WR/W
0
R/W
0
Bit :
Initial value :
R/W :
H'D104: O utput Compar e Re gi ste r AH , BH O CRAH , O CRBH : Ti me r X1
H'D105: O utput Compare Re gi ste r AL, BL O CRAL, O CRBL: Ti me r X1
1
3
1
R/W
5
1
R/W
7
1
9
1
R/W
11
1
13
1
15
R/WR/WR/W
1
R/W R/W
1
1
2
1
R/W
4
1
R/W
6
1
8
1
R/W
10
1
12
1
14
OCRA, OCRB
OCRAH, OCRBH OCRAL, OCRBL
R/WR/WR/WR/W
1
R/W
0
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1040 of 1141
H'D106: Ti me r Contr ol Re gi ster X TCRX: Ti me r X1
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
R/WR/W
IEDGB
0
R/W
IEDGA
R/W
IEDGD
R/W
IEDGC
R/W
BUFEB
R/W
BUFEA CKS0
R/W
CKS1
Capture at falling edge of input capture input A (Initial value)
Capture at rising edge of input capture input A
0
1
Input capture edge select A
Capture at falling edge of input capture input B (Initial value)
Capture at rising edge of input capture input B
0
1
Input capture edge select B
Capture at falling edge of input capture input C (Initial value)
Capture at rising edge of input capture input C
0
1
Input capture edge select C
Capture at falling edge of input capture input D (Initial value)
Capture at rising edge of input capture input D
0
1
Input capture edge select D
ICRC is not used as buffer register for ICRB
(Initial value)
ICRC is used as buffer register for ICRB
0
1
Buffer enable B
ICRC is not used as buffer register for ICRA (Initial value)
ICRC is used as buffer register for ICRA
0
1
Buffer enable A
Clock selct bit Clock select
00 CKS0CKS1
10 01
Internal clock: count at φ/4
(Initial value)
Internal clock: count at φ/16
Internal clock: count at φ/64
11 DVCFG: Edge detection
pulse selected by CFG
frequency division timer
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1041 of 1141
H'D107: Timer O utput Compare Control Register TOCR: Timer X1
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
R/WR/W
ICSC
0
R/W
ICSB
R/W
OSRS
R/W
ICSD
R/W
OEB
R/W
OEA OLVLB
R/W
OLVLA
FTIB pin is selected for input capture B input (Initial value)
VD is selected for input capture B input
0
1
Input capture input select B
Low level
(Initial value)
High level
0
1
Output level B
FTIC pin is selected for input capture C input (Initial value)
DVCTL is selected for input capture C input
0
1
Input capture input select C
FTID pin is selected for input capture D input (Initial value)
NHSW is selected for input capture D input
0
1
Input capture input select D
OCRA register is selected (Initial value)
OCRB register is selected
0
1
Output compare register select
Low level (Initial value)
High level
0
1
Output level A
Output compare A output is disabled (Initial value)
Output compare A output is enabled
0
1
Output enable A
Initial value :
0
1
Output enable B
Output compare B output is disabled
(Initial value)
Output compare B output is enabled
Bit
R/W
:
:
Rev. 1.0, 02/ 00, page 1042 of 1141
H'D108: Input Captur e Re gi ste r AH ICRAH : Ti me r X1
H'D109: Input Captur e Re gi ste r AL ICRAL: Ti me r X1
H' D1 0A: Input Capt ur e Re giste r BH ICRB H : Time r X1
H'D10B: Input Captur e Re gi ster BL ICRBL: Ti me r X1
H' D1 0C: Input Capt ur e Re giste r CH ICRCH: T i m e r X1
H' D1 0D: Input Capt ur e Re giste r CL ICRCL: T i m e r X1
H'D10E: Input Captur e Re gi ste r DH ICRDH : Ti me r X1
H' D1 0F: Input Capt ur e Re giste r DL ICRDL : T i m e r X1
0
3
0
R
5
0
R
7
0
9
0
R
11
0
13
0
15
RRR
0
RR
1
0
2
0
R
4
0
R
6
0
8
0
R
10
0
12
0
14
ICRA, ICRB, ICRC, ICRD
ICRAH, ICRBH, ICRCH, ICRDH ICRAL, ICRBL, ICRCL, ICRDL
RRRR
0
R
0
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1043 of 1141
H'D110: Timer M ode Register B TM B: Time r B
0
0
1
0
R/W
2
0
R/W
3
1
4
1
5
0
6
0
7
R/WR/W
TMBIE
R/(W)*
TMBIF
0
R/W
TMB17 TMB12 TMB11 TMB10
Note: * Only 0 can be written to clear the flag.
Interval function is selected (Initial value)
Auto reload function is selected
0
1
Auto reload function select bit
[Setting conditions]
When TCB overflows
[Clearing conditions] (Initial value)
When 0 is written after reading 1
0
1
Timer B interrupt request flag
Timer B interrupt request is disabled (Initial value)
Timer B interrupt request is enabled
0
1
Timer B interrupt enable bit
00 0 Internal clock: Count at φ/16384 (Initial value)
TMB11 TMB10TMB12 Clock select
0 1 Internal clock: Count at φ/4096
1
0
0
0 0 Internal clock: Count at φ/1024
1 1 Internal clock: Count at φ/512
01 0 Internal clock: Count at φ/128
0 1 Internal clock: Count at φ/32
1
1
1
1 0 Internal clock: Count at φ/8
1 1 Count at rising/falling edge of external
event (TMBI)*
Note: * External event edge selection is set at PMRA6 in port mode register A
(PMRA).
See section 12.2.4, Port Register A (PMRA).
Clock select bit
Initial value :
——
——
Bit
R/W
:
:
H'D111: Timer Counter B TCB: Timer B
0
0
1
0
R
2
0
R
345
0
6
0
7
RR
TCB15
0
R
TCB14
0
R
TCB13
R
TCB16
0
R
TCB17 TCB12 TCB11 TCB10
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1044 of 1141
H'D111: Timer Load Register B TLB: Timer B
0
0
1
0
W
2
0
W
345
0
6
0
7
WW
TLB15
0
W
TLB14
0
W
TLB13
W
TLB16
0
W
TLB17 TLB12 TLB11 TLB10
Bit :
Initial value :
R/W :
H'D112: Timer L M ode Register LM R: Timer L
0
0
1
0
R/W
2
0
R/W
3
0
4
1
5
1
6
0
7
R/WR/WR/W
LMIE
0
R/(W)*
LMIF LMR3 LMR2 LMR1 LMR0
Note: * Only 0 can be written to clear the flag.
Timer L interrupt request flag
[Clearing conditions] (Initial value)
When 0 is written after reading 1
[Setting conditions]
When LTC overflow, underflow or compare
match clear occurs
0
1
Timer L interrupt enable bit
Timer L interrupt request is disabled (Initial value)
Timer L interrupt request is enabled
0
1
Up count control (Initial value)
Down count control
0
1
Up/down count control
Clock select bit
Clock select
00 0 Count at rising edge of PB and REC-CTL
(Initial value)
LMR1 LMR0LMR2
1 Count at falling edge of PB and REC-CTL
1 * Count DVCFG2
01 * Internal clock: Count at φ/128
1 * Internal clock: Count at φ/64
Note: * Don't care.
——
——
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1045 of 1141
H'D113: Linear Ti me Counter LTC: Timer L
0
0
1
0
R
2
0
3
0
456
0
7
RRRR
LTC6
0
R
LTC5
0
R
LTC4
0
R
LTC7 LTC3 LTC2 LTC1 LTC0
Bit :
Initial value :
R/W :
H'D113: Re l oad/ Compare M atc h Re gi ste r RCR: Time r L
0
0
1
0
W
2
0
3
0
456
0
7
WWWW
RCR6
0
W
RCR5
0
W
RCR4
0
W
RCR7 RCR3 RCR2 RCR1 RCR0
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1046 of 1141
H'D118: Timer R Mode Regi ster 1 TM RM1: Ti mer R
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/W
RLD
R/W
AC/BR
0
R/W
CLR2 RLCK PS21 PS20 RLD/CAP CPS
TMRU-2 is not cleard at the time of capture (Initial value)
TMRU-2 is cleard at the time of capture
0
1
TMRU-2 clear select bit
Deceleration (Initial value)
Acceleration
0
1
Acceleration/deceleration select bit
TMRU-2 is not used as reload timer (Initial value)
TMRU-2 is used as reload timer
0
1
Execution/non-execution of reload by TMRU-2
Reload at CFG rising edge (Initial value)
Reload at TMRU-2 underflow
0
1
TMRU-2 reload timing select bit
00 Count at TMRU-1 underflow (Initial value)
PS20PS21
1 PSS, count at φ/256
01 PSS, count at φ/128
PSS, count at φ/64
1
TMRU-2 clock source select bits
Description
Capture signal at CFG rising edge
(Initial value)
Capture signal at IRQ3 edge
0
1
TMRU-1 capture signal select bit
TMRU-1 functions as reload timer (Initial value)
TMRU-1 functions as capture timer
0
1
TMRU-1 operation mode select bit
Initial value :
Bit
R/W
:
:
Rev. 1.0, 02/ 00, page 1047 of 1141
H'D119: Timer R Mode Regi ster 2 TM RM2: Ti mer R
0
0
1
0
R/(W)*
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/(W)*R/WR/W
PS10
R/W
PS11
0
R/W
LAT PS31 PS30 CP/SLM CAPF SLW
TMRU-1 clock source select bits
Description
00 Count at CFG rising edge (Initial value)
PS10PS11
1 PSS, count at φ/4
01 PSS, count at φ/256
1 PSS, count at φ/512
TMRU-3 clock source select bits
Description
00 Count at rising edge of DVCTL from frequency divider (Initial value)
PS30PS31
1 PSS, count at φ/4096
01 PSS, count at φ/2048
1 PSS, count at φ/1024
Interrupt select bit
Interrupt request by TMRU-2 capture signal is enabled (Initial value)
Interrupt request by slow tracking mono-multi end is enabled
0
1
Capture signal flag
[Clearing conditions] (Initial value)
When 0 is written after reading 1
[Setting conditions]
When TMRU-2 capture signal is generated while CP/SLM bit = 0
0
1
Slow tracking mono-multi flag
[Clearing conditions] (Initial value)
When 0 is written after reading 1
[Setting conditions]
When slow tracking mono-multi ends while
CP/SLM bit = 1
0
1
TMRU-2 captrue signal select bits
*0 Capture at TMRU-3 underflow (Initial value)
CPSLAT
01 Capture at CFG rising edge
1 Capture at IRQ3 edge
Description
Note: * Don't care.
Initial value :
Bit
R/W
:
:
Note: * The CAPF bit and the SLW bit, respectively, works to latch the interrupt causes and writing 0
only is valid. Consequently, when these bits are being set to 1, respective interrupt requests
will not be issued. Therefore, it is necessary to check these bits during the course of the
interrupt processing routine to have them cleared.
Also priority is given to the set and, when an interrupt cause occur while the a clearing
command (BCLR, MOV, etc.) is being executed, the CAPF bit and the SLW bit will not be
cleared respectively and it thus becomes necessary to pay attention to the clearing timing.
Rev. 1.0, 02/ 00, page 1048 of 1141
H'D11A: Timer R Capture Register 1 TM RCP1: Time R
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
R
TMRC17
R
TMRC16
R
TMRC15
R
TMRC14
R
TMRC13
R
TMRC12
R
TMRC11
R
TMRC10
Bit :
Initial value :
R/W :
H'D11B: Timer R Capture Register 2 TM RCP2: Time R
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
R
TMRC27
R
TMRC26
R
TMRC25
R
TMRC24
R
TMRC23
R
TMRC22
R
TMRC21
R
TMRC20
Bit :
Initial value :
R/W :
H'D11C: Timer R Load Register 1 TM RL1: Time r R
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
W
TMR17
W
TMR16
W
TMR15
W
TMR14
W
TMR13
W
TMR12
W
TMR11
W
TMR10
Bit :
Initial value :
R/W :
H'D11D: Timer R Load Register 2 TM RL2: Time r R
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
W
TMR27
W
TMR26
W
TMR25
W
TMR24
W
TMR23
W
TMR22
W
TMR21
W
TMR20
Bit :
Initial value :
R/W :
H'D11E: Timer R Load Register 3 TM RL3: Timer R
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
W
TMR37
W
TMR36
W
TMR35
W
TMR34
W
TMR33
W
TMR32
W
TMR31
W
TMR30
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1049 of 1141
H' D1 1F: T i m e r R Co nt r o l / St a tus Regi st e r TM RCS: Time r R
0
1
1
1
2
0
R/(W)*
3
0
4
0
R/(W)*
5
0
6
0
7
R/(W)*R/W
TMRI1E
R/W
TMRI2E
0
R/W
TMRI3E TMRI3 TMRI2 TMRI1
Note: * Only 0 can be written to clear the flag.
TMRI3 interrupt request is disabled (Initial value)
TMRI3 interrupt request is enabled
0
1
TMRI3 interrupt enable bit
TMRI2 interrupt request is disabled (Initial value)
TMRI2 interrupt request is enabled
0
1
TMRI2 interrupt enable bit
TMRI1 interrupt request is disabled (Initial value)
TMRI1 interrupt request is enabled
0
1
TMRI1 interrupt enable bit
TMRI1 interrupt request flag
[Clearing conditions] (Initial value)
When 0 is written after reading 1
[Setting conditions]
When TMRU-1 underflows
0
1
TMRI2 interrupt request flag
[Clearing conditions] (Initial value)
When 0 is written after reading 1
[Setting conditions]
When TMRU-2 underflows or when capstan motor
acceleration/deceleration operation ends
0
1
TMRI3 interrupt request flag
[Clearing conditions] (Initial value)
When 0 is written after reading 1
[Setting conditions]
When interrupt source selected at CP/SLM bit in
TMRM2 is generated
0
1
Initial value :
——
——
Bit
R/W
:
:
Rev. 1.0, 02/ 00, page 1050 of 1141
H'D120: PWM Data Register L P WDRL: 14-Bit PWM
0
0
1
0
2
0
3
0
4
0
5
0
67
W
PWDRL0
W
PWDRL1
W
PWDRL2
W
PWDRL3
W
PWDRL4
W
PWDRL5
0
W
PWDRL6
W
PWDRL7
0
Bit :
Initial value :
R/W :
H'D121: PW M Data Re gi ste r U P WDRU: 14-Bi t PW M
0
0
1
0
2
0
3
0
4
0
5
0
6
1
7
W
PWDRU0
W
PWDRU1
W
PWDRU2
W
PWDRU3
W
PWDRU4
W
PWDRU5
1
Bit :
Initial value :
R/W :
——
——
H'D122: PWM Control Regi sterP WCR: 14-Bit PWM
0
0
1
1
2
1
3
1
4
1
5
1
6
1
7
R/W
PWCR0
1
Clock select bit
Note: tφ: PWM input clock frequency
Input clock is φ/2 (tφ = 2/φ)(Initial value)
Generate PWM waveform with conversion frequency of
16384/φ and minimum pulse width of 1/φ
Input clock is φ/4 (tφ = 4/φ)
Generate PWM waveform with conversion frequency of
32768/φ and minimum pulse width of 2/φ
0
1
Initial value :
———————
———————
Bit
R/W
:
:
H'D126: 8-Bit PWM Data Register 0 PWR0: 8-Bit P WM
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PW04 PW03 PW02 PW01 PW00
0
W
PW07
WWW
PW06 PW05
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1051 of 1141
H'D127: 8-Bit PWM Data Register 1 PWR1: 8-Bit P WM
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PW14 PW13 PW12 PW11 PW10
0
W
PW17
WWW
PW16 PW15
Bit :
Initial value :
R/W :
H'D128: 8-Bit PWM Data Register 2 PWR2: 8-Bit P WM
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PW24 PW23 PW22 PW21 PW20
0
W
PW27
WWW
PW26 PW25
Bit :
Initial value :
R/W :
H'D129: 8-Bit PWM Data Register 3 PWR3: 8-Bit P WM
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PW34 PW33 PW32 PW31 PW30
0
W
PW37
WWW
PW36 PW35
Bit :
Initial value :
R/W :
H'D12A: 8-Bit PWM Control Regi ster PW8CR: 8-Bit PWM
0
0
1
0
R/W
2
0
R/W
3
0
4567 PWC3 PWC2 PWC1 PWC0
R/WR/W
1111
Output polarity select bits
Positive polarity (Initial value)
Negative polarity
0
1(n = 3 to 0)
Bit :
Initial value :
R/W :
————
————
H' D1 2C: Input Capt ur e Re giste r 1 ICR1: P SU
0
0
1
0
R
2
0
R
3
0
4
0
R
0
R
56
0
7ICR14 ICR13 ICR12 ICR11 ICR10
0
R
ICR17
RRR
ICR16 ICR15
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1052 of 1141
H'D12D: Prescaler Unit Control/Status Register PCSR: PSU
0
0
1
0
R/W
2
0
R/W
3
1
4
0
R/W
5
0
6
0
7
R/WR/W
ICEG
R/W
ICIE
0
R/(W)*
ICIF NCon/off DCS2 DCS1 DCS0
Note: * Only 0 can be written to clear the flag.
Interrupt request by input capture is disabled (Initial value)
Interrupt request by input capture is enabled
0
1
Input capture interrupt enable bit
Frequency division clock output select bits
Description
00 0 PSS, output φ/32
(Initial value)
DCS1 DCS0DCS2
1 PSS, output φ/16
1 0 PSS, output φ/8
1 PSS, output φ/4
01 0 PSW, output φW/32
1 PSW, output φW/16
1 0 PSW, output φW/8
1 PSW, output φW/4
Input capture interrupt flag
[Clearing conditions] (Initial value)
When 0 is written after reading 1
[Setting conditions]
When input capture is executed at IC pin edge
0
1
Noise cancel function of IC pin is disabled (Initial value)
Noise cancel function of IC pin is enabled
0
1
Noise cancel ON/OFF bit
IC pin edge select bit
Falling edge of IC pin input is detected (Initial value)
Rising edge of IC pin input is detected
0
1
Initial value :
—
—
Bit
R/W
:
:
Rev. 1.0, 02/ 00, page 1053 of 1141
H'D130: Softwar e Tr i gge r A/ D Re sul t Re gi ste r H ADRH : A/ D Conve r te r
H'D131: Softwar e Tr i gge r A/ D Re sul t Re gi ste r L ADRL: A/ D Conve r te r
ADRH ADRL
1 032547
0
R
6
0
R
9
0
R
8
0
R
11
0
R
10
0
R
0
R
0
R
0
R
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
0
R
12131415
000000
Bit :
Initial value :
R/W :
——————
——————
H'D132: Hardware Tr i gger A/D Result Register H AHRH: A/D Converter
H'D133: Hardware Tr i gger A/D Result Register L AHRL: A/D Converter
AHRH AHRL
1 032547
0
R
6
0
R
9
0
R
8
0
R
11
0
R
10
0
R
0
R
0
R
0
R
AHR9 AHR8 AHR7 AHR6 AHR5 AHR4 AHR3 AHR2 AHR1 AHR0
0
R
12131415
000000
Bit :
Initial value :
R/W :
——————
——————
Rev. 1.0, 02/ 00, page 1054 of 1141
H' D134: A/D Control Re gi ste r ADCR: A/ D Conve r t e r
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
0
6
1
7
R/WR/WR/W
HCH1
0
R/W
CK HCH0 SCH3 SCH2 SCH1 SCH0
Clock select
0 Conversion frequency = 266 states (Initial value)
1 Conversion frequency = 134 states
Hardware channel select bits
HCH1 HCH2 Analog input channel
0 0 AN8 (Initial value)
1 AN9
1 0 ANA
1 ANB
Software channel select bits
SCH3 SCH2 SCH1 SCH0 Analog input channel
0 0 0 0 AN0 (Initial value)
1 AN1
1 0 AN2
1 AN3
1 0 0 AN4
1 AN5
1 0 AN6
1 AN7
1 0 0 0 AN8
1 AN9
1 0 ANA
1 ANB
1 * * Software-triggered conversion
channel is not selected
Notes: 1. If conversion is started by software when SCH3 to
SCH0 are set to 11xx, the conversion result is
undetermined. Hardware- or external-triggered
conversion, however, will be performed on the channel
selected by HCH1 and HCH0.
2. * Don't care.
Initial value :
—
—
Bit
R/W
:
:
Rev. 1.0, 02/ 00, page 1055 of 1141
H' D135: A/D Control / Status Register ADCSR: A/ D Conve rte r
0
0
1
0
R
2
0
R
3
0
4
0
R/W
5
0
67
R/(W)* RR/W
ADIE
0
R/(W)*
SEND SST HST BUSY SCNLHEND
1
A/D interrupt enable bit
0 Interrupt (ADI) upon A/D conversion end is disabled (Initial value)
1 Interrupt (ADI) upon A/D conversion end is enabled
Software A/D start flag
0 Read: Indicates that software-triggered A/D conversion
has ended or been stopped (Initial value)
Write: Software-triggered A/D conversion is aborted
1 Read: Indicates that software-triggered A/D conversion
is in progress
Write: Starts software-triggered A/D conversion
Busy flag
0 No contention for A/D conversion (Initial value)
1 Indicates an attempt to execute software-triggered
A/D conversion while hardware- or external-triggered
A/D conversion was in progress.
Software-triggered A/D conversion cancel flag
0 No contention for A/D conversion
(Initial value)
1 Indicates that software-triggered A/D
conversion was canceled by the start of
hardware-triggered A/D conversion.
Hardware A/D status flag
0 Read: Hardware- or external -triggered A/D conversion is
not in progress (Initial value)
Write: Hardware- or external-triggered A/D conversion is
aborted
1 Hardware- or external-triggered A/D conversion is in
progress.
Software A/D end flag
0 [Clearing conditions] (Initial value)
When 0 is written after reading 1
1 [Setting conditions]
When software-triggered A/D conversion has ended
Hardware A/D end flag
0 [Clearing conditions] (Initial value)
When 0 is written after reading 1
1 [Setting conditions]
When hardware- or external-triggered A/D
conversion has ended
Initial value :
—
—
Note: * Only 0 can be written to clear the flag.
Bit
R/W
:
:
Rev. 1.0, 02/ 00, page 1056 of 1141
H'D136: A/D Trigger Select Register ADTSR: A/D Converter
0123
0
4
R/W
567 TRGS1
0
R/W
TRGS0
111111
Trigger select bits
TRGS1 TRGS0
0 0 Hardware- or external-triggered A/D
conversion is disabled (Initial value)
1 Hardware-triggered (ADTRG) A/D conversion
is selected
1 0 Hardware-triggered (DFG) A/D conversion
is selected
1 External-triggered (ADTRG) A/D conversion
is selected
Initial value :
——————
——————
Bit
R/W
:
:
H'D138: Timer Load Register K TLK : Ti mer J
0
1
1
1
W
2
1
W
3
1
4
1
W
5
1
6
1
7
WWW
TLR25
W
TLR26
1
W
TLR27 TLR24 TLR23 TLR22 TLR21 TLR20
Bit :
Initial value :
R/W :
H'D138: Timer Counter K TCK: Ti mer J
0
1
1
1
R
2
1
R
3
1
4
1
R
5
1
6
1
7
RRR
TDR25
R
TDR26
1
R
TDR27 TDR24 TDR23 TDR22 TDR21 TDR20
Bit :
Initial value :
R/W :
H'D139: Timer Load Register J TLJ: Time r J
0
1
1
1
W
2
1
W
3
1
4
1
W
5
1
6
1
7
WWW
TLR15
W
TLR16
1
W
TLR17 TLR14 TLR13 TLR12 TLR11 TLR10
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1057 of 1141
H'D139: Timer Counter J TCJ: Timer J
0
1
1
1
R
2
1
R
3
1
4
1
R
5
1
6
1
7
RRR
TDR15
R
TDR16
1
R
TDR17 TDR14 TDR13 TDR12 TDR11 TDR10
Bit :
Initial value :
R/W :
H'D13A: Timer M ode Regi ster J TM J: Ti mer J
0
0
1
0
R
2
0
R/W
3
0
4
0
R/W
5
0
6
0
7
R/WR/WR/W
ST
R/W
PS10
0
R/W
PS11 8/16 PS21 PS20 TGL T/R
TMJ-2 toggle flag
TMJ-2 toggle output is 0(Initial value)
TMJ-2 toggle output is 1
0
1
Timer output/remote-controller output
select bit TMJ-1 timer output
(Initial value)
TMJ-1 toggle output (data
transmitted from remote
controller)
0
1
TMJ-1 and TMJ-2 operate separately (Initial value)
TMJ-1 and TMJ-2 operate together as 16-bit
0
1
8-bit/16-bit operation select bit
Stop TMJ-1 clock supply in remote control mode (Initial value)
Start TMJ-1 clock supply in remote control mode
0
1
Remote-controlled operation start bit
Note: * External clock edge selection is set in the IRQ edge select register (IEGR).
See section 6.2.4, IRQ Edge Select Register (IEGR).
When using external clock in remote control mode, set opposite edges for IRQ1 and IRQ2 edges
(eg. When falling edge is set for IRQ1, set rising edge for IRQ2. When rising edge is set for IRQ1,
set falling edge for IRQ2).
00 PS10PS11
1
01
PSS, count at φ/512 (Initial value)
PSS, count at φ/256
PSS, count at φ/4
1 Count at rising/falling edge of external clock ( )*
TMJ-1 input clock select bits Description
Note: * External clock edge selection is set in the IRQ edge select register (IEGR).
See section 6.2.4, IRQ Edge Select Register (IEGR).
00 PS20PS21
1
01
PSS, count at φ/16384 (Initial value)
PSS, count at φ/2048
Count at TMJ-1 underflow
1 Count at rising/falling edge of external clock ( ) *
TMJ-2 input clock select bits Description
Initial value :
Bit
R/W
:
:
Rev. 1.0, 02/ 00, page 1058 of 1141
H'D13B: Timer J Control Regi ster TM JC: Time r J
01
0
2
0
R/W
34
0
R/W
5
0
6
0
7
R/WR/W
MON1
R/W
BUZZ0
0
R/W
BUZZ1 MON0 TMJ2IE TMJ1IE
11
φ/4096 (Initial value)
BUZZ0 Output signalBUZZ1
Frequency when
φ
= 10 MHz
φ/8192 2.44 kHz
1.22 kHz
Output monitor signal
00
1
10
1 Output timer J BUZZ signal
Buzzer output select bits
TMJ2I interrupt request is disabled (Initial value)
TMJ2I interrupt request is enabled
0
1
TMJ2I interrupt enable bit
PS22
Used in combination with bits PS21
and PS20 to select the TMJ-2
input clock.
TMJ1I interrupt request is disabled
(Initial value)
TMJ1I interrupt request is enabled
0
1
TMJ1I interrupt enable bit
PB or REC-CTL (Initial value)
MON0MON1
DVCTL
Output TCA7
00
1
1*
Monitor output select bits
Monitor output select
Note: * Don't care.
TMJ-2 expansion function is enabled
EXN
TMJ-2 expansion function is disabled (Initial value)
0
1
Expansion function control bit
Description
Initial value :
EXN PS22
R/W R/W
Bit
R/W
:
:
Rev. 1.0, 02/ 00, page 1059 of 1141
H'D13C: Timer J Status Register TMJS: Time r J
0123456
0
7
R/(W)*
TMJ1I
0
R/(W)*
TMJ2I
111111
Note: * Only 0 can be written to clear the flag.
TMJ1I interrupt request flag
[Clearing conditions] (Initial value)
When 0 is written after reading 1
[Setting conditions]
When TMJ-1 underflows
0
1
TMJ2I interrupt request flag
[Clearing conditions] (Initial value)
When 0 is written after reading 1
[Setting conditions]
When TMJ-2 underflows
0
1
Initial value :
——————
——————
Bit
R/W
:
:
Rev. 1.0, 02/ 00, page 1060 of 1141
H'D148: Serial Mode Register SMR1: SCI1
7
C/
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
Asynchronous mode (Initial value)
Clock synchronous mode
0
1
Communication mode
Multiprocessor function is disabled
(Initial value)
Multiprocessor format is selected
0
1
Multiprocessor mode
Clock select Clock select
00 CKS0CKS1
1
01
φ clock (Initial value)
φ/4 clock
φ/16 clock
1φ/64 clock
8-bit data
7-bit data*
0
1
Character length
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted,
and LSB-first/MSB-first selection is not available.
Even parity*
1
Odd parity*
2
0
1
Parity mode
Notes: 1. When even parity is set, parity bit addition is performed in transmission
so that the total number of 1 bits in the transmit character plus the parity
bit is even. In reception, a check is performed to see if the total number
of 1 bits in the receive character plus the parity bit is even.
2. When odd parity is set, parity bit addition is performed in transmission
so that the total number of 1 bits in the transmit character plus the parity
bit is odd. In reception, a check is performed to see if the total number
of 1 bits in the receive character plus the parity bit is odd.
1 stop bits*
1
2 stop bits*
2
0
1
Stop bit length
Notes: 1. In transmission, a single 1 bit (stop bit) is added to the end
of a transmit character before it is sent.
2. In transmission, two 1 bits (stop bits) are added to the end
of a transmit character before it is sent.
Parity bit addition and checking disabled
Parity bit addition and checking enabled*
0
1
Parity enable
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/ bit
is added to transmit data before transmission. In reception, the parity bit is
checked for the parity (even or odd) specified by the O/ bit.
Initial value :
(Initial value)
(Initial value)
(Initial value)
(Initial value)
Bit
R/W
:
:
Rev. 1.0, 02/ 00, page 1061 of 1141
H'D149: Bi t Rate Re gi ster BRR1: SCI1
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1062 of 1141
H'D14A: Serial Control Register SCR1: SCI1
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Transmit-data-empty interrupt (TXI) request is disabled* (Initial value)
Transmit-data-empty interrupt (TXI) request is enabled
0
1
Transmit interrupt enable bit
Note: * TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0,
or clearing the TIE bit to 0.
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request is disabled* (Initial value)
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request is enabled
0
1
Receive interrupt enable bit
Note: * RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF, FER, PER, or ORER flag,
then clearing the flag to 0, or clearing the RIE bit to 0.
Transmission is disabled
*1
(Initial value)
Transmission is enabled
*2
0
1
Transmit enable bit
Notes: 1. The TDRE flag in SSR is fixed at 1.
2. In this state, serial transmission is started when transmit data is written to TDR and TDRE flag in SSR
is cleared to 0.
SMR setting must be performed to decide the transmission format before setting the TE bit to 1.
Reception is disabled
*1
(Initial value)
Reception is enabled
*2
0
1
Receive enable bit
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states.
2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial
clock input is detected in synchronous mode.
SMR setting must be performed to decide the reception format before setting the RE bit to 1.
Multiprocessor interrupts are disabled (normal reception performed) (Initial value)
[Clearing conditions]
(1) When the MPIE bit is cleared to 0
(2) When data with MPB = 1 is received
Multiprocessor interrupt are enabled*
Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF,
FER, and ORER flags in SSR1 are disabled until data with the multiprocessor bit set to 1 is received.
0
1
Multiprocessor interrupt enable bit
Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and
setting of the RDRF, FER, and ORER flags in SSR, is not performed. When receive data with MPB = 1 is received,
the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts
(when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled.
Clock enable bits
Notes: 1. Initial value
2. Outputs a clock of the same frequency as the bit rate.
3. Inputs a clock with a frequency 16 times the bit rate.
Clock select
00 Internal clock/SCK pin functions as I/O port
*1
(Initial value)
CKE0CKE1
Internal clock/SCK pin functions as synchronous clock output
*1
1 Internal clock/SCK pin functions as clock output
*2
Internal clock/SCK pin functions as synchronous clock output
01 External clock/SCK pin functions as clock input
*3
External clock/SCK pin functions as synchronous clock input
1 External clock/SCK pin functions as clock input
*3
Asynchronous mode
Clock synchronous mode
Asynchronous mode
Clock synchronous mode
Asynchronous mode
Clock synchronous mode
Asynchronous mode
Clock synchronous mode External clock/SCK pin functions as synchronous clock input
Transmit-end interrupt (TEI) request is disabled* (Initial value)
Transmit-end interrupt (TEI) request is enabled*
0
1
Transmit end interrupt enable bit
Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it
to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1063 of 1141
H'D14B: Tr ansmi t Data Re gi ste r TDR1: SCI1
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1064 of 1141
H'D14C: Serial Status Register SSR1: SCI1
Data with a 0 multiprocessor bit is transmitted (Initial value)
Data with a 1 multiprocessor bit is transmitted
0
1
Multiprocessor bit transfer
Transmit data register empty
[Clearing conditions]
When 0 is written in TDRE after reading TDRE = 1
[Setting conditions]
(1) When the TE bit in SCR1 is 0
(2) When data is transferred from TDR1 to TSR1 and data can be written to TDR1
0
1
Transmit end
0 [Clearing conditions]
(1) When 0 is written in TDRE after reading TDRE = 1
[Setting conditions]
(1) When the TE bit in SCR1 is 0
(2) When TDRE = 1 at trasmission of the last bit of a 1-byte serial
transmit character
1
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Multiprocessor bit
0 [Clearing conditions]*
When data with a 0 multiprocessor bit is received
[Setting conditions]
When data with a 1 multiprocessor bit is reveived
1
Note: * Retains its previous state when the RE bit in SCR1 is cleared to 0 with
multiprocessor format.
[Clearing conditions]
When 0 is written in PER after reading PER = 1
*1
[Setting conditions]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/ bit in SMR
*2
0
1
Parity error
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR1 is cleared to 0.
2. If a parity error occurs, the receive data is transferred to RDR1 but the RDRF flag is not set. Also,
subsequent serial reception cannot be continued while the PER flag is set to 1. In synchronous
mode, serial transmission cannot be continued, either.
Receive data register full
[Clearing conditions]
When 0 is written in RDRF after reading RDRF = 1
[Setting conditions]
When serial reception ends normally and receive data is transferred from RSR to RDR
0
1
Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception
or when the RE bit in SCR1 is cleared to 0. If reception of the next data is completed while the RDRF flag is still set
to 1, an overrun error will occur and the receive data will be lost.
Overrun error
[Clearing conditions]
When 0 is written in ORER after reading ORER = 1
*1
[Setting conditions]
When the next serial reception is completed while RDRF = 1
*2
0
1
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR1 is cleared to 0.
2. The receive data prior to the overrun error is retained in RDR1, and the data received subsequently is lost.
Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In synchronous
mode, serial transmission cannot be continued, either.
Framing error
[Clearing conditions]
When 0 is written in FER after reading FER = 1
*1
[Setting conditions]
When the SCI checks the stop bit at the end of the receive data when reception
ends, and the stop bit is 0.
*2
0
1
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR1 is cleared to 0.
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked.
If a framing error occurs, the receive data is transferred to RDR1 but the RDRF flag is not set.
Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In synchronous
mode, serial transmission cannot be continued, either.
Initial value :
Note: * Only 0 can be written to clear the flag.
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
Bit
R/W
:
:
Rev. 1.0, 02/ 00, page 1065 of 1141
H'D14D: Receive Data Register RDR1: SCI1
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Bit :
Initial value :
R/W :
H'D14E: Serial Interface Mode Register SCMR1: SCI1
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
SDIR
0
R/W
0
—
0
—
2
SINV
0
R/W
1
—
1
—
Data inversion
TDR contents are transmitted (Initial value)
without modification.
Receive data is stored in RDR
without modification.
TDR contents are inverted before
being transmitted.
Receive data is stored in RDR1
in inverted form.
0
1
TDR contents are transmitted LSB-first. (Initial value)
Receive data is stored in RDR LSB-first.
TDR contents are transmitted MSB-first.
Receive data is stored in RDR MSB-first.
0
1
Data transfer direction
Initial value :
Bit
R/W
:
:
Rev. 1.0, 02/ 00, page 1066 of 1141
H'D158: I2C Bus Control Regi st e r ICCR1: I 2C Bus Int e rface
7
ICE
0
R/W
6
IEIC
0
R/W
5
MST
0
R/W
4
TRS
0
R/W
3
ACKE
0
R/W
0
SCP
1
W
2
BBSY
0
R/W
1
IRIC
0
R/(W)*
Note: * Only 0 can be written to clear the flag.
I
2
C bus interface enable
0 I
2
C bus interface module disabled, with SCL and SDA signal pins (Initial value)
set to port function. SAR and SARX can be accessed.
1 I
2
C bus interface module enabled for transfer operation (pins SCL
and SCA are driving the bus). ICMR and ICDR can be accessed.
I
2
C bus interface interrupt enable
0 Interrupt request is disabled (Initial value)
1 Interrupt request is enabled
Acknowledge bit judgment selection
0 The value of the acknowledge bit is ignored, and continuous transfer is performed (Initial value)
1 If the acknowledge bit is 1, continuous transfer is interrupted
Bus busy
0 Bus is free (Initial value)
[Clearing conditions] When a stop condition is detected
1 Bus is busy
[Setting conditions] When a start condition is detected
I
2
C bus interface interrupt request flag
0 Waiting for transfer, or transfer in progress (Initial value)
[Clearing conditions]
(1) When 0 is written in IRIC after reading IRIC = 1
1 Interrupt requested
[Setting conditions]
• I
2
C bus format master mode
— When a start condition is detected in the bus line state after a start condition is
issued (when the TDRE flag is set to 1 because of first frame transmission)
— When a wait is inserted between the data and acknowledge bit when WAIT = 1
— At the end of data transfer
(when the TDRE or RDRF flag is set to 1)
— When a slave address is received after bus arbitration is lost
(when the AL flag is set to 1)
— When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
• I
2
C bus format slave mode
— When the slave address (SVA, SVAX) matches
(when the AAS and AASX flags are set to 1) and at the end of data transfer up
to the subsequent retransmission start condition or stop condition detection
(when the TDRE or RDRF flag is set to 1)
— When the general call address is detected
(when the ADZ flag is set to 1) and at the end of data transfer up to the
subsequent retransmission start condition or stop condition detection
(when the TDRE or RDRF flag is set to 1)
— When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
— When a stop condition is detected
(when the STOP or ESTP flag is set to 1)
• Synchronous serial format
— At the end of data transfer (when the TDRE or RDRF flag is set to 1)
— When a start condition is detected with serial format selected
— When a condition, other than the above, that sets the TDRE or RDRF flag to 1 is
detected
Start condition/stop condition prohibit
0 Writing 0 issues a start or stop condition, in combination with the BBSY flag
1 Reading always returns a value of 1 (Initial value)
Writing is ignored
Master/slave select
Transmit/receive select
MST TRS Description
0 0 Slave reveive mode (Initial value)
1 Slave transmit mode
1 0 Master receive mode
1 Master transmit mode
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1067 of 1141
H'D159: I2C Bus Stat us Re g i st e r ICSR1: I2C Bus Int e rfa c e
7
ESTP
0
R/(W)*
6
STOP
0
R/(W)*
5
IRTR
0
R/(W)*
4
AASX
0
R/(W)*
3
AL
0
R/(W)*
0
ACKB
0
R/W
2
AAS
0
R/(W)*
1
ADZ
0
R/(W)*
Note: * Only 0 can be written to clear the flag.
Error stop condition detection flag
0 No error stop condition (Initial value)
[Clearing conditions]
(1) When 0 is written in ESTP after reading ESTP = 1
(2) When the IRIC flag is cleared to 0
1 • In I
2
C bus format slave mode
Error stop condition detected
[Setting conditions]
–
When a stop condition is detected during frame transfer
• In other mode
No meaning
Normal stop condition detection flag
0 No normal stop condition (Initial value)
[Clearing conditions]
(1) When 0 is written in STOP after reading STOP = 1
(2) When the IRIC flag is cleared to 0
1 • In I
2
C bus format slave mode
Normal stop condition detected
[Setting conditions]
–
When a stop condition is detected after completion of frame transfer
• In other mode
No meaning
I
2
C bus interface continuous transmission/reception interrupt request flag
0 Waiting for transfer, or transfer in progress (Initial value)
[Clearing conditions]
(1) When 0 is written in IRTR after reading IRTR = 1
(2) When the IRIC flag is cleared to 0
1 Continuous transfer state
[Setting conditions]
• In I
2
C bus interface slave mode
–
When the TDRE or RDRF flag is set to 1 when AASX = 1
• In other mode
–
When the TDRE or RDRF flag is set to 1
Second slave address recognition flag
0 Second slave address not recognized (Initial value)
[Clearing conditions]
(1) When 0 is written in AASX after reading AASX = 1
(2) When a start condition is detected
(3) In master mode
1 Second slave address recognized
[Setting conditions]
When the second slave address is detected in slave receive mode
Arbitration lost flag
0 Bus arbitration won (Initial value)
[Clearing conditions]
(1) When ICDR data is written (transmit mode) or read (receive mode)
(2) When 0 is written in AL after reading AL = 1
1 Arbitration lost
[Setting conditions]
(1) If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode
(2) If the internal SCL line is high at the fall of SCL in master transmit mode
Slave address recognition flag
0 Slave address or general call address not recognized (Initial value)
[Clearing conditions]
(1) When ICDR data is written (transmit mode) or read (receive mode)
(2) When 0 is written in AAS after reading AAS = 1
(3) In master mode
1 Slave address or general call address recognized
[Setting conditions]
When the slave address or general call address is detected when FS = 0 in slave receive mode
General call address recognition flag
0 General call address not recognized (Initial value)
[Clearing conditions]
(1) When ICDR data is written (transmit mode) or read (receive mode)
(2) When 0 is written in ADZ after reading ADZ = 1
(3) In master mode
1 General call address recognized
[Setting conditions]
When the general call address is detected when FSX = 0 or FS = 0 in slave receive mode
Acknowledge bit
0 Receive mode: 0 is output at acknowledge output timing (Initial value)
Transmit mode: Indicates that the receiving device has acknowldeged the data (signal is 0)
1 Receive mode; 1 is output at acknowledge output timing
Transmit mode: Indicates that the receiving device has not acknowldeged the data (signal is 1)
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1068 of 1141
H'D15E: I2C Bus Data Registe r ICDR1: I2C Bus Int e rface
7
ICDR7
—
R/W
6
ICDR6
—
R/W
5
ICDR5
—
R/W
4
ICDR4
—
R/W
3
ICDR3
—
R/W
0
ICDR0
—
R/W
2
ICDR2
—
R/W
1
ICDR1
—
R/W
:
:
:
Bit
Note: Refer to section 23.2.1, I
2
C Bus Data Register (ICDR).
Initial value
R/W
H' D15E: Second Sl ave Addr e ss Re gi ste r SARX1: I2C B us Int e r f a c e
7
SVAX6
0
R/W
6
SVAX5
0
R/W
5
SVAX4
0
R/W
4
SVAX3
0
R/W
3
SVAX2
0
R/W
0
FSX
1
R/W
2
SVAX1
0
R/W
1
SVAX0
0
R/W
:
:
:
Bit
Note: Refer to section 23.2.3, Second Slave Address Register (SARX),
and section 23.2.2, Slave Address Register (SAR)
Initial value
R/W
Format select
Used combined with FS bit in SAR.
Rev. 1.0, 02/ 00, page 1069 of 1141
H'D15F: I2C Bus M o de Re g i st e r ICM R1: I2C B us Inter fa c e
7
MLS
0
R/W
6
WAIT
0
R/W
5
CKS2
0
R/W
4
CKS1
0
R/W
3
CKS0
0
R/W
0
BC0
0
R/W
2
BC2
0
R/W
1
BC1
0
R/W
MSB-first/LSB-first select
0 MSB-first (initial value)
1 LSB-first
Wait insertion bit
0 Data and acknowledge bits transferred consecutively (initial value)
1 Wait inserted between data and acknowledge bits
Transfer clock select bits
Bit counter
Bit/frame
BC2 BC1 BC0 Clock sync I
2
C bus format
serial format
0 0 0 8 9 (Initial value)
1 1 2
1 0 2 3
1 3 4
0 0 0 4 5
1 5 6
1 0 6 7
1 7 8
Bit :
Initial value :
R/W :
Note: * See bit 6 in STCR.
IICX* CKS2 CKS1 CKS0 Clock Transfer rate
φ=8 MHz φ=10 MHz
0 0 0 0 φ/28 286 kHz 357 kHz
1 φ/40 200 kHz 250 kHz
1 0 φ/48 167 kHz 208 kHz
1 φ/64 125 kHz 156 kHz
1 0 0 φ/80 100 kHz 125 kHz
1 φ/100 80.0 kHz 100 kHz
1 0 φ/112 71.4 kHz 89.3 kHz
1 φ/128 62.5 kHz 78.1 kHz
1 0 0 0 φ/56 143 kHz 179 kHz
1 φ/80 100 kHz 125 kHz
1 0 φ/96 83.3 kHz 104 kHz
1 φ/128 62.5 kHz 78.1 kHz
1 0 0 φ/160 50.0 kHz 62.5 kHz
1 φ/200 40.0 kHz 50.0 kHz
1 0 φ/224 35.7 kHz 44.6 kHz
1 φ/256 31.3 kHz 39.1 kHz
Rev. 1.0, 02/ 00, page 1070 of 1141
H' D1 5F: Sl a v e Addr ess Re giste r SAR1 : I2C B us Interf a c e
7
SVA6
0
R/W
6
SVA5
0
R/W
5
SVA4
0
R/W
4
SVA3
0
R/W
3
SVA2
0
R/W
0
FS
0
R/W
2
SVA1
0
R/W
1
SVA0
0
R/W
Format select bit
DDCSWR SAR SARX Format select
Bit 6 Bit 0 Bit 0
SW FS FX
000I
2
C bus format
•SAR and SARX slave addresses recognized
1I
2
C bus format (Initial value)
•SAR slave address recognized
•SARX slave address ignored
10I
2
C bus format
•SAR slave address ignored
•SARX slave address recognized
1I
2
C bus format
•SAR and SARX slave addresses ignored
1 0 0 Formatless transfer (start and stop conditions
are not detected)
1•With acknowledge bit
1 0 Formatless transfer* (start and stop conditions
are not detected)
1•Without acknowledge bit
Bit
Initial value
R/W
:
:
:
Note: Do not use this setting when automatically switching the made from
formatless transfer to I
2
C bus format by setting DDCSWR.
Rev. 1.0, 02/ 00, page 1071 of 1141
H'D200 to H'D20B: Row Registers 1 to 12 CLINE1 to CLINE12: OSD
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
57 CLUn2 KRn KGn
KBn
KLUn
0
R/W
BPTNn 6
0
R/W
SZn
R/WR/W
CLUn1
Bit
Initial value
R/W
Character size specification bit
0 Character display size: single height × single width (Initial value)
1 Character display size: double height × double width
Button pattern specification bit
0 Pattern causing buttons in the nth row to appear to be raised (Initial value)
1 Pattern causing buttons in the nth row to appear to be lowered
Cursor brightness/halftone level specification bit
(Cursor Colors in Text Display Mode)
(Cursor Brightness in Text Display Mode)
(Cursor Colors in Superimposed Mode)
Character brightness specification bits
Bit 0 Cursor Color Cursor Brightness Level
KLUn
0 Black
1
0 Blue, green, cyan,
1 red, yellow, magenta
0 White
1
Bit 5 Bit 4 Character Color Character Brightness Level
CLUn1 CLUn0
0 0 Black
1
1 0
1
0 0 Blue, green,
1 cyan, red,
1 0 yellow,
1 magenta
0 0 White
1
1 0
1
Bit 0 Character Brightness Level
KLUn
0
1
:
:
:
Note: All brightness levels are with reference to the pedestal level (5 IRE).
Brightness levels are reference values.
Note: All brightness levels are with reference to the pedestal level (5 IRE).
Brightness levels are reference values.
(Halftone Levels in Superimposed Mode)
Cursor color specification bits
Bit 3 Bit 2 Bit 1 Character Brightness Level
KRn KGn KBn Cursor Color (C.Video Output) Cursor Color (R, G, B Output)
000
1
1 0 Specification invalid
1 (Halftone display in
1 0 0 superimposed mode)
1
10
1
(n = 1 to 12)
(n = 1 to 12)
Bit 3 Bit 2 Bit 1 Character Brightness Level
KRn KGn KBn Cursor Color (C.Video Output) Cursor Color (R, G, B Output)
NTSC PAL
0 0 0 Black Black Black (Initial value)
1
π
±
π
Blue
1 0 7
π
/4 ±7
π
/4
1 3
π
/2 ±3
π
/2
1 0 0
π
/2 ±
π
/2
0 3
π
/4 ±3
π
/4
1 0 Same phase ±0
0 IRE (Initial value)
10 IRE
20 IRE
30 IRE
25 IRE (Initial value)
45 IRE
55 IRE
65 IRE
45 IRE (Initial value)
70 IRE
80 IRE
90 IRE
Green
Cyan
Red
Magenta
Yellow
White
Black (Initial value)
Blue
Green
Cyan
Red
Magenta
Yellow
White
0 IRE (Initial value)
25 IRE
25 IRE (Initial value)
45 IRE
45 IRE (Initial value)
55 IRE
50% halftone (Initial value)
30% halftone
1 White White
Rev. 1.0, 02/ 00, page 1072 of 1141
H'D20C: Vertical Display Position Register VPOS: OSD
8
0
9
0
R/W
10
0
R/W
11
0
12
1
—
1
—
1315 — VSPC2 VSPC1
VSPC0
VP8
1
—
—14
1
—
—
R/WR/W
—
Bit
Initial value
R/W
Vertical row interval specification bits
Vertical display start position specification bits
VSPC2 VSPC1 VSPC0 Description
0 0 0 No row interval
1 Row interval: One scanning line
1 0 Row interval: Two scanning lines
1 Row interval: Three scanning lines
1 0 0 Row interval: Four scanning lines
1 Row interval: Five scanning lines
1 0 Row interval: Six scanning lines
1 Row interval: Seven scanning lines
:
:
:
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
57 VP4 VP3 VP2 VP1 VP0
0
R/W
VP7 6
0
R/W
VP6
R/WR/W
VP5
Bit
Initial value
R/W
:
:
:
H'D20E: Horizontal Display Position Register HPOS: OSD
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
57 HP4 HP3 HP2 HP1 HP0
0
R/W
HP7 6
0
R/W
HP6
R/WR/W
HP5
Bit
Initial value
R/W
:
:
:
Horizontal display start position specification bits
Rev. 1.0, 02/ 00, page 1073 of 1141
H'D20F: Digital Output Specification Register DOUT: OSD
0
0
1
1
—
2
0
R/W
3
0
4
0
R/W
0
R/W
57 DOBC DSEL CRSEL — —
0
—
—6
0
R/W
RGBC
—R/W
YCOC
R, G, B digital output specification bit
0
1
YCO digital output specification bit
0
1
Monitor signal switching bit
0
1
Digital output blink control bit
RAM DOUT Description
Bit 15 Bit 4
@
BLNK
@@
DOBC
0 0 Does not blink (Initial value)
1 Does not blink
1 0 Does not blink
1 Blinks
:
:
:
R, G, B, YCO, YBO pin function select bit
0 R, G, B, YCO, YBO output function is selected (Initial value)
1 Data slicer monitor output function is selected
Bit
Initial value
R/W
Character output is specified (Initial value)
Combined character, border, cursor, background, and button output is specified
Character output is specified (Initial value)
Combined character and border output is specified
R pin = Signal selected by bit 2 (CRSEL)
G pin = Slice data signal analog-compared with Cvin2
B pin = Sampling clock generated within data slicer
YCO pin = External Hsync signal (AFCH) synchronized within the LSI
YBO pin = External Vsync signal (AFCV) synchronized within the LSI
Clock run-in detection window signal output is selected (Initial value)
Start bit detection window signal output is selected
Rev. 1.0, 02/ 00, page 1074 of 1141
H'D210: Screen Control Re gister DCNTL: OSD
8
0
9
0
R/W
10
0
—
11
0
12
0
R/W
0
R/W
131415 BLKS OSDON —
EDGE
EDGC
0
R/W R/W
CDSPON DISPM
R/WR/W
LACEM
0
OSD display start bit
CDSPON OSDON Description
0/1 0
01
11
OSD C. video display enable bit
0 OSD C.Video display is off (Initial value)
1 OSD C.Video display is on
Border specification bit
0 No character border (Initial value)
1 Character border
Superimposed/text display mode select bit
0 Superimposed mode is selected (Initial value)
1 Text display mode is selected
Blinking period select bit
TVM2 BLKS Description
00
1
10
1
Interlaced/noninterlaced display select bit
0 0 Noninterlaced display is selected (Initial value)
1 Interlaced display is selected
Border color specification bit
Bit 8 Border Color (in text display mode)
EDGC Border Color (C.Video output) Border Color (R,G,B Output)
0 Black Black (Initial value)
1 White White
Bit 8 Border Color (in superimposed mode)
EDGC C.Video output R,G,B Output
0 Specification invalid (Black) Black (Initial value)
1 White
:
:
:
(TVM2 is bit15 in DFORM)
Approx. 0.5 sec (32/fv = 0.53 sec) (Initial value)
Approx. 1.0 sec (64/fv = 1.07 sec)
Approx. 0.5 sec (32/fv = 0.64 sec)
Approx. 1.0 sec (64/fv = 1.28 sec)
OSD display is stopped (C.Video output and digital output both off) (Initial value)
OSD display is started (digital output only)
OSD display is started (both C.Video output and digital output enabled)
Bit
Initial value
R/W
Rev. 1.0, 02/ 00, page 1075 of 1141
H'D211: Screen Control Re gister DCNTL: OSD
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
57 BLU1 BLU0 CAMP KAMP BAMP
0
R/W
BR 6
0
R/W
BG
R/WR/W
BB
Background chroma select bit
0
1
Cursor chroma select bit
0
1
Character chroma select bit
0 Character chroma amplitude: 60 IRE (Initial value)
1 Character chroma amplitude: 80 IRE
Background brightness select bits
BUL1 BUL0 Description
0 0 Background Brightness, 10IRE (Initial value)
1 Background Brightness, 30IRE
1 0 Background Brightness, 50IRE
1 Background Brightness, 70IRE
:
:
:
Background color specification
(Background Colors in Text Display Mode)
(Background Colors in Superimposed Mode)
Bit 7 Bit 6 Bit 5 Description
BR BG BB Background color (C.Video Output) Background color (R, G, B Outputs)
000
1
10
1 Specification
1 0 0 invalid
1
10
1
Bit 7 Bit 6 Bit5 Description
BR BG BB Background color (C.Video Output) Background color (R, G, B Outputs)
NTSC PAL
0 0 0 Black Black
1 π ±π
1 0 7π/4 ±7π/4
1 3π/2 ±3π/2
1 0 0 π/2 ±π/2
1 3π/4 ±3π/4
1 0 Same phase ±0
1 White White
Black (Initial value)
Blue
Green
Cyan
Red
Magenta
Yellow
White
Black (Initial value)
Blue
Green
Cyan
Red
Magenta
Yellow
White
Cursor chroma amplitude: 60 IRE (Initial value)
Cursor chroma amplitude: 80 IRE
Background chroma amplitude: 60 IRE (Initial value)
Background chroma amplitude: 80 IRE
Bit
Initial value
R/W
Rev. 1.0, 02/ 00, page 1076 of 1141
H'D212: OSD Format Register DFO RM: OSD
8
0
9
0
R/W
10
0
—
11
0
12
0
R/W
0
R/W
1315 FSCIN FSCEXT —
OSDVE
OSDVF
0
R/W
TVM2 14
0
R/W
TVM1
R/(W)*
1
R/W
TVM0
Notes: 1. Only 0 can be written to clear the flag.
2. The 4fsc and 2fsc frequencies for SECAM do not conform to the SECAM TV format
specifications.
Bit 15 Bit 14 Bit 13 Bit 12 Description
TVM2 TVM1 TVM0 FSCIN TV Format 4fsc (MHz) 2fsc (MHz)
0000M/NTSC 14.31818 —
1 — — 7.15909
017.734475
0 0 1 4.43-NTSC (17.734470)
1 — 8.867235
(8.867238)
0100M/PAL 14.302446 —
(14.302444)
1 — 7.15122298
0 1 1 0/1 Must not be specified
1000N/PAL 14.328225
(14.28244) —
1 — 7.1641125
1 0 1 0/1 Must not be specified
0 B,G,H/PAL 17.734475 —
1 1 0 I/PAL (17.734476)
1 D,K/PAL — 8.867235
(8.867238)
0 B,G,H/SECAM*
2
17.734475 —
1 1 1 L/SECAM (17.734470)
1 D,K,K1/SECAM — 8.867235
(8.867238)
OSDV interrupt enable bit
0
1
4/2fsc external input select bit
0
1
4/2fsc input select bit
TV format select bits
0
1
OSDV interrupt flag
:
:
:
0
1
Bit
Initial value
R/W
—
4fsc input is selected (Initial value)
2fsc input is selected
4/2fsc oscillator uses a crystal oscillator (Initial value)
4/2fsc uses a dedicated amplifier circuit for external clock signal input
The OSDV interrupt is disabled (Initial value)
The OSDV interrupt is enabled
[Clearing condition]
When 0 is written after reading 1 (Initial value)
[Setting condition]
When OSD detects the Vsync signal
Rev. 1.0, 02/ 00, page 1077 of 1141
H'D213: OSD Format Register DFO RM: OSD
0
0
1
0
R/W
2
0
R/W
3
1
4
1
—
1
—
57 — — DTMV LDREQ VACS
1
—
—6
1
—
—
R/(W)*—
—
Writing:
0
1
Reading:
0
1
OSD display update timing control bit
0
1
:
:
:
Master slave RAM transfer state bit
Master slave RAM transfer state bit
0
1
After the LDREQ bit is written to 1, data is transferred from master RAM to slave RAM
regardless of the Vsync signal (OSDV). The OSD display is updated simultaneously
with register* rewriting.
Note: * When transferring data using this setting, do not have the OSD display data
(Initial value)
After the LDREQ bit is written to 1, data is transferred from master RAM to slave RAM
synchronously with the Vsync signal (OSDV). After rewriting the register, the OSD
display is updated synchronously with the Vsync signal (OSDV).
Note: * The registers and register bits whose settings are reflected in the OSD display are the
row registers (CLINE), vertical display position register (VPOS), horizontal display
position register (HPOS), screen control register (DCNTL) except bit 13, and the RGBC,
YCOC, and DOBC bits of the digital output specification register (DOUT).
Data is not being transferred from master RAM to slave RAM (Initial value)
Data is being transferred from master RAM to slave RAM, or is being
prepared for transfer. After transfer is completed, this bit is cleared to 0
Requests abort of data transfer from master RAM to slave RAM
Requests transfer of data from master RAM to slave RAM.
After transfer is completed, this bit is cleared to 0
The CPU did not access OSDRAM during data transfer (Initial value)
The CPU accessed OSDRAM during data transfer; the access is invalid
Bit
Initial value
R/W
Rev. 1.0, 02/ 00, page 1078 of 1141
H'D800 to H ' DAF F : Di spl ay Data RAM O SDRAM : O SD
8
*
9
*
R/W
10
*
R/W
11
*
12
*
R/W
*
R/W
1315 BON0 CR CG
CB
C8
*
R/W
BLNK 14
*
R/W
HT/CR
R/WR/W
BON1
Halftone/cursor display specification bit
DISPM HT/CR
00
1
10
1
Button specification bits
BPTNn BON1 BON0 Description
000
1
10
1
100
1
10
1
:
:
:
Character color specification bits
Character codes specification
CR CG CB Character Color (C.Video Output) Character Color (R, G, B Output)
NTSC PAL
0 0 0 Black Black Black
1π π Blue
107π/4 7π/4 Green
13π/2 3π/2 Cyan
100π/2 π/2 Red
13π/4 3π/4 Magenta
1 0 Same phase 0 Yellow
1 White White White
RGBC HT/CR
0 0/1
10
1
Blinking specification bit
0
1
DOBC BLNK
00
1
10
1(DOBC is bit 4 in DOUT)
(RGBC is bit 6 in DOUT)
(DISPM is bit 14 in DCNTL)
Bit
Initial value
R/W
0
*
1
*
R/W
2
*
R/W
3
*
4
*
R/W
*
R/W
57 C4 C3 C2
C1
C0
*
R/W
C7 6
*
R/W
C6
R/WR/W
C5
:
:
:
Character Codes
Bit
Initial value
R/W
Blinking is off
Blinking is on
Digital Output (YCO, R, G, B)
Blinking is off
Blinking is off
Blinking is off
Blinking is on
C.Video Output
Halftone is off
Halftone is on
Cursor display is off
Cursor display is on
Digital Output (R, G, B)
Character is output (halftone/cursor specification invalid)
Character is output (halftone/cursor display off)
Cursor color data specified by the cursor color specification bit of row register is output
No button is displayed
Button is displayed (start)
Button is displayed (end)
Button is displayed (one character)
No button is displayed
Button is displayed (start)
Button is displayed (end)
Button is displayed (one character)
Rev. 1.0, 02/ 00, page 1079 of 1141
H'D220: Slice Even-Field Mode Register SEVFD: Data Slicer
8
0
9
0
R/W
10
0
R/W
11
0
12
0
R/W
1
—
1315 STBE4 STBE3 STBE2 STBE1 STBE0
0
R/W
EVNIE 14
0
R/(W)*
EVNIF
R/WR/W
—
Even field slice completion interrupt enable flag
0
1
Even field slice interrupt completion flag
0
1
:
:
:
Start bit detection starting position bits
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
57 DLYE4 DLYE3 DLYE2 DLYE1 DLYE0
0
R/W
SLVLE2 6
0
R/W
SLVLE1
R/WR/W
SLVLE0
Slice Level Setting Bits
SLVLE2 SLVLE1 SLVLE0 Description
000
1
10
1
100
1
10
1
:
:
:
Even field data sampling clock delay time
Slice level is 0 IRE (Initial value)
Slice level is 5 IRE
Slice level is 15 IRE
Slice level is 20 IRE
Slice level is 25 IRE
Slice level is 35 IRE
Slice level is 40 IRE
Must not be specified
Note: All slice levels are with reference to the pedestal level (5 IRE).
Slice level values are provided for reference.
Note: * Only 0 can be written to clear the flag.
Bit
Initial value
R/W
Bit
Initial value
R/W
Disables even-field slice completion interrupt (Initial value)
Enables even-field slice completion interrupt
[Clearing condition]
When 0 is written after reading 1 (Initial value)
[Setting condition]
When data slicing is completed for all specified lines of even field
Rev. 1.0, 02/ 00, page 1080 of 1141
H'D222: Slice Odd-Field Mode Register SODFD: Data Slicer
8
0
9
0
R/W
10
0
R/W
11
0
12
0
R/W
1
—
1315 STBO4 STBO3 STBO2 STBO1 STBO0
0
R/W
ODDIE 14
0
R/(W)*
ODDIF
R/WR/W
—
0
1
0
1
:
:
:
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
57 DLYO3 DLYO3 DLYO2 DLYO1 DLYO0
0
R/W
SLVLO2 6
0
R/W
SLVLO1
R/WR/W
SLVLO0
:
:
:
ODD field data sampling clock delay time
Start bit detection starting position bits
Slice level setting bits
SLVLO2 SLVLO1 SLVLO0 Description
000
1
10
1
100
1
10
1
Note: *Only 0 can be written to clear the flag.
Note: All slice levels are with reference to the pedestal level (5 IRE).
Slice level values are provided for reference.
Bit
Initial value
R/W
Slice level is 0 IRE (Initial value)
Slice level is 5 IRE
Slice level is 15 IRE
Slice level is 20 IRE
Slice level is 25 IRE
Slice level is 35 IRE
Slice level is 40 IRE
Must not be specified
Odd field slice completion interrupt enable flag
Odd field slice interrupt completion flag
Disables odd field slice completion interrupt (Initial value)
Enables even-odd field slice completion interrupt
[Clearing condition]
When 0 is written after reading 1 (Initial value)
[Setting condition]
When data slicing is completed for all specified lines of odd field
Bit
Initial value
R/W
Rev. 1.0, 02/ 00, page 1081 of 1141
H'D224 to H'D227: Slice Line Setting Registers 1 to 4 SLINE1 to SLINE4: Data Slicer
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
1
—
57 SLINEn4 SLINEn3 SLINEn2 SLINEn1 SLINEn0
0
R/W
SENBLn 6
0
R/W
SFLDn
R/WR/W
—
Field setting bit
0
1
Slice enable bit
0
1
:
:
:
Slice line setting bit
(n = 1 to 4)
Bit
Initial value
R/W
[When read] Disables data slice operation for the specified lines
[Clearing condition]
When the data slice operation for the line has been completed
Enables data slice operation for the specified lines
Even field (Initial value)
Odd field
Rev. 1.0, 02/ 00, page 1082 of 1141
H'D228 to H'D22B: Slice Detection Registers 1 to 4 SDTCT1 to SDTCT4: Data Slicer
0
0
1
0
R
2
0
R
3
0
4
1
—
0
R
57
—CRICn3 CRICn2 CRICn1 CRICn0
0
R
CRDFn 6
0
R
SBDFn
RR
ENDFn
Data end detection flag
0
1
Start bit detection flag
0
1
Clock run-in detection flag
0
1
:
:
:
Clock run-in count value
(n = 1 to 4)
Bit
Initial value
R/W
Clock run-in not detected for line for data slicing (Initial value)
Clock run-in detected for line for data slicing
Start bit not detected for line for data slicing (Initial value)
Start bit detected for line for data slicing
Data end not detected for line for data slicing (Initial value)
Data end detected for line for data slicing
H'D22C to H'D232: Slice Data Registers 1 to 4 SDATA1 to SDATA4: Data Slicer
15
*
Note: *Undetermined
R
14
*
R
13
*
R
12
*
R
11
*
R
10
*
R
9
*
R
8
*
R
7
*
R
6
*
R
5
*
R
4
*
R
3
*
R
2
*
R
1
*
R
0
*
R
:
:
:
Bit
Initial value
R/W
Rev. 1.0, 02/ 00, page 1083 of 1141
H'D240: Sync Se par ati on Input M ode Re gi ste r SEP IM R: Sync Se par ator
0
0
1
0
R/W
2
0
R/W
3
0
456
0
7
R/WR/W
VSELCCMPV1
R/WR/W
CCMPV0
R/W
CCMPSL
R/W
SYNCT DLPFON
—
FRQSEL
000
Digital LPF control
0
1
Reference clock frequency select
0
1
Vsync input signal select
0
1
Csync separation comparator input select
0
1
0 (Initial value)
1
Sync signal polarity select
:
:
:
Csync separation comparator slicing voltage select
Description
0
0
CCMPV1 CCMPV0
1
0
1
1
Bit
Initial value
R/W
The Csync slicing level is 10 IRE (Initial value)
The Csync slicing level is 5 IRE
The Csync slicing level is 15 IRE
The Csync slicing level is 20 IRE
The Csync separation comparator input is selected
The Csync/Hsync terminal operates as an output terminal (Initial value)
The Csync Schmitt input is selected
The Csync/Hsync terminal operates as an input terminal
Vsync Schmitt input (Initial value)
Csync Schmitt input
The digital LPF does not operate (Initial value)
The digital LPF operates
576 times the horizontal sync frequency (Initial value)
448 times the horizontal sync frequency
Rev. 1.0, 02/ 00, page 1084 of 1141
H'D241: Sync Separation Control Register SEPCR: Sync Separator
0
0
1
0
R/W
2
0
R/W
3
0
456
0
7
RR/W
HCKSEL
R/W
AFCVIE
R/(W)*
AFCVIF
R/W
VCKSL
R/W
VCMPON HHKON
—
FLD
000
HHK forcibly turned on
0
1
Field detection flag
0
1
Internal csync generator clock source select
0
1
V complement function control
0
1
V complement and mask counter clock source select
0
1
:
:
:
External Vsync interrupt flag
0
1
External Vsync interrupt enable
0
1
Bit
Initial value
R/W
Note: *Only 0 can be written to clear the flag
The external Vsync interrupt is disabled (Initial value)
The external Vsync interrupt is enabled
[Clearing condition]
1 is read, then 0 is written (Initial value)
[Setting condition]
The V complement and mask counter detects the external Vsync signal (AFCV signal)
Double the frequency of the horizontal sync signal (AFCH signal) for the AFC (Initial value)
Double the frequency of the horizontal sync signal (OSCH signal) for the
H complement and mask counter
The V complement function is disabled (Initial value)
The V complement function is enabled
4/2 fsc clock (Initial value)
AFC reference clock
The HHK is not operated when complementary
pulses are interpolated three successive times
(Initial value)
The HHK is forcibly operated when complementary
pulses are interpolated three successive times
Even field (Initial value)
Odd field
Rev. 1.0, 02/ 00, page 1085 of 1141
H'D242: Sync Se par ati on AF C Contr ol Re gi ste r SEP ACR: Sync Se par ator
0
0
1
0
—
2
0
R/W
3
0
456
0
7
——
—
R/W
NDETIE
R/(W)*
NDETIF
R/W
HSEL
—
— ARST — —
010
AFC reset control
0
1
Reference Hsync signal select
0
1
:
:
:
Noise detection interrupt flag
0
1
Noise detection interrupt enable
0
1
Bit
Initial value
R/W
Note: *Only 0 can be written to clear the flag
The noise detection interrupt is disabled (Initial value)
The noise detection interrupt is enabled
[Clearing condition]
1 is read, then 0 is written (Initial value)
[Setting condition]
The noise detection counter value matches the noise detection level register value
The external Hsync signal is selected (Initial value)
The internally generated Hsync signal is selected
The reset function is disabled (Initial value)
The reset function is enabled
H'D243: Horizontal Sync Signal Threshold Register HVTHR: Sync Separator
012
HVTH2
3
HVTH3
0
4
HVTH4
WWWW
5
—
—
6
—
—
7
—
—
HVTH1
0
W
HVTH0
111000
Horizontal sync signal threshold
:
:
:
Bit
Initial value
R/W
Note: Refer to section 27.2.4, Horizontal Sync Signal Threshold Register (HVTHR)
Rev. 1.0, 02/ 00, page 1086 of 1141
H'D244: Vertic al Sync Signal Threshold Register VVTHR: Sync Separator
012
VVTH2
3
VVTH3
0
4
VVTH4
WWWWWWW
5
VVTH5
6
VVTH6
7
VVTH7 VVTH1
0
W
VVTH0
000000
:
:
:
Vertical sync signal threshold
Note: Refer to section 27.2.5, Vertical Sync Signal Threshold Register (VVTHR)
Bit
Initial value
R/W
H'D245: Field Detection Window Register FWIDR: Sync Separator
012
FWID2
3
FWID3
0
4
—
—WWW
5
—
—
6
—
—
7
—
—
FWID1
0
W
FWID0
111100
:
:
:
Field detection window timing
Note: Refer to section 27.2.6, Field Detection Window Register (FWIDR)
Bit
Initial value
R/W
H'D246: H Complement and Mask Timing Register HCMM R: Sync Separator
1 032547
0
W
6
0
W
9
0
W
8
0
W
11
0
W
10
0
W
0
W
0
W
0
W
HC8 HC7 HC6 HC5 HC4 HC3 HC2 HC1 HC0 HM6
W
HM5
W
HM4
W
HM3
W
HM2
W
HM1
W
HM0
0
W
12131415
000000
:
:
:
HHK clearing timing
Complementary pulse
generation timing
Note: Refer to section 27.2.7, H Complement and Mask Timing Register (HCMMR)
Bit
Initial value
R/W
Rev. 1.0, 02/ 00, page 1087 of 1141
H'D248: Noise Detecti on Counter NDETC: Sync Separator
012
NC2
3
NC3
0
4
NC4
RRRRRRR
5
NC5
6
NC6
7
NC7 NC1
0
R
NC0
000000
:
:
:
Note: Refer to section 27.2.8, Noise Detection Counter (NDETC)
Bit
Initial value
R/W
H'D248: Noise Detecti on Leve l Regi ster NDETR: Sync Separator
012
NR2
3
NR3
0
4
NR4
WWWWWWW
5
NR5
6
NR6
7
NR7 NR1
0
W
NR0
000000
Noise detection level
:
:
:
Note: Refer to section 27.2.9, Noise Detection Level Register (NDETR)
Bit
Initial value
R/W
Rev. 1.0, 02/ 00, page 1088 of 1141
H'D249: Data Slicer Detection Window Register DDETWR: Sync Separator
0
0
1
0
W
2
0
W
3
0
456
0
7
WW
CRWDE1
W
SRWDE1
W
SRWDE0
W
SRWDS1
W
SRWDS0 CRWDE0 CRWDS1 CRWDS0
000
:
:
:
Start bit detection window signal falling timing setting
Start bit detection window signal rising timing setting
Clock run-in detection window signal falling timing setting
Clock run-in detection window signal rising timing setting
Description
0
0
SRWDE1 SRWDE0
1
0
11
Description
0
0
SRWDS1 SRWDS0
1
0
11
Description
0
0
CRWDE1 CRWDE0
1
0
11
Description
0
0
CRWDS1 CRWDS0
1
0
11
Bit
Initial value
R/W
The detection ends about 29.5 µs after the slicer start point (Initial value)
The detection ends about 29.0 µs after the slicer start point
The detection ends about 30.0 µs after the slicer start point
This setting must not be used
The detection ends about 23.5 µs after the slicer start point (Initial value)
The detection ends about 23.0 µs after the slicer start point
The detection ends about 24.0 µs after the slicer start point
This setting must not be used
The detection starts about 23.5 µs after the slicer start point (Initial value)
The detection starts about 23.0 µs after the slicer start point
The detection starts about 24.0 µs after the slicer start point
This setting must not be used
The detection starts about 10.5 µs after the slicer start point (Initial value)
The detection starts about 10.0 µs after the slicer start point
The detection starts about 11.0 µs after the slicer start point
This setting must not be used
Rev. 1.0, 02/ 00, page 1089 of 1141
H'D24A: Internal Sync Frequency Register INFRQR: Sync Separator
0
0
1
0
—
2
0
—
3
0
456
0
7
——
—
W
VFS2
W
VFS1
W
HFS
—
— ———
000
:
:
:
Hsync frequency selection bit Description
PAL
HFS
Bit 5
fsc/283.75 (Initial value)
fsc/283.5
MPAL
fsc/227.25 (Initial value)
fsc/227.5
NPAL
fsc/229.25 (Initial value)
fsc/229.5
0
1
Vsync frequency selection bit
VFS2
Bit 7
0
Description
PAL
VFS1
Bit 6
fh/313 (Initial value)
fh/314
MPAL
fh/263 (Initial value)
fh/266
NPAL
fh/313 (Initial value)
fh/314
0
1fh/310 fh/262 fh/310
10 fh/312 fh/264 fh/312
1
Bit
Initial value
R/W
Rev. 1.0, 02/ 00, page 1090 of 1141
H'FFB0 to H'FFB2: Trap Address Reg i st e r 0 T AR0: AT C
H'FFB3 to H'FFB5: Trap Address Reg i st e r 1 T AR1: AT C
H'FFB6 to H'FFB8: Trap Address Reg i st e r 2 T AR2: AT C
0
0
1
0
R/W
2
0
R/W
34567
R/W
A18 A17 A16
00
R/W
0
R/W R/W
A23 A22 A21
00
R/W R/W
A20 A19
0
0
1
0
R/W
2
0
R/W
34567
R/W
A10 A9 A8
00
R/W
0
R/W R/W
A15 A14 A13
00
R/W R/W
A12 A11
01
0
R/W
2
0
R/W
34567
A2 A1
00
R/W
0
R/W R/W
A7 A6 A5
00
R/W R/W
A4 A3
0
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
Bit :
Initial value :
R/W :
—
—
Rev. 1.0, 02/ 00, page 1091 of 1141
H'FFB9: Addre ss T r a p Co ntrol Regi st e r AT CR: ATC
0
0
1
0
R/W
2
0
R/W
3
1
4
1
5
1
6
1
7
R/W
TRC2 TRC1 TRC0
1
Trap control 0
0 Address trap function 0 is
disabled (Initial value)
1 Address trap function 0 is
enabled
Trap control 1
0 Address trap function 1 is
disabled (Initial value)
1 Address trap function 1 is
enabled
Trap control 2
0 Address trap function 2 is
disabled (Initial value)
1 Address trap function 2 is
enabled
Bit :
Initial value :
R/W :
—————
—————
Rev. 1.0, 02/ 00, page 1092 of 1141
H'FFBA: Timer Mode Register A TMA: Timer A
0
0
1
0
R/W
2
0
R/W
3
0
4
1
5
1
6
0
7
R/WR/WR/W
TMAIE
0
R/(W)*
TMAOV TMA3 TMA2 TMA1 TMA0
Note: * Only 0 can be written to clear the flag.
[Clearing conditions] (Initial value)
When 0 is written to TMAOV after reading
TMAOV = 1
[Setting conditions]
When TCA overflows
0
1
Timer A overflow flag
Interrupt request by Timer A (TMAI) is disabled (Initial value)
Interrupt request by Timer A (TMAI) is enabled
0
1
Timer A interrupt enable bit
Timer A clock source is PSS (Initial value)
Timer A clock source is PSW
0
1
Clock source, prescaler select bit
PSS, φ/16384 (Initial value)
TMA1 TMA0
TMA2
Prescaler frequency division rate (interval timer)
or overflow frequency (time-base) Operation mode
PSS, φ/8192
PSS, φ/4096
PSS, φ/1024
0
TMA3
PSS, φ/512
PSS, φ/256
PSS, φ/64
PSS, φ/16
1 s
Interval timer
mode
Clock time
base mode
0.5 s
0.25 s
0.03125 s
0
1
0
1
1
Clear PSW and TCA to H'00
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock select bits
Note: φ = f osc
Bit :
Initial value :
R/W :
——
——
Rev. 1.0, 02/ 00, page 1093 of 1141
H'FFBB: Timer Counter A TCA: TimerA
0
0
1
0
R
2
0
R
3
0
4567
RR
TCA3
0
R
TCA4
0
R
TCA5
0
R
TCA6
0
R
TCA7 TCA2 TCA1 TCA0
Bit :
Initial value :
R/W :
H'FFBC: Watchdog Timer Control/Status Register WTCSR: WDT
7
OVF
0
R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
4
—
0
—
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Note: * Only 0 can be written to clear the flag.
Overflow flag
WTCNT is initialized to H'00 and halted (Initial value)
WTCNT counts
0
1
NMI interrupt request is generated (Initial value)
Internal reset request is generated
0
1
Timer mode select bit
Timer enable bit
Reset or NMI
Interval timer mode: Sends the CPU an interval timer interrupt
request (WOVI) when WTCNT overflows (Initial value)
Watchdog timer mode: Sends the CPU a reset or NMI interrupt
request when WTCNT overflows
0
1
[Clearing conditions]
(1) Write 0 in the TME bit (Initial value)
(2) Read WTCSR when OVF = 1, then write 0 in OVF
[Setting conditions]
When WTCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset.)
0
1
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1094 of 1141
H'FFBD: Watchdog Timer Counter WTCNT: WDT
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit :
Initial value :
R/W :
H'FFC0: Port Data Register 0 PDR0: I/O Port
01
R
2
R
34
RR
57 PDR04 PDR03 PDR02 PDR01 PDR00
R
PDR07
RRR
PDR06 PDR05
6
Bit :
Initial value :
R/W : ————————
H'FFC1: Port Data Register 1 PDR1: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PDR14 PDR13 PDR12 PDR11 PDR10PDR17 PDR16 PDR15
Bit :
Initial value :
R/W :
H'FFC2: Port Data Register 2 PDR2: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PDR24 PDR23 PDR22 PDR21 PDR20PDR27 PDR26 PDR25
Bit :
Initial value :
R/W :
H'FFC3: Port Data Register 3 PDR3: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PDR34 PDR33 PDR32 PDR31 PDR30PDR37 PDR36 PDR35
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1095 of 1141
H'FFC4: Port Data Register 4 PDR4: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PDR44 PDR43 PDR42 PDR41 PDR40PDR47 PDR46 PDR45
Bit :
Initial value :
R/W :
H'FFC6: Port Data Register 6 PDR6: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PDR64 PDR63 PDR62 PDR61 PDR60
0
R/W
PDR67
R/WR/WR/W
PDR66 PDR65
Bit :
Initial value :
R/W :
H'FFC7: Port Data Register 7 PDR7: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PDR74 PDR73 PDR72 PDR71 PDR70
0
R/W
PDR77
R/WR/WR/W
PDR76 PDR75
Bit :
Initial value :
R/W :
H'FFC8: Port Data Register 8 PDR8: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PDR84 PDR83 PDR82 PDR81 PDR80
0
R/W
PDR87
R/WR/WR/W
PDR86 PDR85
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1096 of 1141
H'FFCD: Port Mode Register 0 PMR0: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PMR04 PMR03 PMR02 PMR01 PMR00PMR07 PMR06 PMR05
P07/AN7 to P00/IRQ0 rin function select bits
P0n/ANn pin functions as P0n input port (initial value)
P0n/ANn pin functions as ANn input port
0
1
(n = 7 to 0)
Bit :
Initial value :
R/W :
H'FFCE: Port Mode Register 1 PMR1: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PMR14 PMR13 PMR12 PMR11 PMR10PMR17 PMR16 PMR15
P17/TMOW pin functions as P17 I/O port (initial value)
P17/TMOW pin functions as TMOW output port
0
1
P17/TMOW pin function select bit
P1n/IRQn pin functions as P1n I/O port (Initial value)
P1n/IRQn pin functions as IRQn input port
0
1
P15/IRQ5 to P10/IRQ0 pin function select bits
(n = 5 to 0)
P16/IC pin functions as P16 I/O port (Initial value)
P16/IC pin functions as IC input port
0
1
P16/IC pin function select bit
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1097 of 1141
H'FFD0: Port Mode Register 3 PMR3: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PMR34 PMR33 PMR32 PMR31 PMR30PMR37 PMR36 PMR35
P3n/PWMm pin functions as P3n I/O port (Initial value)
P3n/PWMm pin functions as PWMm output port
0
1
P36/BUZZ pin functions as P36 I/O port (Initial value)
P36/BUZZ pin functions as BUZZ output port
0
1
P37/TMO pin functions as P37 I/O port (Initial value)
P37/TMO pin functions as TMO output port
0
1
P37/TMO pin function select bit
Notes: If the TMO pin is used for remote control sending, a careless timer output
pulse may be output when the remote control mode is set after the output
has been switched to the TMO output. Perform the switching and setting in
the following order.
[1] Set the remote control mode.
[2] Set the TMJ-1 and 2 counter data of the timer J.
[3] Switch the P37/TMO pin to the TMO output pin.
[4] Set the ST bit to 1.
P36/BUZZ pin function select bit
P35/PWM3 to P32/PWM0 pin function select bit
P31/SV2 pin functions as P31 I/O port (Initial value)
P31/SV2 pin functions as SV2 output port
0
1
P31/SV2 pin function select bit
(n = 5 to 2, m = 3 to 0)
P30/SV1 pin functions as P30 I/O port (Initial value)
P30/SV1 pin functions as SV1 output port
0
1
P30/SV1 pin function select bit
Bit :
Initial value :
R/W :
H'FFD1: Port Control Register 1 PCR1: I/O Port
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5
0
7
0
W WWW
6PCR14 PCR13 PCR12 PCR11 PCR10PCR17 PCR16 PCR15
P1n pin functions as input port (Initial value)
P1n pin functions as output port
0
1(n = 7 to 0)
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1098 of 1141
H'FFD2: Port Control Register 2 PCR2: I/O Port
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5
0
7
0
W WWW
6PCR24 PCR23 PCR22 PCR21 PCR20PCR27 PCR26 PCR25
P2n pin functions as input port (Initial value)
P2n pin functions as output port
0
1(n = 7 to 0)
Bit
Initial value
R/W
:
:
:
H'FFD3: Port Control Register 3 PCR3: I/O Port
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5
0
7
0
W WWW
6PCR34 PCR33 PCR32 PCR31 PCR30PCR37 PCR36 PCR35
P3n pin functions as input port (Initial value)
P3n pin functions as output port
0
1(n = 7 to 0)
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1099 of 1141
H'FFD4: Port Control Register 4 PCR4: I/O Port
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
5
0
7
0
W WWW
6PCR44 PCR43 PCR42 PCR41 PCR40PCR47 PCR46 PCR45
P4n pin functions as input port (Initial value)
P4n pin functions as output port
0
1(n = 7 to 0)
Bit
Initial value
R/W
:
:
:
H'FFD6: Port Control Register 6 PCR6: I/O Port
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PCR64 PCR63 PCR62 PCR61 PCR60
0
W
PCR67
WWW
PCR66 PCR65
00 P6n/RPn pin functions as P6n general purpose input port (Initial value)
PCR6nPMR6n
1 P6n/RPn pin functions as P6n general purpose output port
*1 P6n/RPn pin functions as RPn realtime output port
Description
Note: * Don't care. (n = 7 to 0)
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1100 of 1141
H'FFD7: Port Control Register 7 PCR7: I/O Port
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PCR74 PCR73 PCR72 PCR71 PCR70
0
W
PCR77
WWW
PCR76 PCR75
P7n pin functions as input port (Initial value)
P7n pin functions as output port
0
1(n = 7 to 0)
Bit
Initial value
R/W
:
:
:
H'FFD8: Port Control Register 8 PCR8: I/O Port
0
0
1
0
W
2
0
W
3
0
4
0
W
0
W
56
0
7PCR84 PCR83 PCR82 PCR81 PCR80
0
W
PCR87
WWW
PCR86 PCR85
P8n pin functions as input port (Initial value)
P8n pin functions as output port
0
1(n = 7 to 0)
Bit
Initial value
R/W
:
:
:
H'FFD9: Port Mode Register A PMRA: I/O Port
0
1
1
1
—
2
1
—
3
1
4
1
—
1
—
57
—————
0
R/W
PMRA7 6
0
R/W
PMRA6
——
—
Timer B event input edge switching
0 Timer B event input falling edge is detected. (Initial value)
1 Timer B event input rising edge is detected.
P67/RP7/TMBI pin switching
0 P67/RP7/TMBI pin functions as a P67/RP7 I/O pin. (Initial value)
1 P67/RP7/TMBI pin functions as a TMBI output pin.
:
:
:
Bit
Initial value
R/W
Rev. 1.0, 02/ 00, page 1101 of 1141
H'FFDA: Port Mode Register B PMRB: I/O Port
0
1
1
1
2
1
3
1
4
0
R/W
0
R/W
57 PMRB4
————
————
0
R/W
PMRB7 6
0
R/W
PMRB6 PMRB5
P77/RPB to P74/RPB pin switching
0 P7n/RPm pin functions as a P7n I/O pin. (Initial value)
1 P7n/RPm pin functions as a RPm output pin.
:
:
:
Bit
Initial value
R/W
(n = 7 to 4, m = B, A, 9, 8)
Rev. 1.0, 02/ 00, page 1102 of 1141
H'FFDB: Port Mode Register 4: PMR4: I/O Port
0
0
1
1
2
1
3
1
4
11
5
1
7
1R/W
6PMR40
P40/PWM14 pin functions as P40 I/O port (Initial value)
P40/PWM14 pin functions as PWM14 output port
0
1
P40/PWM14 pin function select bit
P47/RPTRG pin functions as P47 I/O port (Initial value)
P47/RPTRG pin functions as RPTRG I/O pin
0
1
P47/RPTRG pin function select bit
PMR47 — — — — — —
R/W——————
Bit
Initial value
R/W
:
:
:
H'FFDD: Port Mode Register 6 PMR6: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PMR64 PMR63 PMR62 PMR61 PMR60
0
R/W
PMR67
R/WR/WR/W
PMR66 PMR65
P6n/RPn pin functions as P6n I/O port (Initial value)
P6n/RPn pin functions as RPn output port
0
1
P67/RP7 to P60/RP0 pin function select bit
(n = 7 to 0)
Bit
Initial value
R/W
:
:
:
H'FFDE: Port Mode Register 7 PMR7: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7PMR74 PMR73 PMR72 PMR71 PMR70
0
R/W
PMR77
R/WR/WR/W
PMR76 PMR75
P77/PPG7 to P70/PPG0 pin function select bit
P7n/PPGn pin functions as P7n I/O port (Initial value)
P7n/PPGn pin functions as PPGn output port
0
1(n = 7 to 0)
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1103 of 1141
H'FFDF: Port Mode Register 8 PMR8: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
57 PMR84 PMR83 PMR82 PMR81 PMR80
0
R/W
PMR87 6
0
R/W
PMR86
R/WR/W
PMR85
P81/EXCAP pin function select bit
0 P81/EXCAP pin functions as P81 I/O pin (Initial value)
1 P81/EXCAP pin functions as EXCAP input pin
P80/YCO pin function select bit
0 P80/YCO pin functions as P80 I/O pin (Initial value)
1 P80/YCO pin functions as YCO input pin
P83/C.Rotary pin function select bit
0 P83/C.Rotary pin functions as P83 I/O pin (Initial value)
1 P83/C.Rotary pin functions as C.Rotary output pin
P82/EXCTL pin function select bit
0 P82/EXCTL pin functions as P82 I/O pin (Initial value)
1 P82/EXCTL pin functions as EXCTL input pin
P84/H.Amp.SW pin function select bit
0 P84/H.Amp SW pin functions as P84 I/O pin (Initial value)
1 P84/H.Amp SW pin functions as H.Amp SW output pin
P85/COMP pin function select bit
0 P85/COMP pin functions as P85 I/O pin (Initial value)
1 P85/COMP pin functions as COMP input pin
P86/EXTTRG pin function select bit
0 P86/EXTTRG pin functions as P86 I/O pin (Initial value)
1 P86/EXTTRG pin functions as EXTTRG input pin
P87/DPG pin function select bit
0 P87/DPG pin functions as P87 I/O pin (Initial value)
(Drum control signals are input as an overlapped signal)
1 P87/DPG pin functions as a DPG input pin
(Drum control signals are input as separate signal)
:
:
:
Bit
Initial value
R/W
Rev. 1.0, 02/ 00, page 1104 of 1141
H'FFE0: Port Mode Register C PMRC: I/O Port
0
1
1
0
R/W
2
1
3
0
4
0
R/W
0
R/W
567
PMRC4 PMRC3 PMRC1
11 R/W
PMRC5
P81/YBO pin function select bit
0 P81/YBO pin functions as P81 I/O port (Initial value)
1 P81/YBO pin functions as YBO output pin
P83/R pin function select bit
0 P83/R pin functions as P83 I/O port (Initial value)
1 P83/R pin functions as R output pin
P84/B pin function select bit
0 P84/G pin functions as P84 I/O port (Initial value)
1 P84/G pin functions as G output pin
P85/B pin function select bit
0 P85/B pin functions as P85 I/O port (Initial value)
1 P85/B pin functions as B output pin
:
:
:
Bit
Initial value
R/W
——
——
—
—
—
—
H'FFE1: Pull-Up MOS Select Register 1 PUR1: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PUR14 PUR13 PUR12 PUR11 PUR10PUR17 PUR16 PUR15
P1n pin has no pull-up MOS transistor (Initial value)
P1n pin has pull-up MOS transistor
0
1
(n = 7 to 0)
Bit :
Initial value :
R/W :
Rev. 1.0, 02/ 00, page 1105 of 1141
H'FFE2: Pull-Up MOS Select Register 2 PUR2: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PUR24 PUR23 PUR22 PUR21 PUR20PUR27 PUR26 PUR25
P2n pin has no pull-up MOS transistor (Initial value)
P2n pin has pull-up MOS transistor
0
1(n = 7 to 0)
Bit
Initial value
R/W
:
:
:
H'FFE3: Pull-Up MOS Select Register 3 PUR3: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7
0
R/W R/WR/WR/W
6PUR34 PUR33 PUR32 PUR31 PUR30PUR37 PUR36 PUR35
P3n pin has no pull-up MOS transistor (Initial value)
P3n pin has pull-up MOS transistor
0
1(n = 7 to 0)
Bit
Initial value
R/W
:
:
:
H'FFE4: Realtime Output Trigger Edge Select Register RTPEGR: I/O Port
0
0
1
0
R/W
2
1
3
1
4
11
56
1
7RTPEGR1 RTPEGR0
1R/W
00 Trigger input is disabled (Initial value)
RTPEGR0RTPEGR1
1 Rising edge of trigger input is selected
0
1 Rising and falling edges of trigger input is selected
1 Falling edge of trigger input is selected
Realtime output trigger edge select bit Description
Bit
Initial value
R/W
:
:
:
—
—
—
—
—
—
—
—
—
—
—
—
Rev. 1.0, 02/ 00, page 1106 of 1141
H'FFE5: Realtime Output Trigger Select Register RTPSR: I/O Port
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
56
0
7RTPSR4 RTPSR3 RTPSR2 RTPSR1 RTPSR0
0
R/W
RTPSR7
R/WR/WR/W
RTPSR6 RTPSR5
External trigger (RPTRG pin) input is selected (Initial value)
Internal triggfer (HSW) input is selected
0
1(n = 7 to 0)
Bit
Initial value
R/W
:
:
:
H'FFE6: Realtime Output Trigger Select Register RTPSR2: I/O Port
0
1
1
1
—
2
1
—
3
1
4
0
R/W
0
R/W
57 RTPSR24 — — — —
0
R/W
RTPSR27 6
0
R/W
RTPSR26
——
RTPSR25
:
:
:
External trigger RPTRG input is selected (Initial value)
Internal trigger HSW input is selected
0
1
Bit
Initial value
R/W
H'FFE8: System Control Register SYSCR: System Co ntrol
0
1
1
0
2
0
3
1
4
0
R/W
5
0
6
0
7
RR
INTM1 INTM0 XRST
——
0
00 0 Interrupt is controlled by I bit
INTM0INTM1
Interrupt
control mode
Interrupt control
1 1 Interrupt is controlled by I and UI bits and ICR
01 2 Cannot be used in the H8S/2199 Series
1 3 Cannot be used in the H8S/2199 Series
Reset is generated by watchdog timer overflow
Reset is generaed by external reset input
0
1
Interrupt control mode
External reset
—— —
—— ———
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1107 of 1141
H'FFE9: Mode Control Re gister MDCR: Syst e m Cont r o l
0
—
*
1
0
2
0
3
0
4
0
5
0
6
0
7
R
MDS0
0
Note: * Determined by MD0 pin.
Mode select 0
———————
———————
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1108 of 1141
H'FFEA: Standby Contro l Re g i st e r SBYCR: Syst e m Co ntrol
0
0
1
0
R/W
2
0
3
0
4
0
R/W
5
0
6
0
7
R/WR/W
STS1
R/W
STS2
0
R/W
SSBY STS0 SCK1 SCK0
Transition to sleep mode after execution of SLEEP instruction in
high-speed mode or medium-speed mode
Transition to subsleep mode after execution of SLEEP
instruction in subactive mode
Transition to stadby mode, subactive mode, or watch mode after
execution of SLEEP instruction in high-speed mode or medium-
speed mode
Transition to watch mode or high-speed mode after execution of
SLEEP instruction in subactive mode
0
1
Software standby
System clock select System clock select
00 SCK0SCK1
1
01
Bus master is in high-speed mode
Medium-speed clock is φ/16
Medium-speed clock is φ/32
1 Medium-speed clock is φ/64
00 STS1STS2
1
Standby timer select bits
0
STS0
1
0
Standby time
8192 states
16384 states
32768 states
01 1
0
1
65536 states
1* Reserved
131072 states
262144 states
Note: *Don't care.
——
——
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1109 of 1141
H'FFEB: Low-Power Control Register LPWRCR: Syste m Co nt r o l
0
0
1
0
R/W
2
0
3
0
4
0
5
0
6
0
7
R/WR/W
NESEL
R/W
LSON
0
R/W
DTON SA1 SA0
Low-speed on flag
Noise elimination sampling frequency select
Subactive mode clock select Subactive mode clock select
Sampling at φ divided by 16
Sampling at φ divided by 4
0
1
• When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, standby mode, or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition is made to watch
mode, or directly to high-speed mode
• When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made directly to subactive mode*, or a transition is made to sleep mode
or standby mode
• When a SLEEP instruction is executed in subactive mode, a transition is made
directily to high-speed mode, or a transition is made to subsleep mode
0
1
Direct transfer on flag
• When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, standby mode, or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition is made to watch
mode, or directly to high-speed mode
• After watch mode is cleared, a transition is made to high-speed mode
• When a SLEEP instruction is executed in high-speed mode a transition is made to
watch mode, subactive mode, sleep mode or standby mode.
• When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode or watch mode.
• After watch mode is cleared, a transition is made to subactive mode
0
1
Note: * Don't care.
00 SA0SA1
10 *1
Operating clock of CPU is φw/8
Operating clock of CPU is φw/4
Operating clock of CPU is φw/2
———
———
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1110 of 1141
H'FFEC: Module Stop Control Register MSTPCRH: System Control
H'FFED: Module Stop Control Register MSTPCRL: System Control
7
1
MSTP15
R/W
MSTPCRH
6
1
MSTP14
R/W
5
1
MSTP13
R/W
4
1
MSTP12
R/W
3
1
MSTP11
R/W
2
1
MSTP10
R/W
1
1
MSTP9
R/W
0
1
MSTP8
R/W
7
1
MSTP7
R/W
6
1
MSTP6
R/W
5
1
MSTP5
R/W
4
1
MSTP4
R/W
3
1
MSTP3
R/W
2
1
MSTP2
R/W
1
1
MSTP1
R/W
0
1
MSTP0
R/W
MSTPCRL
Module stop Module stop mode is released
Module stop mode is set (Initial value)
0
1
Bit
Initial value
R/W
:
:
:
H'FFEE: Serial Timer Control Register STCR: System Control
7
—
0
—
6
IICX1
0
R/W
5
IICX0
0
R/W
4
—
0
—
3
FLSHE
0
R/W
2
OSROME
0
R/W
1
—
0
—
0
—
0
—
Flash memory control register enable bit
OSD ROM enable
I
2
C control
Used combined with CKS2 to CKS0 in ICMR0
Note: * Refer to section 23.2.4, I
2
C Bus Mode Register (ICMR)
OSD ROM is accessed by OSD (Initial value)
OSD ROM is accessed by CPU
0
1
Flash memory control register is not selected (Initial value)
Flash memory control register is selected
0
1
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1111 of 1141
H'FFF0: IRQ Edge Select Register IEGR: Interrupt Controller
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
00
7
R/WR/WR/W
IRQ4EG
R/W
IRQ5EG IRQ3EG IRQ2EG IRQ1EG IRQ0EG1 IRQ0EG2
0
6
IRQ0 pin detected dege select bits Description
00 Interrupt request generaed at falling edge of IRQ0 pin input (Initial value)
IRQ0EG0IRQ0EG1
10 Interrupt request generaed at rising edge of IRQ0 pin input
*1 Interrupt request generaed at bath falling and rising edge of IRQ0 pin input
Note: * Don’t care.
IRQ5 to IRQ1 pins detected edge select bits
Interrupt request generated at falling edge of IRQn pin input (Initial value)
Interrupt request generated at rising edge of IRQn pin input
0
1(n = 5 to 1)
:Bit
Initial value :
R/W :
H'FFF1: IRQ Enable Register IENR: Interrupt Controller
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
5
00
7
R/WR/WR/W
IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
0
6
IRQ5 to IRQ0 enable bits
IRQn interrupt is disabled (Initial value)
IRQn interrupt is enabled
0
1(n = 5 to 0)
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1112 of 1141
H'FFF2: IRQ Status Register IRQ R: Interrupt Controller
0
0
1
0
R/(W)*
2
0
R/(W)*
3
0
4
0
R/(W)*
5
00
7
R/(W)*R/(W)*R/(W)*
IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
0
6
Note: * Only 0 can be written to clear the flag.
IRQ5 to IRQ0 flag
[Clearing conditions]
Cleared by reading IRQnF set to 1, then writing 0 in IRQnF
When IRQn interrupt exception handling is executed
[Setting conditions]
(1) When a falling edge occurs in IRQn input while falling edge detection is set (IRQnEG = 0)
(2) When a rising edge occurs in IRQn input while rising edge detection is set (IRQnEG = 0)
(3) When a falling or rising edge occurs in IRQ0 input while both-edge detection is set (IRQ0EG1 = 1)
0
1
(n = 5 to 0)
Bit
Initial value
R/W
:
:
:
(Initial value)
—
—
—
—
H'FFF3: Interrupt Control Register A ICRA: Interrupt Controller
H'FFF4: Interrupt Control Register B ICRB: Interrupt Controller
H'FFF5: Interrupt Control Register C ICRC: Interrupt Controller
H'FFF6: Interrupt Control Register D ICRD: Interrupt Controller
0
0
1
0
R/W
2
0
R/W
3
0
4
0
R/W
0
R/W
5
0
7ICR4 ICR3 ICR2 ICR1 ICR0
0
R/W
ICR7
R/WR/WR/W
ICR6 ICR5
6
Interrupt control level
Corresponding interrupt source is control level 0 (non-priority) (Initial value)
Corresponding interrupt source is control level 1 (priority)
0
1(n = 7 to 0)
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1113 of 1141
H'FFF8: Flash Memory Control Register 1 FLMCR1: FLASH ROM
7
FWE
—*
R
6
SWE1
0
R/W
5
ESU1
0
R/W
4
PSU1
0
R/W
3
EV1
0
R/W
0
P1
0
R/W
2
PV1
0
R/W
1
E1
0
R/W
Note: * Determined by the state of the FWE pin.
Program1
Software write enable
Writes are disabled (Initial value)
Writes are enabled
[Setting condition] When FWE = 1
0
1
Flash write enable
When a low level is input to the FWE pin (hardware-protected state)
When a high level is input to the FWE pin
0
1
Erase-verify1Erase-verify mode cleared (Initial value)
Transition to erase-verify mode
[Setting condition] When FWE = 1 and SWE1 = 1
0
1
Program-verify1
Program-verify mode cleared (Initial value)
Transition to program-verufy mode
[Setting condition] When FWE = 1 and SWE1 = 1
0
1
Program set-up1
Program set-up cleared (Initial value)
Transition to program set-up status
[Setting condition] When FWE = 1 and SWE1 = 1
0
1
Erase set-up1
Erase set-up cleared (Initial value)
Transition to erase set-up status
[Setting condition] When FWE = 1 and SWE1 = 1
0
1
Erase1 Erase mode cleared (Initial value)
Transition to erase mode
[Setting condition] When FWE = 1,
SWE1 = 1, and ESU1 = 1
0
1
Program mode cleared (Initial value)
Transition to program mode
[Setting condition] When FWE = 1,
SWE1 = 1, and PSU1 = 1
0
1
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1114 of 1141
H'FFF9: Flash Memory Control Register 2 FLMCR2: FLASH ROM
Flash memory error
Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition] Reset (Initial value)
An error has occurred during flash memeory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition] See section 7.6.3, Error Protection
0
1
7
FLER
0
R
6
SWE2
0
R/W
5
ESU2
0
R/W
4
PSU2
0
R/W
3
EV2
0
R/W
0
P2
0
R/W
2
PV2
0
R/W
1
E2
0
R/W
Program2
Software write enable2
Writes are disabled (Initial value)
Writes are enabled
[Setting condition] When FWE = 1
0
1
Erase-verify2Erase-verify mode cleared (Initial value)
Transition to erase-verify mode
[Setting condition] When FWE = 1 and SWE2 = 1
0
1
Program-verify2
Program-verify mode cleared (Initial value)
Transition to program-verufy mode
[Setting condition] When FWE = 1 and SWE2 = 1
0
1
Program set-up2
Program set-up cleared (Initial value)
Transition to program set-up status
[Setting condition] When FWE = 1 and SWE2 = 1
0
1
Erase set-up2
Erase set-up cleared (Initial value)
Transition to erase set-up status
[Setting condition] When FWE = 1 and SWE2 = 1
0
1
Erase2 Erase mode cleared (Initial value)
Transition to erase mode
[Setting condition] When FWE = 1,
SWE2 = 1, and ESU2 = 1
0
1
Program mode cleared (Initial value)
Transition to program mode
[Setting condition] When FWE = 1,
SWE2 = 1, and PSU2 = 1
0
1
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1115 of 1141
H'FFFA: Erase Block Select Register 1 EBR1: FLASH ROM
7
EB7
0
R/W
6
EB6
0
R/W
5
EB5
0
R/W
4
EB4
0
R/W
3
EB3
0
R/W
0
EB0
0
R/W
2
EB2
0
R/W
1
EB1
0
R/W
Bit :
Initial value :
R/W :
H'FFFB: Erase Block Select Register 2 EBR2: FLASH ROM
7
EB15
0
R/W
6
EB14
0
R/W
5
EB13
0
R/W
4
EB12
0
R/W
3
EB11
0
R/W
0
EB8
0
R/W
2
EB10
0
R/W
1
EB9
0
R/W
Bit
Initial value
R/W
:
:
:
Rev. 1.0, 02/ 00, page 1116 of 1141
Appendix C Pin Circuit Diagrams
C.1 Pin Circu it Diagrams
Circuit diagrams for all pins except power supply pins are shown in table C.1.
Legend
OUT
G
IN OUT
G
IN
PMOS NMOS Clocked gate
Signal transmitted
when G = 1
Signal transmitted
when G = 0
Table C.1 Pin Circuit Diagrams
Pin St a t e s
Pin Names Ci r cui t Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
P00/AN0 to
P07/AN7
· RD
SCH3 to SCH0
Hi-Z Retained Hi-Z
AN8 t o ANB
HCH1 AHCH0
Hi-Z Retained Hi-Z
Rev. 1.0, 02/ 00, page 1117 of 1141
Pin St a t e s
Pin Names Ci r cui t Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
Ret ain ed Pull-up MO S:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
P10/
,54
to
P15/
,54
P16/
,&
PUR1n ·
RD
PDR1n
PMR1n
PCR1n
INT
INT = to ,
n = 0 to 6
PMR1n
Hi-Z
When
,54
to
,54
and
,&
are selected, pin input
should be fixed high or low.
P17/TMOW
PUR17·
TMOW
PDR17
PMR17
PCR17
RD
Hi-Z Retained Pull-up MO S:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
Ret ain ed Pull-up MO S:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
P20/SI1
PUR20·
RD
PDR20
RXE
PCR20
SI1
RXE
RXE: Input control signal determined
by SCR and SMR
Hi-Z
When SI1 is selected, pin
input should be fixed high
or low.
Rev. 1.0, 02/ 00, page 1118 of 1141
Pin St a t e s
Pin Names Ci r cui t Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
P21/SO1
PUR21·
SO1
PDR21
TXE
PCR21
RD
TXE: Output control signal determined
by SCR and SMR
Hi-Z Retained Pull-up MO S:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
Ret ain ed Pull-up MO S:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
P22/SCK1
PUR22·
SCKO
SCKI
PDR22
CKOE
PCR22
RD
CKIE
SCKO: Transfer clock output
SCKI: Transfer clock input
CKOE: Transfer clock output control signal
determined by SMR and SCR
CKIE: Transfer clock input control signal
determined by SMR and SCR
Hi-Z
When SCK1 is selected,
pin input should be fixed
high or low.
Rev. 1.0, 02/ 00, page 1119 of 1141
Pin St a t e s
Pin Names Ci r cui t Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
Hi-Z Retained Pull-up MO S:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
P23/SDA1
P24/SCL1
P25/SDA0
P26/SCL0
PUR2n ·
SDA/SCL
PDR2n
IICE
PCR2n
RD
IICE
SDA/SCL
IICE = I
2
C bus enable signal
n = 3, 4, 5, 6
As SDA and SCL always function, a
high level or a low level should
always be input t o t he pins.
Hi-Z Retained Pull-up MO S:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
P27/SYNCI
PUR27 ·
PDR27
RD
PCR27
SYNCI
As SYNCI always functions, a high
level or a low level should always be
input to t he pin.
Rev. 1.0, 02/ 00, page 1120 of 1141
Pin St a t e s
Pin Names Ci r cui t Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
P30/SVI
P31/SV2
P32/PWM0
P33/PWM1
P34/PWM2
P35/PWM3
P36/BUZZ
P37/TMO
PUR3n ·
OUT
PDR3n
PMR3n
PCR3n
n = 1 to 7
RD
OUT:
P30/SV1: Servo monitor output
P31/SV2: Servo monitor output
P32/PWM0: 8 bit PWM0 output
P33/PWM1: 8 bit PWM1 output
P34/PWM2: 8 bit PWM2 output
P35/PWM3: 8 bit PWM3 output
P36/BUZZ: Timer J buzzer output
P37/TMO: Timer J timer output
Hi-Z Retained Pull-up MO S:
OFF
Subactive mode:
Functions
Ot her m odes:
Hi-Z
P40/PWM14
OUT
PDR40
PMR40
PCR40
OUT PWM14
RD
Hi-Z Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
Rev. 1.0, 02/ 00, page 1121 of 1141
Pin St a t e s
Pin Names Ci r cui t Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
Hi-Z Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
P41/FTIA
P42/PTIB
P43/FTIC
P44/FTID
RD
PDR4n
PCR4n
IN = FTIA, FTIB, FTIC, FTID
n = 1 to 4
IN
As FTIA to FTID always function, a
high level or a low level should
always be input t o t he pins.
P45/FTOA
P46/PTOB
OUT
PDR4n
TOE
PCR4n
RD n = 5, 6
OUT:
P45/FTOA: Timer X1 output compare
output FTOA
P46/FTOB: Timer X1 output compare
output FTOB
TOE: Output control signal determined
by TOCR
Hi-Z Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
Rev. 1.0, 02/ 00, page 1122 of 1141
Pin St a t e s
Pin Names Ci r cui t Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
Hi-Z Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
P47/RPTRG
RD
PDR47
PMR47
PCR47
RPTRG
PMR47
When RPTRG is selected,
pin input should be fixed
high or low.
P60/RP0 to
P65/RP5
RD n = 0 to 5
PDRS6n
PCRS6n
PMR6n
Hi-Z Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
Hi-Z Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
P66/RP6/
$'75*
RD
TRGE
TRGE: A/D trigger input control signal
PDRS66
PCRS66
PMR66
ADTRG
When
$'75*
is se lec ted ,
pin input should be fixed
high or low.
Rev. 1.0, 02/ 00, page 1123 of 1141
Pin St a t e s
Pin Names Ci r cui t Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
Hi-Z Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
P67/RP7/
TMBI
RD
PMRA7
PDRS67
PMRA7
PCRS67
PMR67
TMBI
When TMBI is selected,
pin input should be fixed
high or low.
P70/PPG0 to
P73/PPG3
PPGn
PDR7n
PMR7n
PCR7n
RD n = 0 to 3
Hi-Z Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
P74/PPG4/
RP8 to P77/
PPG7/RP8
PPGn
PDRS7n
PMRBn
PMR7n
PCRS7n
RD
n = 4 to 7
Hi-Z Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
Rev. 1.0, 02/ 00, page 1124 of 1141
Pin St a t e s
Pin Names Ci r cui t Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
P80/YCO
YCO
PDR80
PMR80
PCR80
RD
Hi-Z Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
P83/
C.Rotary/R
P84/H.Amp
SW/G
OUT1
OUT1:
OUT2:
n = 3, 4
C.Rotary, H.Amp SW
R, G
OUT2
PDR8n
PMRCn
PMR8n
PCR8n
RD
Hi-Z Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
Hi-Z Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
P82/EXCTL
P86/
EXTTRG
PMR8n
IN = EXCTL, EXTTRG
RD
n = 2, 6
PDR8n
PMR8n
PCR8n
IN
When EXCTL and
EXTTRG are selected, pin
input should be fixed high
or low.
Rev. 1.0, 02/ 00, page 1125 of 1141
Pin St a t e s
Pin Names Ci r cui t Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
Hi-Z Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
P85/COMP/
B
P81/EXCAP/
YBO
OUT
PDR8n
PMRCn
PMR8n
PCR8n
IN
RD
PMR8n
n= 1, 5
IN=EXCAP, COMP
OUT= YBO, B
When EXCAP COMP is
selected, pin input should
be fixed high or low.
P87/DPG
RD
PDR87
PCR87
DPG
Hi-Z Retained Subact ive mode:
Functions
Ot her m odes:
Hi-Z
Csync
Module STOP
Pin input should be fixed high or low.
AUDIOFF
VIDEOFF
OUT
LPM
Hi-Z Hi-Z Hi-Z
CAPPWM
DRMPWM Low
output Low
output Low output
Vpulse
LPM
3-level
controller
15kΩ
Typ
Note:Resistance values are
reference values.
15kΩ
Typ
Low
output Low
output Low output
Rev. 1.0, 02/ 00, page 1126 of 1141
Pin St a t e s
Pin Names Ci r cui t Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
5(6
RST
Low input (High) (High)
MD0
FWE
CFG
+
-
+
-
+
-
CFGCOMP
CFGCOMP
P250
REF
M250 S
R
F/F
O
stp
VREF
VREF
CFG
BIAS
Res+ModuleSTOP

DFG
DPG
RD ·
PDRn
DFG
DPG
PMRn
PCRn
DPG SW
DPG SW
Pes+LPM
DFG
DPG
Hi-Z Hi-Z
CTL (+ )
CTL (−)
CTLREF
CTLBias
CTLFB
CTLAmp (O)
CTLSMT (I)
+
-
-
+
+ -
CTLGR3 to 1 CTLFB CTLGR0
AMPSHORT
(REC-CTL)
AMPON
(PB-CTL)
PB-CTL (+)
PB-CTL (Ð)
CTLSMT (i)
CTLREF
CTL (+)CTL (-) CTLBias CTLFB CTLAmp(o)
*
Note: * Connect a capacitor between
CTLAmp (o), CTLSMT (i)

Rev. 1.0, 02/ 00, page 1127 of 1141
Pin St a t e s
Pin Names Ci r cui t Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
X2
X1
10MΩ
Typ
Note:The resistance value is a
reference value.
Oscil-
lation Oscil-
lation Oscillation
OSC2 Low output
OSC1
LPM
Oscil-
lation Oscil-
lation
CVin1
Sync tip
i1.4V j
LPM
+
–
+
–
Hi-Z Hi-Z Hi-Z
CVout
+
–
LPM
Hi-Z Hi-Z Hi-Z
Rev. 1.0, 02/ 00, page 1128 of 1141
Pin St a t e s
Pin Names Ci r cui t Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
4/ 2fs c in Oscilla -
tion Oscilla-
tion
4/2fsc out
LPM
4/2fsc in
(External input)
4/2fsc in
External clock select
Low output
(Oscillation
stopped)
VLPF/Csync Pin input should be fixed high or low
Csync/
Hsync Hi-Z Hi-Z Hi-Z
CVin2
+
–
+
–
+
–
+
–
+
–
+
–
Polarity
switch Signal
selection
Polarity
switch
I/O
switch
Sync tip
(2.0V)
Signal
selection
Vsync
Hsync
VSEL
SYNCT
LPM
·
CCMPSL
CCMPSL
EDS
LPM
Hi-Z Hi-Z Hi-Z
Rev. 1.0, 02/ 00, page 1129 of 1141
Pin St a t e s
Pin Names Ci r cui t Diagram At Reset Sleep
Mode
Power-Down
Modes O t her
Than Sleep
Mode
AFCOSC Oscilla-
tion Oscilla-
tion Hi-Z
Oscillation
stopped
AFCPC 1/2 OVCC 1/2 OVCC
AFCLPF
1/2 OV
CC
LPM
UP
+
DOWN
LPM
LPM
–
Phase
gain
control
Retained Retained
Legend
RD: Read signal
RST: Reset signal
LPM: Power-down mode signal (1 in standby, wat ch, subactive, and subsleep modes)
Hi-Z: High impedance
SLEEP: Sleep mode signal
Note: Numbers given for r esistance values, etc., ar e r ef er ence values.
Rev. 1.0, 02/ 00, page 1130 of 1141
Appendix D Port States in Each Processing State
D.1 Pin Circu it Diagrams
Table D.1 Port States Over vi ew
Port Reset Active Sleep Standby Watch Subactive Subsleep
P07 to
P00 High
imped-
ance
High
imped-
ance
High
imped-
ance
High
imped-
ance
High
imped-
ance
High
impedance High
impedance
P17 to
P10 High
imped-
ance
Functions Retained High
imped-
ance
High
imped-
ance
Functions Retained
P27 to
P20 High
imped-
ance
Functions Retained High
imped-
ance
High
imped-
ance
Functions Retained
P37 to
P30 High
imped-
ance
Functions Retained High
imped-
ance
High
imped-
ance
Functions Retained
P47 to
P40 High
imped-
ance
Functions Retained High
imped-
ance
High
imped-
ance
Functions Retained
P67 to
P60 High
imped-
ance
Functions Retained High
imped-
ance
High
imped-
ance
Functions Retained
P77 to
P70 High
imped-
ance
Functions Retained High
imped-
ance
High
imped-
ance
Functions Retained
P87 to
P80 High
imped-
ance
Functions Retained High
imped-
ance
High
imped-
ance
Functions Retained
Rev. 1.0, 02/ 00, page 1131 of 1141
Appendix E Usage Notes
E.1 Power Supply Rise and Fall Order
Figure E. 1 shows the order in whic h t he power supply pi ns rise when t he c hi p is powered on, a nd
the order in which they fall when the chip is powered down. If the power supply voltages cannot
rise and fall simultaneously, power supply operations should be carried out in this order.
• At power-on, wait until the microcomputer section power supply (VCC) ha s risen to t he
prescribed voltage, then raise the other analog power supplies.
• At power-down, drop the analog power supplies first, followed by the microcomputer section
power supply (VCC).
When powering up and down, the voltage applied to the pins should not exceed the respective
power supply voltage.
V
CC
, AV
CC
V
CC
AV
CC
SV
CC
OSD
Vin
: Microcomputer section power supply voltage
: A/D converter power supply voltage
: Servo section power supply voltage
: Section power supply voltage
: Pin applied voltage
SV
CC
,OV
CC
V
CC
, AV
CC
SV
CC
Vin Vin
Fi g ur e E .1 P o we r Suppl y Rise a nd F a l l O r de r
In power-down modes (except sleep mode), the analog power supplies can be controlled at the
VSS level to reduce current dissi pation. When the microcomputer section power supply (VCC) is
dropped to the backup voltage in a power-down mode, the order shown in figure E. 2 should be
followed. Make sure that the voltage applied to the pins does not exceed the respective power
supply voltage.
The A/D convert e r power supply (AVCC) should be set to the same potential as the
microcomputer section power supply (V CC). In all power-down modes except sleep mode, AVCC
is turned off inside the device. At this time, the AVCC current dissipation is defined as AISTOP.
Rev. 1.0, 02/ 00, page 1132 of 1141
VCC
AVCC
SVCC
OVCC
Vin
5 V
2.7 V
: Microcomputer section power supply voltage
: A/D converter power supply voltage
: Servo section power supply voltage
: OSD Section power supply
: Pin applied voltage
VCC, AVCC
SVCC, OVCC
Vin
Fi g ur e E .2 P o we r Suppl y Co nt r o l i n Powe r - Do wn M o de s
Rev. 1.0, 02/ 00, page 1133 of 1141
E.2 Sampl e Ext ern al Ci rcui t s
Examples of external circuits for the servo section, and sync signal detection circuit are shown in
figures E. 3, E. 4.
1. Servo Section
An exa mp l e of th e e xt e rna l c i r cu i t for th e DRMPW M output a nd CAPPW M out put pi ns i s
shown in figure E. 3.
R1
DRMPWM
CAPPWN
C1
Figure E.3 Sample External Circuit for Servo Section
2. Sync Signal Detection Circuit Section in Servo Circuit
Figure E.4 shows an example of the external circuit for the sync signal detection circuit section
in the servo c i rcui t .
33 kΩ
Csync
Note: Reference values are shown.
The board floating capacitance and wiring resistance must also
be taken into consideration in determining the values.
10 pF
Figure E.4 Example of External Circuit for Sync Signal Detection Circuit Section
Rev. 1.0, 02/ 00, page 1134 of 1141
3. OSD
An exam pl e of t he e xt erna l c i rc ui t for th e OSD i s shown i n fi gure E . 5.
The circuit configuration and values for the filter section will vary according to the wiring
capacitance, impedance, etc.
When designing the board, an appropriate filter should be configured, taking account of the
wiring load. Noise prevention measures also need to be taken when designing the board.
Clamp
(=1.4Vtyp)
Note: Reference values are shown.
The board floating capacitance and wiring resistance must also
be taken into consideration in determining the values.
C.Vin1
C.Vout
4.7µF
470µF
+68Ω
75Ω driver
1kΩ
2.7kΩ
470kΩ
120Ω
5pF
Figure E.5 Example of External Circuit for OSD
4. Sync Separator and Data Slicer
Examples of the external circuits for the sync separator and data slicer are shown in figures E. 6
to E.8.
The sync signal se paration sources can be selected from the following three: (1) CVin2, (2)
Csync, and (3) separate Hsync and Vsync signals. The external circuit configuration will vary
depending on t he separa t ion source .
When the data slicer is used, CVin2 is recommended as the separation source. When Csync or
Hsync and Vsync are selected as the source, connect to CVin2 the same external circuit as when
CVin2 is selected as the separation source.
Rev. 1.0, 02/ 00, page 1135 of 1141
4.7µF
4.7µF
6.8µH/12µH
0.01µF
0.01µF
330pF
680pF
10pF/12pF
C.Vin2
VLPF/Vsync
Csync/Hsync
AFCOSC
AFCPC
AFCLPF
330Ω
470kΩ
10kΩ
470Ω
2.4kΩ
Clamp 2
(=2.0Vtyp)
Note: Reference values are shown.
The board floating capacitance and wiring resistance
must also be taken into consideration in determining the values.
Figure E.6 Example of External Circuit for Sync Separator and Data Slicer
((1) Separation from CVin2)
Rev. 1.0, 02/ 00, page 1136 of 1141
4.7µF
0.01µF
0.01µF
10PF
C.Vin2
VLPF/Vsync
Csync/Hsync
AFCOSC
AFCPC
AFCLPF
10kΩ
10kΩ
33kΩ
2.4kΩ
Clamp 2
(=2.0Vtyp)
6.8µH/12µH
10pF/12pF
470Ω
OVCC
Figure E.7 Example of External Circuit for Sync Separator and Data Slicer
((2) Separation from Csync)
Rev. 1.0, 02/ 00, page 1137 of 1141
4.7µF
4.7µF0.01µF
C.Vin2
VLPF/Vsync
Csync/Hsync
AFCLPF
AFCOSC
2.4kΩ
Clamp 2
(=2.0Vtyp)
6.8µH/12µH
10pF/12pF
470Ω
Note: Reference values are shown.
The board floating capacitance and wiring resistance
must also be taken into consideration in determining the values.
10kΩ
OV
CC
Figure E.8 Example of External Circuit for Sync Separator and Data Slicer
((3) Separation from Hsync and Vsync )
Rev. 1.0, 02/ 00, page 1138 of 1141
E.3 H andling of P ins When OSD Is Not Used
Ta b l e E. 2 sho ws t h e h a n d l i n g of p i n s when t h e OSD, syn c se p a r a tor , o r d ata slicer is not used.
Table E.2 Handling of Pi ns When OSD Is Not Used
Condit ions Pin Handling
OSD Used Not used Not used Not used Not used
Data slicer Not used Used Not used Not used Not used
Module used
or not used
Sync
separator Used Used Used Not used Not used
OSDVCC VCC VCC VCC VCC VSS
OSDVSS VSS VSS VSS VSS VSS
Csync/Hsync Csync/Hsync Csync/Hsync Csync/Hsync 10 kΩ to VSS VSS
VLPF/Vsync VLPF/Vsync VLPF/Vsync VLPF/Vsync 10 k Ω to VSS VSS
AFCOSC AFCO SC AFCOSC AFCOSC 10 k Ω to VSS VSS
AFCPC AFCPC AFCPC AFCPC OPEN VSS
AFCLPF AFCL PF AFCLPF AFCLPF 10 k Ω to VSS VSS
CVin1 CVin1 10 kΩ to VSS 10 kΩ to VSS 10 kΩ to VSS VSS
CVout CVout OPEN OPEN OPEN VSS
4fsc in 4fsc in VSS VSS VSS VSS
4fs c o ut 4f s c o ut OPEN O PEN OPEN OPEN
Pins
CVin2 CVin2 or 10
kΩ to VSS
CVin2 or 10
kΩ to VSS
CVin2 or 10
kΩ to VSS
10 kΩ to VSS VSS
Note The register s
in t he OSD,
sync
separator,
and data
slice r mu s t
not be
accessed.
Rev. 1.0, 02/ 00, page 1139 of 1141
Tabl e E .3 P i n Handl ing When Usi ng OSD and Sy nc Se pa r a t i o n, a nd No t Using CVi n1
and CVin2
Condit ions Pin Handli ng
OSD Used
Module used or not used
Sync separator Used
CVin1 10 KΩ to OVccUnused pins
CVin2 10 KΩ to OVcc
Rev. 1.0, 02/ 00, page 1140 of 1141
Appendix F Product Lineup
Table F.1 Product Lineup of H8S/2199 Series
Product Type Product
Code Mar k Code
Package
(Hitachi
Package Code)
Mask ROM
version HD6432199 HD6432199 (***)F 112-pin FP
(FP-112)
H8S/2199
F-ZTAT
version HD64F2199 HD64F2199F 112-pin FP
(FP-112)
H8S/2198 Mask ROM
version HD6432198 HD6432198 (***)F 112-pin FP
(FP-112)
H8S/2197 Mask ROM
version HD6432197 HD6432197 (***)F 112-pin FP
(FP-112)
H8S/2199
Series
H8S/2196 Mask ROM
version HD6432196 HD6432196 (***)F 112-pin FP
(FP-112)
Note: (***) is the ROM code.
Rev. 1.0, 02/ 00, page 1141 of 1141
Appendix G Package Dimensions
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
FP-112
—
Conforms
2.4 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
0.10
23.2 ± 0.3
*0.32 ±0.08
0.65
1.6
0.8 ± 0.3
*0.17 ± 0.05
3.05 Max
23.2 ± 0.3
84 57
56
29
112
128
20
85
2.70
0° – 8°
0.13 M
0.10
+0.15
–0.10
1.23
0.30 ±0.06
0.15 ± 0.04
Figure G . 1 P ackage Dime nsions (FP-112)
H8S/2199 Series, H8S/2199F-ZTAT™ Hardware Manual
Publication Date: 1st Edition, February 2000
Published by: Electronic Devices Sales & Marketing Group
Semiconductor & Integrated Circuits
Hitachi, Ltd.
Edited by: Technical Documentation Group
Hitachi Kodaira Semiconductor Co., Ltd.
Copyright © Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.