1
Precision Edge®
SY89872U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
Guaranteed AC performance over temperature and
voltage:
• >2GHz fMAX
• < 750ps tPD (matched delay between banks)
• < 15ps within-device skew
• < 200ps rise/fall time
Low jitter design
• < 1psRMS cycle-to-cycle jitter
• < 10psPP total jitter
Unique input termination and VT pin for DC-coupled
and AC-coupled inputs: any differential inputs
(LVPECL, LVDS, CML, HSTL)
Precision differential LVDS outputs
Matched delay: all outputs have matched delay,
independent of divider setting
TTL/CMOS inputs for select and reset/disable
Two output banks (matched delay)
• Bank A: Buffered copy of input clock (undivided)
• Bank B: Divided output (÷2, ÷4, ÷8, ÷16),
two copies
2.5V power supply
Wide operating temperature range: –40°C to +85°C
Available in 16-pin (3mm x 3mm) MLF® package
FEATURES
2.5V, 2GHz ANY DIFF. IN-TO-LVDS
PROGRAMMABLE CLOCK DIVIDER/
FANOUT BUFFER W/INTERNAL TERMINATION
Precision Edge®
SY89872U
APPLICATIONS
OC-3 to OC-192 SONET/SDH applications
Transponders
Oscillators
SONET/SDH line cards
Rev.: F Amendment: /0
Issue Date: August 2007
This 2.5V low-skew, low-jitter, precision LVDS output clock
divider accepts any high-speed differential clock input (AC
or DC-coupled) CML, LVPECL, HSTL or LVDS and divides
down the frequency using a programmable divider ratio to
create a frequency-locked, lower speed version of the input
clock. The SY89872U includes two output banks. Bank A is
an exact copy of the input clock (pass through) with matched
propagation delay to Bank B, the divided output bank.
Available divider ratios are 2, 4, 8 and 16. In a typical
622MHz clock system this would provide availability of
311MHz, 155MHz, 77MHz or 38MHz auxiliary clock
components.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards. A VREF-AC
reference is included for AC-coupled applications.
The SY89872U is part of Micrel’s high-speed Precision
Edge® timing and distribution family. For 3.3V applications,
consider the SY89873L. For applications that require an
LVPECL output, consider the SY89872U.
The /RESET input asynchronously resets the divider
outputs (Bank B). In the pass-through function (Bank A) the
/RESET synchronously enables or disables the outputs on
the next falling edge of IN (rising edge of /IN). Refer to the
“Timing Diagram.”
FUNCTIONAL BLOCK DIAGRAM TYPICAL APPLICATION
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
IN
/IN
S1
S0
QB
1
/QB
1
QB
0
/QB
0
QA
/QA
/RESET,
/
DISABLE
VT
Divided
by
2, 4, 8
or 16
Decoder
Enable
FF
Enable
MUX
50Ω
50Ω
VREF-AC
IN
/IN OC-12 or OC-3
Clock Generator
622MHz LVPECL
Clock In
/QB
QB
/QA
QA
622MHz/155.5MHz
SONET Clock Generator
622MHz LVDS
Clock Out
155.5MHz LVDS
Clock Out
Bank A: 622MHz for OC-12 line card
Bank B: 155.5MHz for OC-3 line card (set to divide-by-4)
Precision Edge®
2
Precision Edge®
SY89872U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
Pin Number Pin Name Pin Function
1, 2, 3, 4 QB0, /QB0 Differential LVDS Compatible Outputs: Divide by 2, 4, 8, 16.
QB1, /QB1 Unused outputs must be terminated with 100ý across the pin (Q, /Q).
5, 6 QA, /QA Differential LVDS Compatible Undivided Output Clock.
7, 14 VCC Positive Power Supply: Bypass with 0.1µF/0.01µF low ESR capacitors.
8 /RESET, /DISABLE Output Reset and Output Enable/Disable: Internal 25ký pull-up. Input threshold is V CC/2.
Logic LOW will reset the divider select, and align Bank A and Bank B edges. In addition, when
LOW, Bank A and Bank B will be disabled.
12, 9 IN, /IN Differential Reference Input Clock: Internal 50ý termination resistors to VT input.
See “Input Interface Applications” section.
10 VREF-AC Reference Voltage: Equal to VCC–1.4V (approx.), and used for AC-coupled applications.
Maximum sink/source current is 0.5mA. See “Input Interface Applications” section.
11 VT Termination Center-Tap: For DC-coupled CML and LVDS inputs, leave this pin floating. See
“Input Interface Applications” section.
13 GND Ground.
15, 16 S1, S0 Select Pins: LVTTL/CMOS logic levels. Internal 25ký pull-up resistor. Logic HIGH if left
unconnected (divided by 16 mode). S0 = LSB. Input threshold is VCC/2.
PIN DESCRIPTION
/RESET
/DISABLE S1 S0 Bank A Output Bank B Outputs
1 0 0 Input Clock Input Clock ÷2
1 0 1 Input Clock Input Clock ÷4
1 1 0 Input Clock Input Clock ÷8
1 1 1 Input Clock Input Clock ÷16
0 X X QA = Low, /QA = High(1) QB0 = Low, /QB0 = High(2)
QB1 = Low, /QB1 = High(2)
TRUTH TABLE
Note 1. On the next negative transition of the input signal.
Note 2. Asynchronous reset/disable function. (See “Timing Diagram”)
PACKAGE/ORDERING INFORMATION
13141516
12
11
10
9
1
2
3
4
8765
QB0
/
QB0
QB1
/
QB1
IN
VT
VREF-A
C
/IN
S0
S1
VC
C
GN
D
QA
/QA
VCC
/RESET
/
DISABLE
16-Pin MLF® (MLF-16)
Ordering Information(1)
Package Operating Package Lead
Part Number Type Range Marking Finish
SY89872UMI MLF-16 Industrial 872U Sn-Pb
SY89872UMITR(2) MLF-16 Industrial 872U Sn-Pb
SY89872UMG(3) MLF-16 Industrial 872U with NiPdAu
Pb-Free bar line indicator Pb-Free
SY89872UMGTR(2, 3) MLF-16 Industrial 872U with NiPdAu
Pb-Free bar line indicator Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
3
Precision Edge®
SY89872U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)...................................–0.5V to +6.0V
Input Voltage (VIN) .......................................... –0.5V to VCC
LVDS Output Current (IOUT) .....................................±10mA
Input Current IN, /IN (IIN) ..........................................±50mA
VREF-AC Input Sink/Source Current (IVREF-AC),Note 3 .±2mA
Lead Temperature (soldering, 20sec.) ...................... 260°C
Storage Temperature (TS) ........................–65°C to +150°C
Operating Ratings(Note 2)
Supply Voltage Range .............................2.375V to 2.625V
Ambient Temperature (TA) .........................–40°C to +85°C
Package Thermal Resistance
MLF® (θJA)
Still-Air............................................................. 60°C/W
500lfpm ........................................................... 54°C/W
MLF® (ψJB), Note 4
Junction-to-Board............................................ 32°C/W
TA= –40°C to +85°C; Unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VCC Power Supply Voltage 2.375 2.5 2.625 V
ICC Power Supply Current No load, max. VCC 75 110 mA
RIN Differential Input Resistance 90 100 110 ý
(IN-to-/IN)
VIH Input High Voltage Note 3 0.1 VCC+0.3 V
IN, /IN
VIL Input Low Voltage Note 3 –0.3 VIH–0.1 V
IN, /IN
VIN Input Voltage Swing Notes 3, 4 0.1 VCC V
VDIFF_IN Differential Input Voltage Swing Notes 3, 4, 5 0.2 V
|IIN| Input Current Note 3 45 mA
IN, /IN
VREF-AC Reference Voltage Note 6 VCC –1.525VCC–1.425 VCC–1.325 V
Note 1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 2. Specification for packaged product only.
Note 3. Due to the internal termination (see “Input Buffer Structure” section) the input current depends on the applied voltages at IN, /IN and VT inputs.
Do not apply a combination of voltages that causes the input current to exceed the maximum limit!
Note 4. See “Timing Diagram” for VIN definition. VIN (max.) is specified when VT is floating.
Note 5. See Figures 1c and 1d for VDIFF definition.
Note 6. Operating using VIN is limited to AC-coupled PECL or CML applications only. Connect directly to VT pin.
DC ELECTRICAL CHARACTERISTICS(Note 1, 2)
Note 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended
periods may affect device reliability.
Note 2. The datasheet limits are not guaranteed if the device is operated beyond the operating ratings.
Note 3. Due to the limited drive capability use for input of the same package only.
Note 4. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB.
4
Precision Edge®
SY89872U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
VCC = 2.5V ±5%; TA = –40°C to +85°C; Unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VIH Input HIGH Voltage 2.0 – VCC V
VIL Input LOW Voltage 0 – 0.8 V
IIH Input HIGH Current –125 – 20 µA
IIL Input LOW Current – – –300 µA
Note 1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 2. Specification for packaged product only.
LVTTL/CMOS INPUTS DC ELECTRICAL CHARACTERISTICS(Note 1, 2)
VCC = 2.5V ±5%; TA = –40°C to +85°C; Unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VOUT Output Voltage Swing Note 5 250 350 450 mV
VOH Output High Voltage Note 3 1.475 V
VOL Output Low Voltage Note 3 0.925 V
VOCM Output Common Mode Voltage Note 4 1.125 1.375 V
∆VOCM Change in Common Mode Voltage –50 50 mV
Note 1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 2. Specification for packaged product only.
Note 3. Measured as per Figure 1a, 100ý across Q and /Q outputs.
Note 4. Measured as per Figure 1b.
Note 5. See Figure 1c.
LVDS OUTPUTS DC ELECTRICAL CHARACTERISTICS(Note 1, 2)
5
Precision Edge®
SY89872U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
VCC = 2.5V ±5%; TA = –40°C to +85°C; Unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
fMAX Maximum Toggle Frequency Output Swing: ž200mV 2 GHz
Maximum Input Frequency Note 3 3.2 GHz
tPD Differential Propagation Delay Input Swing: <400mV 500 625 750 ps
IN to Q Input Swing: ž400mV 450 575 700 ps
tSKEW Within-Device Skew (differential) Note 4 7 15 ps
(QB0-to-QB1)
Within-Device Skew (differential) Note 4 12 30 ps
(Bank A-to-Bank B)
Part-to-Part Skew (differential) Note 4 250 ps
trr Reset Recovery Time Note 5 600 ps
Tjitter Cycle-to-Cycle Jitter Note 6 1 psRMS
Total Jitter Note 7 10 psPP
tr, tfRise / Fall Time (20% to 80%) 70 130 200 ps
Note 1. Measured with 400mV input signal, 50% duty cycle. 100ý termination between Q and /Q, unless otherwise stated.
Note 2. Specification packaged product only.
Note 3. Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-to-output ÷2, ÷4, ÷8, ÷16) can accept an input frequency
>3GHz, while Bank A will be slew rate limited.
Note 4. Skew is measured between outputs under identical transitions.
Note 5. See “Timing Diagram.”
Note 6. Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc=Tn–Tn+1,
where T is the time between rising edges of the output signal.
Note 7. Total jitter definition: with an ideal clock input, of frequency - fMAX (device), no more than one output edge in 1012 output edges will deviate by
more than the specified peak-to-peak jitter value.
AC ELECTRICAL CHARACTERISTICS(Note 1, 2)
6
Precision Edge®
SY89872U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
TIMING DIAGRAM
LVDS OUTPUT
VOUT 100Ω
VOH, VOL
VOH, VOL
GND
Figure 1a. LVDS Differential Measurement
GND
50Ω
50ΩV
OCM,
∆V
OCM
Figure 1b. LVDS Common Mode Measurement
V
IN
Swing
/
RESET
IN
/IN
/QB
QB
QA
/QA
t
PD
t
RR
V
CC/2
V
OUT
Swing
V
IN,
V
OU
T
350mV
(typica
l)
Figure 1c. Single-Ended Swing
700mV (typical)
V
DIFF_IN
,
V
DIFF_OU
T
Figure 1d. Differential Swing
DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING
7
Precision Edge®
SY89872U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
TYPICAL OPERATING CHARACTERISTICS
VCC = 2.5V, VIN = 400mV, TA = 25°C, unless otherwise stated.
0
50
100
150
200
250
300
350
400
0
500
1000
1500
2000
2500
3000
3500
QA AMPLITUDE (mV)
FREQUENCY (MHz)
QA Output Amplitude
vs. Frequency
500
550
600
650
700
0
200
400
600
800
1000
1200
1400
PROPAGATION DELAY (ps)
INPUT SWING (mV)
IN to Q Propagation Delay
vs. Input Swing
500
525
550
575
600
-40 -20 0 20 40 60 80 100
PROPAGATION DELAY (ps)
TEMPERATURE (°C)
IN to Q Propagation Delay
vs. Temperature
QA
/QA
/QB0
QB0
QA @622MHz and QB @155.5MHz
(Divide-by-4)
TIME (1ns/div.)
Output Swing
(100mV/div.)
622MHz Output
155.5MHz Output
1.25GHz Output
TIME (150ps/div.)
/Q
Q
Output Swing
(50mV/div.)
2GHz Output
/Q
Q
TIME (100ps/div.)
Output Swing
(50mV/div.)
8
Precision Edge®
SY89872U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
INPUT BUFFER STRUCTURE
V
CC
GND
50Ω
50Ω
IN
V
T
/
IN
1.86kΩ
1.86kΩ1.86kΩ
1.86kΩ
Figure 2a. Simplified Differential
Input Buffer
VCC
GND
S0
S1
/RESET
R25kΩ
R
Figure 2b. Simplified TTL/CMOS
Input Buffer
9
Precision Edge®
SY89872U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
Part Number Function Data Sheet Link
SY89871U 2.5GHz Any Diff. In-to-LVPECL Programmable
Clock Divider/Fanout Buffer w/Internal Termination http://www.micrel.com/product-info/products/sy89871u.shtml
SY89873L 3.3V, 2GHz Any Diff. In-to-LVDS Programmable
Clock Divider/Fanout Buffer http://www.micrel.com/product-info/products/sy89873l.shtml
MLF® Application Note http://www.amkor.com/products/notes_papers/mlf_appnote_0902.pdf
HBW Solutions New Products and Applications http://www.micrel.com/product-info/products/solutions.shtml
RELATED PRODUCT AND SUPPORT DOCUMENTATION
INPUT INTERFACE APPLICATIONS
CML IN
/IN
VT
NC
G
ND
SY89872
U
VCC VCC
VREF-AC
NC
Figure 3a. DC-Coupled CML
Input Interface
V
CC
0.01µF
CML IN
/IN
V
T
G
ND
SY89872
U
V
CC
V
CC
V
REF-AC
Figure 3b. AC-Coupled CML
Input Interface
PECL IN
/IN
VT
GND SY89872
U
V
CC
V
CC
V
REF-AC
NC
* Bypass with 0.01µF to
V
CC
50Ω
0
.01µF
V
CC
–2V*
V
CC
Figure 3c. DC-Coupled PECL
Input Interface
V
CC
0.01µF
PECL IN
/IN
V
T
G
ND
SY89872
U
V
CC
V
CC
GND
50Ω50Ω
V
REF-AC
Figure 3d. AC-Coupled PECL
Input Interface
LVDS IN
/IN
V
T
NC
G
ND
SY89872
U
V
CC
V
CC
V
REF-AC
NC
Figure 3e. LVDS
Input Interface
HSTL IN
/IN
V
T
G
ND
SY89872
U
V
CC
V
CC
GND
NC V
REF-AC
Figure 3f. HSTL
Input Interface
10
Precision Edge®
SY89872U
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
16-PIN MicroLeadFrame® (MLF-16)
Package
EP- Exposed Pa
d
Die
CompSide Island
Heat Dissipation
Heavy Copper Plane
Heavy Copper Plane
VEE
VEE
Heat Dissipation
PCB Thermal Consideration for 16-Pin MLF® Package
(Always solder, or equivalent, the exposed pad to the PCB)
Package Notes:
Note 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form.
Note 2. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
