BM94801KUT-Z - ROHM SEMICONDUCTOR

Datashee

t

○Product structure：Silicon monolithic integrated circuit ○ This product has no designed protection against radioactive rays

1/376 TSZ02201-0V2V0E600300-1-2

18.Apr.2014 Rev.003

www.rohm.com

TSZ22111・14・001

Audio 1-Chip SOC

BM94801KUT

General Description

The BM94801KUT is a 1-Chip SOC for multimedia audi o

systems, which supports the Bluetooth A2DP, USB

memory, SD memory card, and CD.

This IC has a built-in ARM946ES processor, SDRAM,

and various peripherals. It is designed to download

programs from external Serial Flash ROM and execute

system control, file system management, Audio CODEC,

and a wide range of media control.

Features

This IC includes the following blocks:

Processor

 ARM946ES Microprocessor Core

Memory

 SDRAM

 Initial Program ROM

 Program SRAM

 Data SRAM

 SDRAM Controller

System

 Multilayer AHB

 DMA BUS

 Interrupt Controller

 DMA Controller

Serial, Media I/F

 GPIO

 Pin Controller

 USB2.0 Dual Role (Host/Device) Controller

 SD I/F

 Quad SPI I/F

 SPI I/F (Master/Slave)

 I2C I/F (Master/Slave)

 UART I/F

 I2S Input I/F

 I2S Output I/F

 CD Servo Controllers

 CD-ROM Decoder

 General Purpose A/D Converter

Timer

 Timer

 Watchdog Timer

 Real Time Clock

Other

 Clock Generator

 Reset Generator

 PLL

Package

Application

Component St ereo

Application Block

Figure 1.

TQFP128UM

16.00mm  16.00mm  1.20mm

0.4 mm pitch

Not Recommended for

New Designs

2/376

Datasheet

BM94801KUT

TSZ02201-0V2V0E600300-1-2

18.Apr.2014 Rev.003

www.rohm.com

TSZ22111・15・001

ARM946ES Microprocessor Core

◇ 32 Bit RISC Processor

◇ Operating Frequency: 96 MHz (118 DMIPS)

◇ 8 kByte Cache

4 kByte Data Cache

4 kByte Instruction Cache

SDRAM

◇ 16 MBits

◇ SDRAM with built-in MSM56V16160K from LAPIS Semicon ductor

◇ 2 Bank x 524,288 Word x 16 Bit

Initial Program ROM

◇ ITCM ROM Size: 2 kByte (512 Word x 32 Bit)

◇ Boot Program

◇ No Wait Access

REMAP

◇ Remapping can be impl emented by writing to internal r egisters.

SHADOW SRAM

◇ RAM Size: 512 Byte (128 Word x 32 Bit)

◇ No Wait Access

Program SRAM

◇ ITCM RAM Size: 64 kByte (16,384 Word x 32 Bit)

◇ No Wait Access

Data SRAM

◇ DTCM RAM Size: 64 kByte (16,384 Word x 32 Bit)

◇ No Wait Access

SDRAM Controller

◇ Supports SDRAM

◇ Supports 11 Bit row address, 8-bit column address, and 1-bit bank address to SDRA M

AMBA

◇ Multilayer AHB

◇ 32 Bit Data Bus

◇ Arbitrates ARM and DMA access with an arbiter

◇ Allows parallel access according to different master/slave combinations

Interrupt Controller

◇ 32 IRQ Interrupt Lines

◇ 1 FIQ Interrupt Line

◇ Allows programmable sett ing of interrupt priority levels

◇ Allows setting of 16 vector addresses

DMA Controller

◇ Up to 2 DMA Channels

◇ Channel FIFO Depth Up to 16 Bytes

◇ Allows programmable setting of transfer data width in the range of 1 byte to 4 b ytes

◇ Allows programmable setting of channel priority levels

◇ Maximum Block Length Up to 4,095 Words

◇ Includes 12 handshake interfaces available for assignment to channels with software

◇ Supports multiblock transfers

◇ Connects the master board to system bus

GPIO

◇ GPIO0 (32 pins), GPIO1 (32 pins)

◇ Supports a maximum of 64 I/O pins

◇ Supports the interrupt function

◇ Supports external level-sensitive interrupt

Not Recommended for

New Designs

3/376

Datasheet

BM94801KUT

TSZ02201-0V2V0E600300-1-2

18.Apr.2014 Rev.003

www.rohm.com

TSZ22111・15・001

Pin Controller

◇ Controls connection settings bet ween pins and b locks

Block Number of GPIO Pins

Dedicated GPIO Pins 20

Combined GPIO Pins 44

One Line of 2-Ch I2S Output 5

Two Lines of 2-Ch I2S Input 6

SDIO I/F 8

SPI Master 4

SPI Slave 4

Quad SPI I/F 6

2-Ch UART 6

2-Ch I2C Master/Slave 4

RCR 1

USB 2.0 Dual Role (Host/Device) Controll er

◇ USB 2.0 Compatible

◇ Bit Rate: High Speed (480 Mbps) / Full Speed (12 Mbps)

◇ Configurable for up to five transmit endpoint FIFOs and four receive endpoint F IFOs (including endpoint 0)

◇ Each endpoint FIFO supports bulk transfer, interrupt transfer, and isochron ous transfer.

◇ 2048-Byte RAM for Endpoint FIFO

SD I/F

◇ Supports SDXC, SDHC, and SD cards

◇ Provide access to SD card in SD Bus mode

◇ Allows control from the AMBA-AHB bus

◇ Includes 512 byte data transmit/receive FIFOs

Quad SPI I/F

◇ Supports quad serial flash ROM

◇ Supports serial flash ROM address up to 24 bits

◇ Allows the setting of control registers from the AMBA-AHB bus

◇ Allows direct access from the memory map of the AMBA-AHB bus to serial flash ROM

◇ Includes 32 byte data transmit/receive FIFOs

SSI Master

◇ FIFO Depth Up to 16 Words and FIFO Data Width Up to 16 Bits

◇ Selectable Data Size from 4 Bits to 16 Bits

◇ Serial protocol supports SPI from Motorola

◇ Includes DMA handshake interface

SSI Slave

◇ FIFO Depth Up to 16 Words and FIFO Data Width Up to 16 Bits

◇ Selectable Data Size from 4 Bits to 16 Bits

◇ Serial protocol supports SPI from Motorola

◇ Includes DMA handshake interface

I2C I/F (Master/Slave)

◇ 2 Ch I2C Serial Interface

◇ Supports two speed modes

- Standard Mode (100 Kb/s)

- Fast Mode (400 Kb/s)

◇ Supports I2C Master and Slave operation

◇ Allows 7 and 10 bit addr ess generation

◇ Has built-in 32 stage transmit and receive FIFOs

◇ Includes DMA handshake interface

Not Recommended for

New Designs

4/376

Datasheet

BM94801KUT

TSZ02201-0V2V0E600300-1-2

18.Apr.2014 Rev.003

www.rohm.com

TSZ22111・15・001

UART I/F

◇ IS16550-Based

◇ Allows various baud rate settings with software (up to 6 Mbps)

◇ No Support for IrDA

◇ FIFO DepthUp to 32 Words and FIFO Data Width Up to 8 Bits

◇ Incorporates a function to invert output

◇ Includes DMA handshake interface

I2S Input I/F

◇ Two Lines of 2-Ch Digital Audio Input

◇ I2S, EIAJ Format

◇ 16-Bit Data

◇ Selectable Bit Clock from 32 fs, 48 fs, and 64 fs

◇ Selectable Input Sample Rate from 32 kHz, 44.1 kHz, and 48 kHz

◇ One Line of Internal Input from the CD Servo Controller

◇ Maximum Input Rate Up to 4

◇ Supports detection of CD-DA link

◇ Supports detection of CD-ROM sync

◇ Supports CD-ROM data descrambling

◇ Acquires Sub-Q data

◇ Acquires CD-Text data

◇ Built-in DMA

I2S Output I/F

◇ 2.1-Ch Digital Audio Output x 1

◇ 2 Channels from Decoder, 1 Channel from ADC

◇ I2S, EIAJ Format

◇ Selectable Output Sample Rate from 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,176.4 kHz, and 192 kHz

◇ Selectable Data Width from 16, 24, and 32 bits

◇ 64 fs Bit Clock

◇ Supports pitch control (0.5 to 2.0 in 25 steps)

CD Servo Controller

◇ Supports rotation speed of CD up to 4

◇ Built-in Preservo-Amplifier with Power Save Mode, Which Supports Playback of CD-RW

◇ Allows independent offset adjustment of AC, BD, E, and F amplifiers

◇ Built-in Auto-Tracking and Focus Adjustment Function

◇ Built in PLL and CLV with a Wide Lock Range

◇ Built-in Asymmetry Correction Function

CD-ROM Decoder

◇ Supports Mode1, Mode2 form1, and Mode2 form2

◇ Supports ECC and EDC

◇ Built-in DMA

General Purpose A/D Converter

◇ 10-Bit SAR ADC, 8 Ch ADC

◇ Maximum Frequency for A/D Conversion Up to 736 kHz (for 1 Ch Converter)

Timer

◇ Supports five independent programmable timer functions

◇ Each timer supports time width up to 32 bits

◇ Each timer supports independent interrupt signal

W atchdog T i mer

◇ Composed of a counter having a set c ycle to monitor the occurrence of timeout event

◇ Counter Width Up to 32 Bits

◇ The counter counts down from the set value and sets timeout occurrence when it reaches zero

Real T ime Clock

◇ 32 Bit Programmable Timer

◇ Supports interrupt signals

◇ External 32.768 kHz Crystal Oscillator

(External 32.768 kHz X'tal)

Not Recommended for

New Designs

5/376

Datasheet

BM94801KUT

TSZ02201-0V2V0E600300-1-2

18.Apr.2014 Rev.003

www.rohm.com

TSZ22111・15・001

Remote Controller Receiver (RCR)

◇ Converts infrared remote control signal to code

◇ Compatible with the signal format of the Association for Electric Home Appliances

Clock Generator

◇ Supplies clocks to individual internal blocks

◇ Allows on/off control of clocks to individual blocks

◇ Generates master audio clocks

◇ Supports Power-Down Mode

Reset Generator

◇ Generates a pulse to be supplied to individual blocks

PLL

◇ Generates 192 MHz clock used to generate system clocks

◇ Generates 135.4752 MHz and 147.456 MHz clocks used to generate aud io clocks

Power Supply Voltage

◇ I/O Power Supply Voltage: 3.3V (3.0 to 3.5V)

◇ Analog Power Supply Voltage: 3.3V (3.0 to 3.5V)

(used for SDRAM, CD servo, and USB)

◇ Digital Core Power Supply Voltage: 1.55V (1.5 to 1.6V)

(used for digital core and ADC)

Not Recommended for

New Designs

6/376

Datasheet

BM94801KUT

TSZ02201-0V2V0E600300-1-2

18.Apr.2014 Rev.003

www.rohm.com

TSZ22111・15・001

Pin Description

Pin Assignment

RESETX

SD_WP

DVDDIO

SD_DAT0

SD_CLK

SD_CMD

SD_DAT3

VDDQ

GPIO1

GPIO2

DVDD_M1

VSSQ

SVDD

SVSS

DVSS

VSSQ

GPIO11

DVDD_M2

FL_CS

DVSS

DATAO2

FL_DAT2

VSS

VDD

DATAO1

FL_DAT1

FL_DAT3

FL_CLK

MCLKO1

DVDDIO

BCKO1

FL_DAT0

LRCKO1

SD_DAT1

SD_DAT2

GPIO0

GPIO12

AVDDC

GPIO10

SD_CON

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

MSCS

MSDI

SSCS

SSDI

SSCLK

SSDO

GPIO4

GPIO5

MSDO

GPIO3

GPIO6

MSCLK

20

21

22

23

24

25

26

27

28

29

30

31

32

SCL0

GPIO8

JTAG TDI

JTAG TDO

CLK88

JTAG TCK

JTAG TMS

JTAG TRST

DVSS

GPIO7

SDA0

GPIO9

77

76

75

74

73

72

71

70

69

68

67

66

65

Figure 2. Pin Assignment Diagram

Not Recommended for

New Designs

7/376

Datasheet

BM94801KUT

TSZ02201-0V2V0E600300-1-2

18.Apr.2014 Rev.003

www.rohm.com

TSZ22111・15・001

Pin Description

No. Block Pin Name I/O Function

1 RESET RESETX I H: Release RESET, L: RESET

2 SDIO SD_WP I SD Card I/F WP Detect

3 POWER DVDDIO - VDD (3V)

4 SDIO SD_CON I SD Card I/F Connection Detect

5 SDIO SD_DAT1 I/O SD Card I/F Data I/O (1)

6 SDIO SD_DAT0 I/O SD Card I/F Data I/O (0)

7 SDIO SD_CLK O SD Card I/F Clock Output

8 SDIO SD_CMD O SD Card I/F Command Output

9 SDIO SD_DAT3 I/O SD Card I/F Data I/O (3)

10 SDIO SD_DAT2 I/O SD Card I/F Data I/O (2)

11 POWER VDDQ - SDRAM Power Supply (VDD1)

12 POWER VSSQ - SDRAM Ground

13 GPIO GPIO0 I/O GPIO I/O (0)

14 GPIO GPIO1 I/O GPIO I/O (1)

15 GPIO GPIO2 I/O GPIO I/O (2)

16 POWER SVSS - SDRAM Ground

17 POWER SVDD - SDRAM Power Supply (VDD1)

18 POWER DVDD - VDD (1.5V)

19 POWER DVSS - Ground

20 POWER VSSQ - SDRAM Ground

21 Master SIO MSCS O SIO Master Chip Select Output

22 Master SIO MSDI I SIO Master Data Input

23 Master SIO MSCLK O SIO Master Clock Output

24 Master SIO MSDO O SIO Master Data Output

25 Slave SIO SSCS I SIO Slave Chip Select Input

26 Slave SIO SSDI I SIO Slave Data Input

27 Slave SIO SSCLK I SIO Slave Clock Input

28 Slave SIO SSDO O SIO Slave Data Output

29 GPIO GPIO3 I/O GPIO I/O (3)

30 GPIO GPIO4 I/O GPIO I/O (4)

31 GPIO GPIO5 I/O GPIO I/O (5)

32 GPIO GPIO6 I/O GPIO I/O (6)

33 POWER VDD_ADC - ADC Power Supply (1.5V)

34 ADC ADIN0 I ADC Analog Input (0)

35 ADC ADIN1 I ADC Analog Input (1)

36 ADC ADIN2 I ADC Analog Input (2)

37 ADC ADIN3 I ADC Analog Input (3)

38 ADC ADIN4 I ADC Analog Input (4)

39 ADC ADIN5 I ADC Analog Input (5)

40 ADC ADIN6 I ADC Analog Input (6)

41 ADC ADIN7 I ADC Analog Input (7)

42 POWER VSS_ADC - ADC Ground

43 CDDSP ANA_MONI0 O Input & Analog Monitor Output

44 CDDSP ANA_MONI1 O Input & Analog Monitor Output

45 CDDSP RFI I RF Output Capacitance Coupling Re-Input

46 CDDSP EQO O Output after RF Equalizer

47 CDDSP AD_MONI0 O Input & Monitor Signal Output

48 CDDSP AD_MONI1 O Input & Monitor Signal Output

49 POWER AVDD1 - RF Analog Power Supply

50 CDDSP AC I A



C Voltage Input

51 CDDSP BD I B



D Voltage Input

52 CDDSP VBIAS O Bias Level

53 POWER AGND1 - RF Analog Ground

54 CDDSP E I E Voltage Input

55 CDDSP F I F Voltage Input

56 CDDSP PD I APC Photo Detector Input

57 CDDSP LD O APC Laser Drive Output

58 CDDSP ASY I Asymmetric Correction

59 CDDSP PCO O PLL PCO Output

60 CDDSP FCO O PLL FCO-DAC Output

61 CDDSP FDOUT O Focus Drive Output

62 CDDSP TDOUT O Tracking Drive Output

63 CDDSP SDOUT O Sled Drive Output

64 CDDSP CLVOUT O CLV Drive Output

65 CDDSP CLK88 O Clock Output for Driver IC

Not Recommended for

New Designs

8/376

Datasheet

BM94801KUT

TSZ02201-0V2V0E600300-1-2

18.Apr.2014 Rev.003

www.rohm.com

TSZ22111・15・001

Pin Description - continued

No Block Pin Name I/O Function

66 JT AG JTAG TDO O JT AG TDO

67 JT AG JTAG TCK I JTAG TCK

68 JT AG JT AG TMS I JTAG TMS

69 JT AG JTAG TDI I JT AG TDI

70 JT AG JTAG TRST I JTAG TRST

71 POWER DVSS - Ground

72 GPIO GPIO7 I/O GPIO I/O (7)

73 GPIO GPIO8 I/O GPIO I/O (8)

74 GPIO GPIO9 I/O GPIO I/O (9)

75 I2C SCL0 I/O I

2

C clock I/O (0)

76 I2C SDA0 I/O I

2

C data I/O (0)

77 I2S OUT MCLKO1 O Digital Audio Master Clock Output (1)

78 POWER DVDDIO - VDD (3V)

79 POWER SVDD - SDRAM Power Supply (VDD1)

80 POWER SVSS - SDRAM Ground

81 I2S OUT DATAO1 O Digital Audio Data Output (1)

82 I2S OUT BCKO1 O Digital Audio Bit Clock Output (1)

83 I2S OUT LRCKO1 O Digital Audio Channel Clock Output (1)

84 I2S OUT DATAO2 O Digital Audio Data Output (2)

85 POWER DVSS - Ground

86 FLASH FL_DAT2 I/O Serial Flash ROM I/F Data I/O (2)

87 FLASH FL_DAT1 I/O Serial Flash ROM I/F Data I/O (1)

88 FLASH FL_CS O Serial Flash ROM I/F Command Output

89 FLASH FL_DAT3 I/O Serial Flash ROM I/F Data I/O (3)

90 FLASH FL_CLK O Serial fFash ROM I/F Clock Output

91 FLASH FL_DAT0 I/O Serial Flash ROM I/F Data I/O (0)

92 POWER DVDD - VDD (1.5V)

93 GPIO GPIO10 I/O GPIO I/O (10)

94 GPIO GPIO11 I/O GPIO I/O (11)

95 GPIO GPIO12 I/O GPIO I/O (12)

96 POWER AVDDC - USB Power Supply (VDD1)

97 USB USB_DM1 I/O USB D- I/O

98 USB USB_DP1 I/O USB D+ I/O

99 POWER AVSSC - USB Ground

100 USB REXTI I

Pin is connected to USB reference voltage and AVSSC pin via a

12.3-k USB bias resistor. Connect a resistor of 12.3-k±1% to

GND. Only using USB Full Speed, the resistor of 12.3-k±5% is

approvable on the USB media playability check.

101 UART UART0_RXD I UART0 Receive Data

102 UART UART0_TXD O UART0 Transmit Data

103 UART UART0_RTS O UART0 Transfer Request

104 UART UART0_CTS I UART0 Clear Request

105 GPIO GPIO13 I/O GPIO I/O (13)

106 GPIO GPIO14 I/O GPIO I/O (14)

107 GPIO GPIO15 I/O GPIO I/O (15)

108 GPIO GPIO16 I/O GPIO I/O (16)

109 GPIO GPIO17 I/O GPIO I/O (17)

110 I2S IN LRCKI1 I Digital Audio Channel Clock Input (1)

111 I2S IN BCKI1 I Digital Audio Bit Clock Input (1)

112 I2S IN DATAI1 I Digital Adio Data Input (1)

113 I2S IN LRCKI2 I Digital Audio Channel Clock Input (2)

114 I2S IN BCKI2 I Digital Audio Bit Clock Input (2)

115 I2S IN DATAI2 I Digital Audio Data Input (2)

116 GPIO GPIO18 I/O GPIO I/O (18)

117 GPIO GPIO19 I/O GPIO I/O (19)

118 I2C SCL1 I/O I

2

C Clock I/O (1)

119 I2C SDA1 I/O I

2

C Data I/O (1)

120 RCR RCR I Remote Controller Signal Input

121 UART UART1_RXD I UART1 Receive Data

122 UART UART1_TXD O UART1 Transmit Data

123 POWER DVSS - Ground

124 CLOCK XIN_32K I X'tal (32.768 KHz) Connection Input

125 CLOCK XOUT_32K O X'tal (32.768KHz) Connectio n Output

126 TEST TMODE I Test Mode Terminal: This pin is connected to GND.

127 CLOCK XIN_PLL I X'tal (16.9344 M Hz) Connection Input

128 CLOCK XOUT_PLL O X'tal (16.9344MHz) Connection Output

Not Recommended for

New Designs

9/376

Datasheet

BM94801KUT

TSZ02201-0V2V0E600300-1-2

18.Apr.2014 Rev.003

www.rohm.com

TSZ22111・15・001

Electrical Characteristics

Absolute Maximum Ratings (Ta25C)

Parameter Symbol Rating Unit Remark

Input Voltage (Analog, I/O) VDD1MAX



0.3 to +4.5 V DVDDIO, VDDQ, SVDD, AVDD1, AVDDC

Input Voltage (Core) VDD2MAX



0.3 to +2.1 V DVDD, VDD_ ADC

Input Voltage VIN 0.3 to VDD1



0.3 V

Storage Temperature Range Tstg



55 to +125 C

Operating Temperature Range Topr



40 to +75 CUsing USB High Speed

Operating Temperature Range Topr



40 to +85 CUsing USB Full Speed

Power Dissipation

(N

o

t

e

1)

Pd1 1.96 W

(Note 1) Derating is done in 19.6 mW/°C for operation above Ta≧25 °C Mount on 2-layer 114.3mm x 76.2mm x 1.6mmt board

(bottom side copper layer 74.2mm x 74.2mm)

Caution: Operating the IC ov er the ab solute max imum ratings may damage the IC. The damage can either be a shor t cir cuit between pins o r an

open circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures such as adding a fuse, in

case the IC is operated over the absolute maximum ratings.

Recommended Operating Conditions (Ta=25°C)

Parameter Symbol Rating Unit Remark

Input Voltage (Analog, I/O) VDD1 3.0 to 3.5 V DVDDIO, VDDQ, SVDD, AVDD1, AVDDC

Input Voltage (Core) VDD2 1.55 to 1.65 V DVDD, VDD_ADC (Using USB High Speed)

Input Voltage (Core) VDD2 1.5 to 1.65 V DVDD, VDD_ADC (Using USB Full Speed)

Electrical Characteristics

(Unless otherwise noted, Ta25C, VDD13.3V, VDD21.55V, VSSQSVSSDVSSVSS_ADCAGND1AVSSC0V, XIN_PLL16.9344

MHz, XIN_32K32.768 kHz, REXTI PIN’s Eeternal Resistance=12.3k±1% (Note 8))

Parameter Symbol Rating Unit Conditions

Suitable Pin

Min Typ Max

Operating Current Consumption

(VDD1) IDDHS1 － 110 180 mA Using USB High Speed

Operating Current Consumption

(VDD1) IDDFS1 － 60 130 mA Using USB Full Speed

Operating Current Consumption

(VDD2) IDD2 － 100 200 mA

Input “H” Voltage VIH V

DD1 * 0.7 －VDD1 V

(Note 1)

Input “L” Voltage VIL DVSS －VDD1*0.3 V (Note 1)

Output “H” Voltage 1 VOH1 V

DD1 - 0.4 －VDD1 V

IOH  1.6mA (Note 2)

Output “L” Voltage 1 VOL1 0 －0.4 V IOL  1.6mA (Note 2)

Output “L” Voltage 2 VOL2 0 －0.4 V IOL  3.6mA (Note 3)

Output “H” Voltage 3 VOH3 V

DD1 - 0.4 －VDD1 V

IOH  0.6mA (Note 4)

Output “L” Voltage 3 VOL3 0 －0.4 V IOL  0.6mA (Note 4)

Output “H” Voltage 4 VOH4 V

DD1 - 1.0 －VDD1 V

IOH  0.6mA (Note 5)

Output “L” Voltage 4 VOL4 0 －1.0 V IOL  0.6mA (Note 5)

Idle Pull-Up Resistance RPU

_

ID 0.9 - 1.575 k

(N

o

t

e

7

)

RX Pull-Up Resistance RPU

_

RX 1.425 - 3.09 k

(N

o

t

e

7

)

Pull-Down Resistance RPD 14.25 - 24.8 k

(N

o

t

e

6)

HS Idle Voltage VHSOI -10 5 25 mV

(N

o

t

e

6)

HS High Voltage VHSOH 360 - 440 mV

(N

o

t

e

6)

HS Low Voltage VHSOL -10 5 25 mV

(N

o

t

e

6)

HS RX Differential Input

Sensitivity VHSSQ 100 - - mV (Note 6)

HS RX Differential Input Range VHSCM -50 - 600 mV

(N

o

t

e

6)

HS Disconnect Judgment

Voltage VHSDSC 525 - 625 mV (Note 6)

Chirp J Voltage VCHIRPJ 700 - 1100 mV Measured at 45 Output Termination (Note 6)

Chirp K Voltage VCHIRPK -900 - -500 mV

(N

o

t

e

6)

FS High Output Impedance ZFDRH - 45 - 

(N

o

t

e

6)

FS Low Output Impedance ZFDRL - 45 - 

(N

o

t

e

6)

Not Recommended for

New Designs

10/376

Datasheet

BM94801KUT

TSZ02201-0V2V0E600300-1-2

18.Apr.2014 Rev.003

www.rohm.com

TSZ22111・15・001

Electrical Characteristics – continued

Parameter Symbol Rating Unit Conditions

Suitable Pin

Min. Typ. Max.

FS High Voltage VFOH 2.8 - 3.6 V Measured when pin is pulled down to AVSSC

using 15 k resistor (Note 6)

FS Low Voltage VFOL 0 - 0.3 V Measured when pin is pulled up to AVDDC

using 1.5 k resistor (Note 6)

FS RX Differential Input Range VFLCM 0.8 - 2.5 V

(N

o

t

e

6)

FS RX Differential Input

Sensitivity VFLSNS - - 200 mV (Note 6)

Input “H” Voltage VHUSB 2 - AVDDC V

(N

o

t

e

6)

Input “L” Voltage VILUSB AVSSC - 0.8 V

(N

o

t

e

6)

<ADC>

A/D Conversion Frequency fADCONV - - 736 kHz FADCONV



16.9344MHz/23

Analog Input Voltage Range VAIN ±0.55 ±0.62 ±0.69 V VDD

_

ADC



Within 1.55V 1%

Analog Input Voltage Range VAIN ±0.57 ±0.64 ±0.71 V VDD

_

ADC



Within 1.6V  1%

Differential Non-Linearity DNL - - 5 LSB

Integral Non-Linearity INL - -



5 LSB

(Note 1) 1,2,4 to10,13 to15,21to 32,67 to 70,72 to 77,81 to 84,86 to 91,93 to 95,101 to122,124,127 pins

(Note 2) 13 to15,21 to 32,65 to 66,72 to 74,77,81 to 84,86 to 91,93 to 95,101 to 117,120 to122 pins

(Note 3) 75,76,118,119 pins

(Note 4) 4-10, pin

(Note 5) 125,128 pins

(Note 6) 97,98 pins

(Note 7) 98 pin

(Note 8) Only using USB Full Speed, the resistor of 12.3-k±5% is approvable on the USB media playability check.

Not Recommended for

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18.Apr.2014 Rev.003

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TSZ22111・15・001

Electrical Characteristics – continued

(Unless otherwise noted, Ta25C, VDD13.3V, VDD21.55V, VSSQSVSSDVSSVSS_ADCAGND1AVSSC0V, XIN_PLL16.9344

MHz, XIN_32K32.768 kHz, RL10k, VCReference)

Parameter Symbol

Rating Unit Conditions

Suitable Pin

Min Typ Max

Maximum Oscillation

Frequency fVCOH 4.6 6.5 - MHz 1/4 of FLAG1 and VCO Output

Minimum Oscillation Frequency fVCOL - 1.1 1.7 MHz 1/4 of FLAG1 and VCO Output

Offset Voltage VFCOF -50 - +50 mV FCO

Maximum Output Voltage VFCH 0.2 0.5 - V FCO

Minimum Output Voltage VFCL -



0.5



0.2 V FCO

<PCO>

Output “L” Voltage VPCH -



1.0



0.6 V PCO

Output “H” Voltage VPCL 0.6 1.0 - V PCO

Threshold Voltage VEFM 200 - +200 mV RFI, ANA_MONI0, FLAG2

Offset Voltage VADOF 140 - +140 mV ANA_MONI0, ANA_MONI1

Maximum Conversion Voltage VADH 1.0 1.2 +1.4 V ANA_MONI0, ANA_MONI1

Minimum Conversion Voltage VADL 1.4



1.2



1.0 V ANA_MONI0, ANA_MONI1

Offset Voltage VDAOF -80 - +80 mV FDOUT, TDOUT, SDOUT, CLVOUT

Maximum Output Voltage VDAH 0.8 1.2 - V FDOUT, TDOUT, SDOUT, CLVOUT

Minimum Output Voltage VDAL - -1.2 -0.8 V FDOUT, TDOUT, SDOUT, CLVOUT

Maximum Output Current IBO -



1.5 - mA VBIAS, BIAS Fluctuation: 200mV or less

Offset Voltage VRFOF - 0 - mV AC ,BD, EQO

Maximum Output Voltage VRFH 1.0 1.2 - V AC, BD, EQO

Minimum Output Voltage VRFL -



1.3



1.1 V AC, BD, EQO

Offset Voltage VFEOF - 0 - mV AC, BD, ANA_MONI0, ANA_MONI1

Maximum Output Voltage VFEH 1.0 1.4 - V AC, BD, ANA_MONI0 ,ANA_MONI1

Minimum Output Voltage VFEL -



1.4



1.0 V AC, BD, ANA_MONI0, ANA_MONI1

Offset Voltage VTEOF - 70 - mV E, F, ANA_MONI0, ANA_MONI1

Maximum Output Voltage VTEH 1.0 1.4 - V E, F, ANA_MONI0, ANA_MONI1

Minimum Output Voltage VTEL -



1.4



1.0 V E, F, ANA_MONI0, ANA_MONI1

Offset Voltage VASYOF - 0 - mV ASY



VC, RFI, ANA_MONI0 (ASY_TEST)

Maximum Output Voltage VASYH 1.1 1.4 - V ASY, RFI, ANA_MONI0 (ASY_TEST)

Minimum Output Voltage VASYL -



1.4



1.1 V ASY, RFI, ANA_MONI0 (ASY_TEST)

Output Voltage 1 VAPC1 2.4 2.8 - V

PD



”H”, LD, ANA_MONI0 (APCREF)

Output Voltage 2 VAPC2 - 0.1 0.5 V

PD



”L”, LD, ANA_MONI0 (APCREF)

Maximum Reference Voltage VAPCH - 220 - mV PD, LD, ANA_MONI0 (APCREF)

Minimum Reference Voltage VAPCL - 145 - mV PD, LD, ANA_MONI0 (APCREF)

Not Recommended for

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18.Apr.2014 Rev.003

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TSZ22111・15・001

Application Information

Clock and Reset

Clock

Clock Name I/O Function Remarks

XIN_32K I X'tal (32.768KHz) Connection Input Termin al

XOUT_32K O X'tal (32.768 KHz) Connection Terminal

XIN_PLL I X'tal (16.9344 MHz) Connection Input Terminal

XOUT_PLL O X'tal (16.9344 MHz) Connection Terminal

Reset

Signal Name I/O Function Remarks

RESETX I System Reset Input Terminal

Release reset signal (RESETX = H) 300 us after oscillation of 32.768KHz and 16.9344MHz clock inputs have become

stable. (See Figure 3)

Figure 3.Reset Timing

Item Symbol Rating Unit Remarks

Min Typ Max

Reset L Interval tRSTX 300 - - µs

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1. AMBA

1.1. Features

 Consists of multilayer AHB bus matrix

 Includes three AHB buses, which use ARM9, DMAC, and the DMAC of individual peripherals as bus masters

 Includes APB-to-AHB bridge with the bus master arbitration function

 32-Bit Data Bus

 Arbitrates bus masters with individual peripherals

 Allows parallel access according to different master/slave combinatio ns

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1.2. Description

1.2.1. Block Diagram

The following section shows the block diagram of a system bus.

Figure 4.

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1.2.2. Memory Map

The following section sho ws the hardware memory map.

START-ADR END-ADR Master Name Size

(Bytes)

ARM DMAC

(Note) PDMAC

$00000000 $000007FF  × × Instruction_ROM 2k

$00008000 $00017FFF  × × Instruction_RAM 64k

$10000000 $1000FFFF  ×  WORK_RAM 64k

AHB

$20000000 $20FFFFFF  × × Serial Fl ash ROM Direct 16M

$70000000 $700001FF  × × SHADOW RAM 512

$80000000 $801FFFFF    SDRAM Direct 2M

APB

$D0000000 $D00FFFFF  × × WDT

$D0100000 $D01FFFFF  × × Timer

$D0200000 $D02FFFFF  × × Clock/Power Controller

$D0300000 $D03FFFFF  × × PIN Controller

$D0400000 $D04FFFFF  × × RTC

$D0500000 $D05FFFFF   × UART0

$D0600000 $D06FFFFF   × UART1

$D0700000 $D07FFFFF   × SSI Master

$D0800000 $D08FFFFF   × SSI Slave

$D0900000 $D09FFFFF   × I2C0

$D0A00000 $D0A0FFFF   × I2C1

$D0B00000 $D0BFFFFF  × × I2S OUT

$D0C00000 $D0CFFFFF  × × CD-DSP

$D0D00000 $D0DFFFFF  × × ADC

$D0E00000 $D0EFFFFF  × × REMAP

$D0F00000 $D0FFFFFF  × × RCR

$D1000000 $D10FFFFF  × × GPIO0

$D1100000 $D11FFFFF  × × GPIO1

$D1200000 $D12FFFFF  × × RESETGEN

$D1300000 $D13FFFFF  × × I2SIN/CD-ROM

AHB

$E0000000 $E00FFFFF  × × DMAC

$E0200000 $E02FFFFF  × × (Reserved)

$F0000000 $F00FFFFF  × × SDRAM Controller Setting

$F0100000 $F01FFFFF  × × Quad SPI Controller Setting

$F0200000 $F02FFFFF  × × SDIO Controller

$F8000000 $F80FFFFF  × × Mentor USB Controller

$F8100000 $F81FEFFF  × × USB Connect Detector

$FFF00000 $FFFFFFFF  × × Interrupt Controller (ICTL)

(Note) DMAC Access Size is 32 bits.

1.2.3. ARM AHB

ARM AHB is a single-master AHB, which uses ARM9 as bus master.

1.2.4. DMAC AHB

DMAC AHB is a single-master AHB, which uses DMAC as bus master.

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TSZ22111・15・001

1.2.5. PDMAC AHB

PDMAC AHB is a multi-master AHB, which uses PDMAC and the DMAC of indiv idual peripherals as bus masters.

To access individual bus masters, the arbite r selects the b us master of PDMAC AHB to allow access to the SDRAM or

ARM9 DTCM space.

The following table lists priority levels for the arbiter.

Priority Level Block

1 (High) I2S Output

2 USB

3 SDIO

4 I2S Input

5 CD-ROM

6 (Low) (Reserved)

1.2.6. APB

An AHB-to-APB bridge circuit converts from AHB to APB format.

APB allows access from ARM9 and DMA C to APB peripherals.

MUX

If individual AHBs have simultaneous access to the same perip heral, MUX selects a single AHB with a higher priority level

and connects the AHB bus to a peripheral bus.

All AHBs, except the selected AHB, enter wait state.

The following table lists the levels of priority for AHB selecti on.

Priority Level AHB

1 (High) PDMAC AHB

2 DMAC AHB

3 (Low) ARM9 AHB

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1.3. I/O Signals

Pin Name I/O Function Destination

clk_i In System Clock CLKCTR

ramclk_i In RAM Clock CLKCTR

nreset_i In System Reset RSTGEN

hbusreq_marm_i In AHB HBUSREQ Master ARM9

htrans_marm_i In AHB HTRANS Master ARM9

hsize_marm_i In AHB HSIZE Master ARM9

hburst_marm_i In AHB HBURST Master ARM9

hwdata_marm_i In AHB HWRITE Master ARM9

haddr_marm_i In AHB HADDR Master ARM9

hwrite_marm_i In AHB HWDATA Master ARM9

hgrant_marm_o Out AHB GRANT Master ARM9

hready_marm_o Out AHB HREADY Master ARM9

hrdata_marm_o Out AHB HRDATA Master ARM9

hresp_marm_o Out AHB HRESPM Master ARM9

hbusreq_mdmac_i In DMAC AHB HBUSREQ Master DMAC

htrans_mdmac_i In DMAC AHB HTRANS Master DMAC

hsize_mdmac_i In DMAC AHB HSIZE Master DMAC

hburst_mdmac_i In DMAC AHB HBURST Master DMAC

hwdata_mdmac_i In DMAC AHB HWRITE Master DMAC

haddr_mdmac_i In DMAC AHB HADDR Master DMAC

hwrite_mdmac_i In DMAC AHB HW DATA Master DMAC

hgrant_mdmac_o Out DMAC AHB GRANT Master DMAC

hready_mdmac_o Out DMAC AHB HREADY Master DMAC

hrdata_mdmac_o Out DMAC AHB HRDATA Master DMAC

hresp_mdmac_o Out DMAC AHB HRESPM Master DMAC

hbusreq_mX_i In Peri DMAC AHB HBUSREQ Master PDMAC

htrans_ mX _i In Peri DMAC AHB HTRANS Master PDMAC

hsize_ mX _i In Peri DMAC AHB HSIZE Master PDMAC

hburst_ mX _i In Peri DMAC AHB HBURST Master PDMAC

hwdata_ mX _i In Peri DMAC AHB HWRITE Master PDMAC

haddr_ mX _i In Peri DMAC AHB HADDR Master PDMAC

hwrite_ mX _i In Peri DMAC AHB HWDATA Master PDMAC

hgrant_ mX _o Out Peri DMAC AHB GRANT Master PDMAC

hready_ mX _o Out Peri DMAC AHB HREADY Master PDMAC

hrdata_ mX _o Out Peri DMAC AHB HRDATA Master PDMAC

hresp_ mX _o Out Peri DMAC AHB HRESPM Master PDMAC

hsel_marm_ setc_o Out AHB HSEL Slave AHB

htrans_setc_o Out AHB HTRANS Slave AHB

hwrite_setc_o Out AHB HWRITE DATA Slave AHB

hsize_setc_o Out AHB HSIZE Slave AHB

haddr_setc_o Out AHB HADDR Slave AHB

hwdata_setc_o Out AHB HWDATA Slave AHB

hready_marm_o Out AHB HREADYI Slave AHB

hready_XXX_i In AHB HREADY Out Slave AHB

hrdata_XXX_i In AHB HRDATA Slave AHB

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I/O Signals – continued

Pin Name I/O Function Destination

hresp_XXX_i In AHB RESPONSE Slave AHB

hsel_pdmac_dtcm_o Out AHB HSEL Sla v e DTCM

htrans_pdmac_o Out AHB HTRANS Slave DTCM

hwrite_pdmac_o Out AHB HWRIT E DATA Slave DTCM

hsize_pdmac_o Out AHB HSIZE Slave DTCM

haddr_pdmac_o Out AHB HADDR Slave DTCM

hwdata_pdmac_o Out AHB HWDATA Slave DTCM

hburst_pdmac_o Out AHB HREADYI Slave DT CM

hready_sdtcm_i In AHB HREADY Out Slave DTCM

hrdata_sdtcm_i In AHB HRDATA Slave DTCM

hresp_sdtcm_i In AHB RESPONCE Slave DTCM

psel_x Out APB Sel APB

paddr_sapb_o Out APB Addr APB

penable_sapb_o Out APB Enable APB

pwrite_sapb_o Out APB Write Enable APB

pwdata_sapb_o Out APB Write Data APB

prdata_d0X_i In APB Read D ata APB

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2. REMAP

2.1. Features

 Controls remapping (from boot memory mapping to normal memory mapping) after completion of initialization

sequence

 Generates remap control signals by writing data to internal register

 Connects remap control signals to AHB address decoder

 Supports APB slave interface

 Little-Endian System

2.2. Description

2.2.1. Outline Block Diagram

pclk

presetn

psel

paddr[7:0]

pwdata[31:0]

pwrite

penable

Remap

remap_n

prdata[31:0]

Figure 5. Remap Block

2.2.2. Description

For power-on reset, address 0x0000 is assigned to a program ROM for initialization. This is called boot memory mapping.

Setting the remap co nt rol regi st er out puts a remap s ign al to t he AHB address recorder after completio n of init i aliz ation and,

subsequently, reassigns the address 0x0000 to a shadow RAM. This is called normal memory mapping.

2.3. I/O Signals

Pin Name I/O Function Destination

pclk IN APB Clock Clock Gen

present IN APB Reset Reset Gen

psel IN APB Peripheral Select Signal APB

paddr [7:0] IN APB Address APB

pwdata [31:0] IN APB Write Data APB

pwrite IN APB Write Signal APB

penable IN APB Enable Signal APB

prdata [31:0] OUT APB Read Data APB

remap_n OUT Remap Signal AHB

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2.4. Register

2.4.1. Memory Map

2.4.2. Register Detail

RemapMode

Remap Setting Regist er

Name Address

Offset Width Reset

RemapMode 0x00 1 bit 0x0

Bits Name Direction Reset Description

0 RemapMode

Mode R/W 0x0

Setting this register to “1” makes remapping execution possible.

0: Boot memory mapping

1: Normal memory mapping

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3. SDRAM Controller

3.1. Feature

 SDRAM is supported.

 Supports 11 bit row address, 8 bit colum n address, and 1 bit bank address to SDRAM

 SDRAM Timing is programmable.

 The SDRAM Auto-Refresh function and Refresh timing can be arbitrarily set.

 Supports Power-Down Mode of SDRAM

3.2. Description

3.2.1. FIFO

The memory controller has four "FIFO addresses" and eight "FIFO data" on the AHB interface side. AHB address for MIU

(Memory Interface Unit) is stored in FIFO address for decoding.

Data written in memory and control i nformati on generat ed during burst t ransfer are st ored in FIFO data. The depth of FI FO

is determined depending on the delay value of SDRAM, which contains the refresh, pre-charge, read latency and write

latency etc.

3.2.2. READ_PIPE/WRITE_PIPE

READ_PIPE consists of flip-flops for memory controller, which are used to safely decode read data from SDRAM.

WRITE_PIPE uses a flip-flop to meet the setup time for writing data to SDRAM.

FFs are inserted in all output signals to SDRAM.

DW_memctl

hclkb

s_wr_data_0 s_wr_data

WRITE_PIPE

by inverted clock

QDQD

s_rd_data_1s_rd_data_2

hclk isdram_

clk

READ_PIPE

CIN

IPAD

CIN

IPAD

sdrc_hclkb_o sdrc_hclk_o

ckinv_sdrchclkb ckinv_sdrchclk

memctl_top

clkgen

SDRAM

QD

Figure 6. READ_PIPE/WRITE_PIPE

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3.2.3. SDRAM

Connection of SDRAM Interface and SDR AM

The pin characteristic in the SDRAM interface is shown in the table below.

SDRAM Interface Pin Characteristic

Pin Name Function Direction

A

ctive State

SDCLK SDRAM Clock Signal O Clock

SDCKE SDRAM Clock Enable Signal O High

CS3 - CS0 External RAM Chip Select OLow

RAS SDRAM Row Address Enabl

e

OLow

CAS SDRAM Column Address Enable O Low

SDWR SDRAM Write Signal O Low

BA1 - BA0 SDRAM Bank Address O Address

M_PRE_BIT SDRAM Pre-Charge Bit (Connected to 10-Bi t Address) O Address

A

DDR22 - ADD R0 SDRAM Addresses O Address

DATA31 - DATA0 SDRAM Data Bus I/O Data

DQM3 - DQM0 SDRAM Data Mask O High

SDRAM Controller's SDRAM Initialization Sequence

Because of the default memory allocation in SDRAM, HW does the SDRAM initialization sequence automatically after

power-on reset. However, SDRAM access should be done after register SCTLR[0] becomes 0.

The flow of the init ialization sequence is shown in the figure below.

(1) After Power On, SDCLK is enabled and NOP state is maintained during t_init.

(2) Pre-charging of all banks is done.

(3) Auto-Refresh operation is done num_int_ref times.

(4) Afterwards, the SDRAM mode register is set.

Moreover, after the initialization sequence ends, writing “1” to register SCTLR[0] can execute the initialization sequence

operation agai n.

Figure 7. SDRAM Initialization Sequence

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About SDRAM Controller's SDRAM Mode Register

The mode register is updated during initialization. Afterwards, mode register update is done by writing ‘1’ to the 9-bit SDRAM

Control Register.

The SDRAM controller can change the CAS latency with SDRAM Timing Register as shown in the figure below. However, it

is necessary to update the mode register when the value of controller’s CAS latency is changed. Data cannot be read

correctly. Only burst length of 4 and sequential burst type are supported. However, data transfer is achie ved by repeating

four bursts and burst stops.

A10A9A8A7A6A5

A

4

A

3

A

2

A

1

A

0

BT

0010

A

6

A

5

A

4

000

001

010

011

100

101

110

111

CAS l atency

Reserved

1

Burst Length

Reserve

d

000 CAS latency

Reserved

2

3

4

Reserved

Figure 8. Definition of Mode Register

SDRAM Controller's SDRAM Command

The SDRAM commands are shown in the table below.

SDRAM Command Truth Table

Function Symbol CKE DQM CS RAS CAS WE

Detect NOP XXHXXX

No Operation NOP XXLHHH

READ READ XXLHLH

WRITE WRITE XXLHLL

Bank Activate

A

CT XXLLHH

Pre-Charge PRE XXLLHL

A

uto-Refresh REF XXLLLH

Mode Register Set MRS XXLLLL

Self Refresh Entry REF LXLLLH

Self Refresh Exit - HXHXXX

Power Down Entry - LXXXXX

Power Down Exit - HXHXXX

Data Write / Output Enable - HLXXXX

Data Write / Output Disable - HHXXXX

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・Read/Write

Read and Write operations are executed through this command.

・Burst Terminate

Inputting the burst stop command during read or write cycle ends burst read or write operation.

・Pre-Charge

Pre-Charge state is executed until operation to a present row address is ended and operation to another row address

begins. The device automatically returns to idle state when Pre-Charge command has finished.

・Auto Refresh

Auto-Refresh command can only be executed when all the banks of the device are in idle state. A specific row address in

all the banks is selected when Auto-Refresh command is inputted and refresh operation is executed. The device

automatically returns to idle state when refresh operation has finished executing.

・Mode Register Set

The value of the mode register is updated through address (A0-A10) when Mode Register Set command is inputted.

Mode Register Set command can only be executed when all banks are in idle or suspend state.

・Self Refresh

Self-Refresh command, like the Auto-Refresh command, can only be executed when all banks of the device are idle.

During operation, the device refresh automatically. Refresh operation need not be executed from outside. After

Self-Refresh operation, the device automatically returns to idle state.

・Power Down Mode

Device enters Power Down mode when SDCKE becomes LOW at idle state. All inputs, except SDCLK and SDCKE, are

turned off. During this mode, device’s power consumption is decreased. To return to previous state (idle or active state),

SDCKE should be made HIGH.

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The SDRAM Controller's Read/W rite Access

Data transmission to SDRAM is done by 4 consecut ive burst operati ons. The Rea d/Write timing of SDRAM is sho wn in the

figure below. A s shown in Figure 10, 4 burst operat ions are also needed to execute singl e write. I n this case, Dqm is se t to

HIGH (4’hF) to mask the data to be written. Moreover, in Figure 11, for writing 8 burst data, 4 burst operations are repeated.

SDCLK

Command

ADDR

Data

Dqm[3:0]

WRITE

A0

D3D0 D1 D2

4'h0

Figure 9. Write Transf er of Four Bursts

SDCLK

Command

ADDR

DATA

Dqm[3:0] 4'h0 4'hF 4'h0

WRITE

A0

D0

Figure 10. Single Data Write Transfer

SDCLK

Command

Addr

Data[31:0]

Dqm[3:0]

WRITE WRITE

A4

D4

A0

D0 D1 D2

4'h0

D5 D6 D7D3

Figure 11. Data Write Transfer of Eight Bursts

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Figure 12 is the case where 4 burst read operations are performed by CAS lat ency =2.

Figure 13is the case where 4 burst read operat ions are performed by CAS latency =3.

Figure 14 is the case where 8 burst read operations are performed by CAS lat ency =2.

SDCLK

Command

ADDR

DATA

Dqm[3:0]

READ

A0

4'h0

Q1 Q2 Q3Q0

CL = 2

Figure 12. Data Read of Four Bursts (CAS Latency = 2)

SDCLK

Command

ADDR

DATA

Dqm[3:0]

READ

Q3Q0 Q1 Q2

4'h0

A0

CL = 3

Figure 13. Data Read of Four Bursts (CAS Latency = 3)

Figure 14. Data Read of Eight Bursts (CAS Latency = 2)

SDCLK

Command

ADDR

DATA

Dqm[3:0] 4'h0

Q0 Q1

READ

A0

CL = 2

Q7

READ

A4

Q4 Q5 Q6Q2 Q3

Not Recommended for

New Designs

27/376

Datasheet

BM94801KUT

TSZ02201-0V2V0E600300-1-2

18.Apr.2014 Rev.003

www.rohm.com

TSZ22111・15・001

SDRAM Low Power Consumption Mode

The SDRAM controller supports Power Down Mode, Self-Refresh mode, as well as Low Power Consumption Mode.

By writing ‘1’ to SDRAM control register SCTLR[2], the device goes to Power Down Mode.

By writing ‘1’ to SDRAM control register SCTLR[1], the device goes to Self-Refresh Mode.

Device will exit any of these modes by clearing the SDRAM control register (SCTLR = 0).

Power Down Mode

When device is in Power Down Mode, SDRAM clock is disabled, which results to lower power consumption. If SDRAM

control register SCT LR[2] = ‘1’, clock enable (CKE) is set t o LOW. At this point, Power Down mode will start. Refer to the

figure below.

To return to normal operation, clear register SCTLR[2], and CKE is set to HIGH.

Moreover, when in Power Down mode, during refresh cycle, Power Down Mode is cancelled while device performs

Refresh operation. When refresh operation has finished executing, device returns to Power Down mode again.

At least one SDCLK cycle should be supplied to SDRAM before setting CKE to HIGH.

SDCLK

・・・・・・・・

SDCKE

・・・・・・・・

Command ・・・・・・・・

REF

リフレッシュを行なうために、

一端、パワーダウンモードを解除す

る

パワーダウンモード開始。再度、パワーダウンモード開

始

クロック非活性

Figure 15. Power Down Mode

Self-Refresh Mode

Like in Power Down Mode, when device is in Self-Refresh mode, clock is disabled and power consumption becomes lower.

Refresh operation is automatically executed using the refresh counter inside SDRAM.

This mode takes effect when SDRAM is not accessed for a long time.

Figure 16 shows the ti ming diagram during Self-Refresh mode.

When SDRAM control register SCTLR[1] is set to ‘1’, clock enable (CKE) is set to LOW. Self-Refresh command is inputted

and device enters Self-Refresh mode, as shown in the figure.

To return to normal operation, clear register SCTLR[1], and CKE is set to HIGH.

At least one SDCLK cycle should be supplied to SDRAM before setting CKE to HIGH.

SDCLK

・・・・

SDCKE

・・・・

Command ・・・・

REF

クロック非活性

セルフリフレッシュモード

Figure 16. Self-Refresh Mode

About the Address Translation

The figure shows the correspondence of the AHB address and the SDRAM address.

SDRAM Controller's Default

An initial value of memory controller's SDRAM is set as follows:

 Width of Row address: 11 bits

 Width of Column address: 8 bits

 Number of banks: 2

 CAS Latency: 2

Please refer to the configuration list for other settings.

Cloc

k

disabled.

Sel

f

-Refresh Mode

Cloc

k

disabled.

Powe

r

-Down Mode Start Power-Down Mode is cancelled

to perform Refresh Return to Power-Down Mode

Not Recommended for

New Designs

28/376

Datasheet

BM94801KUT

TSZ02201-0V2V0E600300-1-2

18.Apr.2014 Rev.003

www.rohm.com

TSZ22111・15・001

3.2.4. External Memory Interface

Figure 17. External Memory Interface

Not Recommended for

New Designs

29/376

Datasheet

BM94801KUT

TSZ02201-0V2V0E600300-1-2

18.Apr.2014 Rev.003

www.rohm.com

TSZ22111・15・001

3.3. I/O Signal

MEMCTL

hclk

hresetn

haddr

hsel_mem

hsel_reg

hwrite

htrans

hsize

hburst

hready

hwdata

sm_clken

sm_ready

sm_data_width_set0

s_sda_in

m_rd_data

gpi

remap

power_down

sm_power_down

clear_sr_dp

big_endian

hready_resp

hresp

hrdata

s_ras_n

s_cas_n

s_cke

s_bank_addr

s_sel_n

s_dqm

s_we_n

s_sa

s_scl

s_rd_ready

s_rd_start

s_rd_pop

s_rd_end

s_rd_dqs_mask

s_cas_latency

s_read_pipe

m_wr_data

m_addr

m_precharge_bit

m_dout_valid

sm_oe_n

sm_we_n

sm_bs_n

sm_rp_n

sm_wp_n

sm_adv_n

s_sda_out

s_sda_oe_n

gpo

Figure 18. Memory Controller

Not Recommended for

New Designs