CS4100 ADPCM Speech Coders
2
SPEECH COMPRESSION
In digital communications systems, speech coding (compres-
sion and decompression) is used to reduce the bit rate of a
speech signal with no, or minimal, noticeable degradation.
Without such coding, the typical voice channel would require
12-bit precision at a sampling rate of 8000 times per second,
equivalent to a data rate of 96 Kbits/second. As the ear is less
sensitive to errors at high volume levels than at low volumes,
logarithmic quantization can reduce this data rate to 64
Kbits/second with very little degradation; standard tech-
niques are the European A-law PCM and the American µ-law
PCM, both found in the CCITT G.711 standard. The data rate
can be further reduced through the use of ADPCM, which
transmits only the error between the actual signal and an
adaptively predicted signal. The current standards, G.726 and
G.727, support data rates of 40 Kbits/second down to as little
as 16 Kbits/second while maintaining "toll quality" speech.
The CS4100 cores are designed to provide up to 1024 duplex
channels of speech coding respectively, compliant with the
G.726 and G.727 standards as well as the extensions found in
G.726a and G.727a. The cores are capable of processing both
burst and continuous data streams, with the flexibility to
assign any channel to encode or decode arbitrarily. The imple-
mentation is low latency (ranging from 1 clock cycle in the
CS4180 to 16 clock cycles in the CS4110-30) and the simple
core interface allows easy integration into larger systems.
CS4100 FUNCTIONAL
DESCRIPTION AND OPERATION
The Amphion ADPCM core consists of 5 primary sections: an
ADPCM transcoding engine, logarithmic PCM/uniform PCM
expander, uniform PCM/logarithmic PCM compressor, chan-
nel configuration and control, and coding states storage mem-
ory, as illustrated in Figure 1. The core operates on one input
sample at a time, using 1, 6 or 16 clock cycles1to complete the
encoding or decoding. Multichannel coding is implemented
on time-multiplexing basis. The input/output channel multi-
plexing and serial to/from parallel conversion circuitry may
be added to suit the target system as required.
The CS4100 cores have two channel addressing modes: the
flexible mode and the duplex mode2. In the duplex mode, half
of the channels are set to encode and half to decode. The flexible
mode allows each channel to be set, and reset, individually.
Within each of these modes the core can encode data from
three types of PCM format, as specified by ITU standard G.711,
to 2, 3, 4 or 5-bit ADPCM format. These are 8-bit µ-law or A-
law logarithmic PCM, 14-bit µ-law uniform PCM or 13-bit A-
law uniform PCM. The core can also decode data from the 2,
3, 4 or 5-bit ADPCM format to the three types of PCM format.
The cores are on-line configurable in terms of compression
rate and PCM law3and allow on-the-fly selection of
PCM/uniform PCM input/output. Each member of
Amphion’s ADPCM family has been tested and verified
to be fully compliant using the ITU standard test vectors.
LOGARITHMIC
PCM/UNIFORM PCM EXPANDER
This block converts the input PCM signal from 8-bit A or µ-
law logarithmic PCM format to a 13-bit A-law or 14-bit µ-law
uniform PCM signal. This decoding is performed according to
the G.711 standard.
LOGARITHMIC
PCM/UNIFORM PCM COMPRESSOR
This block converts the output PCM signal from either 13-bit
A-law or 14-bit µ-law uniform PCM format to an 8-bit A- or
µ-law logarithmic PCM signal. This encoding is performed
according to the G.711 standard.
ADPCM TRANSCODING ENGINE
The primary encoding and decoding operations of the CS4100
ASVC take place within the ADPCM transcoding engine.
When encoding, the difference between the uniform PCM
input signal with a prediction of this signal is calculated. The
difference signal is then passed to an adaptive quantizer where
5, 4, 3 or 2 binary digits are assigned as its value, following
the quantization methods stipulated by the G.726 or G.727
standards. The result is the ADPCM signal for transmission.
The current ADPCM signal is then used to predict the next
signal estimate. It is fed to an inverse adaptive quantizer and
the output is added to the current input signal estimate to
determine the reconstructed version of the input signal. This
signal and the output of the adaptive quantizer are then used
by the adaptive predictor to determine the estimate of the
next input signal, which is then fed back to determine the
next difference signal.
When decoding, the reverse procedure is performed. First,
the ADPCM signal is inversely quantized; then the resulting
signal is added to a prediction of this signal, forming a recon-
structed signal. The inversely quantized signal and the recon-
structed signal are used by the adaptive predictor to determine
the signal estimate for the next iteration.
This reconstructed signal is converted to a PCM signal before
passing through an additional block needed for synchronous
coding adjustment. This block prevents cumulative distortion
occurring on synchronous tandem codings. This is when the
signal is converted from PCM to ADPCM to PCM and back to
ADPCM. The idea is that when the PCM signal is converted
the resulting ADPCM signal is the same at every stage. The
output PCM signal from this block is the resulting decoded
output of the codec.
116 clock cycles in the CS4110-30 cores, 1 clock cycle in the CS4180 and 6 clock cycles in the CS4190/91.
2The CS4180 operates in the flexible mode only.
3Compression rate and PCM law are selected on-the-fly in the CS4180.