CS4110 - Amphion Semiconductor Ltd.

Virtual Components for the Converging World

CS4100

ADPCM Speech Coders

The CS4100 family of adaptive differential pulse code modulators (ADPCMs) is designed to provide high per-

formance solutions for a broad range of applications requiring speech compression and decompression. These

application specific virtual components (ASVCs) support up to 1024 duplex channels, each of which is inde-

pendently selectable for encoding or decoding, and are fully compliant with ITU G.726, G.726a, G.727 and G.727a

standards. The CS4100 series of ASVCs is available in both ASIC and programmable logic versions that have

been handcrafted by Amphion for optimal performance while minimizing power consumption and silicon area.

CODER FEATURES

◆Fully Compliant with ITU Standards G.721,

G.723, G.726, G.726a, G.727 and G.727a

◆Supports Large Number of

Simultaneous Channels:

–CS4110: 8 duplex/16 simplex

–CS4120: 32 duplex/64 simplex

–CS4125: 64 duplex/128 simplex

–CS4130: 128 duplex/256 simplex

–CS4180: 512 duplex/1024 simplex4

–CS4190: 512 duplex/1024 simplex5

–CS4191: 1024 duplex/2048 simplex

◆Online Configurable for Different Compression

Rates, µ-law and A-law for each Encoding or

Decoding Channel

◆Burst Mode or Continuous Operation

◆Ease of Integration

–Tapeout-ReadyTM firm-IP targeted netlist

–Simple core interface for easy integration

into larger systems

KEY METRICS AND

SPECIFICATIONS

◆Logic : ~20k Gates

◆Memory: 4.5-288 Kbits Single-Port SRAM1

209 Kbits Dual-Port SRAM (CS4180)

◆Operating Frequency: 2-49 MHz2

◆ Total Die Area3

– 0.32 mm2(CSO4110)

– 0.41 mm2(CSO4120)

– 0.51 mm2(CSO4125)

– 0.73 mm2(CSO4130)

– 2.3 mm2(CSO4190TK)

– 4.3 mm2(CSO4191TK)

APPLICATIONS

◆Wireless Telecommunications

– DECT phones

– Digital cellular

◆Satellite Communications

◆Wired Telecommunications

– Videoconferencing

– Voicemail systems

– PBXs

1Applies to CS4110-30 and CS4190. Amount of memory is dependent upon the maximum number of channels supported. For example, the 8 duplex channel

CSO4110 uses 4.48 Kbits while the 128 duplex channel CSO4130 uses 71.68 Kbits.

2Operating frequency is dependent upon the maximum number of channels supported. For example, the 8 duplex channel CS4110 runs at 2.048

MHz (min.) while the 128 duplex channel CS4130 runs at 32.768 MHz minimum.

3Calculation assumes logic density of 90K gates/mm2; SRAM density of 150 Kbits/mm2plus 20% area overhead for memory peripheral circuitry.

4Celerity CSC4180AA and CSC4180XV versions support 384 duplex/768 simplex channels, and the Celerity CSC4180X2 version supports 512 duplex/1024

simplex channels.

5Refers to Optima version. Celerity version supports 384 duplex/768 simplex channels (CSC4190XE) or 256 duplex/512 simplex channels (CSC4190AA).

CS4100 ADPCM Speech Coders

SPEECH COMPRESSION

In digital communications systems, speech coding (compres-

sion and decompression) is used to reduce the bit rate of a

speech signal with no, or minimal, noticeable degradation.

Without such coding, the typical voice channel would require

12-bit precision at a sampling rate of 8000 times per second,

equivalent to a data rate of 96 Kbits/second. As the ear is less

sensitive to errors at high volume levels than at low volumes,

logarithmic quantization can reduce this data rate to 64

Kbits/second with very little degradation; standard tech-

niques are the European A-law PCM and the American µ-law

PCM, both found in the CCITT G.711 standard. The data rate

can be further reduced through the use of ADPCM, which

transmits only the error between the actual signal and an

adaptively predicted signal. The current standards, G.726 and

G.727, support data rates of 40 Kbits/second down to as little

as 16 Kbits/second while maintaining "toll quality" speech.

The CS4100 cores are designed to provide up to 1024 duplex

channels of speech coding respectively, compliant with the

G.726 and G.727 standards as well as the extensions found in

G.726a and G.727a. The cores are capable of processing both

burst and continuous data streams, with the flexibility to

assign any channel to encode or decode arbitrarily. The imple-

mentation is low latency (ranging from 1 clock cycle in the

CS4180 to 16 clock cycles in the CS4110-30) and the simple

core interface allows easy integration into larger systems.

CS4100 FUNCTIONAL

DESCRIPTION AND OPERATION

The Amphion ADPCM core consists of 5 primary sections: an

ADPCM transcoding engine, logarithmic PCM/uniform PCM

expander, uniform PCM/logarithmic PCM compressor, chan-

nel configuration and control, and coding states storage mem-

ory, as illustrated in Figure 1. The core operates on one input

sample at a time, using 1, 6 or 16 clock cycles1to complete the

encoding or decoding. Multichannel coding is implemented

on time-multiplexing basis. The input/output channel multi-

plexing and serial to/from parallel conversion circuitry may

be added to suit the target system as required.

The CS4100 cores have two channel addressing modes: the

flexible mode and the duplex mode2. In the duplex mode, half

of the channels are set to encode and half to decode. The flexible

mode allows each channel to be set, and reset, individually.

Within each of these modes the core can encode data from

three types of PCM format, as specified by ITU standard G.711,

to 2, 3, 4 or 5-bit ADPCM format. These are 8-bit µ-law or A-

law logarithmic PCM, 14-bit µ-law uniform PCM or 13-bit A-

law uniform PCM. The core can also decode data from the 2,

3, 4 or 5-bit ADPCM format to the three types of PCM format.

The cores are on-line configurable in terms of compression

rate and PCM law3and allow on-the-fly selection of

PCM/uniform PCM input/output. Each member of

Amphion’s ADPCM family has been tested and verified

to be fully compliant using the ITU standard test vectors.

LOGARITHMIC

PCM/UNIFORM PCM EXPANDER

This block converts the input PCM signal from 8-bit A or µ-

law logarithmic PCM format to a 13-bit A-law or 14-bit µ-law

uniform PCM signal. This decoding is performed according to

the G.711 standard.

LOGARITHMIC

PCM/UNIFORM PCM COMPRESSOR

This block converts the output PCM signal from either 13-bit

A-law or 14-bit µ-law uniform PCM format to an 8-bit A- or

µ-law logarithmic PCM signal. This encoding is performed

according to the G.711 standard.

ADPCM TRANSCODING ENGINE

The primary encoding and decoding operations of the CS4100

ASVC take place within the ADPCM transcoding engine.

When encoding, the difference between the uniform PCM

input signal with a prediction of this signal is calculated. The

difference signal is then passed to an adaptive quantizer where

5, 4, 3 or 2 binary digits are assigned as its value, following

the quantization methods stipulated by the G.726 or G.727

standards. The result is the ADPCM signal for transmission.

The current ADPCM signal is then used to predict the next

signal estimate. It is fed to an inverse adaptive quantizer and

the output is added to the current input signal estimate to

determine the reconstructed version of the input signal. This

signal and the output of the adaptive quantizer are then used

by the adaptive predictor to determine the estimate of the

next input signal, which is then fed back to determine the

next difference signal.

When decoding, the reverse procedure is performed. First,

the ADPCM signal is inversely quantized; then the resulting

signal is added to a prediction of this signal, forming a recon-

structed signal. The inversely quantized signal and the recon-

structed signal are used by the adaptive predictor to determine

the signal estimate for the next iteration.

This reconstructed signal is converted to a PCM signal before

passing through an additional block needed for synchronous

coding adjustment. This block prevents cumulative distortion

occurring on synchronous tandem codings. This is when the

signal is converted from PCM to ADPCM to PCM and back to

ADPCM. The idea is that when the PCM signal is converted

the resulting ADPCM signal is the same at every stage. The

output PCM signal from this block is the resulting decoded

output of the codec.

116 clock cycles in the CS4110-30 cores, 1 clock cycle in the CS4180 and 6 clock cycles in the CS4190/91.

2The CS4180 operates in the flexible mode only.

3Compression rate and PCM law are selected on-the-fly in the CS4180.

Virtual Components for the Converging World

72.704 Kbits

PRODUCT NUMBER MEMORY REQUIREMENT

CS4110 4.544 Kbits

CS4120 18.176 Kbits

CS4125 36.352 Kbits

CS4130

G726

Data

input

Data

output

Status

outputs

BSY**

ESI**

DSI**

STE*

EW PCM EDC DSS CHN

A-law/

µ-law

A-law/µ-law

CFG RST CLR MODE**

Uniform/

non-uniform

ADPCM

output signal

PCM

output signal

Logarithmic PCM

output signal

PCM output

Compressor

Memory

Mux

ADPCM

Engine

PCM input

Expander

Mux

Uniform PCM

output signal

Uniform/

non-uniform

Uniform PCM input

Logarithmic

PCM input

ADPCM input signal

* Scan Test Enable – only for the ASIC implementation

**Does not apply to CS4180

CLK

Coding control Reset & Configuration

Figure 1: Input/Outputs for the Amphion ADPCM Cores

1The CS4110-30 use 283 bit states per channel, the CS4180 uses 279 and the CS4190 and 4191 use 282.

CS4180 209.250 Kbits

CS4190 288.768 Kbits

Table 1: Coding States Storage Memory

The ADPCM algorithm requires from 279 to 283 bit states1for

each encoding or decoding channel (i.e., 558 to 566 bits per

duplex channel). These states are stored in the memory of the

ADPCM core.

To reduce the width of the data bus in the CS4110-30 and to

enable the core to complete an encoding or decoding opera-

tion in 16 clock cycles, the memory is organized as 71 bits

wide. This enables storage of a channel in 4 words, or 8

words for a duplex channel. In the CS4180 and CS4190/91, the

memory is organized as 279 or 282 bits wide (respectively)

by N words (where N is the number of channels), allowing

compete encoding or decoding operations in 1 (CS4180) or

6 (CS4190/91) clock cycles. Total memory requirements for

the members of the CS4100 family are found in Table 1.

In the CS4110-30 ASVCs, the core reads the coding states from

the memory in the first 4 clock cycles of the 16 clock cycle

operation period. In the last 4 clock cycles, the core writes the

update states back to the memory. In the CS4180, all memory

operations take place in 1 clock cycle; in the CS4190/91, these

memory read and write operations take 1 clock cycle each

of the 6 clock cycle operation period.

CODING STATES STORAGE MEMORY

CS4191 577.536 Kbits

CS4100 ADPCM Speech Coders

CONFIGURATION AND CONTROL

The 8-bit wide CFG bus determines the compression rate

and law for each channel. The function of each bit is listed

in Table 2. Note that the top 4 bits are only used in the

duplex mode and specify the law and compression rate for

encoding; note that these bits do not apply to the CS4180.

The input signal G726 is used to specify whether the G.726

or G.727 is in use; when high the core operates per the G.726

standard, low indicates G.727.

Duplex (that is, the channels are split evenly between encode

and decode) and flexible channel addressing modes are select-

ed via the static MODE input. When MODE is high, the core

operates in duplex mode and when MODE is low the core

operates in the flexible mode. In the latter case, each channel

can operate as either an encoding or a decoding channel.

Note that the CS4180 operates in the flexible mode only.

ENCODING/DECODING OPERATION

Encoding or decoding of one data sample is started by assert-

ing the data strobe signal (DSS). The input select signal EDC

defines whether the core performs an encoding or a decoding

operation. When EDC is HIGH, the core performs encoding

and the input S is taken. When EDC is LOW the core will

decode and the input ID is taken. Input signal PCM specifies

the type of encoding input data and decoding output data,

and input CHN specifies the channel the data belongs to, as

described in the previous sections.

The ADPCM core requires 1, 6 or 16 clock cycles (in the

CS4180, CS4190/91 and CS4110-30, respectively) to complete

an encoding or decoding operation for one data sample and

the output indicator BSY is de-asserted after the rising edge of

the 6th (or 16th) cycle (note: the output indicator BSY does

not apply to the CS4180, which completes all operations in a

single clock cycle). DSS can then be asserted after the rising

edge to start the next operation. The encoding and decoding

timing diagrams are depicted in Figure 3 and Figure 4,

respectively, for the CS4110-30 and Figures 5 and 6 for the

CS4190/91. The CS4180 completes all operations in a single

clock cycle.

5 bits

Control Values

4 bits

[2]

[3]

Selects either A-law or µ-law for decoding

in the duplex mode or encoding/decoding

in the flexible mode

CFG BITS DESCRIPTION CONTROL CHOICE

µ-law A-law

Control Values 0 1

[5:4] Controls the number of bits in the ADPCM

output word when encoding in the duplex mode 2 bits 3 bits 4 bits 5 bits

Control Values 00 01 10 11

[6]

Controls whether even bit inversion/all bit inversion is

performed for A-law/µ-law encoding operations

in the duplex mode

No bit inversion

Even bit inversion performed

for A-law

All bit inversion

performed for µ-law

[7] Selects either A-law or µ-law for encoding

in the duplex mode µ-law A-law

Control Values 0 1

Controls whether even bit inversion/all bit inversion

is performed for A-law/µ-law decoding operations

in the duplex mode or encoding/decoding

in the flexible mode

No bit inversion

Even bit inversion performed

for A-law

All bit inversion

performed for µ-law

00 01 10 11

[1:0]

Controls the number of bits in the ADPCM output

word when encoding in the duplex mode or the

number of bits in the ADPCM input word and the

ADPCM output word in the flexible mode.

2 bits 3 bits

Table 2: Codec Configuration Control Word

For the CS4110-30 and CS4190/91, it should be noted that:

◆The core should be configured before an encoding or

decoding operation is started.

◆When core busy indicator BSY is HIGH, asserting the

control signal DSS is ignored.

◆Other input control signals, namely, EDC, CHN, PCM,

G726 and EW, are latched on the clock rising edge when

DSS is HIGH and BSY is LOW.

◆Input data S and ID are also latched on the clock rising

edge when DSS is HIGH and BSY is LOW.

◆The output data is registered.

◆The encoding status indicator ESI indicates the internal

encoding state of the core. When it goes to LOW, the core

has completed the predictor state update. When it returns

to HIGH, the encoding output is available.

◆The decoding status indicator (DSI) indicates the internal

decoding state of the core. When it goes to LOW, the core

has completed the predictor state update. When it returns

to HIGH, the decoding output is available.

◆When an encoding or decoding operation is completed,

signal BSY returns to LOW and the core waits for DSS to

be asserted to start the next operation.

◆Encoding and decoding can be performed in any order.

Output signals encode status indicator (ESI) and decode status

indicator (DSI) indicate the encoding and decoding status,

respectively. From the cycle when the codec picks up the

input data, ESI or DSI goes to ‘0’. In the cycle when the

encoding/decoding output is available, the corresponding

signal returns to ‘1’. Both the signals are set to ‘1’ after reset

and before the first input.

CHANNEL SELECTION

The CHN input specifies the channel with which the input

data is associated when the core is performing a coding

operation or with which the CFG word is applied when the

core is performing channel reset and configuration. In the

flexible mode, one channel is either encoding or decoding

and the channel number is fully specified by CHN.

GLOBAL RESET AND CONFIGURATION

The asynchronous global reset signal, RST, resets all the

channels and configures them with the same compression

rate and PCM law; reset is activated when RST is asserted.

RST also resets all the registers in the core and interrupts the

encoding/decoding operation the core is performing. Global

configuration of the core is performed using the CFG input as

described earlier. The reset and configuration process starts

on the first rising clock edge after RST has been de-asserted

and continues for either 4*N cycles (CS4110-30) or N cycles

(CS4180-90), where N is the number of simplex channels

(where each duplex channel is considered as two simplex

channels). Reset occurs in 1 clock cycle for the CS4180.

DSS

RST

CLR

CLK

STE

(Only for ASIC)

EDC

CHN

CFG[7:0]

EW[1:0]

PCM

MODE*

G726

ID[4:0]

S[13:0]

ESI*

DSI*

BSY*

SD[13:0]

I[4:0]

CS4100

ADPCM

CHN[3:0] for CS4110

CHN[5:0] for CS4120

CHN[6:0] for CS4125

CHN[7:0] for CS4130

CHN[9:0] for CS4180/CS4190

CHN[10:0] for CS4191

Figure 2: ADPCM Core Pinouts.

Table 1 gives the descriptions of the input and output ports

(shown graphically in Figure 2) of the CS4100 ADPCM

codecs. Unless otherwise stated, all signals are active high and

bit (0) is the least significant bit.

Virtual Components for the Converging World

PIN/PORT DESCRIPTION

*Does not apply to CS4180

CS4100 ADPCM Speech Coders

Specifies the number of G.727 enhancement bits

"00": 0 bits

"01": 1 bit

"10": 2 bits

"11": 3 bits

SIGNAL DESCRIPTION

ADPCM input word for decoding

ID[4:3]: 2 bit ADPCM word, 16 Kbits/sec data rate

ID[4:2]: 3 bit ADPCM word, 24 Kbits/sec data rate

ID[4:1]: 4 bit ADPCM word, 32 Kbits/sec data rate

ID[4:0]: 5 bit ADPCM word, 40 Kbits/sec data rate

I 5

G726 I 1

Specifies G.726 or G.727 operation

High: G.726 standard

Low: G.727 standard

EW[1:0] I 2

I/O WIDTH

(Bits)

Table 3: Input and Output Descriptions (Continued on page 7)

S[13:0] I14

Logarithmic or uniform PCM input word for encoding

S[13:0]: µ-law uniform PCM input

S[13:1]: A-law uniform PCM input

S[7:0]: Logarithmic PCM input

PCM I 1

Logarithmic PCM or uniform PCM selection control signal

High: logarithmic PCM

Low: uniform PCM

EDC

DSS I 1 Input data strobe signal, active high, encoding/decoding is started

when asserted and BSY is low

Selects encode or decode operation:

High: encode

Low: decode

MODE

(CS4110-30, CS4190/91) I 1

Selects between the two modes of operation for the ADPCM core,

the duplex and flexible modes

High: duplex mode

Low: flexible mode

Clk I 1 Clock input, rising edge active

RST I 1 Global reset and configuration symbol, active high, asynchronous to clock

CLR I 1 Synchronous individual channel reset and configuration signal, active high

CHN[3-10:0] I4/6/7/8/

9/10/11

Specifies channel with which the input data is associated when

the core is performing coding operation or performing channel reset.

Width is 4 bits for CS4110, 6 bits for CS4120, 7 bits for CS4125

and 8 bits for CS4130

Duplex mode: one channel encoding/decoding,

channel number specified by:

CHN[3:1] for the CS4110 core

CHN[5:1] for the CS4120 core

CHN[6:1] for the CS4125 core

CHN[7:1] for the CS4130 core

CHN[9:1] for the CS4180 and CS4190 cores

CHN[10:1] for the CS4191 core

(the LSB is ignored by the core)

In the flexible mode, one channel coding is either encoding or decoding

and the channel number is fully specified by CHN.

Virtual Components for the Converging World

DSI* (CS4110-30, CS4190)

Scan test enable (Optima Cores™ only)

During scan test the memory block must be bypassed to perform the test

During test, STE is set high, bypassing the memory. During normal operation

of the core, STE is low

ESI* (CS4110-30, CS4190)

SD[13:0]

I[4:0]

CFG[7:0]

SIGNAL DESCRIPTION

I 8 Channel configuration word defined as:

CFG(7): selects either A-law (CFG(7)=1), or µ-law (CFG(7)=0) for encoding in

the duplex mode

CFG(6): controls whether even bit inversion is performed for A-law encoding

operations. Even bit inversion on the 8-bit PCM input data is

performed when CFG(6) is ‘1’

CFG(5:4): controls the number of bits in the ADPCM output word when encoding

in the duplex mode

Encoding compress rates: 00 = 16 Kbit/s

01 = 24 Kbit/s

10 = 32 Kbit/s

11 = 40 Kbit/s

CFG(3): selects either A-law (CFG(3)=1), or µ-law (CFG(3)=0) for decoding in

the duplex mode or encoding/decoding in the flexible mode

CFG(2): controls whether even bit inversion is performed for A-law decoding

operations in the duplex mode or encoding/decoding in the flexible

mode. Even bit inversion on the 8-bit PCM input data or the 8-bit PCM

output data is performed when CFG(2) is ‘1’

CFG(1:0): controls the number of bits in the ADPCM output word when encoding

in the duplex mode or the number of bits in the ADPCM input word

and the ADPCM output word in the flexible mode

Decoding compress rates: 00 = 16 Kbit/s

01 = 24 Kbit/s

10 = 32 Kbit/s

11 = 40 Kbit/s

O 5 ADPCM output word

I[4:3]: 2 bit ADPCM output, 16 Kbit/s

I[4:2]: 3 bit ADPCM output, 24 Kbit/s

I[4:1]: 4 bit ADPCM output, 32 Kbit/s

I[4:0]: 5 bit ADPCM output, 40 Kbit/s

O14 Logarithmic or uniform PCM output word from decoding

SD[13:0]: µ-law uniform PCM output

SD[13:1]: A-law uniform PCM output

SD[7:0]: Logarithmic PCM output

BSY* (CS4110-30, CS4190) O 1 Core busy indicator, active high, DSS is ignored when BSY is active

O 1 Encoding status indicator

Decoding status indicator

O 1

1STE I

I/O WIDTH

(Bits)

Table 3: Input and Output Descriptions

*Does not apply to CS4180

CS4100 ADPCM Speech Coders

CS4110-30 Timing

CLK

DSS

EDC

PCM

G726

CHN

BSY

ESI

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

16 clock cycles

CLK

DSS

EDC

PCM

G726

CHN

BSY

DSI

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

16 clock cycles

Figure 4: Decoding Timing Characteristics of the CS4110–30

Figure 3: Encoding Timing Characteristics of the CS4110–30

Virtual Components for the Converging World

CLK

DSS

EDC

PCM

G726

CHN

BSY

ESI

6 clock

cycles

CS4190/CS4191 Timing

CLK

DSS

EDC

PCM

G726

CHN

BSY

DSI

6 clock

cycles

Figure 6: Decoding Timing – CS4190/CS4191

Figure 5: Encoding Timing – CS4190/CS4191

CS4100 ADPCM Speech Coders

AVAILABILITY AND IMPLEMENTATION INFORMATION

OPTIMA™CORES

PRODUCT ID# SILICON

VENDOR

PRODUCT

NAME/PROCESS

CSO4110TK

CSO4120TK

CSO4125TK

TSMC

0.18-micron using Artisan

standard cell libraries

0.18-micron using Artisan

standard cell libraries

0.18-micron using Artisan

standard cell libraries

PERFORMANCE LOGIC

GATES

MEMORY

AREA

(mm2)*

32 duplex channels at

8.192 MHz 19.8K 0.20

0.31

64 duplex channels at

16.384 MHz 19.8K

8 duplex channels at 2.048

MHz 19.6K 0.12

CSO4130TK TSMC 0.18-micron using Artisan

standard cell libraries

128 duplex channels at

32.768 MHz

AVAILABILITY

Now

Now19.8K 0.52

CSO4190TK TSMC 0.18-micron using Artisan

standard cell libraries

512 duplex channels at

49.152 MHz 26.7K 2.05 Now

* Based on an SRAM density of 150 Kbits/mm2plus 20% area overhead for memory peripheral circuitry.

Consult your local Amphion representative for product specific performance information, current availability of individual products, and lead times on Optima core porting.

Table 5: Optima Cores

For applications that require the high performance, low cost and high integration of an ASIC, Amphion delivers the Optima

Cores series of multimedia ASVCs that are pre-optimized by Amphion experts to a targeted silicon technology. Choose from

off-the-shelf versions of the CSO4100 family available for many popular ASIC and foundry silicon supplier technologies or

Amphion can port the cores to a technology of your choice.

CSO4191TK TSMC 0.18-micron using Artisan

standard cell libraries

1024 duplex channels at

98.304 MHz 26.7K 4.1 Now

Virtual Components for the Converging World

4307 Logic Elements

24 ESB

PRODUCT ID# DEVICE RESOURCES

USED

Now

CSC4125XV Xilinx Virtex FPGA 64 duplex channels at

16.384 MHz

1869 SLICEs

9 Block RAMs Now

8 duplex channels at

2.048 MHz

4294 Logic Elements

11 ESB

SILICON

VENDOR

PROGRAMMABLE

LOGIC PRODUCT PERFORMANCE AVAILABILITY

CSC4110AA Altera Apex 20K FPGA

CSC4110XV Xilinx Virtex FPGA 8 duplex channels at

2.048 MHz

1669 SLICEs

5 Block RAMs

CSC4120AA Altera

Altera

Xilinx

Apex 20K FPGA

Virtex FPGA

32 duplex channels at

8.192 MHz

4302 Logic Elements

16 ESB

CSC4120XV 32 duplex channels at

8.192 MHz

1688 SLICEs

5 Block RAMs

CSC4125AA 64 duplex channels at

16.384 MHz

Now

CSC4180AA

CSC4190XE

Altera Apex 20K FPGA 512 simplex channels at

4.092 MHz

6336 Logic Elements

72 ESB Now

Now

CSC4180XE

CSC4190AA

Xilinx

Altera

Virtex-E FPGA

Apex 20K FPGA

512 simplex channels at

4.092 MHz

256 duplex channels at

24.576 MHz

384 duplex channels at

36.864 MHz

2721 SLICEs

71 Block RAMs

7178 Logic Elements

76 ESB

2369 SLICEs*

35 Block RAMS

Table 6: Celerity Cores

*Not all the resources of every slice are used.

CELERITY™CORES

For ASIC prototyping or for projects requiring the fast time to market of a programmable logic solution, Amphion’s Celerity

Core solutions offer the silicon-aware performance tuning found in all Amphion products, combined with the rapid design

times offered by today’s leading programmable logic solutions.

CS4100 ADPCM Speech Coders Virtual Components for the Converging World

THE PERFORMANCE ADVANTAGE OF AMPHION ASVCs

ABOUT AMPHION

Amphion is the leading supplier of

speech coding, video/image process-

ing and channel coding ASVCs for

system-on-a chip (SoC) solutions in

the telecommunications/Internet,

consumer/communications and wire-

less markets.

The performance and cost tradeoffs

between general- and fixed-purpose

solutions are substantial and the gap

grows with every generation of silicon

process technology. The difference

between general-purpose solutions

(microprocessor) and the intrinsic com-

putational efficiency of silicon is nearly

three orders of magnitude. This gap

is the reason that Amphion fixed-pur-

pose ASVCs deliver a ten to one thou-

sand time improvement in performance

when compared to conventional imple-

mentations using general-purpose, soft-

ware-programmable DSP microprocessors.

Using proprietary techniques for direct-

mapped implementations of digital signal

processing functions and algorithms in

hardware, Amphion's ASVCs provide a

well-thought-out design approach that

will continue to provide extraordinary

performance advantages in the future,

as well as time-to-market advantages,

because they are off-the-shelf.

Web: www.amphion.com

Email: info@amphion.com

2 1 0.5 0.25 0.13 0.07

10 6

10 5

10 4

10 3

10 2

10 1

10 0

Feature Size µm

MiPS / WATTS

Application Specific

Virtual Component (ASVC)

DSP Processors

1000X

Difference

U.S. HEADQUARTERS

2001 Gateway Place, Suite 130W

San Jose, CA 95110

Tel: 408.441.1248

Fax: 408.441.1239

EUROPEAN HEADQUARTERS

50 Malone Road

Belfast BT9 5BS

Northern Ireland, UK

Tel: +44.28.9050.4000

Fax: +44.28.9050.4001

EASTERN USA and CANADA

Bay Colony Corporate Center

1050 Winter Street, Ste. 1000

Waltham, MA 92451

Tel: (781) 530-3725

Fax: (781) 530-3726

JAPAN

Hibiya Central Bldg. 14F

1-2-9, Nishi-Shimbashi

Minato-ku

Tokyo 105-0003 JAPAN

Tel: 81-3-5532-7268

Fax: 81-3-5532-7373

Amphion continues to expand its family of ASVC solutions.

See http://www.amphion.com for a current list of products.

SALES AGENTS

MISIL TECHNOLOGIES

2 Rue de la Couture SILIC 301 94588

RUNGIS Cedex France

Tel: +33.1.4560 0021

Fax: +33.1.4560 0186/4762

Email: misil@misil.fr

http://www.misil.fr/

WIZARD LTD.

P.O. Box 262410

Hayetzira Str.

Ranana 43663 Israel

Tel: +972.9.7404.349 and

+972.9.7404.392

Fax: +972.9.7440.348

Email: sales@wiztrade.com

SPINNAKER SYSTEMS INC.

Hatchobori SF Bldg. 5F 3-12-8

Hatchobori, Chuo-ku

Tokyo 104-0033 Japan

Tel: +81.3.3551.2275

Fax: +81.3.3551.2614

Email: info@spinnaker.co.jp

http://www.spinnaker.co.jp/

JASONTECH, INC.

Hansang Building, Suite 300

Bangyidong 181-3, Songpaku

Seoul Korea 138-050

Tel: +82.2.420.6700

Fax: +82.2.420.8600

Email: jsryu@jat.co.kr

http://www.vlab.com

SPS-DA PTE LTD

21 Science Park Rd

#03-19 The Aquarius

Singapore Science Park II

Singapore 117628

Tel: +65.774.9070

Fax: +65.774.9071

Email: raj@spsda.com.sg

http://www.spsda.com.sg/

Amphion, the Amphion logo,

"Virtual Components for the Converging World",

"The Multimedia ASVC Company", Optima, Celerity,

Tapeout-Ready, TestReady and AutoMode

are trademarks of Amphion Semiconductor Ltd.

Figure 10: Amphion ASVCs Outperform DSPs by 1000X

02/01 Publication #: DS4100-b