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Old Company Name in Catalogs and Other Documents
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Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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Document No. U17894EJ9V0UD00 (9th edition)
Date Published July 2009 NS
Printed in Japan 2006
μ
PD78F1162, 78F1162A, 78F1162A(A)
μ
PD78F1163, 78F1163A, 78F1163A(A)
μ
PD78F1164, 78F1164A, 78F1164A(A)
μ
PD78F1165, 78F1165A, 78F1165A(A)
μ
PD78F1166, 78F1166A, 78F1166A(A)
μ
PD78F1167, 78F1167A, 78F1167A(A)
μ
PD78F1168, 78F1168A, 78F1168A(A)
78K0R/KG3
16-bit Single-Chip Microcontrollers
User’s Manual
User’s Manual U17894EJ9V0UD
2
[MEMO]
User’s Manual U17894EJ9V0UD 3
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
User’s Manual U17894EJ9V0UD
4
Windows and Windows NT are registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
EEPROM is a trademark of NEC Electronics Corporation.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the
United States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
The information in this document is current as of July, 2009. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets,
etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or
types are available in every country. Please check with an NEC Electronics sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality and safety of NEC Electronics products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. In addition, NEC
Electronics products are not taken measures to prevent radioactive rays in the product design. When customers
use NEC Electronics products with their products, customers shall, on their own responsibility, incorporate
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persons, as the result of defects of NEC Electronics products.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E0904E
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
User’s Manual U17894EJ9V0UD 5
INTRODUCTION
Readers This manual is intended for user engineers who wish to understand the functions of the
78K0R/KG3 and design and develop application systems and programs for these
devices.
The target products are as follows.
• Conventional-specification products of the 78K0R/KG3:
μ
PD78F1162, 78F1163, 78F1164, 78F1165, 78F1166, 78F1167, 78F1168
• Expanded-specification products of the 78K0R/KG3:
μ
PD78F1162A, 78F1163A, 78F1164A, 78F1165A, 78F1166A, 78F1167A, 78F1168A
• (A) grade products of the expanded-specification products of the 78K0R/KG3:
μ
PD78F1162A(A), 78F1163A(A), 78F1164A(A), 78F1165A(A), 78F1166A(A),
78F1167A(A), 78F1168A(A)
Purpose This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization The 78K0R/KG3 manual is separated into two parts: this manual and the instructions
edition (common to the 78K0R Microcontroller Series).
78K0R/KG3
User’s Manual
(This Manual)
78K0R Microcontroller
User’s Manual
Instructions
• Pin functions
• Internal block functions
• Interrupts
• Other on-chip peripheral functions
• Electrical specifications
• CPU functions
• Instruction set
• Explanation of each instruction
How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• When using this manual as the manual for (A) grade products of the expanded-
specification products of 78K0R/KG3 microcontrollers:
→ Only the electrical specifications and quality grade differ between standard
products and (A) grade products. Read the part number for (A) grade products as
follows.
•
μ
PD78F116yA →
μ
PD78F116yA(A) (y = 2 to 8)
• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark “<R>” shows major
revised points. The revised points can be easily searched by copying an “<R>” in
the PDF file and specifying it in the “Find what:” field.
User’s Manual U17894EJ9V0UD
6
• How to interpret the register format:
→ For a bit number enclosed in angle brackets, the bit name is defined as a
reserved word in the RA78K0R, and is defined as an sfr variable using the
#pragma sfr directive in the CC78K0R.
• To know details of the 78K0R Series instructions:
→ Refer to the separate document 78K0R Microcontroller Instructions User’s
Manual (U17792E).
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representations: Binary
...×××× or ××××B
Decimal
...××××
Hexadecimal
...××××H
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
78K0R/KG3 User’s Manual This manual
78K0R Microcontroller Instructions User’s Manual U17792E
78K0R Microcontroller Self Programming Library Type01 User’s ManualNote U18706E
Note This document is classified under engineering management. Contact an NEC Electronics sales representative.
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name Document No.
Operation U18549E CC78K0R Ver. 2.00 C Compiler
Language U18548E
Operation U18547E RA78K0R Ver. 1.20 Assembler Package
Language U18546E
SM+ System Simulator Operation U18601E
PM+ Ver. 6.30 U18416E
ID78K0R-QB Ver. 3.20 Integrated Debugger Operation U17839E
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name Document No.
QB-MINI2 On-Chip Debug Emulator with Programming Function U18371E
QB-78K0RKX3 In-Circuit Emulator U17866E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
User’s Manual U17894EJ9V0UD 7
Documents Related to Flash Memory Programming (User’s Manuals)
Document Name Document No.
PG-FP4 Flash Memory Programmer U15260E
PG-FP5 Flash Memory Programmer U18865E
Other Documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE − Products and Packages − X13769X
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
User’s Manual U17894EJ9V0UD
8
CONTENTS
CHAPTER 1 OUTLINE ...........................................................................................................................18
1.1 Differences Between Conventional-Specification Products (
μ
PD78F116x) and
Expanded- Specification Products (
μ
PD78F116xA) .............................................................18
1.2 Features ....................................................................................................................................19
1.3 Applications..............................................................................................................................20
1.4 Ordering Information ...............................................................................................................21
1.5 Pin Configuration (Top View)..................................................................................................22
1.6 78K0R/Kx3 Microcontroller Lineup ........................................................................................25
1.7 Block Diagram ..........................................................................................................................26
1.8 Outline of Functions ................................................................................................................27
CHAPTER 2 PIN FUNCTIONS ..............................................................................................................29
2.1 Pin Function List ......................................................................................................................29
2.2 Description of Pin Functions ..................................................................................................35
2.2.1 P00 to P06 (port 0) .....................................................................................................................35
2.2.2 P10 to P17 (port 1) .....................................................................................................................36
2.2.3 P20 to P27 (port 2) .....................................................................................................................37
2.2.4 P30, P31 (port 3) ........................................................................................................................37
2.2.5 P40 to P47 (port 4) .....................................................................................................................38
2.2.6 P50 to P57 (port 5) .....................................................................................................................39
2.2.7 P60 to P67 (port 6) .....................................................................................................................40
2.2.8 P70 to P77 (port 7) .....................................................................................................................40
2.2.9 P80 to P87 (port 8) .....................................................................................................................41
2.2.10 P110, P111 (port 11) ..................................................................................................................41
2.2.11 P120 to P124 (port 12) ...............................................................................................................41
2.2.12 P130, P131 (port 13) ..................................................................................................................42
2.2.13 P140 to P145 (port 14) ...............................................................................................................43
2.2.14 P150 to P157 (port 15) ...............................................................................................................44
2.2.15 AVREF0 ........................................................................................................................................44
2.2.16 AVREF1 ........................................................................................................................................45
2.2.17 AVSS ...........................................................................................................................................45
2.2.18 RESET .......................................................................................................................................45
2.2.19 REGC .........................................................................................................................................45
2.2.20 VDD, EVDD0, EVDD1 ......................................................................................................................46
2.2.21 VSS, EVSS0, EVSS1 .......................................................................................................................46
2.2.22 FLMD0........................................................................................................................................46
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins.......................................47
CHAPTER 3 CPU ARCHITECTURE .....................................................................................................52
3.1 Memory Space..........................................................................................................................52
3.1.1 nternal program memory space..................................................................................................62
3.1.2 Mirror area..................................................................................................................................64
3.1.3 Internal data memory space .......................................................................................................65
3.1.4 Special function register (SFR) area...........................................................................................66
User’s Manual U17894EJ9V0UD 9
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area .................66
3.1.6 Data memory addressing ...........................................................................................................67
3.2 Processor Registers ................................................................................................................74
3.2.1 Control registers .........................................................................................................................74
3.2.2 General-purpose registers..........................................................................................................76
3.2.3 ES and CS registers...................................................................................................................78
3.2.4 Special function registers (SFRs) ...............................................................................................79
3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) .....................85
3.3 Instruction Address Addressing ............................................................................................91
3.3.1 Relative addressing....................................................................................................................91
3.3.2 Immediate addressing ................................................................................................................91
3.3.3 Table indirect addressing ...........................................................................................................92
3.3.4 Register direct addressing..........................................................................................................93
3.4 Addressing for Processing Data Addresses.........................................................................94
3.4.1 Implied addressing .....................................................................................................................94
3.4.2 Register addressing ...................................................................................................................94
3.4.3 Direct addressing .......................................................................................................................95
3.4.4 Short direct addressing ..............................................................................................................96
3.4.5 SFR addressing..........................................................................................................................97
3.4.6 Register indirect addressing .......................................................................................................98
3.4.7 Based addressing.......................................................................................................................99
3.4.8 Based indexed addressing .......................................................................................................102
3.4.9 Stack addressing......................................................................................................................103
CHAPTER 4 PORT FUNCTIONS........................................................................................................104
4.1 Port Functions........................................................................................................................104
4.2 Port Configuration .................................................................................................................107
4.2.1 Port 0........................................................................................................................................108
4.2.2 Port 1........................................................................................................................................114
4.2.3 Port 2........................................................................................................................................120
4.2.4 Port 3........................................................................................................................................122
4.2.5 Port 4........................................................................................................................................123
4.2.6 Port 5........................................................................................................................................132
4.2.7 Port 6........................................................................................................................................134
4.2.8 Port 7........................................................................................................................................137
4.2.9 Port 8........................................................................................................................................138
4.2.10 Port 11......................................................................................................................................139
4.2.11 Port 12......................................................................................................................................140
4.2.12 Port 13......................................................................................................................................143
4.2.13 Port 14......................................................................................................................................145
4.2.14 Port 15......................................................................................................................................149
4.3 Registers Controlling Port Function ....................................................................................150
4.4 Port Function Operations......................................................................................................157
4.4.1 Writing to I/O port .....................................................................................................................157
4.4.2 Reading from I/O port...............................................................................................................157
4.4.3 Operations on I/O port..............................................................................................................157
4.4.4 Connecting to external device with different potential (2.5V, 3 V) ............................................158
User’s Manual U17894EJ9V0UD
10
4.5 Settings of Port Mode Register and Output Latch When Using Alternate
Function ..................................................................................................................................160
4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn)................................163
CHAPTER 5 EXTERNAL BUS INTERFACE .....................................................................................164
5.1 Functions of External Bus Interface ....................................................................................164
5.2 Registers Controlling External Bus Interface Functions ...................................................170
5.3 Setting Port Mode Register and Output Latch ....................................................................173
5.4 Number of Instruction Wait Clocks for Data Access..........................................................174
5.5 Number of Instruction Execution Clocks and Instruction Wait Clocks for Fetch
Access.....................................................................................................................................174
5.6 Number of Instruction Wait Clocks for External Wait Pin..................................................175
5.7 Timing of External Bus Interface Function..........................................................................176
5.7.1 Multiplexed bus mode...............................................................................................................177
5.7.2 Separate bus mode ..................................................................................................................181
5.8 Example of Connection to Memory ......................................................................................185
5.8.1 Connection of external logic (ASIC, etc.)..................................................................................185
5.8.2 Connection of synchronous memory ........................................................................................185
5.8.3 Connection of asynchronous memory ......................................................................................186
CHAPTER 6 CLOCK GENERATOR ...................................................................................................187
6.1 Functions of Clock Generator...............................................................................................187
6.2 Configuration of Clock Generator ........................................................................................188
6.3 Registers Controlling Clock Generator ...............................................................................190
6.4 System Clock Oscillator ........................................................................................................204
6.4.1 X1 oscillator ..............................................................................................................................204
6.4.2 XT1 oscillator............................................................................................................................204
6.4.3 Internal high-speed oscillator....................................................................................................207
6.4.4 Internal low-speed oscillator .....................................................................................................207
6.4.5 Prescaler ..................................................................................................................................207
6.5 Clock Generator Operation ...................................................................................................208
6.6 Controlling Clock ...................................................................................................................212
6.6.1 Example of controlling high-speed system clock ......................................................................212
6.6.2 Example of controlling internal high-speed oscillation clock .....................................................215
6.6.3 Example of controlling subsystem clock ...................................................................................217
6.6.4 Example of controlling internal low-speed oscillation clock ......................................................219
6.6.5 CPU clock status transition diagram.........................................................................................220
6.6.6 Condition before changing CPU clock and processing after changing CPU clock ...................225
6.6.7 Time required for switchover of CPU clock and main system clock .........................................227
6.6.8 Conditions before clock oscillation is stopped ..........................................................................228
CHAPTER 7 TIMER ARRAY UNIT.....................................................................................................229
7.1 Functions of Timer Array Unit ..............................................................................................229
7.1.1 Functions of each channel when it operates independently .....................................................229
7.1.2 Functions of each channel when it operates with another channel...........................................230
7.1.3 LIN-bus supporting function (channel 7 only) ...........................................................................230
User’s Manual U17894EJ9V0UD 11
7.2 Configuration of Timer Array Unit........................................................................................231
7.3 Registers Controlling Timer Array Unit ...............................................................................236
7.4 Channel Output (TO0n pin) Control .....................................................................................257
7.4.1 TO0n pin output circuit configuration........................................................................................257
7.4.2 TO0n pin output setting ............................................................................................................258
7.4.3 Cautions on channel output operation......................................................................................258
7.4.4 Collective manipulation of TO0n bits ........................................................................................262
7.4.5 Timer interrupt and TO0n pin output at count operation start ...................................................263
7.5 Channel Input (TI0n Pin) Control..........................................................................................264
7.5.1 TI0n edge detector ...................................................................................................................264
7.6 Basic Function of Timer Array Unit .....................................................................................265
7.6.1 Overview of single-operation function and combination operation function..............................265
7.6.2 Basic rules of combination operation function ..........................................................................265
7.6.3 Applicable range of basic rules of combination operation function...........................................266
7.7 Operation of Timer Array Unit as Independent Channel ...................................................267
7.7.1 Operation as interval timer/square wave output .......................................................................267
7.7.2 Operation as external event counter ........................................................................................273
7.7.3 Operation as frequency divider (channel 0 only) ......................................................................276
7.7.4 Operation as input pulse interval measurement .......................................................................280
7.7.5 Operation as input signal high-/low-level width measurement..................................................284
7.8 Operation of Plural Channels of Timer Array Unit..............................................................288
7.8.1 Operation as PWM function......................................................................................................288
7.8.2 Operation as one-shot pulse output function............................................................................295
7.8.3 Operation as multiple PWM output function .............................................................................302
CHAPTER 8 REAL-TIME COUNTER..................................................................................................309
8.1 Functions of Real-Time Counter ..........................................................................................309
8.2 Configuration of Real-Time Counter....................................................................................309
8.3 Registers Controlling Real-Time Counter ...........................................................................311
8.4 Real-Time Counter Operation ...............................................................................................326
8.4.1 Starting operation of real-time counter .....................................................................................326
8.4.2 Shifting to STOP mode after starting operation........................................................................327
8.4.3 Reading/writing real-time counter.............................................................................................328
8.4.4 Setting alarm of real-time counter ............................................................................................330
8.4.5 1 Hz output of real-time counter ...............................................................................................331
8.4.6 32.768 kHz output of real-time counter ....................................................................................331
8.4.7 512 Hz, 16.384 kHz output of real-time counter .......................................................................331
8.4.8 Example of watch error correction of real-time counter ............................................................332
CHAPTER 9 WATCHDOG TIMER ......................................................................................................337
9.1 Functions of Watchdog Timer ..............................................................................................337
9.2 Configuration of Watchdog Timer........................................................................................338
9.3 Register Controlling Watchdog Timer .................................................................................339
9.4 Operation of Watchdog Timer ..............................................................................................340
9.4.1 Controlling operation of watchdog timer ...................................................................................340
9.4.2 Setting overflow time of watchdog timer...................................................................................341
9.4.3 Setting window open period of watchdog timer ........................................................................342
9.4.4 Setting watchdog timer interval interrupt ..................................................................................343
User’s Manual U17894EJ9V0UD
12
CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER..............................................344
10.1 Functions of Clock Output/Buzzer Output Controller........................................................344
10.2 Configuration of Clock Output/Buzzer Output Controller .................................................345
10.3 Registers Controlling Clock Output/Buzzer Output Controller.........................................345
10.4 Operations of Clock Output/Buzzer Output Controller ......................................................347
10.4.1 Operation as output pin ............................................................................................................347
CHAPTER 11 A/D CONVERTER ........................................................................................................348
11.1 Function of A/D Converter ....................................................................................................348
11.2 Configuration of A/D Converter............................................................................................349
11.3 Registers Used in A/D Converter .........................................................................................351
11.4 A/D Converter Operations.....................................................................................................360
11.4.1 Basic operations of A/D converter ............................................................................................360
11.4.2 Input voltage and conversion results ........................................................................................362
11.4.3 A/D converter operation mode..................................................................................................363
11.5 Temperature Sensor Function (Expanded-Specification Products
(
μ
PD78F116xA) Only).............................................................................................................365
11.5.1 Configuration of temperature sensor ........................................................................................365
11.5.2 Registers used by temperature sensors ...................................................................................366
11.5.3 Temperature sensor operation .................................................................................................368
11.5.4 Procedures for using temperature sensors...............................................................................370
11.6 How to Read A/D Converter Characteristics Table.............................................................373
11.7 Cautions for A/D Converter...................................................................................................375
CHAPTER 12 D/A CONVERTER ........................................................................................................380
12.1 Function of D/A Converter ....................................................................................................380
12.2 Configuration of D/A Converter............................................................................................380
12.3 Registers Used in D/A Converter .........................................................................................382
12.4 Operation of D/A Converter...................................................................................................385
12.4.1 Operation in normal mode ........................................................................................................385
12.4.2 Operation in real-time output mode ..........................................................................................386
12.4.3 Cautions ...................................................................................................................................387
CHAPTER 13 SERIAL ARRAY UNIT.................................................................................................388
13.1 Functions of Serial Array Unit ..............................................................................................388
13.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20) .......................................................................388
13.1.2 UART (UART0, UART1, UART2, UART3) ...............................................................................389
13.1.3 Simplified I2C (IIC10, IIC20)......................................................................................................390
13.2 Configuration of Serial Array Unit........................................................................................391
13.3 Registers Controlling Serial Array Unit ...............................................................................396
13.4 Operation Stop Mode.............................................................................................................418
13.4.1 Stopping the operation by units ................................................................................................418
13.4.2 Stopping the operation by channels .........................................................................................419
13.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20) Communication .................421
13.5.1 Master transmission .................................................................................................................422
13.5.2 Master reception.......................................................................................................................431
User’s Manual U17894EJ9V0UD 13
13.5.3 Master transmission/reception..................................................................................................439
13.5.4 Slave transmission ...................................................................................................................447
13.5.5 Slave reception.........................................................................................................................456
13.5.6 Slave transmission/reception....................................................................................................462
13.5.7 Calculating transfer clock frequency.........................................................................................471
13.5.8 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10,
CSI20) communication .............................................................................................................473
13.6 Operation of UART (UART0, UART1, UART2, UART3) Communication...........................474
13.6.1 UART transmission ..................................................................................................................475
13.6.2 UART reception........................................................................................................................485
13.6.3 LIN transmission.......................................................................................................................492
13.6.4 LIN reception............................................................................................................................495
13.6.5 Calculating baud rate ...............................................................................................................500
13.6.6 Procedure for processing errors that occurred during UART (UART0, UART1, UART2, UART3)
communication .........................................................................................................................504
13.7 Operation of Simplified I2C (IIC10, IIC20) Communication...................................................505
13.7.1 Address field transmission........................................................................................................506
13.7.2 Data transmission.....................................................................................................................511
13.7.3 Data reception ..........................................................................................................................514
13.7.4 Stop condition generation.........................................................................................................518
13.7.5 Calculating transfer rate ...........................................................................................................519
13.7.6 Procedure for processing errors that occurred during simplified I2C (IIC10, IIC20) communication
.................................................................................................................................................522
13.8 Relationship Between Register Settings and Pins.............................................................523
CHAPTER 14 SERIAL INTERFACE IIC0 ..........................................................................................530
14.1 Functions of Serial Interface IIC0.........................................................................................530
14.2 Configuration of Serial Interface IIC0 ..................................................................................533
14.3 Registers to Controlling Serial Interface IIC0 .....................................................................536
14.4 I2C Bus Mode Functions ........................................................................................................548
14.4.1 Pin configuration.......................................................................................................................548
14.5 I 2C Bus Definitions and Control Methods ...........................................................................549
14.5.1 Start conditions.........................................................................................................................549
14.5.2 Addresses ................................................................................................................................550
14.5.3 Transfer direction specification.................................................................................................550
14.5.4 Transfer clock setting method ..................................................................................................551
14.5.5 Acknowledge (ACK) .................................................................................................................552
14.5.6 Stop condition...........................................................................................................................554
14.5.7 Wait ..........................................................................................................................................555
14.5.8 Canceling wait ..........................................................................................................................557
14.5.9 Interrupt request (INTIIC0) generation timing and wait control .................................................558
14.5.10 Address match detection method .............................................................................................559
14.5.11 Error detection..........................................................................................................................559
14.5.12 Extension code.........................................................................................................................559
14.5.13 Arbitration.................................................................................................................................560
14.5.14 Wakeup function.......................................................................................................................561
14.5.15 Communication reservation......................................................................................................562
14.5.16 Cautions ...................................................................................................................................566
User’s Manual U17894EJ9V0UD
14
14.5.17 Communication operations.......................................................................................................567
14.5.18 Timing of I2C interrupt request (INTIIC0) occurrence................................................................575
14.6 Timing Charts .........................................................................................................................596
CHAPTER 15 MULTIPLIER..................................................................................................................603
15.1 Functions of Multiplier...........................................................................................................603
15.2 Configuration of Multiplier ....................................................................................................604
15.3 Operation of Multiplier...........................................................................................................605
CHAPTER 16 DMA CONTROLLER....................................................................................................606
16.1 Functions of DMA Controller ................................................................................................606
16.2 Configuration of DMA Controller..........................................................................................607
16.3 Registers Controlling DMA Controller .................................................................................610
16.4 Operation of DMA Controller ................................................................................................614
16.4.1 Operation procedure.................................................................................................................614
16.4.2 Transfer mode ..........................................................................................................................616
16.4.3 Termination of DMA transfer ....................................................................................................616
16.5 Example of Setting of DMA Controller.................................................................................617
16.5.1 CSI consecutive transmission ..................................................................................................617
16.5.2 CSI master reception................................................................................................................619
16.5.3 CSI transmission/reception.......................................................................................................621
16.5.4 Consecutive capturing of A/D conversion results .....................................................................623
16.5.5 UART consecutive reception + ACK transmission....................................................................625
16.5.6 Holding DMA transfer pending by DWAITn ..............................................................................627
16.5.7 Forced termination by software ................................................................................................628
16.6 Cautions on Using DMA Controller ......................................................................................630
CHAPTER 17 INTERRUPT FUNCTIONS ...........................................................................................633
17.1 Interrupt Function Types.......................................................................................................633
17.2 Interrupt Sources and Configuration ...................................................................................633
17.3 Registers Controlling Interrupt Functions ..........................................................................638
17.4 Interrupt Servicing Operations .............................................................................................648
17.4.1 Maskable interrupt acknowledgment ........................................................................................648
17.4.2 Software interrupt request acknowledgment ............................................................................650
17.4.3 Multiple interrupt servicing........................................................................................................651
17.4.4 Interrupt request hold ...............................................................................................................654
CHAPTER 18 KEY INTERRUPT FUNCTION ....................................................................................655
18.1 Functions of Key Interrupt ....................................................................................................655
18.2 Configuration of Key Interrupt..............................................................................................655
18.3 Register Controlling Key Interrupt .......................................................................................656
CHAPTER 19 STANDBY FUNCTION .................................................................................................657
19.1 Standby Function and Configuration...................................................................................657
19.1.1 Standby function.......................................................................................................................657
19.1.2 Registers controlling standby function ......................................................................................657
User’s Manual U17894EJ9V0UD 15
19.2 Standby Function Operation.................................................................................................660
19.2.1 HALT mode ..............................................................................................................................660
19.2.2 STOP mode..............................................................................................................................665
CHAPTER 20 RESET FUNCTION ......................................................................................................672
20.1 Register for Confirming Reset Source ................................................................................680
CHAPTER 21 POWER-ON-CLEAR CIRCUIT ....................................................................................681
21.1 Functions of Power-on-Clear Circuit ...................................................................................681
21.2 Configuration of Power-on-Clear Circuit.............................................................................682
21.3 Operation of Power-on-Clear Circuit ...................................................................................682
21.4 Cautions for Power-on-Clear Circuit....................................................................................685
CHAPTER 22 LOW-VOLTAGE DETECTOR ......................................................................................687
22.1 Functions of Low-Voltage Detector .....................................................................................687
22.2 Configuration of Low-Voltage Detector...............................................................................688
22.3 Registers Controlling Low-Voltage Detector ......................................................................688
22.4 Operation of Low-Voltage Detector......................................................................................693
22.4.1 When used as reset .................................................................................................................694
22.4.2 When used as interrupt ............................................................................................................700
22.5 Cautions for Low-Voltage Detector......................................................................................706
CHAPTER 23 REGULATOR ................................................................................................................710
23.1 Regulator Overview ...............................................................................................................710
23.2 Registers Controlling Regulator...........................................................................................710
CHAPTER 24 OPTION BYTE..............................................................................................................712
24.1 Functions of Option Bytes ....................................................................................................712
24.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H) ....................................................712
24.1.2 On-chip debug option byte (000C3H/ 010C3H)........................................................................713
24.2 Format of User Option Byte ..................................................................................................713
24.3 Format of On-chip Debug Option Byte ................................................................................715
24.4 Setting of Option Byte ...........................................................................................................716
CHAPTER 25 FLASH MEMORY.........................................................................................................717
25.1 Writing with Flash Memory Programmer.............................................................................717
25.2 Programming Environment...................................................................................................721
25.3 Communication Mode ...........................................................................................................721
25.4 Connection of Pins on Board ...............................................................................................722
25.4.1 FLMD0 pin................................................................................................................................722
25.4.2 TOOL0 pin................................................................................................................................723
25.4.3 RESET pin................................................................................................................................723
25.4.4 Port pins ...................................................................................................................................724
25.4.5 REGC pin .................................................................................................................................724
25.4.6 X1 and X2 pins .........................................................................................................................724
25.4.7 Power supply............................................................................................................................724
User’s Manual U17894EJ9V0UD
16
25.5 Registers that Control Flash Memory ..................................................................................724
25.6 Programming Method ............................................................................................................725
25.6.1 Controlling flash memory..........................................................................................................725
25.6.2 Flash memory programming mode...........................................................................................725
25.6.3 Selecting communication mode................................................................................................726
25.6.4 Communication commands ......................................................................................................726
25.7 Security Settings....................................................................................................................728
25.8 Processing Time of Each Command When Using PG-FP4 or PG-FP5 (Reference
Values).....................................................................................................................................730
25.9 Flash Memory Programming by Self-Programming...........................................................731
25.9.1 Boot swap function ...................................................................................................................733
25.9.2 Flash shield window function....................................................................................................735
CHAPTER 26 ON-CHIP DEBUG FUNCTION ....................................................................................736
26.1 Connecting QB-MINI2 to 78K0R/KG3 ...................................................................................736
26.2 On-Chip Debug Security ID ...................................................................................................737
26.3 Securing of User Resources.................................................................................................737
CHAPTER 27 BCD CORRECTION CIRCUIT ....................................................................................739
27.1 BCD Correction Circuit Function..........................................................................................739
27.2 Registers Used by BCD Correction Circuit .........................................................................739
27.3 BCD Correction Circuit Operation........................................................................................740
CHAPTER 28 INSTRUCTION SET.......................................................................................................742
28.1 Conventions Used in Operation List....................................................................................743
28.1.1 Operand identifiers and specification methods.........................................................................743
28.1.2 Description of operation column ...............................................................................................744
28.1.3 Description of flag operation column ........................................................................................745
28.1.4 PREFIX instruction ...................................................................................................................745
28.2 Operation List.........................................................................................................................746
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS).................................763
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) ..................................827
CHAPTER 31 PACKAGE DRAWINGS ...............................................................................................889
CHAPTER 32 RECOMMENDED SOLDERING CONDITIONS..........................................................891
APPENDIX A DEVELOPMENT TOOLS..............................................................................................893
A.1 Software Package ..................................................................................................................896
A.2 Language Processing Software............................................................................................896
A.3 Control Software ....................................................................................................................897
A.4 Flash Memory Programming Tools......................................................................................897
User’s Manual U17894EJ9V0UD 17
A.4.1 When using flash memory programmers PG-FP5, FL-PR5, PG-FP4 and FL-PR4 ..................897
A.4.2 When using on-chip debug emulator with programming function QB-MINI2 ............................898
A.5 Debugging Tools (Hardware)................................................................................................898
A.5.1 When using in-circuit emulator QB-78K0RKX3 ........................................................................898
A.5.2 When using on-chip debug emulator with programming function QB-MINI2 ............................899
A.6 Debugging Tools (Software) .................................................................................................899
APPENDIX B LIST OF CAUTIONS....................................................................................................900
APPENDIX C REVISION HISTORY ....................................................................................................935
C.1 Major Revisions in This Edition............................................................................................935
C.2 Revision History of Preceding Editions ..............................................................................940
User’s Manual U17894EJ9V0UD
18
CHAPTER 1 OUTLINE
1.1 Differences Between Conventional-Specification Products (
μ
PD78F116x) and Expanded-
Specification Products (
μ
PD78F116xA)
This manual describes the functions of the 78K0R/KG3 microcontroller products with conventional specifications
(
μ
PD78F116x) and expanded specifications (
μ
PD78F116xA).
The differences between the conventional-specification products (
μ
PD78F116x) and expanded-specification
products (
μ
PD78F116xA) of the 78K0R/KG3 microcontrollers are described below.
Item Conditions Conventional-
Specification
Products
Expanded-
Specification
Products
Reference in This
Manual
Temperature sensor
function
Channel 0 and channel 1 of
the A/D converter are used.
Internal high-speed
oscillator operating
None Available 11.5 Temperature
Sensor Function
4.0 V ≤ AVREF0 ≤ 5.5 V
fAD = 0.6 to 3.6 MHz
4.0 V ≤ AVREF0 ≤ 5.5 V
fAD = 0.33 to 3.6 MHz
Expansion of
frequency range of
conversion clock (fAD)
in A/D converter
(support of low-speed
conversion time)
When the LV1 and LV0 bits
of the A/D converter mode
register (ADM) are set to 0
2.7 V ≤ AVREF0 < 4.0 V
fAD = 0.6 to 1.8 MHz
2.7 V ≤ AVREF0 < 4.0 V
fAD = 0.33 to 1.8 MHz
11.3 (2) A/D converter
mode register (ADM)
Improvement of A/D
converter conversion
accuracy
Overall error when 2.7 V ≤
AVREF0 < 4.0 V
Zero-scale error, full-scale
error, integral linearity
error, and differential
linearity error when 2.3 V ≤
AVREF0 < 4.0 V
− Improved CHAPTER 29
ELECTRICAL
SPECIFICATIONS
(STANDARD
PRODUCTS), A/D
Converter
Characteristics
Number of rewrites Used for updating
programs
When using flash memory
programmer and NEC
Electronics self
programming library
100 1000
Expansion of
EEPROMTM
emulation data
retention period
Used for updating data.
When EEPROM emulation
library provided by NEC
Electronics is used (usable
ROM size: 6 KB, which
consists of 3 consecutive
blocks)
3 years 5 years
CHAPTER 29
ELECTRICAL
SPECIFICATIONS
(STANDARD
PRODUCTS), Flash
Memory Programming
Characteristics
Expansion of operating
voltage in simplified I2C
mode (serial array unit)
1.8 V ≤ VDD < 2.7 V, during
communication at same
potential
Not supported Supported CHAPTER 29
ELECTRICAL
SPECIFICATIONS
(STANDARD
PRODUCTS), Serial
Interface, (d) During
communication at same
potential (simplified I2C
mode)
Expansion of operating
voltage of external bus
interface
1.8 V ≤ VDD < 2.7 V,
synchronous
separate/synchronous
multiplexed/asynchronous
separate mode
Not supported Supported CHAPTER 29
ELECTRICAL
SPECIFICATIONS
(STANDARD
PRODUCTS), External
Bus Interface
Support for (A) grade
product specifications
− Not supported Supported CHAPTER 30
ELECTRICAL
SPECIFICATIONS ((A)
GRADE PRODUCTS
<R>
CHAPTER 1 OUTLINE
User’s Manual U17894EJ9V0UD 19
1.2 Features
{ Minimum instruction execution time can be changed from high speed (0.05
μ
s: @ 20 MHz operation with high-
speed system clock) to ultra low-speed (61
μ
s: @ 32.768 kHz operation with subsystem clock)
{ General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
{ ROM, RAM capacities
Item
Part Number
Program Memory
(ROM)
Data Memory
(RAM)
μ
PD78F1162
μ
PD78F1162A
64 KB 4 KB
μ
PD78F1163
μ
PD78F1163A
96 KB 6 KB
μ
PD78F1164
μ
PD78F1164A
128 KB 8 KB
μ
PD78F1165
μ
PD78F1165A
192 KB 10 KB
μ
PD78F1166
μ
PD78F1166A
256 KB 12 KB
μ
PD78F1167
μ
PD78F1167A
384 KB 24 KB
μ
PD78F1168
μ
PD78F1168A
Flash memory
512 KB 30 KB
{ On-chip single-power-supply flash memory (with prohibition of chip erase/block erase/writing function)
{ Self-programming (with boot swap function/flash shield window function)
{ On-chip debug function
{ On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
{ On-chip watchdog timer (operable with the internal low-speed oscillation clock)
{ On-chip multiplier (16 bits × 16 bits)
{ On-chip functions of external bus interface
{ On-chip key interrupt function
{ On-chip clock output/buzzer output controller
{ On-chip BCD adjustment
{ I/O ports: 88 (N-ch open drain: 4)
{ Timer: 10 channels
• 16-bit timer: 8 channels
• Watchdog timer: 1 channel
• Real-time counter: 1 channel
{ Serial interface
• CSI: 2 channels/UART: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• UART (LIN-bus supported): 1 channel
• I
2C: 1 channel
{ 10-bit resolution A/D converter (AVREF0 = 2.3 to 5.5 V): 16 channels
{ 8-bit resolution D/A converter (AVREF1 = 1.8 to 5.5 V): 2 channels
{ Power supply voltage: VDD = 1.8 to 5.5 V
{ Operating ambient temperature: TA = −40 to +85°C
CHAPTER 1 OUTLINE
User’s Manual U17894EJ9V0UD
20
1.3 Applications
{ Home appliances
• Laser printer motors
• Clothes washers
• Air conditioners
• Refrigerators
{ Home audio systems
{ Digital cameras, digital video cameras
CHAPTER 1 OUTLINE
User’s Manual U17894EJ9V0UD 21
1.4 Ordering Information
• Flash memory version
Part Number Package Quality Grade
μ
PD78F1162GC-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
μ
PD78F1162AGC-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
μ
PD78F1163GC-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
μ
PD78F1163AGC-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
μ
PD78F1164GC-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
μ
PD78F1164AGC-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
μ
PD78F1165GC-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
μ
PD78F1165AGC-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
μ
PD78F1166GC-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
μ
PD78F1166AGC-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
μ
PD78F1167GC-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
μ
PD78F1167AGC-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
μ
PD78F1168GC-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
μ
PD78F1168AGC-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Standard
μ
PD78F1162AGC(A)-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Special
μ
PD78F1163AGC(A)-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Special
μ
PD78F1164AGC(A)-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Special
μ
PD78F1165AGC(A)-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Special
μ
PD78F1166AGC(A)-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Special
μ
PD78F1167AGC(A)-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Special
μ
PD78F1168AGC(A)-UEU-AX 100-pin plastic LQFP (fine pitch) (14 × 14)
Special
μ
PD78F1162GF-GAS-AX 100-pin plastic LQFP (14 × 20) Standard
μ
PD78F1162AGF-GAS-AX 100-pin plastic LQFP (14 × 20) Standard
μ
PD78F1163GF-GAS-AX 100-pin plastic LQFP (14 × 20) Standard
μ
PD78F1163AGF-GAS-AX 100-pin plastic LQFP (14 × 20) Standard
μ
PD78F1164GF-GAS-AX 100-pin plastic LQFP (14 × 20) Standard
μ
PD78F1164AGF-GAS-AX 100-pin plastic LQFP (14 × 20) Standard
μ
PD78F1165GF-GAS-AX 100-pin plastic LQFP (14 × 20) Standard
μ
PD78F1165AGF-GAS-AX 100-pin plastic LQFP (14 × 20) Standard
μ
PD78F1166GF-GAS-AX 100-pin plastic LQFP (14 × 20) Standard
μ
PD78F1166AGF-GAS-AX 100-pin plastic LQFP (14 × 20) Standard
μ
PD78F1167GF-GAS-AX 100-pin plastic LQFP (14 × 20) Standard
μ
PD78F1167AGF-GAS-AX 100-pin plastic LQFP (14 × 20) Standard
μ
PD78F1168GF-GAS-AX 100-pin plastic LQFP (14 × 20) Standard
μ
PD78F1168AGF-GAS-AX 100-pin plastic LQFP (14 × 20) Standard
μ
PD78F1162AGF(A)-GAS-AX 100-pin plastic LQFP (14 × 20) Special
μ
PD78F1163AGF(A)-GAS-AX 100-pin plastic LQFP (14 × 20) Special
μ
PD78F1164AGF(A)-GAS-AX 100-pin plastic LQFP (14 × 20) Special
μ
PD78F1165AGF(A)-GAS-AX 100-pin plastic LQFP (14 × 20) Special
μ
PD78F1166AGF(A)-GAS-AX 100-pin plastic LQFP (14 × 20) Special
μ
PD78F1167AGF(A)-GAS-AX 100-pin plastic LQFP (14 × 20) Special
μ
PD78F1168AGF(A)-GAS-AX 100-pin plastic LQFP (14 × 20) Special
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the device and its
recommended applications.
CHAPTER 1 OUTLINE
User’s Manual U17894EJ9V0UD
22
1.5 Pin Configuration (Top View)
• 100-pin plastic LQFP (14 × 20)
P140/PCLBUZ0/INTP6
P141/PCLBUZ1/INTP7
P142/SCK20/SCL20
P143/SI20/RxD2/SDA20
P144/SO20/TxD2
P145/TI07/TO07
P00/TI00
P01/TO00
P02/SO10/TxD1
P03/SI10/RxD1/SDA10
P04/SCK10/SCL10
P131/TI06/TO06
P130
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P150/ANI8
P151/ANI9
P152/ANI10
P153/ANI11
P154/ANI12
P155/ANI13
P156/ANI14
P157/ANI15
AV
SS
P50/EX8
P51/EX9
P52/EX10
P53/EX11
P54/EX12
P55/EX13
P56/EX14
P57/EX15
P17/EX31/TI02/TO02
P16/EX30/TI01/TO01/INTP5
P15/EX29/RTCDIV/RTCCL
P14/EX28/RxD3
P13/EX27/TxD3
P12/EX26/SO00/TxD0
P11/EX25/SI00/RxD0
P10/EX24/SCK00
AV
REF1
P110/ANO0
P111/ANO1
AV
REF0
EV
DD0
V
DD
EV
SS0
V
SS
REGC
P121/X1
P122/X2/EXCLK
FLMD0
P123/XT1
P124/XT2
RESET
P40/TOOL0
P41/TOOL1
P42/TI04/TO04
P43/SCK01
P44/SI01
P45/SO01
P46/INTP1/TI05/TO05
P47/INTP2
P120/INTP0/EXLVI
P60/SCL0
P61/SDA0
P62
P63
P31/TI03/TO03/INTP4
P64/RD
P65/WR0
P66/WR1
P67/ASTB
P77/EX23/KR7/INTP11
P76/EX22/KR6/INTP10
P75/EX21/KR5/INTP9
P74/EX20/KR4/INTP8
P73/EX19/KR3
P72/EX18/KR2
P71/EX17/KR1
P70/EX16/KR0
P06/WAIT
P05/CLKOUT
EV
SS1
P80/EX0
P81/EX1
P82/EX2
P83/EX3
P84/EX4
P85/EX5
P86/EX6
P87/EX7
P30/INTP3/RTC1HZ
EV
DD1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
Cautions 1. Make AVSS, EVSS0, and EVSS1 the same potential as VSS.
2. Make EVDD0 and EVDD1 the same potential as VDD.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F).
4. P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 are set as analog inputs in the order of
P157/ANI15, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port configuration register
(ADPC). When using P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 as analog inputs,
start designing from P157/ANI15 (see 11.3 (6) A/D port configuration register (ADPC) for
details).
Remark When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD and two EVDD pins and
connect the VSS and two EVSS pins to separate ground lines.
CHAPTER 1 OUTLINE
User’s Manual U17894EJ9V0UD 23
• 100-pin plastic LQFP (fine pitch) (14 × 14)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P157/ANI15
AV
SS
AV
REF0
P111/ANO1
P110/ANO0
AV
REF1
P10/EX24/SCK00
P11/EX25/SI00/RxD0
P12/EX26/SO00/TxD0
P13/EX27/TxD3
P14/EX28/RxD3
P15/EX29/RTCDIV/RTCCL
P16/EX30/TI01/TO01/INTP5
P17/EX31/TI02/TO02
P57/EX15
P56/EX14
P55/EX13
P54/EX12
P53/EX11
P52/EX10
P51/EX9
P50/EX8
EV
DD1
P30/INTP3/RTC1HZ
P87/EX7
P143/SI20/RxD2/SDA20
P144/SO20/TxD2
P145/TI07/TO07
P00/TI00
P01/TO00
P02/SO10/TxD1
P03/SI10/RxD1/SDA10
P04/SCK10/SCL10
P131/TI06/TO06
P130
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P150/ANI8
P151/ANI9
P152/ANI10
P153/ANI11
P154/ANI12
P155/ANI13
P156/ANI14
P62
P63
P31/TI03/TO03/INTP4
P64/RD
P65/WR0
P66/WR1
P67/ASTB
P77/EX23/KR7/INTP11
P76/EX22/KR6/INTP10
P75/EX21/KR5/INTP9
P74/EX20/KR4/INTP8
P73/EX19/KR3
P72/EX18/KR2
P71/EX17/KR1
P70/EX16/KR0
P06/WAIT
P05/CLKOUT
EV
SS1
P80/EX0
P81/EX1
P82/EX2
P83/EX3
P84/EX4
P85/EX5
P86/EX6
P142/SCK20/SCL20
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
P120/INTP0/EXLVI
P47/INTP2
P46/INTP1/TI05/TO05
P45/SO01
P44/SI01
P43/SCK01
P42/TI04/TO04
P41/TOOL1
P40/TOOL0
RESET
P124/XT2
P123/XT1
FLMD0
P122/X2/EXCLK
P121/X1
REGC
V
SS
EV
SS0
V
DD
EV
DD0
P60/SCL0
P61/SDA0
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
Cautions 1. Make AVSS, EVSS0, and EVSS1 the same potential as VSS.
2. Make EVDD0 and EVDD1 the same potential as VDD.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F).
4. P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 are set as analog inputs in the order of
P157/ANI15, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port configuration register
(ADPC). When using P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 as analog inputs,
start designing from P157/ANI15 (see 11.3 (6) A/D port configuration register (ADPC) for
details).
Remark When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the VDD and two EVDD pins and
connect the VSS and two EVSS pins to separate ground lines.
CHAPTER 1 OUTLINE
User’s Manual U17894EJ9V0UD
24
Pin Identification
ANI0 to ANI15: Analog input
ANO0, ANO1: Analog output
ASTB: Address strobe
AVREF0, AVREF1: Analog reference voltage
AVSS : Analog ground
CLKOUT: Clock output
EVDD0, EVDD1: Power supply for port
EVSS0, EVSS1: Ground for port
EX0 to EX31: External extension bus
EXCLK: External clock input
(main system clock)
EXLVI: External potential input
for low-voltage detector
FLMD0: Flash programming mode
INTP0 to INTP11: External interrupt input
KR0 to KR7: Key return
P00 to P06: Port 0
P10 to P17: Port 1
P20 to P27: Port 2
P30, P31: Port 3
P40 to P47: Port 4
P50 to P57: Port 5
P60 to P67: Port 6
P70 to P77: Port 7
P80 to P87: Port 8
P110, P111: Port 11
P120 to P124: Port 12
P130, P131: Port 13
P140 to P145: Port 14
P150 to P157: Port 15
PCLBUZ0, PCLBUZ1: Programmable clock output/
buzzer output
RD: Read strobe
REGC: Regulator capacitance
RESET: Reset
RTC1HZ: Real-time counter correction clock
(1 Hz) output
RTCCL: Real-time counter clock (32 kHz
original oscillation) output
RTCDIV: Real-time counter clock (32 kHz
divided frequency) output
RxD0 to RxD3: Receive data
SCK00, SCK01,
SCK10, SCK20: Serial clock input/output
SCL0, SCL10, SCL20: Serial clock input/output
SDA0, SDA10, SDA20: Serial data input/output
SI00, SI01,
SI10, SI20: Serial data input
SO00, SO01,
SO10, SO20: Serial data output
TI00 to TI07: Timer input
TO00 to TO07: Timer output
TOOL0: Data input/output for tool
TOOL1: Clock output for tool
TxD0 to TxD3: Transmit data
VDD: Power supply
VSS: Ground
WAIT: Wait
WR0: Lower byte write strobe
WR1: Upper byte write strobe
X1, X2: Crystal oscillator (main system
clock)
XT1, XT2: Crystal oscillator (subsystem clock)
CHAPTER 1 OUTLINE
User’s Manual U17894EJ9V0UD 25
1.6 78K0R/Kx3 Microcontroller Lineup
78K0R/KE3 78K0R/KF3 78K0R/KG3 78K0R/KH3 78K0R/KJ3 ROM RAM
64 Pins 80 Pins 100 Pins 128 Pins 144 Pins
μ
PD78F1168
μ
PD78F1178 512 KB 30 KB − −
μ
PD78F1168A
μ
PD78F1178A
μ
PD78F1188A
μ
PD78F1167
μ
PD78F1177 384 KB 24 KB − −
μ
PD78F1167A
μ
PD78F1177A
μ
PD78F1187A
μ
PD78F1146
μ
PD78F1156
μ
PD78F1166
μ
PD78F1176 256 KB 12 KB
μ
PD78F1146A
μ
PD78F1156A
μ
PD78F1166A
μ
PD78F1176A
μ
PD78F1186A
μ
PD78F1145
μ
PD78F1155
μ
PD78F1165
μ
PD78F1175 192 KB 10 KB
μ
PD78F1145A
μ
PD78F1155A
μ
PD78F1165A
μ
PD78F1175A
μ
PD78F1185A
μ
PD78F1144
μ
PD78F1154
μ
PD78F1164
μ
PD78F1174 128 KB 8 KB
μ
PD78F1144A
μ
PD78F1154A
μ
PD78F1164A
μ
PD78F1174A
μ
PD78F1184A
μ
PD78F1143
μ
PD78F1153
μ
PD78F1163 96 KB 6 KB
μ
PD78F1143A
μ
PD78F1153A
μ
PD78F1163A
− −
μ
PD78F1142
μ
PD78F1152
μ
PD78F1162 64 KB 4 KB
μ
PD78F1142A
μ
PD78F1152A
μ
PD78F1162A
− −
CHAPTER 1 OUTLINE
User’s Manual U17894EJ9V0UD
26
1.7 Block Diagram
Port 0 P00 to P06
7
Port 1 P10 to P17
Port 2 P20 to P27
8
Port 3 P30, P31
2
Port 4
Port 5
V
SS
,
EV
SS0,
EV
SS1
FLMD0
V
DD
,
EV
DD0,
EV
DD1
8
Port 6 P60 to P67
8
Port 7 P70 to P77
Port 12 P121 to P124
Port 13 P130
8
P40 to P47
8
P50 to P57
8
Port 14 P140 to P145
6
Buzzer output
PCLBUZ0/P140, PCLBUZ1/P141
Clock output control
Voltage regulator REGC
Interrupt control
RAM
78K/0R
CPU
core
Flash
memory
Window watchdog
timer
Internal
low-speed
oscillator
Power on clear/
low voltage indicator POC/LVI
control
Reset control
Key return 8KR0/P70 to
KR7/P77
EXLVI/P120
System control
RESET
X1/P121
X2/EXCLK/P122
Internal
high-speed
oscillator
XT1/P123
XT2/P124
Multiplier
On-chip debug TOOL0/P40
TOOL1/P41
Real-time counter
Direct memory
access control
Serial array
unit 0 (4 ch)
UART0
Serial array
unit 1 (4 ch)
UART3
LINSEL
UART1
CSI00
IIC1
RxD0/P11
TxD0/P12
RxD1/P03
TxD1/P02
SCK00/P10
SO00/P12
SI00/P11
SCL10/P04
SDA10/P03
RxD3/P14
TxD3/P13
Timer array
unit (8 ch)
Ch 0
Ch 1
TI00/P00
TO00/P01
TI01/TO01/P16
Ch 2
TI02/TO02/P17
Ch 3
TI03/TO03/P31
Ch 4TI04/TO04/P42
Ch 5
TI05/TO05/P46
Ch 6
TI06/TO06/P131
Ch 7
INTP1/P46,
INTP2/P47 2
INTP0/P120
INTP5/P16
INTP8/P74 to
INTP11/P77 4
INTP3/P30,
INTP4/P31 2
INTP6/P140,
INTP7/P141 2
RxD3/P14 (LINSEL)
CSI10
SCK10/P04
SO10/P02
SI10/P03
RxD3/P14 (LINSEL)
Serial interface IIC0
SDA0/P61
SCL0/P60
A/D converter
8ANI0/P20 to
ANI7/P27
AV
REF0
AV
SS
4
P120
2
Port 8 P80 to P87
8
Port 11 P110, P111
2
P131
Port 15 P150 to P157
8
D/A converter
ANO0/P110,
ANO1/P111
AV
REF1
AV
SS
2
8ANI8/P150 to
ANI15/P157
External extention
EX0/P80 to
EX7/P87
EX8/P50 to
EX15/P57
EX16/P70 to
EX23/P77
CSI01
SCK01/P43
SO01/P45
SI01/P44
IIC2
SCL20/P142
SDA20/P143
CSI20
SCK20/P142
SO20/P144
SI20/P143
8
8
EX24/P10 to
EX31/P17
RxD2/P143
TxD2/P144 UART2
RTC1HZ/P30
RTCDIV/RTCCL/P15
TI07/TO07/P145
BCD
adjustment
8
8
CHAPTER 1 OUTLINE
User’s Manual U17894EJ9V0UD 27
1.8 Outline of Functions
(1/2)
Item
μ
PD78F1162,
μ
PD78F1162A
μ
PD78F1163,
μ
PD78F1163A
μ
PD78F1164,
μ
PD78F1164
A
μ
PD78F1165,
μ
PD78F1165A
μ
PD78F1166,
μ
PD78F1166A
μ
PD78F1167,
μ
PD78F1167A
μ
PD78F1168,
μ
PD78F1168A
Flash memory
(self-programming
supported)
64 KB 96 KB 128 KB 192 KB 256 KB 384 KB 512 KB
Internal
memory
RAM 4 KB 6 KB 8 KB 10 KB 12 KB 24 KB 30 KB
Memory space 1 MB
External memory expansion
space
888 KB max. 824 KB max. 760 KB max. 696 KB max. 568 KB max. 440 KB max.
High-speed
system clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
2 to 20 MHz: VDD = 2.7 to 5.5 V, 2 to 5 MHz: VDD = 1.8 to 5.5 V
Main system
clock
(Oscillation
frequency)
Internal high-
speed oscillation
clock
Internal oscillation
8 MHz (TYP.): VDD = 1.8 to 5.5 V
Subsystem clock
(Oscillation frequency)
XT1 (crystal) oscillation
32.768 kHz (TYP.): VDD = 1.8 to 5.5 V
Internal low-speed oscillation
clock (For WDT)
Internal oscillation
240 kHz (TYP.): VDD = 1.8 to 5.5 V
General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
0.05
μ
s (High-speed system clock: fMX = 20 MHz operation)
0.125
μ
s (Internal high-speed oscillation clock: fIH = 8 MHz (TYP.) operation)
Minimum instruction execution
time
61
μ
s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set • 8-bit operation, 16-bit operation
• Multiply (8 bits × 8 bits)
• Bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port Total: 88
CMOS I/O: 79
CMOS input: 4
CMOS output: 1
N-ch open-drain I/O (6 V tolerance): 4
Timer • 16-bit timer: 8 channels
• Watchdog timer: 1 channel
• Real-time counter: 1 channel
Timer outputs 8 (PWM output: 7)
RTC outputs 2
• 1 Hz (Subsystem clock: fSUB = 32.768 kHz)
• 512 Hz or 16.384 kHz or 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz)
Clock output/buzzer output 2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(peripheral hardware clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
A/D converter 10-bit resolution × 16 channels (AVREF0 = 2.3 to 5.5 V)
D/A converter 8-bit resolution × 2 channels (AVREF1 = 1.8 to 5.5 V)
CHAPTER 1 OUTLINE
User’s Manual U17894EJ9V0UD
28
(2/2)
Item
μ
PD78F1162,
μ
PD78F1162A
μ
PD78F1163,
μ
PD78F1163A
μ
PD78F1164,
μ
PD78F1164
A
μ
PD78F1165,
μ
PD78F1165A
μ
PD78F1166,
μ
PD78F1166A
μ
PD78F1167,
μ
PD78F1167A
μ
PD78F1168,
μ
PD78F1168A
Serial interface • UART supporting LIN-bus: 1 channel
• CSI: 2 channels/UART: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• I2C bus: 1 channel
Multiplier 16 bits × 16 bits = 32 bits
DMA controller 2 channels
Internal 28
Vectored interrupt
sources External 13
Key interrupt Key interrupt (INTKR) occurs by detecting falling edge of the key input pins (KR0 to KR7).
Reset • Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-clear
• Internal reset by low-voltage detector
• Internal reset by illegal instruction executionNote
On-chip debug function Provided
Power supply voltage VDD = 1.8 to 5.5 V
Operating ambient temperature TA = −40 to +85°C
Package 100-pin plastic LQFP (14 × 20) (0.65 mm pitch)
100-pin plastic LQFP (14 × 14) (fine pitch) (0.5 mm pitch)
Note When instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
User’s Manual U17894EJ9V0UD 29
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
There are five types of pin I/O buffer power supplies: AVREF0, AVREF1, EVDD0, EVDD1, and VDD. The relationship
between these power supplies and the pins is shown below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins
AVREF0 P20 to P27, P150 to P157
AVREF1 P110, P111
EVDD0, EVDD1 • Port pins other than P20 to P27, P110, P111,
P121 to P124, and P150 to P157
• RESET and FLMD0 pins
VDD • P121 to P124
• Pins other than port pins (excluding RESET and
FLMD0 pins)
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17894EJ9V0UD
30
(1) Port functions (1/2)
Function Name I/O Function After Reset Alternate Function
P00 TI00
P01 TO00
P02 SO10/TxD1
P03 SI10/RxD1/SDA10
P04 SCK10/SCL10
P05 CLKOUT
P06
I/O Port 0.
7-bit I/O port.
Input of P03 and P04 can be set to TTL input buffer.
Output of P02 to P04 can be set to N-ch open-drain output
(VDD tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
WAIT
P10 SCK00/EX24
P11 SI00/RxD0/EX25
P12 SO00/TxD0/EX26
P13 TxD3/EX27
P14 RxD3/EX28
P15 RTCDIV/RTCCL/EX29
P16 TI01/TO01/INTP5/
EX30
P17
I/O Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
TI02/TO02/EX31
P20 to P27 I/O Port 2.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Digital input
port
ANI0 to ANI7
P30 RTC1HZ/INTP3
P31
I/O Port 3.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
TI03/TO03/INTP4
P40Note TOOL0
P41 TOOL1
P42 TI04/TO04
P43 SCK01
P44 SI01
P45 SO01
P46 INTP1/TI05/TO05
P47
I/O Port 4.
8-bit I/O port.
Input of P43 and P44 can be set to TTL input buffer.
Output of P43 and P45 can be set to N-ch open-drain output
(VDD tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
INTP2
P50 to P57 I/O Port 5.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port EX8 to EX15
Note If on-chip debugging is enabled by using an option byte, be sure to pull up the P40/TOOL0 pin externally
(see Caution in 2.2.5 P40 to P47 (port 4)).
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17894EJ9V0UD 31
(1) Port functions (2/2)
Function Name I/O Function After Reset Alternate Function
P60 SCL0
P61 SDA0
P62 −
P63 −
P64 RD
P65 WR0
P66 WR1
P67
I/O Port 6.
8-bit I/O port.
Output of P60 to P63 can be set to N-ch open-drain output (6
V tolerance).
Input/output can be specified in 1-bit units.
For only P64 to P67, use of an on-chip pull-up resistor can be
specified by a software setting.
Input port
ASTB
P70 to P73 KR0/EX16 to KR3/
EX19
P74 to P77
I/O Port 7.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
KR4/EX20/INTP8 to
KR7/EX23/INTP11
P80 to P87 I/O Port 8.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port EX0 to EX7
P110 ANO0
P111
I/O Port 11.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Input port
ANO1
P120 I/O INTP0/EXLVI
P121 X1
P122 X2/EXCLK
P123 XT1
P124
Input
Port 12.
1-bit I/O port and 4-bit input port.
For only P120, use of an on-chip pull-up resistor can be
specified by a software setting.
Input port
XT2
P130 Output Output port −
P131 I/O
Port 13.
1-bit output port and 1-bit I/O port.
For only P131, use of an on-chip pull-up resistor can be
specified by a software setting.
Input port TI06/TO06
P140 PCLBUZ0/INTP6
P141 PCLBUZ1/INTP7
P142 SCK20/SCL20
P143 SI20/RxD2/SDA20
P144 SO20/TxD2
P145
I/O Port 14.
6-bit I/O port.
Input of P142 and P143 can be set to TTL input buffer.
Output of P142 to P144 can be set to the N-ch open-drain
output (VDD tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
TI07/TO07
P150 to P157 I/O Port 15.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Digital input
port
ANI8 to ANI15
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(2) Non-port functions (1/3)
Function Name I/O Function After Reset Alternate Function
ANI0 to ANI7 Input A/D converter analog input Digital input
port
P20 to P27
ANI8 to ANI15 Input A/D converter analog input Digital input
port
P150 to P157
ANO0 Output D/A converter analog output Input port P110
ANO1 Output D/A converter analog output Input port P111
CLKOUT Output External expansion clock output Input port P05
WAIT Input External wait input Input port P06
RD Output Read strobe signal output to external memory Input port P64
WR0 Output Write strobe to external memory (lower 8 bits) Input port P65
WR1 Output Write strobe to external memory (higher 8 bits) Input port P66
ASTB Output Address strobe signal output to external memory Input port P67
EX0 to EX7 P80 to P87
EX8 to EX15
I/O External expansion I/O
P50 to P57
EX16 to EX19 P70/KR0 to P73/KR3
EX20 to EX23 P74/KR4/INTP8 to
P77/KR7/INTP11
EX24 P10/SCK00
EX25 P11/RxD0/SI00
EX26 P12/TxD0/SO00
EX27 P13/TxD3
EX28 P14/RxD3
EX29 P15/RTCDIV/RTCCL
EX30 P16/TI01/TO01/INTP5
EX31
Output External expansion output
Input port
P17/TI02/TO02
EXLVI Input Potential input for external low-voltage detection Input port P120/INTP0
INTP0 P120/EXLVI
INTP1 P46/TI05/TO05
INTP2 P47
INTP3 P30/RTC1HZ
INTP4 P31/TI03/TO03
INTP5 P16/TI01/TO01/EX30
INTP6 P140/PCLBUZ0
INTP7 P141/PCLBUZ1
INTP8
INTP9
INTP10
INTP11
Input External interrupt request input for which the valid edge (rising
edge, falling edge, or both rising and falling edges) can be
specified
Input port
P74/KR4/EX20 to
P77/KR7/EX23
KR0 to KR3 P70/EX16 to P73/EX19
KR4 to KR7
Input Key interrupt input Input port
P74/EX20/INTP8 to
P77/EX23/INTP11
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(2) Non-port functions (2/3)
Function Name I/O Function After Reset Alternate Function
PCLBUZ0 Output Clock output/buzzer output Input port P140/INTP6
PCLBUZ1 P141/INTP7
REGC − Connecting regulator output (2.5 V) stabilization capacitance for
internal operation.
Connect to VSS via a capacitor (0.47 to 1
μ
F).
− −
RTCDIV Output Real-time counter clock (32 kHz divided frequency) output Input port P15/RTCCL/EX29
RTCCL Output Real-time counter clock (32 kHz original oscillation) output Input port P15/RTCDIV/EX29
RTC1HZ Output Real-time counter correction clock (1 Hz) output Input port P30/INTP3
RESET Input System reset input − −
RxD0 Input Serial data input to UART0 Input port P11/SI00/EX25
RxD1 Input Serial data input to UART1 Input port P03/SI10/SDA10
RxD2 Input Serial data input to UART2 Input port P143/SI20/SDA20
RxD3 Input Serial data input to UART3 Input port P14/EX28
SCK00 P10/EX24
SCK01 P43
SCK10 P04/SCL10
SCK20
I/O Clock input/output for CSI00, CSI01, CSI10, and CSI20 Input port
P142/SCL20
SCL0 I/O Clock input/output for I2C Input port P60
SCL10 I/O Clock input/output for simplified I2C Input port P04/SCK10
SCL20 I/O Clock input/output for simplified I2C Input port P142/SCK20
SDA0 Serial data I/O for I2C Input port P61
SDA10 Serial data I/O for simplified I2C Input port P03/SI10/RxD1
SDA20
I/O
Serial data I/O for simplified I2C Input port P143/SI20/RxD2
SI00 P11/RxD0/EX25
SI01 P44
SI10 P03/RxD1/SDA10
SI20
Input Serial data input to CSI00, CSI01, CSI10, and CSI20 Input port
P143/RxD2/SDA20
SO00 P12/TxD0/EX26
SO01 P45
SO10 P02/TxD1
SO20
Output Serial data output from CSI00, CSI01, CSI10, and CSI20 Input port
P144/TxD2
TI00 External count clock input to 16-bit timer 00 P00
TI01 External count clock input to 16-bit timer 01 P16/TO01/INTP5/EX30
TI02 External count clock input to 16-bit timer 02 P17/TO02/EX31
TI03 External count clock input to 16-bit timer 03 P31/TO03/INTP4
TI04 External count clock input to 16-bit timer 04 P42/TO04
TI05 External count clock input to 16-bit timer 05 P46/INTP1/TO05
TI06 External count clock input to 16-bit timer 06 P131/TO06
TI07
Input
External count clock input to 16-bit timer 07
Input port
P145/TO07
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(2) Non-port functions (3/3)
Function Name I/O Function After Reset Alternate Function
TO00 16-bit timer 00 output P01
TO01 16-bit timer 01 output P16/TI01/INTP5/EX30
TO02 16-bit timer 02 output P17/TI02/EX31
TO03 16-bit timer 03 output P31/TI03/INTP4
TO04 16-bit timer 04 output P42/TI04
TO05 16-bit timer 05 output P46/INTP1/TI05
TO06 16-bit timer 06 output P131/TI06
TO07
Output
16-bit timer 07 output
Input port
P145/TI07
TxD0 Output Serial data output from UART0 Input port P12/SO00/EX26
TxD1 Output Serial data output from UART1 Input port P02/SO10
TxD2 Output Serial data output from UART2 Input port P144/SO20
TxD3 Output Serial data output from UART3 Input port P13/EX27
X1 − Input port P121
X2 −
Resonator connection for main system clock
Input port P122/EXCLK
EXCLK Input External clock input for main system clock Input port P122/X2
XT1 − Input port P123
XT2 −
Resonator connection for subsystem clock
Input port P124
VDD − Positive power supply (P121 to P124 and other than ports
(excluding RESET and FLMD0 pins))
− −
EVDD0, EVDD1 − Positive power supply for ports (other than P20 to P27, P110,
P111, P121 to P124, P150 to P157) and RESET and FLMD0
pins
− −
AVREF0 − • A/D converter reference voltage input
• Positive power supply for P20 to P27, P150 to P157, and A/D
converter
− −
AVREF1 − • D/A converter reference voltage input
• Positive power supply for P110, P111, and D/A converter
− −
VSS − Ground potential (P121 to P124 and other than ports (excluding
RESET and FLMD0 pins))
− −
EVSS0, EVSS1 − Ground potential for ports (other than P20 to P27, P110, P111,
P121 to P124, and P150 to P157) and RESET and FLMD0 pins
− −
AVSS − Ground potential for A/D converter, D/A converter, P20 to P27,
P110, P111, and P150 to P157
− −
FLMD0 − Flash memory programming mode setting − −
TOOL0 I/O Data I/O for flash memory programmer/debugger Input port P40
TOOL1 Output Clock output for debugger Input port P41
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2.2 Description of Pin Functions
2.2.1 P00 to P06 (port 0)
P00 to P06 function as a 7-bit I/O port. These pins also function as timer I/O, serial interface data I/O, clock I/O,
internal system clock output, and external wait signal input.
Input to the P03 and P04 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units,
using port input mode register 0 (PIM0).
Output from the P02 to P04 pins can be specified as normal CMOS output or N-ch open-drain output (VDD
tolerance) in 1-bit units, using port output mode register 0 (POM0).
The following operation modes can be specified in 1-bit units.
(1) Port mode
P00 to P06 function as a 7-bit I/O port. P00 to P06 can be set to input or output port in 1-bit units using port
mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0
(PU0).
(2) Control mode
P00 to P06 function as timer I/O, serial interface data I/O, clock I/O, internal system clock output, and external
wait signal input.
(a) TI00
This is a pin for inputting an external count clock/capture trigger to 16-bit timer 00.
(b) TO00
This is a timer output pin of 16-bit timer 00.
(c) SI10
This is a serial data input pin of serial interface CSI10.
(d) SO10
This is a serial data output pin of serial interface CSI10.
(e) SCK10
This is a serial clock I/O pin of serial interface CSI10.
(f) TxD1
This is a serial data output pin of serial interface UART1.
(g) RxD1
This is a serial data input pin of serial interface UART1.
(h) SDA10
This is a serial data I/O pin of serial interface for simplified I2C.
(i) SCL10
This is a serial clock I/O pin of serial interface for simplified I2C.
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(j) CLKOUT
This is an internal system clock output pin.
(e) WAIT
This is an external wait signal input pin.
Caution To use P02/SO10/TxD1 and P04/SCK10/SCL10 as general-purpose ports, set serial
communication operation setting register 02 (SCR02) to the default status (0087H). In
addition, clear port output mode register 0 (POM0) to 00H.
2.2.2 P10 to P17 (port 1)
P10 to P17 function as an 8-bit I/O port. These pins also function as external interrupt request input, serial
interface data I/O, clock I/O, timer I/O, real-time counter clock output, and external expansion output.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output port in 1-bit units using port
mode register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1
(PU1).
(2) Control mode
P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, timer I/O, real-time
counter clock output, and external expansion output.
(a) SI00
This is a serial data input pin of serial interface CSI00.
(b) SO00
This is a serial data output pin of serial interface CSI00.
(c) SCK00
This is a serial clock I/O pin of serial interface CSI00.
(d) RxD0
This is a serial data input pin of serial interface UART0.
(e) RxD3
This is a serial data input pin of serial interface UART3.
(f) TxD0
This is a serial data output pin of serial interface UART0.
(g) TxD3
This is a serial data output pin of serial interface UART3.
(h) TI01, TI02
These are the pins for inputting an external count clock/capture trigger to 16-bit timers 01 and 02.
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User’s Manual U17894EJ9V0UD 37
(i) TO01, TO02
These are the timer output pins of 16-bit timers 01 and 02.
(j) INTP5
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
(k) RTCDIV
This is a real-time counter clock (32 kHz, divided) output pin.
(l) RTCCL
This is a real-time counter clock (32 kHz, original oscillation) output pin.
(m) EX24 to EX31
These are the external expansion output (address bus) pins.
Cautions 1. To use P10/SCK00/EX24 and P12/SO00/TxD0/EX26 as general-purpose ports, set serial
communication operation setting register 00 (SCR00) to the default status (0087H).
2. Do not enable outputting RTCCL and RTCDIV at the same time.
2.2.3 P20 to P27 (port 2)
P20 to P27 function as an 8-bit I/O port. These pins also function as A/D converter analog input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P20 to P27 function as an 8-bit I/O port. P20 to P27 can be set to input or output port in 1-bit units using port
mode register 2 (PM2).
(2) Control mode
P20 to P27 function as A/D converter analog input pins (ANI0 to ANI7). When using these pins as analog input
pins, see 11.7 (6) ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157.
Caution ANI0/P20 to ANI7/P27 are set in the digital input (general-purpose port) mode after release of
reset.
2.2.4 P30, P31 (port 3)
P30 and P31 function as a 2-bit I/O port. These pins also function as external interrupt request input, timer I/O,
and real-time counter correction clock output.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 and P31 function as a 2-bit I/O port. P30 and P31 can be set to input or output port in 1-bit units using port
mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3
(PU3).
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(2) Control mode
P30 and P31 function as external interrupt request input, timer I/O, and real-time counter correction clock output.
(a) INTP3, INTP4
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) TI03
This is a pin for inputting an external count clock/capture trigger to 16-bit timer 03.
(c) TO03
This is a timer output pin from 16-bit timer 03.
(d) RTC1HZ
This is a real-time counter correction clock (1 Hz) output pin.
2.2.5 P40 to P47 (port 4)
P40 to P47 function as an 8-bit I/O port. These pins also function as external interrupt request input, serial
interface data I/O, clock I/O, data I/O for a flash memory programmer/debugger, clock output, and timer I/O.
Input to the P43 and P44 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units
using port input mode register 4 (PIM4).
Output from the P43 and P45 pins can be specified as normal CMOS output or N-ch open-drain output (VDD
tolerance) in 1-bit units using port output mode register 4 (POM4).
The following operation modes can be specified in 1-bit units.
(1) Port mode
P40 to P47 function as an 8-bit I/O port. P40 to P47 can be set to input or output port in 1-bit units using port
mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4
(PU4).
Be sure to connect an external pull-up resistor to P40 when on-chip debugging is enabled (by using an option
byte).
(2) Control mode
P40 to P47 function as serial interface data I/O, clock I/O, external interrupt request input, data I/O for a flash
memory programmer/debugger, clock output, and timer I/O.
(a) INTP1, INTP2
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) TOOL0
This is a data I/O pin for a flash memory programmer/debugger.
Be sure to pull up this pin externally when on-chip debugging is enabled (pulling it down is prohibited).
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(c) TOOL1
This is a clock output pin for a debugger.
When the on-chip debug function is used, P41/TOOL1 pin can be used as follows by the mode setting on the
debugger.
1-line mode: can be used as a port (P41).
2-line mode: used as a TOOL1 pin and cannot be used as a port (P41).
(d) TI04, TI05
These are the pins for inputting an external count clock/capture trigger to 16-bit timers 04 and 05.
(e) TO04, TO05
These are the timer output pins from 16-bit timers 04 and 05.
(f) SCK01
This is a serial clock I/O pin of serial interface CSI01.
(g) SI01
This is a serial data input pin of serial interface CSI01.
(h) SO01
This is a serial data output pin of serial interface CSI01.
Caution The function of the P40/TOOL0 pin varies as described in (a) to (c) below.
In the case of (b) or (c), make the specified connection.
(a) In normal operation mode and when on-chip debugging is disabled (OCDENSET = 0) by
an option byte (000C3H)
=> Use this pin as a port pin (P40).
(b) In normal operation mode and when on-chip debugging is enabled (OCDENSET = 1) by
an option byte (000C3H)
=> Connect this pin to EVDD0 or EVDD1 via an external resistor, and always input a high
level to the pin before reset release.
(c) When on-chip debug function is used, or in write mode of flash memory programmer
=> Use this pin as TOOL0.
Directly connect this pin to the on-chip debug emulator or a flash memory
programmer, or pull it up by connecting it to EVDD0 or EVDD1 via an external resistor.
2.2.6 P50 to P57 (port 5)
P50 to P57 function as an 8-bit I/O port. These pins also function as external expansion I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P50 to P57 function as an 8-bit I/O port. P50 to P57 can be set to input or output port in 1-bit units using port
mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5
(PU5).
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(2) Control mode
P50 to P57 function as external expansion I/O.
(a) EX8 to EX15
These are the external expansion I/O (multiplexed address/data bus, address bus, data bus) pins.
2.2.7 P60 to P67 (port 6)
P60 to P67 function as an 8-bit I/O port. These pins also function as serial interface data I/O, clock I/O, read strobe
signal output, write strobe signal output, and address strobe signal output.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P60 to P67 function as an 8-bit I/O port. P60 to P67 can be set to input port or output port in 1-bit units using port
mode register 6 (PM6). Only for P64 to P67, use of an on-chip pull-up resistor can be specified by pull-up resistor
option register 6 (PU6).
Output of P60 to P63 is N-ch open-drain output (6 V tolerance).
(2) Control mode
P60 to P67 function as serial interface data I/O, clock I/O, read strobe signal output, write strobe signal output,
and address strobe signal output.
(a) SDA0
This is a serial data I/O pin of serial interface IIC0.
(b) SCL0
This is a serial clock I/O pin of serial interface IIC0.
(c) RD
This is a read strobe signal output pin.
(d) WR0
This is a write strobe signal output (8-bit bus mode, 16-bit bus mode (lower byte)) pin.
(e) WR1
This is a write strobe signal output (16-bit bus mode (higher byte)) pin.
(f) ASTB
This is an address strobe signal output pin.
2.2.8 P70 to P77 (port 7)
P70 to P77 function as an 8-bit I/O port. These pins also function as key interrupt input, external interrupt request
input, and external expansion output.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P70 to P77 function as an 8-bit I/O port. P70 to P77 can be set to input or output port in 1-bit units using port
mode register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7
(PU7).
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(2) Control mode
P70 to P77 function as key interrupt input, external interrupt request input, and external expansion output.
(a) KR0 to KR7
These are the key interrupt input pins
(b) INTP8 to INTP11
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(c) EX16 to EX23
These are the external expansion output (address bus) pins.
2.2.9 P80 to P87 (port 8)
P80 to P87 function as an 8-bit I/O port. These pins also function as external expansion I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P80 to P87 function as an 8-bit I/O port. P80 to P87 can be set to input or output port in 1-bit units using port
mode register 8 (PM8). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 8
(PU8).
(2) Control mode
P80 to P87 function as external expansion I/O.
(a) EX0 to EX7
These are the external expansion I/O (multiplexed address/data bus, data bus) pins.
2.2.10 P110, P111 (port 11)
P110 and P111 function as a 2-bit I/O port. These pins also function as D/A converter analog output.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P110 and P111 function as a 2-bit I/O port. P110 and P111 can be set to input or output port in 1-bit units using
port mode register 11 (PM11).
(2) Control mode
P110 and P111 function as D/A converter analog output pins (ANO0, ANO1). When using these pins as analog
input pins, see 12.4.3 Cautions.
2.2.11 P120 to P124 (port 12)
P120 function as a 1-bit I/O port. P121 to P124 functions as a 4-bit input port. These pins also function as external
interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock,
connecting resonator for subsystem clock, and external clock input for main system clock.
The following operation modes can be specified in 1-bit units.
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(1) Port mode
P120 functions as a 1-bit I/O port. P120 can be set to input or output port using port mode register 12 (PM12).
Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
P121 to P124 functions as a 4-bit input port.
(2) Control mode
P120 to P124 function as external interrupt request input, potential input for external low-voltage detection,
connecting resonator for main system clock, connecting resonator for subsystem clock, and external clock input
for main system clock.
(a) INTP0
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
(b) EXLVI
This is a potential input pin for external low-voltage detection.
(c) X1, X2
These are the pins for connecting a resonator for main system clock.
(d) EXCLK
This is an external clock input pin for main system clock.
(e) XT1, XT2
These are the pins for connecting a resonator for subsystem clock.
2.2.12 P130, P131 (port 13)
P130 functions as a 1-bit output port. P131 functions as a 1-bit I/O port. These pins also function as timer I/O.
Remark When the device is reset, P130 outputs a low level. Therefore, to output a high level from P130 before
the device is reset, the output signal of P130 can be used as a pseudo reset signal of the CPU (see the
figure for Remark in 4.2.12 Port 13).
(1) Port mode
P130 functions as a 1-bit output port.
P131 functions as a 1-bit I/O port. P131 can be set to input or output port using port mode register 13 (PM13).
Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 13 (PU13).
(2) Control mode
P131 functions as timer I/O.
(a) TI06
This is a pin for inputting an external count clock/capture trigger to 16-bit timer 06.
(b) TO06
This is a timer output pin from 16-bit timer 06.
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2.2.13 P140 to P145 (port 14)
P140 to P145 function as a 6-bit I/O port. These pins also function as timer I/O, external interrupt request input,
clock/buzzer output, serial interface data I/O, and clock I/O.
Input to the P142 and P143 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units
using port input mode register 14 (PIM14).
Output from the P142 to P144 pins can be specified as normal CMOS output or N-ch open-drain output (VDD
tolerance) in 1-bit units using port output mode register 14 (POM14).
The following operation modes can be specified in 1-bit units.
(1) Port mode
P140 to P145 function as a 6-bit I/O port. P140 to P145 can be set to input or output port in 1-bit units using port
mode register 14 (PM14). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14
(PU14).
(2) Control mode
P140 to P145 function as timer I/O, external interrupt request input, clock/buzzer output, serial interface data I/O,
and clock I/O.
(a) INTP6, INTP7
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) PCLBUZ0, PCLBUZ1
These are the clock/buzzer output pins.
(c) TI07
This is a pin for inputting an external count clock/capture trigger to 16-bit timer 07.
(d) TO07
This is a timer output pin of 16-bit timer 07.
(e) SI20
This is a serial data input pin of serial interface CSI20.
(f) SO20
This is a serial data output pin of serial interface CSI20.
(g) SCK20
This is a serial clock I/O pin of serial interface CSI20.
(h) TxD2
This is a serial data output pin of serial interface UART2.
(i) RxD2
This is a serial data input pin of serial interface UART2.
(j) SDA20
This is a serial data I/O pin of serial interface for simplified I2C.
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(k) SCL20
This is a serial clock I/O pin of serial interface for simplified I2C.
2.2.14 P150 to P157 (port 15)
P150 to P157 function as an 8-bit I/O port. These pins also function as A/D converter analog input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P150 to P157 function as an 8-bit I/O port. P150 to P157 can be set to input or output port in 1-bit units using
port mode register 15 (PM15).
(2) Control mode
P150 to P157 function as A/D converter analog input pins (ANI8 to ANI15). When using these pins as analog
input pins, see 11.7 (6) ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157.
Caution ANI8/P150 to ANI15/P157 are set in the digital input (general-purpose port) mode after release of
reset.
2.2.15 AVREF0
This is the A/D converter reference voltage input pin and the positive power supply pin of P20 to P27, P150 to
P157, and A/D converter.
The voltage that can be supplied to AVREF0 varies as follows, depending on whether P20/ANI0 to P27/ANI7 and
P150/ANI8 to P157/ANI15 are used as digital I/Os or analog inputs.
Table 2-2. AVREF0 Voltage Applied to P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 Pins
Analog/Digital VDD Condition AVREF0 Voltage
Using at least one pin as an analog input and using all
pins not as digital I/Os
2.3 V ≤ VDD ≤ 5.5 V 2.3 V ≤ AVREF0 ≤ VDD = EVDD0 = EVDD1
2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ AVREF0 ≤ VDD = EVDD0 = EVDD1
Pins used as analog inputs and digital I/Os are
mixedNote
2.3 V ≤ VDD < 2.7 V AVREF0 has same potential as EVDD0,
EVDD1, and VDD
2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ AVREF0 ≤ VDD = EVDD0 = EVDD1
Using at least one pin as a digital I/O and using all pins
not as analog inputsNote
1.8 V ≤ VDD < 2.7 V AVREF0 has same potential as EVDD0,
EVDD1, and VDD
Note AVREF0 is the reference for the I/O voltage of a port to be used as a digital port.
• High-/low-level input voltage (VIH4/VIL4)
• High-/low-level output voltage (VOH2/VOL2)
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17894EJ9V0UD 45
2.2.16 AVREF1
This is the D/A converter reference voltage input pin and the positive power supply pin of P110, P111, and the D/A
converter.
The voltage that can be supplied to AVREF1 varies as follows, depending on whether P110/ANO0 and P111/ANO1
are used as digital I/Os or analog outputs.
Table 2-3. AVREF1 Voltage Applied to P110/ANO0 and P111/ANO1 Pins
Analog/Digital VDD Condition AVREF1 Voltage
Using at least one pin as an analog output and using all
pins not as digital I/Os
1.8 V ≤ VDD ≤ 5.5 V 1.8 V ≤ AVREF1 ≤ VDD = EVDD0 = EVDD1
2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ AVREF1 ≤ VDD = EVDD0 = EVDD1
Pins used as analog outputs and digital I/Os are
mixedNote 1.8 V ≤ VDD < 2.7 V AVREF1 has same potential as EVDD0,
EVDD1, and VDD
2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ AVREF1 ≤ VDD = EVDD0 = EVDD1
Using at least one pin as a digital I/O and using all pins
not as analog outputsNote 1.8 V ≤ VDD < 2.7 V AVREF1 has same potential as EVDD0,
EVDD1, and VDD
Note AVREF1 is the reference for the I/O voltage of a port to be used as a digital port.
• High-/low-level input voltage (VIH5/VIL5)
• High-/low-level output voltage (VOH2/VOL2)
2.2.17 AVSS
This is the ground potential pin of A/D converter, D/A converter, P20 to P27, P110, P111, and P150 to P157. Even
when the A/D converter and D/A converter are not used, always use this pin with the same potential as EVSS0, EVSS1,
and VSS.
2.2.18 RESET
This is the active-low system reset input pin.
When the external reset pin is not used, connect this pin directly or via a resistor to EVDD0 or EVDD1.
When the external reset pin is used, design the circuit based on VDD.
2.2.19 REGC
This is the pin for connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect this
pin to VSS via a capacitor (0.47 to 1
μ
F). However, when using the STOP mode that has been entered since operation
of the internal high-speed oscillation clock and external main system clock, 0.47
μ
F is recommended.
Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
REGC
V
SS
Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17894EJ9V0UD
46
2.2.20 VDD, EVDD0, EVDD1
VDD is the positive power supply pin for P121 to P124 and pins other than ports (excluding the RESET and FLMD0
pins).
EVDD0 and EVDD1 are the positive power supply pins for ports other than P20 to P27, P110, P111, P121 to P124,
and P150 to P157 as well as for the RESET and FLMD0 pins.
2.2.21 VSS, EVSS0, EVSS1
VSS is the ground potential pin for P121 to P124 and pins other than ports (excluding the RESET and FLMD0 pins).
EVSS0 and EVSS1 are the ground potential pins for ports other than P20 to P27, P110, P111, P121 to P124, and
P150 to P157 as well as for the RESET and FLMD0 pins.
2.2.22 FLMD0
This is a pin for setting flash memory programming mode.
Perform either of the following processing.
(a) In normal operation mode
It is recommended to leave this pin open during normal operation.
The FLMD0 pin must always be kept at the VSS level before reset release but does not have to be pulled
down externally because it is internally pulled down by reset. However, pulling it down must be kept selected
(i.e., FLMDPUP = “0”, default value) by using bit 7 (FLMDPUP) of the background event control register
(BECTL) (see 25.5 (1) Back ground event control register). To pull it down externally, use a resistor of
200 kΩ or smaller.
Self programming and the rewriting of flash memory with the programmer can be prohibited using hardware,
by directly connecting this pin to the VSS pin.
(b) In self programming mode
It is recommended to leave this pin open when using the self programming function. To pull it down
externally, use a resistor of 100 kΩ to 200 kΩ.
In the self programming mode, the setting is switched to pull up in the self programming library.
(c) In flash memory programming mode
Directly connect this pin to a flash memory programmer when data is written by the flash memory
programmer. This supplies a writing voltage of the VDD level to the FLMD0 pin.
The FLMD0 pin does not have to be pulled down externally because it is internally pulled down by reset. To
pull it down externally, use a resistor of 1 kΩ to 200 kΩ.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17894EJ9V0UD 47
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-4 shows the types of pin I/O circuits and the recommended connections of unused pins.
Table 2-4. Connection of Unused Pins (1/3)
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
P00/TI00 8-R
P01/TO00
P02/SO10/TxD1
5-AG
P03/SI10/RxD1/SDA10
P04/SCK10/SCL10
5-AN
P05/CLKOUT
P06/WAIT
P10/SCK00/EX24
P11/SI00/RxD0/EX25
8-R
P12/SO00/TxD0/EX26
P13/TxD3/EX27
5-AG
P14/RxD3/EX28 8-R
P15/RTCDIV/RTCCL/EX29 5-AG
P16/TI01/TO01/INTP5/EX30
P17/TI02/TO02/EX31
8-R
Input: Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
P20/ANI0 to P27/ANI7Note 11-G Input: Independently connect to AVREF0 or AVSS via a resistor.
Output: Leave open.
P30/RTC1HZ/INTP3
P31/TI03/TO03/INTP4
Input: Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
P40/TOOL0
8-R
<When on-chip debugging is enabled>
Pull this pin up (pulling it down is prohibited).
<When on-chip debugging is disabled>
Input: Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
P41/TOOL1 5-AG
P42/TI04/TO04 8-R
P43/SCK01
P44/SI01
5-AN
P45/SO01 5-AG
P46/TI05/TO05/INTP1
P47/INTP2
8-R
I/O
Input: Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
Note P20/ANI0 to P27/ANI7 are set in the digital input port mode after release of reset.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17894EJ9V0UD
48
Table 2-4. Connection of Unused Pins (2/3)
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
P50/EX8, P51/EX9 8-R
P52/EX10 to P57/EX15 5-AG
Input: Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
P60/SCL0
P61/SDA0
13-R
P62, P63 13-P
Input: Connect to EVSS0 or EVSS1.
Output: Set the port output latch to 0 and leave these pins open
via low-level output.
P64/RD
P65/WR0
P66/WR1
P67/ASTB
5-AG
P70/KR0/EX14 to
P73/KR3/EX19
P74/KR4/EX20/INTP8 to
P77/KR7/EX23/INTP11
8-R
P80/EX0 to P87/EX7 5-AG
Input: Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
P110/ANO0, P111/ANO1 12-G Input: Independently connect to AVREF1 or AVSS via a resistor.
Output: Leave open.
P120/INTP0/EXLVI 8-R
I/O
Input: Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
P121/X1Note 1
P122/X2/EXCLKNote 1
P123/XT1Note 1
P124/XT2Note 1
37-B Input Independently connect to VDD or VSS via a resistor.
P130 3-C Output Leave open.
P131/TI06/TO06
P140/PCLBUZ0/INTP6
P141/PCLBUZ1/INTP7
8-R
P142/SCK20/SCL20
P143/SI20/RxD2/SDA20
5-AN
P144/SO20/TxD2 5-AG
P145/TI07/TO07 8-R
Input: Independently connect to EVDD0, EVDD1, EVSS0, or EVSS1
via a resistor.
Output: Leave open.
P150/ANI8 to P157/ANI15Note 2 11-G
I/O
Input: Independently connect to AVREF0 or AVSS via a resistor.
Output: Leave open.
AVREF0 − − Make this pin the same potential as EVDD0, EVDD1, or VDD.
See 2.2.15 AVREF0 when using P20 to P27 and P150 to P157.
Notes 1. Use recommended connection above in input port mode (see Figure 6-2 Format of Clock Operation
Mode Control Register (CMC)) when these pins are not used.
2. P150/ANI8 to P157/ANI15 are set in the digital input port mode after release of reset.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17894EJ9V0UD 49
Table 2-4. Connection of Unused Pins (3/3)
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
AVREF1 − − Make this pin the same potential as EVDD0, EVDD1, or VDD.
See 2.2.16 AVREF1 when using P110 and P111.
AVSS − − Make this pin the same potential as EVSS0, EVSS1, or VSS.
FLMD0 2-W
− Leave open or connect to VSS via a resistor of 100 kΩ or more.
RESET 2 Input Connect directly or via a resistor to EVDD0 or EVDD1.
REGC − − Connect to VSS via capacitor (0.47 to 1
μ
F).
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17894EJ9V0UD
50
Figure 2-1. Pin I/O Circuit List (1/2)
Type 2 Type 5-AG
Schmitt-triggered input with hysteresis characteristics
IN
Pull-up
enable
Data
Output
disable
Input
enable
EVDD0, EVDD1
P-ch
EVDD0, EVDD1
EVSS0, EVSS1
P-ch
IN/OUT
N
-ch
Type 2-W Type 5-AN
IN
Pull-down
enable
N-ch
Pull-up
enable
P-ch
EVDD0, EVDD1
EVSS0, EVSS1
Schmitt-triggered input with hysteresis characteristics
Pull-up
enable
Data
Output
disable
P-ch
EVDD0, EVDD1
EVDD0, EVDD1
EVSS0, EVSS1
P-ch
IN/OUT
N
-ch
CMOS
TTL
Input
characteristic
Type 3-C Type 8-R
EVDD0, EVDD1
P-ch
N-ch
Data OUT
EVSS0, EVSS1
Data
Output
disable
EV
DD0,
EV
DD1
P-ch
IN/OUT
N-ch
EV
SS0,
EV
SS1
Pull-up
enable
EV
DD0,
EV
DD1
P-ch
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17894EJ9V0UD 51
Figure 2-1. Pin I/O Circuit List (2/2)
Type 11-G Type 13-R
Data
Output
disable
AV
REF0
P-ch
IN/OUT
N-ch
P-ch
N-ch
Input enable
+
_
AV
SS
AV
SS
Comparator
Series resistor string voltage
IN/OUT
N
-ch
Data
Output disable
EV
SS0
, EV
SS1
Type 12-G Type 37-B
Data
Output
disable
Input
enable
AVREF1
P-ch
IN/OUT
N-ch
P-ch
N-ch
AVSS
Output analog voltage
X1, XT1
Input
enable
Input
enable amp
enable
P-ch
N-ch
X2, XT2
Type 13-P
Data
Output
disable
Input
enable
IN/OUT
N
-ch
EV
SS0
, EV
SS1
User’s Manual U17894EJ9V0UD
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CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
Products in the 78K0R/KG3 can access a 1 MB memory space. Figures 3-1 to 3-7 show the memory maps.
Figure 3-1. Memory Map (
μ
PD78F1162, 78F1162A)
00000H
EDFFFH
EE000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
FEEFFH
FEF00H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFFFFH
00000H
0007FH
00080H
000BFH
000C0H
000C3H
000C4H
00FFFH
01000H
0107FH
01080H
010BFH
010C0H
010C3H
010C4H
0FFFFH
0FFFFH
10000H
Special function register (SFR)
256 bytes
RAM
Note 1
4 KB
General-purpose register
32 bytes
Flash memory
64 KB
Special function register (2nd SFR)
2 KB
Mirror
55.75 KB
External expansion area
Note 1
888 KB max.
Vector table area
128 bytes
CALLT table area
64 bytes
Program area
Option byte area
Note 2
4 bytes
Vector table area
128 bytes
CALLT table area
64 bytes
Option byte area
Note 2
4 bytes
Program area
Reserved
Reserved
Program
memory
space
Data memory
space
On-chip debug security
ID setting area
Note 2
10 bytes
01FFFH
Boot cluster 0
Note 3
Boot cluster 1
010CDH
010CEH
On-chip debug security
ID setting area
Note 2
10 bytes
000CDH
000CEH
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area, and from
the external expansion area.
2. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug
security IDs to 000C4H to 000CDH.
When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and
the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to
010CDH.
3. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.7 Security
Setting).
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 53
Figure 3-2. Memory Map (
μ
PD78F1163, 78F1163A)
00000H
EDFFFH
EE000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
FE6FFH
FE700H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFFFFH
00000H
0007FH
00080H
000BFH
000C0H
000C3H
000C4H
00FFFH
01000H
0107FH
01080H
010BFH
010C0H
010C3H
010C4H
17FFFH
17FFFH
18000H
Special function register (SFR)
256 bytes
RAM
Note 1
6 KB
General-purpose register
32 bytes
Flash memory
96 KB
Special function register (2nd SFR)
2 KB
Mirror
53.75 KB
External expansion area
Note 1
824 KB max.
Vector table area
128 bytes
CALLT table area
64 bytes
Program area
Option byte area
Note 2
4 bytes
Vector table area
128 bytes
CALLT table area
64 bytes
Option byte area
Note 2
4 bytes
Program area
Reserved
Reserved
Program
memory
space
Data memory
space
On-chip debug security
ID setting area
Note 2
10 bytes
01FFFH
Boot cluster 0
Note 3
Boot cluster 1
010CDH
010CEH
On-chip debug security
ID setting area
Note 2
10 bytes
000CDH
000CEH
1FFFFH
20000H
Reserved
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area, and from
the external expansion area.
2. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug
security IDs to 000C4H to 000CDH.
When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and
the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to
010CDH.
3. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.7 Security
Setting).
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD
54
Figure 3-3. Memory Map (
μ
PD78F1164, 78F1164A)
00000H
EDFFFH
EE000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
FDEFFH
FDF00H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFFFFH
00000H
0007FH
00080H
000BFH
000C0H
000C3H
000C4H
00FFFH
01000H
0107FH
01080H
010BFH
010C0H
010C3H
010C4H
1FFFFH
1FFFFH
20000H
Special function register (SFR)
256 bytes
RAM
Note 1
8 KB
General-purpose register
32 bytes
Flash memory
128 KB
Special function register (2nd SFR)
2 KB
Mirror
51.75 KB
External expansion area
Note 1
824 KB max.
Vector table area
128 bytes
CALLT table area
64 bytes
Program area
Option byte area
Note 2
4 bytes
Vector table area
128 bytes
CALLT table area
64 bytes
Option byte area
Note 2
4 bytes
Program area
Reserved
Reserved
Program
memory
space
Data memory
space
On-chip debug security
ID setting area
Note 2
10 bytes
01FFFH
Boot cluster 0
Note 3
Boot cluster 1
010CDH
010CEH
On-chip debug security
ID setting area
Note 2
10 bytes
000CDH
000CEH
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area, and from
the external expansion area.
2. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug
security IDs to 000C4H to 000CDH.
When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and
the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to
010CDH.
3. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.7 Security
Setting).
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 55
Figure 3-4. Memory Map (
μ
PD78F1165, 78F1165A)
00000H
EDFFFH
EE000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
FD6FFH
FD700H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFFFFH
00000H
0007FH
00080H
000BFH
000C0H
000C3H
000C4H
00FFFH
01000H
0107FH
01080H
010BFH
010C0H
010C3H
010C4H
2FFFFH
2FFFFH
30000H
Special function register (SFR)
256 bytes
RAM
Note 1
10 KB
General-purpose register
32 bytes
Flash memory
192 KB
Special function register (2nd SFR)
2 KB
Mirror
49.75 KB
External expansion area
Note 1
760 KB max.
Vector table area
128 bytes
CALLT table area
64 bytes
Program area
Option byte area
Note 2
4 bytes
Vector table area
128 bytes
CALLT table area
64 bytes
Option byte area
Note 2
4 bytes
Program area
Reserved
Reserved
Data memory
space
Program
memory
space
On-chip debug security
ID setting area
Note 2
10 bytes
01FFFH
Boot cluster 0
Note 3
Boot cluster 1
010CDH
010CEH
On-chip debug security
ID setting area
Note 2
10 bytes
000CDH
000CEH
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area, and from
the external expansion area.
2. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug
security IDs to 000C4H to 000CDH.
When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and
the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to
010CDH.
3. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.7 Security
Setting).
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD
56
Figure 3-5. Memory Map (
μ
PD78F1166, 78F1166A)
00000H
EDFFFH
EE000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
FCEFFH
FCF00H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFFFFH
00000H
0007FH
00080H
000BFH
000C0H
000C3H
000C4H
00FFFH
01000H
0107FH
01080H
010BFH
010C0H
010C3H
010C4H
3FFFFH
3FFFFH
40000H
Special function register (SFR)
256 bytes
RAM
Notes 1, 2
12 KB
General-purpose register
32 bytes
Flash memory
256 KB
Special function register (2nd SFR)
2 KB
Mirror
47.75 KB
External expansion area
Note 1
696 KB max.
Vector table area
128 bytes
CALLT table area
64 bytes
Program area
Option byte area
Note 3
4 bytes
Vector table area
128 bytes
CALLT table area
64 bytes
Option byte area
Note 3
4 bytes
Program area
Reserved
Reserved
Data memory
space
Program
memory
space
On-chip debug security
ID setting area
Note 3
10 bytes
01FFFH
Boot cluster 0
Note 4
Boot cluster 1
010CDH
010CEH
On-chip debug security
ID setting area
Note 3
10 bytes
000CDH
000CEH
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area, and from
the external expansion area.
2. Use of the area FCF00H to FD6FFH is prohibited when using the self-programming function, since this
area is used for self-programming library.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug
security IDs to 000C4H to 000CDH.
When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and
the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to
010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.7 Security
Setting).
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 57
Figure 3-6. Memory Map (
μ
PD78F1167, 78F1167A)
00000H
EDFFFH
EE000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
F9EFFH
F9F00H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFFFFH
00000H
0007FH
00080H
000BFH
000C0H
000C3H
000C4H
00FFFH
01000H
0107FH
01080H
010BFH
010C0H
010C3H
010C4H
5FFFFH
5FFFFH
60000H
Special function register (SFR)
256 bytes
RAMNote 1
24 KB
General-purpose register
32 bytes
Flash memory
384 KB
Special function register (2nd SFR)
2 KB
Mirror
35.75 KB
External expansion areaNote 1
568 KB max.
Vector table area
128 bytes
CALLT table area
64 bytes
Program area
Option byte areaNote 2
4 bytes
Vector table area
128 bytes
CALLT table area
64 bytes
Option byte areaNote 2
4 bytes
Program area
Reserved
Reserved
Data memory
space
Program
memory
space
On-chip debug security
ID setting areaNote 2
10 bytes
01FFFH
Boot cluster 0Note 3
Boot cluster 1
010CDH
010CEH
On-chip debug security
ID setting areaNote 2
10 bytes
000CDH
000CEH
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area, and from
the external expansion area.
2. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug
security IDs to 000C4H to 000CDH.
When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and
the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to
010CDH.
3. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.7 Security
Setting).
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User’s Manual U17894EJ9V0UD
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Figure 3-7. Memory Map (
μ
PD78F1168, 78F1168A)
00000H
EDFFFH
EE000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
F86FFH
F8700H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFFFFH
00000H
0007FH
00080H
000BFH
000C0H
000C3H
000C4H
00FFFH
01000H
0107FH
01080H
010BFH
010C0H
010C3H
010C4H
7FFFFH
7FFFFH
80000H
Special function register (SFR)
256 bytes
RAM
Notes 1, 2
30 KB
General-purpose register
32 bytes
Flash memory
512 KB
Special function register (2nd SFR)
2 KB
Mirror
29.75 KB
External expansion area
Note 1
440 KB max.
Vector table area
128 bytes
CALLT table area
64 bytes
Program area
Option byte area
Note 3
4 bytes
Vector table area
128 bytes
CALLT table area
64 bytes
Option byte area
Note 3
4 bytes
Program area
Reserved
Reserved
Data memory
space
Program
memory
space
On-chip debug security
ID setting area
Note 3
10 bytes
01FFFH
Boot cluster 0
Note 4
Boot cluster 1
010CDH
010CEH
On-chip debug security
ID setting area
Note 3
10 bytes
000CDH
000CEH
Notes 1. Instructions can be executed from the RAM area excluding the general-purpose register area, and from
the external expansion area.
2. Use of the area F8700H to F8EFFH is prohibited when using the self-programming function, since this
area is used for self-programming library.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug
security IDs to 000C4H to 000CDH.
When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and
the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to
010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.7 Security
Setting).
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 59
Remark The flash memory is divided into blocks (one block = 2 KB). For the address values and block numbers,
see Table 3-1 Correspondence Between Address Values and Block Numbers in Flash Memory.
Block 00H
Block 01H
Block FFH
2 KB
007FFH
00800H
00000H
00FFFH
7F7FFH
7F800H
7FFFFH
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD
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Correspondence between the address values and block numbers in the flash memory are shown below.
Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory (1/2)
Address Value Block
Number
Address Value Block
Number
Address Value Block
Number
Address Value Block
Number
00000H to 007FFH 00H 10000H to 107FFH 20H 20000H to 207FFH 40H 30000H to 307FFH 60H
00800H to 00FFFH 01H 10800H to 10FFFH 21H 20800H to 20FFFH 41H 30800H to 30FFFH 61H
01000H to 017FFH 02H 11000H to 117FFH 22H 21000H to 217FFH 42H 31000H to 317FFH 62H
01800H to 01FFFH 03H 11800H to 11FFFH 23H 21800H to 21FFFH 43H 31800H to 31FFFH 63H
02000H to 027FFH 04H 12000H to 127FFH 24H 22000H to 227FFH 44H 32000H to 327FFH 64H
02800H to 02FFFH 05H 12800H to 12FFFH 25H 22800H to 22FFFH 45H 32800H to 32FFFH 65H
03000H to 037FFH 06H 13000H to 137FFH 26H 23000H to 237FFH 46H 33000H to 337FFH 66H
03800H to 03FFFH 07H 13800H to 13FFFH 27H 23800H to 23FFFH 47H 33800H to 33FFFH 67H
04000H to 047FFH 08H 14000H to 147FFH 28H 24000H to 247FFH 48H 34000H to 347FFH 68H
04800H to 04FFFH 09H 14800H to 14FFFH 29H 24800H to 24FFFH 49H 34800H to 34FFFH 69H
05000H to 057FFH 0AH 15000H to 157FFH 2AH 25000H to 257FFH 4AH 35000H to 357FFH 6AH
05800H to 05FFFH 0BH 15800H to 15FFFH 2BH 25800H to 25FFFH 4BH 35800H to 35FFFH 6BH
06000H to 067FFH 0CH 16000H to 167FFH 2CH 26000H to 267FFH 4CH 36000H to 367FFH 6CH
06800H to 06FFFH 0DH 16800H to 16FFFH 2DH 26800H to 26FFFH 4DH 36800H to 36FFFH 6DH
07000H to 077FFH 0EH 17000H to 177FFH 2EH 27000H to 277FFH 4EH 37000H to 377FFH 6EH
07800H to 07FFFH 0FH 17800H to 17FFFH 2FH 27800H to 27FFFH 4FH 37800H to 37FFFH 6FH
08000H to 087FFH 10H 18000H to 187FFH 30H 28000H to 287FFH 50H 38000H to 387FFH 70H
08800H to 08FFFH 11H 18800H to 18FFFH 31H 28800H to 28FFFH 51H 38800H to 38FFFH 71H
09000H to 097FFH 12H 19000H to 197FFH 32H 29000H to 297FFH 52H 39000H to 397FFH 72H
09800H to 09FFFH 13H 19800H to 19FFFH 33H 29800H to 29FFFH 53H 39800H to 39FFFH 73H
0A000H to 0A7FFH 14H 1A000H to 1A7FFH 34H 2A000H to 2A7FFH 54H 3A000H to 3A7FFH 74H
0A800H to 0AFFFH 15H 1A800H to 1AFFFH 35H 2A800H to 2AFFFH 55H 3A800H to 3AFFFH 75H
0B000H to 0B7FFH 16H 1B000H to 1B7FFH 36H 2B000H to 2B7FFH 56H 3B000H to 3B7FFH 76H
0B800H to 0BFFFH 17H 1B800H to 1BFFFH 37H 2B800H to 2BFFFH 57H 3B800H to 3BFFFH 77H
0C000H to 0C7FFH 18H 1C000H to 1C7FFH 38H 2C000H to 2C7FFH 58H 3C000H to 3C7FFH 78H
0C800H to 0CFFFH 19H 1C800H to 1CFFFH 39H 2C800H to 2CFFFH 59H 3C800H to 3CFFFH 79H
0D000H to 0D7FFH 1AH 1D000H to 1D7FFH 3AH 2D000H to 2D7FFH 5AH 3D000H to 3D7FFH 7AH
0D800H to 0DFFFH 1BH 1D800H to 1DFFFH 3BH 2D800H to 2DFFFH 5BH 3D800H to 3DFFFH 7BH
0E000H to 0E7FFH 1CH 1E000H to 1E7FFH 3CH 2E000H to 2E7FFH 5CH 3E000H to 3E7FFH 7CH
0E800H to 0EFFFH 1DH 1E800H to 1EFFFH 3DH 2E800H to 2EFFFH 5DH 3E800H to 3EFFFH 7DH
0F000H to 0F7FFH 1EH 1F000H to 1F7FFH 3EH 2F000H to 2F7FFH 5EH 3F000H to 3F7FFH 7EH
0F800H to 0FFFFH 1FH 1F800H to 1FFFFH 3FH 2F800H to 2FFFFH 5FH 3F800H to 3FFFFH 7FH
Remark
μ
PD78F1162, 78F1162A: Block numbers 00H to 1FH
μ
PD78F1163, 78F1163A: Block numbers 00H to 2FH
μ
PD78F1164, 78F1164A: Block numbers 00H to 3FH
μ
PD78F1165, 78F1165A: Block numbers 00H to 5FH
μ
PD78F1166, 78F1166A: Block numbers 00H to 7FH
μ
PD78F1167, 78F1167A: Block numbers 00H to BFH
μ
PD78F1168, 78F1168A: Block numbers 00H to FFH
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 61
Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory (2/2)
Address Value Block
Number
Address Value Block
Number
Address Value Block
Number
Address Value Block
Number
40000H to 407FFH 80H 50000H to 507FFH A0H 60000H to 607FFH C0H 70000H to 707FFH E0H
40800H to 40FFFH 81H 50800H to 50FFFH A1H 60800H to 60FFFH C1H 70800H to 70FFFH E1H
41000H to 417FFH 82H 51000H to 517FFH A2H 61000H to 617FFH C2H 71000H to 717FFH E2H
41800H to 41FFFH 83H 51800H to 51FFFH A3H 61800H to 61FFFH C3H 71800H to 71FFFH E3H
42000H to 427FFH 84H 52000H to 527FFH A4H 62000H to 627FFH C4H 72000H to 727FFH E4H
42800H to 42FFFH 85H 52800H to 52FFFH A5H 62800H to 62FFFH C5H 72800H to 72FFFH E5H
43000H to 437FFH 86H 53000H to 537FFH A6H 63000H to 637FFH C6H 73000H to 737FFH E6H
43800H to 43FFFH 87H 53800H to 53FFFH A7H 63800H to 63FFFH C7H 73800H to 73FFFH E7H
44000H to 447FFH 88H 54000H to 547FFH A8H 64000H to 647FFH C8H 74000H to 747FFH E8H
44800H to 44FFFH 89H 54800H to 54FFFH A9H 64800H to 64FFFH C9H 74800H to 74FFFH E9H
45000H to 457FFH 8AH 55000H to 557FFH AAH 65000H to 657FFH CAH 75000H to 757FFH EAH
45800H to 45FFFH 8BH 55800H to 55FFFH ABH 65800H to 65FFFH CBH 75800H to 75FFFH EBH
46000H to 467FFH 8CH 56000H to 567FFH ACH 66000H to 667FFH CCH 76000H to 767FFH ECH
46800H to 46FFFH 8DH 56800H to 56FFFH ADH 66800H to 66FFFH CDH 76800H to 76FFFH EDH
47000H to 477FFH 8EH 57000H to 577FFH AEH 67000H to 677FFH CEH 77000H to 777FFH EEH
47800H to 47FFFH 8FH 57800H to 57FFFH AFH 67800H to 67FFFH CFH 77800H to 77FFFH EFH
48000H to 487FFH 90H 58000H to 587FFH B0H 68000H to 687FFH D0H 78000H to 787FFH F0H
48800H to 48FFFH 91H 58800H to 58FFFH B1H 68800H to 68FFFH D1H 78800H to 78FFFH F1H
49000H to 497FFH 92H 59000H to 597FFH B2H 69000H to 697FFH D2H 79000H to 797FFH F2H
49800H to 49FFFH 93H 59800H to 59FFFH B3H 69800H to 69FFFH D3H 79800H to 79FFFH F3H
4A000H to 4A7FFH 94H 5A000H to 5A7FFH B4H 6A000H to 6A7FFH D4H 7A000H to 7A7FFH F4H
4A800H to 4AFFFH 95H 5A800H to 5AFFFH B5H 6A800H to 6AFFFH D5H 7A800H to 7AFFFH F5H
4B000H to 4B7FFH 96H 5B000H to 5B7FFH B6H 6B000H to 6B7FFH D6H 7B000H to 7B7FFH F6H
4B800H to 4BFFFH 97H 5B800H to 5BFFFH B7H 6B800H to 6BFFFH D7H 7B800H to 7BFFFH F7H
4C000H to 4C7FFH 98H 5C000H to 5C7FFH B8H 6C000H to 6C7FFH D8H 7C000H to 7C7FFH F8H
4C800H to 4CFFFH 99H 5C800H to 5CFFFH B9H 6C800H to 6CFFFH D9H 7C800H to 7CFFFH F9H
4D000H to 4D7FFH 9AH 5D000H to 5D7FFH BAH 6D000H to 6D7FFH DAH 7D000H to 7D7FFH FAH
4D800H to 4DFFFH 9BH 5D800H to 5DFFFH BBH 6D800H to 6DFFFH DBH 7D800H to 7DFFFH FBH
4E000H to 4E7FFH 9CH 5E000H to 5E7FFH BCH 6E000H to 6E7FFH DCH 7E000H to 7E7FFH FCH
4E800H to 4EFFFH 9DH 5E800H to 5EFFFH BDH 6E800H to 6EFFFH DDH 7E800H to 7EFFFH FDH
4F000H to 4F7FFH 9EH 5F000H to 5F7FFH BEH 6F000H to 6F7FFH DEH 7F000H to 7F7FFH FEH
4F800H to 4FFFFH 9FH 5F800H to 5FFFFH BFH 6F800H to 6FFFFH DFH 7F800H to 7FFFFH FFH
Remark
μ
PD78F1162, 78F1162A: Block numbers 00H to 1FH
μ
PD78F1163, 78F1163A: Block numbers 00H to 2FH
μ
PD78F1164, 78F1164A: Block numbers 00H to 3FH
μ
PD78F1165, 78F1165A: Block numbers 00H to 5FH
μ
PD78F1166, 78F1166A: Block numbers 00H to 7FH
μ
PD78F1167, 78F1167A: Block numbers 00H to BFH
μ
PD78F1168, 78F1168A: Block numbers 00H to FFH
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD
62
3.1.1 Internal program memory space
The internal program memory space stores the program and table data.
78K0R/KG3 products incorporate internal ROM (flash memory), as shown below.
Table 3-2. Internal ROM Capacity
Internal ROM Part Number
Structure Capacity
μ
PD78F1162, 78F1162A 65536 × 8 bits (00000H to 0FFFFH)
μ
PD78F1163, 78F1163A 98304 × 8 bits (00000H to 17FFFH)
μ
PD78F1164, 78F1164A 131072 × 8 bits (00000H to 1FFFFH)
μ
PD78F1165, 78F1165A 196608 × 8 bits (00000H to 2FFFFH)
μ
PD78F1166, 78F1166A 262144 × 8 bits (00000H to 3FFFFH)
μ
PD78F1167, 78F1167A 393216 × 8 bits (00000H to 5FFFFH)
μ
PD78F1168, 78F1168A
Flash memory
524288 × 8 bits (00000H to 7FFFFH)
The internal program memory space is divided into the following areas.
(1) Vector table area
The 128-byte area 00000H to 0007FH is reserved as a vector table area. The program start addresses for
branch upon reset or generation of each interrupt request are stored in the vector table area. Furthermore, the
interrupt jump address is a 64 K address of 00000H to 0FFFFH, because the vector code is assumed to be 2
bytes.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd
addresses.
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 63
Table 3-3. Vector Table
Vector Table Address Interrupt Source Vector Table Address Interrupt Source
0002CH INTTM00 00000H RESET input, POC, LVI, WDT,
TRAP 0002EH INTTM01
00004H INTWDTI 00030H INTTM02
00006H INTLVI 00032H INTTM03
00008H INTP0 00034H INTAD
0000AH INTP1 00036H INTRTC
0000CH INTP2 00038H INTRTCI
0000EH INTP3 0003AH INTKR
00010H INTP4 0003CH INTST2/INTCSI20/INTIIC20
00012H INTP5 0003EH INTSR2
00014H INTST3 00040H INTSRE2
00016H INTSR3 00042H INTTM04
00018H INTSRE3 00044H INTTM05
0001AH INTDMA0 00046H INTTM06
0001CH INTDMA1 00048H INTTM07
0001EH INTST0/INTCSI00 0004AH INTP6
00020H INTSR0/INTCSI01 0004CH INTP7
00022H INTSRE0 0004EH INTP8
00024H INTST1/INTCSI10/INTIIC10 00050H INTP9
00026H INTSR1 00052H INTP10
00028H INTSRE1 00054H INTP11
0002AH INTIIC0 0007EH BRK
(2) CALLT instruction table area
The 64-byte area 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT).
Set the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is of 2
bytes).
To use the boot swap function, set a CALLT instruction table also at 01080H to 010BFH.
(3) Option byte area
A 4-byte area of 000C0H to 000C3H can be used as an option byte area. Set the option byte at 010C0H to
010C3H when the boot swap is used. For details, see CHAPTER 24 OPTION BYTE.
(4) On-chip debug security ID setting area
A 10-byte area of 000C4H to 000CDH and 010C4H to 010CDH can be used as an on-chip debug security ID
setting area. Set the on-chip debug security ID of 10 bytes at 000C4H to 000CDH when the boot swap is not
used and at 000C4H to 000CDH and 010C4H to 010CDH when the boot swap is used. For details, see
CHAPTER 26 ON-CHIP DEBUG FUNCTION.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD
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3.1.2 Mirror area
The
μ
PD78F1162 and 78F1162A mirror the data flash area of 00000H to 0FFFFH, to F0000H to FFFFFH.
The
μ
PD78F1163, 78F1163A, 78F1164, 78F1164A, 78F1165, 78F1165A, 78F1166, 78F1166A, 78F1167,
78F1167A, 78F1168, and 78F1168A mirror the data flash area of 00000H to 0FFFFH or 10000H to 1FFFFH, to
F0000H to FFFFFH (the data flash area to be mirrored is set by the processor mode control register (PMC)).
By reading data from F0000H to FFFFFH, an instruction that does not have the ES registers as an operand can be
used, and thus the contents of the data flash can be read with the shorter code. However, the data flash area is not
mirrored to the SFR, extended SFR, RAM, and use prohibited areas.
See 3.1 Memory Space for the mirror area of each product.
The mirror area can only be read and no instruction can be fetched from this area.
The following show examples.
Example 1
μ
PD78F1162, 78F1162A Example 2
μ
PD78F1166, 78F1166A
(Flash memory: 64 KB, RAM: 4 KB) (Flash memory: 256 KB, RAM: 12 KB)
Setting MAA = 0 Setting MAA = 1
Flash memory
Flash memory
Flash memory
01000H
00FFFH
00000H
0EF00H
0EEFFH
10000H
0FFFFH
Mirror
EE000H
EDFFFH
F0000H
EFFFFH
F0800H
F07FFH
F1000H
F0FFFH
FEF00H
FEEFFH
FFEE0H
FFEDFH
FFF00H
FFEFFH
FFFFFH
Special-function register (SFR)
256 bytes
General-purpose register
32 bytes
RAM
4 KB
Flash memory
(same data as 01000H to 0EEFFH)
Special-function register (2nd SFR)
2 KB
External expansion area
888 KB max.
Reserved
Reserved
Special-function register (SFR)
256 bytes
FFFFFH
General-purpose register
32 bytes
FFEE0H
FFEDFH
FFF00H
FFEFFH
RAM
12 KB
FCF00H
FCEFFH Flash memory
(same data as 11000H to 1CEFFH)
F0800H
F07FFH
F1000H
F0FFFH
Reserved
Special-function register (2nd SFR)
2 KB
EE000H
EDFFFH
F0000H
EFFFFH
Reserved
Mirror
External expansion area
696 KB max.
40000H
3FFFFH
00000H
1CF00H
1CEFFH
11000H
10FFFH
Flash memory
Flash memory
Flash memory
Remark MAA: Bit 0 of the processor mode control register (PMC)
PMC register is described below.
For example, 15432H is mirrored to
F5432H. Data can therefore be read by
MOV A, !5432H, instead of MOV ES,
#01H and MOV A, ES:!5432H.
For example, 02345H is mirrored to
F2345H. Data can therefore be read by
MOV A, !2345H, instead of MOV ES,
#00H and MOV A, ES:!2345H.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 65
• Processor mode control register (PMC)
This register selects the flash memory space for mirroring to area from F0000H to FFFFFH.
PMC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 3-8. Format of Processor Mode Control Register (PMC)
Address: FFFFEH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 <0>
PMC 0 0 0 0 0 0 0 MAA
MAA Selection of flash memory space for mirroring to area from F0000H to FFFFFH
0 00000H to 0FFFFH is mirrored to F0000H to FFFFFH
1 10000H to 1FFFFH is mirrored to F0000H to FFFFFH
Cautions 1. Set PMC only once during the initial settings prior to operating the DMA controller. Rewriting
PMC other than during the initial settings is prohibited.
2. After setting PMC, wait for at least one instruction and access the mirror area.
3. When the
μ
PD78F1162 or 78F1162A is used, be sure to set bit 0 (MAA) of this register to 0.
3.1.3 Internal data memory space
78K0R/KG3 products incorporate the following RAMs.
Table 3-4. Internal RAM Capacity
Part Number Internal RAM
μ
PD78F1162, 78F1162A 4096 × 8 bits (FEF00H to FFEFFH)
μ
PD78F1163, 78F1163A 6144 × 8 bits (FE700H to FFEFFH)
μ
PD78F1164, 78F1164A 8192 × 8 bits (FDF00H to FFEFFH)
μ
PD78F1165, 78F1165A 10240 × 8 bits (FD700H to FFEFFH)
μ
PD78F1166, 78F1166A 12288 × 8 bits (FCF00H to FFEFFH)
μ
PD78F1167, 78F1167A 24576 × 8 bits (F9F00H to FFEFFH)
μ
PD78F1168, 78F1168A 30720 × 8 bits (F8700H to FFEFFH)
The internal RAM can be used as a data area and a program area where instructions are written and executed.
Four general-purpose register banks consisting of eight 8-bit registers per bank are assigned to the 32-byte area of
FFEE0H to FFEFFH of the internal RAM area. However, instructions cannot be executed by using general-purpose
registers.
The internal RAM is used as a stack memory.
Cautions 1. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or as a stack area.
2. While using the self-programming function, the area of FFE20H to FFEFFH cannot be used as
a stack memory. Furthermore, the areas of FCF00H to FD6FFH and F8700H to F8EFFH also
cannot be used with the
μ
PD78F1166 and 78F1166A, and
μ
PD78F1168 and 78F1168A,
respectively.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD
66
3.1.4 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see
Table 3-5 in 3.2.4 Special function registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area
On-chip peripheral hardware special function registers (2nd SFRs) are allocated in the area F0000H to F07FFH
(see Table 3-6 in 3.2.5 Extended Special function registers (2nd SFRs: 2nd Special Function Registers)).
SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that
accesses the extended SFR area, however, is 1 byte longer than an instruction that accesses the SFR area.
Caution Do not access addresses to which the 2nd SFR is not assigned.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 67
3.1.6 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of
the register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
78K0R/KG3, based on operability and other considerations. For areas containing data memory in particular, special
addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are
available for use. Figures 3-9 to 3-15 show correspondence between data memory and addressing.
Figure 3-9. Correspondence Between Data Memory and Addressing (
μ
PD78F1162, 78F1162A)
Special function register (SFR)
256 bytes
RAM
4 KB
General-purpose register
32 bytes
Flash memory 64 KB
Special function register (2nd SFR)
2 KB
Mirror area
55.75 KB
External expansion area
888 KB max.
Reserved
Reserved
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Short direct
addressing
SFR addressing
Register addressing
EDFFFH
EE000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
FEEFFH
FEF00H
FFE1FH
FFE20H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFF1FH
FFF20H
FFFFFH
Mirror
MAA = 0
Mirrored area 55.75 KB
00FFFH
01000H
00000H
0EEFFH
0EF00H
0FFFFH
10000H
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD
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Figure 3-10. Correspondence Between Data Memory and Addressing (
μ
PD78F1163, 78F1163A)
Special function register (SFR)
256 bytes
RAM
6 KB
General-purpose register
32 bytes
Flash memory 96 KB
Special function register (2nd SFR)
2 KB
Mirror area
53.75 KB
External expansion area
824 KB max.
Reserved
Reserved
Reserved
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Short direct
addressing
SFR addressing
Register addressing
00000H
17FFFH
18000H
EDFFFH
EE000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
FE6FFH
FE700H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFF1FH
FFF20H
FFE1FH
FFE20H
FFFFFH
1FFFFH
20000H
MAA = 0
Mirror
Mirrored area 53.75 KB
00FFFH
01000H
0E6FFH
0E700H
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CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 69
Figure 3-11. Correspondence Between Data Memory and Addressing (
μ
PD78F1164, 78F1164A)
Special function register (SFR)
256 bytes
RAM
8 KB
General-purpose register
32 bytes
Flash memory 128 KB
Special function register (2nd SFR)
2 KB
Mirror area
51.75 KB
External expansion area
824 KB max.
Reserved
Reserved
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Short direct
addressing
SFR addressing
Register addressing
00000H
EDFFFH
EE000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
FDEFFH
FDF00H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFF1FH
FFF20H
FFE1FH
FFE20H
FFFFFH
1FFFFH
20000H
When MAA = 1
When MAA = 0
Mirror
Mirrored area 51.75 KB
Mirrored area 51.75 KB
00FFFH
01000H
0DEFFH
0DF00H
10FFFH
11000H
1DEFFH
1DF00H
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CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD
70
Figure 3-12. Correspondence Between Data Memory and Addressing (
μ
PD78F1165, 78F1165A)
Special function register (SFR)
256 bytes
RAM
10 KB
General-purpose register
32 bytes
Flash memory 192 KB
Special function register (2nd SFR)
2 KB
Mirror area
49.75 KB
Mirror
External expansion area
760 KB max.
Reserved
Reserved
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Short direct
addressing
SFR addressing
Register addressing
00000H
EDFFFH
EE000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
FD6FFH
FD700H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFF1FH
FFF20H
FFE1FH
FFE20H
FFFFFH
2FFFFH
30000H
When MAA = 1
When MAA = 0
Mirrored area 49.75 KB
Mirrored area 49.75 KB
00FFFH
01000H
0D6FFH
0D700H
10FFFH
11000H
1D6FFH
1D700H
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CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 71
Figure 3-13. Correspondence Between Data Memory and Addressing (
μ
PD78F1166, 78F1166A)
Special function register (SFR)
256 bytes
RAM
Note
12 KB
General-purpose register
32 bytes
Flash memory
256 KB
Special function register (2nd SFR)
2 KB
Mirror area
47.75 KB
Mirror
External expansion area
696 KB max.
Reserved
Reserved
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Short direct
addressing
SFR addressing
Register addressing
00000H
EDFFFH
EE000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
FCEFFH
FCF00H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFF1FH
FFF20H
FFE1FH
FFE20H
FFFFFH
3FFFFH
40000H
When MAA = 1
When MAA = 0
Mirrored area 47.75 KB
Mirrored area 47.75 KB
00FFFH
01000H
0CEFFH
0CF00H
10FFFH
11000H
1CEFFH
1CF00H
Note Use of the area FCF00H to FD6FFH is prohibited when using the self-programming function, since this
area is used for self-programming library.
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CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD
72
Figure 3-14. Correspondence Between Data Memory and Addressing (
μ
PD78F1167, 78F1167A)
Special function register (SFR)
256 bytes
RAM
24 KB
General-purpose register
32 bytes
Flash memory
384 KB
Special function register (2nd SFR)
2 KB
Mirror area
35.75 KB
Mirror
External expansion area
568 KB max.
Reserved
Reserved
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Short direct
addressing
SFR addressing
Register addressing
00000H
EDFFFH
EE000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
F9EFFH
F9F00H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFF1FH
FFF20H
FFE1FH
FFE20H
FFFFFH
5FFFFH
60000H
When MAA = 1
When MAA = 0
Mirrored area 35.75 KB
Mirrored area 35.75 KB
00FFFH
01000H
09EFFH
09F00H
10FFFH
11000H
19EFFH
19F00H
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 73
Figure 3-15. Correspondence Between Data Memory and Addressing (
μ
PD78F1168, 78F1168A)
Special function register (SFR)
256 bytes
RAM
Note
30 KB
General-purpose register
32 bytes
Flash memory
512 KB
Special function register (2nd SFR)
2 KB
Mirror area
29.75 KB
Mirror
External expansion area
440 KB max.
Reserved
Reserved
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Short direct
addressing
SFR addressing
Register addressing
00000H
EDFFFH
EE000H
EFFFFH
F0000H
F07FFH
F0800H
F0FFFH
F1000H
F86FFH
F8700H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFF1FH
FFF20H
FFE1FH
FFE20H
FFFFFH
7FFFFH
80000H
When MAA = 1
When MAA = 0
Mirrored area 29.75 KB
Mirrored area 29.75 KB
00FFFH
01000H
086FFH
08700H
10FFFH
11000H
186FFH
18700H
Note Use of the area F8700H to F8EFFH is prohibited when using the self-programming function, since this area
is used for self-programming library.
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CHAPTER 3 CPU ARCHITECTURE
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74
3.2 Processor Registers
The 78K0R/KG3 products incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 20-bit register that holds the address information of the next program to be executed.
In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be
fetched. When a branch instruction is executed, immediate data and register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-16. Format of Program Counter
19
PC
0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are stored in the stack area upon vector interrupt request acknowledgment or
PUSH PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions.
Reset signal generation sets PSW to 06H.
Figure 3-17. Format of Program Status Word
IE Z RBS1 AC RBS0 ISP0 CY
70
ISP1PSW
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is
controlled with an in-service priority flag (ISP1, ISP0), an interrupt mask flag for various interrupt sources,
and a priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0, RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction
execution is stored.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 75
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
(e) In-service priority flags (ISP1, ISP0)
This flag manages the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests
specified lower than the value of ISP0 and ISP1 by a priority specification flag register (PRn0L, PRn0H,
PRn1L, PRn1H, PRn2L, PRn2H) (see 17.3 (3)) cannot be acknowledged. Actual request acknowledgment is
controlled by the interrupt enable flag (IE).
Remark n = 0, 1
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal RAM area can be
set as the stack area.
Figure 3-18. Format of Stack Pointer
15
SP
SP15 SP14 SP13 SP12 SP11 SP10
SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from
the stack memory.
Each stack operation saves data as shown in Figure 3-19.
Cautions 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP
before using the stack.
2. The values of the stack pointer must be set to even numbers. If odd numbers are specified,
the least significant bit is automatically cleared to 0.
3. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space as a stack
area.
4. While using the self-programming function, the area of FFE20H to FFEFFH cannot be used
as a stack memory. Furthermore, the areas of FCF00H to FD6FFH and F8700H to F8EFFH
also cannot be used with the
μ
PD78F1166 and 78F1166A, and
μ
PD78F1168 and 78F1168A,
respectively.
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CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD
76
Figure 3-19. Data to Be Saved to Stack Memory
PC7 to PC0
PC15 to PC8
PC19 to PC16
PSW
Interrupt, BRK instruction
SP←SP−4
↑
SP−4
↑
SP−3
↑
SP−2
↑
SP−1
↑
SP →
CALL, CALLT instructions
Register pair lower
Register pair higher
PUSH rp instruction
SP←SP−2
↑
SP−2
↑
SP−1
↑
SP →
(4-byte stack) (4-byte stack)
PC7 to PC0
PC15 to PC8
PC19 to PC16
00H
SP←SP−4
↑
SP−4
↑
SP−3
↑
SP−2
↑
SP−1
↑
SP →
00H
PSW
PUSH PSW instruction
SP←SP−2
↑
SP−2
↑
SP−1
↑
SP →
3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The
general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register
(AX, BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
absolute names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of
the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interrupts for each bank.
Caution It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching
instructions or as a stack area.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 77
Figure 3-20. Configuration of General-Purpose Registers
(a) Function name
Register bank 0
Register bank 1
Register bank 2
Register bank 3
FFEFFH
FFEF8H
FFEE0H
HL
DE
BC
AX
H
15 0 7 0
L
D
E
B
C
A
X
16-bit processing 8-bit processing
FFEF0H
FFEE8H
(b) Absolute name
Register bank 0
Register bank 1
Register bank 2
Register bank 3
FFEFFH
FFEF8H
FFEE0H
RP3
RP2
RP1
RP0
R7
15 0 7 0
R6
R5
R4
R3
R2
R1
R0
16-bit processing 8-bit processing
FFEF0H
FFEE8H
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD
78
3.2.3 ES and CS registers
The ES register is used for data access and the CS register is used to specify the higher address when a branch
instruction is executed.
The default value of the ES register after reset is 0FH, and that of the CS register is 00H.
Figure 3-21. Configuration of ES and CS Registers
0 0 0 0 ES3 ES2 ES1 ES0
70
ES
654321
0 0 0 0 CS3 CP2 CP1 CP0
70
CS
654321
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 79
3.2.4 Special function registers (SFRs)
Unlike a general-purpose register, each SFR has a special function.
SFRs are allocated to the FFF00H to FFFFFH area.
SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation
instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This
manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This
manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). When
specifying an address, describe an even address.
Table 3-5 gives a list of the SFRs. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of a special function register. It is a reserved word in the RA78K0R, and is
defined as an sfr variable using the #pragma sfr directive in the CC78K0R. When using the RA78K0R,
ID78K0R-QB, and SM+ for 78K0R, symbols can be written as an instruction operand.
• R/W
Indicates whether the corresponding SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
• Manipulable bit units
“√” indicates the manipulable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon reset signal generation.
Caution Do not access addresses to which SFRs are not assigned.
Remark For extended SFRs (2nd SFRs), see 3.2.5 Extended special function registers (2nd SFRs: 2nd
Special Function Registers).
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD
80
Table 3-5. SFR List (1/5)
Manipulable Bit Range Address Special Function Register (SFR) Name Symbol R/W
1-bit 8-bit 16-bit
After Reset
FFF00H Port register 0 P0 R/W √ √ − 00H
FFF01H Port register 1 P1 R/W √ √ − 00H
FFF02H Port register 2 P2 R/W √ √ − 00H
FFF03H Port register 3 P3 R/W √ √ − 00H
FFF04H Port register 4 P4 R/W √ √ − 00H
FFF05H Port register 5 P5 R/W √ √ − 00H
FFF06H Port register 6 P6 R/W √ √ − 00H
FFF07H Port register 7 P7 R/W √ √ − 00H
FFF08H Port register 8 P8 R/W √ √ − 00H
FFF0BH Port register 11 P11 R/W √ √ − 00H
FFF0CH Port register 12 P12 R/W √ √ − Undefined
FFF0DH Port register 13 P13 R/W √ √ − 00H
FFF0EH Port register 14 P14 R/W √ √ − 00H
FFF0FH Port register 15 P15 R/W √ √ − 00H
FFF10H TXD0/
SIO00
− √
FFF11H
Serial data register 00
−
SDR00 R/W
− −
√ 0000H
FFF12H RXD0/
SIO01
− √
FFF13H
Serial data register 01
−
SDR01 R/W
− −
√ 0000H
FFF14H TXD3
− √
FFF15H
Serial data register 12
−
SDR12 R/W
− −
√ 0000H
FFF16H RXD3
− √
FFF17H
Serial data register 13
−
SDR13 R/W
− −
√ 0000H
FFF18H
FFF19H
Timer data register 00 TDR00 R/W − − √ 0000H
FFF1AH
FFF1BH
Timer data register 01 TDR01 R/W − − √ 0000H
FFF1CH 8-bit D/A conversion value setting register 0 DACS0 R/W √ √ − 00H
FFF1DH 8-bit D/A conversion value setting register 1 DACS1 R/W √ √ − 00H
FFF1EH 10-bit A/D conversion result register ADCR R − − √ 0000H
FFF1FH 8-bit A/D conversion result register ADCRH R − √ − 00H
FFF20H Port mode register 0 PM0 R/W √ √ − FFH
FFF21H Port mode register 1 PM1 R/W √ √ − FFH
FFF22H Port mode register 2 PM2 R/W √ √ − FFH
FFF23H Port mode register 3 PM3 R/W √ √ − FFH
FFF24H Port mode register 4 PM4 R/W √ √ − FFH
FFF25H Port mode register 5 PM5 R/W √ √ − FFH
FFF26H Port mode register 6 PM6 R/W √ √ − FFH
FFF27H Port mode register 7 PM7 R/W √ √ − FFH
FFF28H Port mode register 8 PM8 R/W √ √ − FFH
FFF2BH Port mode register 11 PM11 R/W √ √ − FFH
FFF2CH Port mode register 12 PM12 R/W √ √ − FFH
FFF2DH Port mode register 13 PM13 R/W √ √ − FEH
FFF2EH Port mode register 14 PM14 R/W √ √ − FFH
FFF2FH Port mode register 15 PM15 R/W √ √ − FFH
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 81
Table 3-5. SFR List (2/5)
Manipulable Bit Range Address Special Function Register (SFR) Name Symbol R/W
1-bit 8-bit 16-bit
After Reset
FFF30H A/D converter mode register ADM R/W √ √ − 00H
FFF31H Analog input channel specification register ADS R/W √ √ − 00H
FFF32H D/A converter mode register DAM R/W √ √ − 00H
FFF37H Key return mode register KRM R/W √ √ − 00H
FFF38H External interrupt rising edge enable register 0 EGP0 R/W √ √ − 00H
FFF39H External interrupt falling edge enable register 0 EGN0 R/W √ √ − 00H
FFF3AH External interrupt rising edge enable register 1 EGP1 R/W √ √ − 00H
FFF3BH External interrupt falling edge enable register 1 EGN1 R/W √ √ − 00H
FFF3CH Input switch control register ISC R/W √ √ − 00H
FFF3EH Timer input select register 0 TIS0 R/W √ √ − 00H
FFF44H TXD1/
SIO10
− √
FFF45H
Serial data register 02
−
SDR02 R/W
− −
√ 0000H
FFF46H RXD1
− √
FFF47H
Serial data register 03
−
SDR03 R/W
− −
√ 0000H
FFF48H TXD2/
SIO20
− √
FFF49H
Serial data register 10
−
SDR10 R/W
− −
√ 0000H
FFF4AH RXD2 R/W
− √
FFF4BH
Serial data register 11
−
SDR11
− −
√ 0000H
FFF50H IIC shift register 0 IIC0 R/W − √ − 00H
FFF51H IIC flag register 0 IICF0 R/W √ √ − 00H
FFF52H IIC control register 0 IICC0 R/W √ √ − 00H
FFF53H IIC slave address register 0 SVA0 R/W − √ − 00H
FFF54H IIC clock select register 0 IICCL0 R/W √ √ − 00H
FFF55H IIC function expansion register 0 IICX0 R/W √ √ − 00H
FFF56H IIC status register 0 IICS0 R √ √ − 00H
FFF64H
FFF65H
Timer data register 02 TDR02 R/W − − √ 0000H
FFF66H
FFF67H
Timer data register 03 TDR03 R/W − − √ 0000H
FFF68H
FFF69H
Timer data register 04 TDR04 R/W − − √ 0000H
FFF6AH
FFF6BH
Timer data register 05 TDR05 R/W − − √ 0000H
FFF6CH
FFF6DH
Timer data register 06 TDR06 R/W − − √ 0000H
FFF6EH
FFF6FH
Timer data register 07 TDR07 R/W − − √ 0000H
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD
82
Table 3-5. SFR List (3/5)
Manipulable Bit Range Address Special Function Register (SFR) Name Symbol R/W
1-bit 8-bit 16-bit
After Reset
FFF90H
FFF91H
Sub-count register RSUBC R − − √ 0000H
FFF92H Second count register SEC R/W − √ − 00H
FFF93H Minute count register MIN R/W − √ − 00H
FFF94H Hour count register HOUR R/W − √ − 12HNote 1
FFF95H Week count register WEEK R/W − √ − 00H
FFF96H Day count register DAY R/W − √ − 01H
FFF97H Month count register MONTH R/W − √ − 01H
FFF98H Year count register YEAR R/W − √ − 00H
FFF99H Watch error correction register SUBCUD R/W − √ − 00H
FFF9AH Alarm minute register ALARMWM R/W − √ − 00H
FFF9BH Alarm hour register ALARMWH R/W − √ − 12H
FFF9CH Alarm week register ALARMWW R/W − √ − 00H
FFF9DH Real-time counter control register 0 RTCC0 R/W √ √ − 00H
FFF9EH Real-time counter control register 1 RTCC1 R/W √ √ − 00H
FFF9FH Real-time counter control register 2 RTCC2 R/W √ √ − 00H
FFFA0H Clock operation mode control register CMC R/W − √ − 00H
FFFA1H Clock operation status control register CSC R/W √ √ − C0H
FFFA2H Oscillation stabilization time counter status register OSTC R √ √ − 00H
FFFA3H Oscillation stabilization time select register OSTS R/W − √ − 07H
FFFA4H System clock control register CKC R/W √ √ − 09H
FFFA5H Clock output select register 0 CKS0 R/W √ √ − 00H
FFFA6H Clock output select register 1 CKS1 R/W √ √ − 00H
FFFA8H Reset control flag register RESF R − √ − 00HNote 2
FFFA9H Low-voltage detection register LVIM R/W √ √ − 00HNote 3
FFFAAH Low-voltage detection level select register LVIS R/W √ √ − 0EHNote 4
FFFABH Watchdog timer enable register WDTE R/W − √ − 1A/9ANote 5
FFFACH
FFFADH
− TTBLHNote 6 − − − − Undefined
FFFAEH
FFFAFH
− TTBLLNote 6 − − − − Undefined
Notes 1. The value of this register is 00H if the AMPM bit (bit 3 of the RTCC0 register) is set to 1 after reset.
2. The reset value of RESF varies depending on the reset source.
3. The reset value of LVIM varies depending on the reset source and the setting of the option byte.
4. The reset value of LVIS varies depending on the reset source.
5. The reset value of WDTE is determined by the setting of the option byte.
6. Do not directly operate this SFR, because it cannot be used by the user.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 83
Table 3-5. SFR List (4/5)
Manipulable Bit Range Address Special Function Register (SFR) Name Symbol R/W
1-bit 8-bit 16-bit
After Reset
FFFB0H DMA SFR address register 0 DSA0 R/W − √ − 00H
FFFB1H DMA SFR address register 1 DSA1 R/W − √ − 00H
FFFB2H DMA RAM address register 0L DRA0L R/W − √ 00H
FFFB3H DMA RAM address register 0H DRA0H
DRA0
R/W − √
√
00H
FFFB4H DMA RAM address register 1L DRA1L R/W − √ 00H
FFFB5H DMA RAM address register 1H DRA1H
DRA1
R/W − √
√
00H
FFFB6H DMA byte count register 0L DBC0L R/W − √ 00H
FFFB7H DMA byte count register 0H DBC0H
DBC0
R/W − √
√
00H
FFFB8H DMA byte count register 1L DBC1L R/W − √ 00H
FFFB9H DMA byte count register 1H DBC1H
DBC1
R/W − √
√
00H
FFFBAH DMA mode control register 0 DMC0 R/W √ √ − 00H
FFFBBH DMA mode control register 1 DMC1 R/W √ √ − 00H
FFFBCH DMA operation control register 0 DRC0 R/W √ √ − 00H
FFFBDH DMA operation control register 1 DRC1 R/W √ √ − 00H
FFFBEH Back ground event control register BECTL R/W √ √ − 00H
FFFC0H − PFCMDNote − − − − Undefined
FFFC2H − PFSNote − − − − Undefined
FFFC4H − FLPMCNote − − − − Undefined
FFFD0H Interrupt request flag register 2L IF2L R/W √ √ 00H
FFFD1H Interrupt request flag register 2H IF2H
IF2
R/W √ √
√
00H
FFFD4H Interrupt mask flag register 2L MK2L R/W √ √ FFH
FFFD5H Interrupt mask flag register 2H MK2H
MK2
R/W √ √
√
FFH
FFFD8H Priority specification flag register 02L PR02L R/W √ √ FFH
FFFD9H Priority specification flag register 02H PR02H
PR02
R/W √ √
√
FFH
FFFDCH Priority specification flag register 12L PR12L R/W √ √ FFH
FFFDDH Priority specification flag register 12H PR12H
PR12
R/W √ √
√
FFH
FFFE0H Interrupt request flag register 0L IF0L R/W √ √ 00H
FFFE1H Interrupt request flag register 0H IF0H
IF0
R/W √ √
√
00H
FFFE2H Interrupt request flag register 1L IF1L R/W √ √ 00H
FFFE3H Interrupt request flag register 1H IF1H
IF1
R/W √ √
√
00H
FFFE4H Interrupt mask flag register 0L MK0L R/W √ √ FFH
FFFE5H Interrupt mask flag register 0H MK0H
MK0
R/W √ √
√
FFH
FFFE6H Interrupt mask flag register 1L MK1L R/W √ √ FFH
FFFE7H Interrupt mask flag register 1H MK1H
MK1
R/W √ √
√
FFH
FFFE8H Priority specification flag register 00L PR00L R/W √ √ FFH
FFFE9H Priority specification flag register 00H PR00H
PR00
R/W √ √
√
FFH
FFFEAH Priority specification flag register 01L PR01L R/W √ √ FFH
FFFEBH Priority specification flag register 01H PR01H
PR01
R/W √ √
√
FFH
FFFECH Priority specification flag register 10L PR10L R/W √ √ FFH
FFFEDH Priority specification flag register 10H PR10H
PR10
R/W √ √
√
FFH
Note Do not directly operate this SFR, because it is to be used in the self programming library.
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Table 3-5. SFR List (5/5)
Manipulable Bit Range Address Special Function Register (SFR) Name Symbol R/W
1-bit 8-bit 16-bit
After Reset
FFFEEH Priority specification flag register 11L PR11L R/W √ √ FFH
FFFEFH Priority specification flag register 11H PR11H
PR11
R/W √ √
√
FFH
FFFF0H
FFFF1H
Multiplication input data register A MULA R/W − − √ 0000H
FFFF2H
FFFF3H
Multiplication input data register B MULB R/W − − √ 0000H
FFFF4H
FFFF5H
Higher multiplication result storage register MULOH R − − √ 0000H
FFFF6H
FFFF7H
Lower multiplication result storage register MULOL R − − √ 0000H
FFFFEH Processor mode control register PMC R/W √ √ − 00H
FFFFFH Memory extension mode control register MEM R/W √ √ − 00H
Remark For extended SFRs (2nd SFRs), see Table 3-6 Extended SFR (2nd SFR) List.
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3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers)
Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function.
Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to
FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer
than an instruction that accesses the SFR area.
Extended SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation
instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (!addr16.bit). This
manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (!addr16). This
manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (!addr16). When
specifying an address, describe an even address.
Table 3-6 gives a list of the extended SFRs. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of an extended SFR. It is a reserved word in the RA78K0R, and is defined as an
sfr variable using the #pragma sfr directive in the CC78K0R. When using the RA78K0R, ID78K0R-QB, and
SM+ for 78K0R, symbols can be written as an instruction operand.
• R/W
Indicates whether the corresponding extended SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
• Manipulable bit units
“√” indicates the manipulable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon reset signal generation.
Caution Do not access addresses to which the 2nd SFR is not assigned.
Remark For SFRs in the SFR area, see 3.2.4 Special function registers (SFRs).
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Table 3-6. Extended SFR (2nd SFR) List (1/5)
Manipulable Bit Range Address Special Function Register (SFR) Name Symbol R/W
1-bit 8-bit 16-bit
After Reset
F0017H A/D port configuration register ADPC R/W − √ − 10H
F0030H Pull-up resistor option register 0 PU0 R/W √ √ − 00H
F0031H Pull-up resistor option register 1 PU1 R/W √ √ − 00H
F0033H Pull-up resistor option register 3 PU3 R/W √ √ − 00H
F0034H Pull-up resistor option register 4 PU4 R/W √ √ − 00H
F0035H Pull-up resistor option register 5 PU5 R/W √ √ − 00H
F0036H Pull-up resistor option register 6 PU6 R/W √ √ − 00H
F0037H Pull-up resistor option register 7 PU7 R/W √ √ − 00H
F0038H Pull-up resistor option register 8 PU8 R/W √ √ − 00H
F003CH Pull-up resistor option register 12 PU12 R/W √ √ − 00H
F003DH Pull-up resistor option register 13 PU13 R/W √ √ − 00H
F003EH Pull-up resistor option register 14 PU14 R/W √ √ − 00H
F0040H Port input mode register 0 PIM0 R/W √ √ − 00H
F0044H Port input mode register 4 PIM4 R/W √ √ − 00H
F004EH Port input mode register 14 PIM14 R/W √ √ − 00H
F0050H Port output mode register 0 POM0 R/W √ √ − 00H
F0054H Port output mode register 4 POM4 R/W √ √ − 00H
F005EH Port output mode register 14 POM14 R/W √ √ − 00H
F0060H Noise filter enable register 0 NFEN0 R/W √ √ − 00H
F0061H Noise filter enable register 1 NFEN1 R/W √ √ − 00H
F00F0H Peripheral enable register 0 PER0 R/W √ √ − 00H
F00F1H Peripheral enable register 1 PER1 R/W √ √ − 00H
F00F2H Internal high-speed oscillator trimming register HIOTRM R/W − √ − 10H
F00F3H Operation speed mode control register OSMC R/W − √ − 00H
F00F4H Regulator mode control register RMC R/W − √ − 00H
F00FEH BCD adjust result register BCDADJ R − √ − Undefined
F0100H SSR00L − √
F0101H
Serial status register 00
−
SSR00 R
− −
√ 0000H
F0102H SSR01L − √
F0103H
Serial status register 01
−
SSR01 R
− −
√ 0000H
F0104H SSR02L − √
F0105H
Serial status register 02
−
SSR02 R
− −
√ 0000H
F0106H SSR03L − √
F0107H
Serial status register 03
−
SSR03 R
− −
√ 0000H
F0108H SIR00L − √
F0109H
Serial flag clear trigger register 00
−
SIR00 R/W
− −
√ 0000H
F010AH SIR01L − √
F010BH
Serial flag clear trigger register 01
−
SIR01 R/W
− −
√ 0000H
F010CH SIR02L − √
F010DH
Serial flag clear trigger register 02
−
SIR02 R/W
− −
√ 0000H
F010EH SIR03L − √
F010FH
Serial flag clear trigger register 03
−
SIR03 R/W
− −
√ 0000H
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Table 3-6. Extended SFR (2nd SFR) List (2/5)
Manipulable Bit Range Address Special Function Register (SFR) Name Symbol R/W
1-bit 8-bit 16-bit
After Reset
F0110H
F0111H
Serial mode register 00 SMR00 R/W − − √ 0020H
F0112H
F0113H
Serial mode register 01 SMR01 R/W − − √ 0020H
F0114H
F0115H
Serial mode register 02 SMR02 R/W − − √ 0020H
F0116H
F0117H
Serial mode register 03 SMR03 R/W − − √ 0020H
F0118H
F0119H
Serial communication operation setting register 00 SCR00 R/W − − √ 0087H
F011AH
F011BH
Serial communication operation setting register 01 SCR01 R/W − − √ 0087H
F011CH
F011DH
Serial communication operation setting register 02 SCR02 R/W − − √ 0087H
F011EH
F011FH
Serial communication operation setting register 03 SCR03 R/W − − √ 0087H
F0120H SE0L
√ √
F0121H
Serial channel enable status register 0
−
SE0 R
− −
√ 0000H
F0122H SS0L
√ √
F0123H
Serial channel start register 0
−
SS0 R/W
− −
√ 0000H
F0124H ST0L
√ √
F0125H
Serial channel stop register 0
−
ST0 R/W
− −
√ 0000H
F0126H SPS0L − √
F0127H
Serial clock select register 0
−
SPS0 R/W
− −
√ 0000H
F0128H
F0129H
Serial output register 0 SO0 R/W − − √ 0F0FH
F012AH SOE0L √ √
F012BH
Serial output enable register 0
−
SOE0 R/W
− −
√ 0000H
F0134H SOL0L − √
F0135H
Serial output level register 0
−
SOL0 R/W
− −
√ 0000H
F0140H SSR10L − √
F0141H
Serial status register 10
−
SSR10 R
− −
√ 0000H
F0142H SSR11L − √
F0143H
Serial status register 11
−
SSR11 R
− −
√ 0000H
F0144H SSR12L − √
F0145H
Serial status register 12
−
SSR12 R
− −
√ 0000H
F0146H SSR13L − √
F0147H
Serial status register 13
−
SSR13 R
− −
√ 0000H
F0148H SIR10L − √
F0149H
Serial flag clear trigger register 10
−
SIR10 R/W
− −
√ 0000H
F014AH SIR11L − √
F014BH
Serial flag clear trigger register 11
−
SIR11 R/W
− −
√ 0000H
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Table 3-6. Extended SFR (2nd SFR) List (3/5)
Manipulable Bit Range Address Special Function Register (SFR) Name Symbol R/W
1-bit 8-bit 16-bit
After Reset
F014CH SIR12L − √
F014DH
Serial flag clear trigger register 12
−
SIR12 R/W
− −
√ 0000H
F014EH SIR13L − √
F014FH
Serial flag clear trigger register 13
−
SIR13 R/W
− −
√ 0000H
F0150H
F0151H
Serial mode register 10 SMR10 R/W − − √ 0020H
F0152H
F0153H
Serial mode register 11 SMR11 R/W − − √ 0020H
F0154H
F0155H
Serial mode register 12 SMR12 R/W − − √ 0020H
F0156H
F0157H
Serial mode register 13 SMR13 R/W − − √ 0020H
F0158H
F0159H
Serial communication operation setting register 10 SCR10 R/W − − √ 0087H
F015AH
F015BH
Serial communication operation setting register 11 SCR11 R/W − − √ 0087H
F015CH
F015DH
Serial communication operation setting register 12 SCR12 R/W − − √ 0087H
F015EH
F015FH
Serial communication operation setting register 13 SCR13 R/W − − √ 0087H
F0160H SE1L
√ √
F0161H
Serial channel enable status register 1
−
SE1 R
− −
√ 0000H
F0162H SS1L
√ √
F0163H
Serial channel start register 1
−
SS1 R/W
− −
√ 0000H
F0164H ST1L
√ √
F0165H
Serial channel stop register 1
−
ST1 R/W
− −
√ 0000H
F0166H SPS1L − √
F0167H
Serial clock select register 1
−
SPS1 R/W
− −
√ 0000H
F0168H
F0169H
Serial output register 1 SO1 R/W − − √ 0F0FH
F016AH SOE1L √ √
F016BH
Serial output enable register 1
−
SOE1L R/W
− −
√ 0000H
F0174H SOL1L − √
F0175H
Serial output level register 1
−
SOL1L R/W
− −
√ 0000H
F0180H
F0181H
Timer counter register 00 TCR00 R − − √ FFFFH
F0182H
F0183H
Timer counter register 01 TCR01 R − − √ FFFFH
F0184H
F0185H
Timer counter register 02 TCR02 R − − √ FFFFH
F0186H
F0187H
Timer counter register 03 TCR03 R − − √ FFFFH
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Table 3-6. Extended SFR (2nd SFR) List (4/5)
Manipulable Bit Range Address Special Function Register (SFR) Name Symbol R/W
1-bit 8-bit 16-bit
After Reset
F0188H
F0189H
Timer counter register 04 TCR04 R − − √ FFFFH
F018AH
F018BH
Timer counter register 05 TCR05 R − − √ FFFFH
F018CH
F018DH
Timer counter register 06 TCR06 R − − √ FFFFH
F018EH
F018FH
Timer counter register 07 TCR07 R − − √ FFFFH
F0190H
F0191H
Timer mode register 00 TMR00 R/W − − √ 0000H
F0192H
F0193H
Timer mode register 01 TMR01 R/W − − √ 0000H
F0194H
F0195H
Timer mode register 02 TMR02 R/W − − √ 0000H
F0196H
F0197H
Timer mode register 03 TMR03 R/W − − √ 0000H
F0198H
F0199H
Timer mode register 04 TMR04 R/W − − √ 0000H
F019AH
F019BH
Timer mode register 05 TMR05 R/W − − √ 0000H
F019CH
F019DH
Timer mode register 06 TMR06 R/W − − √ 0000H
F019EH
F019FH
Timer mode register 07 TMR07 R/W − − √ 0000H
F01A0H TSR00L − √
F01A1H
Timer status register 00
−
TSR00 R
− −
√ 0000H
F01A2H TSR01L − √
F01A3H
Timer status register 01
−
TSR01 R
− −
√ 0000H
F01A4H TSR02L − √
F01A5H
Timer status register 02
−
TSR02 R
− −
√ 0000H
F01A6H TSR03L − √
F01A7H
Timer status register 03
−
TSR03 R
− −
√ 0000H
F01A8H TSR04L − √
F01A9H
Timer status register 04
−
TSR04 R
− −
√ 0000H
F01AAH TSR05L − √
F01ABH
Timer status register 05
−
TSR05 R
− −
√ 0000H
F01ACH TSR06L − √
F01ADH
Timer status register 06
−
TSR06 R
− −
√ 0000H
F01AEH TSR07L − √
F01AFH
Timer status register 07
−
TSR07 R
− −
√ 0000H
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Table 3-6. Extended SFR (2nd SFR) List (5/5)
Manipulable Bit Range Address Special Function Register (SFR) Name Symbol R/W
1-bit 8-bit 16-bit
After Reset
F01B0H TE0L
√ √
F01B1H
Timer channel enable status register 0
−
TE0 R
− −
√ 0000H
F01B2H TS0L
√ √
F01B3H
Timer channel start register 0
−
TS0 R/W
− −
√ 0000H
F01B4H TT0L
√ √
F01B5H
Timer channel stop register 0
−
TT0 R/W
− −
√ 0000H
F01B6H TPS0L
− √
F01B7H
Timer clock select register 0
−
TPS0 R/W
− −
√ 0000H
F01B8H TO0L
− √
F01B9H
Timer output register 0
−
TO0 R/W
− −
√ 0000H
F01BAH TOE0L √ √
F01BBH
Timer output enable register 0
−
TOE0 R/W
− −
√ 0000H
F01BCH TOL0L
− √
F01BDH
Timer output level register 0
−
TOL0 R/W
− −
√ 0000H
F01BEH TOM0L − √
F01BFH
Timer output mode register 0
−
TOM0 R/W
− −
√ 0000H
Remark For SFRs in the SFR area, see Table 3-5 SFR List.
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3.3 Instruction Address Addressing
3.3.1 Relative addressing
[Function]
Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the
instruction word (signed complement data: −128 to +127 or −32768 to +32767) to the program counter (PC)’s
value (the start address of the next instruction), and specifies the program address to be used as the branch
destination. Relative addressing is applied only to branch instructions.
Figure 3-22. Outline of Relative Addressing
OP code
PC
DISPLACE 8/16 bits
3.3.2 Immediate addressing
[Function]
Immediate addressing stores immediate data of the instruction word in the program counter, and specifies the
program address to be used as the branch destination.
For immediate addressing, CALL !!addr20 or BR !!addr20 is used to specify 20-bit addresses and CALL !addr16
or BR !addr16 is used to specify 16-bit addresses. 0000 is set to the higher 4 bits when specifying 16-bit
addresses.
Figure 3-23. Example of CALL !!addr20/BR !!addr20
OP code
PC
Low Addr.
High Addr.
Seg Addr.
Figure 3-24. Example of CALL !addr16/BR !addr16
OP code
PC
S
Low Addr.
High Addr.
PC PC
H
PC
L
0000
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3.3.3 Table indirect addressing
[Function]
Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit
immediate data in the instruction word, stores the contents at that table address and the next address in the
program counter (PC) as 16-bit data, and specifies the program address. Table indirect addressing is applied
only for CALLT instructions.
In the 78K0R microcontrollers, branching is enabled only to the 64 KB space from 00000H to 0FFFFH.
Figure 3-25. Outline of Table Indirect Addressing
Low Addr.
High Addr.
0
0000
OP code
00000000 10
Table address
PC
S
PC PC
H
PC
L
Memory
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3.3.4 Register direct addressing
[Function]
Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair
(AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data,
and specifies the program address. Register direct addressing can be applied only to the CALL AX, BC, DE, HL,
and BR AX instructions.
Figure 3-26. Outline of Register Direct Addressing
OP code
PC
S
PC PC
H
PC
L
CS rp
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3.4 Addressing for Processing Data Addresses
3.4.1 Implied addressing
[Function]
Instructions for accessing registers (such as accumulators) that have special functions are directly specified with
the instruction word, without using any register specification field in the instruction word.
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format
is necessary.
Implied addressing can be applied only to MULU X.
Figure 3-27. Outline of Implied Addressing
A register
OP code
Memory
3.4.2 Register addressing
[Function]
Register addressing accesses a general-purpose register as an operand. The instruction word of 3-bit long is
used to select an 8-bit register and the instruction word of 2-bit long is used to select a 16-bit register.
[Operand format]
Identifier Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL
Figure 3-28. Outline of Register Addressing
Register
OP code
Memory
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3.4.3 Direct addressing
[Function]
Direct addressing uses immediate data in the instruction word as an operand address to directly specify the
target address.
[Operand format]
Identifier Description
ADDR16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable)
ES: ADDR16 Label or 16-bit immediate data (higher 4-bit addresses are specified by the ES register)
Figure 3-29. Example of ADDR16
Target memory
OP code
Memory
Low Addr.
High Addr.
FFFFFH
F0000H
Figure 3-30. Example of ES:ADDR16
OP code
Memory
Low Addr.
High Addr.
FFFFFH
00000H
Target memory
ES
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3.4.4 Short direct addressing
[Function]
Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type
of addressing is applied only to the space from FFE20H to FFF1FH.
[Operand format]
Identifier Description
SADDR Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data
(only the space from FFE20H to FFF1FH is specifiable)
SADDRP Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data (even address only)
(only the space from FFE20H to FFF1FH is specifiable)
Figure 3-31. Outline of Short Direct Addressing
OP code
Memory
saddr
FFF1FH
FFE20H
saddr
Remark SADDR and SADDRP are used to describe the values of addresses FE20H to FF1FH with 16-bit
immediate data (higher 4 bits of actual address are omitted), and the values of addresses FFE20H to
FFF1FH with 20-bit immediate data.
Regardless of whether SADDR or SADDRP is used, addresses within the space from FFE20H to
FFF1FH are specified for the memory.
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3.4.5 SFR addressing
[Function]
SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of
addressing is applied only to the space from FFF00H to FFFFFH.
[Operand format]
Identifier Description
SFR SFR name
SFRP 16-bit-manipulable SFR name (even address only)
Figure 3-32. Outline of SFR Addressing
OP code
Memory
SFR
FFFFFH
FFF00H
SFR
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3.4.6 Register indirect addressing
[Function]
Register indirect addressing directly specifies the target addresses using the contents of the register pair
specified with the instruction word as an operand address.
[Operand format]
Identifier Description
− [DE], [HL] (only the space from F0000H to FFFFFH is specifiable)
− ES:[DE], ES:[HL] (higher 4-bit addresses are specified by the ES register)
Figure 3-33. Example of [DE], [HL]
Target memory
OP code
Memory
rp
FFFFFH
F0000H
Figure 3-34. Example of ES:[DE], ES:[HL]
OP code
Memory
FFFFFH
00000H
Target memory
ES
rp
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3.4.7 Based addressing
[Function]
Based addressing uses the contents of a register pair specified with the instruction word as a base address, and
8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the
target address.
[Operand format]
Identifier Description
− [HL + byte], [DE + byte], [SP + byte] (only the space from F0000H to FFFFFH is specifiable)
− word[B], word[C] (only the space from F0000H to FFFFFH is specifiable)
− word[BC] (only the space from F0000H to FFFFFH is specifiable)
− ES:[HL + byte], ES:[DE + byte] (higher 4-bit addresses are specified by the ES register)
− ES:word[B], ES:word[C] (higher 4-bit addresses are specified by the ES register)
− ES:word[BC] (higher 4-bit addresses are specified by the ES register)
Figure 3-35. Example of [SP+byte]
Target memory
OP code
Memory
byte
FFFFFH
F0000H
SP
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Figure 3-36. Example of [HL + byte], [DE + byte]
Target memory
OP code
Memory
byte
FFFFFH
F0000H
rp (HL/DE)
Figure 3-37. Example of word[B], word[C]
Target memory
Memory
FFFFFH
F0000H
r (B/C)
OP code
Low Addr.
High Addr.
Figure 3-38. Example of word[BC]
Target memory
Memory
FFFFFH
F0000H
rp (BC)
OP code
Low Addr.
High Addr.
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Figure 3-39. Example of ES:[HL + byte], ES:[DE + byte]
OP code
byte
rp (HL/DE)
Memory
FFFFFH
00000H
Target memory
ES
Figure 3-40. Example of ES:word[B], ES:word[C]
r (B/C)
Memory
FFFFFH
00000H
Target memory
ES
OP code
Low Addr.
High Addr.
Figure 3-41. Example of ES:word[BC]
rp (BC)
Memory
FFFFFH
00000H
Target memory
ES
OP code
Low Addr.
High Addr.
CHAPTER 3 CPU ARCHITECTURE
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3.4.8 Based indexed addressing
[Function]
Based indexed addressing uses the contents of a register pair specified with the instruction word as the base
address, and the content of the B register or C register similarly specified with the instruction word as offset
address. The sum of these values is used to specify the target address.
[Operand format]
Identifier Description
− [HL+B], [HL+C] (only the space from F0000H to FFFFFH is specifiable)
− ES:[HL+B], ES:[HL+C] (higher 4-bit addresses are specified by the ES register)
Figure 3-42. Example of [HL+B], [HL+C]
Target memory
Memory
FFFFFH
F0000H
r (B/C)
rp (HL)
OP code
Figure 3-43. Example of ES:[HL+B], ES:[HL+C]
r (B/C)
OP code
rp (HL)
ES
Memory
FFFFFH
00000H
Target memory
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17894EJ9V0UD 103
3.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing is automatically
employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is
saved/restored upon generation of an interrupt request.
Stack addressing is applied only to the internal RAM area.
[Operand format]
Identifier Description
− PUSH AX/BC/DE/HL
POP AX/BC/DE/HL
CALL/CALLT
RET
BRK
RETB
(Interrupt request generated)
RETI
User’s Manual U17894EJ9V0UD
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CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
There are five types of pin I/O buffer power supplies: AVREF0, AVREF1, EVDD0, EVDD1, and VDD. The relationship
between these power supplies and the pins is shown below.
Table 4-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins
AVREF0 P20 to P27, P150 to P157
AVREF1 P110, P111
EVDD0, EVDD1 • Port pins other than P20 to P27, P110, P111, P121 to P124, and P150 to P157
• RESET and FLMD0 pins
VDD • P121 to P124
• Non-port pins (excluding RESET and FLMD0 pins)
78K0R/KG3 products are provided with the ports shown in Figure 4-1, which enable variety of control operations.
The functions of each port are shown in Table 4-2.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the
alternate functions, see CHAPTER 2 PIN FUNCTIONS.
Figure 4-1. Port Types
Port 0
P00
P06
Port 1
P10
P17
Port 3
P30
P31
P20
Port 2
P27
Port 7
P70
P77
P120
Port 12
P124
P40
Port 4
P47
Port 8
P80
P87
Port 11 P110
P111
Port 13 P130
P131
Port 14
P140
P145
Port 15
P150
P157
P50
Port 5
P57
P60
Port 6
P67
CHAPTER 4 PORT FUNCTIONS
User’s Manual U17894EJ9V0UD 105
Table 4-2. Port Functions (1/2)
Function Name I/O Function After Reset Alternate Function
P00 TI00
P01 TO00
P02 SO10/TxD1
P03 SI10/RxD1/SDA10
P04 SCK10/SCL10
P05 CLKOUT
P06
I/O Port 0.
7-bit I/O port.
Input of P03 and P04 can be set to TTL input buffer.
Output of P02 to P04 can be set to N-ch open-drain output
(VDD tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
WAIT
P10 SCK00/EX24
P11 SI00/RxD0/EX25
P12 SO00/TxD0/EX26
P13 TxD3/EX27
P14 RxD3/EX28
P15 RTCDIV/RTCCL/EX29
P16 TI01/TO01/INTP5/
EX30
P17
I/O Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
TI02/TO02/EX31
P20 to P27 I/O Port 2.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Digital input
port
ANI0 to ANI7
P30 RTC1HZ/INTP3
P31
I/O Port 3.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
TI03/TO03/INTP4
P40Note TOOL0
P41 TOOL1
P42 TI04/TO04
P43 SCK01
P44 SI01
P45 SO01
P46 INTP1/TI05/TO05
P47
I/O Port 4.
8-bit I/O port.
Input of P43 and P44 can be set to TTL input buffer.
Output of P43 and P45 can be set to N-ch open-drain output
(VDD tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
INTP2
P50 to P57 I/O Port 5.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port EX8 to EX15
Note If on-chip debugging is enabled by using an option byte, be sure to pull up the P40/TOOL0 pin externally
(see Caution in 2.2.5 P40 to P47 (port 4)).
CHAPTER 4 PORT FUNCTIONS
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Table 4-2. Port Functions (2/2)
Function Name I/O Function After Reset Alternate Function
P60 SCL0
P61 SDA0
P62 −
P63 −
P64 RD
P65 WR0
P66 WR1
P67
I/O Port 6.
8-bit I/O port.
Output of P60 to P63 can be set to N-ch open-drain output (6
V tolerance).
Input/output can be specified in 1-bit units.
For only P64 to P67, use of an on-chip pull-up resistor can be
specified by a software setting.
Input port
ASTB
P70 to P73 KR0/EX16 to KR3/
EX19
P74 to P77
I/O Port 7.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
KR4/EX20/INTP8 to
KR7/EX23/INTP11
P80 to P87 I/O Port 8.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port EX0 to EX7
P110 ANO0
P111
I/O Port 11.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Input port
ANO1
P120 I/O INTP0/EXLVI
P121 X1
P122 X2/EXCLK
P123 XT1
P124
Input
Port 12.
1-bit I/O port and 4-bit input port.
For only P120, use of an on-chip pull-up resistor can be
specified by a software setting.
Input port
XT2
P130 Output Output port −
P131 I/O
Port 13.
1-bit output port and 1-bit I/O port.
For only P131, use of an on-chip pull-up resistor can be
specified by a software setting.
Input port TI06/TO06
P140 PCLBUZ0/INTP6
P141 PCLBUZ1/INTP7
P142 SCK20/SCL20
P143 SI20/RxD2/SDA20
P144 SO20/TxD2
P145
I/O Port 14.
6-bit I/O port.
Input of P142 and P143 can be set to TTL input buffer.
Output of P142 to P144 can be set to the N-ch open-drain
output (VDD tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
TI07/TO07
P150 to P157 I/O Port 15.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Digital input
port
ANI8 to ANI15
CHAPTER 4 PORT FUNCTIONS
User’s Manual U17894EJ9V0UD 107
4.2 Port Configuration
Ports include the following hardware.
Table 4-3. Port Configuration
Item Configuration
Control registers Port mode registers (PM0 to PM8, PM11 to PM15)
Port registers (P0 to P8, P11 to P15)
Pull-up resistor option registers (PU0, PU1, PU3 to PU8, PU12 to PU14)
Port input mode registers (PIM0, PIM4, PIM14)
Port output mode registers (POM0, POM4, POM14)
A/D port configuration register (ADPC)
Port Total: 88 (CMOS I/O: 79, CMOS input: 4, CMOS output: 1, N-ch open drain I/O: 4)
Pull-up resistor Total: 61
CHAPTER 4 PORT FUNCTIONS
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4.2.1 Port 0
Port 0 is a 7-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units
using port mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
Input to the P03 and P04 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units
using port input mode register 0 (PIM0).
Output from the P02 to P04 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using
port output mode register 0 (POM0).
This port can also be used for timer I/O, serial interface data I/O, clock I/O, internal system clock output, and
external wait signal input.
Reset signal generation sets port 0 to input mode.
Figures 4-2 to 4-7 show block diagrams of port 0.
Cautions 1. To use P01/TO00 as a general-purpose port, set bit 0 (TO00) of timer output register 0 (TO0)
and bit 0 (TOE00) of timer output enable register 0 (TOE0) to “0”, which is the same as their
default status setting.
2. To use P02/SO10/TxD1, P03/SI10/RxD1/SDA10, or P04/SCK10/SCL10 as a general-purpose
port, note the serial array unit 0 setting. For details, refer to the following tables.
• Table 13-7 Relationship Between Register Settings and Pins (Channel 2 of Unit 0: CSI10,
UART1 Transmission, IIC10)
• Table 13-8 Relationship Between Register Settings and Pins (Channel 3 of Unit 0: UART1
Reception)
Figure 4-2. Block Diagram of P00
P00/TI00
WR
PU
RD
WR
PORT
WR
PM
PU00
Alternate
function
Output latch
(P00)
PM00
EV
DD0
, EV
DD1
P-ch
Selector
Internal bus
PU0
PM0
P0
P0: Port register 0
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
CHAPTER 4 PORT FUNCTIONS
User’s Manual U17894EJ9V0UD 109
Figure 4-3. Block Diagram of P01
P01/TO00
WR
PU
RD
WR
PORT
WR
PM
PU01
PM01
EV
DD0
, EV
DD1
P-ch
PU0
PM0
P0
Selector
Alternate
function
Output latch
(P01)
Internal bus
P0: Port register 0
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
CHAPTER 4 PORT FUNCTIONS
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Figure 4-4. Block Diagram of P02
P02/SO10/TxD1
WR
PU
RD
WR
PORT
WR
PM
PU02
PM02
EV
DD0
, EV
DD1
P-ch
PU0
PM0
P0
POM02
POM0
WR
POM
Selector
Internal bus
Output latch
(P02)
Alternate
function
P0: Port register 0
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
POM0: Port output mode register 0
RD: Read signal
WR××: Write signal
CHAPTER 4 PORT FUNCTIONS
User’s Manual U17894EJ9V0UD 111
Figure 4-5. Block Diagram of P03 and P04
P03/SI10/RxD1/SDA10,
P04/SCK10/SCL10
WR
PU
RD
WR
PORT
PU03, PU04
EV
DD0
, EV
DD1
P-ch
PU0
P0
WR
PM
PM0
POM03, POM04
POM0
WR
POM
PM03, PM04
CMOS
TTL
PIM0
PIM03, PIM04
WR
PIM
Alternate
function
Output latch
(P03, P04)
Alternate
function
Selector
Internal bus
P0: Port register 0
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
PIM0: Port input mode register 0
POM0: Port output mode register 0
RD: Read signal
WR××: Write signal
CHAPTER 4 PORT FUNCTIONS
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Figure 4-6. Block Diagram of P05
P05/CLKOUT
WR
PU
RD
WR
PORT
WR
PM
EV
DD0
, EV
DD1
P-ch
PU0
PM0
P0
PM05
PU05
Alternate
function
Output latch
(P05)
Selector
Internal bus
P0: Port register 0
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
CHAPTER 4 PORT FUNCTIONS
User’s Manual U17894EJ9V0UD 113
Figure 4-7. Block Diagram of P06
P06/WAIT
WR
PU
RD
WR
PORT
WR
PM
EV
DD0
, EV
DD1
P-ch
PU0
PM0
P0
PM06
PU06
Alternate
function
Output latch
(P06)
Selector
Internal bus
Alternate
function
P0: Port register 0
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
CHAPTER 4 PORT FUNCTIONS
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4.2.2 Port 1
Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units
using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, timer I/O, real-
time counter clock output, and external expansion output (address bus).
Reset signal generation sets port 1 to input mode.
Figures 4-8 to 4-12 show block diagrams of port 1.
Cautions 1. To use P10/SCK00/EX24, P11/SI00/RxD0/EX25, P12/SO00/TxD0/EX26, P13/TxD3/EX27, or
P14/RxD3/EX28 as a general-purpose port, note the serial array unit setting. For details, refer
to the following tables.
• Table 13-5 Relationship Between Register Settings and Pins (Channel 0 of Unit 0: CSI00,
UART0 Transmission)
• Table 13-6 Relationship Between Register Settings and Pins (Channel 1 of Unit 0: CSI01,
UART0 Reception)
• Table 13-11 Relationship Between Register Settings and Pins (Channel 2 of Unit 1: UART3
Transmission)
• Table 13-12 Relationship Between Register Settings and Pins (Channel 3 of Unit 1: UART3
Reception)
2. To use P16/TI01/TO01/INTP5/EX30 or P17/TI02/TO02/EX31 as a general-purpose port, set bits
1 and 2 (TO01, TO02) of timer output register 0 (TO0) and bits 1 and 2 (TOE01, TOE02) of
timer output enable register 0 (TOE0) to “0”, which is the same as their default status setting.
3. To use P15/RTCDIV/RTCCL/EX29 as a general-purpose port, set bit 4 (RCLOE0) of real-time
counter control register 0 (RTCC0) and bit 6 (RCLOE2) of real-time counter control register 2
(RTCC2) to “0”, which is the same as their default status settings.
4. Do not enable outputting other alternate functions when the external expansion output
(address bus) function is used.
CHAPTER 4 PORT FUNCTIONS
User’s Manual U17894EJ9V0UD 115
Figure 4-8. Block Diagram of P10
P10/SCK00/EX24
WR
PU
RD
WR
PORT
WR
PM
PU10
PM10
EV
DD0
, EV
DD1
P-ch
PU1
PM1
P1
Alternate
function
Alternate
function
Output latch
(P10)
Selector
Internal bus
Alternate
function
P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
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Figure 4-9. Block Diagram of P11 and P14
P11/SI00/RxD0/EX25,
P14/RxD3/EX28
WR
PU
RD
WR
PORT
WR
PM
PU11, PU14
PM11, PM14
EV
DD0
, EV
DD1
P-ch
PU1
PM1
P1
Alternate
function
Output latch
(P11, P14)
Selector
Internal bus
Alternate
function
P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
CHAPTER 4 PORT FUNCTIONS
User’s Manual U17894EJ9V0UD 117
Figure 4-10. Block Diagram of P12 and P13
P12/SO00/TxD0/EX26,
P13/TxD3/EX27
WR
PU
RD
WR
PORT
WR
PM
PU12, PU13
PM12, PM13
EV
DD0
, EV
DD1
P-ch
PU1
PM1
P1
Alternate
function
Output latch
(P12, P13)
Selector
Internal bus
Alternate
function
P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
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User’s Manual U17894EJ9V0UD
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Figure 4-11. Block Diagram of P15
P15/RTCDIV/RTCCL/EX29
WRPU
RD
WRPORT
WRPM
PU15
PM15
EVDD0, EVDD1
P-ch
PU1
PM1
P1
Output latch
(P15)
Selector
Internal bus
Alternate
function
P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
CHAPTER 4 PORT FUNCTIONS
User’s Manual U17894EJ9V0UD 119
Figure 4-12. Block Diagram of P16 and P17
P16/TI01/TO01/INTP5/EX30,
P17/TI02/TO02/EX31
WRPU
RD
WRPORT
WRPM
PU16, PU17
PM16, PM17
EVDD0, EVDD1
P-ch
PM1
PU1
P1
Alternate
function
Output latch
(P16, P17)
Selector
Internal bus
Alternate
function
P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
CHAPTER 4 PORT FUNCTIONS
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4.2.3 Port 2
Port 2 is an 8-bit I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units
using port mode register 2 (PM2).
This port can also be used for A/D converter analog input.
To use P20/ANI0 to P27/ANI7 as digital input pins, set them in the digital I/O mode by using the A/D port
configuration register (ADPC) and in the input mode by using PM2. Use these pins starting from the lower bit.
To use P20/ANI0 to P27/ANI7 as digital output pins, set them in the digital I/O mode by using ADPC and in the
output mode by using PM2.
To use P20/ANI0 to P27/ANI7 as analog input pins, set them in the analog input mode by using the A/D port
configuration register (ADPC) and in the input mode by using PM2. Use these pins starting from the upper bit.
Table 4-4. Setting Functions of P20/ANI0 to P27/ANI7 Pins
ADPC PM2 ADS P20/ANI0 to P27/ANI7 Pins
Input mode − Digital input Digital I/O selection
Output mode − Digital output
Selects ANI. Analog input (to be converted) Input mode
Does not select ANI. Analog input (not to be converted)
Selects ANI.
Analog input selection
Output mode
Does not select ANI.
Setting prohibited
All P20/ANI0 to P27/ANI7 are set in the digital input mode when the reset signal is generated.
Figure 4-13 shows a block diagram of port 2.
Caution See 2.2.15 AVREF0 for the voltage to be applied to the AVREF0 pin when using port 2 as a digital I/O.
CHAPTER 4 PORT FUNCTIONS
User’s Manual U17894EJ9V0UD 121
Figure 4-13. Block Diagram of P20 to P27
Internal bus
P20/ANI0 to
P27/ANI7
RD
WR
PORT
WR
PM
Output latch
(P20 to P27)
PM20 to PM27
Selector
PM2
A/D converter
P2
P2: Port register 2
PM2: Port mode register 2
RD: Read signal
WR××: Write signal
CHAPTER 4 PORT FUNCTIONS
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4.2.4 Port 3
Port 3 is a 2-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units
using port mode register 3 (PM3). When the P30 and P31 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3).
This port can also be used for external interrupt request input, timer I/O, and real-time counter correction clock
output.
Reset signal generation sets port 3 to input mode.
Figure 4-14 shows block a diagram of port 3.
Cautions 1. To use P31/TI03/TO03/INTP4 as a general-purpose port, set bit 3 (TO03) of timer output
register 0 (TO0) and bit 3 (TOE03) of timer output enable register 0 (TOE0) to “0”, which is the
same as their default status setting.
2. To use P30/RTC1HZ/INTP3 as a general-purpose port, set bit 5 (RCLOE1) of real-time counter
control register 0 (RTCC0) to “0”, which is the same as its default status setting.
Figure 4-14. Block Diagram of P30 and P31
P30/RTC1HZ/INTP3,
P31/TI03/TO03/INTP4
WR
PU
RD
WR
PORT
WR
PM
PU30, PU31
PM30, PM31
EV
DD0
, EV
DD1
P-ch
PU3
PM3
P3
Alternate
function
Output latch
(P30, P31)
Selector
Internal bus
Alternate
function
P3: Port register 3
PU3: Pull-up resistor option register 3
PM3: Port mode register 3
RD: Read signal
WR××: Write signal
CHAPTER 4 PORT FUNCTIONS
User’s Manual U17894EJ9V0UD 123
4.2.5 Port 4
Port 4 is an 8-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units
using port mode register 4 (PM4). When the P40 to P47 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4)Note.
Input to the P43 and P44 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units
using port input mode register 4 (PIM4).
Output from the P43 and P45 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using
port output mode register 4 (POM4).
This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, flash memory
programmer/debugger data I/O, clock output, and timer I/O.
Reset signal generation sets port 4 to input mode.
Figures 4-15 to 4-22 show block diagrams of port 4.
Note When a tool is connected, the P40 and P41 pins cannot be connected to a pull-up resistor.
Cautions 1. When a tool is connected, the P40 pin cannot be used as a port pin.
When the on-chip debug function is used, P41 pin can be used as follows by the mode
setting on the debugger.
1-line mode: can be used as a port (P41).
2-line mode: used as a TOOL1 pin and cannot be used as a port (P41).
2. To use P43/SCK01, P44/SI01, or P45/SO01 as a general-purpose port, note the serial array
unit 0 setting. For details, refer to Table 13-6 Relationship Between Register Settings and
Pins (Channel 1 of Unit 0: CSI01, UART0 reception).
3. To use P42/TI04/TO04 or P46/INTP1/TI05/TO05 as a general-purpose port, set bits 4 and 5
(TO04, TO05) of timer output register 0 (TO0) and bits 4 and 5 (TOE04, TOE05) of timer output
enable register 0 (TOE0) to “0”, which is the same as their default status setting.
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User’s Manual U17894EJ9V0UD
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Figure 4-15. Block Diagram of P40
P40/TOOL0
RD
WRPORT
WRPM
PM4
P4
WRPU
EVDD0, EVDD1
P-ch
PU4
PM40
PU40
Alternate
function
Output latch
(P40)
Selector
Selector
Internal bus
Alternate
function
P4: Port register 4
PU4: Pull-up resistor option register 4
PM4: Port mode register 4
RD: Read signal
WR××: Write signal
CHAPTER 4 PORT FUNCTIONS
User’s Manual U17894EJ9V0UD 125
Figure 4-16. Block Diagram of P41
P41/TOOL1
WRPU
RD
WRPORT
WRPM
PU41
PM41
EVDD0, EVDD1
P-ch
PU4
PM4
P4
Output latch
(P41)
Selector
Selector
Internal bus
Alternate
function
P4: Port register 4
PU4: Pull-up resistor option register 4
PM4: Port mode register 4
RD: Read signal
WR××: Write signal
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Figure 4-17. Block Diagram of P42
P42/TI04/TO04
RD
WRPORT
WRPM
PM4
P4
WRPU
EVDD0, EVDD1
P-ch
PU4
PM42
PU42
Alternate
function
Output latch
(P42)
Selector
Internal bus
Alternate
function
P4: Port register 4
PU4: Pull-up resistor option register 4
PM4: Port mode register 4
RD: Read signal
WR××: Write signal
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Figure 4-18. Block Diagram of P43
P43/SCK01
WR
PU
RD
WR
PORT
PU43
EV
DD0
, EV
DD1
P-ch
PU4
P4
CMOS
TTL
PIM4
PIM43
WR
PIM
WR
PM
PM4
POM43
POM4
WR
POM
PM43
Alternate
function
Output latch
(P43)
Selector
Internal bus
Alternate
function
P4: Port register 4
PU4: Pull-up resistor option register 4
PM4: Port mode register 4
PIM4: Port input mode register 4
POM4: Port output mode register 4
RD: Read signal
WR××: Write signal
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Figure 4-19. Block Diagram of P44
CMOS
TTL
PIM4
PIM44
WR
PIM
P44/SI01
WR
PU
RD
PU4
PM4
WR
PORT
WR
PM
PU44
PM44
EV
DD0
, EV
DD1
P-ch
P4
Output latch
(P44)
Selector
Internal bus
Alternate
function
P4: Port register 4
PU4: Pull-up resistor option register 4
PM4: Port mode register 4
PIM4: Port input mode register 4
RD: Read signal
WR××: Write signal
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Figure 4-20. Block Diagram of P45
WRPM
PM4
POM45
POM4
WRPOM
PM45
P45/SO01
WRPU
RD
WRPORT
PU45
EVDD0, EVDD1
P-ch
PU4
P4
Output latch
(P45)
Selector
Internal bus
Alternate
function
P4: Port register 4
PU4: Pull-up resistor option register 4
PM4: Port mode register 4
POM4: Port output mode register 4
RD: Read signal
WR××: Write signal
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Figure 4-21. Block Diagram of P46
P46/TI05/TO05/INTP1
WR
PU
RD
WR
PORT
WR
PM
PU46
PM46
EV
DD0
, EV
DD1
P-ch
PM4
PU4
P4
Alternate
function
Output latch
(P46)
Selector
Internal bus
Alternate
function
P4: Port register 4
PU4: Pull-up resistor option register 4
PM4: Port mode register 4
RD: Read signal
WR××: Write signal
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Figure 4-22. Block Diagram of P47
P47/INTP2
WR
PU
RD
PU4
PM4
WR
PORT
WR
PM
PU47
PM47
EV
DD0
, EV
DD1
P-ch
P4
Output latch
(P47)
Selector
Internal bus
Alternate
function
P4: Port register 4
PU4: Pull-up resistor option register 4
PM4: Port mode register 4
RD: Read signal
WR××: Write signal
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4.2.6 Port 5
Port 5 is an 8-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units
using port mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 5 (PU5).
This port can also be used for external expansion I/O (multiplexed address/data bus, address bus, data bus).
When the external expansion I/O function is used, it controls the I/O ignoring the settings on port mode register 5
(PM5), port register 5 (P5), and pull-up resistor option register 5 (PU5).
Reset signal generation sets port 5 to input mode.
Figures 4-23 and 4-24 show block diagrams of port 5.
Figure 4-23. Block Diagram of P50 and P51
P50/EX8,
P51/EX9
WR
PU
RD
WR
PORT
WR
PM
PU50, PU51
PM50, PM51
EV
DD0
, EV
DD1
P-ch
PM5
PU5
P5
EXEN, MM0 to MM3
Alternate
function
Output latch
(P50, P51)
Selector
Selector
Internal bus
Alternate
function
P5: Port register 5
PU5: Pull-up resistor option register 5
PM5: Port mode register 5
RD: Read signal
WR××: Write signal
EXEN: Bit 7 of memory extension mode control register (MEM)
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Figure 4-24. Block Diagram of P52 to P57
P52/EX10 to
P57/EX15
WRPU
RD
WRPORT
WRPM
PU52 to PU57
PM52 to PM57
EVDD0, EVDD1
P-ch
PM5
PU5
P5
EXEN, MM0 to MM3
Alternate
function
Output latch
(P52 to P57)
Selector
Selector
Internal bus
Alternate
function
P5: Port register 5
PU5: Pull-up resistor option register 5
PM5: Port mode register 5
RD: Read signal
WR××: Write signal
EXEN: Bit 7 of memory extension mode control register (MEM)
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4.2.7 Port 6
Port 6 is an 8-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units
using port mode register 6 (PM6). When the P64 to P67 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 6 (PU6).
The output of the P60 to P63 pins is N-ch open-drain output (6 V tolerance).
This port can also be used for serial interface data I/O, clock I/O, read strobe signal output, write strobe signal
output (8-bit bus mode, 16-bit bus mode (lower)), write strobe signal output (16-bit bus mode (higher)), and address
strobe signal output.
Reset signal generation sets port 6 to input mode.
Figures 4-25 to 4-27 show block diagrams of port 6.
Caution Stop the operation of serial interface IIC0 when using P60/SCL0 and P61/SDA0 as general-
purpose ports.
Figure 4-25. Block Diagram of P60 and P61
P60/SCL0,
P61/SDA0
RD
WR
PORT
WR
PM
Alternate
function
Output latch
(P60, P61)
PM60, PM61
Alternate
function
Internal bus
Selector
PM6
P6
P6: Port register 6
PM6: Port mode register 6
RD: Read signal
WR××: Write signal
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Figure 4-26. Block Diagram of P62 and P63
P62, P63
RD
WR
PORT
WR
PM
Output latch
(P62, P63)
PM62, PM63
Internal bus
Selector
PM6
P6
P6: Port register 6
PM6: Port mode register 6
RD: Read signal
WR××: Write signal
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Figure 4-27. Block Diagram of P64 to P67
P64/RD,
P65/WR0,
P66/WR1,
P67/ASTB
WR
PU
RD
WR
PORT
WR
PM
PU64 to PU67
PM64 to PM67
EV
DD0
, EV
DD1
P-ch
PU6
PM6
P6
Alternate
function
Output latch
(P64 to P67)
Internal bus
Selector
P6: Port register 6
PU6: Pull-up resistor option register 6
PM6: Port mode register 6
RD: Read signal
WR××: Write signal
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4.2.8 Port 7
Port 7 is an 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units
using port mode register 7 (PM7). When used as an input port, use of an on-chip pull-up resistor can be specified in
1-bit units by pull-up resistor option register 7 (PU7).
This port can also be used for key return input, external expansion output (address bus), and interrupt request
input.
Reset signal generation sets port 7 to input mode.
Figure 4-28 shows a block diagram of port 7.
Figure 4-28. Block Diagram of P70 to P77
P70/KR0/EX16
to
P73/KR3/EX19,
P74/KR4/EX20/INTP8
to
P77/KR7/EX23/INTP11
WR
PU
RD
WR
PORT
WR
PM
PU70 to PU77
PM70 to PM77
EV
DD0
, EV
DD1
P-ch
PU7
PM7
P7
Alternate
function
Output latch
(P70 to P77)
Alternate
function
Internal bus
Selector
P7: Port register 7
PU7: Pull-up resistor option register 7
PM7: Port mode register 7
RD: Read signal
WR××: Write signal
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4.2.9 Port 8
Port 8 is an 8-bit I/O port with an output latch. Port 8 can be set to the input mode or output mode in 1-bit units
using port mode register 8 (PM8). When the P80 to P87 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 8 (PU8).
This port can also be used for external expansion I/O (multiplexed address/data bus, data bus). When the external
expansion I/O function is used, it controls the I/O ignoring the settings on port mode register 8 (PM8), port register 8
(P8), and pull-up resistor option register 8 (PU8).
Reset signal generation sets port 8 to input mode.
Figures 4-29 shows a block diagram of port 8.
Figure 4-29. Block Diagram of P80 to P87
P80/EX0 to
P87/EX7
WR
PU
RD
WR
PORT
WR
PM
PU80 to PU87
PM80 to PM87
EV
DD0
, EV
DD1
P-ch
PM8
PU8
P8
EXEN
Alternate
function
Output latch
(P80 to P87)
Alternate
function
Internal bus
Selector
Selector
P8: Port register 8
PU8: Pull-up resistor option register 8
PM8: Port mode register 8
RD: Read signal
WR××: Write signal
EXEN: Bit 7 of memory extension mode control register (MEM)
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4.2.10 Port 11
Port 11 is a 2-bit I/O port with an output latch. Port 11 can be set to the input mode or output mode in 1-bit units
using port mode register 11 (PM11).
This port can also be used for D/A converter analog output.
Reset signal generation sets port 11 to input mode.
Figure 4-30 shows a block diagram of port 11.
Caution See 2.2.16 AVREF1 for the voltage to be applied to the AVREF1 pin when using P110 and P111 as
digital I/O.
Figure 4-30. Block Diagram of P110 and P111
D/A converter output
D/A converter operation enable signal (DACEn)
D/A converter operation enable signal (DACEn)
Output latch
(P110, P111)
Internal bus
P110/ANO0,
P111/ANO1
RD
PM11
WR
PORT
WR
PM
PM110, PM111
P11
Selector
Selector
P11: Port register 11
PM11: Port mode register 11
RD: Read signal
WR××: Write signal
DACEn: Bits 4 and 5 of D/A converter mode register (DAM) (n = 0, 1)
<R>
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4.2.11 Port 12
P120 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units
using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified
by pull-up resistor option register 12 (PU12).
P121 to P124 are 4-bit input ports.
This port can also be used for external interrupt request input, potential input for external low-voltage detection,
connecting resonator for main system clock, connecting resonator for subsystem clock, and external clock input for
main system clock.
Reset signal generation sets port 12 to input mode.
Figures 4-31 to 4-33 show block diagrams of port 12.
Caution The function setting on P121 to P124 is available only once after the reset release. The port once
set for connection to an oscillator cannot be used as an input port unless the reset is performed.
Figure 4-31. Block Diagram of P120
P120/INTP0/EXLVI
WR
PU
RD
WR
PORT
WR
PM
PU120
PM120
EV
DD0
, EV
DD1
P-ch
PU12
PM12
P12
Alternate
function
Output latch
(P120)
Internal bus
Selector
P12: Port register 12
PU12: Pull-up resistor option register 12
PM12: Port mode register 12
RD: Read signal
WR××: Write signal
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Figure 4-32. Block Diagram of P121 and P122
P122/X2/EXCLK
RD
EXCLK, OSCSEL
CMC
OSCSEL
CMC
P121/X1
RD
Internal bus
Clock generator
CMC: Clock operation mode control register
RD: Read signal
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Figure 4-33. Block Diagram of P123 and P124
P124/XT2
RD
OSCSELS
CMC
OSCSELS
CMC
P123/XT1
RD
Internal bus
Clock generator
CMC: Clock operation mode control register
RD: Read signal
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4.2.12 Port 13
P130 is a 1-bit output-only port with an output latch.
P131 is a 1-bit I/O port with an output latch. When used as an input port, use of an on-chip pull-up resistor can be
specified by pull-up resistor option register 13 (PU13).
Reset signal generation sets port 13 to input mode.
This port can also be used for timer I/O.
Figures 4-34 and 4-35 show block diagrams of port 13.
Caution To use P131/TI06/TO06 as a general-purpose port, set bit 6 (TO06) of timer output register 0 (TO0)
and bit 6 (TOE06) of timer output enable register 0 (TOE0) to “0”, which is the same as their
default status setting.
Figure 4-34. Block Diagram of P130
RD
WR
PORT
P130
P13
Output latch
(P130)
Internal bus
P13: Port register 13
RD: Read signal
WR××: Write signal
Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
P130
Set by software
Reset signal
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Figure 4-35. Block Diagram of P131
P131/TI06/TO06
WRPU
RD
WRPORT
WRPM
PU131
PM131
EVDD0, EVDD1
P-ch
PM13
PU13
P13
Alternate
function
Selector
Internal bus
Alternate
function
Output latch
(P131)
P13: Port register 13
PU13: Pull-up resistor option register 13
PM13: Port mode register 13
RD: Read signal
WR××: Write signal
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4.2.13 Port 14
Port 14 is a 6-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units
using port mode register 14 (PM14). When the P140 to P145 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14).
Input to the P142 and P143 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units
using port input mode register 14 (PIM14).
Output from the P142 to P144 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using
port output mode register 14 (POM14).
This port can also be used for timer I/O, external interrupt request input, clock/buzzer output, serial interface data
I/O, and clock I/O.
Reset signal generation sets port 14 to input mode.
Figures 4-36 to 4-38 show block diagrams of port 14.
Cautions 1. To use P142/SCK20/SCL20, P143/SI20/RxD2/SDA20, or P144/SO20/TxD2 as a general-purpose
port, note the serial array unit 1 setting. For details, refer to the following tables.
• Table 13-9 Relationship Between Register Settings and Pins (Channel 0 of Unit 1: CSI20,
UART2 Transmission, IIC20)
• Table 13-10 Relationship Between Register Settings and Pins (Channel 1 of Unit 1: UART2
Reception)
2. To use P145/TI07/TO07 as a general-purpose port, set bit 7 (TO07) of timer output register 0
(TO0) and bit 7 (TOE07) of timer output enable register 0 (TOE0) to “0”, which is the same as
their default status setting.
3. To use P140/PCLBUZ0/INTP6 or P141/PCLBUZ1/INTP7 as a general-purpose port, set bit 7 of
clock output select registers 0 and 1 (CKS0, CKS1) to “0”, which is the same as their default
status settings.
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Figure 4-36. Block Diagram of P140, P141, and P145
P140/PCLBUZ0/INTP6,
P141/PCLBUZ1/INTP7,
P145/TI07/TO07
WR
PU
RD
WR
PORT
WR
PM
PU140, PU141, PU145
PM140, PM141, PM145
EV
DD0
, EV
DD1
P-ch
PU14
PM14
P14
Alternate
function
Output latch
(P140, P141, P145)
Selector
Internal bus
Alternate
function
P14: Port register 14
PU14: Pull-up resistor option register 14
PM14: Port mode register 14
RD: Read signal
WR××: Write signal
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Figure 4-37. Block Diagram of P142 and P143
CMOS
TTL
PIM14
PIM142, PIM143
WRPIM
WRPM
PM14
POM142, POM143
POM14
WRPOM
PM142, PM143
P142/SCK20/SCL20,
P143/SI20/RxD2/SDA20
WRPU
RD
WRPORT
PU142, PU143
EVDD0, EVDD1
P-ch
PU14
P14
Alternate
function
Output latch
(P142, P143)
Selector
Internal bus
Alternate
function
P14: Port register 14
PU14: Pull-up resistor option register 14
PM14: Port mode register 14
PIM14: Port input mode register 14
POM14: Port output mode register 14
RD: Read signal
WR××: Write signal
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Figure 4-38. Block Diagram of P144
WRPM
PM14
POM144
POM14
WRPOM
PM144
P144/SO20/TxD2
WRPU
RD
WRPORT
PU144
EVDD0, EVDD1
P-ch
PU14
P14
Alternate
function
Output latch
(P144)
Selector
Internal bus
P14: Port register 14
PU14: Pull-up resistor option register 14
PM14: Port mode register 14
POM14: Port output mode register 14
RD: Read signal
WR××: Write signal
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4.2.14 Port 15
Port 15 is an 8-bit I/O port with an output latch. Port 15 can be set to the input mode or output mode in 1-bit units
using port mode register 15 (PM15).
This port can also be used for A/D converter analog input.
To use P150/ANI8 to P157/ANI15 as digital input pins, set them in the digital I/O mode by using the A/D port
configuration register (ADPC) and in the input mode by using PM15. Use these pins starting from the lower bit.
To use P150/ANI8 to P157/ANI15 as digital output pins, set them in the digital I/O mode by using ADPC and in the
output mode by using PM15.
Table 4-5. Setting Functions of P150/ANI8 to P157/ANI15 Pins
ADPC PM15 ADS P150/ANI8 to P157/ANI15 Pins
Input mode − Digital input Digital I/O selection
Output mode − Digital output
Selects ANI. Analog input (to be converted) Input mode
Does not select ANI. Analog input (not to be converted)
Selects ANI.
Analog input selection
Output mode
Does not select ANI.
Setting prohibited
All P150/ANI8 to P157/ANI15 are set in the digital input mode when the reset signal is generated.
Figure 4-39 shows a block diagram of port 15.
Caution See 2.2.15 AVREF0 for the voltage to be applied to the AVREF0 pin when using port 15 as a digital
I/O.
Figure 4-39. Block Diagram of P150 to P157
P150/ANI8 to
P157/ANI15
RD
WR
PORT
WR
PM
PM150 to PM157
PM15
A/D converter
P15
Output latch
(P150 to P157)
Selector
Internal bus
P15: Port register 15
PM15: Port mode register 15
RD: Read signal
WR××: Write signal
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4.3 Registers Controlling Port Function
Port functions are controlled by the following six types of registers.
• Port mode registers (PM0 to PM8, PM11 to PM15)
• Port registers (P0 to P8, P11 to P15)
• Pull-up resistor option registers (PU0, PU1, PU3 to PU8, PU12 to PU14)
• Port input mode registers (PIM0, PIM4, PIM14)
• Port output mode registers (POM0, POM4, POM14)
• A/D port configuration register (ADPC)
(1) Port mode registers (PM0 to PM8, PM11 to PM15)
These registers specify input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH (FEH for PM13).
When port pins are used as alternate-function pins, set the port mode register by referencing 4.5 Settings of
Port Mode Register and Output Latch When Using Alternate Function.
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Figure 4-40. Format of Port Mode Register
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00 FFF20H FFH R/W
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W
PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FFF22H FFH R/W
PM3 1 1 1 1 1 1 PM31 PM30 FFF23H FFH R/W
PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 FFF24H FFH R/W
PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 FFF25H FFH R/W
PM6 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 FFF26H FFH R/W
PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 FFF27H FFH R/W
PM8 PM87 PM86 PM85 PM84 PM83 PM82 PM81 PM80 FFF28H FFH R/W
PM11 1 1 1 1 1 1 PM111 PM110 FFF2BH FFH R/W
PM12 1 1 1 1 1 1 1 PM120 FFF2CH FFH R/W
PM13 1 1 1 1 1 1 PM131 0 FFF2DH FEH R/W
PM14 1 1 PM145 PM144 PM143 PM142 PM141 PM140 FFF2EH FFH R/W
PM15 PM157 PM156 PM155 PM154 PM153 PM152 PM151 PM150 FFF2FH FFH R/W
PMmn Pmn pin I/O mode selection
(m = 0 to 8, 11 to 15; n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
Caution Be sure to set bit 7 of PM0, bits 2 to 7 of PM3, bits 2 to 7 of PM11, bits 1 to 7 of PM12, bits 2 to 7
of PM13, and bits 6 and 7 of PM14 to “1”. And be sure to set bit 0 of PM13 to “0”.
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(2) Port registers (P0 to P8, P11 to P15)
These registers write the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is
readNote.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Note It is always 0 and never a pin level that is read out if a port is read during the input mode when P2 and P15
are set to function as an analog input for a A/D converter or P11 is set to function as an analog output for a
D/A converter.
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User’s Manual U17894EJ9V0UD 153
Figure 4-41. Format of Port Register
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
P0 0 P06 P05 P04 P03 P02 P01 P00 FFF00H 00H (output latch) R/W
P1 P17 P16 P15 P14 P13 P12 P11 P10 FFF01H 00H (output latch) R/W
P2 P27 P26 P25 P24 P23 P22 P21 P20 FFF02H 00H (output latch) R/W
P3 0 0 0 0 0 0 P31 P30 FFF03H 00H (output latch) R/W
P4 P47 P46 P45 P44 P43 P42 P41 P40 FFF04H 00H (output latch) R/W
P5 P57 P56 P55 P54 P53 P52 P51 P50 FFF05H 00H (output latch) R/W
P6 P67 P66 P65 P64 P63 P62 P61 P60 FFF06H 00H (output latch) R/W
P7 P77 P76 P75 P74 P73 P72 P71 P70 FFF07H 00H (output latch) R/W
P8 P87 P86 P85 P84 P83 P82 P81 P80 FFF08H 00H (output latch) R/W
P11 0 0 0 0 0 0 P111 P110 FFF0BH 00H (output latch) R/W
P12 0 0 0 P124 P123 P122 P121 P120 FFF0CH Undefined R/WNote
P13 0 0 0 0 0 0 P131 P130 FFF0DH 00H (output latch) R/W
P14 0 0 P145 P144 P143 P142 P141 P140 FFF0EH 00H (output latch) R/W
P15 P157 P156 P155 P154 P153 P152 P151 P150 FFF0FH 00H (output latch) R/W
m = 0 to 8, 11 to 15; n = 0 to 7 Pmn
Output data control (in output mode) Input data read (in input mode)
0 Output 0 Input low level
1 Output 1 Input high level
Note P121 to P124 are read-only.
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(3) Pull-up resistor option registers (PU0, PU1, PU3 to PU8, PU12 to PU14)
These registers specify whether the on-chip pull-up resistors of P00 to P06, P10 to P17, P30, P31, P40 to P47,
P50 to P57, P64 to P67, P70 to P77, P80 to P87, P120, P131, or P140 to P145 are to be used or not. On-chip
pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-
chip pull-up resistor has been specified in PU0, PU1, PU3 to PU8, and PU12 to PU14. On-chip pull-up resistors
cannot be connected to bits set to output mode and bits used as alternate-function output pins, regardless of the
settings of PU0, PU1, PU3 to PU8, and PU12 to PU14.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 4-42. Format of Pull-up Resistor Option Register
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PU0 0 PU06 PU05 PU04 PU03 PU02 PU01 PU00 F0030H 00H R/W
PU1 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 F0031H 00H R/W
PU3 0 0 0 0 0 0 PU31 PU30 F0033H 00H R/W
PU4 PU47 PU46 PU45 PU44 PU43 PU42 PU41 PU40 F0034H 00H R/W
PU5Note PU57 PU56 PU55 PU54 PU53 PU52 PU51 PU50 F0035H 00H R/W
PU6 PU67 PU66 PU65 PU64 0 0 0 0 F0036H 00H R/W
PU7 PU77 PU76 PU75 PU74 PU73 PU72 PU71 PU70 F0037H 00H R/W
PU8 Note PU87 PU86 PU85 PU84 PU83 PU82 PU81 PU80 F0038H 00H R/W
PU12 0 0 0 0 0 0 0 PU120 F003CH 00H R/W
PU13 0 0 0 0 0 0 PU131 0 F003DH 00H R/W
PU14 0 0 PU145 PU144 PU143 PU142 PU141 PU140 F003EH 00H R/W
PUmn Pmn pin on-chip pull-up resistor selection
(m = 0, 1, 3 to 8, 12 to 14; n = 0 to 7)
0 On-chip pull-up resistor not connected
1 On-chip pull-up resistor connected
Note When the external expansion function is used, on-chip pull-up resistors cannot be connected, regardless
of the settings of the PU5 and PU8 registers.
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(4) Port input mode registers (PIM0, PIM4, PIM14)
These registers set the input buffer of P03, P04, P43, P44, P142, or P143 in 1-bit units.
TTL input buffer can be selected during serial communication with an external device of the different potential.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 4-43. Format of Port Input Mode Register
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PIM0 0 0 0 PIM04 PIM03 0 0 0 F0040H 00H R/W
PIM4 0 0 0 PIM44 PIM43 0 0 0 F0044H 00H R/W
PIM14 0 0 0 0 PIM143 PIM142 0 0 F004EH 00H R/W
PIMmn Pmn pin input buffer selection
(m = 0, 4, 14; n = 2 to 4)
0 Normal input buffer
1 TTL input buffer
(5) Port output mode registers (POM0, POM4, POM14)
These registers set the output mode of P02 to P04, P43, P45, or P142 to P144 in 1-bit units.
N-ch open drain output (VDD tolerance) mode can be selected during serial communication with an external
device of the different potential, and for the SDA10 and SDA20 pins during simplified I2C communication with an
external device of the same potential.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 4-44. Format of Port Input Mode Register
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
POM0 0 0 0 POM04 POM03 POM02 0 0 F0050H 00H R/W
POM4 0 0 POM45 0 POM43 0 0 0 F0054H 00H R/W
POM14 0 0 0 POM144 POM143 POM142 0 0 F005EH 00H R/W
POMmn Pmn pin output mode selection
(m = 0, 4, 14; n = 2 to 5)
0 Normal output mode
1 N-ch open-drain output (VDD tolerance) mode
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(6) A/D port configuration register (ADPC)
This register switches the P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 pins to digital I/O of port or
analog input of A/D converter.
ADPC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 10H.
Figure 4-45. Format of A/D Port Configuration Register (ADPC)
Address: F0017H After reset: 10H R/W
Symbol 7 6 5 4 3 2 1 0
ADPC 0 0 0 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
Analog input (A)/digital I/O (D) switching
Port 15 Port 2
ADP
C4
ADP
C3
ADP
C2
ADP
C1
ADP
C0
ANI15
/
P157
ANI14
/
P156
ANI13
/
P155
ANI12
/
P154
ANI11
/
P153
ANI10
/
P152
ANI9/
P151
ANI8/
P150
ANI7/
P27
ANI6/
P26
ANI5/
P25
ANI4/
P24
ANI3/
P23
ANI2/
P22
ANI1/
P21
ANI0/
P20
0 0 0 0 0 A A A A A A A A A A A A A A A A
0 0 0 0 1 A A A A A A A A A A A A A A A D
0 0 0 1 0 A A A A A A A A A A A A A A D D
0 0 0 1 1 A A A A A A A A A A A A A D D D
0 0 1 0 0 A A A A A A A A A A A A D D D D
0 0 1 0 1 A A A A A A A A A A A D D D D D
0 0 1 1 0 A A A A A A A A A A D D D D D D
0 0 1 1 1 A A A A A A A A A D D D D D D D
0 1 0 0 0 A A A A A A A A D D D D D D D D
0 1 0 0 1 A A A A A A A D D D D D D D D D
0 1 0 1 0 A A A A A A D D D D D D D D D D
0 1 0 1 1 A A A A A D D D D D D D D D D D
0 1 1 0 0 A A A A D D D D D D D D D D D D
0 1 1 0 1 A A A D D D D D D D D D D D D D
0 1 1 1 0 A A D D D D D D D D D D D D D D
0 1 1 1 1 A D D D D D D D D D D D D D D D
1 0 0 0 0 D D D D D D D D D D D D D D D D
Other than above Setting prohibited
Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode registers 2
and 15 (PM2, PM15).
2. Do not set the pin set by ADPC as digital I/O by analog input channel specification register
(ADS).
3. P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 are set as analog inputs in the order of
P157/ANI15, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port configuration register
(ADPC). When using P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 as analog inputs,
start designing from P157/ANI15.
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4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
4.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does
not change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
4.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
4.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output
latch contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode
The pin level is read and an operation is performed on its contents. The result of the operation is written to the
output latch, but since the output buffer is off, the pin status does not change.
The data of the output latch is cleared when a reset signal is generated.
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4.4.4 Connecting to external device with different potential (2.5V, 3 V)
When parts of ports 0, 4, and 14 operate with VDD = 4.0 V to 5.5 V, I/O connections with an external device that
operates on 2.5 V, 3 V power supply voltage are possible.
Regarding inputs, CMOS/TTL switching is possible on a bit-by-bit basis by port input mode registers (PIM0, PIM4,
PIM14).
Moreover, regarding outputs, different potentials can be supported by switching the output buffer to the N-ch open
drain (VDD withstand voltage) by the port output mode registers (POM0, POM4, POM14).
(1) Setting procedure when using I/O pins of UART1, UART2, CSI01, and CSI20 functions
(a) Use as 3 V input port
<1> After reset release, the port mode is the input mode (Hi-Z).
<2> If pull-up is needed, externally pull up the pin to be used (on-chip pull-up resistor cannot be used).
In case of UART1: P03
In case of UART2: P143
In case of CSI01: P43, P44
In case of CSI10: P03, P04
In case of CSI20: P142, P143
<3> Set the corresponding bit of the PIMn register to 1 to switch to the TTL input buffer.
<4> VIH/VIL operates on 2.5V, 3 V operating voltage.
(b) Use as 2.5 V, 3 V output port
<1> After reset release, the port mode changes to the input mode (Hi-Z).
<2> Pull up externally the pin to be used (on-chip pull-up resistor cannot be used).
In case of UART1: P02
In case of UART2: P144
In case of CSI01: P43, P45
In case of CSI10: P02, P04
In case of CSI20: P142, P144
<3> Set the output latch of the corresponding port to 1.
<4> Set the corresponding bit of the POMn register to 1 to set the N-ch open drain output (VDD withstand
voltage) mode.
<5> Set the output mode by manipulating the PMn register.
At this time, the output data is high level, so the pin is in the Hi-Z state.
<6> Operation is done only in the low level according to the operating status of the serial array unit.
Remark n = 0, 4, 14
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(2) Setting procedure when using I/O pins of simplified IIC10 and IIC20 functions
<1> After reset release, the port mode is the input mode (Hi-Z).
<2> Externally pull up the pin to be used (on-chip pull-up resistor cannot be used).
In case of simplified IIC10: P03, P04
In case of simplified IIC20: P142, P143
<3> Set the output latch of the corresponding port to 1.
<4> Set the corresponding bit of the POMn register to 1 to set the N-ch open drain output (VDD withstand
voltage) mode.
<5> Set the corresponding bit of the PMn register to the output mode (data I/O is possible in the output
mode).
At this time, the output data is high level, so the pin is in the Hi-Z state.
<6> Enable the operation of the serial array unit and set the mode to the simplified IIC mode.
Remark n = 0, 14
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4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function
To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 4-6.
Table 4-6. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/3)
Alternate Function Pin Name
Function Name I/O
PM×× P××
P00 TI00 Input 1 ×
P01 TO00 Output 0 0
SO10 Output 0 1 P02
TxD1 Output 0 1
SI10 Input 1
×
RxD1 Input 1
×
P03
SDA10 I/O 0 1
Input 1
×
SCK10
Output 0 1
P04
SCL10 I/O 0 1
P05 CLKOUT Output 0 0
P06 WAIT Input 1 ×
Input 1
×
SCK00
Output 0 1
P10
EX24 Output 0 0
SI00 Input 1
×
RxD0 Input 1
×
P11
EX25 Output 0 0
SO00 Output 0 1
TxD0 Output 0 1
P12
EX26 Output 0 0
TxD3 Output 0 1 P13
EX27 Output 0 0
RxD3 Input 1
×
P14
EX28 Output 0 0
RTCDIV Output 0 0
RTCCL Output 0 0
P15
EX29 Output 0 0
TI01 Input 1
×
TO01 Output 0 0
INTP5 Input 1
×
P16
EX30 Output 0 0
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
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Table 4-6. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/3)
Alternate Function Pin Name
Function Name I/O
PM×× P××
TI02 Input 1
×
TO02 Output 0 0
P17
EX31 Output 0 0
P20 to P27Note 1 ANI0 to ANI7Note 1 Input 1
×
RTC1HZ Output 0 0 P30
INTP3 Input 1
×
TI03 Input 1
×
TO03 Output 0 0
P31
INTP4 Input 1
×
P40 TOOL0 I/O × ×
P41 TOOL1 Output × ×
TI04 Input 1
×
P42
TO04 Output 0 0
Input 1
×
P43 SCK01
Output 0 1
P44 SI01 Input 1 ×
P45 SO01 Output 0 1
TI05 Input 1
×
TO05 Output 0 0
P46
INTP1 Input 1
×
P47 INTP2 Input 1 ×
P50 to P57 EX8 to EX15Note 2 I/O ×Note 4
P60 SCL0 I/O 0 0
P61 SDA0 I/O 0 0
P64 RD Output 0 0
P65 WR0 Output 0 0
P66 WR1 Output 0 0
P67 ASTB Output 0 0
P70 to P73 KR0 to KR3 Input 1 ×
EX16 to EX19 Output 0 0
INTP8 to INTP11 Input 1 ×
P74 to P77
KR4 to KR7 Input 1 ×
EX20 to EX23 Output 0 0
P80 to P87 EX0 to EX7Note 3 I/O ×Note 4
P110, P111 ANO0, ANO1Note 5 Output 1
×
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
(Notes 1, 2, 3, and 4 are listed on the next page.)
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Table 4-6. Settings of Port Mode Register and Output Latch When Using Alternate Function (3/3)
Alternate Function Pin Name
Function Name I/O
PM×× P××
INTP0 Input 1
×
P120
EXLVI Input 1
×
TI06 Input 1
×
P131
TO06 Output 0 0
PCLBUZ0 Output 0 0 P140
INTP6 Input 1
×
PCLBUZ1 Output 0 0 P141
INTP7 Input 1
×
Input 1
×
SCK20
Output 0 1
P142
SCL20 I/O 0 1
SI20 Input 1
×
RxD2 Input 1
×
P143
SDA20 I/O 0 1
SO20 Output 0 1 P144
TxD2 Output 0 1
TI07 Input 1
×
P145
TO07 Output 0 0
P150 to P157Note 1 ANI8 to ANI15Note 1 Input 1
×
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
Notes 1. The functions of the ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157 pins can be selected by
using the A/D port configuration register (ADPC), the analog input channel specification register (ADS),
PM2, and PM15.
Table 4-7. Setting Functions of ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157 Pins
ADPC PM2, PM15 ADS ANI0/P20 to ANI7/P27,
ANI8/P150 to ANI15/P157 Pins
Input mode − Digital input Digital I/O selection
Output mode − Digital output
Selects ANI. Analog input (to be converted) Input mode
Does not select ANI. Analog input (not to be converted)
Selects ANI.
Analog input selection
Output mode
Does not select ANI.
Setting prohibited
2. The functions of EX8 to EX15 are selected depending on the setting of the memory extension mode
control register (MEM). For details, see CHAPTER 5 EXTERNAL BUS INTERFACE.
3. When the external bus interface is enabled to operate (EXEN = 1), the functions of EX0 to EX7 are
automatically selected.
4. When using an alternate function of these pins, select the function by using the memory extension
mode control register (MEM).
5. When the D/A converter operation is enabled (DACEn = 1), the function of ANOn is automatically
selected. However, set port mode register 11 in the input mode (PM11n = 1).
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4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn)
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the
output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
<Example> When P10 is an output port, P11 to P17 are input ports (all pin statuses are high level), and the port
latch value of port 1 is 00H, if the output of output port P10 is changed from low level to high level
via a 1-bit manipulation instruction, the output latch value of port 1 is FFH.
Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the
output latch and pin status, respectively.
A 1-bit manipulation instruction is executed in the following order in the 78K0R/KG3.
<1> The Pn register is read in 8-bit units.
<2> The targeted one bit is manipulated.
<3> The Pn register is written in 8-bit units.
In step <1>, the output latch value (0) of P10, which is an output port, is read, while the pin statuses
of P11 to P17, which are input ports, are read. If the pin statuses of P11 to P17 are high level at
this time, the read value is FEH.
The value is changed to FFH by the manipulation in <2>.
FFH is written to the output latch by the manipulation in <3>.
Figure 4-46. Bit Manipulation Instruction (P10)
Low-level output
1-bit manipulation
instruction
(set1 P1.0)
is executed for P10
bit.
Pin status: High level
P10
P11 to P17
Port 1 output latch
00000000
High-level output
Pin status: High level
P10
P11 to P17
Port 1 output latch
11111111
1-bit manipulation instruction for P10 bit
<1> Port register 1 (P1) is read in 8-bit units.
• In the case of P10, an output port, the value of the port output latch (0) is read.
• In the case of P11 to P17, input ports, the pin status (1) is read.
<2> Set the P10 bit to 1.
<3> Write the results of <2> to the output latch of port register 1 (P1)
in 8-bit units.
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CHAPTER 5 EXTERNAL BUS INTERFACE
5.1 Functions of External Bus Interface
The external bus interface function is used to connect an external device to an area other than the internal ROM,
RAM, and SFR areas. An external device is connected by using ports 0, 1, and 5 to 8. Ports 0, 1, and 5 to 8 control
signals such as address/data, read/write strobe, wait, and address strobe.
The external bus interface has the following features.
• The number of address bits can be selected from 8, 12, 16, and 20.
• Data bus supporting 8 bits and 16 bits
• Multiplexed bus and separate bus are supported.
• Separate bus mode and 16-bit bus mode are selected when an instruction is fetched from external memory.
The following table shows the pin functions in an external memory extension mode.
Pin Function When External Device Is Connected
Name Function
Alternate-Function Pin
EX0 to EX7 External extension I/O (multiplexed address/data bus, data
bus)
P80 to P87
EX8 to EX15 External extension I/O (multiplexed address/data bus,
address bus, data bus)
P50 to P57
EX16 to EX23 External extension output (address bus) P70/KR0 to P77/KR7/INTP11
EX24 to EX31 External extension output (address bus) P10/SCK00 to P17/TI02/TO02
RD Read strobe signal P64
WR0 Write strobe signal (8-bit bus mode, 16-bit bus mode
(lower byte))
P65
WR1 Write strobe signal (16-bit bus mode (higher byte)) P66
CLKOUT Internal system clock output P05
WAIT Wait signal P06
ASTB Address strobe signal P67
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The function of the external bus interface pins differs depending on the set mode.
Pin
External Extension Mode
EX31 to
EX28
EX27 to
EX24
EX23 to
EX20
EX19 to
EX16
EX15 to
EX12
EX11 to
EX8
EX7 to EX0
256-byte extension mode − − − − − − AD7 to AD0
4 KB extension mode − − − − − A11 to A8 AD7 to AD0
64 KB extension mode − − − − A15 to A12 A11 to A8 AD7 to AD0
8-bit bus mode
Full address mode − − − A19 to A16 A15 to A12 A11 to A8 AD7 to AD0
256-byte extension mode − − − − D15 to D12 D11 to D8 AD7 to AD0
4 KB extension mode − − − − D15 to D12 AD11 to
AD8
AD7 to AD0
64 KB extension mode − − − − AD15 to
AD12
AD11 to
AD8
AD7 to AD0
Multiplexed bus mode
16-bit bus mode
Full address mode − − − A19 to A16 AD15 to
AD12
AD11 to
AD8
AD7 to AD0
256-byte extension mode − − − − A7 to A4 A3 to A0 D7 to D0
4 KB extension mode − − − A11 to A8 A7 to A4 A3 to A0 D7 to D0
64 KB extension mode − − A15 to A12 A11 to A8 A7 to A4 A3 to A0 D7 to D0
8-bit bus mode
Full address mode − A19 to A16 A15 to A12 A11 to A8 A7 to A4 A3 to A0 D7 to D0
256-byte extension mode − − A7 to A4 A3 to A0 D15 to D12 D11 to D8 D7 to D0
4 KB extension mode − A11 to A8 A7 to A4 A3 to A0 D15 to D12 D11 to D8 D7 to D0
64 KB extension mode A15 to A12 A11 to A8 A7 to A4 A3 to A0 D15 to D12 D11 to D8 D7 to D0
Separate bus mode
16-bit bus mode
Full address mode Setting prohibited
Remark EXxx: Pin name
Axx: Address bus
Dxx: Data bus
ADxx: Multiplexed address/data bus
−: External bus interface is not used. These pins can be used as port pins.
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The memory maps when using the external bus interface function are as follows.
Figure 5-1. Memory Map When Using External Bus Interface Function (1/4)
(a) Memory map of
μ
PD78F1162, 78F1162A (b) Memory map of
μ
PD78F1163, 78F1163A
FFFFFH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FFFFFH
FFF00H
FFEFFH
FE700H
FE6FFH
F1000H
F0FFFH
F0800H
F07FFH
F0000H
EFFFFH
30000H
2FFFFH
21000H
20FFFH
20100H
200FFH
20000H
1FFFFH
18000H
17FFFH
00000H
FFEE0H
FFEDFH
EE000H
EDFFFH
EE000H
EDFFFH
FEF00H
FEEFFH
F1000H
F0FFFH
F0800H
F07FFH
F0000H
EFFFFH
20000H
1FFFFH
11000H
10FFFH
10100H
100FFH
10000H
0FFFFH
00000H
Special-function register (SFR)
256 bytes
Special-function register (SFR)
256 bytes
General-purpose register
32 bytes
General-purpose register
32 bytes
RAM
4 KB
RAM
6 KB
Mirror
53.75 KB
Use prohibited
Use prohibited
Special-function register (2nd SFR)
2 KB
Full-address mode
(when MM1, MM0 = 11)
64 KB extension mode
(when MM1, MM0 = 10)
4 KB extension mode
(when MM1, MM0 = 01)
Flash memory
96 KB
256 KB extension mode
(when MM1, MM0 = 00)
Use-prohibited area
Mirror
55.75 KB
Special-function register (2nd SFR)
2 KB
Full-address mode
(when MM1, MM0 = 11)
64 KB extension mode
(when MM1, MM0 = 10)
4 KB extension mode
(when MM1, MM0 = 01)
256-byte extension mode
(when MM1, MM0 = 00)
Flash memory
64 KB
Use prohibited
Use prohibited
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Figure 5-1. Memory Map When Using External Bus Interface Function (2/4)
(c) Memory map of
μ
PD78F1164, 78F1164A (d) Memory map of
μ
PD78F1165, 78F1165A
FFFFFH FFFFFH
FFF00H
FFEFFH
F1000H
F0FFFH
F0800H
F07FFH
F0000H
EFFFFH
30000H
2FFFFH
21000H
20FFFH
20100H
00000H
200FFH
20000H
1FFFFH
EE000H
FFEE0H
FFEDFH
FFF00H
FFEFFH
F1000H
F0FFFH
F0800H
F07FFH
40000H
3FFFFH
31000H
30FFFH
30100H
300FFH
30000H
2FFFFH
00000H
F0000H
EFFFFH
EE000H
FD700H
FD6FFH
FFEE0H
FFEDFH
EDFFFH
EDFFFH
FDEFFH
FDF00H
Special-function register (SFR)
256 bytes
Special-function register (SFR)
256 bytes
General-purpose register
32 bytes
General-purpose register
32 bytes
RAM
8 KB
RAM
10 KB
Mirror
49.75 KB
Use prohibited
Use prohibited
Special-function register (2nd SFR)
2 KB
Full-address mode
(when MM1, MM0 = 11)
64 KB extension mode
(when MM1, MM0 = 10)
4 KB extension mode
(when MM1, MM0 = 01)
Flash memory
192 KB
256 KB extension mode
(when MM1, MM0 = 00)
Mirror
51.75 KB
Special-function register (2nd SFR)
2 KB
Full-address mode
(when MM1, MM0 = 11)
64 KB extension mode
(when MM1, MM0 = 10)
4 KB extension mode
(when MM1, MM0 = 01)
256-byte extension mode
(when MM1, MM0 = 00)
Flash memory
128 KB
Use prohibited
Use prohibited
CHAPTER 5 EXTERNAL BUS INTERFACE
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Figure 5-1. Memory Map When Using External Bus Interface Function (3/4)
(e) Memory map of
μ
PD78F1166, 78F1166A (f) Memory map of
μ
PD78F1167, 78F1167A
FFFFFH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FCF00H
FCEFFH
F0800H
F07FFH
F0000H
EFFFFH
EE000H
EDFFFH
50000H
4FFFFH
41000H
40FFFH
40100H
400FFH
40000H
3FFFFH
00000H
F1000H
F0FFFH
Special-function register (SFR)
256 bytes
General-purpose register
32 bytes
RAM
Note
12 KB
Mirror
47.75 KB
Use prohibited
Use prohibited
Special-function register (2nd SFR)
2 KB
Full-address mode
(when MM1, MM0 = 11)
64 KB extension mode
(when MM1, MM0 = 10)
4 KB extension mode
(when MM1, MM0 = 01)
256-byte extension mode
(when MM1, MM0 = 00)
Flash memory
256 KB
FFFFFH
FFF00H
FFEFFH
FFEE0H
FFEDFH
F9F00H
F9EFFH
F0800H
F07FFH
F0000H
EFFFFH
EE000H
EDFFFH
70000H
6FFFFH
61000H
60FFFH
60100H
600FFH
60000H
5FFFFH
00000H
F1000H
F0FFFH
Special-function register (SFR)
256 bytes
General-purpose register
32 bytes
RAM
24 KB
Mirror
35.75 KB
Use prohibited
Use prohibited
Special-function register (2nd SFR)
2 KB
Full-address mode
(when MM1, MM0 = 11)
64 KB extension mode
(when MM1, MM0 = 10)
4 KB extension mode
(when MM1, MM0 = 01)
256-byte extension mode
(when MM1, MM0 = 00)
Flash memory
384 KB
Note Use of the area FCF00H to FD6FFH is prohibited when using the self-programming function, since this
area is used for self-programming library.
CHAPTER 5 EXTERNAL BUS INTERFACE
User’s Manual U17894EJ9V0UD 169
Figure 5-1. Memory Map When Using External Bus Interface Function (4/4)
(g) Memory map of
μ
PD78F1168, 78F1168A
FFFFFH
FFF00H
FFEFFH
FFEE0H
FFEDFH
F8700H
F86FFH
F0800H
F07FFH
F0000H
EFFFFH
EE000H
EDFFFH
90000H
8FFFFH
81000H
80FFFH
80100H
800FFH
80000H
7FFFFH
00000H
F1000H
F0FFFH
Special-function register (SFR)
256 bytes
General-purpose register
32 bytes
RAM
Note
30 KB
Mirror
29.75 KB
Use prohibited
Use prohibited
Special-function register (2nd SFR)
2 KB
Full-address mode
(when MM1, MM0 = 11)
64 KB extension mode
(when MM1, MM0 = 10)
4 KB extension mode
(when MM1, MM0 = 01)
256-byte extension mode
(when MM1, MM0 = 00)
Flash memory
512 KB
Note Use of the area F8700H to F8EFFH is prohibited when using the self-programming function, since this area
is used for self-programming library.
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5.2 Registers Controlling External Bus Interface Functions
The external bus interface function is controlled by the following registers.
• Peripheral enable register 1 (PER1)
• Memory extension mode control register (MEM)
• Port mode registers 0, 1, 5, 6, 7, 8 (PM0, PM1, PM5, PM6, PM7, PM8)
• Port registers 0, 1, 5, 6, 7, 8 (P0, P1, P5, P6, P7, P8)
(1) Peripheral enable register 1 (PER1)
PER1 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro
that is not used is stopped in order to reduce the power consumption and noise.
When the external bus interface is used, be sure to set bit 0 (EXBEN) of this register to 1.
PER1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 5-2. Format of Peripheral Enable Register 1 (PER1)
Address: F00F1H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 <0>
PER1 0 0 0 0 0 0 0 EXBEN
EXBEN Control of external bus interface input clock
0
Stops supply of input clock.
• SFR used by external bus interface cannot be written.
• External bus interface is in the reset status.
1
Supplies input clock.
• SFR used by external bus interface can be read/written.
Caution When setting the external bus interface, be sure to set EXBEN to 1 first. If EXBEN = 0, writing to
a control register of the external bus interface is ignored, and, even if the register is read, only
the default value is read (except for port mode registers 0, 1, 5, 6, 7, 8 (PM0, PM1, PM5, PM6,
PM7, PM8) and port registers 0, 1, 5, 6, 7, 8 (P0, P1, P5, P6, P7, P8)).
CHAPTER 5 EXTERNAL BUS INTERFACE
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(2) Memory extension mode control register (MEM)
MEM is a register that sets an external extension area.
MEM can be set by a 1-bit or 8-bit manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 5-3. Format of Memory Extension Mode Control Register (MEM)
Address: FFFFFH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
MEM EXEN EXWEN EW1 EW0 MM3 MM2 MM1 MM0
EXEN External bus interface enable flag
0 Single-chip mode (Port function is valid.)
1 External bus interface is used.
EXWEN External wait pin enable signal
0 External wait pin is not used and can be used as a port.
1 External wait pin is used.
EW1 EW0 CLKOUT pin output clock selection
0 0 fCLK
0 1 fCLK/2
1 0 fCLK/3
1 1 fCLK/4
MM3 Bus mode switching of external bus interface
0
Multiplexed bus mode
(Can be selected only for accessing memory and cannot be selected for fetching.)
1 Separate bus mode
MM2 Bus width selection of external bus interface
0
8-bit bus modeNote
(Can be selected only for accessing memory and cannot be selected for fetching.)
1 16-bit bus mode
MM1 MM0 Mode selection
0 0 256-byte extension mode. 8 address bus pins are used.
0 1 4 KB extension mode. 12 address bus pins are used.
1 0 64 KB extension mode. 16 address bus pins are used.
1 1 Full address mode. 20 address bus pins are used.
Note In the 8-bit bus mode, 16-bit access instructions cannot be used.
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The function of the external bus interface pins differs depending on the setting of the memory extension mode
control register (MEM).
MM3 MM2 MM1 MM0 EX31 to
EX28
EX27 to
EX24
EX23 to
EX20
EX19 to
EX16
EX15 to
EX12
EX11 to
EX8
EX7 to
EX0
0 0 0 0 − − − − − − AD7 to AD0
0 0 0 1 − − − − − A11 to A8 AD7 to AD0
0 0 1 0 − − − − A15 to A12 A11 to A8 AD7 to AD0
0 0 1 1 − − − A19 to A16 A15 to A12 A11 to A8 AD7 to AD0
0 1 0 0 − − − − D15 to D12 D11 to D8 AD7 to AD0
0 1 0 1 − − − − D15 to D12 AD11 to AD8 AD7 to AD0
0 1 1 0 − − − − AD15 to
AD12
AD11 to AD8 AD7 to AD0
0 1 1 1 − − − A19 to A16 AD15 to
AD12
AD11 to AD8 AD7 to AD0
1 0 0 0 − − − − A7 to A4 A3 to A0 D7 to D0
1 0 0 1 − − − A11 to A8 A7 to A4 A3 to A0 D7 to D0
1 0 1 0 − − A15 to A12 A11 to A8 A7 to A4 A3 to A0 D7 to D0
1 0 1 1 − A19 to A16 A15 to A12 A11 to A8 A7 to A4 A3 to A0 D7 to D0
1 1 0 0 − − A7 to A4 A3 to A0 D15 to D12 D11 to D8 D7 to D0
1 1 0 1 − A11 to A8 A7 to A4 A3 to A0 D15 to D12 D11 to D8 D7 to D0
1 1 1 0 A15 to A12 A11 to A8 A7 to A4 A3 to A0 D15 to D12 D11 to D8 D7 to D0
1 1 1 1 Setting prohibited
EXEN EXWEN MM3 MM2 CLKOUT ASTB RD WR0 WR1 WAIT
0 X X X − − − − − −
1 0 0 0 CLKOUT ASTB RD Write strobe − −
1 0 0 1 CLKOUT ASTB RD Low bytes
write strobe
High bytes
write strobe
−
1 0 1 0 CLKOUT − RD Write strobe − −
1 0 1 1 CLKOUT − RD Low bytes
write strobe
High bytes
write strobe
−
1 1 0 0 CLKOUT ASTB RD Write strobe − WAIT
1 1 0 1 CLKOUT ASTB RD Low bytes
write strobe
High bytes
write strobe
WAIT
1 1 1 0 CLKOUT − RD Write strobe − WAIT
1 1 1 1 CLKOUT − RD Low bytes
write strobe
High bytes
write strobe
WAIT
Remark EXxx: Pin name
Axx: Address bus
Dxx: Data bus
ADxx: Multiplexed address/data bus
−: External bus interface is not used. These pins can be used as port pins.
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5.3 Setting Port Mode Register and Output Latch
Set the port mode register and output latch as follows when using the external bus interface.
P17/EX31 to
P14/EX28
P13/EX27 to
P10/EX24
P77/EX23 to
P74/EX20
P73/EX19 to
P70/EX16
P57/EX15 to
P54/EX12
P53/EX11 to
P50/EX8
P87/EX7 to
P80/EX0
EXEN MM3 MM2 MM1 MM0
PM1x P1x PM1x P1x PM7x P7x PM7x P7x PM5x P5x PM5x P5x PM8x P8x
0 X X X X − − − − − − − − − − − − − −
1 0 0 0 0 − − − − − − − − − − − − X X
1 0 0 0 1 − − − − − − − − − − X X X X
1 0 0 1 0 − − − − − − − − X X X X X X
1 0 0 1 1 − − − − − − 0 0 X X X X X X
1 0 1 0 0 − − − − − − − − X X X X X X
1 0 1 0 1 − − − − − − − − X X X X X X
1 0 1 1 0 − − − − − − − − X X X X X X
1 0 1 1 1 − − − − − − 0 0 X X X X X X
1 1 0 0 0 − − − − − − − − X X X X X X
1 1 0 0 1 − − − − − − 0 0 X X X X X X
1 1 0 1 0 − − − − 0 0 0 0 X X X X X X
1 1 0 1 1 − − 0 0 0 0 0 0 X X X X X X
1 1 1 0 0 − − − − 0 0 0 0 X X X X X X
1 1 1 0 1 − − 0 0 0 0 0 0 X X X X X X
1 1 1 1 0 0 0 0 0 0 0 0 0 X X X X X X
1 1 1 1 1 Setting prohibited
P05/CLKOUT P67/ASTB P64/RD P65/WR0 P66/WR1 P06/WAIT EXEN EXWEN MM3
PM05 P05 PM67 P67 PM64 P64 PM65 P65 PM66 P66 PM06 P06
0 X X
− − − − − − − − − − − −
1 0 0 0 0 0 0 0 0 0 0 0 0 − −
1 0 1 0 0
− − 0 0 0 0 0 0 − −
1 1 0 0 0 0 0 0 0 0 0 0 0 1 X
1 1 1 0 0
− − 0 0 0 0 0 0 1 X
Remark X: Does not have to be set. These pins are used as external bus interface pins.
−: External bus interface is not used. These pins can be used as port pins.
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5.4 Number of Instruction Wait Clocks for Data Access
Wait clocks are added to the number of clocks of an instruction when the external bus interface is accessed.
The actual number of operating clocks is therefore the sum of the number of operating clocks of each instruction
and the number of wait states.
CLKOUT Pin Selection Clock Number of Wait States
(Read/Write)
fCLK 3 clocks
fCLK/2 5 or 6 clocks
fCLK/3 7 to 9 clocks
fCLK/4 9 to 12 clocks
Remark 1 clock: 1/fCLK (fCLK: CPU clock)
5.5 Number of Instruction Execution Clocks and Instruction Wait Clocks for Fetch Access
The internal flash captures an opcode every 32 bits. However, an opcode is captured from the external bus
interface every 16 bits. Consequently, it takes time about two times longer than the internal flash to capture an
instruction. Furthermore, a wait is inserted when accessing an external memory. Consequently, the minimum and
maximum numbers of execution clocks of each instruction when fetching instructions from the external memory are as
follows, for the number of clocks when instructions are fetched from the internal ROM (flash memory) area.
When Fetching Instructions from External Memory
No. of Instruction Execution Clocks
When Fetching Instructions from
Internal ROM AreaNote
Minimum No. of
Execution Clocks
Maximum No. of
Execution Clocks
1 2 + 2 × Wait 5 + 3 × Wait
2 6 + 2 × Wait 7 + 6 × Wait
3 4 + 2 × Wait 8 + 8 × Wait
4 8 + 2 × Wait 10 + 10 × Wait
5 6 + 2 × Wait 12 + 9 × Wait
6 10 + 5 × Wait 14 + 11 × Wait
Note Number of clocks when the internal RAM area, SFR area, or expanded SFR area has been
accessed, or when an instruction that does not access data is executed
Furthermore, the number of waits is as follows, depending on the clock selected for the CLKOUT pin.
CLKOUT Pin Selection Clock Number of Wait States (Fetch)
fCLK 3 clocks
fCLK/2 5 or 6 clocks
fCLK/3 7 to 9 clocks
fCLK/4 9 to 12 clocks
Caution The flash memory and external memory are located in consecutive spaces, but start fetching in
the external memory space by using a branch instruction (CALL, BR) in the flash memory or
RAM memory.
Remark 1 clock: 1/fCLK (fCLK: CPU clock)
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5.6 Number of Instructed Wait Cycles According to External Wait Cycles
If an external device that has a low access speed is accessed, wait cycles can be inserted into the bus cycle. If a
low-level signalNote is input to the WAIT pin at the rising edge of the CLKOUT signal, a wait of one CLKOUT clock cycle
is inserted.
For example, if fCLK/3 is selected as the clock signal for the CLKOUT pin, and a low-level signal is input to the WAIT
pin at the rising edge of the CLKOUT signal for the second time in a row, a wait cycle of two CLKOUT clock cycles
occurs. Therefore, the number of external wait cycles in 1/fCLK units is six clock cycles (see Figure 5-4).
Figure 5-4. Example in Which External Wait Cycles Are Inserted When Separate Bus Is Read
CLKOUT
(= f
CLK
/3)
f
CLK
WAIT
Wait
External Wait = (1/CLKOUT) × 2 = (1/f
CLK
) × 6
Wait
RD
Note The WAIT setup time from CLKOUT ↑ (tSKWT1) and WAIT hold time from CLKOUT ↑ (tHKWT1) in the
electrical specifications must be satisfied(see CHAPTER 29 ELECTRICAL SPECIFICATIONS
(STANDARD PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS)).
Remarks 1. 1 clock: 1/fCLK (fCLK: CPU clock)
2. The broken line in Figure 5-4 shows the waveform of the signal output from the RD pin if no
external wait cycle occurred.
<R>
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5.7 Timing of External Bus Interface Function
The functions of the timing control signal output pins in the external memory extension mode are described below.
(1) RD pin (alternate function: P64)
This pin outputs a read strobe signal when an instruction is fetched or data is read from the external memory.
It does not output the read strobe signal (holds the high level) when the internal memory is read.
(2) WR0 pin (alternate function: P65)
This pin outputs a write strobe signal (in 8-bit bus mode or 16-bit bus mode (lower byte)) when data is written to
the external memory.
It does not output the write strobe signal (holds the high level) when data is written to the internal memory.
(3) WR1 pin (alternate function: P66)
This pin outputs a write strobe signal (in 16-bit bus mode (higher byte)) when data is written to the external
memory.
It does not output the write strobe signal (holds the high level) when data is written to the internal memory.
(4) WAIT pin (alternate function: P06)
This pin inputs an external wait signal.
A wait can be inserted to the bus cycle by inputting an external wait signal in synchronization with the CLKOUT
signal.
It can be used as an I/O port pin when the external wait signal is not used.
The external wait signal is ignored when the internal memory is accessed.
(5) ASTB pin (alternate function: P67)
This pin outputs an address strobe signal.
This pin outputs the address strobe signal in the multiplexed bus mode.
During internal memory access, the address strobe signal is not output (the low level is maintained).
(6) CLKOUT pin (alternate function: P05)
This pin outputs the internal system clock. The internal system clock is output when the external bus interface is
used (EXEN bit of the MEM register = 1).
(7) EX0 to EX7, EX8 to EX15, EX16 to EX23, and EX24 to EX31 pins (alternate function: P80 to P87, P50 to
P57, P70 to P77, and P10 to P17)
These pins output an address signal and input/output a data signal. A valid signal is output or input when an
instruction is fetched from or data is accessed to/from the external memory.
During internal memory access, the address output pin holds the address that was accessed last. The data
output pin goes into the Hi-Z state.
Figures 5-5 to 5-8 show the timing charts.
CHAPTER 5 EXTERNAL BUS INTERFACE
User’s Manual U17894EJ9V0UD 177
5.7.1 Multiplexed bus mode
Figure 5-5. Timing to Read External Memory (1/2)
(a) No wait, 8-bit bus CLKOUT = fCLK (EXWEN = 0, MM3 = 0, MM2 = 0)
RD
ASTB
AD7 to AD0
A19 to A8
A7 to A0
Hi-Z Hi-Z
D7 to D0
A19 to A8
CLKOUT
fCLK
CPU EXE (wait) EXE (wait) EXE (wait) EXE (read)
(b) With wait, 8-bit bus CLKOUT = fCLK (EXWEN = 1, MM3 = 0, MM2 = 0)
RD
ASTB
AD7 to AD0
A19 to A8
A7 to A0
Hi-Z Hi-Z Hi-Z
A19 to A8
CLKOUT
f
CLK
CPU
D7 to D0
WAIT
EXE (wait) EXE (wait) EXE (wait) EXE (wait) EXE (wait) EXE (read)
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Figure 5-5. Timing to Read External Memory (2/2)
(c) No wait, 16-bit bus CLKOUT = fCLK/2 (EXWEN = 0, MM3 = 0, MM2 = 1)
RD
ASTB
AD15 to AD0
A19 to A16
A15 to A0
Hi-Z Hi-Z
D15 to D0
A19 to A16
CLKOUT
fCLK
CPU (Ex.2)
CPU (Ex.1)
EXE (wait)
EXE (wait) EXE (wait) EXE (wait) EXE (wait) EXE (wait) EXE (wait) EXE (read)
EXE (wait) EXE (wait) EXE (wait) EXE (wait) EXE (read)
(d) With wait, 16-bit bus CLKOUT = fCLK/2 (EXWEN = 1, MM3 = 0, MM2 = 1)
RD
ASTB
AD15 to AD0
A19 to A16
A15 to A0
Hi-Z Hi-Z Hi-Z
A19 to A16
CLKOUT
f
CLK
CPU (Ex.2)
CPU (Ex.1)
EXE
(read)
EXE
(wait)
D15 to D0
WAIT
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(read)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
CHAPTER 5 EXTERNAL BUS INTERFACE
User’s Manual U17894EJ9V0UD 179
Figure 5-6. Timing to Write to External Memory (1/2)
(a) No wait, 8-bit bus CLKOUT = fCLK (EXWEN = 0, MM3 = 0, MM2 = 0)
WR0
ASTB
AD7 to AD0
A19 to A8
A7 to A0
Hi-Z Hi-Z
D7 to D0
A19 to A8
CLKOUT
fCLK
CPU
EXE (wait) EXE (wait) EXE (wait) EXE (write)
(b) With wait, 8-bit bus CLKOUT = fCLK (EXWEN = 1, MM3 = 0, MM2 = 0)
WR0
ASTB
AD7 to AD0
A19 to A8
A7 to A0
Hi-Z Hi-Z
A19 to A8
CLKOUT
f
CLK
CPU
EXE (write)
D7 to D0
WAIT
EXE (wait) EXE (wait) EXE (wait) EXE (wait) EXE (wait)
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Figure 5-6. Timing to Write to External Memory (2/2)
(c) No wait, 16-bit bus CLKOUT = fCLK/2 (EXWEN = 0, MM3 = 0, MM2 = 1)
WR0
ASTB
AD15 to AD0
A19 to A16
A15 to A0
Hi-Z Hi-Z
D15 to D0
A19 to A16
CLKOUT
fCLK
CPU (Ex.2)
EXE (write)EXE (wait)EXE (wait) EXE (wait) EXE (wait) EXE (wait) EXE (wait)
CPU (Ex.1)
EXE (write)EXE (wait)EXE (wait) EXE (wait) EXE (wait) EXE (wait)
WR1
(d) With wait, 16-bit bus CLKOUT = fCLK/2 (EXWEN = 1, MM3 = 0, MM2 = 1), lower 8-bit writing
WR0
ASTB
AD15 to AD0
A19 to A16
A15 to A0
Hi-Z Hi-Z
A19 to A16
CLKOUT
f
CLK
CPU (Ex.2)
CPU (Ex.1)
EXE
(write)
EXE
(wait)
D15 to D0
WAIT
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(write)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
WR1
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5.7.2 Separate bus mode
Figure 5-7. Timing to Read External Memory (1/2)
(a) No waits, 8-bit bus CLKOUT = fCLK (EXWEN = 0, MM3 = 1, MM2 = 0)
RD
D7 to D0
A19 to A0
D7 to D0
Hi-Z Hi-Z
A19 to A0
CLKOUT
f
CLK
CPU
EXE (wait) EXE (wait) EXE (wait) EXE (read)
(b) With wait, 8-bit bus CLKOUT = fCLK (EXWEN = 1, MM3 = 1, MM2 = 0)
RD
D7 to D0
A19 to A0 A19 to A0
CLKOUT
f
CLK
CPU
EXE (read)
D7 to D0
Hi-Z Hi-Z
WAIT
EXE (wait)EXE (wait) EXE (wait) EXE (wait) EXE (wait)
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Figure 5-7. Timing to Read External Memory (2/2)
(c) No wait, 16-bit bus CLKOUT = fCLK/2 (EXWEN = 0, MM3 = 1, MM2 = 1)
RD
D15 to D0
A15 to A0
D15 to D0
Hi-Z Hi-Z
A15 to A0
CLKOUT
f
CLK
CPU (Ex.2) EXE (read)EXE (wait)EXE (wait) EXE (wait) EXE (wait) EXE (wait) EXE (wait)
CPU (Ex.1) EXE (read)EXE (wait)EXE (wait) EXE (wait) EXE (wait) EXE (wait)
(d) With wait, 16-bit bus CLKOUT = fCLK/2 (EXWEN = 1, MM3 = 1, MM2 = 1)
RD
D15 to D0
A15 to A0 A15 to A0
CLKOUT
f
CLK
CPU (Ex.2)
CPU (Ex.1)
EXE
(read)
EXE
(wait)
D15 to D0
Hi-Z Hi-Z
WAIT
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(read)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
CHAPTER 5 EXTERNAL BUS INTERFACE
User’s Manual U17894EJ9V0UD 183
Figure 5-8. Timing to Write to External Memory (1/2)
(a) No wait, 8-bit bus CLKOUT = fCLK (EXWEN = 0, MM3 = 1, MM2 = 0)
WR0
D7 to D0
A19 to A0
D7 to D0
A19 to A0
CLKOUT
f
CLK
CPU
EXE (wait) EXE (wait) EXE (wait) EXE (write)
Hi-Z Hi-Z
(b) With wait, 8-bit bus CLKOUT = fCLK (EXWEN = 1, MM3 = 1, MM2 = 0)
WR0
D7 to D0
A19 to A0 A19 to A0
CLKOUT
f
CLK
CPU
EXE (write)
D7 to D0
WAIT
EXE (wait)EXE (wait) EXE (wait) EXE (wait) EXE (wait)
Hi-Z Hi-Z
CHAPTER 5 EXTERNAL BUS INTERFACE
User’s Manual U17894EJ9V0UD
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Figure 5-8. Timing to Write to External Memory (2/2)
(c) No wait, 16-bit bus CLKOUT = fCLK/2 (EXWEN = 0, MM3 = 1, MM2 = 1) , higher 8-bit writing
WR0
D15 to D0
A15 to A0
D15 to D0
A15 to A0
CLKOUT
fCLK
CPU (Ex.2) EXE (write)
EXE (wait)EXE (wait) EXE (wait) EXE (wait) EXE (wait) EXE (wait)
CPU (Ex.1) EXE (write)EXE (wait)EXE (wait) EXE (wait) EXE (wait) EXE (wait)
WR1
Hi-Z Hi-Z
(d) With wait, 16-bit bus CLKOUT = fCLK/2 (EXWEN = 1, MM3 = 1, MM2 = 1)
WR0
D15 to D0
A15 to A0 A15 to A0
CLKOUT
f
CLK
CPU (Ex.2)
CPU (Ex.1)
EXE
(write)
EXE
(wait)
D15 to D0
WAIT
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(write)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
EXE
(wait)
WR1
Hi-Z Hi-Z
CHAPTER 5 EXTERNAL BUS INTERFACE
User’s Manual U17894EJ9V0UD 185
5.8 Example of Connection to Memory
5.8.1 Connection of external logic (ASIC, etc.)
When connecting the external logic, select the multiplexed bus mode or separate bus mode. When connecting
buses, use CLKOUT as the reference clock. Other signals have delay on CLKOUT, however, note with caution that
the CLKOUT does not delay on-board or when designing external logic.
Figure 5-9. Example of External Logic Connection
A11 to A8
AD7 to AD0
78K0R/KG3
RD
WR0
CLKOUT
WAIT
Address bus
Write data bus
Read
Write
Clock
Wait
ASTB
4
8EN
Read data bus
5.8.2 Connection of synchronous memory
Use a separate bus mode for connecting a synchronous memory.
Figure 5-10. Example of Synchronous Memory Connection
A15 to A1
D15 to D0
Synchronous memory
78K0R/KG3
RD
WR0
CLKOUT
WR1
P××
A14 to A0 (address)
D15 to D0 (data)
OE (output enable)
WR0 (lower byte write enable)
CLKOUT (input clock)
WR1 (higher byte write enable)
CE (chip enable)
15
16
CHAPTER 5 EXTERNAL BUS INTERFACE
User’s Manual U17894EJ9V0UD
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5.8.3 Connection of asynchronous memory
Use the separate bus mode for connecting an asynchronous memory.
Figure 5-11. Example of Asynchronous Memory Connection
A15 to A1
D15 to D0
Asynchronous memory
78K0R/KG3
RD
WR0
WR1
P××
A14 to A0 (address)
D15 to D0 (data)
OE (output enable)
WR0 (lower byte write enable)
WR1 (higher byte write enable)
CE (chip enable)
15
16
User’s Manual U17894EJ9V0UD 187
CHAPTER 6 CLOCK GENERATOR
6.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three kinds of system clocks and clock oscillators are selectable.
(1) Main system clock
<1> X1 oscillator
This circuit oscillates a clock of fX = 2 to 20 MHz by connecting a resonator to X1 and X2.
Oscillation can be stopped by executing the STOP instruction or setting of MSTOP (bit 7 of the clock
operation status control register (CSC)).
<2> Internal high-speed oscillator
This circuit oscillates a clock of fIH = 8 MHz (TYP.). After a reset release, the CPU always starts
operating with this internal high-speed oscillation clock. Oscillation can be stopped by executing the
STOP instruction or setting of HIOSTOP (bit 0 of CSC).
An external main system clock (fEX = 2 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin. An
external main system clock input can be disabled by executing the STOP instruction or setting of MSTOP.
As the main system clock, a high-speed system clock (X1 clock or external main system clock) or internal high-
speed oscillation clock can be selected by setting of MCM0 (bit 4 of the system clock control register (CKC)).
(2) Subsystem clock
• XT1 clock oscillator
This circuit oscillates a clock of fSUB = 32.768 kHz by connecting a 32.768 kHz resonator to XT1 and XT2.
Oscillation can be stopped by setting XTSTOP (bit 6 of CSC).
Remark fX: X1 clock oscillation frequency
fIH: Internal high-speed oscillation clock frequency
fEX: External main system clock frequency
fSUB: Subsystem clock frequency
(3) Internal low-speed oscillation clock (clock for watchdog timer)
• Internal low-speed oscillator
This circuit oscillates a clock of fIL = 240 kHz (TYP.).
The internal low-speed oscillation clock cannot be used as the CPU clock. The only hardware that operates
with the internal low-speed oscillation clock is the watchdog timer.
Oscillation is stopped when the watchdog timer stops.
Remarks 1. fIL: Internal low-speed oscillation clock frequency
2. The watchdog timer stops in the following cases.
• When bit 4 (WDTON) of an option byte (000C0H) = 0
• If the HALT or STOP instruction is executed when bit 4 (WDTON) of an option byte (000C0H) = 1
and bit 0 (WDSTBYON) = 0
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6.2 Configuration of Clock Generator
The clock generator includes the following hardware.
Table 6-1. Configuration of Clock Generator
Item Configuration
Control registers Clock operation mode control register (CMC)
Clock operation status control register (CSC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
System clock control register (CKC)
Peripheral enable register 0, 1 (PER0, PER1)
Operation speed mode control register (OSMC)
Internal high-speed oscillator trimming register (HIOTRM)
Oscillators X1 oscillator
XT1 oscillator
Internal high-speed oscillator
Internal low-speed oscillator
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17894EJ9V0UD 189
Figure 6-1. Block Diagram of Clock Generator
f
IL
XT1/P123
XT2//P124
f
SUB
f
CLK
CSSCLS
f
MAIN
f
MAINC
OSTS1 OSTS0OSTS2
3
MOST
18
MOST
17
MOST
15
MOST
13
MOST
11
MSTOP
STOP
EXCLK
OSCSEL
AMPH
4
f
IH
X1/P121
X2/EXCLK
/P122
f
MX
OSCSELS
f
X
f
EX
f
XT
XTSTOP
CLS
HIOSTOP
MCM0
MCS MD
IV2
MD
IV1
MD
IV0
CPU
f
MAIN
/2
5
f
MAIN
/2
4
f
MAIN
/2
3
f
MAIN
/2
2
f
MAIN
/2
f
MAIN
1
MOST
10
MOST
9
MOST
8
TAU0
EN
SAU0
EN
SAU1
EN
IIC0
EN
ADC
EN
DAC
EN
RTC
EN
f
SUB
/2
EXB
EN
External bus interface
Internal bus
Internal bus
Clock operation mode
control register
(CMC)
Clock operation status
control register
(CSC)
Oscillation stabilization
time select register (OSTS)
System clock control
register (CKC)
X1 oscillation
stabilization time counter
Oscillation stabilization time counter
status register
(OSTC)
High-speed system
clock oscillator
Crystal/ceramic
oscillation
External input
clock
Subsystem clock
oscillator
Crystal
oscillation
Clock operation mode
control register
(CMC)
Internal
high-speed
oscillator
(8 MHz (typ.))
Internal
low-speed
oscillator
(240 kHz (typ.))
Clock operation status
control register
(CSC)
Main system
clock source
selection
Watchdog timer
Real-time counter, clock
output/buzzer output
Peripheral enable register 1
(PER1)
Clock output/
buzzer output
Prescaler
Selector
Selection of
CPU clock and
peripheral
hardware clock
source
Controller
Peripheral enable register 0
(PER0)
Timer array unit
Serial array unit 0
Serial array unit 1
Serial interface IIC0
A/D converter
D/A converter
Real-time counter
Standby control
Controller
<R>
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User’s Manual U17894EJ9V0UD
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Remark fX: X1 clock oscillation frequency
fIH: Internal high-speed oscillation clock frequency
fEX: External main system clock frequency
fMX: High-speed system clock frequency
fMAIN: Main system clock frequency
fMAINC: Main system select clock frequency
fXT: XT1 clock oscillation frequency
fSUB: Subsystem clock frequency
fCLK: CPU/peripheral hardware clock frequency
fIL: Internal low-speed oscillation clock frequency
6.3 Registers Controlling Clock Generator
The following eight registers are used to control the clock generator.
• Clock operation mode control register (CMC)
• Clock operation status control register (CSC)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
• System clock control register (CKC)
• Peripheral enable registers 0, 1 (PER0, PER1)
• Operation speed mode control register (OSMC)
• Internal high-speed oscillator trimming register (HIOTRM)
<R>
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17894EJ9V0UD 191
(1) Clock operation mode control register (CMC)
This register is used to set the operation mode of the X1/P121, X2/EXCLK/P122, XT1/P123, and XT2/P124 pins,
and to select a gain of the oscillator.
CMC can be written only once by an 8-bit memory manipulation instruction after reset release. This register can
be read by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 6-2. Format of Clock Operation Mode Control Register (CMC)
Address: FFFA0H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CMC EXCLK OSCSEL 0 OSCSELS 0 0 0 AMPH
EXCLK OSCSEL High-speed system clock
pin operation mode
X1/P121 pin X2/EXCLK/P122 pin
0 0 Input port mode Input port
0 1 X1 oscillation mode Crystal/ceramic resonator connection
1 0 Input port mode Input port
1 1 External clock input mode Input port External clock input
OSCSELS Subsystem clock pin operation mode XT1/P123 pin XT2/P124 pin
0 Input port mode Input port
0 XT1 oscillation mode Crystal resonator connection
AMPH Control of X1 clock oscillation frequency
0 2 MHz ≤ fX ≤ 10 MHz
1 10 MHz < fX ≤ 20 MHz
Cautions 1. CMC can be written only once after reset release, by an 8-bit memory
manipulation instruction.
2. After reset release, set CMC before X1 or XT1 oscillation is started as set by the
clock operation status control register (CSC).
3. Be sure to set AMPH to 1 if the X1 clock oscillation frequency exceeds 10 MHz.
4. It is recommended to set the default value (00H) to CMC after reset release, even
when the register is used at the default value, in order to prevent malfunctioning
during a program loop.
Remark f
X: X1 clock oscillation frequency
<R>
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User’s Manual U17894EJ9V0UD
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(2) Clock operation status control register (CSC)
This register is used to control the operations of the high-speed system clock, internal high-speed oscillation clock,
and subsystem clock (except the internal low-speed oscillation clock).
CSC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to C0H.
Figure 6-3. Format of Clock Operation Status Control Register (CSC)
Address: FFFA1H After reset: C0H R/W
Symbol <7> <6> 5 4 3 2 1 <0>
CSC MSTOP XTSTOP 0 0 0 0 0 HIOSTOP
Control of high-speed system clock operation
MSTOP
X1 oscillation mode External clock input mode Input port mode
0 X1 oscillator operating External clock from EXCLK
pin is valid
1 X1 oscillator stopped External clock from EXCLK
pin is invalid
−
Subsystem clock operation control
XTSTOP
XT1 oscillation mode Input port mode
0 XT1 oscillator operating
1 XT1 oscillator stopped
−
HIOSTOP
0 Internal high-speed oscillator operating
1 Internal high-speed oscillator stopped
Cautions 1. After reset release, set the clock operation mode control register (CMC) before
starting X1 oscillation as set by MSTOP or XT1 oscillation as set by XTSTOP.
2. To start X1 oscillation as set by MSTOP, check the oscillation stabilization time
of the X1 clock by using the oscillation stabilization time counter status register
(OSTC).
3. Do not stop the clock selected for the CPU/peripheral hardware clock (fCLK) with
the OSC register.
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17894EJ9V0UD 193
Caution 4. The setting of the flags of the register to stop clock oscillation (invalidate the
external clock input) and the condition before clock oscillation is to be stopped
are as follows.
Table 6-2. Condition Before Stopping Clock Oscillation and Flag Setting
Clock Condition Before Stopping Clock
(Invalidating External Clock Input)
Setting of CSC
Register Flags
X1 clock
External main system
clock
• CLS = 0 and MCS = 0
• CLS = 1
(CPU and peripheral hardware clocks operate with a clock
other than the high-speed system clock.)
MSTOP = 1
Subsystem clock • CLS = 0
(CPU and peripheral hardware clocks operate with a clock
other than the subsystem clock.)
XTSTOP = 1
Internal high-speed
oscillation clock
• CLS = 0 and MCS = 1
• CLS = 1
(CPU and peripheral hardware clocks operate with a clock
other than the internal high-speed oscillator clock.)
HIOSTOP = 1
(3) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case,
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or subsystem clock is being
used as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used
as the CPU clock with the X1 clock oscillating.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset signal is generated, the STOP instruction and MSTOP (bit 7 of CSC register) = 1 clear OSTC to 00H.
Remark The oscillation stabilization time counter starts counting in the following cases.
• When oscillation of the X1 clock starts (EXCLK, OSCSEL = 0, 1 → MSTOP = 0)
• When the STOP mode is released
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User’s Manual U17894EJ9V0UD
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Figure 6-4. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFFA2H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
OSTC MOST
8
MOST
9
MOST
10
MOST
11
MOST
13
MOST
15
MOST
17
MOST
18
Oscillation stabilization time status MOST
8
MOST
9
MOST
10
MOST
11
MOST
13
MOST
15
MOST
17
MOST
18 f
X = 10 MHz fX = 20 MHz
0 0 0 0 0 0 0 0 28/fX max. 25.6
μ
s max. 12.8
μ
s max.
1 0 0 0 0 0 0 0 28/fX min. 25.6
μ
s min. 12.8
μ
s min.
1 1 0 0 0 0 0 0 29/fX min. 51.2
μ
s min. 25.6
μ
s min.
1 1 1 0 0 0 0 0 210/fX min. 102.4
μ
s min. 51.2
μ
s min.
1 1 1 1 0 0 0 0 211/fX min. 204.8
μ
s min. 102.4
μ
s min.
1 1 1 1 1 0 0 0 213/fX min. 819.2
μ
s min. 409.6
μ
s min.
1 1 1 1 1 1 0 0 215/fX min. 3.27 ms min. 1.64 ms min.
1 1 1 1 1 1 1 0 217/fX min. 13.11 ms min. 6.55 ms min.
1 1 1 1 1 1 1 1 218/fX min. 26.21 ms min. 13.11 ms min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST8 and
remain 1.
2. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS.
In the following cases, set the oscillation stabilization time of OSTS to the value
greater than or equal to the count value which is to be checked by the OSTC
register.
• If the X1 clock starts oscillation while the internal high-speed oscillation
clock or subsystem clock is being used as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time
set by OSTS is set to OSTC after the STOP mode is released.)
3. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark fX: X1 clock oscillation frequency
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17894EJ9V0UD 195
(4) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation automatically waits for the time set using OSTS
after the STOP mode is released.
When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired
oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can
be checked up to the time set using OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets OSTS to 07H.
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User’s Manual U17894EJ9V0UD
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Figure 6-5. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFFA3H After reset: 07H R/W
Symbol 7 6 5 4 3 2 1 0
OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0
Oscillation stabilization time selection
OSTS2 OSTS1 OSTS0
fX = 10 MHz fX = 20 MHz
0 0 0 28/fX 25.6
μ
s Setting prohibited
0 0 1 29/fX 51.2
μ
s 25.6
μ
s
0 1 0 210/fX 102.4
μ
s 51.2
μ
s
0 1 1 211/fX 204.8
μ
s 102.4
μ
s
1 0 0 213/fX 819.2
μ
s 409.6
μ
s
1 0 1 215/fX 3.27 ms 1.64 ms
1 1 0 217/fX 13.11 ms 6.55 ms
1 1 1 218/fX 26.21 ms 13.11 ms
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the
OSTS register before executing the STOP instruction.
2. Setting the oscillation stabilization time to 20
μ
s or less is prohibited.
3. To change the setting of the OSTS register, be sure to confirm that the counting
operation of the OSTC register has been completed.
4. Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
5. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS.
In the following cases, set the oscillation stabilization time of OSTS to the value
greater than or equal to the count value which is to be checked by the OSTC
register.
• If the X1 clock starts oscillation while the internal high-speed oscillation
clock or subsystem clock is being used as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time
set by OSTS is set to OSTC after the STOP mode is released.)
6. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark f
X: X1 clock oscillation frequency
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17894EJ9V0UD 197
(5) System clock control register (CKC)
This register is used to select a CPU/peripheral hardware clock and a division ratio.
CKC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 09H.
Figure 6-6. Format of System Clock Control Register (CKC)
Address: FFFA4H After reset: 09H R/WNote 1
Symbol <7> <6> <5> <4> 3 2 1 0
CKC CLS CSS MCS MCM0 1 MDIV2 MDIV1 MDIV0
CLS Status of CPU/peripheral hardware clock (fCLK)
0 Main system clock (fMAIN)
1 Subsystem clock (fSUB)
MCS Status of Main system clock (fMAIN)
0 Internal high-speed oscillation clock (fIH)
1 High-speed system clock (fMX)
CSS MCM0 MDIV2 MDIV1 MDIV0
Selection of CPU/peripheral
hardware clock (fCLK)
0 0 0 fIH
0 0 1 fIH/2 (default)
0 1 0 fIH/22
0 1 1 fIH/23
1 0 0 fIH/24
0 0
1 0 1 fIH/25
0 0 0 fMX
0 0 1 fMX/2
0 1 0 fMX/22
0 1 1 fMX/23
1 0 0 fMX/24
0 1
1 0 1 fMX/25 Note 2
1
Note 3 ×Note 3 × × × fSUB/2
Other than above Setting prohibited
Notes 1. Bits 7 and 5 are read-only.
2. Setting is prohibited when fMX < 4 MHz.
3. Changing the value of the MCM0 bit is prohibited while CSS is set to 1.
Remarks 1. fIH: Internal high-speed oscillation clock frequency
fMX: High-speed system clock frequency
fSUB: Subsystem clock frequency
2. ×: don’t care
(Cautions 1 to 3 are listed on the next page.)
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17894EJ9V0UD
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Cautions 1. Be sure to set bit 3 to 1.
2. The clock set by CSS, MCM0, and MDIV2 to MDIV0 is supplied to the CPU and
peripheral hardware. If the CPU clock is changed, therefore, the clock supplied
to peripheral hardware (except the real-time counter, clock output/buzzer output,
and watchdog timer) is also changed at the same time. Consequently, stop each
peripheral function when changing the CPU/peripheral operating hardware clock.
3. If the peripheral hardware clock is used as the subsystem clock, the operations
of the A/D converter and IIC0 are not guaranteed. For the operating
characteristics of the peripheral hardware, refer to the chapters describing the
various peripheral hardware as well as CHAPTER 29 ELECTRICAL
SPECIFICATIONS (STANDARD PRODUCTS) and CHAPTER 30 ELECTRICAL
SPECIFICATIONS ((A) GRADE PRODUCTS).
The fastest instruction can be executed in 1 clock of the CPU clock in the 78K0R/KG3. Therefore, the
relationship between the CPU clock (fCLK) and the minimum instruction execution time is as shown in Table 6-3.
Table 6-3. Relationship Between CPU Clock and Minimum Instruction Execution Time
Minimum Instruction Execution Time: 1/fCLK
Main System Clock (CSS = 0)
High-Speed System Clock
(MCM0 = 1)
Internal High-Speed Oscillation Clock
(MCM0 = 0)
Subsystem Clock
(CSS = 1)
CPU Clock
(Value set by the
MDIV2 to MDIV0
bits)
At 10 MHz Operation At 20 MHz Operation At 8 MHz (TYP.) Operation At 32.768 kHz Operation
fMAIN 0.1
μ
s 0.05
μ
s 0.125
μ
s (TYP.) −
fMAIN/2 0.2
μ
s 0.1
μ
s 0.25
μ
s (TYP.) (default) −
fMAIN/22 0.4
μ
s 0.2
μ
s 0.5
μ
s (TYP.) −
fMAIN/23 0.8
μ
s 0.4
μ
s 1.0
μ
s (TYP.) −
fMAIN/24 1.6
μ
s 0.8
μ
s 2.0
μ
s (TYP.) −
fMAIN/25 3.2
μ
s 1.6
μ
s 4.0
μ
s (TYP.) −
fSUB/2 − − 61
μ
s
Remark fMAIN: Main system clock frequency (fIH or fMX)
fSUB: Subsystem clock frequency
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17894EJ9V0UD 199
(6) Peripheral enable registers 0, 1 (PER0, PER1)
These registers are used to enable or disable use of each peripheral hardware macro. Clock supply to the
hardware that is not used is also stopped so as to decrease the power consumption and noise.
PER0 and PER1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears theses registers to 00H.
Figure 6-7. Format of Peripheral Enable Register (1/2)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> 1 <0>
PER0 RTCEN DACEN ADCEN IIC0EN SAU1EN SAU0EN 0 TAU0EN
Address: F00F1H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 <0>
PER1 0 0 0 0 0 0 0 EXBEN
RTCEN Control of real-time counter (RTC) input clockNote
0
Stops input clock supply.
• SFR used by the real-time counter (RTC) cannot be written.
• The real-time counter (RTC) is in the reset status.
1
Supplies input clock.
• SFR used by the real-time counter (RTC) can be read and written.
DACEN Control of D/A converter input clock
0
Stops input clock supply.
• SFR used by D/A converter cannot be written.
• The D/A converter is in the reset status.
1
Supplies input clock.
• SFR used by the D/A converter can be read and written.
ADCEN Control of A/D converter input clock
0
Stops input clock supply.
• SFR used by the A/D converter cannot be written.
• The A/D converter is in the reset status.
1
Supplies input clock.
• SFR used by the A/D converter can be read and written.
IIC0EN Control of serial interface IIC0 input clock
0
Stops input clock supply.
• SFR used by the serial interface IIC0 cannot be written.
• The serial interface IIC0 is in the reset status.
1
Supplies input clock.
• SFR used by the serial interface IIC0 can be read and written.
Note The input clock that can be controlled by RTCEN is used when the register that is used by the
real-time counter (RTC) is accessed from the CPU. RTCEN cannot control supply of the
operating clock (fSUB) to RTC.
Caution Be sure to clear bit 1 of the PER0 register and bits 1 to 7 of the PER1 register to 0.
<R>
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Figure 6-7. Format of Peripheral Enable Register (2/2)
SAU1EN Control of serial array unit 1 input clock
0
Stops input clock supply.
• SFR used by the serial array unit 1 cannot be written.
• The serial array unit 1 is in the reset status.
1
Supplies input clock.
• SFR used by the serial array unit 1 can be read and written.
SAU0EN Control of serial array unit 0 input clock
0
Stops input clock supply.
• SFR used by the serial array unit 0 cannot be written.
• The serial array unit 0 is in the reset status.
1
Supplies input clock.
• SFR used by the serial array unit 0 can be read and written.
TAU0EN Control of timer array unit input clock
0
Stops input clock supply.
• SFR used by the timer array unit cannot be written.
• The timer array unit is in the reset status.
1
Supplies input clock.
• SFR used by the timer array unit can be read and written.
EXBEN Control of external bus interface input clock
0
Stops input clock supply.
• SFR used by the external bus interface cannot be written.
• The external bus interface is in the reset status.
1
Supplies input clock.
• SFR used by the external bus interface can be read and written.
Caution Be sure to clear bit 1 of the PER0 register and bits 1 to 7 of the PER1 register to 0.
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(7) Operation speed mode control register (OSMC)
This register is used to control the step-up circuit of the flash memory for high-speed operation.
If the microcontroller operates at a low speed with a system clock of 10 MHz or less, the power consumption can
be lowered by setting this register to the default value, 00H.
OSMC can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 6-8. Format of Operation Speed Mode Control Register (OSMC)
Address: F00F3H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
OSMC 0 0 0 0 0 0 0 FSEL
FSEL fCLK frequency selection
0 Operates at a frequency of 10 MHz or less (default).
1 Operates at a frequency higher than 10 MHz.
Cautions 1. OSMC can be written only once after reset release, by an 8-bit memory
manipulation instruction.
2. Write “1” to FSEL before the following two operations.
• Changing the clock prior to dividing fCLK to a clock other than fIH.
• Operating the DMA controller.
3. The CPU waits when “1” is written to the FSEL flag.
Interrupt requests issued during a wait will be suspended.
The wait time is 16.6
μ
s to 18.5
μ
s when fCLK = fIH, and 33.3
μ
s to 36.9
μ
s when fCLK
= fIH/2.
However, counting the oscillation stabilization time of fX can continue even while
the CPU is waiting.
4. To increase fCLK to 10 MHz or higher, set FSEL to “1”, then change fCLK after two
or more clocks have elapsed. Use the external bus interface two clock cycles
after setting FSEL to 1.
5. Flash memory can be used at a frequency of 10 MHz or lower if FSEL is 1.
<R>
<R>
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(8) Internal high-speed oscillator trimming register (HIOTRM)
This register is used to adjust the accuracy of the internal high-speed oscillator.
With self-measurement of the internal high-speed oscillator frequency via a subsystem clock using a crystal
resonator, a timer using high-accuracy external clock input (real-time counter or timer array unit), and so on, the
register can adjust the accuracy.
HIOTRM can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 10H.
Caution The frequency will vary if the temperature and VDD pin voltage change after accuracy
adjustment.
Moreover, if the HIOTRM register is set to any value other than the initial value (10H), the
oscillation accuracy of the internal high-speed oscillation clock may exceed 8 MHz±5%,
depending on the subsequent temperature and VDD voltage change, or HIOTRM register
setting. When the temperature and VDD voltage change, accuracy adjustment must be
executed regularly or before the frequency accuracy is required
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Figure 6-9. Format of Internal High-Speed Oscillator Trimming Register (HIOTRM)
Address: F00F2H After reset: 10H R/W
Symbol 7 6 5 4 3 2 1 0
HIOTRM 0 0 0 TTRM4 TTRM3 TTRM2 TTRM1 TTRM0
Clock correction value
(2.7 V ≤ VDD ≤ 5.5 V)
TTRM4 TTRM3 TTRM2 TTRM1 TTRM0
MIN. TYP. MAX.
0 0 0 0 0 −5.54% −4.88% −4.02%
0 0 0 0 1 −5.28% −4.62% −3.76%
0 0 0 1 0 −4.99% −4.33% −3.47%
0 0 0 1 1 −4.69% −4.03% −3.17%
0 0 1 0 0 −4.39% −3.73% −2.87%
0 0 1 0 1 −4.09% −3.43% −2.57%
0 0 1 1 0 −3.79% −3.13% −2.27%
0 0 1 1 1 −3.49% −2.83% −1.97%
0 1 0 0 0 −3.19% −2.53% −1.67%
0 1 0 0 1 −2.88% −2.22% −1.36%
0 1 0 1 0 −2.23% −1.91% −1.31%
0 1 0 1 1 −1.92% −1.60% −1.28%
0 1 1 0 0 −1.60% −1.28% −0.96%
0 1 1 0 1 −1.28% −0.96% −0.64%
0 1 1 1 0 −0.96% −0.64% −0.32%
0 1 1 1 1 −0.64% −0.32% ±0%
1 0 0 0 0 ±0% (default)
1 0 0 0 1 ±0% +0.32% +0.64%
1 0 0 1 0 +0.33% +0.65% +0.97%
1 0 0 1 1 +0.66% +0.98% +1.30%
1 0 1 0 0 +0.99% +1.31% +1.63%
1 0 1 0 1 +1.32% +1.64% +1.96%
1 0 1 1 0 +1.38% +1.98% +2.30%
1 0 1 1 1 +1.46% +2.32% +2.98%
1 1 0 0 0 +1.80% +2.66% +3.32%
1 1 0 0 1 +2.14% +3.00% +3.66%
1 1 0 1 0 +2.48% +3.34% +4.00%
1 1 0 1 1 +2.83% +3.69% +4.35%
1 1 1 0 0 +3.18% +4.04% +4.70%
1 1 1 0 1 +3.53% +4.39% +5.05%
1 1 1 1 0 +3.88% +4.74% +5.40%
1 1 1 1 1 +4.24% +5.10% +5.76%
Caution The internal high-speed oscillation frequency becomes faster/slower by increasing/decreasing
the HIOTRM value to a value larger/smaller than a certain value. A reversal, such as the
frequency becoming slower/faster by increasing/decreasing the HIOTRM value does not occur.
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6.4 System Clock Oscillator
6.4.1 X1 oscillator
The X1 oscillator oscillates with a crystal resonator or ceramic resonator (2 to 20 MHz) connected to the X1 and X2
pins.
An external clock can also be input. In this case, input the clock signal to the EXCLK pin.
To use the X1 oscillator, set bits 7 and 6 (EXCLK, OSCSEL) of the clock operation mode control register (CMC) as
follows.
• Crystal or ceramic oscillation: EXCLK, OSCSEL = 0, 1
• External clock input: EXCLK, OSCSEL = 1, 1
When the X1 oscillator is not used, set the input port mode (EXCLK, OSCSEL = 0, 0).
When the pins are not used as input port pins, either, see Table 2-2 Connection of Unused Pins.
Figure 6-10 shows an example of the external circuit of the X1 oscillator.
Figure 6-10. Example of External Circuit of X1 Oscillator
(a) Crystal or ceramic oscillation (b) External clock
VSS
X1
X2
Crystal resonator
or
ceramic resonator
EXCLK
External clock
Cautions are listed on the next page.
6.4.2 XT1 oscillator
The XT1 oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins.
To use the XT1 oscillator, set bit 4 (OSCSELS) of the clock operation mode control register (CMC) to 1.
When the XT1 oscillator is not used, set the input port mode (OSCSELS = 0).
When the pins are not used as input port pins, either, see Table 2-2 Connection of Unused Pins.
Figure 6-11 shows an example of the external circuit of the XT1 oscillator.
Figure 6-11. Example of External Circuit of XT1 Oscillator (Crystal Oscillation)
XT2
V
SS
XT1
32.768
kHz
Cautions are listed on the next page.
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Caution When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the
broken lines in the Figures 6-10 and 6-11 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal
line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing power
consumption.
Figure 6-12 shows examples of incorrect resonator connection.
Figure 6-12. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring (b) Crossed signal line
X2V
SS
X1 X1V
SS
X2
PORT
Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert
resistors in series on the XT2 side.
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Figure 6-12. Examples of Incorrect Resonator Connection (2/2)
(c) Wiring near high alternating current (d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
V
SS
X1 X2
V
SS
X1 X2
AB C
Pmn
V
DD
High current
High current
(e) Signals are fetched
VSS X1 X2
Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert
resistors in series on the XT2 side.
Caution When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1,
resulting in malfunctioning.
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6.4.3 Internal high-speed oscillator
The internal high-speed oscillator is incorporated in the 78K0R/KG3 (8 MHz (TYP.)). Oscillation can be controlled
by bit 0 (HIOSTOP) of the clock operation status control register (CSC).
After a reset release, the internal high-speed oscillator automatically starts oscillation.
6.4.4 Internal low-speed oscillator
The internal low-speed oscillator is incorporated in the 78K0R/KG3.
The internal low-speed oscillation clock is used only as the watchdog timer clock. The internal low-speed
oscillation clock cannot be used as the CPU clock.
After a reset release, the internal low-speed oscillator automatically starts oscillation, and the watchdog timer is
driven (240 kHz (TYP.)) if the watchdog timer operation is enabled by the option byte.
The internal low-speed oscillator continues oscillation except when the watchdog timer stops. When the watchdog
timer operates, the internal low-speed oscillation clock does not stop, even in case of a program loop.
6.4.5 Prescaler
The prescaler generates CPU/peripheral hardware clock by dividing the main system clock and subsystem clock.
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6.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby
mode (see Figure 6-1).
• Main system clock fMAIN
• High-speed system clock fMX
X1 clock fX
External main system clock fEX
• Internal high-speed oscillation clock fIH
• Subsystem clock fSUB
• Internal low-speed oscillation clock fIL
• CPU/peripheral hardware clock fCLK
The CPU starts operation when the internal high-speed oscillator starts outputting after a reset release in the
78K0R/KG3, thus enabling the following.
(1) Enhancement of security function
When the X1 clock is set as the CPU clock by the default setting, the device cannot operate if the X1 clock is
damaged or badly connected and therefore does not operate after reset is released. However, the start clock of
the CPU is the internal high-speed oscillation clock, so the device can be started by the internal high-speed
oscillation clock after a reset release. As a result, reset sources can be detected by software and the minimum
amount of safety processing can be done during anomalies to ensure that the system terminates safely.
(2) Improvement of performance
Because the CPU can be started without waiting for the X1 clock oscillation stabilization time, the total
performance can be improved.
When the power supply voltage is turned on, the clock generator operation is shown in Figure 6-13 and Figure 6-
14.
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Figure 6-13. Clock Generator Operation When Power Supply Voltage Is Turned On
(When LVI Default Start Function Stopped Is Set (Option Byte: LVIOFF = 1))
Internal high-speed
oscillation clock (fRH)
CPU clock
High-speed
system clock (fXH)
(when X1 oscillation
selected)
Internal high-speed oscillation clock
High-speed system clock
Switched by
software
Subsystem clock (fSUB)
(when XT1 oscillation
selected)
Subsystem clock
X1 clock
oscillation stabilization time:
28/fX to 218/fXNote 2
Starting X1 oscillation
is set by software.
Starting XT1 oscillation
is set by software.
Reset processing
Waiting for voltage
stabilization
Internal reset signal
0 V
1.59 V
(TYP.)
1.8 V
0.5 V/ms
(MIN.)
Power supply
voltage (V
DD
)
<1>
<2>
<4>
<5> <5>
<4>
Note 1
1.92 to 6.17 ms
<3>
<1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
<2> When the power supply voltage exceeds 1.59 V (TYP.), the reset is released and the internal high-speed
oscillator automatically starts oscillation.
<3> When the power supply voltage rises with a slope of 0.5 V/ms (MIN.), the CPU starts operation on the
internal high-speed oscillation clock after the reset is released and after the stabilization times for the voltage
of the power supply and regulator have elapsed, and then reset processing is performed.
<4> Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 6.6.1 Example of controlling high-
speed system clock and (1) in 6.6.3 Example of controlling subsystem clock).
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
switching via software (see (3) in 6.6.1 Example of controlling high-speed system clock and (2) in 6.6.3
Example of controlling subsystem clock).
Notes 1. The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
2. When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the
internal high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the
oscillation stabilization time counter status register (OSTC). If the CPU operates on the high-speed
system clock (X1 oscillation), set the oscillation stabilization time when releasing STOP mode using the
oscillation stabilization time select register (OSTS).
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Cautions 1. If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application until the
voltage reaches 1.8 V, input a low level to the RESET pin from power application until the
voltage reaches 1.8 V, or set the LVI default start function stopped by using the option byte
(LVIOFF = 0) (see Figure 6-14). By doing so, the CPU operates with the same timing as <2>
and thereafter in Figure 6-13 after reset release by the RESET pin.
2. It is not necessary to wait for the oscillation stabilization time when an external clock input
from the EXCLK pin is used.
Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via
software settings. The internal high-speed oscillation clock and high-speed system clock can be stopped
by executing the STOP instruction (see (4) in 6.6.1 Example of controlling high-speed system clock,
(3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (3) in 6.6.3 Example
of controlling subsystem clock).
Figure 6-14. Clock Generator Operation When Power Supply Voltage Is Turned On
(When LVI Default Start Function Enabled Is Set (Option Byte: LVIOFF = 0))
Internal high-speed
oscillation clock (fRH)
CPU clock
High-speed
system clock (fXH)
(when X1 oscillation
selected)
Internal high-speed
oscillation clock High-speed system clock
Switched by
software
Subsystem clock (fSUB)
(when XT1 oscillation
selected)
Subsystem clock
X1 clock
oscillation stabilization time:
28/fX to 218/fXNote 2
Starting X1 oscillation
is set by software.
Starting XT1 oscillation
is set by software.
Internal reset signal
0 V
2.07 V (TYP.)
Power supply
voltage (VDD)
<1>
<3>
<2>
<4>
<5>
Reset processing
(43 to 160 s)
<4>
<5>
Note 1
μ
<1> When the power is turned on, an internal reset signal is generated by the low-voltage detector (LVI).
<2> When the power supply voltage exceeds 2.07 V (TYP.), the reset is released and the internal high-speed
oscillator automatically starts oscillation.
<3> After the reset is released and reset processing is performed, the CPU starts operation on the internal high-
speed oscillation clock.
<4> Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 6.6.1 Example of controlling high-
speed system clock and (1) in 6.6.3 Example of controlling subsystem clock).
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
switching via software (see (3) in 6.6.1 Example of controlling high-speed system clock and (2) in 6.6.3
Example of controlling subsystem clock).
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Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
2. When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the
internal high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the
oscillation stabilization time counter status register (OSTC). If the CPU operates on the high-speed
system clock (X1 oscillation), set the oscillation stabilization time when releasing STOP mode using the
oscillation stabilization time select register (OSTS).
Cautions 1. A voltage oscillation stabilization time is required after the supply voltage reaches 1.59 V
(TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.07 V (TYP.) within the power supply
oscillation stabilization time, the power supply oscillation stabilization time is automatically
generated before reset processing.
2. It is not necessary to wait for the oscillation stabilization time when an external clock input
from the EXCLK pin is used.
Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via
software settings. The internal high-speed oscillation clock and high-speed system clock can be stopped
by executing the STOP instruction (see (4) in 6.6.1 Example of controlling high-speed system clock,
(3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (3) in 6.6.3 Example
of controlling subsystem clock).
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6.6 Controlling Clock
6.6.1 Example of controlling high-speed system clock
The following two types of high-speed system clocks are available.
• X1 clock: Crystal/ceramic resonator is connected to the X1 and X2 pins.
• External main system clock: External clock is input to the EXCLK pin.
When the high-speed system clock is not used, the X1/P121 and X2/EXCLK/P122 pins can be used as input port
pins.
Caution The X1/P121 and X2/EXCLK/P122 pins are in the input port mode after a reset release.
The following describes examples of setting procedures for the following cases.
(1) When oscillating X1 clock
(2) When using external main system clock
(3) When using high-speed system clock as CPU/peripheral hardware clock
(4) When stopping high-speed system clock
(1) Example of setting procedure when oscillating the X1 clock
<1> Setting P121/X1 and P122/X2/EXCLK pins and setting oscillation frequency (CMC register)
• 2 MHz ≤ fX ≤ 10 MHz
EXCLK OSCSEL 0 OSCSELS 0 0 0 AMPH
0 1 0 0/1 0 0 0 0
• 10 MHz < fX ≤ 20 MHz
EXCLK OSCSEL 0 OSCSELS 0 0 0 AMPH
0 1 0 0/1 0 0 0 1
Remarks 1. f
X: X1 clock oscillation frequency
2. For setting of the P123/XT1 and P124/XT2 pins, see 6.6.3 Example of controlling
subsystem clock.
<2> Controlling oscillation of X1 clock (CSC register)
If MSTOP is cleared to 0, the X1 oscillator starts oscillating.
<3> Waiting for the stabilization of the oscillation of X1 clock
Check the OSTC register and wait for the necessary time.
During the wait time, other software processing can be executed with the internal high-speed oscillation
clock.
Cautions 1. The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction.
Therefore, it is necessary to also set the value of the OSCSELS bit at the same time. For
OSCSELS bit, see 6.6.3 Example of controlling subsystem clock.
2. Set the X1 clock after the supply voltage has reached the operable voltage of the clock to
be used (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
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(2) Example of setting procedure when using the external main system clock
<1> Setting P121/X1 and P122/X2/EXCLK pins (CMC register)
EXCLK OSCSEL 0 OSCSELS 0 0 0 AMPH
1 1 0 0/1 0 0 0 ×
Remarks 1. ×: don’t care
2. For setting of the P123/XT1 and P124/XT2 pins, see 6.6.3 (1) Example of setting
procedure when oscillating the subsystem clock.
<2> Controlling external main system clock input (CSC register)
When MSTOP is cleared to 0, the input of the external main system clock is enabled.
Cautions 1. The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction.
Therefore, it is necessary to also set the value of the OSCSELS bits at the same time. For
OSCSELS bits, see 6.6.3 Example of controlling subsystem clock.
2. Set the external main system clock after the supply voltage has reached the operable
voltage of the clock to be used (see CHAPTER 29 ELECTRICAL SPECIFICATIONS
(STANDARD PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS)).
(3) Example of setting procedure when using high-speed system clock as CPU/peripheral hardware clock
<1> Setting high-speed system clock oscillationNote
(See 6.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of
setting procedure when using the external main system clock.)
Note The setting of <1> is not necessary when high-speed system clock is already operating.
<2> Setting the high-speed system clock as the source clock of the CPU/peripheral hardware clock and
setting the division ratio of the set clock (CKC register)
MCM0 MDIV2 MDIV1 MDIV0 Selection of CPU/Peripheral
Hardware Clock (fCLK)
0 0 0 fMX
0 0 1 fMX/2
0 1 0 fMX/22
0 1 1 fMX/23
1 0 0 fMX/24
1
1 0 1 fMX/25 Note
Note Setting is prohibited when fMX < 4 MHz.
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<3> If some peripheral hardware macros are not used, supply of the input clock to each hardware macro can
be stopped.
(PER0 register)
RTCEN DACEN ADCEN IIC0EN SAU1EN SAU0EN 0 TAU0EN
(PER1 register)
0 0 0 0 0 0 0 EXBEN
xxxEN Input clock control
0 Stops input clock supply.
1 Supplies input clock.
Caution Be sure to clear bit 1 of the PER0 register and bits 1 to 7 of the PER1 register to 0.
Remark RTCEN: Control of the real-time counter input clock
DACEN: Control of the D/A converter input clock
ADCEN: Control of the A/D converter input clock
IIC0EN: Control of the serial interface IIC0 input clock
SAU1EN: Control of the serial array unit 1 input clock
SAU0EN: Control of the serial array unit 0 input clock
TAU0EN: Control of the timer array unit input clock
EXBEN: Control of the external bus interface input clock
(4) Example of setting procedure when stopping the high-speed system clock
The high-speed system clock can be stopped (disabling clock input if the external clock is used) in the following
two ways.
• Executing the STOP instruction
• Setting MSTOP to 1
(a) To execute a STOP instruction
<1> Setting to stop peripheral hardware
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that
cannot be used in STOP mode, see CHAPTER 19 STANDBY FUNCTION).
<2> Setting the X1 clock oscillation stabilization time after STOP mode is released
If the X1 clock oscillates before the STOP mode is entered, set the value of the OSTS register before
executing the STOP instruction.
<3> Executing the STOP instruction
When the STOP instruction is executed, the system is placed in the STOP mode and X1 oscillation is
stopped (the input of the external clock is disabled).
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(b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1
<1> Confirming the CPU clock status (CKC register)
Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system
clock.
When CLS = 0 and MCS = 1, the high-speed system clock is supplied to the CPU, so change the
CPU clock to the subsystem clock or internal high-speed oscillation clock.
CLS MCS CPU Clock Status
0 0 Internal high-speed oscillation clock
0 1 High-speed system clock
1 × Subsystem clock
<2> Setting of X1 clock oscillation stabilization time after restart of X1 clock oscillationNote
Prior to setting "1" to MSTOP, set the OSTS register to a value greater than the count value to be
confirmed with the OSTS register after X1 clock oscillation is restarted.
<3> Stopping the high-speed system clock (CSC register)
When MSTOP is set to 1, X1 oscillation is stopped (the input of the external clock is disabled).
Note This setting is required to resume the X1 clock oscillation when the high-speed system clock is in the
X1 oscillation mode.
This setting is not required in the external clock input mode.
Caution Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, stop
peripheral hardware that is operating on the high-speed system clock.
6.6.2 Example of controlling internal high-speed oscillation clock
The following describes examples of clock setting procedures for the following cases.
(1) When restarting oscillation of the internal high-speed oscillation clock
(2) When using internal high-speed oscillation clock as CPU/peripheral hardware clock
(3) When stopping the internal high-speed oscillation clock
(1) Example of setting procedure when restarting oscillation of the internal high-speed oscillation clockNote
<1> Setting restart of oscillation of the internal high-speed oscillation clock (CSC register)
When HIOSTOP is cleared to 0, the internal high-speed oscillation clock restarts oscillation.
Note After a reset release, the internal high-speed oscillator automatically starts oscillating and the internal
high-speed oscillation clock is selected as the CPU/peripheral hardware clock.
(2) Example of setting procedure when using internal high-speed oscillation clock as CPU/peripheral
hardware clock
<1> Restarting oscillation of the internal high-speed oscillation clockNote
(See 6.6.2 (1) Example of setting procedure when restarting internal high-speed oscillation clock).
Note The setting of <1> is not necessary when the internal high-speed oscillation clock is operating.
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<2> Setting the internal high-speed oscillation clock as the source clock of the CPU/peripheral hardware clock
and setting the division ratio of the set clock (CKC register)
MCM0 MDIV2 MDIV1 MDIV0 Selection of CPU/Peripheral
Hardware Clock (fCLK)
0 0 0 fIH
0 0 1 fIH/2
0 1 0 fIH/22
0 1 1 fIH/23
1 0 0 fIH/24
0
1 0 1 fIH/25
Caution If switching the CPU/peripheral hardware clock from the high-speed system clock to the
internal high-speed oscillation clock after restarting the internal high-speed oscillation
clock, do so after 10
μ
s or more have elapsed.
If the switching is made immediately after the internal high-speed oscillation clock is
restarted, the accuracy of the internal high-speed oscillation cannot be guaranteed for
10
μ
s.
(3) Example of setting procedure when stopping the internal high-speed oscillation clock
The internal high-speed oscillation clock can be stopped in the following two ways.
• Executing the STOP instruction
• Setting HIOSTOP to 1
(a) To execute a STOP instruction
<1> Setting of peripheral hardware
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that
cannot be used in STOP mode, see CHAPTER 19 STANDBY FUNCTION).
<2> Setting the X1 clock oscillation stabilization time after STOP mode is released
If the X1 clock oscillates before the STOP mode is entered, set the value of the OSTS register before
executing the STOP instruction.
<3> Executing the STOP instruction
When the STOP instruction is executed, the system is placed in the STOP mode and internal high-
speed oscillation clock is stopped.
(b) To stop internal high-speed oscillation clock by setting HIOSTOP to 1
<1> Confirming the CPU clock status (CKC register)
Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed
oscillation clock.
When CLS = 0 and MCS = 0, the internal high-speed oscillation clock is supplied to the CPU, so
change the CPU clock to the high-speed system clock or subsystem clock.
CLS MCS CPU Clock Status
0 0 Internal high-speed oscillation clock
0 1 High-speed system clock
1 × Subsystem clock
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<2> Stopping the internal high-speed oscillation clock (CSC register)
When HIOSTOP is set to 1, internal high-speed oscillation clock is stopped.
Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting HIOSTOP to 1. In addition, stop
peripheral hardware that is operating on the internal high-speed oscillation clock.
6.6.3 Example of controlling subsystem clock
The subsystem clock can be oscillated by connecting a crystal resonator to the XT1 and XT2 pins.
When the subsystem clock is not used, the XT1/P123 and XT2/P124 pins can be used as input port pins.
Caution The XT1/P123 and XT2/P124 pins are in the input port mode after a reset release.
The following describes examples of setting procedures for the following cases.
(1) When oscillating subsystem clock
(2) When using subsystem clock as CPU clock
(3) When stopping subsystem clock
Caution When the subsystem clock is used as the CPU clock, the subsystem clock is also supplied to the
peripheral hardware (except the real-time counter, clock output/buzzer output, and watchdog
timer). At this time, the operations of the A/D converter and IIC0 are not guaranteed. For the
operating characteristics of the peripheral hardware, refer to the chapters describing the various
peripheral hardware as well as CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD
PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS).
(1) Example of setting procedure when oscillating the subsystem clock
<1> Setting P123/XT1 and P124/XT2 pins (CMC register)
EXCLK OSCSEL 0 OSCSELS 0 0 0 AMPH
0/1 0/1 0 1 0 0 0 0/1
Remark For setting of the P121/X1 and P122/X2 pins, see 6.6.1 Example of controlling high-speed
system clock.
<2> Controlling oscillation of subsystem clock (CSC register)
If XTSTOP is cleared to 0, the XT1 oscillator starts oscillating.
<3> Waiting for the stabilization of the subsystem clock oscillation
Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function.
Caution The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction.
Therefore, it is necessary to also set the value of the EXCLK and OSCSEL bits at the same
time. For EXCLK and OSCSEL bits, see 6.6.1 (1) Example of setting procedure when
oscillating the X1 clock or 6.6.1 (2) Example of setting procedure when using the external
main system clock.
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(2) Example of setting procedure when using the subsystem clock as the CPU clock
<1> Setting subsystem clock oscillationNote
(See 6.6.3 (1) Example of setting procedure when oscillating the subsystem clock.)
Note The setting of <1> is not necessary when while the subsystem clock is operating.
<2> Setting the subsystem clock as the source clock of the CPU clock (CKC register)
CSS Selection of CPU/Peripheral Hardware Clock (fCLK)
1 fSUB/2
Caution When the subsystem clock is used as the CPU clock, the subsystem clock is also supplied to
the peripheral hardware (except the real-time counter, clock output/buzzer output, and
watchdog timer). At this time, the operations of the A/D converter and IIC0 are not
guaranteed. For the operating characteristics of the peripheral hardware, refer to the
chapters describing the various peripheral hardware as well as CHAPTER 29 ELECTRICAL
SPECIFICATIONS (STANDARD PRODUCTS) and CHAPTER 30 ELECTRICAL
SPECIFICATIONS ((A) GRADE PRODUCTS).
(3) Example of setting procedure when stopping the subsystem clock
<1> Confirming the CPU clock status (CKC register)
Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock.
When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to the internal
high-speed oscillation clock or high-speed system clock. (See Figure 6-15 CPU Clock Status
Transition Diagram or Table 6-5 Changing CPU Clock for the conditions to change the subsystem
clock to another clock.)
CLS MCS CPU Clock Status
0 0 Internal high-speed oscillation clock
0 1 High-speed system clock
1 × Subsystem clock
<2> Stopping the subsystem clock (CSC register)
When XTSTOP is set to 1, the subsystem clock is stopped.
Cautions 1. Be sure to confirm that CLS = 0 when setting XTSTOP to 1. In addition, stop the
peripheral hardware if it is operating on the subsystem clock.
2. The subsystem clock oscillation cannot be stopped using the STOP instruction.
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6.6.4 Example of controlling internal low-speed oscillation clock
The internal low-speed oscillation clock cannot be used as the CPU clock. Used only as the watchdog timer clock.
The internal low-speed oscillator automatically starts oscillation after a reset release, and the watchdog timer is
driven (240 kHz (TYP.)) if the watchdog timer operation is enabled by the option byte.
The internal low-speed oscillator continues oscillation except when the watchdog timer stops. When the watchdog
timer operates, the internal low-speed oscillation clock does not stop even in case of a program loop.
(1) Example of setting procedure when stopping the internal low-speed oscillation clock
The internal low-speed oscillation clock can be stopped in the following two ways.
• Stop the watchdog timer in the HALT/STOP mode by the option byte (bit 0 (WDSTBYON) of 000C0H = 0),
and execute the HALT or STOP instruction.
• Stop the watchdog timer by the option byte (bit 4 (WDTON) of 000C0H = 0).
(2) Example of setting procedure when restarting oscillation of the internal low-speed oscillation clock
The internal low-speed oscillation clock can be restarted as follows.
• Release the HALT or STOP mode
(only when the watchdog timer is stopped in the HALT/STOP mode by the option byte (bit 0 (WDSTBYON)
of 000C0H) = 0) and when the watchdog timer is stopped as a result of execution of the HALT or STOP
instruction).
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6.6.5 CPU clock status transition diagram
Figure 6-15 shows the CPU clock status transition diagram of this product.
Figure 6-15. CPU Clock Status Transition Diagram
CPU: Operating
with X1 oscillation
or EXCLK input
(C)
(G)
CPU:
Operating with
XT1 oscillation
CPU:
XT1 oscillation
→
HALT
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Operating
(D)
Power ON
Reset release VDD ≥ 1.59 V±0.09 V
VDD < 1.59 V±0.09 V
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input:
Stops (input port mode)
XT1 oscillation: Stops (input port mode)
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Stops (input port mode)
XT1 oscillation: Stops (input port mode)
(A)
VDD ≥ 1.8 V
CPU: Operating
with internal high-
speed oscillation CPU: Internal high-
speed oscillation
→ STOP
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input:
Stops
XT1 oscillation: Oscillatable
CPU: Internal high-
speed oscillation
→ HALT
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Oscillatable
CPU: X1
oscillation/EXCLK
input → STOP
CPU: X1
oscillation/EXCLK
input → HALT
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input:
Stops
XT1 oscillation: Oscillatable
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Operating
XT1 oscillation: Oscillatable
(E)
(F)
(H)
(I)
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation: Selectable by CPU
CPU:
Operating with
XT1 oscillation
CPU:
XT1 oscillation
→ HALT
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Operating
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Operating
(B)
(D)
(G)
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation: Operating
Internal high-speed
oscillation:
Selectable by CPU
X1 oscillation/EXCLK
input: Operating
XT1 oscillation:
Selectable by CPU
Remark If the low-voltage detector (LVI) is set to ON by default by the option bytes, the reset will not be released
until the power supply voltage (VDD) exceeds 2.07 V±0.2 V.
After the reset operation, the status will shift to (B) in the above figure.
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Table 6-4 shows transition of the CPU clock and examples of setting the SFR registers.
Table 6-4. CPU Clock Transition and SFR Register Setting Examples (1/4)
(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
Status Transition SFR Register Setting
(A) → (B) SFR registers do not have to be set (default status after reset release).
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
CMC Register Note 1 CSC
Register
OSMC
Register
CKC
Register
Setting Flag of SFR Register
Status Transition EXCLK
OSCSEL
AMPH
MSTOP
FSEL
OSTC
Register
MCM0
(A) → (B) → (C)
(X1 clock: 2 MHz ≤ fX ≤ 10 MHz)
0 1 0 0 0
Must be
checked
1
(A) → (B) → (C)
(X1 clock: 10 MHz < fX ≤ 20 MHz)
0 1 1 0 1Note 2
Must be
checked
1
(A) → (B) → (C)
(external main clock)
1 1 × 0 0/1
Must
not be
checked
1
Notes 1. The CMC and OSMC registers can be written only once by an 8-bit memory manipulation instruction
after reset release.
2. FSEL = 1 when fCLK > 10 MHz
If a divided clock is selected and fCLK ≤ 10 MHz, use with FSEL = 0 is possible even if fX > 10 MHz.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set
(see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and CHAPTER 30
ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
Remark ×: don’t care
(3) CPU operating with subsystem clock (D) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
CMC RegisterNote CSC Register CKC Register
Setting Flag of SFR Register
Status Transition
OSCSELS XTSTOP
Waiting for
Oscillation
Stabilization
CSS
(A) → (B) → (D) 1 0 Necessary 1
Note The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release.
Remark (A) to (I) in Table 6-4 correspond to (A) to (I) in Figure 6-15.
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Table 6-4. CPU Clock Transition and SFR Register Setting Examples (2/4)
(4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
CMC RegisterNote 1 CSC
Register
OSMC
Register
CKC
Register
Setting Flag of SFR Register
Status Transition EXCLK
OSCSEL
AMPH
OSTS
Register
MSTOP FSEL
OSTC
Register
MCM0
(B) → (C)
(X1 clock: 2 MHz ≤ fX ≤ 10 MHz)
0 1 0 Note 2 0 0
Must be
checked
1
(B) → (C)
(X1 clock: 10 MHz < fX ≤ 20 MHz)
0 1 1 Note 2 0 1Note 3
Must be
checked
1
(B) → (C)
(external main clock)
1 1 × Note 2 0 0/1
Must not be
checked
1
Unnecessary if these
registers are already set
Unnecessary if the CPU is operating with
the high-speed system clock
Notes 1. The CMC and OSMC registers can be changed only once after reset release. This setting is not
necessary if it has already been set.
2. Set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
3. FSEL = 1 when fCLK > 10 MHz
If a divided clock is selected and fCLK ≤ 10 MHz, use with FSEL = 0 is possible even if fX > 10 MHz.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set
(see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and CHAPTER 30
ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
Remark ×: don’t care
(5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)
(Setting sequence of SFR registers)
CMC RegisterNote CSC Register CKC Register
Setting Flag of SFR Register
Status Transition
OSCSELS XTSTOP
Waiting for
Oscillation
Stabilization
CSS
(B) → (D) 1 0 Necessary 1
Unnecessary if the CPU is operating
with the subsystem clock
Note The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release.
Remark (A) to (I) in Table 6-4 correspond to (A) to (I) in Figure 6-15.
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Table 6-4. CPU Clock Transition and SFR Register Setting Examples (3/4)
(6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
CSC Register CKC Register
Setting Flag of SFR Register
Status Transition HIOSTOP
Oscillation accuracy
stabilization time MCM0
(C) → (B) 0 10
μ
s 0
Unnecessary if these
registers are already
set
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(Setting sequence of SFR registers)
CMC RegisterNote CSC Register CKC Register
Setting Flag of SFR Register
Status Transition
OSCSELS XTSTOP
Waiting for
Oscillation
Stabilization
CSS
(C) → (D) 1 0 Necessary 1
Unnecessary if the CPU is operating with the internal
high-speed oscillation clock
Note The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release.
(8) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
CSC Register CKC Register
Setting Flag of SFR Register
Status Transition HIOSTOP MCM0 CSS
(D) → (B) 0 0 0
Unnecessary if the CPU
is operating with the
internal high-speed
oscillation clock
Unnecessary if this
register is already set
Remark (A) to (I) in Table 6-4 correspond to (A) to (I) in Figure 6-15.
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Table 6-4. CPU Clock Transition and SFR Register Setting Examples (4/4)
(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
(Setting sequence of SFR registers)
CSC
Register
OSMC
Register
CKC
Register
Setting Flag of SFR Register
Status Transition
OSTS
Register
MSTOP FSEL
OSTC
Register
MCM0 CSS
(D) → (C)
(X1 clock: 2 MHz ≤ fX ≤ 10 MHz)
Note 1 0 0
Must be
checked
1 0
(D) → (C)
(X1 clock: 10 MHz < fX ≤ 20 MHz)
Note 1 0 1Note 2
Must be
checked
1 0
(D) → (C)
(external main clock)
Note 1 0 0/1
Must not be
checked
1 0
Unnecessary if the CPU is operating
with the high-speed system clock
Unnecessary if these registers
are already set
Notes 1. Set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
2. FSEL = 1 when fCLK > 10 MHz
If a divided clock is selected and fCLK ≤ 10 MHz, use with FSEL = 0 is possible even if fX > 10 MHz.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set
(see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and CHAPTER 30
ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
(10) • HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
• HALT mode (F) set while CPU is operating with high-speed system clock (C)
• HALT mode (G) set while CPU is operating with subsystem clock (D)
Status Transition Setting
(B) → (E)
(C) → (F)
(D) → (G)
Executing HALT instruction
(11) • STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
• STOP mode (I) set while CPU is operating with high-speed system clock (C)
(Setting sequence)
Status Transition Setting
(B) → (H) −
In X1 oscillation Sets the OSTS
register
(C) → (I)
External clock
Stopping peripheral
functions that cannot
operate in STOP mode
−
Executing STOP
instruction
Remark (A) to (I) in Table 6-4 correspond to (A) to (I) in Figure 6-15.
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6.6.6 Condition before changing CPU clock and processing after changing CPU clock
Condition before changing the CPU clock and processing after changing the CPU clock are shown below.
Table 6-5. Changing CPU Clock (1/2)
CPU Clock
Before Change After Change
Condition Before Change Processing After Change
X1 clock Stabilization of X1 oscillation
• OSCSEL = 1, EXCLK = 0, MSTOP = 0
• After elapse of oscillation stabilization time
External main
system clock
Enabling input of external clock from EXCLK
pin
• OSCSEL = 1, EXCLK = 1, MSTOP = 0
Internal high-
speed oscillation
clock
Subsystem clock Stabilization of X1 oscillation
• OSCSELS = 1, XTSTOP = 0
• After elapse of oscillation stabilization time
Operating current can be reduced by
stopping internal high-speed oscillator
(HIOSTOP = 1).
Internal high-
speed oscillation
clock
Oscillation of internal high-speed oscillator
• HIOSTOP = 0
X1 oscillation can be stopped (MSTOP = 1).
External main
system clock
Transition not possible
(To change the clock, set it again after
executing reset once.)
−
X1 clock
Subsystem clock Stabilization of XT1 oscillation
• OSCSELS = 1, XTSTOP = 0
• After elapse of oscillation stabilization time
X1 oscillation can be stopped (MSTOP = 1).
Internal high-
speed oscillation
clock
Oscillation of internal high-speed oscillator
• HIOSTOP = 0
External main system clock input can be
disabled (MSTOP = 1).
X1 clock Transition not possible
(To change the clock, set it again after
executing reset once.)
−
External main
system clock
Subsystem clock Stabilization of XT1 oscillation
• OSCSELS = 1, XTSTOP = 0
• After elapse of oscillation stabilization time
External main system clock input can be
disabled (MSTOP = 1).
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Table 6-5. Changing CPU Clock (2/2)
CPU Clock
Before Change After Change
Condition Before Change Processing After Change
Internal high-
speed oscillation
clock
Oscillation of internal high-speed oscillator
and selection of internal high-speed
oscillation clock as main system clock
• HIOSTOP = 0, MCS = 0
X1 clock Stabilization of X1 oscillation and selection
of high-speed system clock as main system
clock
• OSCSEL = 1, EXCLK = 0, MSTOP = 0
• After elapse of oscillation stabilization time
• MCS = 1
Subsystem
clockNote
External main
system clock
Enabling input of external clock from EXCLK
pin and selection of high-speed system clock
as main system clock
• OSCSEL = 1, EXCLK = 1, MSTOP = 0
• MCS = 1
XT1 oscillation can be stopped (XTSTOP =
1)
Note When changing the subsystem clock to another clock, the clock must be set back to the clock before setting the
subsystem clock. For example, when changing the clock to the X1 clock after having changed the internal
high-speed oscillation clock to the subsystem clock, the clock is changed in the order of the subsystem clock,
the internal high-speed oscillation clock, and the X1 clock.
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6.6.7 Time required for switchover of CPU clock and main system clock
By setting bits 0 to 2, 4, and 6 (MDIV0 to MDIV2, MCM0, CSS) of the system clock control register (CKC), the CPU
clock can be switched (between the main system clock and the subsystem clock), main system clock can be switched
(between the internal high-speed oscillation clock and the high-speed system clock), and the division ratio of the main
system clock can be changed.
The actual switchover operation is not performed immediately after rewriting to CKC; operation continues on the
pre-switchover clock for several clocks (see Table 6-6 to Table 6-9).
Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 7
(CLS) of CKC. Whether the main system clock is operating on the high-speed system clock or internal high-speed
oscillation clock can be ascertained using bit 5 (MCS) of CKC.
When the CPU clock is switched, the peripheral hardware clock is also switched.
Table 6-6. Maximum Time Required for Main System Clock Switchover
Clock A Switching directions Clock B Type
fMAINC
(Changing the division ratio)
fMAINC Type 1 (see Table 6-7)
fIH fMX Type 2 (see Table 6-8)
fMAINC fSUB/2 Type 3 (see Table 6-9)
Table 6-7. Maximum Number of Clocks Required in Type 1
Set Value After Switchover Set Value Before Switchover
Clock A Clock B
Clock A 1 + fA/fB clock
Clock B 1 + fB/fA clock
Table 6-8. Maximum Number of Clocks Required in Type 2
Set Value Before Switchover Set Value After Switchover
MCM0 MCM0
0
(fMAIN = fIH)
1
(fMAIN = fMX)
fMX≥fIH 1 + fIH/fMX clock 0
(fMAIN = fIH) fMX<fIH 2 fIH/fMX clock
fMX≥fIH 2 fMX/fIH clock 1
(fMAIN = fMX) fMX<fIH 1 + fMX/fIH clock
(Remarks are listed on the next page.)
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Table 6-9. Maximum Number of Clocks Required in Type 3
Set Value Before Switchover Set Value After Switchover
CSS CSS
0
(fCLK = fMAINC)
1
(fCLK = fSUB/2)
0
(fCLK = fMAINC)
1 + 4 fMAINC/fSUB clock
1
(fCLK = fSUB/2)
2 + fSUB/2fMAINC clock
Remarks 1. fIH :Internal high-speed oscillation clock frequency
fMX :High-speed system clock frequency
fMAIN :Main system clock frequency
fMAINC :Main system select clock frequency
fSUB :Subsystem clock frequency
fCLK :CPU/peripheral hardware clock frequency
2. The number of clocks listed in Table 6-7 to Table 6-9 is the number of CPU clocks before switchover.
3. Calculate the number of clocks in Table 6-7 to Table 6-9 by removing the decimal portion.
Example When switching the main system clock from the internal high-speed oscillation clock to the
high-speed system clock (@ oscillation with fIH = 8 MHz, fMX = 10 MHz)
1 + fIH/fMX = 1 + 8/10 = 1 + 0.8 = 1.8 → 2 clocks
6.6.8 Conditions before clock oscillation is stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped.
Table 6-10. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Clock Conditions Before Clock Oscillation Is Stopped
(External Clock Input Disabled)
Flag Settings of SFR
Register
Internal high-speed
oscillation clock
MCS = 1 or CLS = 1
(The CPU is operating on a clock other than the internal high-speed
oscillation clock)
HIOSTOP = 1
X1 clock
External main system clock
MCS = 0 or CLS = 1
(The CPU is operating on a clock other than the high-speed system clock)
MSTOP = 1
Subsystem clock CLS = 0
(The CPU is operating on a clock other than the subsystem clock)
XTSTOP = 1
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CHAPTER 7 TIMER ARRAY UNIT
The timer array unit has eight 16-bit timers per unit. Each 16-bit timer is called a channel and can be used as an
independent timer. In addition, two or more “channels” can be used to create a high-accuracy timer.
Single-Operation Function Combination Operation Function
• Interval timer
• Square wave output
• External event counter
• Divider function (channel 0 only)
• Input pulse interval measurement
• Measurement of high-/low-level width of input signal
• PWM output
• One-shot pulse output
• Multiple PWM output
Channel 7 can be used to realize LIN-bus reception processing in combination with UART3 of serial array unit 1.
7.1 Functions of Timer Array Unit
The timer array unit has the following functions.
7.1.1 Functions of each channel when it operates independently
Single-operation functions are those functions that can be used for any channel regardless of the operation mode
of the other channel (for details, refer to 7.6.1 Overview of single-operation function and combination operation
function).
(1) Interval timer
Each timer of a unit can be used as a reference timer that generates an interrupt (INTTM0n) at fixed intervals.
(2) Square wave output
A toggle operation is performed each time INTTM0n is generated and a square wave with a duty factor of 50%
is output from a timer output pin (TO0n).
(3) External event counter
Each timer of a unit can be used as an event counter that generates an interrupt when the number of the valid
edges of a signal input to the timer input pin (TI0n) has reached a specific value.
(4) Divider function (channel 0 only)
A clock input from a timer input pin (TI00) is divided and output from an output pin (TO00).
(5) Input pulse interval measurement
Counting is started by the valid edge of a pulse signal input to a timer input pin (TI0n). The count value of the
timer is captured at the valid edge of the next pulse. In this way, the interval of the input pulse can be
measured.
(6) Measurement of high-/low-level width of input signal
Counting is started by a single edge of the signal input to the timer input pin (TI0n), and the count value is
captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured.
Remark n: Channel number (n = 0 to 7)
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7.1.2 Functions of each channel when it operates with another channel
Combination operation functions are those functions that are attained by using the master channel (mostly the
reference timer that controls cycles) and the slave channels (timers that operate following the master channel) in
combination (for details, refer to 7.6.1 Overview of single-operation function and combination operation
function).
(1) PWM (Pulse Width Modulator) output
Two channels are used as a set to generate a pulse with a specified period and a specified duty factor.
(2) One-shot pulse output
Two channels are used as a set to generate a one-shot pulse with a specified delay time and a specified pulse
width.
(3) Multiple PWM (Pulse Width Modulator) output
By extending the PWM function and using one master channel and two or more slave channels, up to seven
types of PWM signals that have a specific period and a specified duty factor can be generated.
7.1.3 LIN-bus supporting function (channel 7 only)
(1) Detection of wakeup signal
The timer starts counting at the falling edge of a signal input to the serial data input pin (RxD3) of UART3 and
the count value of the timer is captured at the rising edge. In this way, a low-level width can be measured. If
the low-level width is greater than a specific value, it is recognized as a wakeup signal.
(2) Detection of sync break field
The timer starts counting at the falling edge of a signal input to the serial data input pin (RxD3) of UART3 after
a wakeup signal is detected, and the count value of the timer is captured at the rising edge. In this way, a low-
level width is measured. If the low-level width is greater than a specific value, it is recognized as a sync break
field.
(3) Measurement of pulse width of sync field
After a sync break field is detected, the low-level width and high-level width of the signal input to the serial
data input pin (RxD3) of UART3 are measured. From the bit interval of the sync field measured in this way, a
baud rate is calculated.
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7.2 Configuration of Timer Array Unit
The timer array unit includes the following hardware.
Table 7-1. Configuration of Timer Array Unit
Item Configuration
Timer/counter Timer counter register 0n (TCR0n)
Register Timer data register 0n (TDR0n)
Timer input TI00 to TI07 pins, RxD3 pin (for LIN-bus)
Timer output TO00 to TO07 pins, output controller
<Registers of unit setting block>
• Peripheral enable register 0 (PER0)
• Timer clock select register 0 (TPS0)
• Timer channel enable status register 0 (TE0)
• Timer channel start register 0 (TS0)
• Timer channel stop register 0 (TT0)
• Timer input select register 0 (TIS0)
• Timer output enable register 0 (TOE0)
• Timer output register 0 (TO0)
• Timer output level register 0 (TOL0)
• Timer output mode register 0 (TOM0)
Control registers
<Registers of each channel>
• Timer mode register 0n (TMR0n)
• Timer status register 0n (TSR0n)
• Input switch control register (ISC) (channel 7 only)
• Noise filter enable register 1 (NFEN1)
• Port mode registers 0, 1, 3, 4, 13, 14 (PM0, PM1, PM3, PM4, PM13, PM14)
• Port registers 0, 1, 3, 4, 13, 14 (P0, P1, P3, P4, P13, P14)
Remark n: Channel number (n = 0 to 7)
Figure 7-1 shows the block diagram.
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Figure 7-1. Block Diagram of Timer Array Unit
Timer clock select register 0 (TPS0)
44
f
CLK
f
CLK
/2
0
to f
CLK
/2
15
Selector
f
CLK
/2
0
to f
CLK
/2
15
Selector
Timer output
register 0
(TO0)
TO07 TO03TO06 TO05 TO04 TO02 TO01 TO00
Timer output
enable register 0
(TOE0)
TAU0EN
Peripheral enable
register 0
(PER0)
Timer channel
enable status
register 0 (TE0)
Timer channel
stop register 0
(TT0)
Timer channel
start register 0
(TS0)
Prescaler
TE07 TE03TE06 TE05 TE04 TE02 TE01 TE00
TOE07 TOE03TOE06 TOE05 TOE04 TOE02 TOE01 TOE00
TS07 TS03TS06 TS05 TS04 TS02 TS01 TS00
TT07 TT03TT06 TT05 TT04 TT02 TT01 TT00
TOL07 TOL03TOL06 TOL05 TOL04 TOL02 TOL01 TOL00
TOM07 TOM03TOM06TOM05 TOM04 TOM02TOM01 TOM00
Timer output
level register 0
(TOL0)
Timer output
mode register 0
(TOM0)
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7 (LIN-bus supported)
INTTM02
INTTM03
INTTM04
INTTM05
INTTM06
INTTM07
ISC1
Noise filter
enable register 1
(NFEN1)
Timer input
select register 0
(TIS0)
TNFEN
07
TNFEN
06
TNFEN
05
TNFEN
04
TNFEN
03
TNFEN
02
TNFEN
01
TNFEN
00
TIS07 TIS03TIS06 TIS05 TIS04 TIS02 TIS01 TIS00
Selector
PRS013 PRS003PRS012 PRS011 PRS010 PRS002 PRS001 PRS000
INTTM00
PM16
CKS01 CCS01 MAS
TER01 STS012 STS011 STS010 MD012CIS011CIS010 MD013 MD011 MD010
OVF
01
CK00
CK01
MCK
TCLK
f
SUB
/4
TIS01
TNFEN01
Interrupt
controller
Output
controller
Output latch
(P16)
INTTM01
(Timer
interrupt)
Timer status
register 01 (TSR01)
Overflow
Timer data register 01 (TDR01)
Timer counter register 01 (TCR01)
Timer mode register 01 (TMR01)
Channel 0
Channel 1
Timer controller
Trigger
selection
Count clock
selection
Mode
selection
Slave/master
controller
Slave/master
controller
Edge
detection
Selector
Operating
clock selection
Noise elimination
enabled/disabled
Trigger signal to slave channel
Clock signal to slave channel
Interrupt signal to slave channel
TI00/P00
RxD3/P14/
EX28
TI02/P17/
TO02/EX31
TI03/P31/
TO03/INTP4
TI04/P42/
TO04
TI05/P46/
INTP1/TO05
TI06/
P131/TO06
TI07/P145/
TO07
(Serial input pin)
TI01/
P16/TO01/
INTP5/EX30
(Timer input pin)
TO00/P01
TO02/P17/TI02/
EX31
TO03/P31/TI03/
INTP4
TO04/P42/TI04
TO05/P46/INTP1/
TI05
TO06/P131/TI06
TO07/P145/TI07
TO01/P16/TI01/
INTP5/EX30
(Timer output pin)
f
SUB
/4
TIS07
Selector
<R>
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(1) Timer/counter register 0n (TCR0n)
TCR0n is a 16-bit read-only register and is used to count clocks.
The value of this counter is incremented or decremented in synchronization with the rising edge of a count
clock.
Whether the counter is incremented or decremented depends on the operation mode that is selected by the
MD0n3 to MD0n0 bits of TMR0n.
Figure 7-2. Format of Timer/Counter Register 0n (TCR0n)
Address: F0180H, F0181H (TCR00) to F018EH, F018FH (TCR07) After reset: FFFFH R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCR0n
(n = 0 to 7)
The count value can be read by reading TCR0n.
The count value is set to FFFFH in the following cases.
• When the reset signal is generated
• When the TAU0EN bit of peripheral enable register 0 (PER0) is cleared
• When counting of the slave channel has been completed in the PWM output mode
• When counting of the master/slave channel has been completed in the one-shot pulse output mode
• When counting of the slave channel has been completed in the multiple PWM output mode
The count value is cleared to 0000H in the following cases.
• When the start trigger is input in the capture mode
• When capturing has been completed in the capture mode
Caution The count value is not captured to TDR0n even when TCR0n is read.
F0181H (TCR00) F0180H (TCR00)
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The TCR0n register read value differs as follows according to operation mode changes and the operating status.
Table 7-2. TCR0n Register Read Value in Various Operation Modes
TCR0n Register Read ValueNote Operation Mode Count Mode
Operation mode
change after reset
Operation mode
change after count
operation paused
(TT0n = 1)
Operation restart
after count operation
paused (TT0n = 1)
During start trigger
wait status after one
count
Interval timer
mode
Count down FFFFH Undefined Stop value −
Capture mode Count up 0000H Undefined Stop value −
Event counter
mode
Count down FFFFH Undefined Stop value −
One-count mode Count down FFFFH Undefined Stop value FFFFH
Capture & one-
count mode
Count up 0000H Undefined Stop value Capture value of
TDR0n register + 1
Note The read values of the TCR0n register when TS0n has been set to "1" while TE0n = 0 are shown. The read value
is held in the TCR0n register until the count operation starts.
Remark n = 0 to 7
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(2) Timer data register 0n (TDR0n)
This is a 16-bit register from which a capture function and a compare function can be selected.
The capture or compare function can be switched by selecting an operation mode by using the MD0n3 to
MD0n0 bits of TMR0n.
The value of TDR0n can be changed at any time.
This register can be read or written in 16-bit units.
Reset signal generation clears this register to 0000H.
Figure 7-3. Format of Timer Data Register 0n (TDR0n)
Address: FFF18H, FFF19H (TDR00), FFF1AH, FFF1BH (TDR01), After reset: 0000H R/W
FFF64H, FFF65H (TDR02) to FFF6EH, FFF6FH (TDR07)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR0n
(n = 0 to 7)
(i) When TDR0n is used as compare register
Counting down is started from the value set to TDR0n. When the count value reaches 0000H, an interrupt
signal (INTTM0n) is generated. TDR0n holds its value until it is rewritten.
Caution TDR0n does not perform a capture operation even if a capture trigger is input, when it is
set to the compare function.
(ii) When TDR0n is used as capture register
The count value of TCR0n is captured to TDR0n when the capture trigger is input.
A valid edge of the TI0n pin can be selected as the capture trigger. This selection is made by TMR0n.
Remark n = 0 to 7
FFF19H (TDR00) FFF18H (TDR00)
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7.3 Registers Controlling Timer Array Unit
The timer array unit is controlled by the following registers.
• Peripheral enable register 0 (PER0)
• Timer clock select register 0 (TPS0)
• Timer mode register 0n (TMR0n)
• Timer status register 0n (TSR0n)
• Timer channel enable status register 0 (TE0)
• Timer channel start register 0 (TS0)
• Timer channel stop register 0 (TT0)
• Timer input select register 0 (TIS0)
• Timer output enable register 0 (TOE0)
• Timer output register 0 (TO0)
• Timer output level register 0 (TOL0)
• Timer output mode register 0 (TOM0)
• Input switch control register (ISC)
• Noise filter enable register 1 (NFEN1)
• Port mode registers 0, 1, 3, 4, 13, 14 (PM0, PM1, PM3, PM4, PM13, PM14)
• Port registers 0, 1, 3, 4, 13, 14 (P0, P1, P3, P4, P13, P14)
Remark n = 0 to 7
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(1) Peripheral enable register 0 (PER0)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro
that is not used is stopped in order to reduce the power consumption and noise.
When the timer array unit is used, be sure to set bit 0 (TAU0EN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-4. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> 1 <0>
PER0 RTCEN DACEN ADCEN IIC0EN SAU1EN SAU0EN 0 TAU0EN
TAU0EN Control of timer array unit input clock
0 Stops supply of input clock.
• SFR used by the timer array unit cannot be written.
• The timer array unit is in the reset status.
1 Supplies input clock.
• SFR used by the timer array unit can be read/written.
Cautions 1. When setting the timer array unit, be sure to set TAU0EN to 1 first. If TAU0EN = 0, writing
to a control register of the timer array unit is ignored, and all read values are default
values (except for timer input select register 0 (TIS0), input switch control register (ISC),
noise filter enable register 1 (NFEN1), port mode registers 0, 1, 3, 4, 13, 14 (PM0, PM1, PM3,
PM4, PM13, PM14), and port registers 0, 1, 3, 4, 13, 14 (P0, P1, P3, P4, P13, P14)).
2. Be sure to clear bit 1 of the PER0 register to 0.
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(2) Timer clock select register 0 (TPS0)
TPS0 is a 16-bit register that is used to select two types of operation clocks (CK00, CK01) that are commonly
supplied to each channel. CK01 is selected by bits 7 to 4 of TPS0, and CK00 is selected by bits 3 to 0.
Rewriting of TPS0 during timer operation is possible only in the following cases.
Rewriting of PRS000 to PRS003 bits: Possible only when all the channels set to CKS0n = 0 are in the
operation stopped state (TE0n = 0)
Rewriting of PRS010 to PRS013 bits: Possible only when all the channels set to CKS0n = 1 are in the
operation stopped state (TE0n = 0)
TPS0 can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TPS0 can be set with an 8-bit memory manipulation instruction with TPS0L.
Reset signal generation clears this register to 0000H.
Figure 7-5. Format of Timer Clock Select Register 0 (TPS0)
Address: F01B6H, F01B7H After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPS0 0 0 0 0 0 0 0 0
PRS
013
PRS
012
PRS
011
PRS
010
PRS
003
PRS
002
PRS
001
PRS
000
Selection of operation clock (CK0m)Note
PRS
0m3
PRS
0m2
PRS
0m1
PRS
0m0 f
CLK = 2 MHz fCLK = 5 MHz fCLK = 10 MHz fCLK = 20 MHz
0 0 0 0 fCLK 2 MHz 5 MHz 10 MHz 20 MHz
0 0 0 1 fCLK/2 1 MHz 2.5 MHz 5 MHz 10 MHz
0 0 1 0 fCLK/22 500 kHz 1.25 MHz 2.5 MHz 5 MHz
0 0 1 1 fCLK/23 250 kHz 625 kHz 1.25 MHz 2.5 MHz
0 1 0 0 fCLK/24 125 kHz 312.5 kHz 625 kHz 1.25 MHz
0 1 0 1 fCLK/25 62.5 kHz 156.2 kHz 312.5 kHz 625 kHz
0 1 1 0 fCLK/26 31.25 kHz 78.1 kHz 156.2 kHz 312.5 kHz
0 1 1 1 fCLK/27 15.62 kHz 39.1 kHz 78.1 kHz 156.2 kHz
1 0 0 0 fCLK/28 7.81 kHz 19.5 kHz 39.1 kHz 78.1 kHz
1 0 0 1 fCLK/29 3.91 kHz 9.76 kHz 19.5 kHz 39.1 kHz
1 0 1 0 fCLK/210 1.95 kHz 4.88 kHz 9.76 kHz 19.5 kHz
1 0 1 1 fCLK/211 976 Hz 2.44 kHz 4.88 kHz 9.76 kHz
1 1 0 0 fCLK/212 488 Hz 1.22 kHz 2.44 kHz 4.88 kHz
1 1 0 1 fCLK/213 244 Hz 610 Hz 1.22 kHz 2.44 kHz
1 1 1 0 fCLK/214 122 Hz 305 Hz 610 Hz 1.22 kHz
1 1 1 1 fCLK/215 61 Hz 153 Hz 305 Hz 610 Hz
Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value),
stop the timer array unit (TT0 = 00FFH).
Caution Be sure to clear bits 15 to 8 to “0”.
Remarks 1. f
CLK: CPU/peripheral hardware clock frequency
2. m = 0, 1 n = 0 to 7
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(3) Timer mode register 0n (TMR0n)
TMR0n sets an operation mode of channel n. It is used to select an operation clock (MCK), a count clock,
whether the timer operates as the master or a slave, a start trigger and a capture trigger, the valid edge of the
timer input, and an operation mode (interval, capture, event counter, one-count, or capture & one-count).
Rewriting TMR0n is prohibited when the register is in operation (when TE0 = 1). However, bits 7 and 6
(CIS0n1, CIS0n0) can be rewritten even while the register is operating with some functions (when TE0 = 1) (for
details, see 7.7 Operation of Timer Array Unit as Independent Channel and 7.8 Operation of Plural
Channels of Timer Array Unit).
TMR0n can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 7-6. Format of Timer Mode Register 0n (TMR0n) (1/3)
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS
0n
0 0
CCS
0n
MAST
ER0n
STS
0n2
STS
0n1
STS
0n0
CIS
0n1
CIS
0n0
0 0
MD
0n3
MD
0n2
MD
0n1
MD
0n0
CKS
0n
Selection of operation clock (MCK) of channel n
0 Operation clock CK00 set by TPS0 register
1 Operation clock CK01 set by TPS0 register
Operation clock MCK is used by the edge detector. A count clock (TCLK) is generated depending on the setting of
the CCS0n bit.
CCS
0n
Selection of count clock (TCLK) of channel n
0 Operation clock MCK specified by CKS0n bit
1 Valid edge of input signal input from TI0n pin/subsystem clock divided by 4 (fSUB/4)
Count clock TCLK is used for the timer/counter, output controller, and interrupt controller.
MAS
TER
0n
Selection of operation in single-operation function or as slave channel in combination operation function/
operation as master channel in combination operation function of channel n
0 Operates in single-operation function or as slave channel in combination operation function.
1 Operates as master channel in combination operation function.
Only the even channel can be set as a master channel (MASTER0n = 1).
Be sure to use the odd channel as a slave channel (MASTER0n = 0).
Clear MASTER0n to 0 for a channel that is used as the single-operation function.
Caution Be sure to clear bits 14, 13, 5, and 4 to “0”.
Remark n = 0 to 7
<R>
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Figure 7-6. Format of Timer Mode Register 0n (TMR0n) (2/3)
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS
0n
0 0
CCS
0n
MAST
ER0n
STS
0n2
STS
0n1
STS
0n0
CIS
0n1
CIS
0n0
0 0
MD
0n3
MD
0n2
MD
0n1
MD
0n0
STS
0n2
STS
0n1
STS
0n0
Setting of start trigger or capture trigger of channel n
0 0 0 Only software trigger start is valid (other trigger sources are unselected).
0 0 1 Valid edge of TI0n pin input is used as both the start trigger and capture trigger.
0 1 0 Both the edges of TI0n pin input are used as a start trigger and a capture trigger.
1 0 0
Interrupt signal of the master channel is used (when the channel is used as a slave channel
with the combination operation function).
Other than above Setting prohibited
CIS
0n1
CIS
0n0
Selection of TI0n pin input valid edge
0 0 Falling edge
0 1 Rising edge
1 0
Both edges (when low-level width is measured)
Start trigger: Falling edge, Capture trigger: Rising edge
1 1
Both edges (when high-level width is measured)
Start trigger: Rising edge, Capture trigger: Falling edge
If both the edges are specified when the value of the STS0n2 to STS0n0 bits is other than 010B, set the CIS0n1 to
CIS0n0 bits to 10B.
Remark n = 0 to 7
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User’s Manual U17894EJ9V0UD 241
Figure 7-6. Format of Timer Mode Register 0n (TMR0n) (3/3)
Address: F0190H, F0191H (TMR00) - F019EH, F019FH (TMR07) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS
0n
0 0
CCS
0n
MAST
ER0n
STS
0n2
STS
0n1
STS
0n0
CIS
0n1
CIS
0n0
0 0
MD
0n3
MD
0n2
MD
0n1
MD
0n0
MD
0n3
MD
0n2
MD
0n1
MD
0n0
Operation mode of channel n Count operation of TCR
Independent operation
0 0 0 1/0 Interval timer mode Counting down Possible
0 1 0 1/0 Capture mode Counting up Possible
0 1 1 0 Event counter mode Counting down Possible
1 0 0 1/0 One-count mode Counting down Impossible
1 1 0 0 Capture & one-count mode Counting up Possible
Other than above Setting prohibited
The operation of MD0n0 bits varies depending on each operation mode (see table below).
Operation mode
(Value set by the MD0n3 to MD0n1 bits
(see table above))
MD
0n0
Setting of starting counting and interrupt
0 Timer interrupt is not generated when counting is started
(timer output does not change, either).
• Interval timer mode
(0, 0, 0)
• Capture mode
(0, 1, 0)
1 Timer interrupt is generated when counting is started
(timer output also changes).
• Event counter mode
(0, 1, 1)
0 Timer interrupt is not generated when counting is started
(timer output does not change, either).
0 Start trigger is invalid during counting operation.
At that time, interrupt is not generated, either.
• One-count mode
(1, 0, 0)
1 Start trigger is valid during counting operationNote.
At that time, interrupt is also generated.
• Capture & one-count mode
(1, 1, 0)
0 Timer interrupt is not generated when counting is started
(timer output does not change, either).
Start trigger is invalid during counting operation.
At that time interrupt is not generated, either.
Other than above Setting prohibited
Note If the start trigger (TS0n = 1) is issued during operation, the counter is cleared, an interrupt is generated,
and recounting is started.
Remark n = 0 to 7
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(4) Timer status register 0n (TSR0n)
TSR0n indicates the overflow status of the counter of channel n.
TSR0n is valid only in the capture mode (MD0n3 to MD0n1 = 010B) and capture & one-count mode (MD0n3 to
MD0n1 = 110B). It will not be set in any other mode. See Table 7-3 for the operation of the OVF bit in each
operation mode and set/clear conditions.
TSR0n can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of TSR0n can be set with an 8-bit memory manipulation instruction with TSR0nL.
Reset signal generation clears this register to 0000H.
Figure 7-7. Format of Timer Status Register 0n (TSR0n)
Address: F01A0H, F01A1H (TSR00) to F01AEH, F01AFH (TSR07) After reset: 0000H R
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSR0n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF
OVF Counter overflow status of channel n
0 Overflow does not occur.
1 Overflow occurs.
When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow.
Table 7-3. OVF Bit Operation and Set/Clear Conditions in Each Operation Mode
Timer operation mode OVF Set/clear conditions
clear When no overflow has occurred upon capturing • Capture mode
• Capture & one-count mode set When an overflow has occurred upon capturing
clear • Interval timer mode
• Event counter mode
• One-count mode set
−
(Use prohibited, not set/cleared)
Remark The OVF bit does not change immediately after the counter has overflowed, but changes upon
the subsequent capture.
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(5) Timer channel enable status register 0 (TE0)
TE0 is used to enable or stop the timer operation of each channel.
When a bit of timer channel start register 0 (TS0) is set to 1, the corresponding bit of this register is set to 1.
When a bit of timer channel stop register 0 (TT0) is set to 1, the corresponding bit of this register is cleared to
0.
TE0 can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of TE0 can be set with a 1-bit or 8-bit memory manipulation instruction with TE0L.
Reset signal generation clears this register to 0000H.
Figure 7-8. Format of Timer Channel Enable Status Register 0 (TE0)
Address: F01B0H, F01B1H After reset: 0000H R
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE0 0 0 0 0 0 0 0 0 TE07 TE06 TE05 TE04 TE03 TE02 TE01 TE00
TE0n Indication of operation enable/stop status of channel n
0 Operation is stopped.
1 Operation is enabled.
Remark n = 0 to 7
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(6) Timer channel start register 0 (TS0)
TS0 is a trigger register that is used to clear a timer counter (TCR0n) and start the counting operation of each
channel.
When a bit (TS0n) of this register is set to 1, the corresponding bit (TE0n) of timer channel enable status
register 0 (TE0) is set to 1. TS0n is a trigger bit and cleared immediately when TE0n = 1.
TS0 can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TS0 can be set with a 1-bit or 8-bit memory manipulation instruction with TS0L.
Reset signal generation clears this register to 0000H.
Figure 7-9. Format of Timer Channel Start Register 0 (TS0)
Address: F01B2H, F01B3H After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS0 0 0 0 0 0 0 0 0 TS07 TS06 TS05 TS04 TS03 TS02 TS01 TS00
TS0n Operation enable (start) trigger of channel n
0 No trigger operation
1 TE0n is set to 1 and the count operation becomes enabled.
The TCR0n count operation start in the count operation enabled state varies depending on each operation
mode (see Table 7-4).
Caution Be sure to clear bits 15 to 8 to “0”.
Remarks 1. When the TS0 register is read, 0 is always read.
2. n = 0 to 7
Table 7-4. Operations from Count Operation Enabled State to TCR0n Count Start (1/2)
Timer operation mode Operation when TS0n = 1 is set
• Interval timer mode
No operation is carried out from start trigger detection (TS0n=1) until count clock
generation.
The first count clock loads the value of TDR0n to TCR0n and the subsequent
count clock performs count down operation (see 7.3 (6) (a) Start timing in
interval timer mode).
• Event counter mode
Writing 1 to TS0n bit loads the value of TDR0n to TCR0n.
The subsequent count clock performs count down operation.
The external trigger detection selected by STS0n2 to STS0n0 bits in the TMR0n
register does not start count operation (see 7.3 (6) (b) Start timing in event
counter mode).
• Capture mode
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to TCR0n and the subsequent count clock
performs count up operation (see 7.3 (6) (c) Start timing in capture mode).
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Table 7-4. Operations from Count Operation Enabled State to TCR0n Count Start (2/2)
Timer operation mode Operation when TS0n = 1 is set
• One-count mode When TS0n = 0, writing 1 to TS0n bit sets the start trigger wait state.
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads the value of TDR0n to TCR0n and the subsequent
count clock performs count down operation (see 7.3 (6) (d) Start timing in one-
count mode).
• Capture & one-count mode When TS0n = 0, writing 1 to TS0n bit sets the start trigger wait state.
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to TCR0n and the subsequent count clock
performs count up operation (see 7.3 (6) (e) Start timing in capture & one-
count mode).
(a) Start timing in interval timer mode
<1> Writing 1 to TS0n sets TE0n = 1
<2> The write data to TS0n is held until count clock generation.
<3> TCR0n holds the initial value until count clock generation.
<4> On generation of count clock, the “TDR0n value” is loaded to TCR0n and count starts.
Figure 7-10. Start Timing (In Interval Timer Mode)
TS0n (write)
TE0n
Count clock
fCLK
TCR0n
INTTM0n
Initial value TDR0n value
When MD0n0 = 1 is set
<1>
<2>
<3> <4>
Start trigger detection signal
TS0n (write) hold signal
Caution In the first cycle operation of count clock after writing TS0n, an error at a maximum of one
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start
by setting MD0n0 = 1.
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(b) Start timing in event counter mode
<1> While TE0n is set to 0, TCR0n holds the initial value.
<2> Writing 1 to TS0n sets 1 to TE0n.
<3> As soon as 1 has been written to TS0n and 1 has been set to TE0n, the "TDR0n value" is loaded to
TCR0n to start counting.
<4> After that, the TCR0n value is counted down according to the count clock.
Figure 7-11. Start Timing (In Event Counter Mode)
TE0n
f
CLK
TCR0n TDR0n value
<1>
<1>
<2>
<3>
TDR0n value − 1
Initial value
TS0n (write)
Count clock
Start trigger detection signal
TS0n (write) hold signal
(c) Start timing in capture mode
<1> Writing 1 to TS0n sets TE0n = 1
<2> The write data to TS0n is held until count clock generation.
<3> TCR0n holds the initial value until count clock generation.
<4> On generation of count clock, 0000H is loaded to TCR0n and count starts.
Figure 7-12. Start Timing (In Capture Mode)
TE0n
f
CLK
TCR0n
INTTM0n
0000H
<1>
<2>
<3> <4>
Initial value
When MD0n0 = 1 is set
TS0n (write)
Count clock
Start trigger detection signal
TS0n (write) hold signal
Caution In the first cycle operation of count clock after writing TS0n, an error at a maximum of one
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start
by setting MD0n0 = 1.
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(d) Start timing in one-count mode
<1> Writing 1 to TS0n sets TE0n = 1
<2> Enters the start trigger input wait status, and TCR0n holds the initial value.
<3> On start trigger detection, the “TDR0n value” is loaded to TCR0n and count starts.
Figure 7-13. Start Timing (In One-count Mode)
TE0n
f
CLK
TCR0n
Start trigger input wait status
TDR0n valueInitial value
<1>
<2> <3>
TS0n (write)
Count clock
Note
Start trigger detection signal
TS0n (write) hold signal
TI0n edge detection signal
Note When the one-count mode is set, the operation clock (MCK) is selected as count clock (CCS0n = 0).
Caution An input signal sampling error is generated since operation starts upon start trigger
detection (The error is one count clock when TI0n is used).
<R>
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(e) Start timing in capture & one-count mode
<1> Writing 1 to TS0n sets TE0n = 1
<2> Enters the start trigger input wait status, and TCR0n holds the initial value.
<3> On start trigger detection, 0000H is loaded to TCR0n and count starts.
Figure 7-14. Start Timing (In Capture & One-count Mode)
TE0n
f
CLK
TCR0n 0000H
TS0n (write)
Count clock
Note
Start trigger detection signal
TS0n (write) hold signal
TI0n edge detection signal
Start trigger input wait status
Initial value
<2> <3>
<1>
Note When the capture & one-count mode is set, the operation clock (MCK) is selected as count clock
(CCS0n = 0).
Caution An input signal sampling error is generated since operation starts upon start trigger
detection (The error is one count clock when TI0n is used).
<R>
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(7) Timer channel stop register 0 (TT0)
TT0 is a trigger register that is used to clear a timer counter (TCR0n) and start the counting operation of each
channel.
When a bit (TT0n) of this register is set to 1, the corresponding bit (TE0n) of timer channel enable status
register 0 (TE0) is cleared to 0. TT0n is a trigger bit and cleared to 0 immediately when TE0n = 0.
TT0 can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TT0 can be set with a 1-bit or 8-bit memory manipulation instruction with TT0L.
Reset signal generation clears this register to 0000H.
Figure 7-15. Format of Timer Channel Stop Register 0 (TT0)
Address: F01B4H, F01B5H After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TT0 0 0 0 0 0 0 0 0 TT07 TT06 TT05 TT04 TT03 TT02 TT01 TT00
TT0n Operation stop trigger of channel n
0 No trigger operation
1 Operation is stopped (stop trigger is generated).
Caution Be sure to clear bits 15 to 8 to “0”.
Remarks 1. When the TT0 register is read, 0 is always read.
2. n = 0 to 7
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(8) Timer input select register 0 (TIS0)
TIS0 is used to select whether a signal input to the timer input pin (TI0n) or the subsystem clock divided by four
(fSUB/4) is valid for each channel.
TIS0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-16. Format of Timer Input Select Register 0 (TIS0)
Address: FFF3EH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
TIS0 TIS07 TIS06 TIS05 TIS04 TIS03 TIS02 TIS01 TIS00
TIS0n Selection of timer input/subsystem clock used with channel n
0 Input signal of timer input pin (TI0n)
1 Subsystem clock divided by 4 (fSUB/4)
(9) Timer output enable register 0 (TOE0)
TOE0 is used to enable or disable timer output of each channel.
Channel n for which timer output has been enabled becomes unable to rewrite the value of the TO0n bit of the
timer output register (TO0) described later by software, and the value reflecting the setting of the timer output
function through the count operation is output from the timer output pin (TO0n).
TOE0 can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TOE0 can be set with a 1-bit or 8-bit memory manipulation instruction with TOE0L.
Reset signal generation clears this register to 0000H.
Figure 7-17. Format of Timer Output Enable Register 0 (TOE0)
Address: F01BAH, F01BBH After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOE0 0 0 0 0 0 0 0 0
TOE
07
TOE
06
TOE
05
TOE
04
TOE
03
TOE
02
TOE
01
TOE
00
TOE
0n
Timer output enable/disable of channel n
0 The TO0n operation stopped by count operation (timer channel output bit).
Writing to the TO0n bit is enabled.
The TO0n pin functions as data output, and it outputs the level set to the TO0n bit.
The output level of the TO0n pin can be manipulated by software.
1 The TO0n operation enabled by count operation (timer channel output bit).
Writing to the TO0n bit is disabled (writing is ignored).
The TO0n pin functions as timer output, and the TOE0n is set or reset depending on the timer operation.
The TO0n pin outputs the square-wave or PWM depending on the timer operation.
Caution Be sure to clear bits 15 to 8 to “0”.
Remark n = 0 to 7
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(10) Timer output register 0 (TO0)
TO0 is a buffer register of timer output of each channel.
The value of each bit in this register is output from the timer output pin (TO0n) of each channel.
This register can be rewritten by software only when timer output is disabled (TOE0n = 0). When timer output
is enabled (TOE0n = 1), rewriting this register by software is ignored, and the value is changed only by the
timer operation.
To use the P01/TO00, P16/TO01, P17/TO02, P31/TO03, P42/TO04, P46/TO05, P131/TO06, or P145/TO07
pin as a port function pin, set the corresponding TO0n bit to “0”.
TO0 can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TO0 can be set with an 8-bit memory manipulation instruction with TO0L.
Reset signal generation clears this register to 0000H.
Figure 7-18. Format of Timer Output Register 0 (TO0)
Address: F01B8H, F01B9H After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO0 0 0 0 0 0 0 0 0
TO0
7
TO0
6
TO0
5
TO0
4
TO0
3
TO0
2
TO0
1
TO0
0
TO0
n
Timer output of channel n
0 Timer output value is “0”.
1 Timer output value is “1”.
Caution Be sure to clear bits 15 to 8 to “0”.
Remark n = 0 to 7
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(11) Timer output level register 0 (TOL0)
TOL0 is a register that controls the timer output level of each channel.
The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the
timer output signal while the timer output is enabled (TOE0n = 1) in the combination operation mode (TOM0n
= 1). In the toggle mode (TOM0n = 0), this register setting is invalid.
TOL0 can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TOL0 can be set with an 8-bit memory manipulation instruction with TOL0L.
Reset signal generation clears this register to 0000H.
Figure 7-19. Format of Timer Output Level Register 0 (TOL0)
Address: F01BCH, F01BDH After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOL0 0 0 0 0 0 0 0 0
TOL
07
TOL
06
TOL
05
TOL
04
TOL
03
TOL
02
TOL
01
TOL
00
TOL
0n
Control of timer output level of channel n
0 Positive logic output (active-high)
1 Inverted output (active-low)
Caution Be sure to clear bits 15 to 8 to “0”.
Remarks 1. If the value of this register is rewritten during timer operation, the timer output is inverted when
the timer output signal changes next, instead of immediately after the register value is rewritten.
2. n = 0 to 7
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(12) Timer output mode register 0 (TOM0)
TOM0 is used to control the timer output mode of each channel.
When a channel is used for the single-operation function, set the corresponding bit of the channel to be used
to 0.
When a channel is used for the combination operation function (PWM output, one-shot pulse output, or
multiple PWM output), set the corresponding bit of the master channel to 0 and the corresponding bit of the
slave channel to 1.
The setting of each channel n by this register is reflected at the timing when the timer output signal is set or
reset while the timer output is enabled (TOE0n = 1).
TOM0 can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TOM0 can be set with an 8-bit memory manipulation instruction with TOM0L.
Reset signal generation clears this register to 0000H.
Figure 7-20. Format of Timer Output Mode Register 0 (TOM0)
Address: F01BEH, F01BFH After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOM0 0 0 0 0 0 0 0 0
TOM
07
TOM
06
TOM
05
TOM
04
TOM
03
TOM
02
TOM
01
TOM
00
TOM
0n
Control of timer output mode of channel n
0 Toggle mode (to produce toggle output by timer interrupt request signal (INTTM0n))
1 Combination operation mode (output is set by the timer interrupt request signal (INITTM0n) of the master
channel, and reset by the timer interrupt request signal (INITTM0m) of the slave channel)
Caution Be sure to clear bits 15 to 8 to “0”.
Remark n: Channel number, m: Slave channel number
n = 0 to 7 (n = 0, 2, 4, 6 for master channel)
n < m ≤ 7 (where m is a consecutive integer greater than n)
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(13) Input switch control register (ISC)
ISC is used to implement LIN-bus communication operation with channel 7 in association with serial array unit
1.
When bit 1 of this register is set to 1, the input signal of the serial data input pin (RxD3) is selected as a timer
input signal.
ISC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-21. Format of Input Switch Control Register (ISC)
Address: FFF3CH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ISC 0 0 0 0 0 0 ISC1 ISC0
ISC1 Switching channel 7 input of timer array unit
0 Uses the input signal of the TI07 pin as a timer input (normal operation).
1 Input signal of RXD3 pin is used as timer input
(to measure the pulse widths of the sync break field and sync field).
ISC0 Switching external interrupt (INTP0) input
0 Uses the input signal of the INTP0 pin as an external interrupt (normal operation).
1 Uses the input signal of the RXD3 pin as an external interrupt (wakeup signal detection).
Caution Be sure to clear bits 7 to 2 to “0”.
Remark When the LIN-bus communication function is used, select the input signal of the RxD3 pin by
setting ISC1 to 1.
(14) Noise filter enable register 1 (NFEN1)
NFEN1 is used to set whether the noise filter can be used for the timer input signal to each channel.
Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
When the noise filter is ON, match detection and synchronization of the 2 clocks is performed with the
CPU/peripheral hardware clock (fCLK). When the noise filter is OFF, only synchronization is performed with
the CPU/peripheral hardware clock (fCLK).
NFEN1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
<R>
<R>
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Figure 7-22. Format of Noise Filter Enable Register 1 (NFEN1)
Address: F0061H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00
TNFEN07 Enable/disable using noise filter of TI07/TO07/P145 pin or RxD3/P14/EX26 pin input signalNote
0 Noise filter OFF
1 Noise filter ON
TNFEN06 Enable/disable using noise filter of TI06/TO06/P131 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN05 Enable/disable using noise filter of TI05/TO05/P46 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN04 Enable/disable using noise filter of TI04/TO04/P42 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN03 Enable/disable using noise filter of TI03/TO03/INTP4/P31 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN02 Enable/disable using noise filter of TI02/TO02/P17 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN01 Enable/disable using noise filter of TI01/TO01/INTP5/P16 pin input signal
0 Noise filter OFF
1 Noise filter ON
TNFEN00 Enable/disable using noise filter of TI00/P00 pin input signal
0 Noise filter OFF
1 Noise filter ON
Note The applicable pin can be switched by setting ISC1 of the ISC register.
ISC1 = 0: Whether or not to use the noise filter of TI07 pin can be selected.
ISC1 = 1: Whether or not to use the noise filter of RxD3 pin can be selected.
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(15) Port mode registers 0, 1, 3, 4, 13, 14 (PM0, PM1, PM3, PM4, PM13, PM14)
These registers set input/output of ports 0, 1, 3, 4, 13, and 14 in 1-bit units.
When using the P01/TO00, P16/TO01/TI01/INTP5/EX30, P17/TO02/TI02/EX31, P31/TO03/TI03/INTP4,
P42/TO04/TI04, P46/TO05/TI05/INTP1, P131/TO06/TI06, and P145/TO07/TI07 pins for timer output, set
PM01, PM16, PM17, PM31, PM42, PM46, PM131, and PM145 and the output latches of P01, P16, P17, P31,
P42, P46, P131, and P145 to 0.
When using the P00/TI00, P16/TO01/TI01/INTP5/EX30, P17/TO02/TI02/EX31, P31/TO03/TI03/INTP4,
P42/TO04/TI04, P46/TO05/TI05/INTP1, P131/TO06/TI06, and P145/TO07/TI07 pins for timer input, set PM00,
PM16, PM17, PM31, PM42, PM46, PM131, and PM145 to 1. At this time, the output latches of P00, P16,
P17, P31, P42, P46, P131, and P145 may be 0 or 1.
PM0, PM1, PM3, PM4, PM13, and PM14 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Figure 7-23. Format of Port Mode Registers 0, 1, 3, 4, 13, and 14 (PM0, PM1, PM3, PM4, PM13, PM14)
Address: FFF20H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00
Address: FFF21H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
Address: FFF23H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM3 1 1 1 1 1 1 PM31 PM30
Address: FFF24H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40
Address: FFF2DH After reset: FEH R/W
Symbol 7 6 5 4 3 2 1 0
PM13 1 1 1 1 1 1 PM131 0
Address: FFF2EH After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM14 1 1 PM145 PM144 PM143 PM142 PM141 PM140
PMmn Pmn pin I/O mode selection (m = 0, 1, 3, 4, 13, 14; n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
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7.4 Channel Output (TO0n pin) Control
7.4.1 TO0n pin output circuit configuration
Figure 7-24. Output Circuit Configuration
Interrupt signal of the master channel
(INTTM0n)
TOL0n
TOM0n
TOE0n
<1>
<2> <3> <4>
<5>
TO0n write signal
TO0n pin
TO0n register
Set
Reset/toggle
Internal bus
Interrupt signal of the slave channel
(INTTM0p)
Controller
The following describes the TO0n pin output circuit.
<1> When TOM0n = 0 (toggle mode), the set value of the TOL0n register is ignored and only INTTM0p (slave
channel timer interrupt) is transmitted to the TO0n register.
<2> When TOM0n = 1 (combination operation mode), both INTTM0n (master channel timer interrupt) and
INTTM0p (slave channel timer interrupt) are transmitted to the TO0n register.
At this time, the TOL0n register becomes valid and the signals are controlled as follows:
When TOL0n = 0: Forward operation (INTTM0 → set, INTTM0p → reset)
When TOL0n = 1: Reverse operation (INTTM0 → reset, INTTM0p → set)
When INTTM0n and INTTM0p are simultaneously generated, (0% output of PWM), INTTM0p (reset
signal) takes priority, and INTTM0n (set signal) is masked.
<3> When TOE0n = 1, INTTM0n (master channel timer interrupt) and INTTM0p (slave channel timer interrupt)
are transmitted to the TO0n register. Writing to the TO0n register (TO0n write signal) becomes invalid.
When TOE0n = 1, the TO0n pin output never changes with signals other than interrupt signals.
To initialize the TO0n pin output level, it is necessary to set TOE0n = 0 and to write a value to TO0n.
<4> When TOE0n = 0, writing to TO0n bit to the target channel (TO0n signal) becomes valid. When TOE0n =
0, neither INTTM0n (master channel timer interrupt) nor INTTM0p (slave channel timer interrupt) is
transmitted to TO0n register.
<5> The TO0n register can always be read, and the TO0n pin output level can be checked.
Remarks 1. n = 0 to 7 (n = 0, 2, 4, or 6 for master channel)
2. p = n + 1, n + 2, n + 3 ... (where p ≤ 7)
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7.4.2 TO0n pin output setting
The following figure shows the procedure and status transition of TO0n out put pin from initial setting to timer
operation start.
Figure 7-25. Status Transition from Timer Output Setting to Operation Start
TCR0n
Timer alternate-function pin
Timer output signal
TOE0n
TO0n
(Counter)
Undefined value (FFFFH after reset)
Write operation enabled period to TO0n
<1> Set TOM0n
Set TOL0n
<4> Set the port to
output mode
<2> Set TO0n <3> Set TOE0n <5> Timer operation start
Write operation disabled period to TO0n
Hi-Z
<1> The operation mode of timer output is set.
• TOM0n bit (0: Toggle mode, 1: Combination operation mode)
• TOL0n bit (0: Forward output, 1: Reverse output)
<2> The timer output signal is set to the initial status by setting TO0n.
<3> The timer output operation is enabled by writing 1 to TOE0n (writing to TO0n is disabled).
<4> The port I/O setting is set to output (see 7.3 (15) Port mode registers 0, 1, 3, 4, 13, 14).
<5> The timer operation is enabled (TS0n = 1).
Remark n = 0 to 7
7.4.3 Cautions on channel output operation
(1) Changing values set in registers TO0, TOE0, TOL0, and TOM0 during timer operation
Since the timer operations (operations of TCR0n and TDR0n) are independent of the TO0n output circuit and
changing the values set in TO0, TOE0, TOL0, and TOM0 does not affect the timer operation, the values can be
changed during timer operation. To output an expected waveform from the TO0n pin by timer operation,
however, set TO0, TOE0, TOL0, and TOM0 to the values stated in the register setting example of each
operation.
When the values set in TOE0, TOL0, and TOM0 (except for TO0) are changed close to the timer interrupt
(INTTM0n), the waveform output to the TO0n pin may be different depending on whether the values are
changed immediately before or immediately after the timer interrupt (INTTM0n) signal generation timing.
Remark n = 0 to 7
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(2) Default level of TO0n pin and output level after timer operation start
The following figure shows the TO0n pin output level transition when writing has been done in the state of
TOE0n = 0 before port output is enabled and TOE0n = 1 is set after changing the default level.
(a) When operation starts with TOM0n = 0 setting (toggle output)
The setting of TOL0n is invalid when TOM0n = 0. When the timer operation starts after setting the default
level, the toggle signal is generated and the output level of TO0n pin is reversed.
Figure 7-26. TO0n Pin Output Status at Toggle Output (TOM0n = 0)
TOE0n
TO0n = 0, TOL0n = 0
TO0n = 1, TOL0n = 0
TO0n = 0, TOL0n = 1
(Same output waveform as TOL0n = 0)
TO0n = 1, TOL0n = 1
(Same output waveform as TOL0n = 0)
Default level, TOL0n setting
Independent of TOL0n setting
Port output is enabled
TO0n pin transition
Toggle Toggle Toggle Toggle Toggle
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Dependent on TO0n setting
Remarks 1. Toggle: Reverse TO0n pin output status
2. n = 0 to 7
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(b) When operation starts with TOM0n = 1 setting (Combination operation mode (PWM output))
When TOM0n = 1, the active level is determined by TOL0n setting.
Figure 7-27. TO0n Pin Output Status at PWM Output (TOM0n = 1)
TOE0n
TO0n = 0, TOL0n = 0
(Active high)
TO0n = 1, TOL0n = 0
(Active high)
TO0n = 0, TOL0n = 1
(Active low)
TO0n = 1, TOL0n = 1
(Active low)
Default level, TOL0n setting
Dependent on TOL0n setting
Dependent on TO0n setting
No change
Set Reset Set Reset Set
Hi-Z
Hi-Z
Hi-Z
Hi-Z
TO0n pin transition
Port output is enabled
Remarks 1. Set: The output signal of TO0n pin changes from inactive level to active level.
Reset: The output signal of TO0n pin changes from active level to inactive level.
2. n = 0 to 7
(3) Operation of TO0n pin in combination operation mode (TOM0n = 1)
(a) When TOL0n setting has been changed during timer operation
When the TOL0n setting has been changed during timer operation, the setting becomes valid at the
generation timing of TO0n change condition. Rewriting TOL0n does not change the output level of TO0n.
The following figure shows the operation when the value of TOL0n has been changed during timer
operation (TOM0n = 1).
Figure 7-28. Operation when TOL0n Has Been Changed during Timer Operation
Internal set signal
Internal reset signal
TOL0n
TO0n pin
Set/reset signals are invertedTO0n does not change
Remarks 1. Set: The output signal of TO0n pin changes from inactive level to active level.
Reset: The output signal of TO0n pin changes from active level to inactive level.
2. n = 0 to 7
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(b) Set/reset timing
To realize 0%/100% output at PWM output, the TO0n pin/TO0n set timing at master channel timer interrupt
(INTTM0n) generation is delayed by 1 count clock by the slave channel.
If the set condition and reset condition are generated at the same time, a higher priority is given to the
latter.
Figure 7-29 shows the set/reset operating statuses where the master/slave channels are set as follows.
Master channel: TOE0n = 1, TOM0n = 0, TOL0n = 0
Slave channel: TOE0p = 1, TOM0p = 1, TOL0p = 0
Figure 7-29. Set/Reset Timing Operating Statuses
to_reset
(Internal signal)
to_reset
(Internal signal)
(Internal signal)
INTTM0n
TO0n pin/
TO0n
TO0p pin/
TO0p
Count clock
f
CLK
INTTM0p
to_set
Delays to_reset by 1 count
clock with slave channel
Toggle
Set Reset
Master channel
Slave channel
Remarks 1. to_reset: TO0n pin reset/toggle signal
to_set: TO0n pin set signal
2. n = 0 to 7 (where n = 0, 2, 4, or 6 for master channel)
3. p = n + 1, n + 2, n + 3 ... (where p ≤ 7)
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7.4.4 Collective manipulation of TO0n bits
In the TO0 register, the setting bits for all the channels are located in one register in the same way as the TS0
register (channel start trigger). Therefore, TO0n of all the channels can be manipulated collectively. Only specific bits
can also be manipulated by setting the corresponding TOE0n = 0 to a target TO0n (channel output).
Figure 7-30. Example of TO0n Bits Collective Manipulation
Before writing
TO0 0 0 0 0 0 0 0 0 TO07
0
TO06
0
TO05
1
TO04
0
TO03
0
TO02
0
TO01
1
TO00
0
TOE0 0 0 0 0 0 0 0 0
TOE07
0
TOE06
0
TOE05
1
TOE04
0
TOE03
1
TOE02
1
TOE01
1
TOE00
1
Data to be written
0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
After writing
TO0 0 0 0 0 0 0 0 0 TO07
1
TO06
1
TO05
1
TO04
0
TO03
0
TO02
0
TO01
1
TO00
0
Writing is done only to TO0n bits with TOE0n = 0, and writing to TO0n bits with TOE0n = 1 is ignored.
TO0n (channel output) to which TOE0n = 1 is set is not affected by the write operation. Even if the write operation
is done to TO0n, it is ignored and the output change by timer operation is normally done.
Figure 7-31. TO0n Pin Statuses by Collective Manipulation of TO0n Bit
TO07
TO06
TO05
TO04
TO03
TO02
TO01
TO00
Two or more TO0n output can
be changed simultaneously
Output does not change
when value does not
change
Before writing
Writing to TO0n register
is ignored when TOE0n
= 1
Writing to TO0n register
(Caution and Remark are given on the next page.)
O
OO× ×
×
××
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Caution When TOE0n = 1, even if the output by timer interrupt of each timer (INTTM0n) contends with
writing to TO0n, output is normally done to TO0n pin.
Remark n = 0 to 7
7.4.5 Timer interrupt and TO0n pin output at count operation start
In the interval timer mode or capture mode, the MD0n0 bit in the TMR0n register sets whether or not to generate a
timer interrupt at count start.
When MD0n0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTM0n)
generation.
In the other modes, neither timer interrupt at count operation start nor TO0n output is controlled.
Figures 7-32 and 7-33 show operation examples when the interval timer mode (TOE0n = 1, TOM0n = 0) is set.
Figure 7-32. When MD0n0 Is Set to 1
TCR0n
TE0n
TO0n
INTTM0n
Count operation start
When MD0n0 is set to 1, a timer interrupt (INTTM0n) is output at count operation start, and TO0n performs a
toggle operation.
Figure 7-33. When MD0n0 Is Set to 0
TCR0n
TE0n
TO0n
INTTM0n
Count operation start
When MD0n0 is set to 0, a timer interrupt (INTTM0n) is not output at count operation start, and TO0n does not
change either. After counting one cycle, INTTM0n is output and TO0n performs a toggle operation.
Remark n = 0 to 7
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7.5 Channel Input (TI0n Pin) Control
7.5.1 TI0n edge detector
(1) Edge detection basic operation timing
Edge detector sampling is done in accordance with the operation clock (MCK).
Figure 7-34. Edge Detection Basic Operation Timing
Synchronized (noise filter)
internal TI0n signal
fCLK
Rising edge detection
internal trigger
Falling edge detection
internal trigger
Operation clock (MCK)
Remark n = 0 to 7
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7.6 Basic Function of Timer Array Unit
7.6.1 Overview of single-operation function and combination operation function
The timer array unit consists of several channels and has a single-operation function that allows each channel to
operate independently, and a combination operation function that uses two or more channels in combination.
The single-operation function can be used for any channel, regardless of the operation mode of the other channels.
The combination operation function is realized by combining a master channel (reference timer that mainly counts
periods) and a slave channel (timer that operates in accordance with the master channel), and several rules must be
observed when using this function.
7.6.2 Basic rules of combination operation function
The basic rules of using the combination operation function are as follows.
(1) Only an even channel (channel 0, 2, 4, etc.) can be set as a master channel.
(2) Any channel, except channel 0, can be set as a slave channel.
(3) The slave channel must be lower than the master channel.
Example: If channel 2 is set as a master channel, channel 3 or those that follow (channels 3, 4, 5, etc.) can
be set as a slave channel.
(4) Two or more slave channels can be set for one master channel.
(5) When two or more master channels are to be used, slave channels with a master channel between them may
not be set.
Example: If channels 0 and 4 are set as master channels, channels 1 to 3 can be set as the slave channels
of master channel 0. Channels 5 to 7 cannot be set as the slave channels of master channel 0.
(6) The operating clock for a slave channel in combination with a master channel must be the same as that of the
master channel. The CKS bit (bit 15 of the TMR0n register) of the slave channel that operates in combination
with the master channel must be the same value as that of the master channel.
(7) A master channel can transmit INTTM0n (interrupt), start software trigger, and count clock to the lower
channels.
(8) A slave channel can use the INTTM0n (interrupt), start software trigger, and count clock of the master channel,
but it cannot transmit its own INTTM0n (interrupt), start software trigger, and count clock to the lower channel.
(9) A master channel cannot use the INTTM0n (interrupt), start software trigger, and count clock from the other
master channel.
(10) To simultaneously start channels that operate in combination, the TS0n bit of the channels in combination
must be set at the same time.
(11) During a counting operation, the TS0n bit of all channels that operate in combination or only the master
channel can be set. TS0n of only a slave channel cannot be set.
(12) To stop the channels in combination simultaneously, the TT0n bit of the channels in combination must be set
at the same time.
Remark n = 0 to 7
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Channel 1: Slave
Channel 0: Master Channel group 1
(combination operation function)
* The operating clock of channel group 1 may
be different from that of channel group 2.
Channel 2: Slave
Channel 3: Single-operation function
Channel 4: Master
Channel 5: Slave
Channel 6: Single-operation function
Channel 7: Single-operation function
CK00
CK01
TAU
* A channel that singly operates may be
between channel group 1 and channel group
2.
Channel group 2
(combination operation function)
7.6.3 Applicable range of basic rules of combination operation function
The rules of the combination operation function are applied in a channel group (a master channel and slave
channels forming one combination operation function).
If two or more channel groups that do not operate in combination are specified, the basic rules of the combination
operation function in 7.6.2 Basic rules of combination operation function do not apply to the channel groups.
Example
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7.7 Operation of Timer Array Unit as Independent Channel
7.7.1 Operation as interval timer/square wave output
(1) Interval timer
The timer array unit can be used as a reference timer that generates INTTM0n (timer interrupt) at fixed
intervals.
The interrupt generation period can be calculated by the following expression.
Generation period of INTTM0n (timer interrupt) = Period of count clock × (Set value of TDR0n + 1)
A subsystem clock divided by four (fSUB/4) can be selected as the count clock, in addition to CK00 and CK01.
Consequently, the interval timer can be operated with the count clock fixed to fSUB/4, regardless of the fCLK
frequency (main system clock, subsystem clock). When changing the clock selected as fCLK (changing the
value of the system clock control register (CKC)), however, stop the timer array unit (TAU) (TT0 = 00FFH) first.
(2) Operation as square wave output
TO0n performs a toggle operation as soon as INTTM0n has been generated, and outputs a square wave with
a duty factor of 50%.
The period and frequency for outputting a square wave from TO0n can be calculated by the following
expressions.
• Period of square wave output from TO0n = Period of count clock × (Set value of TDR0n + 1) × 2
• Frequency of square wave output from TO0n = Frequency of count clock/{(Set value of TDR0n + 1) × 2}
TCR0n operates as a down counter in the interval timer mode.
TCR0n loads the value of TDR0n at the first count clock after the channel start trigger bit (TS0n) is set to 1. If
MD0n0 of TMR0n = 0 at this time, INTTM0n is not output and TO0n is not toggled. If MD0n0 of TMR0n = 1,
INTTM0n is output and TO0n is toggled.
After that, TCR0n count down in synchronization with the count clock.
When TCR0n = 0000H, INTTM0n is output and TO0n is toggled at the next count clock. At the same time,
TCR0n loads the value of TDR0n again. After that, the same operation is repeated.
TDR0n can be rewritten at any time. The new value of TDR0n becomes valid from the next period.
Remarks 1. n = 0 to 7
2. f
CLK: CPU/peripheral hardware clock frequency
f
SUB: Subsystem clock oscillation frequency
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Figure 7-35. Block Diagram of Operation as Interval Timer/Square Wave Output
CK00
f
SUB
/4
CK01
TS0n
Timer counter
(TCR0n) TO0n pin
Interrupt signal
(INTTM0n)
Data register
(TDR0n)
Interrupt
controller
Output
controller
Clock selection
Trigger selection
Operation clock
Edge
detection
Figure 7-36. Example of Basic Timing of Operation as Interval Timer/Square Wave Output (MD0n0 = 1)
TS0n
TE0n
TDR0n
TCR0n
TO0n
INTTM0n
a
a + 1
b
0000H
a + 1 a + 1 b + 1 b + 1 b + 1
Remark n = 0 to 7
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Figure 7-37. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output
(1/3)
(1) When CK00 or CK01 is selected as count clock
(a) Timer mode register 0n (TMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS0n
1/0
0
0
CCS0n
0
MAS
TER0n
0
STS0n2
0
STS0n1
0
STS0n0
0
CIS0n1
0
CIS0n0
0
0
0
MD0n3
0
MD0n2
0
MD0n1
0
MD0n0
1/0
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTM0n nor inverts
timer output when counting is started.
1: Generates INTTM0n and inverts timer
output when counting is started.
Selection of TI0n pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Slave/master selection
0: Cleared to 0 when single-operation function is selected.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CK00 as operation clock of channel n.
1: Selects CK01 as operation clock of channel n.
(b) Timer output register 0 (TO0)
Bit n
TO0 TO0n
1/0
0: Outputs 0 from TO0n.
1: Outputs 1 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE0n
1/0
0: Stops the TO0n output operation by counting operation.
1: Enables the TO0n output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL0n
0
0: Cleared to 0 when TOM0n = 0 (toggle mode)
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM0n
0
0: Sets toggle mode.
Remark n = 0 to 7
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Figure 7-37. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output
(2/3)
(2) When fSUB/4 is selected as count clock
(a) Timer mode register 0n (TMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS0n
1/0
0
0
CCS0n
1
MAS
TER0n
0
STS0n2
0
STS0n1
0
STS0n0
0
CIS0n1
1/0
CIS0n0
1/0
0
0
MD0n3
0
MD0n2
0
MD0n1
0
MD0n0
1/0
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTM0n nor inverts
timer output when counting is started.
1: Generates INTTM0n and inverts timer
output when counting is started.
fSUB/4 edge selection
00B: Detects falling edge (counts on fSUB/4 cycles).
01B: Detects rising edge (counts on fSUB/4 cycles).
10B: Detects both edges (counts on fSUB/2 cycles).
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
Slave/master selection
0: Cleared to 0 when single-operation function is selected.
Count clock selection
1: Selects subsystem clock divided by four (fSUB/4).
Operation clock selection
0: Selects CK00 as operation clock of channel n.
1: Selects CK01 as operation clock of channel n.
fCLK (no division) is selected as selected operation clock by TPS0 register.
(b) Timer clock select register 0 (TPS0)
Bits 7 to 4, 3 to 0
TPS0 PRS0m3 to PRS0m0
0000
0000B: Selects fCLK (no division) as operation clock selected by CKS0n of TMR0n register.
m = 0 (bits 0 to 3) when CK00 is selected and m = 1 (bits 4 to 7) when CK01 is selected
(c) Timer input select register 0 (TIS0)
Bit n
TIS0 TIS0n
1
1: Selects subsystem clock divided by four (fSUB/4).
(d) Timer output register 0 (TO0)
Bit n
TO0 TO0n
1/0
0: Outputs 0 from TO0n.
1: Outputs 1 from TO0n.
Remarks 1. n = 0 to 7, m = 0, 1
2. f
SUB: Subsystem clock oscillation frequency
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Figure 7-37. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output
(3/3)
(2) When fSUB/4 is selected as count clock (continued)
(e) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE0n
1/0
0: Stops the TO0n output operation by counting operation.
1: Enables the TO0n output operation by counting operation.
(f) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL0n
0
0: Cleared to 0 when TOM0n = 0 (toggle mode)
(g) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM0n
0
0: Sets toggle mode.
Remark n = 0 to 7, m = 0, 1
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Figure 7-38. Operation Procedure of Interval Timer/Square Wave Output Function
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of the PER0 register to 1. Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets the TPS0 register.
Determines clock frequencies of CK00 and CK01.
Sets the TMR0n register (determines operation mode of
channel).
Sets the TIS0n bit to 1 (fSUB/4) when fSUB/4 is selected as
the count clock.
Sets interval (period) value to the TDR0n register.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Channel
default
setting
To use the TO0n output
Clears the TOM0n bit of the TOM0 register to 0 (toggle
mode).
Clears the TOL0n bit to 0.
Sets the TO0n bit and determines default level of the
TO0n output.
Sets TOE0n to 1 and enables operation of TO0n.
Clears the port register and port mode register to 0.
The TO0n pin goes into Hi-Z output state.
The TO0n default setting level is output when the port mode
register is in the output mode and the port register is 0.
TO0n does not change because channel stops operating.
The TO0n pin outputs the TO0n set level.
Operation
start
Sets TOE0n to 1 (only when operation is resumed).
Sets the TS0n bit to 1.
The TS0n bit automatically returns to 0 because it is a
trigger bit.
TE0n = 1, and count operation starts.
Value of TDR0n is loaded to TCR0n at the count clock
input. INTTM0n is generated and TO0n performs toggle
operation if the MD0n0 bit of the TMR0n register is 1.
During
operation
Set values of the TMR0n register, TOM0n, and TOL0n
bits cannot be changed.
Set value of the TDR0n register can be changed.
The TCR0n register can always be read.
The TSR0n register is not used.
Set values of the TO0 and TOE0 registers can be
changed.
Counter (TCR0n) counts down. When count value reaches
0000H, the value of TDR0n is loaded to TCR0n again and the
count operation is continued. By detecting TCR0n = 0000H,
INTTM0n is generated and TO0n performs toggle operation.
After that, the above operation is repeated.
The TT0n bit is set to 1.
The TT0n bit automatically returns to 0 because it is a
trigger bit.
TE0n = 0, and count operation stops.
TCR0n holds count value and stops.
The TO0n output is not initialized but holds current status.
Operation
stop
TOE0n is cleared to 0 and value is set to the TO0n bit. The TO0n pin outputs the TO0n set level.
TAU stop To hold the TO0n pin output level
Clears TO0n bit to 0 after the value to
be held is set to the port register.
When holding the TO0n pin output level is not necessary
Switches the port mode register to input mode.
The TO0n pin output level is held by port function.
The TO0n pin output level goes into Hi-Z output state.
The TAU0EN bit of the PER0 register is cleared to 0. Power-off status
All circuits are initialized and SFR of each channel is also
initialized.
(The TO0n bit is cleared to 0 and the TO0n pin is set to
port mode.)
Remark n = 0 to 7
Operation is resumed.
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7.7.2 Operation as external event counter
The timer array unit can be used as an external event counter that counts the number of times the valid input edge
(external event) is detected in the TI0n pin. When a specified count value is reached, the event counter generates an
interrupt. The specified number of counts can be calculated by the following expression.
Specified number of counts = Set value of TDR0n + 1
TCR0n operates as a down counter in the event counter mode.
When the channel start trigger bit (TS0n) is set to 1, TCR0n loads the value of TDR0n.
TCR0n counts down each time the valid input edge of the TI0n pin has been detected. When TCR0n = 0000H,
TCR0n loads the value of TDR0n again, and outputs INTTM0n.
After that, the above operation is repeated.
TO0n must not be used because its waveform depends on the external event and irregular.
TDR0n can be rewritten at any time. The new value of TDR0n becomes valid during the next count period.
Figure 7-39. Block Diagram of Operation as External Event Counter
Timer counter
(TCR0n)
Edge
detection
Interrupt signal
(INTTM0n)
TI0n pin
Data register
(TDR0n) Interrupt
controller
Clock selection
Trigger selection
TS0n
Remark n = 0 to 7
Figure 7-40. Example of Basic Timing of Operation as External Event Counter
TS0n
TE0n
TI0n
TDR0n
TCR0n
0003H 0002H
0
0000H
1
3
0
12
0
121
2
3
2
INTTM0n
4 events 4 events 3 events
Remark n = 0 to 7
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Figure 7-41. Example of Set Contents of Registers in External Event Counter Mode
(a) Timer mode register 0n (TMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS0n
1/0
0
0
CCS0n
1
MAS
TER0n
0
STS0n2
0
STS0n1
0
STS0n0
0
CIS0n1
1/0
CIS0n0
1/0
0
0
MD0n3
0
MD0n2
1
MD0n1
1
MD0n0
0
Operation mode of channel n
011B: Event count mode
Setting of operation when counting is started
0: Neither generates INTTM0n nor inverts
timer output when counting is started.
Selection of TI0n pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
Slave/master selection
0: Cleared to 0 when single-operation function is selected.
Count clock selection
1: Selects the TI0n pin input valid edge.
Operation clock selection 0: Selects CK00 as operation clock of channel n.
1: Selects CK01 as operation clock of channel n.
(b) Timer output register 0 (TO0)
Bit n
TO0 TO0n
0
0: Outputs 0 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE0n
0
0: Stops the TO0n output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL0n
0
0: Cleared to 0 when TOM0n = 0 (toggle mode).
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM0n
0
0: Sets toggle mode.
Remark n = 0 to 7
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Figure 7-42. Operation Procedure When External Event Counter Function Is Used
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of the PER0 register to 1. Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets the TPS0 register.
Determines clock frequencies of CK00 and CK01.
Channel
default
setting
Sets the TMR0n register (determines operation mode of
channel).
Sets number of counts to the TDR0n register.
Clears the TOE0n bit of the TOE0 register to 0.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Operation
start
Sets the TS0n bit to 1.
The TS0n bit automatically returns to 0 because it is a
trigger bit.
TE0n = 1, and count operation starts.
Value of TDR0n is loaded to TCR0n and detection of
the TI0n pin input edge is awaited.
During
operation
Set value of the TDR0n register can be changed.
The TCR0n register can always be read.
The TSR0n register is not used.
Set values of the TMR0n register, TOM0n, TOL0n, TO0n,
and TOE0n bits cannot be changed.
Counter (TCR0n) counts down each time input edge of the
TI0n pin has been detected. When count value reaches
0000H, the value of TDR0n is loaded to TCR0n again, and
the count operation is continued. By detecting TCR0n =
0000H, the INTTM0n output is generated.
After that, the above operation is repeated.
Operation
stop
The TT0n bit is set to 1.
The TT0n bit automatically returns to 0 because it is a
trigger bit.
TE0n = 0, and count operation stops.
TCR0n holds count value and stops.
TAU stop The TAU0EN bit of the PER0 register is cleared to 0. Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark n = 0 to 7
Operation is resumed.
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7.7.3 Operation as frequency divider (channel 0 only)
The timer array unit can be used as a frequency divider that divides a clock input to the TI00 pin and outputs the
result from TO00.
The divided clock frequency output from TO00 can be calculated by the following expression.
• When rising edge/falling edge is selected:
Divided clock frequency = Input clock frequency/{(Set value of TDR00 + 1) × 2}
• When both edges are selected:
Divided clock frequency ≅ Input clock frequency/(Set value of TDR00 + 1)
TCR00 operates as a down counter in the interval timer mode.
After the channel start trigger bit (TS00) is set to 1, TCR00 loads the value of TDR00 when the TI00 valid edge is
detected. If MD000 of TMR00 = 0 at this time, INTTM00 is not output and TO00 is not toggled. If MD000 of TMR00 =
1, INTTM00 is output and TO00 is toggled.
After that, TCR00 counts down at the valid edge of TI00. When TCR00 = 0000H, it toggles TO00. At the same
time, TCR00 loads the value of TDR00 again, and continues counting.
If detection of both the edges of TI00 is selected, the duty factor error of the input clock affects the divided clock
period of the TO00 output.
The period of the TO00 output clock includes a sampling error of one period of the operation clock.
Clock period of TO00 output = Ideal TO00 output clock period ± Operation clock period (error)
TDR00 can be rewritten at any time. The new value of TDR00 becomes valid during the next count period.
Figure 7-43. Block Diagram of Operation as Frequency Divider
Timer counter
(TCR00)
Edge
detection
TI00 pin
Data register
(TDR00)
Clock selection
Trigger selection
TS00
TO00 pin
Output
controller
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Figure 7-44. Example of Basic Timing of Operation as Frequency Divider (MD000 = 1)
TS00
TE00
TI00
TDR00
TCR00
TO00
INTTM00
0002H
Divided
by 6
0001H
0
0000H
1
2
0
1
2
0
1
0
1
0
1
0
1
0
1
2
Divided
by 4
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Figure 7-45. Example of Set Contents of Registers When Frequency Divider Is Used
(a) Timer mode register 00 (TMR00)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR00 CKS00
1/0
0
0
CCS00
1
MAS
TER00
0
STS002
0
STS001
0
STS000
0
CIS001
1/0
CIS000
1/0
0
0
MD003
0
MD002
0
MD001
0
MD000
1/0
Operation mode of channel 0
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTM00 nor inverts
timer output when counting is started.
1: Generates INTTM00 and inverts timer
output when counting is started.
Selection of TI00 pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
Slave/master selection
0: Cleared to 0 when single-operation function is selected.
Count clock selection
1: Selects the TI00 pin input valid edge.
Operation clock selection 0: Selects CK00 as operation clock of channel 0.
1: Selects CK01 as operation clock of channel 0.
(b) Timer output register 0 (TO0)
Bit n
TO0 TO00
1/0
0: Outputs 0 from TO00.
1: Outputs 1 from TO00.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE00
1/0
0: Stops the TO00 output operation by counting operation.
1: Enables the TO00 output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL00
0
0: Cleared to 0 when TOM00 = 0 (toggle mode)
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM00
0
0: Sets toggle mode.
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Figure 7-46. Operation Procedure When Frequency Divider Function Is Used
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of the PER0 register to 1. Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets the TPS0 register.
Determines clock frequencies of CK00 and CK01.
Sets the TMR00 register (determines operation mode of
channel).
Sets interval (period) value to the TDR00 register.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Channel
default
setting
Clears the TOM00 bit of the TOM0 register to 0 (toggle
mode).
Clears the TOL00 bit to 0.
Sets the TO00 bit and determines default level of the
TO00 output.
Sets TOE00 to 1 and enables operation of TO00.
Clears the port register and port mode register to 0.
The TO00 pin goes into Hi-Z output state.
The TO00 default setting level is output when the port
mode register is in output mode and the port register is 0.
TO00 does not change because channel stops operating.
The TO00 pin outputs the TO00 set level.
Operation
start
Sets TOE00 to 1 (only when operation is resumed).
Sets the TS00 bit to 1.
The TS00 bit automatically returns to 0 because it is a
trigger bit.
TE00 = 1, and count operation starts.
Value of TDR00 is loaded to TCR00 at the count clock
input. INTTM00 is generated and TO00 performs toggle
operation if the MD000 bit of the TMR00 register is 1.
During
operation
Set value of the TDR00 register can be changed.
The TCR00 register can always be read.
The TSR00 register is not used.
Set values of the TO0 and TOE0 registers can be
changed.
Set values of the TMR00 register, TOM00, and TOL00
bits cannot be changed.
Counter (TCR00) counts down. When count value
reaches 0000H, the value of TDR00 is loaded to TCR00
again, and the count operation is continued. By detecting
TCR00 = 0000H, INTTM00 is generated and TO00
performs toggle operation.
After that, the above operation is repeated.
The TT00 bit is set to 1.
The TT00 bit automatically returns to 0 because it is a
trigger bit.
TE00 = 0, and count operation stops.
TCR00 holds count value and stops.
The TO00 output is not initialized but holds current
status.
Operation
stop
TOE00 is cleared to 0 and value is set to the TO00 bit. The TO00 pin outputs the TO00 set level.
To hold the TO00 pin output level
Clears the TO00 bit to 0 after the value
to be held is set to the port register.
When holding the TO00 pin output level is not
necessary
Switches the port mode register to input mode.
The TO00 pin output level is held by port function.
The TO00 pin output level goes into Hi-Z output state.
TAU stop
The TAU0EN bit of the PER0 register is cleared to 0. Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TO00 bit is cleared to 0 and the TO00 pin is set to
port mode).
Operation is resumed.
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7.7.4 Operation as input pulse interval measurement
The count value can be captured at the TI0n valid edge and the interval of the pulse input to TI0n can be measured.
The pulse interval can be calculated by the following expression.
TI0n input pulse interval = Period of count clock × ((10000H × TSR0n: OVF) + (Capture value of TDR0n + 1))
Caution The TI0n pin input is sampled using the operating clock selected with the CKS0n bit of the
TMR0n register, so an error equal to the number of operating clocks occurs.
TCR0n operates as an up counter in the capture mode.
When the channel start trigger (TS0n) is set to 1, TCR0n counts up from 0000H in synchronization with the count
clock.
When the TI0n pin input valid edge is detected, the count value is transferred (captured) to TDR0n and, at the
same time, the counter (TCR0n) is cleared to 0000H, and the INTTM0n is output. If the counter overflows at this time,
the OVF bit of the TSR0n register is set to 1. If the counter does not overflow, the OVF bit is cleared. After that, the
above operation is repeated.
As soon as the count value has been captured to the TDR0n register, the OVF bit of the TSR0n register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF
bit of the TSR0n register is set to 1. However, the OVF bit is configured as a cumulative flag, the correct interval
value cannot be measured if an overflow occurs more than once.
Set STS0n2 to STS0n0 of the TMR0n register to 001B to use the valid edges of TI0n as a start trigger and a
capture trigger.
When TE0n = 1, instead of the TI0n pin input, a software operation (TS0n = 1) can be used as a capture trigger.
Figure 7-47. Block Diagram of Operation as Input Pulse Interval Measurement
Timer counter
(TCR0n)
Interrupt signal
(INTTM0n)
Data register
(TDR0n) Interrupt
controller
Clock selection
Trigger selection
Operation clock
CK00
CK01
Edge
detection
TI0n pin
TS0n
Remark n = 0 to 7
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Figure 7-48. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MD0n0 = 0)
TS0n
TE0n
TI0n
TDR0n
TCR0n
0000H c
b
0000H
acd
INTTM0n
FFFFH
ba d
OVF
Remark n = 0 to 7
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Figure 7-49. Example of Set Contents of Registers to Measure Input Pulse Interval
(a) Timer mode register 0n (TMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS0n
1/0
0
0
CCS0n
0
MAS
TER0n
0
STS0n2
0
STS0n1
0
STS0n0
1
CIS0n1
1/0
CIS0n0
1/0
0
0
MD0n3
0
MD0n2
1
MD0n1
0
MD0n0
1/0
Operation mode of channel n
010B: Ca
p
ture mode
Setting of operation when counting is started
0: Does not generate INTTM0n when
counting is started.
1: Generates INTTM0n when counting is
started.
Selection of TI0n pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Capture trigger selection
001B: Selects the TI0n pin input valid edge.
Slave/master selection
0: Cleared to 0 when single-operation function is selected.
Count clock selection
0: Selects operation clock.
Operation clock selection 0: Selects CK00 as operation clock of channel n.
1: Selects CK01 as operation clock of channel n.
(b) Timer output register 0 (TO0)
Bit n
TO0 TO0n
0
0: Outputs 0 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE0n
0
0: Stops TO0n output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL0n
0
0: Cleared to 0 when TOM0n = 0 (toggle mode).
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM0n
0
0: Sets toggle mode.
Remark n = 0 to 7
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Figure 7-50. Operation Procedure When Input Pulse Interval Measurement Function Is Used
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of the PER0 register to 1. Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets the TPS0 register.
Determines clock frequencies of CK00 and CK01.
Channel
default
setting
Sets the TMR0n register (determines operation mode of
channel).
Channel stops operating.
(Clock is supplied and some power is consumed.)
Operation
start
Sets TS0n bit to 1.
The TS0n bit automatically returns to 0 because it is a
trigger bit.
TE0n = 1, and count operation starts.
TCR0n is cleared to 0000H at the count clock input.
When the MD0n0 bit of the TMR0n register is 1,
INTTM0n is generated.
During
operation
Set values of only the CIS0n1 and CIS0n0 bits of the
TMR0n register can be changed.
The TDR0n register can always be read.
The TCR0n register can always be read.
The TSR0n register can always be read.
Set values of the TOM0n, TOL0n, TO0n, and TOE0n bits
cannot be changed.
Counter (TCRn) counts up from 0000H. When the TI0n
pin input valid edge is detected, the count value is
transferred (captured) to TDR0n. At the same time,
TCR0n is cleared to 0000H, and the INTTM0n signal is
generated.
If an overflow occurs at this time, the OVF bit of the
TSR0n register is set; if an overflow does not occur, the
OVF bit is cleared.
After that, the above operation is repeated.
Operation
stop
The TT0n bit is set to 1.
The TT0n bit automatically returns to 0 because it is a
trigger bit.
TE0n = 0, and count operation stops.
TCR0n holds count value and stops.
The OVF bit of the TSR0n register is also held.
TAU stop The TAU0EN bit of the PER0 register is cleared to 0. Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark n = 0 to 7
Operation is resumed.
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7.7.5 Operation as input signal high-/low-level width measurement
By starting counting at one edge of TI0n and capturing the number of counts at another edge, the signal width
(high-level width/low-level width) of TI0n can be measured. The signal width of TI0n can be calculated by the
following expression.
Signal width of TI0n input = Period of count clock × ((10000H × TSRn: OVF) + (Capture value of TDR0n + 1))
Caution The TI0n pin input is sampled using the operating clock selected with the CKS0n bit of the
TMR0n register, so an error equal to the number of operating clocks occurs.
TCR0n operates as an up counter in the capture & one-count mode.
When the channel start trigger (TS0n) is set to 1, TE0n is set to 1 and the TI0n pin start edge detection wait status
is set.
When the TI0n start valid edge (rising edge of TI0n when the high-level width is to be measured) is detected, the
counter counts up in synchronization with the count clock. When the valid capture edge (falling edge of TI0n when the
high-level width is to be measured) is detected later, the count value is transferred to TDR0n and, at the same time,
INTTM0n is output. If the counter overflows at this time, the OVF bit of the TSR0n register is set to 1. If the counter
does not overflow, the OVF bit is cleared. TCR0n stops at the value “value transferred to TDR0n + 1”, and the TI0n
pin start edge detection wait status is set. After that, the above operation is repeated.
As soon as the count value has been captured to the TDR0n register, the OVF bit of the TSR0n register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF
bit of the TSR0n register is set to 1. However, the OVF bit is configured as an integral flag, and the correct interval
value cannot be measured if an overflow occurs more than once.
Whether the high-level width or low-level width of the TI0n pin is to be measured can be selected by using the
CIS0n1 and CIS0n0 bits of the TMR0n register.
Because this function is used to measure the signal width of the TI0n pin input, TS0n cannot be set to 1 while TE0n
is 1.
CIS0n1, CIS0n0 of TMR0n = 10B: Low-level width is measured.
CIS0n1, CIS0n0 of TMR0n = 11B: High-level width is measured.
Figure 7-51. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement
Timer counter
(TCR0n)
Interrupt signal
(INTTM0n)
Data register
(TDR0n) Interrupt
controller
Clock selection
Trigger selection
Operation clock
CK00
CK01
Edge
detection
TI0n pin
Remark n = 0 to 7
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Figure 7-52. Example of Basic Timing of Operation as Input Signal High-/Low-Level Width Measurement
TS0n
TE0n
TI0n
TDR0n
TCR0n
b
0000H
a
c
INTTM0n
FFFFH
b
ac
OVF
0000H
Remark n = 0 to 7
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Figure 7-53. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width
(a) Timer mode register 0n (TMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS0n
1/0
0
0
CCS0n
0
MAS
TER0n
0
STS0n2
0
STS0n1
1
STS0n0
0
CIS0n1
1
CIS0n0
1/0
0
0
MD0n3
1
MD0n2
1
MD0n1
0
MD0n0
0
Operation mode of channel n
110B: Capture & one-count
Setting of operation when counting is started
0: Does not generate INTTM0n when
counting is started.
Selection of TI0n pin input edge
10B: Both edges (to measure low-level width)
11B: Both edges (to measure high-level width)
Start trigger selection
010B: Selects the TI0n pin input valid edge.
Slave/master selection
0: Cleared to 0 when single-operation function is selected.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CK00 as operation clock of channel n.
1: Selects CK01 as operation clock of channel n.
(b) Timer output register 0 (TO0)
Bit n
TO0 TO0n
0
0: Outputs 0 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE0n
0
0: Stops the TO0n output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL0n
0
0: Cleared to 0 when TOM0n = 0 (toggle mode).
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM0n
0
0: Sets toggle mode.
Remark n = 0 to 7
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Figure 7-54. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of the PER0 register to 1. Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets the TPS0 register.
Determines clock frequencies of CK00 and CK01.
Channel
default
setting
Sets the TMR0n register (determines operation mode of
channel).
Clears TOE0n to 0 and stops operation of TO0n.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Sets the TS0n bit to 1.
The TS0n bit automatically returns to 0 because it is a
trigger bit.
TE0n = 1, and the TI0n pin start edge detection wait
status is set.
Operation
start
Detects TI0n pin input count start valid edge. Clears TCR0n to 0000H and starts counting up.
During
operation
Set value of the TDR0n register can be changed.
The TCR0n register can always be read.
The TSR0n register is not used.
Set values of the TMR0n register, TOM0n, TOL0n, TO0n,
and TOE0n bits cannot be changed.
When the TI0n pin start edge is detected, the counter
(TCRn) counts up from 0000H. If a capture edge of the
TI0n pin is detected, the count value is transferred to
TDR0n and INTTM0n is generated.
If an overflow occurs at this time, the OVF bit of the
TSR0n register is set; if an overflow does not occur, the
OVF bit is cleared. TCR0n stops the count operation until
the next TI0n pin start edge is detected.
Operation
stop
The TT0n bit is set to 1.
TT0n bit automatically returns to 0 because it is a
trigger bit.
TE0n = 0, and count operation stops.
TCR0n holds count value and stops.
The OVF bit of the TSR0n register is also held.
TAU stop The TAU0EN bit of PER0 register is cleared to 0. Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark n = 0 to 7
Operation is resumed.
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7.8 Operation of Plural Channels of Timer Array Unit
7.8.1 Operation as PWM function
Two channels can be used as a set to generate a pulse of any period and duty factor.
The period and duty factor of the output pulse can be calculated by the following expressions.
Pulse period = {Set value of TDR0n (master) + 1} × Count clock period
Duty factor [%] = {Set value of TDR0m (slave)}/{Set value of TDR0n (master) + 1} × 100
0% output: Set value of TDR0m (slave) = 0000H
100% output: Set value of TDR0m (slave) ≥ {Set value of TDR0n (master) + 1}
Remark The duty factor exceeds 100% if the set value of TDR0m (slave) > (set value of TDR0n (master) + 1),
it summarizes to 100% output.
The master channel operates in the interval timer mode and counts the periods. When the channel start trigger
(TS0m) is set to 1, INTTM0n is output. TCR0n counts down starting from the loaded value of TDR0n, in
synchronization with the count clock. When TCR0n = 0000H, INTTM0n is output. TCR0n loads the value of TDR0n
again. After that, it continues the similar operation.
TCR0m of a slave channel operates in one-count mode, counts the duty factor, and outputs a PWM waveform from
the TO0m pin. TCR0m of the slave channel loads the value of TDR0m, using INTTM0n of the master channel as a
start trigger, and stops counting until the next start trigger (INTTM0n of the master channel) is input.
The output level of TO0m becomes active one count clock after generation of INTTM0n from the master channel,
and inactive when TCR0m = 0000H.
Caution To rewrite both TDR0n of the master channel and TDR0m of the slave channel, a write access is
necessary two times. The timing at which the values of TDR0n and TDR0m are loaded to TCR0n
and TRC0m is upon occurrence of INTTM0n of the master channel. Thus, when rewriting is
performed split before and after occurrence of INTTM0n of the master channel, the TO0m pin
cannot output the expected waveform. To rewrite both TDR0n of the master and TDR0m of the
slave, therefore, be sure to rewrite both the registers immediately after INTTM0n is generated
from the master channel.
Remark n = 0, 2, 4, 6
m = n + 1
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Figure 7-55. Block Diagram of Operation as PWM Function
Timer counter
(TCR0n)
Interrupt signal
(INTTM0n)
Data register
(TDR0n) Interrupt
controller
Clock selection
Trigger selection
Operation clock
CK00
CK01
TS0n
Timer counter
(TCR0m)
Interrupt signal
(INTTM0m)
Data register
(TDR0m) Interrupt
controller
Clock selection
Trigger selection
Operation clock
CK00
CK01
TO0m pin
Output
controller
Master channel
(interval timer mode)
Slave channel
(one-count mode)
Remark n = 0, 2, 4, 6
m = n + 1
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Figure 7-56. Example of Basic Timing of Operation as PWM Function
TS0n
TE0n
TDR0n
TCR0n
TO0n
INTTM0n
a b
0000H
TS0m
TE0m
TDR0m
TCR0m
TO0m
INTTM0m
c
c
d
0000H
cd
Master
channel
Slave
channel
a+1 a+1 b+1
FFFFH
FFFFH
Remark n = 0, 2, 4, 6
m = n + 1
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Figure 7-57. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used
(a) Timer mode register 0n (TMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS0n
1/0
0
0
CCS0n
0
MAS
TER0n
1
STS0n2
0
STS0n1
0
STS0n0
0
CIS0n1
0
CIS0n0
0
0
0
MD0n3
0
MD0n2
0
MD0n1
0
MD0n0
1
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
1: Generates INTTM0n when counting is
started.
Selection of TI0n pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Slave/master selection
1: Channel 1 is set as master channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CK00 as operation clock of channel n.
1: Selects CK01 as operation clock of channel n.
(b) Timer output register 0 (TO0)
Bit n
TO0 TO0n
0
0: Outputs 0 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE0n
0
0: Stops the TO0n output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL0n
0
0: Cleared to 0 when TOM0n = 0 (toggle mode).
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM0n
0
0: Sets toggle mode.
Remark n = 0, 2, 4, 6
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Figure 7-58. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used
(a) Timer mode register 0m (TMR0m)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0m CKS0m
1/0
0
0
CCS0m
0
MAS
TER0m
0
STS0m2
1
STS0m1
0
STS0m0
0
CIS0m1
0
CIS0m0
0
0
0
MD0m3
1
MD0m2
0
MD0m1
0
MD0m0
1
Operation mode of channel m
100B: One-count mode
Start trigger during operation
1: Trigger input is valid.
Selection of TI0m pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTM0n of master channel.
Slave/master selection
0: Channel 0 is set as slave channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CK00 as operation clock of channel m.
1: Selects CK01 as operation clock of channel m.
* Make the same setting as master channel.
(b) Timer output register 0 (TO0)
Bit m
TO0 TO0m
1/0
0: Outputs 0 from TO0m.
1: Outputs 1 from TO0m.
(c) Timer output enable register 0 (TOE0)
Bit m
TOE0 TOE0m
1/0
0: Stops the TO0m output operation by counting operation.
1: Enables the TO0m output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit m
TOL0 TOL0m
1/0
0: Positive logic output (active-high)
1: Inverted output (active-low)
(e) Timer output mode register 0 (TOM0)
Bit m
TOM0 TOM0m
1
1: Sets the combination operation mode.
Remark n = 0, 2, 4, 6
m = n + 1
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Figure 7-59. Operation Procedure When PWM Function Is Used (1/2)
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of the PER0 register to 1. Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets the TPS0 register.
Determines clock frequencies of CK00 and CK01.
Sets the TMR0n and TMR0m registers of two channels
to be used (determines operation mode of channels).
An interval (period) value is set to the TDR0n register of
the master channel, and a duty factor is set to the
TDR0m register of the slave channel.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Channel
default
setting
Sets slave channel.
The TOM0m bit of the TOM0 register is set to 1
(combination operation mode).
Sets the TOL0mbit.
Sets the TO0m bit and determines default level of the
TO0m output.
Sets TOE0m to 1 and enables operation of TO0m.
Clears the port register and port mode register to 0.
The TO0m pin goes into Hi-Z output state.
The TO0m default setting level is output when the port
mode register is in output mode and the port register is 0.
TO0m does not change because channel stops operating.
The TO0m pin outputs the TO0m set level.
Remark n = 0, 2, 4, 6
m = n + 1
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Figure 7-59. Operation Procedure When PWM Function Is Used (2/2)
Software Operation Hardware Status
Operation
start
Sets TOE0m (slave) to 1 (only when operation is
resumed).
The TS0n (master) and TS0m (slave) bits of the TS0
register are set to 1 at the same time.
The TS0n and TS0m bits automatically return to 0
because they are trigger bits.
TE0n = 1, TE0m = 1
When the master channel starts counting, INTTM0n is
generated. Triggered by this interrupt, the slave
channel also starts counting.
During
operation
Set values of the TMR0n and TMR0m registers, TOM0n,
TOM0m, TOL0n, and TOL0m bits cannot be changed.
Set values of the TDR0n and TDR0m registers can be
changed after INTTM0n of the master channel is
generated.
The TCR0n and TCR0m registers can always be read.
The TSR0n and TSR0m registers are not used.
Set values of the TO0 and TOE0 registers can be
changed.
The counter of the master channel loads the TDR0n value
to TCR0n, and counts down. When the count value
reaches TCR0n = 0000H, INTTM0n output is generated.
At the same time, the value of the TDR0n register is
loaded to TCR0n, and the counter starts counting down
again.
At the slave channel, the value of TDR0m is loaded to
TCR0m, triggered by INTTM0n of the master channel, and
the counter starts counting down. The output level of
TO0m becomes active one count clock after generation of
the INTTM0n output from the master channel. It becomes
inactive when TCR0m = 0000H, and the counting
operation is stopped.
After that, the above operation is repeated.
The TT0n (master) and TT0m (slave) bits are set to 1 at
the same time.
The TT0n and TT0m bits automatically return to 0
because they are trigger bits.
TE0n, TE0m = 0, and count operation stops.
TCR0n and TCR0m hold count value and stops.
The TO0m output is not initialized but holds current
status.
Operation
stop
TOE0m of slave channel is cleared to 0 and value is set
to the TO0m bit.
The TO0m pin outputs the TO0m set level.
To hold the TO0m pin output levels
Clears the TO0m bit to 0 after the value
to be held is set to the port register.
When holding the TO0m pin output level is not
necessary
Switches the port mode register to input mode.
The TO0m pin output level is held by port function.
The TO0m pin output level goes into Hi-Z output state.
TAU stop
The TAU0EN bit of the PER0 register is cleared to 0. Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TO0m bit is cleared to 0 and the TO0m pin is set
to port mode.)
Remark n = 0, 2, 4, 6
m = n + 1
Operation is resumed.
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7.8.2 Operation as one-shot pulse output function
By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal
input to the TI0n pin.
The delay time and pulse width can be calculated by the following expressions.
Delay time = {Set value of TDR0n (master) + 2} × Count clock period
Pulse width = {Set value of TDR0m (slave)} × Count clock period
The Master channel operates in the one-count mode and counts the delays. TCR0n of the master channel starts
operating upon start trigger detection and TCR0n loads the value of TDR0n. TCR0n counts down from the value of
TDR0n it has loaded, in synchronization with the count clock. When TCR0n = 0000H, it outputs INTTM0n and stops
counting until the next start trigger is detected.
The slave channel operates in the one-count mode and counts the pulse width. TCR0m of the slave channel starts
operation using INTTM0n of the master channel as a start trigger, and loads the TDR0m value. TCR0m counts down
from the value of TDR0m it has loaded, in synchronization with the count value. When TCR0m = 0000H, it outputs
INTTM0m and stops counting until the next start trigger (INTTM0n of the master channel) is detected. The output
level of TO0m becomes active one count clock after generation of INTTM0n from the master channel, and inactive
when TCR0m = 0000H.
Instead of using the TI0n pin input, a one-shot pulse can also be output using the software operation (TS0n = 1) as
a start trigger.
Caution The timing of loading of TDR0n of the master channel is different from that of TDR0m of the slave
channel. If TDR0n and TDR0m are rewritten during operation, therefore, an illegal waveform is
output. Rewrite the TDR0n after INTTM0n is generated and the TDR0m after INTTM0m is
generated.
Remark n = 0, 2, 4, 6
m = n + 1
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Figure 7-60. Block Diagram of Operation as One-Shot Pulse Output Function
Timer counter
(TCR0n)
Interrupt signal
(INTTM0n)
Data register
(TDR0n) Interrupt
controller
Clock selection
Trigger selection
Operation clock
CK00
CK01
TS0n
Timer counter
(TCR0m)
Interrupt signal
(INTTM0m)
Data register
(TDR0m) Interrupt
controller
Clock selection
Trigger selection
Operation clock
CK00
CK01
TO0m pin
Output
controller
Master channel
(one-count mode)
Slave channel
(one-count mode)
Edge
detection
TI0n pin
Remark n = 0, 2, 4, 6
m = n + 1
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Figure 7-61. Example of Basic Timing of Operation as One-Shot Pulse Output Function
TE0n
TDR0n
TCR0n
TO0n
INTTM0n
a
b
0000H
TS0m
TE0m
TDR0m
TCR0m
TO0m
INTTM0m
0000H
b
Master
channel
Slave
channel
a + 2 b
a + 2
FFFFH
FFFFH
TI0n
TS0n
Remark n = 0, 2, 4, 6
m = n + 1
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Figure 7-62. Example of Set Contents of Registers
When One-Shot Pulse Output Function Is Used (Master Channel)
(a) Timer mode register 0n (TMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS0n
1/0
0
0
CCS0n
0
MAS
TER0n
1
STS0n2
0
STS0n1
0
STS0n0
1
CIS0n1
1/0
CIS0n0
1/0
0
0
MD0n3
1
MD0n2
0
MD0n1
0
MD0n0
0
Operation mode of channel n
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
Selection of TI0n pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
001B: Selects the TI0n pin input valid edge.
Slave/master selection
1: Channel 1 is set as master channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CK00 as operation clock of channels n.
1: Selects CK01 as operation clock of channels n.
(b) Timer output register 0 (TO0)
Bit n
TO0 TO0n
0
0: Outputs 0 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE0n
0
0: Stops the TO0n output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL0n
0
0: Cleared to 0 when TOM0n = 0 (toggle mode).
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM0n
0
0: Sets toggle mode.
Remark n = 0, 2, 4, 6
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Figure 7-63. Example of Set Contents of Registers
When One-Shot Pulse Output Function Is Used (Slave Channel)
(a) Timer mode register 0m (TMR0m)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0m CKS0m
1/0
0
0
CCS0m
0
MAS
TER0m
0
STS0m2
1
STS0m1
0
STS0m0
0
CIS0m1
0
CIS0m0
0
0
0
MD0m3
1
MD0m2
0
MD0m1
0
MD0m0
0
Operation mode of channel m
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
Selection of TI0m pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTM0n of master channel.
Slave/master selection
0: Channel 0 is set as slave channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CK00 as operation clock of channel m.
1: Selects CK01 as operation clock of channel m.
* Make the same setting as master channel.
(b) Timer output register 0 (TO0)
Bit m
TO0 TO0m
1/0
0: Outputs 0 from TO0m.
1: Outputs 1 from TO0m.
(c) Timer output enable register 0 (TOE0)
Bit m
TOE0 TOE0m
1/0
0: Stops the TO0m output operation by counting operation.
1: Enables the TO0m output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit m
TOL0 TOL0m
1/0
0: Positive logic output (active-high)
1: Inverted output (active-low)
(e) Timer output mode register 0 (TOM0)
Bit m
TOM0 TOM0m
1
1: Sets the combination operation mode.
Remark n = 0, 2, 4, 6
m = n + 1
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Figure 7-64. Operation Procedure of One-Shot Pulse Output Function (1/2)
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of the PER0 register to 1. Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets the TPS0 register.
Determines clock frequencies of CK00 and CK01.
Sets the TMR0n and TMR0m registers of two channels
to be used (determines operation mode of channels).
An output delay is set to the TDR0n register of the
master channel, and a pulse width is set to the TDR0m
register of the slave channel.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Channel
default
setting
Sets slave channel.
The TOM0m bit of the TOM0 register is set to 1
(combination operation mode).
Sets the TOL0m bit.
Sets the TO0m bit and determines default level of the
TO0m output.
Sets TOE0m to 1 and enables operation of TO0m.
Clears the port register and port mode register to 0.
The TO0m pin goes into Hi-Z output state.
The TO0m default setting level is output when the port
mode register is in output mode and the port register is 0.
TO0m does not change because channel stops operating.
The TO0m pin outputs the TO0m set level.
Remark n = 0, 2, 4, 6
m = n + 1
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Figure 7-64. Operation Procedure of One-Shot Pulse Output Function (2/2)
Software Operation Hardware Status
Sets TOE0m (slave) to 1 (only when operation is
resumed).
The TS0n (master) and TS0m (slave) bits of the TS0
register are set to 1 at the same time.
The TS0n and TS0m bits automatically return to 0
because they are trigger bits.
TE0n and TE0m are set to 1 and the master channel
enters the TI0n input edge detection wait status.
Counter stops operating.
Operation
start
Detects the TI0n pin input valid edge of master channel. Master channel starts counting.
During
operation
Set values of only the CIS0n1 and CIS0n0 bits of the
TMR0n register can be changed.
Set values of the TMR0m, TDR0n, TDR0m registers,
TOM0n, TOM0m, TOL0n, and TOL0m bits cannot be
changed.
The TCR0n and TCR0m registers can always be read.
The TSR0n and TSR0m registers are not used.
Set values of the TO0 and TOE0 registers can be
changed.
Master channel loads the value of TDR0n to TCR0n when
the TI0n pin valid input edge is detected, and the counter
starts counting down. When the count value reaches
TCR0n = 0000H, the INTTM0n output is generated, and
the counter stops until the next valid edge is input to the
TI0n pin.
The slave channel, triggered by INTTM0n of the master
channel, loads the value of TDR0m to TCR0m, and the
counter starts counting down. The output level of TO0m
becomes active one count clock after generation of
INTTM0n from the master channel. It becomes inactive
when TCR0m = 0000H, and the counting operation is
stopped.
After that, the above operation is repeated.
The TT0n (master) and TT0m (slave) bits are set to 1 at
the same time.
The TT0n and TT0m bits automatically return to 0
because they are trigger bits.
TE0n, TE0m = 0, and count operation stops.
TCR0n and TCR0m hold count value and stops.
The TO0m output is not initialized but holds current
status.
Operation
stop
TOE0m of slave channel is cleared to 0 and value is set
to the TO0m bit.
The TO0m pin outputs the TO0m set level.
To hold the TO0m pin output levels
Clears the TO0m bit to 0 after the value
to be held is set to the port register.
When holding the TO0m pin output level is not
necessary
Switches the port mode register to input mode.
The TO0m pin output level is held by port function.
The TO0m pin output level goes into Hi-Z output state.
TAU stop
The TAU0EN bit of the PER0 register is cleared to 0. Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TO0m bit is cleared to 0 and the TO0m pin is set to
port mode.)
Remark n = 0, 2, 4, 6
m = n + 1
Operation is resumed.
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7.8.3 Operation as multiple PWM output function
By extending the PWM function and using two or more slave channels, many PWM output signals can be produced.
For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by
the following expressions.
Pulse period = {Set value of TDR0n (master) + 1} × Count clock period
Duty factor 1 [%] = {Set value of TDR0m (slave 1)}/{Set value of TDR0n (master) + 1} × 100
Duty factor 2 [%] = {Set value of TDR0m (slave 2)}/{Set value of TDR0n (master) + 1} × 100
Remark Although the duty factor exceeds 100% if the set value of TDR0p (slave 1) > {set value of TDR0n
(master) + 1} or if the {set value of TDR0q (slave 2)} > {set value of TDR0n (master) + 1}, it is
summarized into 100% output.
TCR0n of the master channel operates in the interval timer mode and counts the periods.
TCR0p of the slave channel 1 operates in one-count mode, counts the duty factor, and outputs a PWM waveform
from the TO0p pin. TCR0p loads the value of TDR0p to TCR0p, using INTTM0n of the master channel as a start
trigger, and start counting down. When TCR0p = 0000H, TCR0p outputs INTTM0p and stops counting until the next
start trigger (INTTM0n of the master channel) has been input. The output level of TO0p becomes active one count
clock after generation of INTTM0n from the master channel, and inactive when TCR0p = 0000H.
In the same way as TCR0p of the slave channel 1, TCR0q of the slave channel 2 operates in one-count mode,
counts the duty factor, and outputs a PWM waveform from the TO0q pin. TCR0q loads the value of TDR0q to TCR0q,
using INTTM0n of the master channel as a start trigger, and starts counting down. When TCR0q = 0000H, TCR0q
outputs INTTM0q and stops counting until the next start trigger (INTTM0n of the master channel) has been input. The
output level of TO0q becomes active one count clock after generation of INTTM0n from the master channel, and
inactive when TCR0q = 0000H.
When channel 0 is used as the master channel as above, up to seven types of PWM signals can be output at the
same time.
Caution To rewrite both TDR0n of the master channel and TDR0p of the slave channel 1, write access is
necessary at least twice. Since the values of TDR0n and TDR0p are loaded to TCR0n and TCR0p
after INTTM0n is generated from the master channel, if rewriting is performed separately before
and after generation of INTTM0n from the master channel, the TO0p pin cannot output the
expected waveform. To rewrite both TDR0n of the master and TDR0p of the slave, be sure to
rewrite both the registers immediately after INTTM0n is generated from the master channel (This
applies also to TDR0q of the slave channel 2) .
Remarks 1. n = 0, 2, 4
n < p < q ≤ 7
Where p and q are consecutive integers following n (p = n + 1, q = n + 2)
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Figure 7-65. Block Diagram of Operation as Multiple PWM Output Function (Output Two Types of PWMs)
Timer counter
(TCR0n)
Interrupt signal
(INTTM0n)
Data register
(TDR0n) Interrupt
controller
Clock selection
Trigger selection
Operation clock
CK00
CK01
TS0n
Timer counter
(TCR0p)
Interrupt signal
(INTTM0p)
Data register
(TDR0p) Interrupt
controller
Clock selection
Trigger selection
Operation clock
CK00
CK01
TO0p pin
Output
controller
Master channel
(interval timer mode)
Slave channel 1
(one-count mode)
Timer counter
(TCR0q)
Interrupt signal
(INTTM0q)
Data register
(TDR0q) Interrupt
controller
Clock selection
Trigger selection
Operation clock
CK00
CK01
TO0q pin
Output
controller
Slave channel 2
(one-count mode)
Remarks 1. n = 0, 2, 4
2. p = n + 1
q = n + 2
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Figure 7-66. Example of Basic Timing of Operation as Multiple PWM Output Function (Output Two Types of PWMs)
TS0n
TE0n
TDR0n
TCR0n
TO0n
INTTM0n
a b
0000H
TS0p
TE0p
TDR0p
TCR0p
TO0p
INTTM0p
c
c
d
0000H
cd
Master
channel
Slave
channel 1
a + 1 a + 1 b + 1
FFFFH
FFFFH
TS0q
TE0q
TDR0q
TCR0q
TO0q
INTTM0q
ef
0000H
ef
Slave
channel 2
a + 1 a + 1 b + 1
FFFFH
ef
d
Remarks 1. n = 0, 2, 4
2. p = n + 1
q = n + 2
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Figure 7-67. Example of Set Contents of Registers
When Multiple PWM Output Function (Master Channel) Is Used
(a) Timer mode register 0n (TMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS0n
1/0
0
0
CCS0n
0
MAS
TER0n
1
STS0n2
0
STS0n1
0
STS0n0
0
CIS0n1
0
CIS0n0
0
0
0
MD0n3
0
MD0n2
0
MD0n1
0
MD0n0
1
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
1: Generates INTTM0n when counting is
started.
Selection of TI0n pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Slave/master selection
1: Channel 1 is set as master channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CK00 as operation clock of channel n.
1: Selects CK01 as operation clock of channel n.
(b) Timer output register 0 (TO0)
Bit n
TO0 TO0n
0
0: Outputs 0 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE0n
0
0: Stops the TO0n output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL0n
0
0: Cleared to 0 when TOM0n = 0 (toggle mode).
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM0n
0
0: Sets toggle mode.
Remark n = 0, 2, 4
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Figure 7-68. Example of Set Contents of Registers
When Multiple PWM Output Function (Slave Channel) Is Used (Output Two Types of PWMs)
(a) Timer mode registers 0p, 0q (TMR0p, TMR0q)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0p CKS0p
1/0
0
0
CCS0p
0
MAS
TER0p
0
STS0p2
1
STS0p1
0
STS0p0
0
CIS0p1
0
CIS0p0
0
0
0
MD0p3
1
MD0p2
0
MD0p1
0
MD0p0
1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0q CKS0q
1/0
0
0
CCS0q
0
MAS
TER0q
0
STS0q2
1
STS0q1
0
STS0q0
0
CIS0q1
0
CIS0q0
0
0
0
MD0q3
1
MD0q2
0
MD0q1
0
MD0q0
1
Operation mode of channel p, q
100B: One-count mode
Start trigger during operation
1: Trigger input is valid.
Selection of TI0p and TI0q pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTM0n of master channel.
Slave/master selection
0: Channel 0 is set as slave channel.
Count clock selection
0: Selects operation clock.
Operation clock selection
0: Selects CK00 as operation clock of channel p, q.
1: Selects CK01 as operation clock of channel p, q.
* Make the same setting as master channel.
(b) Timer output register 0 (TO0)
Bit q Bit p
TO0 TO0q
1/0
TO0p
1/0
0: Outputs 0 from TO0p or TO0q.
1: Outputs 1 from TO0p or TO0q.
(c) Timer output enable register 0 (TOE0)
Bit q Bit p
TOE0 TOE0q
1/0
TOE0p
1/0
0: Stops the TO0p or TO0q output operation by counting operation.
1: Enables the TO0p or TO0q output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit q Bit p
TOL0 TOL0q
1/0
TOL0p
1/0
0: Positive logic output (active-high)
1: Inverted output (active-low)
(e) Timer output mode register 0 (TOM0)
Bit q Bit p
TOM0 TOM0q
1
TOM0p
1
1: Sets the combination operation mode.
Remark n = 0, 2, 4; p = n + 1; q = n + 2
CHAPTER 7 TIMER ARRAY UNIT
User’s Manual U17894EJ9V0UD 307
Figure 7-69. Operation Procedure When Multiple PWM Output Function Is Used (1/2)
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of the PER0 register to 1. Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets the TPS0 register.
Determines clock frequencies of CK00 and CK01.
Sets the TMR0n, TMR0p, and TMR0q registers of each
channel to be used (determines operation mode of
channels).
An interval (period) value is set to the TDR0n register of
the master channel, and a duty factor is set to the
TDR0p and TDR0q registers of the slave channel.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Channel
default
setting
Sets slave channel.
The TOM0p and TOM0q bits of the TOM0 register are
set to 1 (combination operation mode).
Clears the TOL0p and TOL0q bits to 0.
Sets the TO0p and TO0q bits and determines default
level of the TO0p and TO0q outputs.
Sets TOE0p or TOE0q to 1 and enables operation of
TO0p or TO0q.
Clears the port register and port mode register to 0.
The TO0p and TO0q pins go into Hi-Z output state.
The TO0p and TO0q default setting levels are output when
the port mode register is in output mode and the port
register is 0.
TO0p or TO0q does not change because channel stops
operating.
The TO0p and TO0q pins output the TO0p and TO0q set
levels.
Remarks 1. n = 0, 2, 4
2. p = n + 1; q = n + 2
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Figure 7-69. Operation Procedure When Multiple PWM Output Function Is Used (2/2)
Software Operation Hardware Status
Operation
start
Sets TOE0p and TOE0q (slave) to 1 (only when
operation is resumed).
The TS0n bit (master), and TS0p and TS0q (slave) bits of
the TS0 register are set to 1 at the same time.
The TS0n, TS0p, and TS0q bits automatically return to
0 because they are trigger bits.
TE0n = 1, TE0p, TE0q = 1
When the master channel starts counting, INTTM0n is
generated. Triggered by this interrupt, the slave
channel also starts counting.
During
operation
Set values of the TMR0n, TMR0p, TMR0q registers,
TOM0n, TOM0p, TOM0q, TOL0n, TOL0p, and TOL0q
bits cannot be changed.
Set values of the TDR0n, TDR0p, and TDR0q registers
can be changed after INTTM0n of the master channel is
generated.
The TCR0n, TCR0p, and TCR0q registers can always be
read.
The TSR0n, TSR0p, and TSR0q registers are not used.
Set values of the TO0 and TOE0 registers can be
changed.
The counter of the master channel loads the TDR0n value
to TCR0n and counts down. When the count value
reaches TCRn = 0000H, INTTM0n output is generated. At
the same time, the value of the TDR0n register is loaded to
TCR0n, and the counter starts counting down again.
At the slave channel 1, the values of TDR0p are transferred
to TCR0p, triggered by INTTM0n of the master channel,
and the counter starts counting down. The output levels of
TO0p become active one count clock after generation of
the INTTM0n output from the master channel. It becomes
inactive when TCR0p = 0000H, and the counting operation
is stopped.
At the slave channel 2, the values of TDR0q are transferred
to TDR0q, triggered by INTTM0n of the master channel,
and the counter starts counting down. The output levels of
TO0q become active one count clock after generation of
the INTTM0n output from the master channel. It becomes
inactive when TCR0q = 0000H, and the counting operation
is stopped.
After that, the above operation is repeated.
The TT0n bit (master), TT0p, and TT0q (slave) bits are
set to 1 at the same time.
The TT0n, TT0p, and TT0q bits automatically return to
0 because they are trigger bits.
TE0n, TE0p = 0, TE0q = 0, and count operation stops.
TCR0n, TCR0p, and TCR0q hold count value and stops.
The TO0p and TO0q outputs are not initialized but holds
current status.
Operation
stop
TOE0p or TOE0q of slave channel is cleared to 0
and value is set to the TO0p and TO0q bits.
The TO0p and TO0q pins output the TO0p and TO0q set
levels.
To hold the TO0p and TO0q pin output levels
Clears TO0p and TO0q bits to 0 after
the value to be held is set to the port register.
When holding the TO0p and TO0q pin output level is not
necessary
Switches the port mode register to input mode.
The TO0p and TO0q pin output levels are held by port
function.
The TO0p and TO0q pin output levels go into Hi-Z output
state.
TAU stop
The TAU0EN bit of the PER0 register is cleared to 0. Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TO0p and TO0q bits are cleared to 0 and the
TO0p and TO0q pins are set to port mode.)
Remarks 1. n = 0, 2, 4
2. p = n + 1; q = n + 2
Operation is resumed.
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CHAPTER 8 REAL-TIME COUNTER
8.1 Functions of Real-Time Counter
The real-time counter has the following features.
• Having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years.
• Constant-period interrupt function (period: 1 month to 0.5 seconds)
• Alarm interrupt function (alarm: week, hour, minute)
• Interval interrupt function
• Pin output function of 1 Hz
• Pin output function of 512 Hz or 16.384 kHz or 32.768 kHz
8.2 Configuration of Real-Time Counter
The real-time counter includes the following hardware.
Table 8-1. Configuration of Real-Time Counter
Item Configuration
Control registers Peripheral enable register 0 (PER0)
Real-time counter control register 0 (RTCC0)
Real-time counter control register 1 (RTCC1)
Real-time counter control register 2 (RTCC2)
Sub-count register (RSUBC)
Second count register (SEC)
Minute count register (MIN)
Hour count register (HOUR)
Day count register (DAY)
Week count register (WEEK)
Month count register (MONTH)
Year count register (YEAR)
Watch error correction register (SUBCUD)
Alarm minute register (ALARMWM)
Alarm hour register (ALARMWH)
Alarm week register (ALARMWW)
Port mode registers 1 and 3 (PM1, PM3)
Port registers 1 and 3 (P1, P3)
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Figure 8-1. Block Diagram of Real-Time Counter
INTRTC
f
SUB
RTCE
RCLOE1 RCLOE0
AMPM CT2 CT1 CT0
RINTE RCLOE2 ICT2 ICT1 ICT0
RTCE
AMPM
CT0 to CT2
RCKDIV
f
SUB
RTC1HZ/
INTP3/P30
RCKDIV
RINTE
RTCDIV/RTCCL/P15
INTRTCI
RCLOE2
f
SUB
RWAIT
WALE WALIE WAFG RWAIT
RWST
RIFG
RWST
RIFG
12-bit counter
Real-time counter control register 1 Real-time counter control register 0
Alarm week
register
(ALARMWW)
(7-bit)
Alarm hour
register
(ALARMWH)
(6-bit)
Alarm minute
register
(ALARMWM)
(7-bit)
Year count
register
(YEAR)
(8-bit)
Month count
register
(MONTH)
(5-bit)
Week count
register
(WEEK)
(3-bit)
Day count
register
(DAY)
(6-bit)
Hour count
register
(HOUR)
(6-bit)
Minute count
register
(MIN)
(7-bit)
Second
count
register
(SEC)
(7-bit)
Wait control
0.5
seconds
Sub-count
register
(RSUBC)
(16-bit)
Count clock
= 32.768 kHz
Selector
Buffer Buffer Buffer Buffer Buffer Buffer Buffer
Count enable/
disable circuit
Watch error
correction
register
(SUBCUD)
(8-bit)
Selector
Selector
Internal bus
Real-time counter control register 2
1 month 1 day 1 hour 1 minute
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User’s Manual U17894EJ9V0UD 311
8.3 Registers Controlling Real-Time Counter
The real-time counter is controlled by the following 18 registers.
• Peripheral enable register 0 (PER0)
• Real-time counter control register 0 (RTCC0)
• Real-time counter control register 1 (RTCC1)
• Real-time counter control register 2 (RTCC2)
• Sub-count register (RSUBC)
• Second count register (SEC)
• Minute count register (MIN)
• Hour count register (HOUR)
• Day count register (DAY)
• Week count register (WEEK)
• Month count register (MONTH)
• Year count register (YEAR)
• Watch error correction register (SUBCUD)
• Alarm minute register (ALARMWM)
• Alarm hour register (ALARMWH)
• Alarm week register (ALARMWW)
• Port mode registers 1, 3 (PM1, PM3)
• Port registers 1, 3 (P1, P3)
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(1) Peripheral enable register 0 (PER0)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro
that is not used is stopped in order to reduce the power consumption and noise.
When the real-time counter is used, be sure to set bit 7 (RTCEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> 1 <0>
PER0 RTCEN DACEN ADCEN IIC0EN SAU1EN SAU0EN 0 TAU0EN
RTCEN Control of real-time counter (RTC) input clock supplyNote
0 Stops supply of input clock.
• SFR used by the real-time counter (RTC) cannot be written.
• The real-time counter (RTC) is in the reset status.
1 Supplies input clock.
• SFR used by the real-time counter (RTC) can be read/written.
Note RTCEN is used to supply or stop the clock used when accessing the real-time counter (RTC)
register from the CPU. RTCEN cannot control supply of the operating clock (fSUB) to RTC.
Cautions 1. When using the real-time counter, first set RTCEN to 1, while oscillation of the
subsystem clock (fSUB) is stable. If RTCEN = 0, writing to a control register of the
real-time counter is ignored, and, even if the register is read, only the default
value is read.
2. Be sure to clear bit 1 of the PER0 register to 0.
(2) Real-time counter control register 0 (RTCC0)
The RTCC0 register is an 8-bit register that is used to start or stop the real-time counter operation, control the
RTCCL and RTC1HZ pins, and set a 12- or 24-hour system and the constant-period interrupt function.
RTCC0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
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Figure 8-3. Format of Real-Time Counter Control Register 0 (RTCC0)
Address: FFF9DH After reset: 00H R/W
Symbol <7> 6 <5> <4> 3 2 1 0
RTCC0 RTCE 0 RCLOE1 RCLOE0 AMPM CT2 CT1 CT0
RTCE Real-time counter operation control
0 Stops counter operation.
1 Starts counter operation.
RCLOE1 RTC1HZ pin output control
0 Disables output of RTC1HZ pin (1 Hz).
1 Enables output of RTC1HZ pin (1 Hz).
RCLOE0Note RTCCL pin output control
0 Disables output of RTCCL pin (32.768 kHz).
1 Enables output of RTCCL pin (32.768 kHz).
AMPM Selection of 12-/24-hour system
0 12-hour system (a.m. and p.m. are displayed.)
1 24-hour system
Rewrite the AMPM value after setting RWAIT (bit 0 of RTCC1) to 1. If the AMPM value is changed, the values of
the hour count register (HOUR) change according to the specified time system.
Table 8-2 shows the displayed time digits.
CT2 CT1 CT0 Constant-period interrupt (INTRTC) selection
0 0 0 Does not use constant-period interrupt function.
0 0 1 Once per 0.5 s (synchronized with second count up)
0 1 0 Once per 1 s (same time as second count up)
0 1 1 Once per 1 m (second 00 of every minute)
1 0 0 Once per 1 hour (minute 00 and second 00 of every hour)
1 0 1 Once per 1 day (hour 00, minute 00, and second 00 of every day)
1 1 × Once per 1 month (Day 1, hour 00 a.m., minute 00, and second 00 of
every month)
When changing the values of CT2 to CT0 while the counter operates (RTCE = 1), rewrite the values of CT2 to CT0
after disabling interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore, after rewriting the
values of CT2 to CT0, enable interrupt servicing after clearing the RIFG and RTCIF flags.
Note RCLOE0 and RCLOE2 must not be enabled at the same time.
Caution If RCLOE0 and RCLOE1 are changed when RTCE = 1, glitches may occur in the 32.768 kHz
and 1 Hz output signals.
Remark ×: don’t care
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(3) Real-time counter control register 1 (RTCC1)
The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of
the counter.
RTCC1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8-4. Format of Real-Time Counter Control Register 1 (RTCC1) (1/2)
Address: FFF9EH After reset: 00H R/W
Symbol <7> <6> 5 <4> <3> 2 <1> <0>
RTCC1 WALE WALIE 0 WAFG RIFG 0 RWST RWAIT
WALE Alarm operation control
0 Match operation is invalid.
1 Match operation is valid.
When setting a value to the WALE bit while the counter operates (RTCE = 1) and WALIE = 1, rewrite the WALE bit
after disabling interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore, clear the WAFG
and RTCIF flags after rewriting the WALE bit. When setting each alarm register (WALIE flag of RTCC1, the
ALARMWM register, the ALARMWH register, and the ALARMWW register), set match operation to be invalid (“0”)
for the WALE bit.
WALIE Control of alarm interrupt (INTRTC) function operation
0 Does not generate interrupt on matching of alarm.
1 Generates interrupt on matching of alarm.
WAFG Alarm detection status flag
0 Alarm mismatch
1 Detection of matching of alarm
This is a status flag that indicates detection of matching with the alarm. It is valid only when WALE = 1 and is set to
“1” one clock (32.768 kHz) after matching of the alarm is detected. This flag is cleared when “0” is written to it.
Writing “1” to it is invalid.
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Figure 8-4. Format of Real-Time Counter Control Register 1 (RTCC1) (2/2)
RIFG Constant-period interrupt status flag
0 Constant-period interrupt is not generated.
1 Constant-period interrupt is generated.
This flag indicates the status of generation of the constant-period interrupt. When the constant-period interrupt is
generated, it is set to “1”.
This flag is cleared when “0” is written to it. Writing “1” to it is invalid.
RWST Wait status flag of real-time counter
0 Counter is operating.
1 Mode to read or write counter value
This status flag indicates whether the setting of RWAIT is valid.
Before reading or writing the counter value, confirm that the value of this flag is 1.
Table 8-2 shows the displayed time digits.
RWAIT Wait control of real-time counter
0 Sets counter operation.
1 Stops SEC to YEAR counters. Mode to read or write counter value
This bit controls the operation of the counter.
Be sure to write “1” to it to read or write the counter value.
Because RSUBC continues operation, complete reading or writing of it in 1 second, and clear this bit back to 0.
When RWAIT = 1, it takes up to 1 clock (32.768 kHz) until the counter value can be read or written.
If RSUBC overflows when RWAIT = 1, it counts up after RWAIT = 0. If the second count register is written,
however, it does not count up because RSUBC is cleared.
Caution The RIFG and WAFG flags may be cleared when the RTCC1 register is written by using a 1-bit
manipulation instruction. Use, therefore, an 8-bit manipulation instruction in order to write to
the RTCC1 register. To prevent the RIFG and WAFG flags from being cleared during writing,
disable writing by setting “1” to the corresponding bit. When the value may be rewritten
because the RIFG and WAFG flags are not being used, the RTCC1 register may be written by
using a 1-bit manipulation instruction.
Remark Fixed-cycle interrupts and alarm match interrupts use the same interrupt source (INTRTC). When
using these two types of interrupts at the same time, which interrupt occurred can be judged by
checking the fixed-cycle interrupt status flag (RIFG) and the alarm detection status flag (WAFG)
upon INTRTC occurrence.
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(4) Real-time counter control register 2 (RTCC2)
The RTCC2 register is an 8-bit register that is used to control the interval interrupt function and the RTCDIV
pin.
RTCC2 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8-5. Format of Real-Time Counter Control Register 2 (RTCC2)
Address: FFF9FH After reset: 00H R/W
Symbol <7> <6> <5> 4 3 2 1 0
RTCC2 RINTE RCLOE2 RCKDIV 0 0 ICT2 ICT1 ICT0
RINTE ICT2 ICT1 ICT0 Interval interrupt (INTRTCI) selection
0 × × × Interval interrupt is not generated.
1 0 0 0 26/fXT (1.953125 ms)
1 0 0 1 27/fXT (3.90625 ms)
1 0 1 0 28/fXT (7.8125 ms)
1 0 1 1 29/fXT (15.625 ms)
1 1 0 0 210/fXT (31.25 ms)
1 1 0 1 211/fXT (62.5 ms)
1 1 1 × 212/fXT (125 ms)
RCLOE2Note RTCDIV pin output control
0 Output of RTCDIV pin is disabled.
1 Output of RTCDIV pin is enabled.
RCKDIV Selection of RTCDIV pin output frequency
0 RTCDIV pin outputs 512 Hz. (1.95 ms)
1 RTCDIV pin outputs 16.384 kHz. (0.061 ms)
Notes RCLOE0 and RCLOE2 must not be enabled at the same time.
Cautions 1. Change ICT2, ICT1, and ICT0 when RINTE = 0.
2. When the output from RTCDIV pin is stopped, the output continues after a maximum of
two clocks of fXT and enters the low level. While 512 Hz is output, and when the output is
stopped immediately after entering the high level, a pulse of at least one clock width of fXT
may be generated.
3. After the real-time counter starts operating, the output width of the RTCDIV pin may be
shorter than as set during the first interval period.
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(5) Sub-count register (RSUBC)
The RSUBC register is a 16-bit register that counts the reference time of 1 second of the real-time counter. It
takes a value of 0000H to 7FFFH and counts 1 second with a clock of 32.768 kHz.
RSUBC can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Cautions 1. When a correction is made by using the SUBCUD register, the value may become 8000H
or more.
2. This register is also cleared by reset effected by writing the second count register.
3. The value read from this register is not guaranteed if it is read during operation, because
a value that is changing is read.
Figure 8-6. Format of Sub-Count Register (RSUBC)
Address: FFF90H After reset: 0000H R
Symbol 7 6 5 4 3 2 1 0
RSUBC SUBC7 SUBC6 SUBC5 SUBC4 SUBC3 SUBC2 SUBC1 SUBC0
Address: FFF91H After reset: 0000H R
Symbol 7 6 5 4 3 2 1 0
RSUBC SUBC15 SUBC14 SUBC13 SUBC12 SUBC11 SUBC10 SUBC9 SUBC8
(6) Second count register (SEC)
The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of
seconds.
It counts up when the sub-counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz)
later. Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set, the
register value returns to the normal value after 1 period.
SEC can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8-7. Format of Second Count Register (SEC)
Address: FFF92H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
SEC 0 SEC40 SEC20 SEC10 SEC8 SEC4 SEC2 SEC1
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(7) Minute count register (MIN)
The MIN register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of
minutes.
It counts up when the second counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz)
later. Even if the second count register overflows while this register is being written, this register ignores the
overflow and is set to the value written. Set a decimal value of 00 to 59 to this register in BCD code. If a value
outside the range is set, the register value returns to the normal value after 1 period.
MIN can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8-8. Format of Minute Count Register (MIN)
Address: FFF93H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
MIN 0 MIN40 MIN20 MIN10 MIN8 MIN4 MIN2 MIN1
(8) Hour count register (HOUR)
The HOUR register is an 8-bit register that takes a value of 00 to 23 or 01 to 12, 21 to 32 (decimal) and
indicates the count value of hours.
It counts up when the minute counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz)
later. Even if the minute count register overflows while this register is being written, this register ignores the
overflow and is set to the value written. Specify a decimal value of 00 to 23, 01 to 12, or 21 to 32 by using BCD
code according to the time system specified using bit 3 (AMPM) of real-time counter control register 0
(RTCC0).
If the AMPM bit value is changed, the values of the HOUR register change according to the specified time
system.
If a value outside the range is set, the register value returns to the normal value after 1 period.
HOUR can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 12H.
However, the value of this register is 00H if the AMPM bit is set to 1 after reset.
Figure 8-9. Format of Hour Count Register (HOUR)
Address: FFF94H After reset: 12H R/W
Symbol 7 6 5 4 3 2 1 0
HOUR 0 0 HOUR20 HOUR10 HOUR8 HOUR4 HOUR2 HOUR1
Caution Bit 5 (HOUR20) of HOUR indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system is
selected).
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Table 8-2. Displayed Time Digits
24-Hour Display (AMPM Bit = 1) 12-Hour Display (AMPM Bit = 0)
Time HOUR Register Time HOUR Register
0 00H 0 a.m. 12H
1 01H 1 a.m. 01H
2 02H 2 a.m. 02H
3 03H 3 a.m. 03H
4 04H 4 a.m. 04H
5 05H 5 a.m. 05H
6 06H 6 a.m. 06H
7 07H 7 a.m. 07H
8 08H 8 a.m. 08H
9 09H 9 a.m. 09H
10 10H 10 a.m. 10H
11 11H 11 a.m. 11H
12 12H 0 p.m. 32H
13 13H 1 p.m. 21H
14 14H 2 p.m. 22H
15 15H 3 p.m. 23H
16 16H 4 p.m. 24H
17 17H 5 p.m. 25H
18 18H 6 p.m. 26H
19 19H 7 p.m. 27H
20 20H 8 p.m. 28H
21 21H 9 p.m. 29H
22 22H 10 p.m. 30H
23 23H 11 p.m. 31H
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(9) Day count register (DAY)
The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of
days.
It counts up when the hour counter overflows.
This counter counts as follows.
• 01 to 31 (January, March, May, July, August, October, December)
• 01 to 30 (April, June, September, November)
• 01 to 29 (February, leap year)
• 01 to 28 (February, normal year)
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz)
later. Even if the hour count register overflows while this register is being written, this register ignores the
overflow and is set to the value written. Set a decimal value of 01 to 31 to this register in BCD code. If a value
outside the range is set, the register value returns to the normal value after 1 period.
DAY can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 01H.
Figure 8-10. Format of Day Count Register (DAY)
Address: FFF96H After reset: 01H R/W
Symbol 7 6 5 4 3 2 1 0
DAY 0 0 DAY20 DAY10 DAY8 DAY4 DAY2 DAY1
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(10) Week count register (WEEK)
The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of
weekdays.
It counts up in synchronization with the day counter.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz)
later. Set a decimal value of 00 to 06 to this register in BCD code. If a value outside the range is set, the
register value returns to the normal value after 1 period.
WEEK can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8-11. Format of Week Count Register (WEEK)
Address: FFF95H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
WEEK 0 0 0 0 0 WEEK4 WEEK2 WEEK1
Caution The value corresponding to the month count register or the day count register is not stored
in the week count register automatically. After reset release, set the week count register as
follow.
Day WEEK
Sunday 00H
Monday 01H
Tuesday 02H
Wednesday 03H
Thursday 04H
Friday 05H
Saturday 06H
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(11) Month count register (MONTH)
The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value
of months.
It counts up when the day counter overflows.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz)
later. Even if the day count register overflows while this register is being written, this register ignores the
overflow and is set to the value written. Set a decimal value of 01 to 12 to this register in BCD code. If a value
outside the range is set, the register value returns to the normal value after 1 period.
MONTH can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 01H.
Figure 8-12. Format of Month Count Register (MONTH)
Address: FFF97H After reset: 01H R/W
Symbol 7 6 5 4 3 2 1 0
MONTH 0 0 0 MONTH10 MONTH8 MONTH4 MONTH2 MONTH1
(12) Year count register (YEAR)
The YEAR register is an 8-bit register that takes a value of 0 to 99 (decimal) and indicates the count value of
years.
It counts up when the month counter overflows.
Values 00, 04, 08, …, 92, and 96 indicate a leap year.
When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz)
later. Even if the month count register overflows while this register is being written, this register ignores the
overflow and is set to the value written. Set a decimal value of 00 to 99 to this register in BCD code. If a value
outside the range is set, the register value returns to the normal value after 1 period.
YEAR can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8-13. Format of Year Count Register (YEAR)
Address: FFF98H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
YEAR YEAR80 YEAR40 YEAR20 YEAR10 YEAR8 YEAR4 YEAR2 YEAR1
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(13) Watch error correction register (SUBCUD)
This register is used to correct the watch with high accuracy when it is slow or fast by changing the value
(reference value: 7FFFH) that overflows from the sub-count register (RSUBC) to the second count register.
SUBCUD can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8-14. Format of Watch Error Correction Register (SUBCUD)
Address: FFF99H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
SUBCUD DEV F6 F5 F4 F3 F2 F1 F0
DEV Setting of watch error correction timing
0 Corrects watch error when the second digits are at 00, 20, or 40 (every 20 seconds).
1 Corrects watch error only when the second digits are at 00 (every 60 seconds).
Writing to the SUBCUD register at the following timing is prohibited.
• When DEV = 0 is set: For a period of SEC = 00H, 20H, 40H
• When DEV = 1 is set: For a period of SEC = 00H
F6 Setting of watch error correction value
0 Increases by {(F5, F4, F3, F2, F1, F0) – 1} × 2.
1 Decreases by {(/F5, /F4, /F3, /F2, /F1, /F0) + 1} × 2.
When (F6, F5, F4, F3, F2, F1, F0) = (*, 0, 0, 0, 0, 0, *), the watch error is not corrected. * is 0 or 1.
/F5 to /F0 are the inverted values of the corresponding bits (000011 when 111100).
Range of correction value: (when F6 = 0) 2, 4, 6, 8, … , 120, 122, 124
(when F6 = 1) –2, –4, –6, –8, … , –120, –122, –124
The range of value that can be corrected by using the watch error correction register (SUBCUD) is shown
below.
DEV = 0 (correction every 20 seconds) DEV = 1 (correction every 60 seconds)
Correctable range –189.2 ppm to 189.2 ppm –63.1 ppm to 63.1 ppm
Maximum excludes
quantization error
±1.53 ppm ±0.51 ppm
Minimum resolution ±3.05 ppm ±1.02 ppm
Remark Set DEV to 0 when the correction range is −63.1 ppm or less, or 63.1 ppm or more.
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(14) Alarm minute register (ALARMWM)
This register is used to set minutes of alarm.
ALARMWM can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is
set, the alarm is not detected.
Figure 8-15. Format of Alarm Minute Register (ALARMWM)
Address: FFF9AH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ALARMWM 0 WM40 WM20 WM10 WM8 WM4 WM2 WM1
(15) Alarm hour register (ALARMWH)
This register is used to set hours of alarm.
ALARMWH can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 12H.
However, the value of this register is 00H if the AMPM bit is set to 1 after reset.
Caution Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code. If a value
outside the range is set, the alarm is not detected.
Figure 8-16. Format of Alarm Hour Register (ALARMWH)
Address: FFF9BH After reset: 12H R/W
Symbol 7 6 5 4 3 2 1 0
ALARMWH 0 0 WH20 WH10 WH8 WH4 WH2 WH1
Caution Bit 5 (WH20) of ALARMWH indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system is
selected).
(16) Alarm week register (ALARMWW)
This register is used to set date of alarm.
ALARMWW can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8-17. Format of Alarm Week Register (ALARMWW)
Address: FFF9CH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ALARMWW 0 WW6 WW5 WW4 WW3 WW2 WW1 WW0
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Here is an example of setting the alarm.
Day 12-Hour Display 24-Hour Display Time of Alarm
Sunday
W
W
0
Monday
W
W
1
Tuesday
W
W
2
Wednesday
W
W
3
Thursday
W
W
4
Friday
W
W
5
Saturday
W
W
6
Hour
10
Hour
1
Minute
10
Minute
1
Hour
10
Hour
1
Minute
10
Minute
1
Every day, 0:00 a.m. 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0
Every day, 1:30 a.m. 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0
Every day, 11:59 a.m. 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9
Monday through
Friday, 0:00 p.m.
0 1 1 1 1 1 0 3 2 0 0 1 2 0 0
Sunday, 1:30 p.m. 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0
Monday, Wednesday,
Friday, 11:59 p.m.
0 1 0 1 0 1 0 3 1 5 9 2 3 5 9
(17) Port mode registers 1, 3 (PM1, PM3)
This register sets ports 1 and 3 input/output in 1-bit units.
When using the P15/RTCDIV/RTCCL and P30/RTC1HZ/INTP3 pins for clock output of real-time counter, clear
PM15 and PM30 and the output latches of P15 and P30 to 0.
PM1 and PM3 are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 8-18. Format of Port Mode Registers 1 and 3 (PM1, PM3)
Address: FFF21H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
Address: FFF23H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM3 1 1 1 1 1 1 PM31 PM30
PMmn Pmn pin I/O mode selection (m = 1 and 3 ; n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
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8.4 Real-Time Counter Operation
8.4.1 Starting operation of real-time counter
Figure 8-19. Procedure for Starting Operation of Real-Time Counter
Setting AMPM, CT2 to CT0
Setting MIN
RTCE = 0
Setting SEC (clearing RSUBC)
Start
INTRTC = 1?
Stops counter operation.
Selects 12-/24-hour system and interrupt (INTRTC).
Sets second count register.
Sets minute count register.
No
Yes
Setting HOUR Sets hour count register.
Setting WEEK Sets week count register.
Setting DAY Sets day count register.
Setting MONTH Sets month count register.
Setting YEAR Sets year count register.
Setting SUBCUD
Note 2
Sets watch error correction register.
Clearing IF flags of interrupt Clears interrupt request flags (RTCIF, RTCIIF).
Clearing MK flags of interrupt Clears interrupt mask flags (RTCMK, RTCIMK).
RTCE = 1
Note 3
Starts counter operation.
Reading counter
RTCEN = 1
Note 1
Supplies input clock.
Notes 1. First set RTCEN to 1, while oscillation of the subsystem clock (fSUB) is stable.
2. Set up SUBCUD only if the watch error must be corrected. For details about how to calculate the
correction value, see 8.4.8 Example of watch error correction of real-time counter.
3. Confirm the procedure described in 8.4.2 Shifting to STOP mode after starting operation when
shifting to STOP mode without waiting for INTRTC = 1 after RTCE = 1.
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Yes
RTCE = 1
RWAIT = 1
No
Yes
RWAIT = 0
No RWST = 1 ?
RWST = 0 ?
STOP mode
RTCE = 1
STOP mode
Waiting at least for 2
fSUB clocks
Sets to counter operation
start
Shifts to STOP mode
Sets to counter operation
start
Sets to stop the SEC to YEAR
counters, reads the counter
value, write mode
Checks the counter wait status
Sets the counter operation
Shifts to STOP mode
Example 2
Example 1
8.4.2 Shifting to STOP mode after starting operation
Perform one of the following processing when shifting to STOP mode immediately after setting RTCE to 1.
However, after setting RTCE to 1, this processing is not required when shifting to STOP mode after the first
INTRTC interrupt has occurred.
• Shifting to STOP mode when at least two subsystem clocks (fSUB) (about 62
μ
s) have elapsed after setting RTCE
to 1 (see Figure 8-20, Example 1).
• Checking by polling RWST to become 1, after setting RTCE to 1 and then setting RWAIT to 1. Afterward, setting
RWAIT to 0 and shifting to STOP mode after checking again by polling that RWST has become 0 (see Figure 8-
20, Example 2).
Figure 8-20. Procedure for Shifting to STOP Mode After Setting RTCE to 1
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8.4.3 Reading/writing real-time counter
Read or write the counter after setting 1 to RWAIT first.
Figure 8-21. Procedure for Reading Real-Time Counter
Reading MIN
RWAIT = 1
Reading SEC
Start
RWST = 1?
Stops SEC to YEAR counters.
Mode to read and write count values
Reads second count register.
Reads minute count register.
No
Yes
Reading HOUR
Reads hour count register.
Reading WEEK
Reads week count register.
Reading DAY
Reads day count register.
Reading MONTH
Reads month count register.
Reading YEAR
Reads year count register.
RWAIT = 0
RWST = 0?
Note
No
Yes
Sets counter operation.
Checks wait status of counter.
End
Note Be sure to confirm that RWST = 0 before setting STOP mode.
Caution Complete the series of operations of setting RWAIT to 1 to clearing RWAIT to 0 within 1 second.
Remark SEC, MIN, HOUR, WEEK, DAY, MONTH, and YEAR may be read in any sequence.
All the registers do not have to be set and only some registers may be read.
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Figure 8-22. Procedure for Writing Real-Time Counter
Writing MIN
RWAIT = 1
Writing SEC
Start
RWST = 1?
Stops SEC to YEAR counters.
Mode to read and write count values
No
Yes
Writing HOUR
Writing WEEK
Writing DAY
Writing MONTH
Writing YEAR
RWAIT = 0
RWST = 0?
Note
No
Yes
Sets counter operation.
Checks wait status of counter.
End
Writes second count register.
Writes minute count register.
Writes hour count register.
Writes week count register.
Writes day count register.
Writes month count register.
Writes year count register.
Note Be sure to confirm that RWST = 0 before setting STOP mode.
Caution Complete the series of operations of setting RWAIT to 1 to clearing RWAIT to 0 within 1 second.
Remark SEC, MIN, HOUR, WEEK, DAY, MONTH, and YEAR may be written in any sequence.
All the registers do not have to be set and only some registers may be written.
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8.4.4 Setting alarm of real-time counter
Set time of alarm after setting 0 to WALE first.
Figure 8-23. Alarm Setting Procedure
WALE = 0
Setting ALARMWM
Start
INTRTC = 1?
Match operation of alarm is invalid.
Sets alarm minute register.
Alarm processing
Yes
WALIE = 1 Interrupt is generated when alarm matches.
Setting ALARMWH Sets alarm hour register.
Setting ALARMWW Sets alarm week register.
WALE = 1 Match operation of alarm is valid.
WAFG = 1? No
Yes
Constant-period interrupt servicing
Match detection of alarm
No
Remarks 1. ALARMWM, ALARMWH, and ALARMWW may be written in any sequence.
2. Fixed-cycle interrupts and alarm match interrupts use the same interrupt source (INTRTC). When
using these two types of interrupts at the same time, which interrupt occurred can be judged by
checking the fixed-cycle interrupt status flag (RIFG) and the alarm detection status flag (WAFG) upon
INTRTC occurrence.
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8.4.5 1 Hz output of real-time counter
Figure 8-24. 1 Hz Output Setting Procedure
RTCE = 0
RTCE = 1
Start
Stops counter operation.
RCLOE1 = 1 Enables output of RTC1HZ pin (1 Hz).
Starts counter operation.
Output start from RTC1HZ pin
Caution First set RTCEN to 1, while oscillation of the subsystem clock (fSUB) is stable.
8.4.6 32.768 kHz output of real-time counter
Figure 8-25. 32.768 kHz Output Setting Procedure
Start
RCLOE0 = 1 Enables output of RTCCL pin (32.768 kHz).
32.768 kHz output
start from RTCCL pin
Caution First set RTCEN to 1, while oscillation of the subsystem clock (fSUB) is stable.
8.4.7 512 Hz, 16.384 kHz output of real-time counter
Figure 8-26. 512 Hz, 16.384 kHz output Setting Procedure
Start
RCLOE2 = 1
512 Hz Output: RCKDIV = 0
16.384 kHz Output: RCKDIV = 1
Selects output frequency of
RTCDIV pin.
512 Hz or 16.384 kHz
output start from RTCDIV pin
Enables output of RTCDIV pin.
Caution First set RTCEN to 1, while oscillation of the subsystem clock (fSUB) is stable.
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8.4.8 Example of watch error correction of real-time counter
The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error
correction register.
Example of calculating the correction value
The correction value used when correcting the count value of the sub-count register (RSUBC) is calculated by
using the following expression.
Set DEV to 0 when the correction range is −63.1 ppm or less, or 63.1 ppm or more.
(When DEV = 0)
Correction valueNote = Number of correction counts in 1 minute ÷ 3 = (Oscillation frequency ÷ Target frequency
− 1) ¯ 32768 ¯ 60 ÷ 3
(When DEV = 1)
Correction valueNote = Number of correction counts in 1 minute = (Oscillation frequency ÷ Target frequency − 1)
¯ 32768 ¯ 60
Note The correction value is the watch error correction value calculated by using bits 6 to 0 of the watch error
correction register (SUBCUD).
(When F6 = 0) Correction value = {(F5, F4, F3, F2, F1, F0) − 1} ¯ 2
(When F6 = 1) Correction value = − {(/F5, /F4, /F3, /F2, /F1, /F0) + 1} ¯ 2
When (F6, F5, F4, F3, F2, F1, F0) is (*, 0, 0, 0, 0, 0, *), watch error correction is not performed. “*” is 0
or 1.
/F5 to /F0 are bit-inverted values (000011 when 111100).
Remarks 1. The correction value is 2, 4, 6, 8, … 120, 122, 124 or −2, −4, −6, −8, … −120, −122, −124.
2. The oscillation frequency is the subsystem clock (fSUB).
It can be calculated from the 32 kHz output frequency of the RTCCL pin or the output frequency of
the RTC1HZ pin ¯ 32768 when the watch error correction register is set to its initial value (00H).
3. The target frequency is the frequency resulting after correction performed by using the watch error
correction register.
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Correction example <1>
Example of correcting from 32772.3 Hz to 32768 Hz (32772.3 Hz − 131.2 ppm)
[Measuring the oscillation frequency]
The oscillation frequencyNote of each product is measured by outputting about 32 kHz from the RTCCL pin or
outputting about 1 Hz from the RTC1HZ pin when the watch error correction register is set to its initial value (00H).
Note See 8.4.5 1 Hz output of real-time counter for the setting procedure of outputting about 1 Hz from the
RTC1HZ pin, and 8.4.6 32.768 kHz output of real-time counter for the setting procedure of outputting
about 32 kHz from the RTCCL pin.
[Calculating the correction value]
(When the output frequency from the RTCCL pin is 32772.3 Hz)
If the target frequency is assumed to be 32768 Hz (32772.3 Hz − 131.2 ppm), the correction range for −131.2
ppm is −63.1 ppm or less, so assume DEV to be 0.
The expression for calculating the correction value when DEV is 0 is applied.
Correction value = Number of correction counts in 1 minute ÷ 3
= (Oscillation frequency ÷ Target frequency − 1) ¯ 32768 ¯ 60 ÷ 3
= (32772.3 ÷ 32768 − 1) ¯ 32768 ¯ 60 ÷ 3
= 86
[Calculating the values to be set to (F6 to F0)]
(When the correction value is 86)
If the correction value is 0 or more (when delaying), assume F6 to be 0.
Calculate (F5, F4, F3, F2, F1, F0) from the correction value.
{(F5, F4, F3, F2, F1, F0) − 1} ¯ 2 = 86
(F5, F4, F3, F2, F1, F0) = 44
(F5, F4, F3, F2, F1, F0) = (1, 0, 1, 1, 0, 0)
Consequently, when correcting from 32772.3 Hz to 32768 Hz (32772.3 Hz − 131.2 ppm), setting the correction
register such that DEV is 0 and the correction value is 86 (bits 6 to 0 of SUBCUD: 0101100) results in 32768 Hz
(0 ppm).
Figure 8-27 shows the operation when (DEV, F6, F5, F4, F3, F2, F1, F0) is (0, 0, 1, 0, 1, 1, 0, 0).
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Figure 8-27. Operation When (DEV, F6, F5, F4, F3, F2, F1, F0) = (0, 0, 1, 0, 1, 1, 0, 0)
RSUBC
count value
SEC
00 01
8055H 0000H 0001H 7FFFH0000H 8054H
40
8055H0000H 8054H8055H0000H 8054H
19
0000H 0001H 7FFFH
20 39
0000H 0001H 7FFFH 0000H 0001H 7FFFH
59 00
8055H0000H 8054H
7FFFH + 56H (86) 7FFFH + 56H (86)
7FFFH + 56H (86) 7FFFH+56H (86)
Count start
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Correction example <2>
Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm)
[Measuring the oscillation frequency]
The oscillation frequencyNote of each product is measured by outputting about 32 kHz from the RTCCL pin or
outputting about 1 Hz from the RTC1HZ pin when the watch error correction register is set to its initial value (00H).
Note See 8.4.5 1 Hz output of real-time counter for the setting procedure of outputting about 1 Hz from the
RTC1HZ pin, and 8.4.6 32.768 kHz output of real-time counter for the setting procedure of outputting
about 32 kHz from the RTCCL pin.
[Calculating the correction value]
(When the output frequency from the RTCCL pin is 0.9999817 Hz)
Oscillation frequency = 32768 ¯ 0.9999817 ≈ 32767.4 Hz
Assume the target frequency to be 32768 Hz (32767.4 Hz + 18.3 ppm) and DEV to be 1.
The expression for calculating the correction value when DEV is 1 is applied.
Correction value = Number of correction counts in 1 minute
= (Oscillation frequency ÷ Target frequency − 1) ¯ 32768 ¯ 60
= (32767.4 ÷ 32768 − 1) ¯ 32768 ¯ 60
= −36
[Calculating the values to be set to (F6 to F0)]
(When the correction value is −36)
If the correction value is 0 or less (when speeding up), assume F6 to be 1.
Calculate (F5, F4, F3, F2, F1, F0) from the correction value.
− {(/F5, /F4, /F3, /F2, /F1, /F0) + 1} ¯ 2 = −36
(/F5, /F4, /F3, /F2, /F1, /F0) = 17
(/F5, /F4, /F3, /F2, /F1, /F0) = (0, 1, 0, 0, 0, 1)
(F5, F4, F3, F2, F1, F0) = (1, 0, 1, 1, 1, 0)
Consequently, when correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm), setting the correction
register such that DEV is 1 and the correction value is −36 (bits 6 to 0 of SUBCUD: 1101110) results in 32768
Hz (0 ppm).
Figure 8-28 shows the operation when (DEV, F6, F5, F4, F3, F2, F1, F0) is (1, 1, 1, 0, 1, 1, 1, 0).
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Figure 8-28. Operation When (DEV, F6, F5, F4, F3, F2, F1, F0) = (1, 1, 1, 0, 1, 1, 1, 0)
RSUBC
count value
SEC
00 01
7FDBH 0000H 0001H 7FFFH0000H 7FDAH
4019
0000H 0001H 7FFFH 0000H 0001H 7FFFH
20 39
0000H 0001H 7FFFH 0000H 0001H 7FFFH 0000H 0001H 7FFFH
59 00
7FDBH0000H 7FDAH
7FFFH − 24H (36) 7FFFH − 24H (36)
Count start
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CHAPTER 9 WATCHDOG TIMER
9.1 Functions of Watchdog Timer
The watchdog timer operates on the internal low-speed oscillation clock.
The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset
signal is generated.
Program loop is detected in the following cases.
• If the watchdog timer counter overflows
• If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
• If data other than “ACH” is written to WDTE
• If data is written to WDTE during a window close period
When a reset occurs due to the watchdog timer, bit 4 (WDRF) of the reset control flag register (RESF) is set to 1.
For details of RESF, see CHAPTER 20 RESET FUNCTION.
When 75% of the overflow time is reached, an interval interrupt can be generated.
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9.2 Configuration of Watchdog Timer
The watchdog timer includes the following hardware.
Table 9-1. Configuration of Watchdog Timer
Item Configuration
Control register Watchdog timer enable register (WDTE)
How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the
option byte.
Table 9-2. Setting of Option Bytes and Watchdog Timer
Setting of Watchdog Timer Option Byte (000C0H)
Watchdog timer interval interrupt Bit 7 (WDTINT)
Window open period Bits 6 and 5 (WINDOW1, WINDOW0)
Controlling counter operation of watchdog timer Bit 4 (WDTON)
Overflow time of watchdog timer Bits 3 to 1 (WDCS2 to WDCS0)
Controlling counter operation of watchdog timer
(in HALT/STOP mode)
Bit 0 (WDSTBYON)
Remark For the option byte, see CHAPTER 24 OPTION BYTE.
Figure 9-1. Block Diagram of Watchdog Timer
f
IL
WDTON of option
byte (000C0H)
WDTINT of option
byte (000C0H)
Interval time controller
(Count value overflow time × 3/4) Interval time interrupt
WDCS2 to WDCS0 of
option byte (000C0H)
Clock
input
controller
20-bit
counter Selector Overflow signal
Reset
output
controller
Internal reset signal
Count clear
signal Window size
decision signal
Window size check
Watchdog timer enable
register (WDTE)
Write detector to
WDTE except ACH
Internal bus
WINDOW1 and
WINDOW0 of option
byte (000C0H)
f
IL
/2
10
to f
IL
/2
20
Remark fIL: Internal low-speed oscillation clock frequency
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9.3 Register Controlling Watchdog Timer
The watchdog timer is controlled by the watchdog timer enable register (WDTE).
(1) Watchdog timer enable register (WDTE)
Writing “ACH” to WDTE clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 9AH or 1AHNote.
Figure 9-2. Format of Watchdog Timer Enable Register (WDTE)
01234567
Symbol
WDTE
Address: FFFABH After reset: 9AH/1AH
Note
R/W
Note The WDTE reset value differs depending on the WDTON setting value of the option byte (000C0H). To
operate watchdog timer, set WDTON to 1.
WDTON Setting Value WDTE Reset Value
0 (watchdog timer count operation disabled) 1AH
1 (watchdog timer count operation enabled) 9AH
Cautions 1. If a value other than “ACH” is written to WDTE, an internal reset signal is generated.
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal
is generated.
3. The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)).
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9.4 Operation of Watchdog Timer
9.4.1 Controlling operation of watchdog timer
1. When the watchdog timer is used, its operation is specified by the option byte (000C0H).
• Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1
(the counter starts operating after a reset release) (for details, see CHAPTER 24).
WDTON Watchdog Timer Counter
0 Counter operation disabled (counting stopped after reset)
1 Counter operation enabled (counting started after reset)
• Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H) (for details, see
9.4.2 and CHAPTER 24).
• Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (000C0H)
(for details, see 9.4.3 and CHAPTER 24).
2. After a reset release, the watchdog timer starts counting.
3. By writing “ACH” to WDTE after the watchdog timer starts counting and before the overflow time set by the
option byte, the watchdog timer is cleared and starts counting again.
4. After that, write WDTE the second time or later after a reset release during the window open period. If WDTE
is written during a window close period, an internal reset signal is generated.
5. If the overflow time expires without “ACH” written to WDTE, an internal reset signal is generated.
A internal reset signal is generated in the following cases.
• If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
• If data other than “ACH” is written to WDTE
Cautions 1. When data is written to WDTE for the first time after reset release, the watchdog timer is
cleared in any timing regardless of the window open time, as long as the register is written
before the overflow time, and the watchdog timer starts counting again.
2. If the watchdog timer is cleared by writing “ACH” to WDTE, the actual overflow time may be
different from the overflow time set by the option byte by up to 2/fIL seconds.
3. The watchdog timer can be cleared immediately before the count value overflows.
<Example> When the overflow time is set to 210/fIL, writing “ACH” is valid up to count value
3FH.
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User’s Manual U17894EJ9V0UD 341
Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows
depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H).
WDSTBYON = 0 WDSTBYON = 1
In HALT mode
In STOP mode
Watchdog timer operation stops. Watchdog timer operation continues.
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is cleared to 0 and counting starts.
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is
short, an overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time
when operating with the X1 oscillation clock and when the watchdog timer is to be cleared
after the STOP mode release by an interval interrupt.
5. The watchdog timer continues its operation during self-programming of the flash memory
and EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set
the overflow time and window size taking this delay into consideration.
9.4.2 Setting overflow time of watchdog timer
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer
starts counting again by writing “ACH” to WDTE during the window open period before the overflow time.
The following overflow time is set.
Table 9-3. Setting of Overflow Time of Watchdog Timer
WDCS2 WDCS1 WDCS0 Overflow Time of Watchdog Timer
0 0 0 210/fIL (3.88 ms)
0 0 1 211/fIL (7.76 ms)
0 1 0 212/fIL (15.52 ms)
0 1 1 213/fIL (31.03 ms)
1 0 0 215/fIL (124.12 ms)
1 0 1 217/fIL (496.48 ms)
1 1 0 218/fIL (992.97 ms)
1 1 1 220/fIL (3971.88 ms)
Caution The watchdog timer continues its operation during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
Remarks 1. fIL: Internal low-speed oscillation clock frequency
2. ( ): fIL = 264 kHz (MAX.)
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9.4.3 Setting window open period of watchdog timer
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option
byte (000C0H). The outline of the window is as follows.
• If “ACH” is written to WDTE during the window open period, the watchdog timer is cleared and starts counting
again.
• Even if “ACH” is written to WDTE during the window close period, an abnormality is detected and an internal
reset signal is generated.
Example: If the window open period is 25%
Window close period (75%) Window open
period (25%)
Counting
starts
Overflow
time
Counting starts again when
“ACH” is written to WDTE.
Internal reset signal is generated
if “ACH” is written to WDTE.
Caution When data is written to WDTE for the first time after reset release, the watchdog timer is cleared
in any timing regardless of the window open time, as long as the register is written before the
overflow time, and the watchdog timer starts counting again.
The window open period to be set is as follows.
Table 9-4. Setting Window Open Period of Watchdog Timer
WINDOW1 WINDOW0 Window Open Period of Watchdog Timer
0 0 25%
0 1 50%
1 0 75%
1 1 100%
Cautions 1. The watchdog timer continues its operation during self-programming of the flash memory
and EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set
the overflow time and window size taking this delay into consideration.
2. When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period is 100%
regardless of the values of WINDOW1 and WINDOW0.
3. Do not set the window open period to 25% if the watchdog timer corresponds to either of the
conditions below.
• When used at a supply voltage (VDD) below 2.7 V.
• When stopping all main system clocks (internal high-speed oscillation clock, X1 clock,
and external main system clock) by use of the STOP mode or software.
• Low-power consumption mode
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User’s Manual U17894EJ9V0UD 343
Remarks 1. If the overflow time is set to 210/fIL, the window close time and open time are as follows.
Setting of Window Open Period
25% 50% 75% 100%
Window close time 0 to 3.56 ms 0 to 2.37 ms 0 to 0.119 ms None
Window open time 3.56 to 3.88 ms 2.37 to 3.88 ms 0.119 to 3.88 ms 0 to 3.88 ms
<When window open period is 25%>
• Overflow time:
210/fIL (MAX.) = 210/264 kHz (MAX.) = 3.88 ms
• Window close time:
0 to 210/fIL (MIN.) × (1 − 0.25) = 0 to 210/216 kHz (MIN.) × 0.75 = 0 to 3.56 ms
• Window open time:
210/fIL (MIN.) × (1 − 0.25) to 210/fIL (MAX.) = 210/216 kHz (MIN.) × 0.75 to 210/264 kHz (MAX.)
= 3.56 to 3.88 ms
2. fIL: Internal low-speed oscillation clock frequency
9.4.4 Setting watchdog timer interval interrupt
Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be
generated when 75% of the overflow time is reached.
Table 9-5. Setting of Watchdog Timer Interval Interrupt
WDTINT Use of Watchdog Timer Interval Interrupt
0 Interval interrupt is used.
1 Interval interrupt is generated when 75% of overflow time is reached.
Caution When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is
short, an overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the
STOP mode release by an interval interrupt.
Remark The watchdog timer continues counting even after INTWDTI is generated (until ACH is written to the
WDTE register). If ACH is not written to the WDTE register before the overflow time, an internal reset
signal is generated.
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CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
10.1 Functions of Clock Output/Buzzer Output Controller
The clock output controller is intended for carrier output during remote controlled transmission and clock output for
supply to peripheral ICs.
Buzzer output is a function to output a square wave of buzzer frequency.
One pin can be used to output a clock or buzzer sound.
Two output pins, PCLBUZ0 and PCLBUZ1, are available.
PCLBUZ0 outputs a clock selected by clock output select register 0 (CKS0).
PCLBUZ1 outputs a clock selected by clock output select register 1 (CKS1).
Figure 10-1 shows the block diagram of clock output/buzzer output controller.
Figure 10-1. Block Diagram of Clock Output/Buzzer Output Controller
f
MAIN
f
SUB
PCLOE0 0 0 0
PCLOE0
53
PCLBUZ0
Note
/INTP6/P140
PCLBUZ1
Note
/INTP7/P141
CSEL0 CCS02 CCS01 CCS00
PM141
PM140
PCLOE1 0 0 0 CSEL1 CCS12 CCS11 CCS10
8
PCLOE1
8
f
MAIN
/2
11
to f
MAIN
/2
13
Clock/buzzer
controller
Internal bus
Clock output select register 1 (CKS1)
Prescaler
Prescaler
Selector
Selector
Clock/buzzer
controller
Output latch
(P141)
Internal bus
Clock output select register 0 (CKS0)
Output latch
(P140)
f
MAIN
/2
11
to f
MAIN
/2
13
f
MAIN
to f
MAIN
/2
4
f
MAIN
to f
MAIN
/2
4
f
SUB
to f
SUB
/2
7
f
SUB
to f
SUB
/2
7
Note The PCLBUZ0 and PCLBUZ1 pins can output a clock of up to 10 MHz at 2.7 V ≤ V
DD. Setting a clock
exceeding 5 MHz at VDD < 2.7 V is prohibited.
Remark fMAIN: Main system clock frequency
fSUB: Subsystem clock frequency
CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
User’s Manual U17894EJ9V0UD 345
10.2 Configuration of Clock Output/Buzzer Output Controller
The clock output/buzzer output controller includes the following hardware.
Table 10-1. Configuration of Clock Output/Buzzer Output Controller
Item Configuration
Control registers Clock output select registers 0, 1 (CKS0, CKS1)
Port mode register 14 (PM14)
Port register 14 (P14)
10.3 Registers Controlling Clock Output/Buzzer Output Controller
The following two registers are used to control the clock output/buzzer output controller.
• Clock output select registers 0, 1 (CKS0, CSK1)
• Port mode register 14 (PM14)
(1) Clock output select registers 0, 1 (CKS0, CKS1)
These registers set output enable/disable for clock output or for the buzzer frequency output pin
(PCLBUZ0/PCLBUZ1), and set the output clock.
Select the clock to be output from PCLBUZ0 by using CKS0.
Select the clock to be output from PCLBUZ1 by using CKS1.
CKS0 and CKS1 are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
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Figure 10-2. Format of Clock Output Select Register n (CKSn)
Address: FFFA5H After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 0
CKSn PCLOEn 0 0 0 CSELn CCSn2 CCSn1 CCSn0
PCLOEn PCLBUZn output enable/disable specification
0 Output disable (default)
1 Output enable
PCLBUZn output clock selection CSELn CCSn2 CCSn1 CCSn0
fMAIN =
5 MHz
fMAIN =
10 MHz
fMAIN =
20 MHz
0 0 0 0 fMAIN 5 MHz 10 MHzNote Setting
prohibitedNote
0 0 0 1 fMAIN/2 2.5 MHz 5 MHz 10 MHzNote
0 0 1 0 fMAIN/221.25 MHz 2.5 MHz 5 MHz
0 0 1 1 fMAIN/23625 kHz 1.25 MHz 2.5 MHz
0 1 0 0 fMAIN/24312.5 kHz 625 kHz 1.25 MHz
0 1 0 1 fMAIN/211 2.44 kHz 4.88 kHz 9.76 kHz
0 1 1 0 fMAIN/212 1.22 kHz 2.44 kHz 4.88 kHz
0 1 1 1 fMAIN/213 610 Hz 1.22 kHz 2.44 kHz
1 0 0 0 fSUB 32.768 kHz
1 0 0 1 fSUB/2 16.384 kHz
1 0 1 0 fSUB/22 8.192 kHz
1 0 1 1 fSUB/23 4.096 kHz
1 1 0 0 fSUB/24 2.048 kHz
1 1 0 1 fSUB/25 1.024 kHz
1 1 1 0 fSUB/26 512 Hz
1 1 1 1 fSUB/27 256 Hz
Note Setting an output clock exceeding 10 MHz is prohibited when 2.7 V ≤ V
DD. Setting a clock exceeding 5
MHz at VDD < 2.7 V is also prohibited.
Cautions 1. Change the output clock after disabling clock output (PCLOEn = 0).
2. If the selected clock (fMAIN or fSUB) stops during clock output (PCLOEn = 1), the output
becomes undefined.
Remarks 1. n = 0, 1
2. f
MAIN: Main system clock frequency
3. f
SUB: Subsystem clock frequency
CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
User’s Manual U17894EJ9V0UD 347
(2) Port mode register 14 (PM14)
This register sets port 14 input/output in 1-bit units.
When using the P140/INTP6/PCLBUZ0 and P141/INTP7/PCLBUZ1 pins for clock output/buzzer output, clear
PM140 and PM141 and the output latches of P140 and P141 to 0.
PM14 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 10-3. Format of Port Mode Register 14 (PM14)
Address: FFF2EH After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM14 1 1 PM145 PM144 PM143 PM142 PM141 PM140
PM14n P14n pin I/O mode selection (n = 0 to 5)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
10.4 Operations of Clock Output/Buzzer Output Controller
One pin can be used to output a clock or buzzer sound.
Two output pins, PCLBUZ0 and PCLBUZ1, are available.
PCLBUZ0 outputs a clock/buzzer selected by clock output select register 0 (CKS0).
PCLBUZ1 outputs a clock/buzzer selected by clock output select register 1 (CKS1).
10.4.1 Operation as output pin
PCLBUZn is output as the following procedure.
<1> Select the output frequency with bits 0 to 3 (CCSn0 to CCSn2, CSELn) of the clock output select register
(CKSn) of the PCLBUZn pin (output in disabled status).
<2> Set bit 7 (PCLOEn) of CKSn to 1 to enable clock/buzzer output.
Remarks 1. The controller used for outputting the clock starts or stops outputting the clock one clock after
enabling or disabling clock output (PCLOEn) is switched. At this time, pulses with a narrow width
are not output. Figure 10-4 shows enabling or stopping output using PCLOEn and the timing of
outputting the clock.
2. n = 0, 1
Figure 10-4. Remote Control Output Application Example
PCLOEn
1 clock elapsed
Narrow pulses are not recognized
Clock output
<R>
<R>
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CHAPTER 11 A/D CONVERTER
11.1 Function of A/D Converter
The A/D converter converts an analog input signal into a digital value, and consists of up to 16 channels (ANI0 to
ANI15) with a resolution of 10 bits.
The A/D converter has the following function.
• 10-bit resolution A/D conversion
10-bit resolution A/D conversion is carried out repeatedly for one analog input channel selected from ANI0 to
ANI15. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated.
Figure 11-1. Block Diagram of A/D Converter
INTAD
ADCS FR2 FR1 ADCEFR0
AV
SS
5
ANI0/P20
ANI1/P21
ANI2/P22
ANI3/P23
ANI4/P24
ANI5/P25
ANI6/P26
ANI7/P27
ANI8/P150
ANI9/P151
ANI10/P152
ANI11/P153
ANI12/P154
ANI13/P155
ANI14/P156
ANI15/P157
LV1 LV0
5
ADPC3 ADPC2 ADPC1 ADPC0
5
ADPC4
ADS3 ADS2 ADS1 ADS0
ADISS
AV
REF0
AV
SS
A/D converter mode
register (ADM)
Sample & hold circuit
A/D Voltage comparator
ADCS bit
Tap selector
Successive
approximation
register (SAR)
Controller
A/D conversion result
register (ADCR)
Selector
Internal bus
Analog input channel
specification register (ADS)
A/D port configuration
register (ADPC)
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User’s Manual U17894EJ9V0UD 349
11.2 Configuration of A/D Converter
The A/D converter includes the following hardware.
(1) ANI0 to ANI15 pins
These are the analog input pins of the 16-channel A/D converter. They input analog signals to be converted into
digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins.
(2) Sample & hold circuit
The sample & hold circuit samples the input voltage of the analog input pin selected by the selector when A/D
conversion is started, and holds the sampled voltage value during A/D conversion.
(3) Series resistor string
The series resistor string is connected between AVREF0 and AVSS, and generates a voltage to be compared with
the sampled voltage value.
Figure 11-2. Circuit Configuration of Series Resistor String
ADCS
Series resistor string
AV
REF0
P-ch
AV
SS
(4) A/D Voltage comparator
The A/D voltage comparator compares the sampled voltage value and the output voltage of the series resistor
string.
(5) Successive approximation register (SAR)
This register converts the result of comparison by the A/D voltage comparator, starting from the most significant
bit (MSB).
When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D
conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR).
(6) 10-bit A/D conversion result register (ADCR)
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCR register holds the A/D conversion result in its higher 10 bits (the lower 6
bits are fixed to 0).
(7) 8-bit A/D conversion result register (ADCRH)
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result.
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(8) Controller
This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as
well as starting and stopping of the conversion operation. When A/D conversion has been completed, this
controller generates INTAD.
(9) AVREF0 pin
This pin inputs an analog power/reference voltage to the A/D converter. The signal input to ANI0 to ANI15 is
converted into a digital signal, based on the voltage applied across AVREF0 and AVSS. The voltage that can be
supplied to AVREF0 varies as follows, depending on whether P20/ANI0 to P27/ANI7 and P150/ANI8 to
P157/ANI15 are used as digital I/Os or analog inputs.
Table 11-1. AVREF0 Voltage Applied to P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 Pins
Analog/Digital VDD Condition AVREF0 Voltage
Using at least one pin as an analog input and using all
pins not as digital I/Os
2.3 V ≤ VDD ≤ 5.5 V 2.3 V ≤ AVREF0 ≤ VDD = EVDD0 = EVDD1
2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ AVREF0 ≤ VDD = EVDD0 = EVDD1
Pins used as analog inputs and digital I/Os are
mixedNote 2.3 V ≤ VDD < 2.7 V AVREF0 has same potential as EVDD0,
EVDD1, and VDD
2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ AVREF0 ≤ VDD = EVDD0 = EVDD1
Using at least one pin as a digital I/O and using all pins
not as analog inputsNote 1.8 V ≤ VDD < 2.7 V AVREF0 has same potential as EVDD0,
EVDD1, and VDD
Note AVREF0 is the reference for the I/O voltage of a port to be used as a digital port.
• High-/low-level input voltage (VIH4/VIL4)
• High-/low-level output voltage (VOH2/VOL2)
(10) AVSS pin
This is the ground potential pin of the A/D converter. Always use this pin at the same potential as that of the
EVSS0, EVSS1, and VSS pins even when the A/D converter is not used.
(11) A/D converter mode register (ADM)
This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the
conversion operation.
(12) A/D port configuration register (ADPC)
This register switches the ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157 pins to analog input of A/D
converter or digital I/O of port.
(13) Analog input channel specification register (ADS)
This register is used to specify the port that inputs the analog voltage to be converted into a digital signal.
(14) Port mode registers 2 and 15 (PM2, PM15)
This register switches the ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157 pins to input or output.
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11.3 Registers Used in A/D Converter
The A/D converter uses the following seven registers.
• Peripheral enable register 0 (PER0)
• A/D converter mode register (ADM)
• A/D port configuration register (ADPC)
• Analog input channel specification register (ADS)
• Port mode registers 2 and 15 (PM2, PM15)
• 10-bit A/D conversion result register (ADCR)
• 8-bit A/D conversion result register (ADCRH)
(1) Peripheral enable register 0 (PER0)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro
that is not used is stopped in order to reduce the power consumption and noise.
When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-3. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> 1 <0>
PER0 RTCEN DACEN ADCEN IIC0EN SAU1EN SAU0EN 0 TAU0EN
ADCEN Control of A/D converter input clock
0 Stops supply of input clock.
• SFR used by the A/D converter cannot be written.
• The A/D converter is in the reset status.
1 Supplies input clock.
• SFR used by the A/D converter can be read/written.
Cautions 1. When setting the A/D converter, be sure to set ADCEN to 1 first. If ADCEN = 0, writing to a
control register of the A/D converter is ignored, and, even if the register is read, only the
default value is read (except for port mode registers 2 and 15 (PM2, PM15)).
2. Be sure to clear bit 1 of the PER0 register to 0.
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(2) A/D converter mode register (ADM)
This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.
ADM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-4. Format of A/D Converter Mode Register (ADM)
ADCELV0
Note 1
LV1
Note 1
FR0
Note 1
FR1
Note 1
FR2
Note 1
0ADCS
A/D conversion operation control
Stops conversion operation
Enables conversion operation
ADCS
0
1
<0>123456<7>
ADM
Address: FFF30H After reset: 00H R/W
Symbol
A/D voltage comparator operation control
Note 2
Stops A/D voltage comparator operation
Enables A/D voltage comparator operation
ADCE
0
1
Notes 1. For details of FR2 to FR0, LV1, LV0, and A/D conversion, see Table 11-3 A/D Conversion Time
Selection.
2. The operation of the A/D voltage comparator is controlled by ADCS and ADCE, and it takes 1
μ
s from
operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1
μ
s or more has
elapsed from the time ADCE is set to 1, the conversion result at that time has priority over the first
conversion result. Otherwise, ignore data of the first conversion.
Table 11-2. Settings of ADCS and ADCE
ADCS ADCE A/D Conversion Operation
0 0 Stop status (DC power consumption path does not exist)
0 1 Conversion waiting mode (only A/D voltage comparator consumes power)
1 0 Setting prohibited
1 1 Conversion mode (A/D voltage comparator: enables operation)
Figure 11-5. Timing Chart When A/D voltage Comparator Is Used
ADCE
A/D voltage
comparator
ADCS
Conversion
operation
Conversion
operation
Conversion
stopped
Conversion
waiting
A/D voltage comparator : enables operation
Note
Note To stabilize the internal circuit, the time from the rising of the ADCE bit to the falling of the ADCS bit must be
1
μ
s or longer.
Caution A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and LV0 to values other
than the identical data.
<R>
<R>
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Table 11-3. A/D Conversion Time Selection
(1) 2.7 V ≤ AVREF0 ≤ 5.5 V
A/D Converter Mode Register (ADM) Conversion Time Selection
FR2 FR1 FR0 LV1 LV0 fCLK = 2 MHz fCLK = 10 MHz fCLK = 20 MHz
Conversion Clock
(fAD)
0 0 0 0 0 264/fCLK 26.4
μ
s 13.2
μ
s fCLK/12
0 0 1 0 0 176/fCLK
Setting prohibited
17.6
μ
s 8.8
μ
sNote 1 fCLK/8
0 1 0 0 0 132/fCLK 66.0
μ
sNote 2 13.2
μ
s 6.6
μ
sNote 1 fCLK/6
0 1 1 0 0 88/fCLK 44.0
μ
sNote 2 8.8
μ
sNote 1 fCLK/4
1 0 0 0 0 66/fCLK 33.0
μ
s 6.6
μ
sNote 1 fCLK/3
1 0 1 0 0 44/fCLK 22.0
μ
s fCLK/2
1 1 1 0 0 22/fCLK 11.0
μ
sNote 1
Setting prohibited
Setting prohibited
fCLK
Other than above Setting prohibited
Notes 1. This can be set only when 4.0 V ≤ AVREF0 ≤ 5.5 V.
2. Functionally expanded products (
μ
PD78F116xA) only.
Caution Set the conversion times with the following conditions.
Conventional-specification products (
μ
PD78F116x)
• 4.0 V ≤ AVREF0 ≤ 5.5 V: fAD = 0.6 to 3.6 MHz
• 2.7 V ≤ AVREF0 < 4.0 V: fAD = 0.6 to 1.8 MHz
Functionally expanded products (
μ
PD78F116xA)
• 4.0 V ≤ AVREF0 ≤ 5.5 V: fAD = 0.33 to 3.6 MHz
• 2.7 V ≤ AVREF0 < 4.0 V: fAD = 0.33 to 1.8 MHz
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(2) 2.3 V ≤ AVREF0 ≤ 5.5 V
A/D Converter Mode Register (ADM) Conversion Time Selection
FR2 FR1 FR0 LV1 LV0 fCLK = 2 MHz fCLK = 5 MHz
Conversion Clock
(fAD)
0 0 0 0 1 480/fCLK Setting prohibited fCLK/12
0 0 1 0 1 320/fCLK 64.0
μ
s fCLK/8
0 1 0 0 1 240/fCLK 48.0
μ
s fCLK/6
0 1 1 0 1 160/fCLK
Setting prohibited
32.0
μ
s fCLK/4
1 0 0 0 1 120/fCLK 60.0
μ
s 24.0
μ
sNote 1 fCLK/3
1 0 1 0 1 80/fCLK 40.0
μ
s 16.0
μ
sNote 2 fCLK/2
1 1 1 0 1 40/fCLK 20.0
μ
sNote 2 Setting prohibited fCLK
Other than above Setting prohibited
Notes 1. This can be set only when 2.7 V ≤ AVREF0 ≤ 5.5 V.
2. This can be set only when 4.0 V ≤ AVREF0 ≤ 5.5 V.
Cautions 1. Set the conversion times with the following conditions.
• 4.0 V ≤ AVREF0 ≤ 5.5 V: fAD = 0.6 to 3.6 MHz
• 2.7 V ≤ AVREF0 < 4.0 V: fAD = 0.6 to 1.8 MHz
• 2.3 V ≤ AVREF0 < 2.7 V: fAD = 0.6 to 1.44 MHz
2. When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D conversion
once (ADCS = 0) beforehand.
3. Change LV1 and LV0 from the default value, when 2.3 V ≤ AVREF0 < 2.7 V.
4. The above conversion time does not include clock frequency errors. Select conversion time,
taking clock frequency errors into consideration.
Remark f
CLK: CPU/peripheral hardware clock frequency
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Figure 11-6. A/D Converter Sampling and A/D Conversion Timing
ADCS
Conversion time Conversion time
Sampling
Sampling
timing
INTAD
ADCS ← 1 or ADS rewrite
Sampling
SAR
clear
SAR
clear
Transfer
to ADCR,
INTAD
generation
Successive conversion
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(3) 10-bit A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time
A/D conversion ends, the conversion result is loaded from the successive approximation register. The higher 8
bits of the conversion result are stored in FFF1FH and the lower 2 bits are stored in the higher 2 bits of FFF1EH.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 11-7. Format of 10-Bit A/D Conversion Result Register (ADCR)
Symbol
Address: FFF1FH, FFF1EH After reset: 0000H R
FFF1FH FFF1EH
000000
ADCR
Caution When writing to the A/D converter mode register (ADM), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of ADCR may become
undefined. Read the conversion result following conversion completion before writing to ADM,
ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to
be read.
(4) 8-bit A/D conversion result register (ADCRH)
This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are
stored.
ADCRH can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-8. Format of 8-Bit A/D Conversion Result Register (ADCRH)
Symbol
ADCRH
Address: FFF1FH After reset: 00H R
76543210
Caution When writing to the A/D converter mode register (ADM), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of ADCRH may become
undefined. Read the conversion result following conversion completion before writing to ADM,
ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to
be read.
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(5) Analog input channel specification register (ADS)
This register specifies the input channel of the analog voltage to be A/D converted.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-9. Format of Analog Input Channel Specification Register (ADS)
Address: FFF31H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADS ADISS 0 0 0 ADS3 ADS2 ADS1 ADS0
ADISS ADS3 ADS2 ADS1 ADS0
Analog input
channel
Input source
0 0 0 0 0 ANI0 P20/ANI0 pin
0 0 0 0 1 ANI1 P21/ANI1 pin
× 0 0 1 0 ANI2 P22/ANI2 pin
× 0 0 1 1 ANI3 P23/ANI3 pin
× 0 1 0 0 ANI4 P24/ANI4 pin
× 0 1 0 1 ANI5 P25/ANI5 pin
× 0 1 1 0 ANI6 P26/ANI6 pin
× 0 1 1 1 ANI7 P27/ANI7 pin
× 1 0 0 0 ANI8 P150/ANI8 pin
× 1 0 0 1 ANI9 P151/ANI9 pin
× 1 0 1 0 ANI10 P152/ANI10 pin
× 1 0 1 1 ANI11 P153/ANI11 pin
× 1 1 0 0 ANI12 P154/ANI12 pin
× 1 1 0 1 ANI13 P155/ANI13 pin
× 1 1 1 0 ANI14 P156/ANI14 pin
× 1 1 1 1 ANI15 P157/ANI15 pin
Cautions 1. Be sure to clear bits 4 to 6 to “0”.
2 Set a channel to be used for A/D conversion in the input mode by using port mode registers 2
and 15 (PM2, PM15).
3. Do not set the pin that is set by ADPC as digital I/O by ADS.
Remark ×: don’t care
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(6) A/D port configuration register (ADPC)
This register switches the ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157 pins to analog input of A/D
converter or digital I/O of port.
ADPC can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 10H.
Figure 11-10. Format of A/D Port Configuration Register (ADPC)
Address: F0017H After reset: 10H R/W
Symbol 7 6 5 4 3 2 1 0
ADPC 0 0 0 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
Analog Input (A)/digital I/O (D) switching
Port 15 Port 2
ADP
C4
ADP
C3
ADP
C2
ADP
C1
ADP
C0
ANI15
/P157
ANI14
/P156
ANI13
/P155
ANI12
/P154
ANI11
/P153
ANI10
/P152
ANI9
/P151
ANI8
/P150
ANI7
/P27
ANI6
/P26
ANI5
/P25
ANI4
/P24
ANI3
/P23
ANI2
/P22
ANI1
/P21
ANI0
/P20
0 0 0 0 0 A A A A A A A A A A A A A A A A
0 0 0 0 1 A A A A A A A A A A A A A A A D
0 0 0 1 0 A A A A A A A A A A A A A A D D
0 0 0 1 1 A A A A A A A A A A A A A D D D
0 0 1 0 0 A A A A A A A A A A A A D D D D
0 0 1 0 1 A A A A A A A A A A A D D D D D
0 0 1 1 0 A A A A A A A A A A D D D D D D
0 0 1 1 1 A A A A A A A A A D D D D D D D
0 1 0 0 0 A A A A A A A A D D D D D D D D
0 1 0 0 1 A A A A A A A D D D D D D D D D
0 1 0 1 0 A A A A A A D D D D D D D D D D
0 1 0 1 1 A A A A A D D D D D D D D D D D
0 1 1 0 0 A A A A D D D D D D D D D D D D
0 1 1 0 1 A A A D D D D D D D D D D D D D
0 1 1 1 0 A A D D D D D D D D D D D D D D
0 1 1 1 1 A D D D D D D D D D D D D D D D
1 0 0 0 0 D D D D D D D D D D D D D D D D
Other than above Setting prohibited
Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode registers 2
and 15 (PM2, PM15).
2. Do not set the pin that is set by ADPC as digital I/O by ADS.
3. P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 are set as analog inputs in the order of
P157/ANI15, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port configuration register
(ADPC). When using P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 as analog inputs,
start designing from P157/ANI15.
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(7) Port mode registers 2 and 15 (PM2, PM15)
When using the ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157 pins for analog input port, set PM20 to
PM27 and PM150 to PM157 to 1. The output latches of P20 to P27 and P150 to P157 at this time may be 0 or 1.
If PM20 to PM27 and PM150 to PM157 are set to 0, they cannot be used as analog input port pins.
PM2 and PM15 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Caution If a pin is set as an analog input port, not the pin level but “0” is always read.
Figure 11-11. Format of Port Mode Registers 2 and 15 (PM2, PM15)
Address: FFF22H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20
Address: FFF2FH After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM15 PM157 PM156 PM155 PM154 PM153 PM152 PM151 PM150
PMmn Pmn pin I/O mode selection (m = 2, 15; n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157 pins are as shown below depending on the settings of
ADPC, ADS, PM2, and PM15.
Table 11-4. Setting Functions of ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157 Pins
ADPC PM2 and PM15 ADS ANI0/P20 to ANI7/P27 and
ANI8/P150 to ANI15/P157 Pins
Input mode − Digital input Digital I/O selection
Output mode − Digital output
Selects ANI. Analog input (to be converted) Input mode
Does not select ANI. Analog input (not to be converted)
Selects ANI.
Analog input selection
Output mode
Does not select ANI.
Setting prohibited
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11.4 A/D Converter Operations
11.4.1 Basic operations of A/D converter
<1> Set bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 1 to start the supply of the input clock to the A/D
converter.
<2> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1 to start the operation of the A/D voltage
comparator.
<3> Set channels for A/D conversion to analog input by using the A/D port configuration register (ADPC) and set
to input mode by using port mode registers 2 and 15 (PM2, PM15).
<4> Set A/D conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM.
<5> Select one channel for A/D conversion using the analog input channel specification register (ADS).
<6> Start the conversion operation by setting bit 7 (ADCS) of ADM to 1.
(<7> to <13> are operations performed by hardware.)
<7> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<8> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
sampled voltage is held until the A/D conversion operation has ended.
<9> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to
(1/2) AVREF0 by the tap selector.
<10> The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the
A/D voltage comparator. If the analog input is greater than (1/2) AVREF0, the MSB of SAR remains set to 1. If
the analog input is smaller than (1/2) AVREF0, the MSB is reset to 0.
<11> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series
resistor string voltage tap is selected according to the preset value of bit 9, as described below.
• Bit 9 = 1: (3/4) AVREF0
• Bit 9 = 0: (1/4) AVREF0
The voltage tap and sampled voltage are compared and bit 8 of SAR is manipulated as follows.
• Analog input voltage ≥ Voltage tap: Bit 8 = 1
• Analog input voltage < Voltage tap: Bit 8 = 0
<12> Comparison is continued in this way up to bit 0 of SAR.
<13> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result
value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
<14> Repeat steps <7> to <13>, until ADCS is cleared to 0.
To stop the A/D converter, clear ADCS to 0.
To restart A/D conversion from the status of ADCE = 1, start from <6>. To start A/D conversion again when
ADCE = 0, set ADCE to 1, wait for 1
μ
s or longer, and start <6>. To change a channel of A/D conversion,
start from <5>.
Caution Make sure the period of <2> to <6> is 1
μ
s or more.
Remark Two types of A/D conversion result registers are available.
• ADCR (16 bits): Store 10-bit A/D conversion value
• ADCRH (8 bits): Store 8-bit A/D conversion value
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Figure 11-12. Basic Operation of A/D Converter
Conversion time
Sampling time
Sampling A/D conversion
Undefined Conversion
result
A/D converter
operation
SAR
ADCR
INTAD
Conversion
result
A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM)
is reset (0) by software.
If a write operation is performed to the analog input channel specification register (ADS) during an A/D conversion
operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the
beginning.
Reset signal generation clears the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H.
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11.4.2 Input voltage and conversion results
The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI15) and the
theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following
expression.
SAR = INT ( × 1024 + 0.5)
ADCR = SAR × 64
or
( − 0.5) × ≤ VAIN < ( + 0.5) ×
where, INT( ): Function which returns integer part of value in parentheses
V
AIN: Analog input voltage
AVREF0: AVREF0 pin voltage
ADCR: A/D conversion result register (ADCR) value
SAR: Successive approximation register
Figure 11-13 shows the relationship between the analog input voltage and the A/D conversion result.
Figure 11-13. Relationship Between Analog Input Voltage and A/D Conversion Result
1023
1022
1021
3
2
1
0
FFC0H
FF80H
FF40H
00C0H
0080H
0040H
0000H
A/D conversion result
SAR ADCR
1
2048
1
1024
3
2048
2
1024
5
2048
Input voltage/AV
REF0
3
1024
2043
2048
1022
1024
2045
2048
1023
1024
2047
2048
1
VAIN
AVREF0
AVREF0
1024
AVREF0
1024
ADCR
64
ADCR
64
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11.4.3 A/D converter operation mode
The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to
ANI15 by the analog input channel specification register (ADS) and A/D conversion is executed.
(1) A/D conversion operation
By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the
voltage, which is applied to the analog input pin specified by the analog input channel specification register
(ADS), is started.
When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result
register (ADCR), and an interrupt request signal (INTAD) is generated. When one A/D conversion has been
completed, the next A/D conversion operation is immediately started.
If ADS is rewritten during A/D conversion, the A/D conversion operation under execution is stopped and restarted
from the beginning.
If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. At this time, the
conversion result immediately before is retained.
Figure 11-14. A/D Conversion Operation
ANIn
Rewriting ADM
ADCS = 1 Rewriting ADS ADCS = 0
ANIn
ANIn ANIn ANIm
ANIn ANIm ANIm
Stopped
Conversion result
immediately before
is retained
A/D conversion
ADCR,
ADCRH
INTAD
Conversion is stopped
Conversion result immediately
before is retained
Remarks 1. n = 0 to 15
2. m = 0 to 15
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The setting methods are described below.
<1> Set bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 1.
<2> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.
<3> Set the channel to be used in the analog input mode by using bits 4 to 0 (ADPC4 to ADPC0) of the A/D
port configuration register (ADPC) and bits 7 to 0 (PM27 to PM20) of port mode register 2 (PM2) and
bits 7 to 0 (PM157 to PM150) of port mode register 15 (PM15).
<4> Select conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM.
<5> Select a channel to be used by using bits 7 and 3 to 0 (ADISS, ADS3 to ADS0) of the analog input
channel specification register (ADS).
<6> Set bit 7 (ADCS) of ADM to 1 to start A/D conversion.
<7> When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated.
<8> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).
<Change the channel>
<9> Change the channel using bits 7 and 3 to 0 (ADISS, ADS3 to ADS0) of ADS to start A/D conversion.
<10> When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated.
<11> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).
<Complete A/D conversion>
<12> Clear ADCS to 0.
<13> Clear ADCE to 0.
<14> Clear bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 0.
Cautions 1. Make sure the period of <2> to <6> is 1
μ
s or more.
2. <2> may be done between <3> and <5>.
3. The period from <7> to <10> differs from the conversion time set using bits 5 to 1 (FR2 to
FR0, LV1, LV0) of ADM. The period from <9> to <10> is the conversion time set using
FR2 to FR0, LV1, and LV0.
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11.5 Temperature Sensor Function (Expanded-Specification Products (
μ
PD78F116xA) Only)
A temperature sensor performs A/D conversion for two voltages, an internal reference voltage (sensor 0 on the
ANI0 side) that depends on the temperature and an internal reference voltage (sensor 1 on the ANI1 side) that does
not depend on the temperature, and calculations, so that the temperature is obtained without depending on the AVREF0
voltage (AVREF0 ≥ 2.7 V).
Caution The temperature sensor cannot be used when low current consumption mode is set (RMC = 5AH)
or when the internal high-speed oscillator has been stopped (HIOSTOP = 1 (bit 0 of CSC
register)). The temperature sensor can operate as long as the internal high-speed oscillator
operates (HIOSTOP = 0), even if it is not selected as the CPU/peripheral hardware clock source.
11.5.1 Configuration of temperature sensor
The temperature sensor consists of an A/D converter and the following hardware.
• Temperature sensor 0: Outputs the internal reference voltage that depends on the temperature
• Temperature sensor 1: Outputs the internal reference voltage that does not depend on the temperature
Figure 11-15. Temperature Sensor Block Diagram
INTAD
ADCS FR2 FR1 ADCEFR0
Sample & hold circuit
AV
SS
A/D Voltage comparator
A/D converter mode
register (
ADM)
Internal bus
4
Analog input channel
specification register (ADS)
Selector
(Analog input for normal
use of A/D converter)
ANI0/P20
Temperature sensor 0
Controller
A/D conversion result
register (ADCR)
Successive
approximation
register (SAR)
LV1 LV0
5
ADS3 ADS2 ADS1 ADS0
ADISS
AV
REF0
AV
SS
ADCS bit
Tap selector
ANI1/P21
Selector
Selector
Temperature sensor 1
(Analog input for normal
use of A/D converter)
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11.5.2 Registers used by temperature sensors
The following four types of registers are used when using a temperature sensor.
• Peripheral enable register 0 (PER0)
• A/D converter mode register (ADM)
• Analog input channel specification register (ADS)
• 10-bit A/D conversion result register (ADCR)
Caution Setting of the A/D port configuration register (ADPC), port mode register 2 (PM2) and port
register 2 (P2) is not required when using the temperature sensor. There is no problem if the
pin function is set as digital I/O.
(1) Peripheral enable register 0 (PER0)
Use the PER0 register in the same manner as during A/D converter basic operation (see 11.3 (1) Peripheral
enable register 0 (PER0)).
(2) A/D converter mode register (ADM)
Use the ADM register in the same manner as during A/D converter basic operation (see 11.3 (2) A/D
converter mode register (ADM)).
However, selection of the A/D conversion time when a temperature sensor is used varies as shown in Table 11-
5.
Table 11-5. Selection of A/D Conversion Time When Using Temperature Sensor
(1) 2.7 V ≤ AVREF0 ≤ 5.5 V
A/D Converter Mode Register (ADM) Conversion Time Selection
FR2 FR1 FR0 LV1 LV0 fCLK = 2 MHz fCLK = 8 MHz fCLK = 20 MHz
Conversion Clock
(fAD)
0 0 0 0 1 480/fCLK 60.0
μ
s 24.0
μ
s fCLK/12
0 0 1 0 1 320/fCLK 40.0
μ
s fCLK/8
0 1 0 0 1 240/fCLK 30.0
μ
s fCLK/6
0 1 1 0 1 160/fCLK
Setting prohibited
fCLK/4
1 0 0 0 1 120/fCLK 60.0
μ
s fCLK/3
1 0 1 0 1 80/fCLK 40.0
μ
s fCLK/2
1 1 1 0 1 40/fCLK Setting prohibited
Setting prohibited
Setting prohibited
fCLK
Other than above Setting prohibited
Cautions 1. Set the conversion times so as to satisfy the following condition.
f
AD = 0.6 to 1.8 MHz
2. When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D conversion
(ADCS = 0) beforehand.
3. The above conversion time does not include clock frequency errors. Select conversion time,
taking clock frequency errors into consideration.
Remark f
CLK: CPU/peripheral hardware clock frequency
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(3) 10-bit A/D conversion result register (ADCR)
Use the ADCR register in the same manner as during A/D converter basic operation (see 11.3 (3) 10-bit A/D
conversion result register (ADCR)).
Caution When using a temperature sensor, use the result of the second or later A/D conversion for
temperature sensor 0 (ANI0 side), and the result of the third or later A/D conversion for
temperature sensor 1 (ANI1 side).
(4) Analog input channel specification register (ADS)
This register specifies the channel from which an analog voltage to be A/D-converted is input, in the same
manner as during A/D converter basic operation. When a temperature sensor is used, however, some settings
differ from those of A/D converter basic operation.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-16. Format of Analog Input Channel Specification Register (ADS) When Using Temperature Sensor
Address: FFF31H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADS ADISS 0 0 0 ADS3 ADS2 ADS1 ADS0
ADISS ADS3 ADS2 ADS1 ADS0
Analog input
channel
Input source
1 0 0 0 0 ANI0
Temperature sensor 0 output
1 0 0 0 1 ANI1
Temperature sensor 1 output
Other than above Setting prohibited
Caution Be sure to clear bits 4 to 6 to “0”.
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11.5.3 Temperature sensor operation
(1) Temperature sensor detection value
When using a temperature sensor, determine as reference temperatures two points of temperature (high and
low) in the temperature range to be used, and measure the result of A/D conversion with temperature sensors
0 and 1 at each reference temperature in advance. Perform the measurement in the same environment as the
one in which the temperature sensor is used in a set.
By using an expression of temperature sensor detection value characteristics, which are obtained from the
values of high and low reference temperatures and the result of A/D conversion with temperature sensors 0
and 1 at an arbitrary temperature, the temperature at that time can be obtained.
Remark The value obtained from the ratio of the results of A/D conversion with a sensor that depends/does
not depend on temperature is called a “temperature sensor detection value”.
• Sensor that depends on temperature
Conversion channel: temperature sensor 0 (ANI0 side)
A/D conversion result: ADT0
• Sensor that does not depend on temperature
Conversion channel: temperature sensor 1 (ANI1 side)
A/D conversion result: ADT1
• Temperature sensor detection value = KTV = ADT0
ADT1 × 256
The characteristics (reference value) of the temperature sensor detection value are as follows.
Figure 11-17. Characteristics of Temperature Sensor Detection Value (Reference Value)
Characteristics of temperature sensor detection value
50
60
70
80
90
100
110
120
130
−40
˚C
25
˚C
85
˚C
Temperature (TA)
Temperature Sensor Detection Value
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(2) How to calculate temperature
As shown in Figure 11-17, the temperature sensor detection value makes a characteristics curve that is linear
with respect to the temperature. Therefore, the temperature sensor detection value can be expressed with the
following expressions.
Temperature sensor detection value ≅ Tilt × (TNOW − TBASE1) + Offset
KTVNOW ≅ (KTVBASE2 − KTVBASE1)
(TBASE2 − TBASE1) × (TNOW − TBASE1) + KTVBASE1
TBASE1: Low reference temperature, TBASE2: High reference temperature
TNOW: Temperature during sensor operation
KTVBASE1: Temperature sensor detection value at a low reference temperature
KTVBASE2: Temperature sensor detection value at a high reference temperature
KTVNOW: Temperature sensor detection value during temperature measurement
When ADT0BASE1: Result of A/D conversion (sensor 0) at a low reference temperature
ADT1BASE1: Result of A/D conversion (sensor 1) at a low reference temperature
ADT0BASE2: Result of A/D conversion (sensor 0) at a high reference temperature
ADT1BASE2: Result of A/D conversion (sensor 1) at a high reference temperature
ADT0NOW: Result of A/D conversion (sensor 0) during temperature measurement
ADT1NOW: Result of A/D conversion (sensor 1) during temperature measurement
KTVBASE1, KTVBASE2, and KTVNOW are obtained as follows.
KTVBASE1 = ADT0BASE1
ADT1BASE1 × 256
KTVBASE2 = ADT0BASE2
ADT1BASE2 × 256
KTVNOW = ADT0NOW
ADT1NOW × 256
Thus, temperature TNOW is obtained by using the following expressions.
TNOW ≅ (KTVNOW − KTVBASE1) × (TBASE2 − TBASE1)
(KTVBASE2 − KTVBASE1) + TBASE1
ADT1BASE2 × (ADT1BASE1 × ADT0NOW − ADT0BASE1 × ADT1NOW) × (TBASE2 − TBASE1)
TNOW ≅
ADT1NOW × (ADT1BASE1 × ADT0BASE2 − ADT0BASE1 × ADT1BASE2)
+ TBASE1
Remarks 1. When obtaining a temperature through calculation, it is recommended to determine the
upper and lower end of the temperature range as the reference temperatures for
measurement.
2. In addition to calculation, temperature TNOW can also be obtained by measuring the
temperature sensor detection values at each temperature in advance, preparing them as
table data, and comparing them with the temperature sensor detection value during
temperature measurement. With this method, table data must be created for each interval
of temperatures to be detected.
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11.5.4 Procedures for using temperature sensors
(1) Procedure for using temperature sensors
<1> Perform the following steps in the same environment as the one in which the temperature sensor is used
in a set
• When obtaining a temperature through calculation
Determine as reference temperatures two points of temperature (high and low) in the temperature
range to be used, and measure the result of A/D conversion with temperature sensors 0 and 1 at
the reference temperature in advance, before shipment of the set.
• When obtaining a temperature through table reference
Measure the temperature sensor detection values at each temperature in advance, and prepare
them as table data.
Store the above values into the internal flash memory area by means such as writing them via self
programming, or store them into an external memory.
Remark When obtaining the temperature through calculation and the result of A/D conversion by
temperature sensors 0 and 1 at a high and low temperature, it is recommended to determine
the upper and lower end of the temperature range as the reference temperatures for
measurement.
<2> To obtain a temperature, perform A/D conversion for the voltage output from temperature sensors 0 and
1 and calculation by using the expression based on ADT0 and ADT1, or calculate the temperature
sensor detection value and compare it with table data prepared in advance.
(2) Procedure for obtaining ADT0 and ADT1 of temperature sensors 0 and 1
(ADT0BASE1, ADT1BASE1, ADT0BASE2 and ADT1BASE2 at reference temperatures, ADT0NOW and ADT1NOW during
temperature measurement)
<Initial setting for A/D conversion>
<1> Set bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 1.
<2> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.
<3> Select the conversion time by using bits 5 to 1 (FR2 to FR0, LV1 and LV0) of ADM.
<Measurement by temperature sensor 0>
<4> Set the analog input channel specification register (ADS) to “80H” to select temperature sensor 0.
<5> Set bit 7 (ADCS) of ADM to 1 to start A/D conversion operation.
<6> The first A/D conversion ends and an interrupt request signal (INTAD) occurs.
<7> The second A/D conversion ends and an interrupt request signal (INTAD) occurs.
<8> Read A/D conversion data (ADT0) from the A/D conversion result register (ADCR).
<Measurement by temperature sensor 1>
<9> Set the analog input channel specification register (ADS) to “81H” to select temperature sensor 1.
<10> The first A/D conversion ends and an interrupt request signal (INTAD) occurs.
<11> The second A/D conversion ends and an interrupt request signal (INTAD) occurs.
<12> The third A/D conversion ends and an interrupt request signal (INTAD) occurs.
<13> Read A/D conversion data (ADT1) from the A/D conversion result register (ADCR).
(The procedure is continued on the next page.)
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<Obtaining temperature TNOW>
<14> Calculate the temperature by using either of the following methods.
• When obtaining a temperature through calculation
During measurement at reference temperatures, write ADT0 and ADT1 to the internal flash memory
by means such as self programming. During actual measurement, calculate the current temperature
TNOW by using the following expression, based on ADT0 and ADT1 at that time.
ADT1BASE2 × (ADT1BASE1 × ADT0NOW − ADT0BASE1 × ADT1NOW) × (TBASE2 − TBASE1)
TNOW ≅
ADT1NOW × (ADT1BASE1 × ADT0BASE2 − ADT0BASE1 × ADT1BASE2)
+ TBASE1
• When obtaining a temperature through table reference
Measure and calculate the temperature sensor detection values (ADT0/ADT1 × 256) based on ADT0
and ADT1 at each temperature interval. Set the temperature corresponding to that value as table
data, and write it to the internal flash memory by means such as self programming.
During actual measurement, calculate the temperature sensor detection value (ADT0/ADT1 × 256)
based on ADT0 and ADT1 at that time, compare it with the value of table data, and obtain the current
temperature TNOW.
<Finishing A/D conversion>
<15> Clear ADCS to 0.
<16> Clear ADCE to 0.
<17> Clear bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 0.
Cautions 1. Make sure the period of <2> to <5> is 1
μ
s or more. If ADCS is set to 1 within 1
μ
s,
the result of the third and later conversion becomes valid on the sensor 0 side.
2. <2> can be done between <3> and <4>.
3. The period from <7> to <10> differs from the conversion time set using bits 5 to 1
(FR2 to FR0, LV1, LV0) of ADM. The period from <9> to <10> is the conversion time
set using FR2 to FR0, LV1, and LV0.
4. Do not change the AVREF0 voltage during <4> to <13>. Although the temperature
sensor detection value does not depend on the AVREF0 voltage and thus there is no
problem even if the AVREF0 voltage varies at every temperature measurement, it
must be stable during a measurement cycle (from <4> to <13>).
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Figure 11-18. Flowchart of Procedure for Using Temperature Sensor
ADCEN of PER0 register = 1
START
END
No INTAD occurred?
Starts the supply of the
input clock to A/D converter
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10>
<11>
<12>
<13>
<14>
<15>
<16>
<17>
Starts the operation of
the comparator
Sets conversion time
Select temperature
sensor 0 as input source
Yes
No INTAD occurred?
Yes
ADCE of ADM register = 1
Starts A/D conversion
operation
First A/D conversion
First A/D conversion
Second A/D conversion
Third A/D conversion
Second A/D conversion
Read A/D conversion
result (ADT0)
ADCS of ADM register = 1
Stops A/D conversion
operation
ADCS = 0
Stops the operation of
the comparator
ADCE = 0
Stops the supply of the
input clock to A/D converter
ADCEN = 0
Read ADCR register
ADM ← 00XXX011B
ADS ← 80H No INTAD occurred?
Select temperature
sensor 1 as input source
Yes
No INTAD occurred?
Yes
No INTAD occurred?
Yes
Read A/D conversion
result (ADT1)
Read ADCR register
Obtain the current temperature
(T
NOW
) by calculation
(see 11.5.3 (2)) or table reference
ADS ← 81H
Caution Use the result of the second or later A/D conversion for temperature sensor 0 (ANI0 side), and
the result of the third or later A/D conversion for temperature sensor 1 (ANI1 side).
Remark Steps <1> to <17> in Figure 11-18 correspond to steps <1> to <17> in 11.5.4 (2) Procedure for
obtaining ADT0 and ADT1 of temperature sensors 0 and 1.
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11.6 How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained.
(1) Resolution
This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input
voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the
full scale is expressed by %FSR (Full Scale Range).
1LSB is as follows when the resolution is 10 bits.
1LSB = 1/210 = 1/1024
= 0.098%FSR
Accuracy has no relation to resolution, but is determined by overall error.
(2) Overall error
This shows the maximum error value between the actual measured value and the theoretical value.
Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of
these express the overall error.
Note that the quantization error is not included in the overall error in the characteristics table.
(3) Quantization error
When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter, an
analog input voltage in a range of ±1/2LSB is converted to the same digital code, so a quantization error cannot
be avoided.
Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral
linearity error, and differential linearity error in the characteristics table.
Figure 11-19. Overall Error Figure 11-20. Quantization Error
Ideal line
0......0
1......1
Digital output
Overall
error
Analog input
AV
REF0
0
0......0
1......1
Digital output
Quantization error
1/2LSB
1/2LSB
Analog input
0AV
REF0
(4) Zero-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (1/2LSB) when the digital output changes from 0......000 to 0......001.
If the actual measurement value is greater than the theoretical value, it shows the difference between the actual
measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output
changes from 0……001 to 0……010.
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(5) Full-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111.
(6) Integral linearity error
This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It
expresses the maximum value of the difference between the actual measurement value and the ideal straight line
when the zero-scale error and full-scale error are 0.
(7) Differential linearity error
While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value
and the ideal value.
Figure 11-21. Zero-Scale Error Figure 11-22. Full-Scale Error
111
011
010
001 Zero-scale error
Ideal line
000
012 3 AV
REF0
Digital output (Lower 3 bits)
Analog input (LSB)
111
110
101
000
0
AV
REF0
− 3
Full-scale error
Ideal line
Analog input (LSB)
Digital output (Lower 3 bits)
AV
REF0
− 2AV
REF0
− 1
AV
REF0
Figure 11-23. Integral Linearity Error Figure 11-24. Differential Linearity Error
0
AV
REF0
Digital output
Analog input
Integral linearity
error
Ideal line
1......1
0......0
0
AV
REF0
Digital output
Analog input
Differential
linearity error
1......1
0......0
Ideal 1LSB width
(8) Conversion time
This expresses the time from the start of sampling to when the digital output is obtained.
The sampling time is included in the conversion time in the characteristics table.
(9) Sampling time
This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.
Sampling
time Conversion time
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11.7 Cautions for A/D Converter
(1) Operating current in STOP mode
Shift to STOP mode after clearing the A/D converter (by clearing bit 7 (ADCS) of the A/D converter mode register
(ADM) to 0). The operating current can be reduced by clearing bit 0 (ADCE) of the A/D converter mode register
(ADM) to 0 at the same time.
To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start
operation.
(2) Reducing current when A/D converter is stopped
Be sure that the voltage to be applied to AVREF0 normally satisfies the conditions stated in Table 11-1.
If bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) are set to 0, the current will not be
increased by the A/D converter even if a voltage is applied to AVREF0, while the A/D converter is stopped. If a
current flows from the power supply that supplies a voltage to AVREF0 to an external circuit of the microcontroller
as shown in Figure 11-25, AVREF0 = 0 V = AVSS can be achieved and the external current can be reduced by
satisfying the following conditions.
Set the following states before setting AVREF0 = 0 V.
• Set ADCS and ADCE of the A/D converter mode register (ADM) to 0.
• Set the port mode registers (PM20 to PM27 and PM150 to PM157) of the digital I/O pins to 1 to set to input
mode, or set the digital I/O pins to low-level output (high-level output disabled) by setting the port mode
registers (PM20 to PM27 and PM150 to PM157) and port registers (P20 to P27 and P150 to P157) to 0 to
set to output mode.
• Make sure that no voltage is applied to all any of the analog or digital pins (P20/ANI0 to P27/ANI7 and
P150/ANI8 to P157/ANI15) (set to 0 V).
Do not perform the following operation when AVREF0 = 0 V.
• Do not access the port registers (P20 to P27 and P150 to P157) or port mode registers (PM20 to PM27 and
PM150 to PM157) by using instructions or via DMA transfer.
Figure 11-25. Example of Circuit Where Current Flows to External Circuit
AVREF0
ANI0 to ANI15
Current flowing from power
supply supplying voltage to
AVREF0 to external circuit
When restarting the A/D converter, operate it after the AVREF0 voltage rises and stabilizes and setting ADCE = 1
(see 11.4.1 Basic operations of A/D converter for the procedure for setting the A/D converter operation).
Access digital ports after the AVREF0 voltage has risen and stabilized.
Stop the conversion performed by the D/A converter when the AVREF0 voltage is rising or falling.
<R>
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(3) Input range of ANI0 to ANI15
Observe the rated range of the ANI0 to ANI15 input voltage. If a voltage of AVREF0 or higher and AVSS or lower
(even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that
channel becomes undefined. In addition, the converted values of the other channels may also be affected.
(4) Conflicting operations
<1> Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR or ADCRH read by
instruction upon the end of conversion
ADCR or ADCRH read has priority. After the read operation, the new conversion result is written to ADCR
or ADCRH.
<2> Conflict between ADCR or ADCRH write and A/D converter mode register (ADM) write, analog input
channel specification register (ADS), or A/D port configuration register (ADPC) write upon the end of
conversion
ADM, ADS, or ADPC write has priority. ADCR or ADCRH write is not performed, nor is the conversion end
interrupt signal (INTAD) generated.
(5) Noise countermeasures
To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF0 pin and pins ANI0 to ANI15.
<1> Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply.
<2> The higher the output impedance of the analog input source, the greater the influence. To reduce the
noise, connecting external C as shown in Figure 11-26 is recommended.
<3> Do not switch these pins with other pins during conversion.
<4> The accuracy is improved if the HALT mode is set immediately after the start of conversion.
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Figure 11-26. Analog Input Pin Connection
Reference
voltage
input
C = 100 to 1,000 pF
If there is a possibility that noise equal to or higher than AV
REF0
or
equal to or lower than AV
SS
may enter, clamp with a diode with a
small V
F
value (0.3 V or lower).
AV
REF0
AV
SS
V
SS
ANI0 to ANI15
(6) ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI15/P157
<1> The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27).
The analog input pins (ANI8 to ANI15) are also used as input port pins (P150 to P157).
When A/D conversion is performed with any of ANI0 to ANI15 selected, do not access P20 to P27 and
P150 to P157 while conversion is in progress; otherwise the conversion resolution may be degraded. It is
recommended to select pins used as P20 to P27 and P150 to P157 starting with the ANI0/P20 that is the
furthest from AVREF0.
<2> If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected
value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to
the pins adjacent to the pin undergoing A/D conversion.
(7) Input impedance of ANI0 to ANI15 pins
This A/D converter charges a sampling capacitor for sampling during sampling time.
Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the
capacitor flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling
is in progress, and on the other states.
To make sure that sampling is effective, however, it is recommended to keep the output impedance of the analog
input source to within 10 kΩ, and to connect a capacitor of about 100 pF to the ANI0 to ANI15 pins (see Figure
11-26).
(8) AVREF0 pin input impedance
A series resistor string of several tens of kΩ is connected between the AVREF0 and AVSS pins.
Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to
the series resistor string between the AVREF0 and AVSS pins, resulting in a large reference voltage error.
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(9) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the
pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time,
when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-
change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed.
Figure 11-27. Timing of A/D Conversion End Interrupt Request Generation
ADS rewrite
(start of ANIn conversion)
A/D conversion
ADCR
ADIF
ANIn ANIn ANIm ANIm
ANIn ANIn ANIm ANIm
ADS rewrite
(start of ANIm conversion)
ADIF is set but ANIm conversion
has not ended.
Remarks 1. n = 0 to 15
2. m = 0 to 15
(10) Conversion results just after A/D conversion start
The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the
ADCS bit is set to 1 within 1
μ
s after the ADCE bit was set to 1. Take measures such as polling the A/D
conversion end interrupt request (INTAD) and removing the first conversion result.
(11) A/D conversion result register (ADCR, ADCRH) read operation
When a write operation is performed to the A/D converter mode register (ADM), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR and ADCRH may
become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and
ADPC. Using a timing other than the above may cause an incorrect conversion result to be read.
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(12) Internal equivalent circuit
The equivalent circuit of the analog input block is shown below.
Figure 11-28. Internal Equivalent Circuit of ANIn Pin
ANIn
C1 C2
R1
Table 11-6. Resistance and Capacitance Values of Equivalent Circuit (Reference Values)
AVREF0 R1 C1 C2
4.0 V ≤ VDD ≤ 5.5 V 8.1 kΩ 8 pF 5 pF
2.7 V ≤ VDD < 4.0 V 31 kΩ 8 pF 5 pF
2.3 V ≤ VDD < 2.7 V 381 kΩ 8 pF 5 pF
Remarks 1. The resistance and capacitance values shown in Table 11-6 are not guaranteed values.
2. n = 0 to 15
(13) Starting the A/D converter
Start the A/D converter after the AVREF0 and AVREF1 voltages (the reference voltages for the D/A converter)
stabilize.
<R>
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CHAPTER 12 D/A CONVERTER
12.1 Function of D/A Converter
The D/A converter has a resolution of 8 bits and converts an input digital signal into an analog signal. It is
configured so that output analog signals of two channels (ANO0 and ANO1) can be controlled. The D/A converter has
the following features.
{ 8-bit resolution × 2 channels
{ R-2R ladder method
{ Output analog voltage: AVREF1 × m/256 (AVREF1: Reference voltage for D/A converter, m: Value set to DACSn
register)
{ Operation mode: Normal mode/real-time output mode
Remark n = 0, 1
12.2 Configuration of D/A Converter
The configuration of the D/A converter is shown below.
Figure 12-1. Block Diagram of D/A Converter
8-bit D/A conversion value
setting register 1 (DACS1)
Write signal of DACS0 register
DAMD0 of DAM register
INTTM04 signal
8-bit D/A conversion value
setting register 0 (DACS0)
DACE0 of DAM register
AVREF1 pin
AVSS pin
Selector
Selector
ANO0/P110 pin
ANO1/P111 pin
DACE1 of DAM register
Write signal of DACS1 register
DAMD1 of DAM register
INTTM05 signal
Remarks 1. INTTM04 and INTTM05 are timer trigger signals (interrupt signals from timer channels 4 and 5) that
are used in the real-time output mode.
2. Channel 0 and channel 1 of the D/A converter share the AVREF1 pin.
3. Channel 0 and channel 1 of the D/A converter share the AVSS pin. The AVSS pin is also shared with
the A/D converter.
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The D/A converter includes the following hardware.
Table 12-1. Configuration of D/A Converter
Item Configuration
Control registers Peripheral enable register 0 (PER0)
D/A converter mode register (DAM)
8-bit D/A conversion value setting registers 0, 1 (DACS0, DACS1)
(1) AVREF1 pin
This is the D/A converter reference voltage input pin and the positive power supply pin of P110, P111, and the
D/A converter.
The voltage that can be supplied to AVREF1 varies as follows, depending on whether the P110/ANO0 and
P111/ANO1 pins are used as digital I/Os or analog outputs.
Table 12-2. AVREF1 Voltage Applied to P110/ANO0 and P111/ANO1 Pins
Analog/Digital VDD Condition AVREF1 Voltage
Using at least one pin as an analog output and using all
pins not as digital I/Os
1.8 V ≤ VDD ≤ 5.5 V 1.8 V ≤ AVREF1 ≤ VDD = EVDD0 = EVDD1
2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ AVREF1 ≤ VDD = EVDD0 = EVDD1
Pins used as analog outputs and digital I/Os are
mixedNote 1.8 V ≤ VDD < 2.7 V AVREF1 has same potential as EVDD0,
EVDD1, and VDD
2.7 V ≤ VDD ≤ 5.5 V 2.7 V ≤ AVREF1 ≤ VDD = EVDD0 = EVDD1
Using at least one pin as a digital I/O and using all pins
not as analog outputsNote 1.8 V ≤ VDD < 2.7 V AVREF1 has same potential as EVDD0,
EVDD1, and VDD
Note AVREF1 is the reference for the I/O voltage of a port to be used as a digital port.
• High-/low-level input voltage (VIH5/VIL5)
• High-/low-level output voltage (VOH2/VOL2)
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12.3 Registers Used in D/A Converter
The D/A converter uses the following registers.
• Peripheral enable register 0 (PER0)
• D/A converter mode register (DAM)
• 8-bit D/A conversion value setting registers 0, 1 (DACS0, DACS1)
• Port mode register 11 (PM11)
• Port register 11 (P11)
(1) Peripheral enable register 0 (PER0)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro
that is not used is stopped in order to reduce the power consumption and noise.
When the D/A converter is used, be sure to set bit 6 (DACEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 12-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> 1 <0>
PER0 RTCEN DACEN ADCEN IIC0EN SAU1EN SAU0EN 0 TAU0EN
DACEN Control of D/A converter input clock
0 Stops supply of input clock.
• SFR used by the D/A converter cannot be written.
• The D/A converter is in the reset status.
1 Supplies input clock.
• SFR used by the D/A converter can be read/written.
Cautions 1. When setting the D/A converter, be sure to set DACEN to 1 first. If DACEN = 0, writing to a
control register of the D/A converter is ignored, and, even if the register is read, only the
default value is read (except for port mode register 11 (PM11) and port register 11 (P11)).
2. Be sure to clear bit 1 of the PER0 register to 0.
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(2) D/A converter mode register (DAM)
This register controls the operation of the D/A converter.
DAM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 12-3. Format of D/A Converter Mode Register (DAM)
Address: FFF32H After reset: 00H R/W
Symbol 7 6 <5> <4> 3 2 1 0
DAM 0 0 DACE1 DACE0 0 0 DAMD1 DAMD0
DACEn Control of D/A conversion operation (n = 0, 1)
0 Stops conversion operation
1 Enables conversion operation
DAMDn Selection of D/A converter operation mode (n = 0, 1)
0 Normal mode
1 Real-time output mode
(3) 8-bit D/A conversion value setting registers 0 and 1 (DACS0, DACS1)
These registers are used to set an analog voltage value to be output to the ANO0 and ANO1 pins.
DACS0 and DACS1 can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 12-4. Format of 8-Bit D/A Conversion Value Setting Registers 0 and 1 (DACS0, DACS1)
Address: FFF1CH, FFF1DH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
DACSn DACSn7 DACSn6 DACSn5 DACSn4 DACSn3 DACSn2 DACSn1 DACSn0
Remark n = 0, 1
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(4) Port mode register 11 (PM11)
This register sets the input or output of port 11 in 1-bit units.
When using the P110/ANO0 and P111/ANO1 pins as the analog output function of the D/A converter, set both
PM110 and PM111 to 1. The output latches of P110 and P111 at this time may be 0 or 1.
PM11 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 12-5. Format of Port Mode Register 11 (PM11)
Address: FFF2BH After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM11 1 1 1 1 1 1 PM111 PM110
PM11n P11n pin I/O mode selection (n = 0, 1)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
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12.4 Operation of D/A Converter
12.4.1 Operation in normal mode
D/A conversion is performed using write operation to the DACSn register as the trigger. The setting method is
described below.
<1> Set the DAMDn bit of the DAM register to 0 (normal mode).
<2> Set the analog voltage value to be output to the ANOn pin to the DACSn register.
Steps <1> and <2> above constitute the initial settings.
<3> Set the DACEn bit of the DAM register to 1 (D/A conversion enable).
D/A conversion starts and the analog voltage set in <2> is output to the ANOn pin when this setting is
performed.
The output level, however, is determined when the settling time elapses after D/A conversion starts.
<4> To perform subsequent D/A conversions, write to the DACSn register.
D/A conversion starts and an analog voltage is output to the ANOn pin when one fCLK clock elapses after the
write operation. The output level, however, is determined when the settling time elapses after D/A conversion
starts.
The previous D/A conversion result is held until the next D/A conversion is performed.
When the DACEn bit of the DAM register is set to 0 (D/A conversion operation stop), analog voltage output is
stopped, and the P110/ANO0 and P111/ANO1 pins can be used in port mode. At this time, the P110/ANO0
and P111/ANO1 pins are at high impedance because the PM11n bit of the PM11 register is 1 (input mode).
The set value of the P11 register is output by setting the PM11n bit to 0 (output mode).
Caution Make the interval for writing DACSn of the same channel by one clock longer than fCLK. If writing
is successively performed, only the value written last will be converted.
Remarks 1. n = 0, 1
2. fCLK: CPU/peripheral hardware clock
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12.4.2 Operation in real-time output mode
D/A conversion is performed using the interrupt request signals (INTTM04 and INTTM05) of timer channel 4 and
timer channel 5 as triggers.
The setting method is described below.
<1> Set the DAMDn bit of the DAM register to 1 (real-time output mode).
<2> Set the analog voltage value to be output to the ANOn pin to the DACSn register.
<3> Set the DACEn bit of the DAM register to 1 (D/A conversion enable).
Steps <1> to <3> above constitute the initial settings.
<4> Operate timer channel 4 and timer channel 5.
<5> D/A conversion starts and the analog voltage set in <2> is output to the ANOn pin when the INTTM04 and
INTTM05 signals are generated.
The output level, however, is determined when the settling time elapses after D/A conversion starts.
<6> After that, the value set in the DACSn register is output every time the INTTM04 and INTTM05 signals are
generated.
Set the analog voltage value to be output to the ANOn pin to the DACSn register before the next D/A
conversion is started (INTTM04 and INTTM05 signals are generated).
When the DACEn bit of the DAM register is set to 0 (D/A conversion operation stop), analog voltage output is
stopped, and the P110/ANO0 and P111/ANO1 pins can be used in port mode. At this time, the P110/ANO0
and P111/ANO1 pins are at high impedance because the PM11n bit of the PM11 register is 1 (input mode).
The set value of the P11 register is output by setting the PM11n bit to 0 (output mode).
D/A conversion starts by setting the DACEn bit, as described in <3>, and an analog voltage is output to the ANOn
pin, but the output value of the ANOn pin up to <5> is undefined. An arbitrary value, however, can be output in <3> by
performing the following settings before performing the setting in <1>.
i. Set the DAMDn bit of the DAM register to 0 (normal mode).
ii. Set the voltage value output from the ANOn pin in <3> to the DACSn register.
iii. Afterward, perform <1> to <3>.
Consequently, the value set in ii can be output in <3>. The output level, however, is determined when the
settling time elapses after D/A conversion starts.
Cautions 1. Make the interval for generating a start trigger to the same channel by one clock longer than
fCLK. If a start trigger is successively generated for every fCLK, D/A conversion will be
performed only at the first trigger.
2. Note the following points in the procedure (i to iii) for outputting an arbitrary value in <3>.
• Do not generate the start trigger of the real-time output mode before enabling D/A
conversion operation in <3> after the value is set to the DACSn register in ii.
• An arbitrary value cannot be output in <3> if the DACEN bit of the PER0 register is cleared
once after the value is set to the DACSn register in ii.
Remarks 1. For the output values of the ANO0 and ANO1 pins in the HALT and STOP modes, see CHAPTER 19
STANDBY FUNCTION.
2. n = 0, 1
3. fCLK: CPU/peripheral hardware clock
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12.4.3 Cautions
Observe the following cautions when using the D/A converter of the 78K0R/KG3.
(1) The digital port I/O function, which is the alternate function of the ANO0 and ANO1 pins, does not operate during
D/A conversion.
During D/A conversion, 0 is read from the P11 register in input mode.
(2) Do not read/write the P11 register and do not change the setting of the PM11 register during D/A conversion
(otherwise the conversion accuracy may decrease).
(3) It is recommended that both the ANO0 and ANO1 pins be used as analog output pins or digital I/O pins, that is,
use these two channels for the same application (if these pins are used for the different applications, the
conversion accuracy may decrease).
(4) In the real-time output mode, set the DACSn register value before the timer trigger is generated. In addition, do
not change the set value of the DACSn register while the trigger signal is output.
(5) Before changing the operation mode, be sure to clear the DACEn bit of the DAM register to 0 (D/A conversion
stop).
(6) When using the port that functions alternately as the ANO0 or ANO1 pin, use it as the port input with few level
changes.
(7) Stop the conversion performed by the D/A converter when supplying AVREF1 or AVREF0 (the reference voltages for
the A/D converter) starts or stops.
(8) Because the D/A converter stops operation in the STOP mode, the ANO0 and ANO1 pins go into a high-
impedance state, and the power consumption can be reduced.
In the standby modes other than the STOP mode, however, the operation continues. To lower the power
consumption, therefore, clear the DACEn bit of the DAM register to 0 (D/A conversion stop).
(9) Since the output impedance of the D/A converter is high, the current cannot be obtained from the ANOn pin (n =
0, 1). When the input impedance of the load is low, insert a follower amplifier between the load and ANOn pin
keeping the wiring length as short as possible (for high impedance). If the wiring becomes too long, take
necessary actions such as surrounding with a ground pattern.
<R>
<R>
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CHAPTER 13 SERIAL ARRAY UNIT
The serial array unit has four serial channels per unit and can use two or more of various serial interfaces (3-wire
serial (CSI), UART, and simplified I2C) in combination.
Function assignment of each channel supported by the 78K0R/KG3 is as shown below (channels 2 and 3 of unit 1
are dedicated to UART3 (supporting LIN-bus)).
Unit Channel Used as CSI Used as UART Used as Simplified I2C
0 CSI00 −
1 CSI01
UART0
−
2 CSI10 IIC10
0
3 −
UART1
−
0 CSI20 IIC20
1 −
UART2
−
2 − −
1
3 −
UART3 (supporting LIN-bus)
−
(Example of combination) When “UART0” is used for channels 0 and 1 of unit 0, CSI00 and CSI01 cannot be used,
but CSI10, UART1, or IIC10 can be used.
13.1 Functions of Serial Array Unit
Each serial interface supported by the 78K0R/KG3 has the following features.
13.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20)
This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines.
[Data transmission/reception]
• Data length of 7 or 8 bits
• Phase control of transmit/receive data
• MSB/LSB first selectable
• Level setting of transmit/receive data
[Clock control]
• Master/slave selection
• Phase control of I/O clock
• Setting of transfer period by prescaler and internal counter of each channel
[Interrupt function]
• Transfer end interrupt/buffer empty interrupt
[Error detection flag]
• Overrun error
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13.1.2 UART (UART0, UART1, UART2, UART3)
This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data
reception (RXD) lines. It transmits or receives data in asynchronization with the party of communication (by using an
internal baud rate). Full-duplex UART communication can be realized by using two channels, one dedicated to
transmission (even channel) and the other to reception (odd channel).
[Data transmission/reception]
• Data length of 5, 7, or 8 bits
• Select the MSB/LSB first
• Level setting of transmit/receive data and select of reverse
• Parity bit appending and parity check functions
• Stop bit appending
[Interrupt function]
• Transfer end interrupt/buffer empty interrupt
• Error interrupt in case of framing error, parity error, or overrun error
[Error detection flag]
• Framing error, parity error, or overrun error
The LIN-bus is accepted in UART3 (2 and 3 channels of unit 1)
[LIN-bus functions]
• Wakeup signal detection
• Sync break field (SBF) detection
• Sync field measurement, baud rate calculation
External interrupt (INTP0) or timer array unit (TAU) is
used.
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13.1.3 Simplified I2C (IIC10, IIC20)
This is a clocked communication function to communicate with two or more devices by using two lines: serial clock
(SCL) and serial data (SDA). This simplified I2C is designed for single communication with a device such as EEPROM,
flash memory, or A/D converter, and therefore, it functions only as a master and does not have a function to detect
wait states.
Make sure by using software, as well as operating the control registers, that the AC specifications of the start and
stop conditions are observed.
[Data transmission/reception]
• Master transmission, master reception (only master function with a single master)
• ACK output functionNote and ACK detection function
• Data length of 8 bits (When an address is transmitted, the address is specified by the higher 7 bits, and the
least significant bit is used for R/W control.)
• Manual generation of start condition and stop condition
[Interrupt function]
• Transfer end interrupt
[Error detection flag]
• Parity error (ACK error)
* [Functions not supported by simplified I2C]
• Slave transmission, slave reception
• Arbitration loss detection function
• Wait detection functions
Note An ACK is not output when the last data is being received by writing 0 to the SOEmn (SOEm register)
bit and stopping the output of serial communication data. See 13.7.3 (2) Processing flow for details.
Remarks 1. To use the full-function I2C bus, see CHAPTER 14 SERIAL INTERFACE IIC0.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
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13.2 Configuration of Serial Array Unit
Serial array unit includes the following hardware.
Table 13-1. Configuration of Serial Array Unit
Item Configuration
Shift register 8 bits
Buffer register Lower 8 bits of serial data register mn (SDRmn)Note
Serial clock I/O SCK00, SCK01, SCK10, SCK20 pins (for 3-wire serial I/O), SCL10, SCL20 pins (for simplified
I2C)
Serial data input SI00, SI01, SI10, SI20 pins (for 3-wire serial I/O), RXD0, RXD1, RXD2 pins (for UART),
RXD3 pin (for UART supporting LIN-bus)
Serial data output SO00, SO01, SO10, SO20 pins (for 3-wire serial I/O), TXD0, TXD1, TXD2 pins (for UART),
TXD3 pin (for UART supporting LIN-bus), output controller
Serial data I/O SDA10, SDA20 pins (for simplified I2C)
<Registers of unit setting block>
• Peripheral enable register 0 (PER0)
• Serial clock select register m (SPSm)
• Serial channel enable status register m (SEm)
• Serial channel start register m (SSm)
• Serial channel stop register m (STm)
• Serial output enable register m (SOEm)
• Serial output register m (SOm)
• Serial output level register m (SOLm)
• Input switch control register (ISC)
• Noise filter enable register 0 (NFEN0)
Control registers
<Registers of each channel>
• Serial data register mn (SDRmn)
• Serial mode register mn (SMRmn)
• Serial communication operation setting register mn (SCRmn)
• Serial status register mn (SSRmn)
• Serial flag clear trigger register mn (SIRmn)
• Port input mode registers 0, 4, 14 (PIM0, PIM4, PIM14)
• Port output mode registers 0, 4, 14 (POM0, POM4, POM14)
• Port mode registers 0, 1, 4, 14 (PM0, PM1, PM4, PM14)
• Port registers 0, 1, 4, 14 (P0, P1, P4, P14)
Note The lower 8 bits of the serial data register mn (SDRmn) can be read or written as the following SFR,
depending on the communication mode.
• CSIp communication … SIOp (CSIp data register)
• UARTq reception … RXDq (UARTq receive data register)
• UARTq transmission … TXDq (UARTq transmit data register)
• IICr communication … SIOr (IICr data register)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
p: CSI number (p = 00, 01, 10, 20), q: UART number (q = 0 to 3), r: IIC number (r = 10, 20)
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Figure 13-1 shows the block diagram of serial array unit 0.
Figure 13-1. Block Diagram of Serial Array Unit 0
Serial data input pin
(when CSI0: SI01/P44)
Serial transfer end interrupt
(when CSI01: INTCSI01)
(when UART0: INTSR0)
Serial clock select register 0 (SPS0)
PRS
013
4
PRS
003
PRS
012
PRS
011
PRS
010
PRS
002
PRS
001
PRS
000
4
f
CLK
f
CLK
/2
0
to f
CLK
/2
11
Selector
f
CLK
/2
0
to
f
CLK
/2
11
Selector
CKS00 MD001CCS00 STS00 MD002
Mode selection
CSI00 or UART0
(for transmission)
Edge
detection
Communication controller
Shift register
Serial data register 00 (SDR00)
Interrupt
controller
Edge/level
detection
Serial output register 0 (SO0)
Serial output enable
register 0 (SOE0)
Serial clock I/O pin
(when CSI00: SCK00
/P10/EX24)
PM10
SAU0EN
Peripheral enable
register 0 (PER0)
Serial data input pin
(when CSI00: SI00/
P11/RxD0/EX25)
(when UART0: RxD0/
P11/SI00/EX25)
Serial mode register 00 (SMR00)
Serial channel enable
status register 0 (SE0)
Serial channel stop
register 0 (ST0)
Serial channel start
register 0 (SS0)
(Buffer register block)
(Clock division setting block)
Error controller
TXE
00
RXE
00
DAP
00
CKP
00
Serial communication operation setting register 00 (SCR00)
EOC
00
FECT
00
PECT
00
Serial flag clear trigger
register 00 (SIR00)
OVCT
00
PTC
001
SLC
000
PTC
000
DIR
00
SLC
001
DLS
002
DLS
001
DLS
000
TSF
00
OVF
00
BFF
00
FEF
00
PEF
00
Serial status register 00 (SSR00)
Output
controller
Serial transfer end interrupt
(when CSI00: INTCSI00)
(when UART0: INTST0)
Error
information
Clear
Channel 0
Mode selection
CSI01 or UART0
(for reception)
Communication controller
Channel 1
Serial data input pin
(when CSI10: SI10/
P03/RxD1/SDA10)
(when IIC10: SDA10/
P03/RxD1/SI10)
(when UART1: RxD1/
P03/SI10/SDA10)
Serial data output pin
(when CSI10: SO10/
P02/TxD1)
(when IIC10: SDA10/
P03/SI10/RxD1)
when (UART1: TxD1/
P02/SO10)
Serial transfer end interrupt
(when CSI10: INTCSI10)
(when IIC10: INTIIC10)
(when UART1: INTST1)
Mode selection
CSI10 or IIC10
or UART1
(for transmission)
Communication controller
Channel 2
Mode selection
UART1
(for reception)
Communication controller
Channel 3
CK01
INTTM02
CK00
MCK
TCLK
SCK
Output latch
(P10)
Serial clock I/O pin
(when CSI10: SCK10/
P04/SCL10)
(when IIC10: SCL10/
P04/SCK10)
Serial transfer error interrupt
(INTSRE0)
Serial transfer end interrupt
(when UART1: INTSR1)
Serial transfer error interrupt
(INTSRE1)
Serial data output pin
(when CSI01: SO01/P45)
Serial clock I/O pin
(when CSI01: SCK01/P43)
CK01 CK00
CK01 CK00
CK01 CK00
Noise filter enable
register 0 (NFEN0)
Noise
elimination
enabled/
disabled
SNFEN00
Edge/level
detection
Selector
When UART0
Edge/level
detection
Edge/level
detection
Noise
elimination
enabled/
disabled
SNFEN10
When UART1
PM12
Output latch
(P12)
Serial output level
register 0 (SOL0)
Error controller
Error controller
Selector
Clock controller
Selector
Communication
status
Prescaler 0SOE02 SOE01 SOE00
SE03 SE02 SE01 SE00
ST03 ST02 ST01 ST00
SS03 SS02 SS01 SS00
SNFEN
10
SNFEN
00
0SOL02 0 SOL00
11CKO02 CKO01 CKO00 SO02 SO01 SO00
0000 0000
Serial data output pin
(when CSI00: SO00/
P12/TxD0/EX26)
(whe UART0: TxD0/
P12/SO00/EX26)
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Figure 13-2 shows the block diagram of serial array unit 1.
Figure 13-2. Block Diagram of Serial Array Unit 1
Serial clock select register 1 (SPS1)
PRS
113
4
PRS
103
PRS
112
PRS
111
PRS
110
PRS
102
PRS
101
PRS
100
4
f
CLK
f
CLK
/2
0
to f
CLK
/2
11
Selector
f
CLK
/2
0
to
f
CLK
/2
11
Selector
CKS10 MD101CCS10 STS10 MD102
Mode selection
CSI20 or IIC20
or UART2
(for transmission)
Communication controller
Shift register
Serial data register 10 (SDR10)
Interrupt
controller
Serial output register 1 (SO1)
SAU1EN
Peripheral enable
register 0 (PER0)
Serial data output pin
(when CSI20: SO20/
P144/TxD2)
(when IIC20: SDA20/
P143/SI20/RxD2)
(when UART2: TxD2/
P144/SO20)
Serial mode register 10 (SMR10)
(Buffer register block)
(Clock division setting block)
Error controller
TXE
10
RXE
10
DAP
10
CKP
10
Serial communication operation setting register 10 (SCR10)
EOC
10
FECT
10
PECT
10
Serial flag clear trigger
register 10 (SIR10)
OVCT
10
PTC
101
SLC
100
PTC
100
DIR
10
SLC
101
DLS
102
DLS
101
DLS
100
TSF
10
OVF
10
BFF
10
FEF
10
PEF
10
Serial status register 10 (SSR10)
Output
controller
Serial transfer end interrupt
(when CSI20: INTCSI20)
(when IIC20: INTIIC20)
(when UART2: INTST2)
Error
information
Clear
Channel 0 CK11 CK10
MCK
TCLK
Serial transfer end interrupt
(when UART3: INTSR3)
Serial transfer error interrupt
(INTSRE3)
Mode selection
UART2
(for reception)
Communication controller
Channel 1
Mode selection
UART3
(for transmission)
Communication controller
Channel 2 (LIN-bus supported)
Mode selection
UART3
(for reception)
Communication controller
Channel 3 (LIN-bus supported)
Serial transfer end interrupt
(when UART2: INTSR2)
Serial transfer error interrupt
(INTSRE2)
Serial data output pin
(when UART3: TxD3/P13/EX27)
Serial transfer end interrupt
(when UART3: INTST3)
CK11 CK10
CK11 CK10
CK11 CK10
Edge
detection
Serial clock I/O pin
(when CSI20: SCK20/
P142/SCL20)
(when IIC20: SCL20/
P142/SCK20)
PM142
SCK
Output latch
(P142)
Edge/level
detection
Serial data input pin
(when CSI20: SI20/
P143/RxD2/SDA20)
(when IIC20: SDA20/
P143/RxD2/SI20)
(when UART2: RxD2/
P143/SI20/SDA20)
Noise
elimination
enabled/
disabled
SNFEN20
Noise filter enable
register 0 (NFEN0)
Edge/level
detection
Serial data input pin
(when UART3: RxD3/P14/EX28)
SNFEN30
When UART3
Edge/level
detection
When UART2
Noise
elimination
enabled/
disabled
PM144 or PM143
Output latch
(
P144 or p143)
Serial output enable
register 1 (SOE1)
Serial channel enable
status register 1 (SE1)
Serial channel stop
register 1 (ST1)
Serial channel start
register 1 (SS1)
Serial output level
register 1 (SOL1)
Error controller
Error controller
Selector
Clock controller
Selector
Communication
status
INTTM03
Prescaler
SNFEN
30
SNFEN
20
0SOE12 0 SOE10
SE13 SE12 SE11 SE10
ST13 ST12 ST11 ST10
SS13 SS12 SS11 SS10
0SOL12 0 SOL10
111 1 CKO10 SO12 1 SO10
0000 0000
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(1) Shift register
This is an 8-bit register that converts parallel data into serial data or vice versa.
During reception, it converts data input to the serial pin into parallel data.
When data is transmitted, the value set to this register is output as serial data from the serial output pin.
The shift register cannot be directly manipulated by program.
To read or write the shift register, use the lower 8 bits of serial data register mn (SDRmn).
7 6 5 4 3 2 1 0
Shift register
(2) Lower 8 bits of the serial data register mn (SDRmn)
SDRmn is the transmit/receive data register (16 bits) of channel n. Bits 7 to 0 function as a transmit/receive
buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (MCK).
When data is received, parallel data converted by the shift register is stored in the lower 8 bits. When data is
to be transmitted, set transmit to be transferred to the shift register to the lower 8 bits.
The data stored in the lower 8 bits of this register is as follows, depending on the setting of bits 0 to 2
(DLSmn0 to DLSmn2) of the SCRmn register, regardless of the output sequence of the data.
• 5-bit data length (stored in bits 0 to 4 of SDRmn register) (settable in UART mode only)
• 7-bit data length (stored in bits 0 to 6 of SDRmn register)
• 8-bit data length (stored in bits 0 to 7 of SDRmn register)
SDRmn can be read or written in 16-bit units.
The lower 8 bits of SDRmn of SDRmn can be read or writtenNote as the following SFR, depending on the
communication mode.
• CSIp communication … SIOp (CSIp data register)
• UARTq reception … RXDq (UARTq receive data register)
• UARTq transmission … TXDq (UARTq transmit data register)
• IICr communication … SIOr (IICr data register)
Reset signal generation clears this register to 0000H.
Remarks 1. After data is received, “0” is stored in bits 0 to 7 in bit portions that exceed the data length.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
p: CSI number (p = 00, 01, 10, 20), q: UART number (q = 0 to 3), r: IIC number (r = 10, 20)
Note Writing in 8-bit units is prohibited
when the operation is stopped
(SEmn = 0).
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Figure 13-3. Format of Serial Data Register mn (SDRmn)
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01), After reset: 0000H R/W
FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03),
FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11),
FFF14H, FFF15H (SDR12), FFF16H, FFF17H (SDR13)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0
(m = 0, 1; n = 0 to 3)
7 6 5 4 3 2 1 0
Shift register
Caution Be sure to clear bit 8 to “0”.
Remarks 1. For the function of the higher 7 bits of SDRmn, see 13.3 Registers Controlling Serial Array
Unit.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
p: CSI number (p = 00, 01, 10, 20), q: UART number (q = 0 to 3), r: IIC number (r = 10, 20)
FFF11H (SDR00) FFF10H (SDR00)
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13.3 Registers Controlling Serial Array Unit
Serial array unit is controlled by the following registers.
• Peripheral enable register 0 (PER0)
• Serial clock select register m (SPSm)
• Serial mode register mn (SMRmn)
• Serial communication operation setting register mn (SCRmn)
• Serial data register mn (SDRmn)
• Serial status register mn (SSRmn)
• Serial flag clear trigger register mn (SIRmn)
• Serial channel enable status register m (SEm)
• Serial channel start register m (SSm)
• Serial channel stop register m (STm)
• Serial output enable register m (SOEm)
• Serial output level register m (SOLm)
• Serial output register m (SOm)
• Input switch control register (ISC)
• Noise filter enable register 0 (NFEN0)
• Port input mode registers 0, 4, 14 (PIM0, PIM4, PIM14)
• Port output mode registers 0, 4, 14 (POM0, POM4, POM14)
• Port mode registers 0, 1, 4, 14 (PM0, PM1, PM4, PM14)
• Port registers 0, 1, 4, 14 (P0, P1, P4, P14)
Remark m: Unit number (m = 0, 1)
n: Channel number (n = 0 to 3)
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(1) Peripheral enable register 0 (PER0)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro
that is not used is stopped in order to reduce the power consumption and noise.
When serial array unit 0 is used, be sure to set bit 2 (SAU0EN) of this register to 1.
When serial array unit 1 is used, be sure to set bit 3 (SAU1EN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13-4. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> 1 <0>
PER0 RTCEN DACEN ADCEN IIC0EN SAU1EN SAU0EN 0 TAU0EN
SAUmEN Control of serial array unit m input clock
0 Stops supply of input clock.
• SFR used by serial array unit m cannot be written.
• Serial array unit m is in the reset status.
1 Supplies input clock.
• SFR used by serial array unit m can be read/written.
Cautions 1. When setting serial array unit m, be sure to set SAUmEN to 1 first. If SAUmEN = 0, writing
to a control register of serial array unit m is ignored, and, even if the register is read, only
the default value is read (except for input switch control register (ISC), noise filter enable
register (NFEN0), port input mode registers (PIM0, PIM4, PIM14), port output mode
registers (POM0, POM4, POM14), port mode registers (PM0, PM1, PM4, PM14), and port
registers (P0, P1, P4, P14)).
2. After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
3. Be sure to clear bit 1 of the PER0 register to 0.
Remark m: Unit number (m = 0, 1)
(2) Serial clock select register m (SPSm)
SPSm is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are
commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of SPSm, and CKm0 is selected by bits 3
to 0.
Rewriting SPSm is prohibited when the register is in operation (when SEmn = 1).
SPSm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SPSm can be set with an 8-bit memory manipulation instruction with SPSmL.
Reset signal generation clears this register to 0000H.
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Figure 13-5. Format of Serial Clock Select Register m (SPSm)
Address: F0126H, F0127H (SPS0), F0166H, F0167H (SPS1) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPSm 0 0 0 0 0 0 0 0
PRS
m13
PRS
m12
PRS
m11
PRS
m10
PRS
m03
PRS
m02
PRS
m01
PRS
m00
Section of operation clock (CKmp)Note 1
PRS
mp3
PRS
mp2
PRS
mp1
PRS
mp0 f
CLK = 2 MHz fCLK = 5 MHz fCLK = 10 MHz fCLK = 20 MHz
0 0 0 0 fCLK 2 MHz 5 MHz 10 MHz 20 MHz
0 0 0 1 fCLK/2 1 MHz 2.5 MHz 5 MHz 10 MHz
0 0 1 0 fCLK/22 500 kHz 1.25 MHz 2.5 MHz 5 MHz
0 0 1 1 fCLK/23 250 kHz 625 kHz 1.25 MHz 2.5 MHz
0 1 0 0 fCLK/24 125 kHz 313 kHz 625 kHz 1.25 MHz
0 1 0 1 fCLK/25 62.5 kHz 156 kHz 313 kHz 625 kHz
0 1 1 0 fCLK/26 31.3 kHz 78.1 kHz 156 kHz 313 kHz
0 1 1 1 fCLK/27 15.6 kHz 39.1 kHz 78.1 kHz 156 kHz
1 0 0 0 fCLK/28 7.81 kHz 19.5 kHz 39.1 kHz 78.1 kHz
1 0 0 1 fCLK/29 3.91 kHz 9.77 kHz 19.5 kHz 39.1 kHz
1 0 1 0 fCLK/210 1.95 kHz 4.88 kHz 9.77 kHz 19.5 kHz
1 0 1 1 fCLK/211 977 Hz 2.44 kHz 4.88 kHz 9.77 kHz
1 1 1 1 INTTM02 if m = 0, INTTM03 if m = 1Note 2
Other than above Setting prohibited
Notes 1. When changing the clock selected for fCLK (by changing the system clock control register (CKC)
value), do so after having stopped (STm = 000FH) the operation of the serial array unit (SAU). When
selecting INTTM02 and INTTM03 for the operation clock, also stop the timer array unit (TAU) (TT0 =
00FFH).
2. SAU can be operated at a fixed division ratio of the subsystem clock, regardless of the fCLK frequency
(main system clock, subsystem clock), by operating the interval timer for which fSUB/4 has been
selected as the count clock (setting TIS02 (if m = 0) or TIS03 (if m = 1) of the TIS0 register to 1) and
selecting INTTM02 and INTTM03 by using the SPSm register in channels 2 and 3 of TAU. When
changing fCLK, however, SAU and TAU must be stopped as described in Note 1 above.
Cautions 1. Be sure to clear bits 15 to 8 to “0”.
2. After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
Remarks 1. f
CLK: CPU/peripheral hardware clock frequency
f
SUB: Subsystem clock frequency
2. m: Unit number (m = 0, 1), p = 0, 1
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(3) Serial mode register mn (SMRmn)
SMRmn is a register that sets an operation mode of channel n. It is also used to select an operation clock
(MCK), specify whether the serial clock (SCK) may be input or not, set a start trigger, an operation mode (CSI,
UART, or I2C), and an interrupt source. This register is also used to invert the level of the receive data only in
the UART mode.
Rewriting SMRmn is prohibited when the register is in operation (when SEmn = 1). However, the MDmn0 bit
can be rewritten during operation.
SMRmn can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets this register to 0020H.
Figure 13-6. Format of Serial Mode Register mn (SMRmn) (1/2)
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03), After reset: 0020H R/W
F0150H, F0151H (SMR10), F0152H, F0153H (SMR11),
F0154H, F0155H (SMR12), F0156H, F0157H (SMR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKS
mn
CCS
mn
0 0 0 0 0
STS
mn
0 SIS
mn0
1 0 0
MD
mn2
MD
mn1
MD
mn0
CKS
mn
Selection of operation clock (MCK) of channel n
0 Operation clock CKm0 set by SPSm register
1 Operation clock CKm1 set by SPSm register
Operation clock MCK is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the
higher 7 bits of the SDRmn register, a transfer clock (TCLK) is generated.
CCS
mn
Selection of transfer clock (TCLK) of channel n
0 Divided operation clock MCK specified by CKSmn bit
1 Clock input from SCK pin (slave transfer in CSI mode)
Transfer clock TCLK is used for the shift register, communication controller, output controller, interrupt controller,
and error controller. When CCSmn = 0, the division ratio of MCK is set by the higher 7 bits of the SDRmn register.
STS
mn
Selection of start trigger source
0 Only software trigger is valid (selected for CSI, UART transmission, and simplified I2C).
1 Valid edge of RXD pin (selected for UART reception)
Transfer is started when the above source is satisfied after 1 is set to the SSm register.
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 to “0”. Be sure to set bit 5 to “1”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 13-6. Format of Serial Mode Register mn (SMRmn) (2/2)
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03), After reset: 0020H R/W
F0150H, F0151H (SMR10), F0152H, F0153H (SMR11),
F0154H, F0155H (SMR12), F0156H, F0157H (SMR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKS
mn
CCS
mn
0 0 0 0 0
STS
mn
0 SIS
mn0
1 0 0
MD
mn2
MD
mn1
MD
mn0
SIS
mn0
Controls inversion of level of receive data of channel n in UART mode
0 Falling edge is detected as the start bit.
The input communication data is captured as is.
1 Rising edge is detected as the start bit.
The input communication data is inverted and captured.
MD
mn2
MD
mn1
Setting of operation mode of channel n
0 0 CSI mode
0 1 UART mode
1 0 Simplified I2C mode
1 1 Setting prohibited
MD
mn0
Selection of interrupt source of channel n
0 Transfer end interrupt
1 Buffer empty interrupt
(Occurs when data is transferred from the SDRmn register to the shift register.)
For successive transmission, the next transmit data is written by setting MDmn0 to 1 when SDRmn data has run
out.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
<R>
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(4) Serial communication operation setting register mn (SCRmn)
SCRmn is a communication operation setting register of channel n. It is used to set a data
transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity
bit, start bit, stop bit, and data length.
Rewriting SCRmn is prohibited when the register is in operation (when SEmn = 1).
SCRmn can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets this register to 0087H.
Figure 13-7. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/3)
Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03), After reset: 0087H R/W
F0158H, F0159H (SCR10), F015AH, F015BH (SCR11),
F015CH, F015DH (SCR12), F015EH, F015FH (SCR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXE
mn
RXE
mn
DAP
mn
CKP
mn
0 EOC
mn
PTC
mn1
PTC
mn0
DIR
mn
0 SLC
mn1
SLC
mn0
0 DLS
mn2
DLS
mn1
DLS
mn0
TXE
mn
RXE
mn
Setting of operation mode of channel n
0 0 Does not start communication.
0 1 Reception only
1 0 Transmission only
1 1 Transmission/reception
DAP
mn
CKP
mn
Selection of data and clock phase in CSI mode Type
0 0
D7 D6 D5 D4 D3 D2 D1 D0
SCKp
SOp
SI
p
input timing
1
0 1
D7 D6 D5 D4 D3 D2 D1 D0
SCKp
SOp
SI
p input timing
2
1 0
D7 D6 D5 D4 D3 D2 D1 D0
SCKp
SOp
SI
p
input timing
3
1 1
D7 D6 D5 D4 D3 D2 D1 D0
SCKp
SOp
SI
p
input timing
4
Be sure to set DAPmn, CKPmn = 0, 0 in the UART mode and simplified I2C mode.
Caution Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 20)
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Figure 13-7. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/3)
Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03), After reset: 0087H R/W
F0158H, F0159H (SCR10), F015AH, F015BH (SCR11),
F015CH, F015DH (SCR12), F015EH, F015FH (SCR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXE
mn
RXE
mn
DAP
mn
CKP
mn
0 EOC
mn
PTC
mn1
PTC
mn0
DIR
mn
0 SLC
mn1
SLC
mn0
0 DLS
mn2
DLS
mn1
DLS
mn0
EOC
mn
Selection of masking of error interrupt signal (INTSREx (x = 0 to 3))
0 Masks error interrupt INTSREx (INTSRx is not masked).
1 Enables generation of error interrupt INTSREx (INTSRx is masked if an error occurs).
Set EOCmn = 0 in the CSI mode, simplified I2C mode, and during UART transmissionNote 1.
Set EOCmn = 1 during UART reception.
Setting of parity bit in UART mode
PTC
mn1
PTC
mn0 Transmission Reception
0 0 Does not output the parity bit. Receives without parity
0 1 Outputs 0 parity Note 2. No parity judgment
1 0 Outputs even parity. Judged as even parity.
1 1 Outputs odd parity. Judges as odd parity.
Be sure to set PTCmn1, PTCmn0 = 0, 0 in the CSI mode and simplified I2C mode.
DIR
mn
Selection of data transfer sequence in CSI and UART modes
0 Inputs/outputs data with MSB first.
1 Inputs/outputs data with LSB first.
Be sure to clear DIRmn = 0 in the simplified I2C mode.
SLC
mn1
SLC
mn0
Setting of stop bit in UART mode
0 0 No stop bit
0 1 Stop bit length = 1 bit
1 0 Stop bit length = 2 bits
1 1 Setting prohibited
When the transfer end interrupt is selected, the interrupt is generated when all stop bits have been completely
transferred.
Set 1 bit (SLCmn1, SLCmn0 = 0, 1) during UART reception and in the simplified I2C mode.
Set no stop bit (SLCmn1, SLCmn0 = 0, 0) in the CSI mode.
Notes 1. When not using CSI01 with EOC01 = 0, error interrupt INTSRE0 may be generated.
2. 0 is always added regardless of the data contents.
Caution Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
<R>
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Figure 13-7. Format of Serial Communication Operation Setting Register mn (SCRmn) (3/3)
Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03), After reset: 0087H R/W
F0158H, F0159H (SCR10), F015AH, F015BH (SCR11),
F015CH, F015DH (SCR12), F015EH, F015FH (SCR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXE
mn
RXE
mn
DAP
mn
CKP
mn
0 EOC
mn
PTC
mn1
PTC
mn0
DIR
mn
0 SLC
mn1
SLC
mn0
0 DLS
mn2
DLS
mn1
DLS
mn0
DLS
mn2
DLS
mn1
DLS
mn0
Setting of data length in CSI and UART modes
1 0 0
5-bit data length (stored in bits 0 to 4 of SDRmn register)
(settable in UART mode only)
1 1 0 7-bit data length (stored in bits 0 to 6 of SDRmn register)
1 1 1 8-bit data length (stored in bits 0 to 7 of SDRmn register)
Other than above Setting prohibited
Be sure to set DLSmn0 = 1 in the simplified I2C mode.
Caution Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(5) Higher 7 bits of the serial data register mn (SDRmn)
SDRmn is the transmit/receive data register (16 bits) of channel n. Bits 7 to 0 function as a transmit/receive
buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (MCK).
If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operating
clock by the higher 7 bits of SDRmn is used as the transfer clock.
For the function of the lower 8 bits of SDRmn, see 13.2 Configuration of Serial Array Unit.
SDRmn can be read or written in 16-bit units.
However, the higher 7 bits can be written or read only when the operation is stopped (SEmn = 0). During
operation (SEmn = 1), a value is written only to the lower 8 bits of SDRmn. When SDRmn is read during
operation, 0 is always read.
Reset signal generation clears this register to 0000H.
Figure 13-8. Format of Serial Data Register mn (SDRmn)
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01), After reset: 0000H R/W
FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03),
FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11),
FFF14H, FFF15H (SDR12), FFF16H, FFF17H (SDR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0
SDRmn[15:9] Transfer clock setting by dividing the operating clock (MCK)
0 0 0 0 0 0 0 MCK/2
0 0 0 0 0 0 1 MCK/4
0 0 0 0 0 1 0 MCK/6
0 0 0 0 0 1 1 MCK/8
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1 1 1 1 1 1 0 MCK/254
1 1 1 1 1 1 1 MCK/256
Cautions 1. Be sure to clear bit 8 to “0”.
2. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
3. Setting SDRmn[15:9] = 0000000B is prohibited when simplified I2C is used. Set
SDRmn[15:9] to 0000001B or greater.
4. Do not write eight bits to the lower eight bits if operation is stopped (SEmn = 0). (If these
bits are written to, the higher seven bits are cleared to 0.)
Remarks 1. For the function of the lower 8 bits of SDRmn, see 13.2 Configuration of Serial Array Unit.
2. m: Unit number (m = 0, 1)
n: Channel number (n = 0 to 3)
FFF11H (SDR00) FFF10H (SDR00)
<R>
<R>
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(6) Serial status register mn (SSRmn)
SSRmn is a register that indicates the communication status and error occurrence status of channel n. The
errors indicated by this register are a framing error, parity error, and overrun error.
SSRmn can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of SSRmn can be set with an 8-bit memory manipulation instruction with SSRmnL.
Reset signal generation clears this register to 0000H.
Figure 13-9. Format of Serial Status Register mn (SSRmn) (1/2)
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03), After reset: 0000H R
F0140H, F0141H (SSR10), F0142H, F0143H (SSR11),
F0144H, F0145H (SSR12), F0146H, F0147H (SSR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSRmn 0 0 0 0 0 0 0 0 0
TSF
mn
BFF
mn
0 0
FEF
mn
PEF
mn
OVF
mn
TSF
mn
Communication status indication flag of channel n
0 Communication is not under execution.
1 Communication is under execution.
Because this flag is an updating flag, it is automatically cleared when the communication operation is completed.
This flag is cleared also when the STmn/SSmn bit is set to 1.
BFF
mn
Buffer register status indication flag of channel n
0 Valid data is not stored in the SDRmn register.
1 Valid data is stored in the SDRmn register.
This is an updating flag. It is automatically cleared when transfer from the SDRmn register to the shift register is
completed. During reception, it is automatically cleared when data has been read from the SDRmn register. This
flag is cleared also when the STmn/SSmn bit is set to 1.
This flag is automatically set if transmit data is written to the SDRmn register when the TXEmn bit of the SCRmn
register = 1 (transmission or reception mode in each communication mode). It is automatically set if receive data is
stored in the SDRmn register when the RXEmn bit of the SCRmn register = 1 (transmission or reception mode in
each communication mode). It is also set in case of a reception error.
If data is written to the SDRmn register when BFFmn = 1, the transmit/receive data stored in the register is
discarded and an overrun error (OVFmn = 1) is detected.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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Figure 13-9. Format of Serial Status Register mn (SSRmn) (2/2)
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03), After reset: 0000H R
F0140H, F0141H (SSR10), F0142H, F0143H (SSR11),
F0144H, F0145H (SSR12), F0146H, F0147H (SSR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSRmn 0 0 0 0 0 0 0 0 0
TSF
mn
BFF
mn
0 0
FEF
mn
PEF
mn
OVF
mn
FEF
mn
Framing error detection flag of channel n
0 No error occurs.
1 A framing error occurs during UART reception.
<Framing error cause>
A framing error occurs if the stop bit is not detected upon completion of UART reception.
This is a cumulative flag and is not cleared until 1 is written to the FECTmn bit of the SIRmn register.
PEF
mn
Parity error detection flag of channel n
0 Error does not occur.
1 A parity error occurs during UART reception or ACK is not detected during I2C transmission.
<Parity error cause>
• A parity error occurs if the parity of transmit data does not match the parity bit on completion of UART
reception.
• ACK is not detected if the ACK signal is not returned from the slave in the timing of ACK reception
during I2C transmission.
This is a cumulative flag and is not cleared until 1 is written to the PECTmn bit of the SIRmn register.
OVF
mn
Overrun error detection flag of channel n
0 No error occurs.
1 An overrun error occurs.
<Causes of overrun error>
• Receive data stored in the SDRmn register is not read and transmit data is written or the next receive
data is written.
• Transmit data is not ready for slave transmission or reception in the CSI mode.
This is a cumulative flag and is not cleared until 1 is written to the OVCTmn bit of the SIRmn register.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(7) Serial flag clear trigger register mn (SIRmn)
SIRmn is a trigger register that is used to clear each error flag of channel n.
When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn,
PEFmn, OVFmn) of serial status register mn is cleared to 0. Because SIRmn is a trigger register, it is cleared
immediately when the corresponding bit of SSRmn is cleared.
SIRmn can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SIRmn can be set with an 8-bit memory manipulation instruction with SIRmnL.
Reset signal generation clears this register to 0000H.
Figure 13-10. Format of Serial Flag Clear Trigger Register mn (SIRmn)
Address: F0108H, F0109H (SIR00) to F010EH, F010FH (SIR03), After reset: 0000H R/W
F0148H, F0149H (SIR10), F014AH, F014BH (SIR11),
F014CH, F014DH (SIR12), F014EH, F014FH (SIR13)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIRmn 0 0 0 0 0 0 0 0 0 0 0 0 0
FEC
Tmn
PEC
Tmn
OVC
Tmn
FEC
Tmn
Clear trigger of framing error of channel n
0 No trigger operation
1 Clears the FEFmn bit of the SSRmn register to 0.
PEC
Tmn
Clear trigger of parity error flag of channel n
0 No trigger operation
1 Clears the PEFmn bit of the SSRmn register to 0.
OVC
Tmn
Clear trigger of overrun error flag of channel n
0 No trigger operation
1 Clears the OVFmn bit of the SSRmn register to 0.
Caution Be sure to clear bits 15 to 3 to “0”.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
2. When the SIRmn register is read, 0000H is always read.
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(8) Serial channel enable status register m (SEm)
SEm indicates whether data transmission/reception operation of each channel is enabled or stopped.
When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1.
When 1 is written a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0.
Channel n that is enabled to operate cannot rewrite by software the value of CKOmn of the serial output
register m (SOm) to be described below, and a value reflected by a communication operation is output from the
serial clock pin.
Channel n that stops operation can set the value of CKOmn of the SOm register by software and output its
value from the serial clock pin. In this way, any waveform, such as that of a start condition/stop condition, can
be created by software.
SEm can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of SEm can be set with an 1-bit or 8-bit memory manipulation instruction with SEmL.
Reset signal generation clears this register to 0000H.
Figure 13-11. Format of Serial Channel Enable Status Register m (SEm)
Address: F0120H, F0121H (SE0), F0160H, F0161H (SE1) After reset: 0000H R
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEm 0 0 0 0 0 0 0 0 0 0 0 0
SEm
3
SEm
2
SEm
1
SEm
0
SEm
n
Indication of operation enable/stop status of channel n
0 Operation stops (stops with the values of the control register and shift register, and the statuses of the serial
clock I/O pin, serial data output pin, and the FEF, PEF, and OVF error flags retainedNote).
1 Operation is enabled.
Note Bits 6 and 5 (TSFmn, BFFmn) of the SSRmn register are cleared.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(9) Serial channel start register m (SSm)
SSm is a trigger register that is used to enable starting communication/count by each channel.
When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status
register m (SEm) is set to 1. Because SSmn is a trigger bit, it is cleared immediately when SEmn = 1.
SSm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SSm can be set with an 1-bit or 8-bit memory manipulation instruction with SSmL.
Reset signal generation clears this register to 0000H.
Figure 13-12. Format of Serial Channel Start Register m (SSm)
Address: F0122H, F0123H (SS0), F0162H, F0163H (SS1) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm 0 0 0 0 0 0 0 0 0 0 0 0
SSm
3
SSm
2
SSm
1
SSm
0
SSmn Operation start trigger of channel n
0 No trigger operation
1 Sets SEmn to 1 and enters the communication wait status (if a communication operation is already under
execution, the operation is stopped and the start condition is awaited).
Caution Be sure to clear bits 15 to 4 to “0”.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
2. When the SSm register is read, 0000H is always read.
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(10) Serial channel stop register m (STm)
STm is a trigger register that is used to enable stopping communication/count by each channel.
When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status
register m (SEm) is cleared to 0. Because STmn is a trigger bit, it is cleared immediately when SEmn = 0.
STm can set written by a 16-bit memory manipulation instruction.
The lower 8 bits of STm can be set with an 1-bit or 8-bit memory manipulation instruction with STmL.
Reset signal generation clears this register to 0000H.
Figure 13-13. Format of Serial Channel Stop Register m (STm)
Address: F0124H, F0125H (ST0), F0164H, F0165H (ST1) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STm 0 0 0 0 0 0 0 0 0 0 0 0
STm
3
STm
2
STm
1
STm
0
STm
n
Operation stop trigger of channel n
0 No trigger operation
1 Clears SEmn to 0 and stops the communication operation.
(Stops with the values of the control register and shift register, and the statuses of the serial clock I/O pin,
serial data output pin, and the FEF, PEF, and OVF error flags retainedNote.)
Note Bits 6 and 5 (TSFmn, BFFmn) of the SSRmn register are cleared.
Caution Be sure to clear bits 15 to 4 to “0”.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
2. When the STm register is read, 0000H is always read.
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(11) Serial output enable register m (SOEm)
SOEm is a register that is used to enable or stop output of the serial communication operation of each
channel.
Channel n that enables serial output cannot rewrite by software the value of SOmn of the serial output register
m (SOm) to be described below, and a value reflected by a communication operation is output from the serial
data output pin.
For channel n, whose serial output is stopped, the SOmn value of the SOm register can be set by software,
and that value can be output from the serial data output pin. In this way, any waveform of the start condition
and stop condition can be created by software.
SOEm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SOEm can be set with an 1-bit or 8-bit memory manipulation instruction with SOEmL.
Reset signal generation clears this register to 0000H.
Figure 13-14. Format of Serial Output Enable Register m (SOEm)
Address: F012AH, F012BH After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOE0 0 0 0 0 0 0 0 0 0 0 0 0 0
SOE
02
SOE
01
SOE
00
Address: F016AH, F016BH After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOE1 0 0 0 0 0 0 0 0 0 0 0 0 0
SOE
12
0 SOE
10
SOE
mn
Serial output enable/disable of channel n
0 Stops output by serial communication operation.
1 Enables output by serial communication operation.
Caution Be sure to clear bits 15 to 3 of SOE0, and bits 15 to 3 and 1 of SOE1 to “0”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2),
mn = 00 to 02, 10, 12
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(12) Serial output register m (SOm)
SOm is a buffer register for serial output of each channel.
The value of bit n of this register is output from the serial data output pin of channel n.
The value of bit (n + 8) of this register is output from the serial clock output pin of channel n.
SOmn of this register can be rewritten by software only when serial output is disabled (SOEmn = 0). When
serial output is enabled (SOEmn = 1), rewriting by software is ignored, and the value of the register can be
changed only by a serial communication operation.
CKOmn of this register can be rewritten by software only when the channel operation is stopped (SEmn = 0).
While channel operation is enabled (SEmn = 1), rewriting by software is ignored, and the value of CKOmn can
be changed only by a serial communication operation.
To use the P02/SO10/TxD1, P03/SI10/SDA10/RxD1, P04/SCK10/SCL10, P10/SCK00/EX24,
P12/SO00/TxD0/EX26, P13/TxD3/EX27, P43/SCK01, P45/SO01, P142/SCK20/SCL20,
P143/SI20/SDA20/RxD2, or P144/SO20/TxD2 pin as a port function pin, set the corresponding CKOmn and
SOmn bits to “1”.
SOm can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0F0FH.
Figure 13-15. Format of Serial Output Register m (SOm)
Address: F0128H, F0129H After reset: 0F0FH R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO0 0 0 0 0 1
CKO
02
CKO
01
CKO
00
0 0 0 0 1
SO
02
SO
01
SO
00
Address: F0168H, F0169H After reset: 0F0FH R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO1 0 0 0 0 1 1 1
CKO
10
0 0 0 0 1
SO
12
1 SO
10
CKO
mn
Serial clock output of channel n
0 Serial clock output value is “0”.
1 Serial clock output value is “1”.
SO
mn
Serial data output of channel n
0 Serial data output value is “0”.
1 Serial data output value is “1”.
Caution Be sure to set bits 11 and 3 of SO0, and bits 11 to 9, 3, and 1 of SO1 to “1”. And be sure to
clear bits 15 to 12 and 7 to 4 of SOm to “0”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2),
mn = 00-02, 10, 12
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(13) Serial output level register m (SOLm)
SOLm is a register that is used to set inversion of the data output level of each channel.
This register can be set only in the UART mode. Be sure to set 0000H in the CSI mode and simplifies I2C
mode.
Inverting channel n by using this register is reflected on pin output only when serial output is enabled (SOEmn
= 1). When serial output is disabled (SOEmn = 0), the value of the SOmn bit is output as is.
Rewriting SOLm is prohibited when the register is in operation (when SEmn = 1).
SOLm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SOLm can be set with an 8-bit memory manipulation instruction with SOLmL.
Reset signal generation clears this register to 0000H.
Figure 13-16. Format of Serial Output Level Register m (SOLm)
Address: F0134H, F0135H (SOL0), F0174H, F0175H (SOL1) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOLm 0 0 0 0 0 0 0 0 0 0 0 0 0
SOL
m2
0 SOL
m0
SOL
mn
Selects inversion of the level of the transmit data of channel n in UART mode
0 Communication data is output as is.
1 Communication data is inverted and output.
Caution Be sure to clear bits 15 to 3 and 1 to “0”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
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(14) Input switch control register (ISC)
ISC is used to realize a LIN-bus communication operation by UART3 in coordination with an external interrupt
and the timer array unit.
When bit 0 is set to 1, the input signal of the serial data input (RXD3) pin is selected as an external interrupt
(INTP0) that can be used to detect a wakeup signal.
When bit 1 is set to 1, the input signal of the serial data input (RXD3) pin is selected as a timer input, so that
the pulse widths of a sync break field and a sync field can be measured by the timer.
ISC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13-17. Format of Input Switch Control Register (ISC)
Address: FFF3CH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ISC 0 0 0 0 0 0 ISC1 ISC0
ISC1 Switching channel 7 input of timer array unit
0 Uses the input signal of the TI07 pin as a timer input (normal operation).
1 Input signal of RXD3 pin is used as timer input
(to measure the pulse widths of the sync break field and sync field).
ISC0 Switching external interrupt (INTP0) input
0 Uses the input signal of the INTP0 pin as an external interrupt (normal operation).
1 Uses the input signal of the RXD3 pin as an external interrupt (wakeup signal detection).
Caution Be sure to clear bits 7 to 2 to “0”.
<R>
<R>
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(15) Noise filter enable register 0 (NFEN0)
NFEN0 is used to set whether the noise filter can be used for the input signal from the serial data input pin to
each channel.
Disable the noise filter of the pin used for CSI or simplified I2C communication, by clearing the corresponding
bit of this register to 0.
Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this
register to 1.
When the noise filter is enabled, CPU/peripheral operating clock (fCLK) is synchronized with 2-clock match
detection.
NFEN0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13-18. Format of Noise Filter Enable Register 0 (NFEN0)
Address: F0060H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
NFEN0 0 SNFEN30 0 SNFEN20 0 SNFEN10 0 SNFEN00
SNFEN30 Use of noise filter of RXD3/P14 pin
0 Noise filter OFF
1 Noise filter ON
Set SNFEN30 to 1 to use the RXD3 pin.
Clear SNFEN30 to 0 to use the P14 pin.
SNFEN20 Use of noise filter of RXD2/SDA20/SI20/P143 pin
0 Noise filter OFF
1 Noise filter ON
Set SNFEN20 to 1 to use the RXD2 pin.
Clear SNFEN20 to 0 to use the SDA20, SI20, and P143 pins.
SNFEN10 Use of noise filter of RXD1/SDA10/SI10/P03 pin
0 Noise filter OFF
1 Noise filter ON
Set SNFEN10 to 1 to use the RXD1 pin.
Clear SNFEN10 to 0 to use the SDA10, SI10, and P03 pins.
SNFEN00 Use of noise filter of RXD0/SI00/P11 pin
0 Noise filter OFF
1 Noise filter ON
Set SNFEN00 to 1 to use the RXD0 pin.
Clear SNFEN00 to 0 to use the SI00 and P11 pins.
Caution Be sure to clear bits 7, 5, 3, and 1 to “0”.
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(16) Port input mode registers 0, 4, 14 (PIM0, PIM4, PIM14)
These registers set the input buffer of ports 0, 4, and 14 in 1-bit units.
PIM0, PIM4, and PIM14 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 13-19. Format of Port Input Mode Registers 0, 4, and 14 (PIM0, PIM4, PIM14)
Address F0040H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PIM0 0 0 0 PIM04 PIM03 0 0 0
Address F0044H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PIM4 0 0 0 PIM44 PIM43 0 0 0
Address F004EH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PIM14 0 0 0 0 PIM143 PIM142 0 0
PIMmn Pmn pin input buffer selection (m = 0, 4, 14; n = 2 to 4)
0 Normal input buffer
1 TTL input buffer
(17) Port output mode registers 0, 4, 14 (POM0, POM4, POM14)
These registers set the output mode of ports 0, 4, and 14 in 1-bit units.
POM0, POM4, and POM14 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 13-20. Format of Port Output Mode Registers 0, 4, and 14 (POM0, POM4, POM14)
Address F0050H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
POM0 0 0 0 POM04 POM03 POM02 0 0
Address F0054H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
POM4 0 0 POM45 0 POM43 0 0 0
Address F005EH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
POM14 0 0 0 POM144 POM143 POM142 0 0
POMmn Pmn pin output buffer selection (m = 0, 4, 14; n = 2 to 5)
0 Normal output mode
1 N-ch open-drain output (VDD tolerance) mode
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(18) Port mode registers 0, 1, 4, 14 (PM0, PM1, PM4, PM14)
These registers set input/output of ports 0, 1, 4 and 14 in 1-bit units.
When using the P02/SO10/TXD1, P03/SI10/RXD1/SDA10, P04/SCK10/SCL10, P10/SCK00/EX24,
P12/SO00/TXD0/EX26, P13/TXD3/EX27, P43/SCK01, P45/SO01, P142/SCK20/SCL20,
P143/SI20/RXD2/SDA20, and P144/SO20/TXD2 pins for serial data output or serial clock output, clear the
PM02, PM03, PM04, PM10, PM12, PM13, PM43, PM45, PM142, PM143, and PM144 bits to 0, and set the
output latches of P02, P03, P04, P10, P12, P13, P43, P45, P142, P143, and P144 to 1.
When using the P03/SI10/RXD1/SDA10, P04/SCK10/SCL10, P10/SCK00/EX24, P11/SI00/RXD0/EX25,
P14/RXD3/EX28, P43/SCK01, P44/SI01, P142/SCK20/SCL20, and P143/SI20/RXD2/SDA20 pins for serial
data input or serial clock input, set the PM03, PM04, PM10, PM11, PM14, PM43, PM44, PM142, and PM143
bits to 1. At this time, the output latches of P03, P04, P10, P11, P14, P43, P44, P142, and P143 may be 0 or
1.
PM0, PM1, PM4, and PM14 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Figure 13-21. Format of Port Mode Registers 0, 1, 4, and 14 (PM0, PM1, PM4, PM14)
Address: FFF20H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00
Address: FFF21H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
Address: FFF24H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40
Address: FFF2EH After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM14 1 1 PM145 PM144 PM143 PM142 PM141 PM140
PMmn Pmn pin I/O mode selection (m = 0, 1, 4, 14; n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
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13.4 Operation Stop Mode
Each serial interface of serial array unit has the operation stop mode.
In this mode, serial communication cannot be executed, thus reducing the power consumption.
In addition, the P02/SO10/TxD1, P03/SI10/SDA10/RxD1, P04/SCK10/SCL10, P10/SCK00/EX24,
P11/SI00/RxD0/EX25, P12/SO00/TxD0/EX26, P13/TxD3/EX27, P43/SCK01, P44/SI01, P45/SO01,
P142/SCK20/SCL20, P143/SI20/SDA20/RxD2, or P144/SO20/TxD2 pin can be used as ordinary port pins in this
mode.
13.4.1 Stopping the operation by units
The stopping of the operation by units is set by using peripheral enable register 0 (PER0).
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that
is not used is stopped in order to reduce the power consumption and noise.
To stop the operation of serial array unit 0, set bit 2 (SAU0EN) to 0.
To stop the operation of serial array unit 1, set bit 3 (SAU1EN) to 0.
Figure 13-22. Peripheral Enable Register 0 (PER0) Setting When Stopping the Operation by Units
Cautions 1. If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and, even if
the register is read, only the default value is read (except for input switch control register
(ISC), noise filter enable register (NFEN0), port input mode registers (PIM0, PIM4, PIM14),
port output mode registers (POM0, POM4, POM14), port mode registers (PM0, PM1, PM4,
PM14), and port registers (P0, P1, P4, P14)).
2. Be sure to clear bit 1 of the PER0 register to 0.
Remark m: Unit number (m = 0, 1), : Setting disabled (fixed by hardware)
×: Bits not used with serial array units (depending on the settings of other peripheral functions)
0/1: Set to 0 or 1 depending on the usage of the user
(a) Peripheral enable register 0 (PER0) … Set only the bit of SAUm to be stopped to 0.
7 6 5 4 3 2 1 0
PER0 RTCEN
×
DACEN
×
ADCEN
×
IIC0EN
×
SAU1EN
0/1
SAU0EN
0/1
0
TAU 0 EN
0/1
Control of SAUm input clock
0: Stops supply of input clock
1: Su
pp
lies in
p
ut cloc
k
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13.4.2 Stopping the operation by channels
The stopping of the operation by channels is set using each of the following registers.
Figure 13-23. Each Register Setting When Stopping the Operation by Channels (1/2)
(a) Serial Channel Enable Status Register m (SEm) … This register indicates whether data
transmission/reception operation of each channel is enabled or stopped.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEm
0
0
0
0
0
0
0
0
0
0
0
0
SEm3
0/1
SEm2
0/1
SEm1
0/1
SEm0
0/1
0: Operation stops
* The SEm register is a read-only status register, whose operation is stopped by using the STm register.
With a channel whose operation is stopped, the value of CKOmn of the SOm register can be set by software.
(b) Serial channel stop register m (STm) … This register is a trigger register that is used to enable
stopping communication/count by each channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STm
0
0
0
0
0
0
0
0
0
0
0
0
STm3
0/1
STm2
0/1
STm1
0/1
STm0
0/1
1: Clears SEmn to 0 and stops the communication operation
* Because STmn is a trigger bit, it is cleared immediately when SEmn = 0.
(c) Serial output enable register m (SOEm) … This register is a register that is used to enable or stop
output of the serial communication operation of each channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOE0
0
0
0
0
0
0
0
0
0
0
0
0
0
SOE02
0/1
SOE01
0/1
SOE00
0/1
0: Stops output by serial communication operation
* For channel n, whose serial output is stopped, the SO0n value of the SO0 register can be set by software.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOE1
0
0
0
0
0
0
0
0
0
0
0
0
0
SOE12
0/1
0
SOE10
0/1
0: Stops output by serial communication operation
* For channel n, whose serial output is stopped, the SO1n value of the SO1 register can be set by software.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
: Setting disabled (fixed by hardware), 0/1: Set to 0 or 1 depending on the usage of the user
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Figure 13-23. Each Register Setting When Stopping the Operation by Channels (2/2)
(d) Serial output register m (SOm) …This register is a buffer register for serial output of each channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO0
0
0
0
0
1
CKO02
0/1
CKO01
0/1
CKO00
0/1
0
0
0
0
1
SO02
0/1
SO01
0/1
SO00
0/1
1: Serial clock output value is “1”
1: Serial data output value is “1”
* When using pins corresponding to each channel as port function pins, set the corresponding CKO0n and SO0n bits to “1”.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO1
0
0
0
0
1
1
1
CKO10
0/1
0
0
0
0
1
SO12
0/1
1
SO10
0/1
1: Serial clock output value is “1”
1: Serial data output value is “1”
* When using pins corresponding to each channel as port function pins, set the corresponding CKO10 and SO1n bits to “1”.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
: Setting disabled (fixed by hardware), 0/1: Set to 0 or 1 depending on the usage of the user
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13.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20) Communication
This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines.
[Data transmission/reception]
• Data length of 7 or 8 bits
• Phase control of transmit/receive data
• MSB/LSB first selectable
• Level setting of transmit/receive data
[Clock control]
• Master/slave selection
• Phase control of I/O clock
• Setting of transfer period by prescaler and internal counter of each channel
[Interrupt function]
• Transfer end interrupt/buffer empty interrupt
[Error detection flag]
• Overrun error
The channels supporting 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20) are channels 0 to 2 of SAU0 and channel
0 of SAU1.
Unit Channel Used as CSI Used as UART Used as Simplified I2C
0 CSI00 UART0 −
1 CSI01 −
2 CSI10 UART1 IIC10
0
3 − −
0 CSI20 UART2 IIC20
1 − −
2 − UART3 (supporting LIN-bus) −
1
3 − −
3-wire serial I/O (CSI00, CSI01, CIS10, CSI20) performs the following six types of communication operations.
• Master transmission (See 13.5.1.)
• Master reception (See 13.5.2.)
• Master transmission/reception (See 13.5.3.)
• Slave transmission (See 13.5.4.)
• Slave reception (See 13.5.5.)
• Slave transmission/reception (See 13.5.6.)
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13.5.1 Master transmission
Master transmission is an operation in which the 78K0R/KG3 outputs a transfer clock and transmits data to another
device.
3-Wire Serial I/O CSI00 CSI01 CSI10 CSI20
Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 2 of SAU0 Channel 0 of SAU1
Pins used SCK00, SO00 SCK01, SO01 SCK10, SO10 SCK20, SO20
INTCSI00 INTCSI01 INTCSI10 INTCSI20 Interrupt
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Error detection flag None
Transfer data length 7 or 8 bits
Transfer rate Max. fCLK/4 [Hz], Min. fCLK/(2 × 211 × 128) [Hz]Note fCLK: System clock frequency
Data phase Selectable by DAPmn bit
• DAPmn = 0: Data output starts from the start of the operation of the serial clock.
• DAPmn = 1: Data output starts half a clock before the start of the serial clock operation.
Clock phase Selectable by CKPmn bit
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
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(1) Register setting
Figure 13-24. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O
(CSI00, CSI01, CSI10, CSI20)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
CKOm2
0/1
CKOm1
0/1
CKOm0
0/1
0
0
0
0
1
SOm2
0/1
SOm1
0/1
SOm0
0/1
Communication starts when these bits are 1 if the data
phase is forward (CKPmn = 0). If the phase is reversed
(CKPmn = 1), communication starts when these bits are 0.
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm2
0/1
SOEm1
0/1
SOEm0
0/1
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
×
SSm2
0/1
SSm1
0/1
SSm0
0/1
(d) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1
CCSmn
0
0
0
0
0
0
STSmn
0
0
SISm0
0
1
0
0
MDmn2
0
MDmn1
0
MDmn0
0/1
Interrupt sources of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(e) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
1
RXEmn
0
DAPmn
0/1
CKPmn
0/1
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0/1
0
SLCmn1
0
SLCmn0
0
0
DLSmn2
1
DLSmn1
1
DLSmn0
0/1
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting
0
Transmit data setting
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
: Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOp
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(2) Operation procedure
Figure 13-25. Initial Setting Procedure for Master Transmission
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Starting initial setting
Setting PER0 register
Setting SPSm register
Setting SMRmn register
Setting SCRmn register
Setting SDRmn register
Setting SOm register
Changing setting of SOEm register
Setting port
Writing to SSm register
Starting communication
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate.
Manipulate the SOmn and CKOmn bits
and set an initial output level.
Set the SOEmn bit to 1 and enable data
output of the target channel.
Enable data output and clock output of
the target channel by setting a port
register and a port mode register.
Set transmit data to the SIOp register (bits
7 to 0 of the SDRmn register) and start
communication.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
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User’s Manual U17894EJ9V0UD 425
Figure 13-26. Procedure for Stopping Master Transmission
Remarks 1. Even after communication is stopped, the pin level is retained. To resume the operation, re-set
the SOm register (see Figure 13-27 Procedure for Resuming Master Transmission).
2. p: CSI number (p = 00, 01, 10, 20)
Starting setting to stop
Setting STm register
Stopping communication
Write 1 to the STmn bit of the target
channel.
Stop communication in midway.
Set the SOEm register and stop the
output of the target channel
Changing setting of SOEm
register
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Figure 13-27. Procedure for Resuming Master Transmission
Starting setting for resumption
Port manipulation
Changing setting of SPSm register
Changing setting of SDRmn register
Changing setting of SMRmn register
Changing setting of SOm register
Port manipulation
Writing to SSm register
Starting communication
Disable data output and clock output of
the target channel by setting a port
register and a port mode register.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if an incorrect
transfer baud rate is set.
Change the setting if the setting of the
SMRmn register is incorrect.
Manipulate the SOmn and CKOmn bits
and set an initial output level.
Enable data output and clock output of
the target channel by setting a port
register and a port mode register.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set transmit data to the SIOp register (bits 7
to 0 of the SDRmn register) and start
communication.
(Essential)
(Selective)
(Selective)
(Selective)
(
Selective
)
(
Essential
)
(Essential)
(Essential)
Change the setting if the setting of the
SCRmn register is incorrect.
(Selective) Changing setting of SCRmn register
Cleared by using SIRmn registe
r
if FEF,
PEF, or OVF flag remains set.
(Selective) Clearing error flag
Set the SOEm register and enable data
output of the target channel.
(Selective) Changing setting of SOEm register
Set the SOEm register and stop the
output of the target channel.
(Selective) Changing setting of SOEm register
CHAPTER 13 SERIAL ARRAY UNIT
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(3) Processing flow (in single-transmission mode)
Figure 13-28. Timing Chart of Master Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0,
CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
SCKp pin
SOp pin
Shift
register mn
INTCSIp
TSFmn
Data transmission (8-bit length) Data transmission (8-bit length) Data transmission (8-bit length)
Transmit data 3
Transmit data 2
Transmit data 1
Transmit data 1 Transmit data 2 Transmit data 3
Shift operation Shift operation Shift operation
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 13-29. Flowchart of Master Transmission (in Single-Transmission Mode)
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Starting CSI communication
Writing 1 to SSmn bit
Writing transmit data to
SIOp (=SDRmn[7:0])
Writing 1 to STmn bit
Perform initial setting when SEmn = 0.
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting transfer rate
SOm, SOEm: Setting output
Transfer end interrupt
g
enerated?
Transmission completed?
No
No
Yes
Yes
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting operation clock by
SPSm register
Port manipulation
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
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(4) Processing flow (in continuous transmission mode)
Figure 13-30. Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0,
CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SOp pin
Shift
register mn
INTCSIp
TSFmn
Data transmission (8-bit length) Data transmission (8-bit length)
Transmit data 2
Transmit data 1
Transmit data 3
BFFmn
MDmn0
Transmit data 2
<1>
<2>
<2>
<2>
<3>
<3> <3> <5><6><4>
(Note)
Shift operation Shift operation Shift operation
Transmit data 3
Data transmission (8-bit length)
STmn
Transmit data 1
Note When transmit data is written to the SDRmn register while BFFmn = 1, the transmit data is overwritten.
Caution The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten before
the transfer end interrupt of the last transmit data.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
CHAPTER 13 SERIAL ARRAY UNIT
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Figure 13-31. Flowchart of Master Transmission (in Continuous Transmission Mode)
Starting CSI communication
Writing 1 to SSmn bit
Writing transmit data to
SIOp (=SDRmn[7:0])
Writing 1 to STmn bit
Perform initial setting when SEmn = 0.
<1> Select the buffer empty interrupt.
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting transfer rate
SOm, SOEm; Setting output
N
o
N
o
N
o
Y
es
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting operation clock by
SPSm register
Port manipulation
End of communication
Clearing 0 to MDmn0 bit
Y
es
N
o
Y
es
N
o
Communication continued?
Y
es
Y
es
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
<2>
<3>
<4>
<5>
Transmitting next data?
Buffer empty interrupt
generated?
Transfer end interrupt
generated?
TSFmn = 1?
Writing 1 to MDmn0 bit
<6>
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 13-30 Timing Chart of Master
Transmission (in Continuous Transmission Mode).
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13.5.2 Master reception
Master reception is an operation in which the 78K0R/KG3 outputs a transfer clock and receives data from another
device.
3-Wire Serial I/O CSI00 CSI01 CSI10 CSI20
Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 2 of SAU0 Channel 0 of SAU1
Pins used SCK00, SI00 SCK01, SI01 SCK10, SI10 SCK20, SI20
INTCSI00 INTCSI01 INTCSI10 INTCSI20 Interrupt
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 7 or 8 bits
Transfer rate Max. fCLK/4 [Hz], Min. fCLK/(2 × 211 × 128) [Hz]Note fCLK: System clock frequency
Data phase Selectable by DAPmn bit
• DAPmn = 0: Data input starts from the start of the operation of the serial clock.
• DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Clock phase Selectable by CKPmn bit
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) ).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
<R>
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(1) Register setting
Figure 13-32. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10, CSI20)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
CKOm2
0/1
CKOm1
0/1
CKOm0
0/1
0
0
0
0
1
SOm2
×
SOm1
×
SOm0
×
Communication starts when these bits are 1 if the data
phase is forward (CKPmn = 0). If the phase is reversed
(CKPmn = 1), communication starts when these bits are 0.
(b) Serial output enable register m (SOEm) …The register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm2
×
SOEm1
×
SOEm0
×
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
×
SSm2
0/1
SSm1
0/1
SSm0
0/1
(d) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1
CCSmn
0
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
0
MDmn1
0
MDmn0
0/1
Interrupt sources of channel n
0: Transfer end interrupt
1: Buffer em
p
t
y
interru
p
t
(e) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
0
RXEmn
1
DAPmn
0/1
CKPmn
0/1
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0/1
0
SLCmn1
0
SLCmn0
0
0
DLSmn2
1
DLSmn1
1
DLSmn0
0/1
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting
0
Receive data register
(Write FFH as dummy data.)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
: Setting is fixed in the CSI master reception mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOp
<R>
<R>
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(2) Operation procedure
Figure 13-33. Initial Setting Procedure for Master Reception
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Figure 13-34. Procedure for Stopping Master Reception
Remark Even after communication is stopped, the pin level is retained. To resume the operation, re-set the
SOm register (see Figure 13-35 Procedure for Resuming Master Reception).
Starting initial setting
Setting PER0 register
Setting SPSm register
Setting SMRmn register
Setting SCRmn register
Setting SDRmn register
Setting SOm register
Setting port
Writing to SSm register
Starting communication
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate.
Manipulate the CKOmn bit and set an
initial output level.
Enable clock output of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set dummy data to the SIOp register (bits
7 to 0 of the SDRmn register) and start
communication.
Starting setting to stop
Setting STm register
Stopping communication
Write 1 to the STmn bit of the target
channel.
Stop communication in midway.
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Figure 13-35. Procedure for Resuming Master Reception
Starting setting for resumption
Port manipulation
Changing setting of SPSm register
Changing setting of SDRmn register
Changing setting of SMRmn register
Changing setting of SOm register
Port manipulation
Writing to SSm register
Starting communication
Disable clock output of the target
channel by setting a port register and a
port mode register.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if an incorrect
transfer baud rate is set.
Change the setting if the setting of the
SMRmn register is incorrect.
Manipulate the CKOmn bit and set a
clock output level.
Enable clock output of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set dummy data to the SIOp register (bits
7 to 0 of the SDRmn register) and start
communication.
(Essential)
(Selective)
(Selective)
(
Selective
)
(Selective)
(
Essential
)
(Essential)
(Essential)
Change the setting if the setting of the
SCRmn register is incorrect.
(Selective)
Changing setting of SCRmn register
Cleared by using SIRmn register if FEF,
PEF, or OVF flag remains set.
(Selective) Clearing error flag
<R>
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(3) Processing flow (in single-reception mode)
Figure 13-36. Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
Shift
register mn
INTCSIp
TSFmn
Data reception (8-bit length) Data reception (8-bit length) Data reception (8-bit length)
Reception & shift operation Reception & shift operation
Reception & shift operation
STmn
Receive data 3
Receive data 2
Receive data 1
Dummy data for reception Dummy data Dummy data
Receive data 1 Receive data 2 Receive data 3
Write
Read Write
Read Read
Write
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 13-37. Flowchart of Master Reception (in Single-Reception Mode)
Starting CSI communication
Writing 1 to SSmn bit
Writing dummy data to
SIOp (=SDRmn[7:0])
Writing 1 to STmn bit
Perform initial setting when SEmn = 0.
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting transfer rate
SOm Setting SCKp output
Transfer end interrupt
generated?
Reception completed?
No
No
Yes
Yes
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
Port manipulation
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
Reading
SIOp (= SDRmn[7:0])
register
Starting reception
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
<R>
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(4) Processing flow (in continuous reception mode)
Figure 13-38. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
Shift
register mn
INTCSIp
TSFmn
Reception & shift operation Reception & shift operation
BFFmn
Reception & shift operation
MDmn0
Data reception (8-bit length) Data reception (8-bit length) Data reception (8-bit length)
STmn
<4> <5>
Dummy data Dummy data
Receive data 3
Write
Read Read Read
Write
<1>
<2>
<3>
<2>
<3>
<4> <2>
<7> <8>
Dummy data
Write
<6>
<3>
Receive data 2
Receive data 1
Receive data 1 Receive data 2 Receive data 3
Caution The MDmn0 bit can be rewritten even during operation.
However, rewrite it before receive of the last bit is started, so that it has been rewritten before
the transfer end interrupt of the last receive data.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 13-39 Flowchart of Master
Reception (in Continuous Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
<R>
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Figure 13-39. Flowchart of Master Reception (in Continuous Reception Mode)
Starting CSI communication
Writing 1 to SSmn bit
Reading receive data from
SIOp (=SDRmn[7:0])
Writing 1 to STmn bit
Perform initial setting when SEmn = 0.
<1> Select the buffer empty interrupt.
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting transfer rate
SOm Setting output and SCKp output
Y
es
Y
es
N
o
N
o
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
Port manipulation
End of communication
Clearing 0 to MDmn0 bit
N
o
Transfer end interrupt
generated?
Y
es
N
o
Communication continued?
Y
es
Y
es
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
The following is the last
receive data?
Writing dummy data to SIOp
(=SDRmn[7:0])
TSFmn = 1?
Reading receive data from
SIOp (=SDRmn[7:0])
Writing 1 to MDmn0 bit
Buffer empty interrupt
generated?
<2>
<3>
<5>
<6>
<7>
<4>
<8>
N
o
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 13-38 Timing Chart of Master
Reception (in Continuous Reception Mode).
<R>
CHAPTER 13 SERIAL ARRAY UNIT
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13.5.3 Master transmission/reception
Master transmission/reception is an operation in which the 78K0R/KG3 outputs a transfer clock and
transmits/receives data to/from another device.
3-Wire Serial I/O CSI00 CSI01 CSI10 CSI20
Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 2 of SAU0 Channel 0 of SAU1
Pins used SCK00, SI00, SO00 SCK01, SI01, SO01 SCK10, SI10, SO10 SCK20, SI20, SO20
INTCSI00 INTCSI01 INTCSI10 INTCSI20 Interrupt
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 7 or 8 bits
Transfer rate Max. fCLK/4 [Hz], Min. fCLK/(2 × 211 × 128) [Hz]Note fCLK: System clock frequency
Data phase Selectable by DAPmn bit
• DAPmn = 0: Data I/O starts at the start of the operation of the serial clock.
• DAPmn = 1: Data I/O starts half a clock before the start of the serial clock operation.
Clock phase Selectable by CKPmn bit
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
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(1) Register setting
Figure 13-40. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10, CSI20)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
CKOm2
0/1
CKOm1
0/1
CKOm0
0/1
0
0
0
0
1
SOm2
0/1
SOm1
0/1
SOm0
0/1
Communication starts when these bits are 1 if the data
phase is forward (CKPmn = 0). If the phase is reversed
(CKPmn = 1), communication starts when these bits are 0.
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm2
0/1
SOEm1
0/1
SOEm0
0/1
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
×
SSm2
0/1
SSm1
0/1
SSm0
0/1
(d) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1
CCSmn
0
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
0
MDmn1
0
MDmn0
0/1
Interrupt sources of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(e) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
1
RXEmn
1
DAPmn
0/1
CKPmn
0/1
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0/1
0
SLCmn1
0
SLCmn0
0
0
DLSmn2
1
DLSmn1
1
DLSmn0
0/1
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting
0
Transmit data setting/receive data register
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
: Setting is fixed in the CSI master transmission/reception mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOp
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(2) Operation procedure
Figure 13-41. Initial Setting Procedure for Master Transmission/Reception
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Figure 13-42. Procedure for Stopping Master Transmission/Reception
Remark Even after communication is stopped, the pin level is retained. To resume the operation, re-set the
SOm register (see Figure 13-43 Procedure for Resuming Master Transmission/Reception).
Starting initial setting
Setting PER0 register
Setting SPSm register
Setting SMRmn register
Setting SCRmn register
Setting SDRmn register
Setting SOm register
Changing setting of SOEm register
Setting port
Writing to SSm register
Starting communication
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate.
Manipulate the SOmn and CKOmn bits
and set an initial output level.
Set the SOEmn bit to 1 and enable data
output of the target channel.
Enable data output and clock output of
the target channel by setting a port
register and a port mode register.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set transmit data to the SIOp register
(bits 7 to 0 of the SDRmn register) and
start communication.
Starting setting to stop
Setting STm register Write 1 to the STmn bit of the target
channel.
Changing setting of SOEm
register
Stopping communication
Set the SOEm register and stop the
output of the target channel.
Stop communication in midway.
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Figure 13-43. Procedure for Resuming Master Transmission/Reception
Starting setting for resumption
Port manipulation
Changing setting of SPSm register
Changing setting of SDRmn register
Changing setting of SMRmn register
Changing setting of SOm register
Disable data output and clock output of
the target channel by setting a port
register and a port mode register.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if an incorrect
transfer baud rate is set.
Change the setting if the setting of the
SMRmn register is incorrect.
Manipulate the SOmn and CKOmn bits
and set an initial output level.
(Essential)
(Selective)
(Selective)
(Selective)
(Selective)
Change the setting if the setting of the
SCRmn register is incorrect.
(Selective) Changing setting of SCRmn register
Cleared by using SIRmn registe
r
if FEF,
PEF, or OVF flag remains set.
(Selective) Clearing error flag
Set the SOEm register and stop the
output of the target channel.
(Selective) Changing setting of SOEm register
Changing setting of SOEm register
Port manipulation
Writing to SSm register
Starting communication
Set the SOEm register and enable the
output of the target channel.
Enable data output and clock output of
the target channel by setting a port
register and a port mode register.
Set the SSmn bit of the target channel to
1 and set SEmn to 1.
Set transmit data to the SIOp register (bits 7
to 0 of the SDRmn register) and start
communication.
(Selective)
(
Essential
)
(Essential)
(Essential)
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(3) Processing flow (in single-transmission/reception mode)
Figure 13-44. Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
Shift
register mn
INTCSIp
TSFmn
Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) Data transmission/reception (8-bit length)
SOp pin
Reception & shift operation Reception & shift operation
Reception & shift operation
STmn
Receive data 3
Receive data 2
Receive data 1
Transmit data 1 Transmit data 2
Receive data 1 Receive data 2 Receive data 3
Write
Read
Write
Read Read
Write
Transmit data 3
Transmit data 2
Transmit data 1
Transmit data 2
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 13-45. Flowchart of Master Transmission/Reception (in Single- Transmission/Reception Mode)
Starting CSI communication
Writing 1 to SSmn bit
Writing transmit data to
SIOp (=SDRmn[7:0])
Writing 1 to STmn bit
Perform initial setting when SEmn = 0.
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting transfer rate
SOm, SOEm: Setting output and SCKp output
Transfer end interrupt
generated?
Transmission/reception
completed?
No
No
Yes
Yes
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting operation clock by
SPSm register
Port manipulation
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
Reading
SIOp (=SDRmn[7:0])
register
Starting transmission/reception
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
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(4) Processing flow (in continuous transmission/reception mode)
Figure 13-46. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
Shift
register mn
INTCSIp
TSFmn
SOp pin
Reception & shift operation Reception & shift operation
BFFmn
Reception & shift operation
MDmn0
Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) Data transmission/reception (8-bit length)
STmn
<4> <5>
Transmit data 1 Transmit data 3
Receive data 3
Write
Read Read Read
Write
<1>
<2>
<3>
<2>
<3>
<4> <2>
<7> <8>
(Note 1)
Transmit data 2
Write
<6>
<3>
(Note 2)(Note 2)
Receive data 2
Receive data 1
Receive data 1 Receive data 2 Receive data 3
Transmit data 3
Transmit data 2
Transmit data 1
Notes 1. When transmit data is written to the SDRmn register while BFFmn = 1, the transmit data is
overwritten.
2. The transmit data can be read by reading the SDRmn register during this period. At this time, the
transfer operation is not affected.
Caution The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been rewritten
before the transfer end interrupt of the last transmit data.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 13-47 Flowchart of Master
Transmission/Reception (in Continuous Transmission/Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 13-47. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode)
Starting CSI communication
Writing 1 to SSmn bit
Reading receive data from
SIOp (=SDRmn[7:0])
Writing 1 to STmn bit
Perform initial setting when SEmn = 0.
<1> Select the buffer empty interrupt.
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting transfer rate
SOm, SOEm: Setting output and SCKp output
Y
es
Y
es
N
o
N
o
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting operation clock by
SPSm register
Port manipulation
End of communication
Clearing 0 to MDmn0 bit
N
o
Transfer end interrupt
generated?
Y
es
N
o
Communication continued?
Y
es
Y
es
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
Communication data
exists?
Writing transmit data to
SIOp (=SDRmn[7:0])
TSFmn = 1?
Reading receive data from
SIOp (=SDRmn[7:0])
Writing 1 to MDmn0 bit
Buffer empty interrupt
generated?
<2>
<3>
<5>
<6>
<7>
<4>
<8>
N
o
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 13-46 Timing Chart of Master
Transmission/Reception (in Continuous Transmission/Reception Mode).
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13.5.4 Slave transmission
Slave transmission is an operation in which the 78K0R/KG3 transmits data to another device in the state of a
transfer clock being input from another device.
3-Wire Serial I/O CSI00 CSI01 CSI10 CSI20
Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 2 of SAU0 Channel 0 of SAU1
Pins used SCK00, SO00 SCK01, SO01 SCK10, SO10 SCK20, SO20
INTCSI00 INTCSI01 INTCSI10 INTCSI20 Interrupt
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 7 or 8 bits
Transfer rate Max. fMCK/6 [Hz]Notes 1, 2
Data phase Selectable by DAPmn bit
• DAPmn = 0: Data output starts from the start of the operation of the serial clock.
• DAPmn = 1: Data output starts half a clock before the start of the serial clock operation.
Clock phase Selectable by CKPmn bit
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
Data direction MSB or LSB first
Notes 1. Because the external serial clock input to pins SCK00, SCK01, SCK10, and SCK20 is sampled internally
and used, the fastest transfer rate is fMCK/6 [Hz].
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
electrical specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD
PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
Remarks 1. fMCK: Operation clock (MCK) frequency of target channel
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
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(1) Register setting
Figure 13-48. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O
(CSI00, CSI01, CSI10, CSI20)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
CKOm2
×
CKOm1
×
CKOm0
×
0
0
0
0
1
SOm2
0/1
SOm1
0/1
SOm0
0/1
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm2
0/1
SOEm1
0/1
SOEm0
0/1
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
×
SSm2
0/1
SSm1
0/1
SSm0
0/1
(d) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1
CCSmn
1
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
0
MDmn1
0
MDmn0
0/1
Interrupt sources of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(e) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
1
RXEmn
0
DAPmn
0/1
CKPmn
0/1
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0/1
0
SLCmn1
0
SLCmn0
0
0
DLSmn2
1
DLSmn1
1
DLSmn0
0/1
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting
0
Transmit data setting
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
: Setting is fixed in the CSI slave transmission mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOp
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(2) Operation procedure
Figure 13-49. Initial Setting Procedure for Slave Transmission
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Starting initial setting
Setting PER0 register
Setting SPSm register
Setting SMRmn register
Setting SCRmn register
Setting SDRmn register
Setting SOm register
Changing setting of SOEm register
Setting port
Writing to SSm register
Starting communication
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set bits 15 to 9 to 0000000B for baud
rate setting.
Manipulate the SOmn bit and set an
initial output level.
Set the SOEmn bit to 1 and enable data
output of the target channel.
Enable data output of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set transmit data to the SIOp register
(bits 7 to 0 of the SDRmn register) and
wait for a clock from the master.
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Figure 13-50. Procedure for Stopping Slave Transmission
Remark Even after communication is stopped, the pin level is retained. To resume the operation, re-set the
SOm register (see Figure 13-51 Procedure for Resuming Slave Transmission).
Starting setting to stop
Setting STm register Write 1 to the STmn bit of the target
channel.
Changing setting of SOEm
register
Stopping communication
Set the SOEm register and stop the
output of the target channel.
Stop communication in midway.
CHAPTER 13 SERIAL ARRAY UNIT
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Figure 13-51. Procedure for Resuming Slave Transmission
Starting setting for resumption
Port manipulation
Changing setting of SPSm register
Changing setting of SMRmn register
Disable data output of the target channel
by setting a port register and a port
mode register.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if the setting of the
SMRmn register is incorrect.
(Selective)
(Selective)
(Selective)
Change the setting if the setting of the
SCRmn register is incorrect.
(Selective) Changing setting of SCRmn register
Cleared by using SIRmn registe
r
if FEF,
PEF, or OVF flag remains set.
(Selective) Clearing error flag
Stop the target fo
r
communication or wait
until the target completes its operation.
(Essential) Manipulating target for communication
Changing setting of SOm register
Port manipulation
Writing to SSm register
Manipulate the SOmn bit and set an
initial output level.
Enable data output of the target channel
by setting a port register and a port
mode register.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set transmit data to the SIOp register (bits 7
to 0 of the SDRmn register) and wait for a
clock from the master.
(Selective)
(
Essential
)
(Essential)
(Essential)
Set the SOEm register and stop the
output of the target channel.
(Selective) Changing setting of SOEm register
Set the SOEm register and enable the
output of the target channel.
(Selective) Changing setting of SOEm register
Starting target for communication Start the target for communication.
(Essential)
Starting communication
<R>
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(3) Processing flow (in single-transmission mode)
Figure 13-52. Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn
= 0)
SSmn
SEmn
SDRmn
SCKp pin
SOp pin
Shift
register mn
INTCSIp
TSFmn
STmn
Data transmission (8-bit length) Data transmission (8-bit length) Data transmission (8-bit length)
Transmit data 3
Transmit data 2
Transmit data 1
Transmit data 1 Transmit data 2 Transmit data 3
Shift operation
Shift operation
Shift operation
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 13-53. Flowchart of Slave Transmission (in Single-Transmission Mode)
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Starting CSI communication
Writing 1 to SSmn bit
Writing transmit data to
SIOp (=SDRmn[7:0])
Writing 1 to STmn bit
Perform initial setting when SEmn = 0.
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting 0000000B
SOm, SOEm: Setting output
Transfer end interrupt
generated?
Transmission completed?
No
No
Yes
Yes
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
Port manipulation
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
<R>
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(4) Processing flow (in continuous transmission mode)
Figure 13-54. Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0,
CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SOp pin
Shift
register mn
INTCSIp
TSFmn
BFFmn
MDmn0
STmn
Data transmission (8-bit length) Data transmission (8-bit length)
Transmit data 2
Transmit data 1
Transmit data 3
Transmit data 2
<1>
<2>
<2>
<2>
<3>
<3> <3> <5><4>
(Note)
Shift operation Shift operation Shift operation
Transmit data 3
Data transmission (8-bit length)
Transmit data 1
<6>
Note When transmit data is written to the SDRmn register while BFFmn = 1, the transmit data is overwritten.
Caution The MDmn0 bit can be rewritten even during operation. However, rewrite it before transfer of
the last bit is started.
CHAPTER 13 SERIAL ARRAY UNIT
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Figure 13-55. Flowchart of Slave Transmission (in Continuous Transmission Mode)
Starting CSI communication
Writing 1 to SSmn bit
Writing transmit data to
SIOp (=SDRmn[7:0])
Writing 1 to STmn bit
Perform initial setting when SEmn = 0.
<1> Select the buffer empty interrupt.
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting 0000000B
SOm, SOEm: Setting output
N
o
N
o
N
o
Y
es
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
Port manipulation
End of communication
Clearing 0 to MDmn0 bit
Y
es
N
o
Y
es
N
o
Communication continued?
Y
es
Y
es
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
<2>
<3>
<4>
<5>
Transmitting next data?
Buffer empty interrupt
generated?
Transfer end interrupt
generated?
TSFmn = 1?
Writing 1 to MDmn0 bit
<6>
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 13-54 Timing Chart of Slave
Transmission (in Continuous Transmission Mode).
<R>
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13.5.5 Slave reception
Slave reception is an operation in which the 78K0R/KG3 receives data from another device in the state of a transfer
clock being input from another device.
3-Wire Serial I/O CSI00 CSI01 CSI10 CSI20
Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 2 of SAU0 Channel 0 of SAU1
Pins used SCK00, SI00 SCK01, SI01 SCK10, SI10 SCK20, SI20
INTCSI00 INTCSI01 INTCSI10 INTCSI20 Interrupt
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 7 or 8 bits
Transfer rate Max. fMCK/6 [Hz]Notes 1, 2
Data phase Selectable by DAPmn bit
• DAPmn = 0: Data input starts from the start of the operation of the serial clock.
• DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Clock phase Selectable by CKPmn bit
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
Data direction MSB or LSB first
Notes 1. Because the external serial clock input to pins SCK00, SCK01, SCK10, and SCK20 is sampled internally
and used, the fastest transfer rate is fMCK/6 [Hz].
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
electrical specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD
PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
Remarks 1. fMCK: Operation clock (MCK) frequency of target channel
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
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(1) Register setting
Figure 13-56. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10, CSI20)
(a) Serial output register m (SOm) …The register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
CKOm2
×
CKOm1
×
CKOm0
×
0
0
0
0
1
SOm2
×
SOm1
×
SOm0
×
(b) Serial output enable register m (SOEm) …The register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm2
×
SOEm1
×
SOEm0
×
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
×
SSm2
0/1
SSm1
0/1
SSm0
0/1
(d) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1
CCSmn
1
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
0
MDmn1
0
MDmn0
0
Interrupt sources of channel n
0: Transfer end interrupt
(e) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
0
RXEmn
1
DAPmn
0/1
CKPmn
0/1
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0/1
0
SLCmn1
0
SLCmn0
0
0
DLSmn2
1
DLSmn1
1
DLSmn0
0/1
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0000000
(baud rate setting)
0
Receive data register
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
: Setting is fixed in the CSI slave reception mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOp
<R>
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(2) Operation procedure
Figure 13-57. Initial Setting Procedure for Slave Reception
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Figure 13-58. Procedure for Stopping Slave Reception
Starting initial settings
Setting PER0 register
Setting SPSm register
Setting SMRmn register
Setting SCRmn register
Setting SDRmn register
Setting port
Writing to SSm register
Starting communication
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set bits 15 to 9 to 0000000B for baud
rate setting.
Enable data input and clock input of the
target channel by setting a port register
and a port mode register.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Wait for a clock from the master.
Starting setting to stop
Setting STm register
Stopping communication
Write 1 to the STmn bit of the target
channel.
Stop communication in midway.
CHAPTER 13 SERIAL ARRAY UNIT
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Figure 13-59. Procedure for Resuming Slave Reception
Starting setting for resumption
Port manipulation
Changing setting of SPSm register
Changing setting of SMRmn register
Port manipulation
Writing to SSm register
Starting communication
Disable clock output of the target
channel by setting a port register and a
port mode register.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if the setting of the
SMRmn register is incorrect.
Enable clock output of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Wait for a clock from the master.
(Essential)
(Selective)
(Selective)
(Essential)
(Essential)
(Essential)
Change the setting if the setting of the
SCRmn register is incorrect.
(Selective)
Changing setting of SCRmn register
Cleared by using SIRmn register if FEF,
PEF, or OVF flag remains set.
(Selective) Clearing error flag
Manipulating target for communication
Stop the target for communication or wait
until the target completes its operation.
(Essential)
<R>
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(3) Processing flow (in single-reception mode)
Figure 13-60. Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
Shift
register mn
INTCSIp
TSFmn
STmn
Data reception (8-bit length) Data reception (8-bit length) Data reception (8-bit length)
Receive data 3
Receive data 2
Receive data 1
Receive data 1 Receive data 2
Receive data 3
Read Read Read
Reception & shift operation Reception & shift operation Reception & shift operation
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 13-61. Flowchart of Slave Reception (in Single-Reception Mode)
Starting CSI communication
Writing 1 to SSmn bit
Writing 1 to STmn bit
Perform initial setting when SEmn = 0.
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting 0000000B
Transfer end interrupt
generated?
Reception completed?
No
No
Yes
Yes
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
Port manipulation
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
Reading
SIOp (=SDRmn[7:0])
register
Starting reception
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
<R>
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13.5.6 Slave transmission/reception
Slave transmission/reception is an operation in which the 78K0R/KG3 transmits/receives data to/from another
device in the state of a transfer clock being input from another device.
3-Wire Serial I/O CSI00 CSI01 CSI10 CSI20
Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 2 of SAU0 Channel 0 of SAU1
Pins used SCK00, SI00, SO00 SCK01, SI01, SO01 SCK10, SI10, SO10 SCK20, SI20, SO20
INTCSI00 INTCSI01 INTCSI10 INTCSI20 Interrupt
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 7 or 8 bits
Transfer rate Max. fMCK/6 [Hz]Notes 1, 2
Data phase Selectable by DAPmn bit
• DAPmn = 0: Data I/O starts from the start of the operation of the serial clock.
• DAPmn = 1: Data I/O starts half a clock before the start of the serial clock operation.
Clock phase Selectable by CKPmn bit
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
Data direction MSB or LSB first
Notes 1. Because the external serial clock input to pins SCK00, SCK01, SCK10, and SCK20 is sampled internally
and used, the fastest transfer rate is fMCK/6 [Hz].
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
electrical specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD
PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
Remarks 1. fMCK: Operation clock (MCK) frequency of target channel
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
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(1) Register setting
Figure 13-62. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI10, CSI20)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
CKOm2
×
CKOm1
×
CKOm0
×
0
0
0
0
1
SOm2
0/1
SOm1
0/1
SOm0
0/1
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm2
0/1
SOEm1
0/1
SOEm0
0/1
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
×
SSm2
0/1
SSm1
0/1
SSm0
0/1
(d) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1
CCSmn
1
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
0
MDmn1
0
MDmn0
0/1
Interrupt sources of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(e) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
1
RXEmn
1
DAPmn
0/1
CKPmn
0/1
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0/1
0
SLCmn1
0
SLCmn0
0
0
DLSmn2
1
DLSmn1
1
DLSmn0
0/1
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0000000
(baud rate setting)
0
Transmit data setting/receive data register
Caution Be sure to set transmit data to the SlOp register before the clock from the master is started.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
: Setting is fixed in the CSI slave transmission/reception mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOp
<R>
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(2) Operation procedure
Figure 13-63. Initial Setting Procedure for Slave Transmission/Reception
Cautions 1. After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
2. Be sure to set transmit data to the SlOp register before the clock from the master is
started.
Starting initial setting
Setting PER0 register
Setting SPSm register
Setting SMRmn register
Setting SCRmn register
Setting SDRmn register
Setting SOm register
Changing setting of SOEm register
Setting port
Writing to SSm register
Starting communication
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set bits 15 to 9 to 0000000B for baud
rate setting.
Manipulate the SOmn bit and set an
initial output level.
Set the SOEmn bit to 1 and enable data
output of the target channel.
Enable data output of the target channel
by setting a port register and a port
mode register.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set transmit data to the SIOp register
(bits 7 to 0 of the SDRmn register) and
wait for a clock from the master.
<R>
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Figure 13-64. Procedure for Stopping Slave Transmission/Reception
Remark Even after communication is stopped, the pin level is retained. To resume the operation, re-set the
SOm register (see Figure 13-65 Procedure for Resuming Slave Transmission/Reception).
Starting setting to stop
Setting STm register Write 1 to the STmn bit of the target
channel.
Changing setting of SOEm
register
Stopping communication
Set the SOEm register and stop the
output of the target channel.
Stop communication in midway.
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Figure 13-65. Procedure for Resuming Slave Transmission/Reception
Caution Be sure to set transmit data to the SlOp register before the clock from the master is
started.
Starting setting for resumption
Manipulating target for communication
Port manipulation
Changing setting of SPSm register
Changing setting of SMRmn register
Changing setting of SOm register
Stop the target fo
r
communication or wait
until the target completes its operation.
Disable data output of the target channel
by setting a port register and a port
mode register.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if the setting of the
SMRmn register is incorrect.
Manipulate the SOmn bit and set an
initial output level.
(Essential)
(Essential)
(
Selective
)
(Selective)
(Selective)
Clearing error flag
(
Selective
)
Cleared by using SIRmn registe
r
if FEF,
PEF, or OVF flag remains set.
Changing setting of SCRmn register Change the setting if the setting of the
SCRmn register is incorrect.
(Selective)
Changing setting of SOEm register Set the SOEm register and stop the
output of the target channel.
(Selective)
Changing setting of SOEm register
Port manipulation
Writing to SSm register
Set the SOEm register and enable the
output of the target channel.
Enable data output of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
(Selective)
(Essential)
(Essential)
Starting communication
Starting target for communication
Set transmit data to the SIOp register
(bits 7 to 0 of the SDRmn register) and
wait for a clock from the master.
Start the target for communication.
(Essential)
(Essential)
<R>
<R>
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(3) Processing flow (in single-transmission/reception mode)
Figure 13-66. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
Shift
register mn
INTCSIp
TSFmn
SOp pin
STmn
Data transmission/reception (8-bit length)
Receive data 3
Receive data 2
Receive data 1
Transmit data 1 Transmit data 2 Transmit data 3
Receive data 2 Receive data 3
Write
Read
Write
Read Read
Write
Transmit data 3
Transmit data 2
Transmit data 1
Reception & shift operation Reception & shift operation Reception & shift operation
Receive data 1
Data transmission/reception (8-bit length) Data transmission/reception (8-bit length)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 13-67. Flowchart of Slave Transmission/Reception (in Single- Transmission/Reception Mode)
Starting CSI communication
Writing 1 to SSmn bit
Writing transmit data to
SIOp (=SDRmn[7:0])
Writing 1 to STmn bit
Perform initial setting when SEmn = 0.
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting 0000000B
SOm, SOEm: Setting output
Transfer end interrupt
generated?
Transmission/reception
completed?
No
No
Yes
Yes
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
Port manipulation
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
End of communication
Reading
SIOp (=SDRmn[7:0])
register
Starting transmission/reception
Cautions 1. After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
2. Be sure to set transmit data to the SlOp register before the clock from the master is
started.
<R>
<R>
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(4) Processing flow (in continuous transmission/reception mode)
Figure 13-68. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
Shift
register mn
INTCSIp
TSFmn
SOp pin
BFFmn
MDmn0
STmn
<4> <5>
Transmit data 1 Transmit data 3
Receive data 3
Write
Read Read Read
Write
<1>
<2>
<3>
<2>
<3>
<4> <2>
<7><8>
(Note 1)
Transmit data
2
Write
<6>
<3>
(Note 2)(Note 2)
Reception & shift operation
Receive data 2
Receive data 1
Receive data 1 Receive data 2 Receive data 3
Transmit data 3
Transmit data 2
Transmit data 1
Data transmission/reception (8-bit length)
Reception & shift operation Reception & shift operation
Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length)
Notes 1. When transmit data is written to the SDRmn register while BFFmn = 1, the transmit data is
overwritten.
2. The transmit data can be read by reading the SDRmn register during this period. At this time, the
transfer operation is not affected.
Caution The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten before
the transfer end interrupt of the last transmit data.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 13-69 Flowchart of Slave
Transmission/Reception (in Continuous Transmission/Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), p: CSI number (p = 00, 01, 10, 20)
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Figure 13-69. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode)
Starting CSI communication
Writing 1 to SSmn bit
Reading receive data to
SIOp (=SDRmn[7:0])
Writing 1 to STmn bit
Perform initial setting when SEmn = 0.
<1> Select the buffer empty interrupt.
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting 0000000B
SOm, SOEm: Setting output
Y
es
Y
es
N
o
N
o
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
Port manipulation
End of communication
Clearing 0 to MDmn0 bit
N
o
Transfer end interrupt
generated?
Y
es
N
o
Communication continued?
Y
es
Y
es
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
Communication data
exists?
Writing transmit data to
SIOp (=SDRmn[7:0])
TSFmn = 1?
Reading receive data to
SIOp (=SDRmn[7:0])
Writing 1 to MDmn0 bit
Buffer empty interrupt
generated?
<2>
<3>
<5>
<6>
<7>
<4>
<8>
N
o
Cautions 1. After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
2. Be sure to set transmit data to the SlOp register before the clock from the master is
started.
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 13-68 Timing Chart of Slave
Transmission/Reception (in Continuous Transmission/Reception Mode).
<R>
<R>
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13.5.7 Calculating transfer clock frequency
The transfer clock frequency for 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20) communication can be calculated
by the following expressions.
(1) Master
(Transfer clock frequency) = {Operation clock (MCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz]
(2) Slave
(Transfer clock frequency) = {Frequency of serial clock (SCK) supplied by master}Note [Hz]
Note The permissible maximum transfer clock frequency is fMCK/6.
Remarks 1. The value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn register (0000000B to
1111111B) and therefore is 0 to 127.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
The operation clock (MCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial
mode register mn (SMRmn).
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Table 13-2. Selection of Operation Clock
SMRmn
Register
SPSm Register Operation Clock (MCK)Note 1
CKSmn PRS
m13
PRS
m12
PRS
m11
PRS
m10
PRS
m03
PRS
m02
PRS
m01
PRS
m00
fCLK = 20 MHz
X X X X 0 0 0 0 fCLK 20 MHz
X X X X 0 0 0 1 fCLK/2 10 MHz
X X X X 0 0 1 0 fCLK/22 5 MHz
X X X X 0 0 1 1 fCLK/23 2.5 MHz
X X X X 0 1 0 0 fCLK/24 1.25 MHz
X X X X 0 1 0 1 fCLK/25 625 kHz
X X X X 0 1 1 0 fCLK/26 313 kHz
X X X X 0 1 1 1 fCLK/27 156 kHz
X X X X 1 0 0 0 fCLK/28 78.1 kHz
X X X X 1 0 0 1 fCLK/29 39.1 kHz
X X X X 1 0 1 0 fCLK/210 19.5 kHz
X X X X 1 0 1 1 fCLK/211 9.77 kHz
0
X X X X 1 1 1 1 INTTM02 if m = 0,
INTTM03 if m = 1Note 2
0 0 0 0 X X X X fCLK 20 MHz
0 0 0 1 X X X X fCLK/2 10 MHz
0 0 1 0 X X X X fCLK/22 5 MHz
0 0 1 1 X X X X fCLK/23 2.5 MHz
0 1 0 0 X X X X fCLK/24 1.25 MHz
0 1 0 1 X X X X fCLK/25 625 kHz
0 1 1 0 X X X X fCLK/26 313 kHz
0 1 1 1 X X X X fCLK/27 156 kHz
1 0 0 0 X X X X fCLK/28 78.1 kHz
1 0 0 1 X X X X fCLK/29 39.1 kHz
1 0 1 0 X X X X fCLK/210 19.5 kHz
1 0 1 1 X X X X fCLK/211 9.77 kHz
1
1 1 1 1 X X X X INTTM02 if m = 0,
INTTM03 if m = 1Note 2
Other than above Setting prohibited
Notes 1. When changing the clock selected for fCLK (by changing the system clock control register (CKC)
value), do so after having stopped (STm = 000FH) the operation of the serial array unit (SAU).
When selecting INTTM02 and INTTM03 for the operation clock, also stop the timer array unit (TAU)
(TT0 = 00FFH).
2. SAU can be operated at a fixed division ratio of the subsystem clock, regardless of the fCLK
frequency (main system clock, subsystem clock), by operating the interval timer for which fSUB/4
has been selected as the count clock (setting TIS02 (if m = 0) or TIS03 (if m = 1) of the TIS0
register to 1) and selecting INTTM02 and INTTM03 by using the SPSm register in channels 2 and
3 of TAU. When changing fCLK, however, SAU and TAU must be stopped as described in Note 1
above.
Remarks 1. X: Don’t care
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
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13.5.8 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20)
communication
The procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20)
communication is described in Figure 13-70.
Figure 13-70. Processing Procedure in Case of Overrun Error
Software Manipulation Hardware Status Remark
Reads serial data SDRmn register. The BFF = 0, and channel n is enabled
to receive data.
This is to prevent an overrun error if the
next reception is completed during error
processing.
Reads SSRmn register. Error type is identified and the read
value is used to clear error flag.
Writes SIRmn register Error flag is cleared. Only error generated at the point of
reading can be cleared, by writing the
value read from the SSRmn register to
the SIRmn register without modification.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2), mn = 00 to 02, 10
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13.6 Operation of UART (UART0, UART1, UART2, UART3) Communication
This is a start-stop synchronization function using two lines: serial data transmission (TxD) and serial data
reception (RxD) lines. It transmits or receives data in asynchronization with the party of communication (by using an
internal baud rate). Full-duplex UART communication can be realized by using two channels, one dedicated to
transmission (even channel) and the other to reception (odd channel).
[Data transmission/reception]
• Data length of 5, 7, or 8 bits
• Select the MSB/LSB first
• Level setting of transmit/receive data and select of reverse
• Parity bit appending and parity check functions
• Stop bit appending
[Interrupt function]
• Transfer end interrupt/buffer empty interrupt
• Error interrupt in case of framing error, parity error, or overrun error
[Error detection flag]
• Framing error, parity error, or overrun error
The LIN-bus is supported in UART3 (2, 3 channels of unit 1)
[LIN-bus functions]
• Wakeup signal detection
• Sync break field (SBF) detection
• Sync field measurement, baud rate calculation
UART0 uses channels 0 and 1 of SAU0.
UART1 uses channels 2 and 3 of SAU0.
UART2 uses channels 0 and 1 of SAU1.
UART3 uses channels 2 and 3 of SAU1.
Unit Channel Used as CSI Used as UART Used as Simplified I2C
0 CSI00 UART0 −
1 CSI01 −
2 CSI10 UART1 IIC10
0
3 − −
0 CSI20 IIC20
1 −
UART2
−
2 − UART3 (supporting LIN-bus) −
1
3 − −
Caution When using serial array units 0 and 1 as UARTs, the channels of both the transmitting side (even-
number channel) and the receiving side (odd-number channel) can be used only as UARTs.
UART performs the following four types of communication operations.
• UART transmission (See 13.6.1.)
• UART reception (See 13.6.2.)
• LIN transmission (UART3 only) (See 13.6.3.)
• LIN reception (UART 3 only) (See 13.6.4.)
External interrupt (INTP0) or timer array unit (TAU) is
used.
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13.6.1 UART transmission
UART transmission is an operation to transmit data from the 78K0R/KG3 to another device asynchronously (start-
stop synchronization).
Of two channels used for UART, the even channel is used for UART transmission.
UART UART0 UART1 UART2 UART3
Target channel Channel 0 of SAU0 Channel 2 of SAU0 Channel 0 of SAU1 Channel 2 of SAU1
Pins used TxD0 TxD1 TxD2 TxD3
INTST0 INTST1 INTST2 INTST3 Interrupt
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Error detection flag None
Transfer data length 5, 7, or 8 bits
Transfer rate Max. fMCK/6 [bps] (SDRmn [15:9] = 2 or more), Min. fCLK/(2 × 211 × 128) [bps]Note
Data phase Forward output (default: high level)
Reverse output (default: low level)
Parity bit The following selectable
• No parity bit
• Appending 0 parity
• Appending even parity
• Appending odd parity
Stop bit The following selectable
• Appending 1 bit
• Appending 2 bits
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
Remarks 1. f
MCK: Operation clock (MCK) frequency of target channel
f
CLK: System clock frequency
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
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(1) Register setting
Figure 13-71. Example of Contents of Registers for UART Transmission of UART
(UART0, UART1, UART2, UART3) (1/2)
(a) Serial output register m (SOm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
CKOm2
×
CKOm1
×
CKOm0
×
0
0
0
0
1
SOm2
0/1Note
SOm1
×
SOm0
0/1Note
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm2
0/1
SOEm1
×
SOEm0
0/1
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
×
SSm2
0/1
SSm1
×
SSm0
0/1
(d) Serial output level register m (SOLm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOLm
0
0
0
0
0
0
0
0
0
0
0
0
0
SOLm2
0/1
0
SOLm0
0/1
0: Forward (normal) transmission
1: Reverse transmission
(e) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1
CCSmn
0
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
0
MDmn1
1
MDmn0
0/1
Interrupt sources of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
Note Before transmission is started, be sure to set to 1 when the SOLmn bit of the target channel is set to 0,
and set to 0 when the SOLmn bit of the target channel is set to 1. The value varies depending on the
communication data during communication operation.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3)
: Setting is fixed in the UART transmission mode, : Setting disabled (fixed by hardware)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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Figure 13-71. Example of Contents of Registers for UART Transmission of UART
(UART0, UART1, UART2, UART3) (2/2)
(f) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
1
RXEmn
0
DAPmn
0
CKPmn
0
0
EOCmn
0
PTCmn1
0/1
PTCmn0
0/1
DIRmn
0/1
0
SLCmn1
0/1
SLCmn0
0/1
0
DLSmn2
1
DLSmn1
0/1
DLSmn0
0/1
Setting of stop bit
01B: Appending 1 bit
10B: Appending 2 bits
Setting of parity bit
00B: No parity
01B: 0 parity
10B: Even parity
11B: Odd parity
(g) Serial data register mn (SDRmn) (lower 8 bits: TXDq)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting
0
Transmit data setting
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3)
: Setting is fixed in the UART transmission mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
TXDq
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(2) Operation procedure
Figure 13-72. Initial Setting Procedure for UART Transmission
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Starting initial setting
Setting PER0 register
Setting SPSm register
Setting SMRmn register
Setting SCRmn register
Setting SDRmn register
Setting SOm register
Setting port
Changing setting of SOEm register
Writing to SSm register
Starting communication
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate.
Manipulate the SOmn bit and set an
initial output level.
Enable data output of the target channel
by setting a port register and a port mode
register.
Set the SOEmn bit to 1 and enable data
output of the target channel.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set transmit data to the TXDq register (bits
7 to 0 of the SDRmn register) and start
communication.
Changing setting of SOLm register Set an output data level.
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Figure 13-73. Procedure for Stopping UART Transmission
Remark Even after communication is stopped, the pin level is retained. To resume the operation, re-set the
SOm register (see Figure 13-74 Procedure for Resuming UART Transmission).
Starting setting to stop
Setting STm register Write 1 to the STmn bit of the target
channel.
Changing setting of SOEm
register
Stopping communication
Set the SOEmn bit to 0 and stop the
output.
Stop communication in midway.
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Figure 13-74. Procedure for Resuming UART Transmission
Port manipulation
Changing setting of SPSm register
Changing setting of SDRm register
Changing setting of SMRmn register
Changing setting of SOm register
Port manipulation
Writing to SSm register
Starting communication
Disable data output of the target channel
by setting a port register and a port mode
register.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if an incorrect
transfer baud rate is set.
Change the setting if the setting of the
SMRmn register is incorrect.
Manipulate the SOmn bit and set an
initial output level.
Enable data output of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set transmit data to the TXDq register
(bits 7 to 0 of the SDRmn register) and
start communication.
(Essential)
(Selective)
(Essential)
Changing setting of SOEm register
Set the SOEmn bit to 1 and enable
output.
Changing setting of SOEm register
Clear the SOEmn bit to 0 and stop
output.
(Essential)
Changing setting of SCRmn register
Change the setting if the setting of the
SCRmn register is incorrect.
Changing setting of SOLmn register
Change the setting if the setting of the
SOLmn register is incorrect.
Starting setting for resumption
(Essential)
(Essential)
(Essential)
(Essential)
(Selective)
(Selective)
(Selective)
(Selective)
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(3) Processing flow (in single-transmission mode)
Figure 13-75. Timing Chart of UART Transmission (in Single-Transmission Mode)
SSmn
SEmn
SDRmn
TxDq pin
Shift
register mn
INTSTq
TSFmn
PSP
ST ST PSP ST PSP
STmn
Data transmission (7-bit length) Data transmission (7-bit length) Data transmission (7-bit length)
Transmit data 1 Transmit data 2 Transmit data 3
Transmit data 3
Transmit data 2
Transmit data 1
Shift operation Shift operation Shift operation
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3)
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Figure 13-76. Flowchart of UART Transmission (in Single-Transmission Mode)
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Starting UART communication
Writing 1 to SSmn bit
Writing transmit data to
TXDq (=SDRmn[7:0])
Writing 1 to STmn bit
Perform initial setting when SEmn = 0.
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting transfer rate
SOLmn: Setting output data level
SOm, SOEm: Setting output
Transfer end interrupt
g
enerated?
Transmission completed?
No
No
Yes
Yes
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting operation clock by
SPSm register
Port manipulation
End of communication
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
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(4) Processing flow (in continuous transmission mode)
Figure 13-77. Timing Chart of UART Transmission (in Continuous Transmission Mode)
SSmn
SEmn
SDRmn
TxDq pin
Shift
register mn
INTSTq
TSFmn
P
ST ST PST PSP
BFFmn
MDmn0
STmn
SP
SP
Data transmission (7-bit length) Data transmission (7-bit length)
Transmit data 1 Transmit data 2 Transmit data 3
Transmit data 3
Transmit data 2
Transmit data 1
Shift operation Shift operation Shift operation
<1>
<2>
<2>
<3>
(Note)
<2>
<3> <5><3> <4>
Data transmission (7-bit length)
<6>
Note When transmit data is written to the SDRmn register while BFFmn = 1, the transmit data is overwritten.
Caution The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been rewritten
before the transfer end interrupt of the last transmit data.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3)
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Figure 13-78. Flowchart of UART Transmission (in Continuous Transmission Mode)
Starting UART communication
Writing 1 to SSmn bit
Writing transmit data to
TXDq (=SDRmn[7:0])
Writing 1 to STmn bit
Perform initial setting when SEmn = 0.
<1> Select the buffer empty interrupt.
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting transfer rate
SOLmn: Setting output data level
SOm, SOEm: Setting output
N
o
N
o
N
o
Y
es
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting operation clock by
SPSm register
Port manipulation
End of communication
Clearing 0 to MDmn0 bit
Y
es
TSFmn = 1?
Transfer end interrupt
g
enerated?
N
o
Y
es
N
o
Communication continued?
Y
es
Y
es
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
Transmitting next data?
<2>
<3>
Buffer empty interrupt
generated?
Writing 1 to MDmn0 bit
<4>
<5>
<6>
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 13-77 Timing Chart of UART
Transmission (in Continuous Transmission Mode).
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13.6.2 UART reception
UART reception is an operation wherein the 78K0R/KG3 asynchronously receives data from another device (start-
stop synchronization).
For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of
both the odd- and even-numbered channels must be set.
UART UART0 UART1 UART2 UART3
Target channel Channel 1 of SAU0 Channel 3 of SAU0 Channel 1 of SAU1 Channel 3 of SAU1
Pins used RxD0 RxD1 RxD2 RxD3
INTSR0 INTSR1 INTSR2 INTSR3 Interrupt
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error interrupt INTSRE0 INTSRE1 INTSRE2 INTSRE3
Error detection flag • Framing error detection flag (FEFmn)
• Parity error detection flag (PEFmn)
• Overrun error detection flag (OVFmn)
Transfer data length 5, 7, or 8 bits
Transfer rate Max. fMCK/6 [bps] (SDRmn [15:9] = 2 or more), Min. fCLK/(2 × 211 × 128) [bps]Note
Data phase Forward output (default: high level)
Reverse output (default: low level)
Parity bit The following selectable
• No parity bit (no parity check)
• Appending 0 parity (no parity check)
• Appending even parity
• Appending odd parity
Stop bit Appending 1 bit
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
Remarks 1. f
MCK: Operation clock (MCK) frequency of target channel
f
CLK: System clock frequency
2. m: Unit number (m = 0, 1), n: Channel number (n = 1, 3)
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(1) Register setting
Figure 13-79. Example of Contents of Registers for UART Reception of UART
(UART0, UART1, UART2, UART3) (1/2)
(a) Serial output register m (SOm) …The register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
CKOm2
×
CKOm1
×
CKOm0
×
0
0
0
0
1
SOm2
×
SOm1
×
SOm0
×
(b) Serial output enable register m (SOEm) …The register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm2
×
SOEm1
×
SOEm0
×
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
0/1
SSm2
×
SSm1
0/1
SSm0
×
(d) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1
CCSmn
0
0
0
0
0
0
STSmn
1
0
SISmn0
0/1
1
0
0
MDmn2
0
MDmn1
1
MDmn0
0
0: Forward (normal) reception
1: Reverse reception
Interrupt sources of channel n
0: Transfer end interrupt
(e) Serial mode register mr (SMRmr)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmr CKSmr
0/1
CCSmr
0
0
0
0
0
0
STSmr
0
0
SISmr0
0
1
0
0
MDmr2
0
MDmr1
1
MDmr0
0/1
Same setting value as CKSmn
Interrupt sources of channel r
0: Transfer end interrupt
1: Buffer empty interrupt
(f) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
0
RXEmn
1
DAPmn
0
CKPmn
0
0
EOCmn
1
PTCmn1
0/1
PTCmn0
0/1
DIRmn
0/1
0
SLCmn1
0
SLCmn0
1
0
DLSmn2
1
DLSmn1
0/1
DLSmn0
0/1
Caution For the UART reception, be sure to set SMRmr of channel r that is to be paired with channel
n.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), r: Channel number (r = n − 1),
q: UART number (q = 0 to 3)
: Setting is fixed in the UART reception mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
<R>
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Figure 13-79. Example of Contents of Registers for UART Reception of UART
(UART0, UART1, UART2, UART3) (2/2)
(g) Serial data register mn (SDRmn) (lower 8 bits: RXDq)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting
0
Receive data register
Caution For the UART reception, be sure to set SMRmr of channel r that is to be paired with channel
n.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), r: Channel number (r = n − 1),
q: UART number (q = 0 to 3)
: Setting is fixed in the UART reception mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
RXDq
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(2) Operation procedure
Figure 13-80. Initial Setting Procedure for UART Reception
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Figure 13-81. Procedure for Stopping UART Reception
Starting initial setting
Setting PER0 register
Setting SPSm register
Setting SMRmn and SMRmr registers
Setting SCRmn register
Setting SDRmn register
Writing to SSm register
Starting communication
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
The start bit is detected.
Starting setting to stop
Setting STm register
Stopping communication
Write 1 to the STmn bit of the target
channel.
Stop communication in midway.
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Figure 13-82. Procedure for Resuming UART Reception
Starting setting for resumption
Manipulating target for communication
Changing setting of SPSm register
Changing setting of SDRmn register
Writing to SSm
register
Starting communication
Stop the target for communication or wait
until the target completes its operation.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if an incorrect
transfer baud rate is set.
Change the setting if the setting of the
SMRmn and SMRmr registers is incorrect.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
The start bit is detected.
(Essential)
(Selective)
Change the setting if the setting of the
SCRmn register is incorrect.
Changing setting of SCRmn register
Cleared by using SIRmn register if FEF,
PEF, or OVF flag remains set.
Clearing error flag
Changing setting of SMRmn
and SMRmr registers
(Essential)
(Essential)
(Selective)
(Selective)
(Selective)
(Selective)
<R>
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(3) Processing flow
Figure 13-83. Timing Chart of UART Reception
SSmn
SEmn
SDRmn
RxDq pin
Shift
register mn
INTSRq
TSFmn
P
ST ST PST P
STmn
SP SP SP
Data reception (7-bit length) Data reception (7-bit length) Data reception (7-bit length)
Receive data 1 Receive data 2
Receive data 3
Receive data 2
Receive data 1
Shift operation Shift operation Shift operation
Receive data 3
Remark m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), q: UART number (q = 0 to 3)
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Figure 13-84. Flowchart of UART Reception
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Starting UART communication
Writing 1 to SSmn bit
Writing 1 to STmn bit
End of UART communication
Perform initial setting when
SEmn = 0.
SMRmn, SMRmr, SCRmn: Setting communication
SDRmn[15:9]: Setting transfer rate
Transfer end interrupt
generated?
Reception completed?
No
No
Yes
Yes
Starting reception
Reading RXDq register
(SDRmn[7:0])
Detecting start bit
Error interrupt generated?
Error processing
No
Yes
Port manipulation
Clearing SAU1EN and SAU0EN
bits of PER0 register to 0
Setting SAU1EN and SAU0EN
bits of PER0 register to 1
Setting transfer rate by
SPSm register
<R>
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13.6.3 LIN transmission
Of UART transmission, UART3 supports LIN communication.
For LIN transmission, channel 2 of unit 1 (SAU1) is used.
UART UART0 UART1 UART2 UART3
Support of LIN communication Not supported Not supported Not supported Supported
Target channel − − − Channel 2 of SAU1
Pins used − − − TxD3
− − − INTST3
Interrupt
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer
mode) can be selected.
Error detection flag None
Transfer data length 8 bits
Transfer rate Max. fMCK/6 [bps] (SDR12 [15:9] = 2 or more), Min. fCLK/(2 × 211 × 128) [bps]Note
Data phase Forward output (default: high level)
Reverse output (default: low level)
Parity bit The following selectable
• No parity bit
• Appending 0 parity
• Appending even parity
• Appending odd parity
Stop bit The following selectable
• Appending 1 bit
• Appending 2 bits
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
Remark f
MCK: Operation clock (MCK) frequency of target channel
fCLK: System clock frequency
LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol
designed to reduce the cost of an automobile network.
Communication of LIN is single-master communication and up to 15 slaves can be connected to one master.
The slaves are used to control switches, actuators, and sensors, which are connected to the master via LIN.
Usually, the master is connected to a network such as CAN (Controller Area Network).
A LIN bus is a single-wire bus to which nodes are connected via transceiver conforming to ISO9141.
According to the protocol of LIN, the master transmits a frame by attaching baud rate information to it. A slave
receives this frame and corrects a baud rate error from the master. If the baud rate error of a slave is within ±15%,
communication can be established.
Figure 13-85 outlines a transmission operation of LIN.
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Figure 13-85. Transmission Operation of LIN
LIN Bus
Wakeup signal
frame
8 bits
Note 1
55H
transmission
Data
transmission
Data
transmission
Data
transmission
Data
transmission
13-bit SBF
transmission
Note 2
Sync break
field
Sync field Identification
field
Data field Data field Checksum
field
T
X
D3
(output)
INTST3
Note 3
Notes 1. The baud rate is set so as to satisfy the standard of the wakeup signal and data of 00H is transmitted.
2. A sync break field is defined to have a width of 13 bits and output a low level. Where the baud rate for
main transfer is N [bps], therefore, the baud rate of the sync break field is calculated as follows.
(Baud rate of sync break field) = 9/13 × N
By transmitting data of 00H at this baud rate, a sync break field is generated.
3. INTST3 is output upon completion of transmission. INTST3 is also output when SBF transmission is
executed.
Remark The interval between fields is controlled by software.
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Figure 13-86. Flowchart for LIN Transmission
Starting LIN communication
Writing 1 to SS12
Transmitting wakeup
signal frame
Transmitting
sync break field
Writing 1 to ST12
End of LIN communication
Sync break field
Identification field
Data field
Checksum field
Sync field
Transfer end interrupt
g
enerated?
Transfer end interrupt
g
enerated?
Writing 1 to SS12
Transmitting 55H
Wakeup signal frame
Setting baud rate
Setting transfer data 00H
Setting transfer data 00H
Setting baud rate
Receiving data
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13.6.4 LIN reception
Of UART reception, UART3 supports LIN communication.
For LIN reception, channel 3 of unit 1 (SAU1) is used.
UART UART0 UART1 UART2 UART3
Support of LIN communication Not supported Not supported Not supported Supported
Target channel − − − Channel 3 of SAU1
Pins used − − − RxD3
− − − INTSR3
Interrupt
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error interrupt − − − INTSRE3
Error detection flag • Framing error detection flag (FEF13)
• Parity error detection flag (PEF13)
• Overrun error detection flag (OVF13)
Transfer data length 8 bits
Transfer rate Max. fMCK/6 [bps] (SDR13 [15:9] = 2 or more), Min. fCLK/(2 × 211 × 128) [bps]Note
Data phase Forward output (default: high level)
Reverse output (default: low level)
Parity bit The following selectable
• No parity bit (no parity check)
• Appending 0 parity (no parity check)
• Appending even parity
• Appending odd parity
Stop bit The following selectable
• Appending 1 bit
• Appending 2 bits
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
Remark f
MCK: Operation clock (MCK) frequency of target channel
fCLK: System clock frequency
Figure 13-87 outlines a reception operation of LIN.
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Figure 13-87. Reception Operation of LIN
LIN Bus
13-bit SBF
reception
SF
reception
ID
reception
Data
reception
Data
reception
Data
reception
Wakeup signal
frame
Sync break
field
Sync field Identification
field
Data filed Data filed Checksum
field
R
X
D3 (input)
Reception interrupt
(INTSR3)
Edge detection
(INTP0)
Capture
timer Disable Enable
Disable Enable
<1>
<2>
<3>
<4>
<5>
Here is the flow of signal processing.
<1> The wakeup signal is detected by detecting an interrupt edge (INTP0) on a pin. When the wakeup signal is
detected, enable reception of UART3 (RXE13 = 1) and wait for SBF reception.
<2> When the start bit of SBF is detected, reception is started and serial data is sequentially stored in the RXD3
register (= bits 7 to 0 of the serial data register 13 (SDR13)) at the set baud rate. When the stop bit is
detected, the reception end interrupt request (INTSR3) is generated. When data of low levels of 11 bits or
more is detected as SBF, it is judged that SBF reception has been correctly completed. If data of low levels of
less than 11 bits is detected as SBF, it is judged that an SBF reception error has occurred, and the system
returns to the SBF reception wait status.
<3> When SBF reception has been correctly completed, start channel 7 of the timer array unit and measure the
bit interval (pulse width) of the sync field (see 7.7.5 Operation as input signal high-/low-level width
measurement).
<4> Calculate a baud rate error from the bit interval of sync field (SF). Stop UART3 once and adjust (re-set) the
baud rate.
<5> The checksum field should be distinguished by software. In addition, processing to initialize UART3 after the
checksum field is received and to wait for reception of SBF should also be performed by software.
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Figure 13-88 shows the configuration of a port that manipulates reception of LIN.
The wakeup signal transmitted from the master of LIN is received by detecting an edge of an external interrupt
(INTP0). The length of the sync field transmitted from the master can be measured by using the external event
capture operation of the timer array unit (TAU) to calculate a baud-rate error.
By controlling switch of port input (ISC0/ISC1), the input source of port input (RxD3) for reception can be input to
the external interrupt pin (INTP0) and timer array unit (TAU).
Figure 13-88. Port Configuration for Manipulating Reception of LIN
RXD3 input
INTP0 input
Channel 7 input of TAU
P14/RxD3
P120/INTP0/
EXLVI
P145/TI07
Port input
switch control
(ISC0)
<ISC0>
0: Selects INTP0 (P120)
1: Selects RxD3 (P14)
Port mode
(PM14)
Output latch
(P14)
Port mode
(PM120)
Output latch
(P120)
Port input
switch control
(ISC1)
<ISC1>
0: Selects TI07 (P145)
1: Selects RxD3 (P14)
Selector Selector
Selector
Selector
Selector
Port mode
(PM145)
Output latch
(P145)
Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (See Figure 13-17.)
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The peripheral functions used for the LIN communication operation are as follows.
<Peripheral functions used>
• External interrupt (INTP0); Wakeup signal detection
Usage: To detect an edge of the wakeup signal and the start of communication
• Channel 7 of timer array unit (TAU); Baud rate error detection
Usage: To detect the length of the sync field (SF) and divide it by the number of bits in order to detect an error
(The interval of the edge input to RxD3 is measured in the capture mode.)
• Channels 2 and 3 (UART3) of serial array unit 1 (SAU1)
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Figure 13-89. Flowchart of LIN Reception
Starting LIN communication
Detecting low-level width
Detecting low-level width
Stopping operation
Detecting high-level width
End of LIN communication
Sync break field
Identification field
Data field
Checksum field
Sync field
SBF detected?
Writing 1 to ST13
Writing 1 to SS13
Wakeup signal frame
Setting TAU in capture
mode (to measure
low-level width)
Detecting low-level width
Receiving data
Wakeup detected?
Setting TAU in capture
mode (to measure
low-/high-level width)
Detecting low-level width
Setting UART reception mode
Calculating baud rate
Detecting high-level width
INTP0,
TAU
SAU
For
details,
See
Figure
13-84
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13.6.5 Calculating baud rate
(1) Baud rate calculation expression
The baud rate for UART (UART0, UART1, UART2, UART3) communication can be calculated by the following
expressions.
(Baud rate) = {Operation clock (MCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [bps]
Caution Setting SDRmn [15:9] = (0000000B, 0000001B) is prohibited.
Remarks 1. When UART is used, the value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn
register (0000010B to 1111111B) and therefore is 2 to 127.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
The operation clock (MCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial
mode register mn (SMRmn).
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Table 13-3. Selection of Operation Clock
SMRmn
Register
SPSm Register Operation Clock (MCK)Note 1
CKSmn PRS
m13
PRS
m12
PRS
m11
PRS
m10
PRS
m03
PRS
m02
PRS
m01
PRS
m00
fCLK = 20 MHz
X X X X 0 0 0 0 fCLK 20 MHz
X X X X 0 0 0 1 fCLK/2 10 MHz
X X X X 0 0 1 0 fCLK/22 5 MHz
X X X X 0 0 1 1 fCLK/23 2.5 MHz
X X X X 0 1 0 0 fCLK/24 1.25 MHz
X X X X 0 1 0 1 fCLK/25 625 kHz
X X X X 0 1 1 0 fCLK/26 313 kHz
X X X X 0 1 1 1 fCLK/27 156 kHz
X X X X 1 0 0 0 fCLK/28 78.1 kHz
X X X X 1 0 0 1 fCLK/29 39.1 kHz
X X X X 1 0 1 0 fCLK/210 19.5 kHz
X X X X 1 0 1 1 fCLK/211 9.77 kHz
0
X X X X 1 1 1 1 INTTM02 if m = 0,
INTTM03 if m = 1Note 2
0 0 0 0 X X X X fCLK 20 MHz
0 0 0 1 X X X X fCLK/2 10 MHz
0 0 1 0 X X X X fCLK/22 5 MHz
0 0 1 1 X X X X fCLK/23 2.5 MHz
0 1 0 0 X X X X fCLK/24 1.25 MHz
0 1 0 1 X X X X fCLK/25 625 kHz
0 1 1 0 X X X X fCLK/26 313 kHz
0 1 1 1 X X X X fCLK/27 156 kHz
1 0 0 0 X X X X fCLK/28 78.1 kHz
1 0 0 1 X X X X fCLK/29 39.1 kHz
1 0 1 0 X X X X fCLK/210 19.5 kHz
1 0 1 1 X X X X fCLK/211 9.77 kHz
1
1 1 1 1 X X X X INTTM02 if m = 0,
INTTM03 if m = 1Note 2
Other than above Setting prohibited
Notes 1. When changing the clock selected for fCLK (by changing the system clock control register (CKC)
value), do so after having stopped (STm = 000FH) the operation of the serial array unit (SAU).
When selecting INTTM02 and INTTM03 for the operation clock, also stop the timer array unit (TAU)
(TT0 = 00FFH).
2. SAU can be operated at a fixed division ratio of the subsystem clock, regardless of the fCLK
frequency (main system clock, subsystem clock), by operating the interval timer for which fSUB/4
has been selected as the count clock (setting TIS02 (if m = 0) or TIS03 (if m = 1) of the TIS0
register to 1) and selecting INTTM02 and INTTM03 by using the SPSm register in channels 2 and
3 of TAU. When changing fCLK, however, SAU and TAU must be stopped as described in Note 1
above.
Remarks 1. X: Don’t care
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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(2) Baud rate error during transmission
The baud rate error of UART (UART0, UART1, UART2, UART3) communication during transmission can be
calculated by the following expression. Make sure that the baud rate at the transmission side is within the
permissible baud rate range at the reception side.
(Baud rate error) = (Calculated baud rate value) ÷ (Target baud rate) × 100 − 100 [%]
Here is an example of setting a UART baud rate at fCLK = 20 MHz.
fCLK = 20 MHz UART Baud Rate
(Target Baud Rate) Operation Clock (MCK) SDRmn[15:9] Calculated Baud Rate Error from Target Baud Rate
300 bps fCLK/29 64 300.48 bps +0.16 %
600 bps fCLK/28 64 600.96 bps +0.16 %
1200 bps fCLK/27 64 1201.92 bps +0.16 %
2400 bps fCLK/26 64 2403.85 bps +0.16 %
4800 bps fCLK/25 64 4807.69 bps +0.16 %
9600 bps fCLK/24 64 9615.38 bps +0.16 %
19200 bps fCLK/23 64 19230.8 bps +0.16 %
31250 bps fCLK/23 39 31250.0 bps ±0.0 %
38400 bps fCLK/22 64 38461.5 bps +0.16 %
76800 bps fCLK/2 64 76923.1 bps +0.16 %
153600 bps fCLK 64 153846 bps +0.16 %
312500 bps fCLK 31 312500 bps ±0.0 %
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
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(3) Permissible baud rate range for reception
The permissible baud rate range for reception during UART (UART0, UART1, UART2, UART3) communication
can be calculated by the following expression. Make sure that the baud rate at the transmission side is within
the permissible baud rate range at the reception side.
2 × k × Nfr
(Maximum receivable baud rate) = 2 × k × Nfr − k + 2 × Brate
2 × k × (Nfr − 1)
(Minimum receivable baud rate) = 2 × k × Nfr − k − 2 × Brate
Brate: Calculated baud rate value at the reception side (See 13.6.5 (1) Baud rate calculation expression.)
k: SDRmn[15:9] + 1
Nfr: 1 data frame length [bits]
= (Start bit) + (Data length) + (Parity bit) + (Stop bit)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 1, 3)
Figure 13-90. Permissible Baud Rate Range for Reception (1 Data Frame Length = 11 Bits)
FL
1 data frame (11 × FL)
(11 × FL) min.
(11 × FL) max.
Data frame length
of SAU
Start
bit Bit 0 Bit 1 Bit 7 Parity
bit
Permissible minimum
data frame length
Permissible maximum
data frame length
Stop
bit
Start
bit Bit 0 Bit 1 Bit 7 Parity
bit
Latch
timing
Stop
bit
Start
bit Bit 0 Bit 1 Bit 7 Parity
bit
Stop
bit
As shown in Figure 13-90, the timing of latching receive data is determined by the division ratio set by bits 15
to 9 of the serial data register mn (SDRmn) after the start bit is detected. If the last data (stop bit) is received
before this latch timing, the data can be correctly received.
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13.6.6 Procedure for processing errors that occurred during UART (UART0, UART1, UART2, UART3)
communication
The procedure for processing errors that occurred during UART (UART0, UART1, UART2, UART3) communication
is described in Figures 13-91 and 13-92.
Figure 13-91. Processing Procedure in Case of Parity Error or Overrun Error
Software Manipulation Hardware Status Remark
Reads SDRmn register. The BFF0 = 0, and channel n is
enabled to receive data.
This is to prevent an overrun error if the
next reception is completed during error
processing.
Reads SSRmn register. Error type is identified and the read
value is used to clear error flag.
Writes SIRmn register.
Error flag is cleared. Only error generated at the point of
reading can be cleared, by writing the
value read from the SSRmn register to
the SIRmn register without modification.
Figure 13-92. Processing Procedure in Case of Framing Error
Software Manipulation Hardware Status Remark
Reads SDRmn register. The BFF = 0, and channel n is enabled
to receive data.
This is to prevent an overrun error if the
next reception is completed during error
processing.
Reads SSRmn register. Error type is identified and the read
value is used to clear error flag.
Writes SIRmn register. Error flag is cleared. Only error generated at the point of
reading can be cleared, by writing the
value read from the SSRmn register to
the SIRmn register without modification.
Sets STmn bit to 1. The SEmn = 0, and channel n stops
operating.
Synchronization with other party of
communication
Synchronization with the other party of
communication is re-established and
communication is resumed because it is
considered that a framing error has
occurred because the start bit has been
shifted.
Sets SSmn bit to 1. The SEmn = 1, and channel n is
enabled to operate.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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13.7 Operation of Simplified I2C (IIC10, IIC20) Communication
This is a clocked communication function to communicate with two or more devices by using two lines: serial clock
(SCL) and serial data (SDA). This communication function is designed to execute single communication with devices
such as EEPROM, flash memory, and A/D converter, and therefore, can be used only by the master and does not
have a wait detection function. Make sure by using software, as well as operating the control registers, that the AC
specifications of the start and stop conditions are observed.
[Data transmission/reception]
• Master transmission, master reception (only master function with a single master)
• ACK output functionNote and ACK detection function
• Data length of 8 bits
(When an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is
used for R/W control.)
• Manual generation of start condition and stop condition
[Interrupt function]
• Transfer end interrupt
[Error detection flag]
• Overrun error
• Parity error (ACK error)
* [Functions not supported by simplified I2C]
• Slave transmission, slave reception
• Arbitration loss detection function
• Wait detection function
Note An ACK is not output when the last data is being received by writing 0 to the SOEmn (SOEm register) bit
and stopping the output of serial communication data. See 13.7.3 (2) Processing flow for details.
Remarks 1. To use the full-function I2C bus, see CHAPTER 14 SERIAL INTERFACE IIC0.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
The channels supporting simplified I2C (IIC10, IIC20) are channel 2 of SAU0 and channel 0 of SAU1.
Unit Channel Used as CSI Used as UART Used as Simplified I2C
0 CSI00 −
1 CSI01
UART0
−
2 CSI10 UART1 IIC10
0
3 − −
0 CSI20 UART2 IIC20
1 − −
2 − −
1
3 −
UART3 (supporting LIN-bus)
−
Simplified I2C (IIC10, IIC20) performs the following four types of communication operations.
• Address field transmission (See 13.7.1.)
• Data transmission (See 13.7.2.)
• Data reception (See 13.7.3.)
• Stop condition generation (See 13.7.4.)
<R>
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13.7.1 Address field transmission
Address field transmission is a transmission operation that first executes in I2C communication to identify the target
for transfer (slave). After a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are
transmitted in one frame.
Simplified I2C IIC10 IIC20
Target channel Channel 2 of SAU0 Channel 0 of SAU1
Pins used SCL10, SDA10Note SCL20, SDA20Note
INTIIC10 INTIIC20 Interrupt
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag Parity error detection flag (PEFmn)
Transfer data length 8 bits (transmitted with specifying the higher 7 bits as address and the least significant bit as R/W
control)
Transfer rate Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock (MCK) frequency of target channel
However, the following condition must be satisfied in each mode of I2C.
• Max. 400 kHz (first mode)
• Max. 100 kHz (standard mode)
Data level Forward output (default: high level)
Parity bit No parity bit
Stop bit Appending 1 bit (for ACK reception timing)
Data direction MSB first
Note To perform communication via simplified I2C, set the N-ch open-drain output (VDD tolerance) mode (POM03,
POM143 = 1) for the port output mode registers (POM0, POM14) (see 4.3 Registers Controlling Port
Function for details). When communicating with an external device with a different potential, set the N-ch
open-drain output (VDD tolerance) mode (POM04, POM142 = 1) also for the clock input/output pins (SCL10,
SCL20) (see 4.4.4 Connecting to external device with different potential (2.5 V, 3 V) for details).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
<R>
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(1) Register setting
Figure 13-93. Example of Contents of Registers for Address Field Transmission of Simplified I2C (IIC10, IIC20)
(a) Serial output register m (SOm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
CKOm2
0/1
CKOm1
×
CKOm0
0/1
0
0
0
0
1
SOm2
0/1
SOm1
×
SOm0
0/1
Start condition is generated by manipulating the SOmn bit.
(b) Serial output enable register m (SOEm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm2
0/1
SOEm1
×
SOEm0
0/1
SOEmn = 0 until the start condition is generated, and SOEmn =
1 after generation.
(c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
×
SSm2
0/1
SSm1
×
SSm0
0/1
(d) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1
CCSmn
0
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
1
MDmn1
0
MDmn0
0
Interrupt sources of channel n
0: Transfer end interrupt
(e) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
1
RXEmn
0
DAPmn
0
CKPmn
0
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0
0
SLCmn1
0
SLCmn0
1
0
DLSmn2
1
DLSmn1
1
DLSmn0
1
Setting of parity bit
00B: No parity
Setting of stop bit
01B: Appending 1 bit (ACK)
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting
0
Transmit data setting (address + R/W)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
: Setting is fixed in the IIC mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOr
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(2) Operation procedure
Figure 13-94. Initial Setting Procedure for Address Field Transmission
Caution After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks
have elapsed.
Starting initial setting
Setting PER0 register
Setting SPSm register
Setting SMRmn register
Setting SCRmn register
Setting SDRmn register
Setting SOm register
Setting port
Setting SOm register
Starting communication
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock .
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate.
Manipulate the SOmn and CKOmn bits
and set an initial output level.
Enable data output, clock output, and the N-ch
open-drain output (VDD tolerance) mode of the
target channel by setting a port register, a port
mode register, and a port output mode register.
Clear the SOmn bit to 0 to generate the
start condition.
Set address and R/W to the SIOr register
(bits 7 to 0 of the SDRmn register) and
start communication.
Writing to SSm register Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Setting SOm register Clear the CKOmn bit to 0 to lower the
clock output level.
Changing setting of SOEm register Set the SOEmn bit to 1 and enable data
output of the target channel.
Secure a wait time so that the specifications of
I2C on the slave side are satisfied.
Wait
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(3) Processing flow
Figure 13-95. Timing Chart of Address Field Transmission
D7 D6 D5 D4 D3 D2 D1 D0
R/W
D7 D6
SSmn
SEmn
SOEmn
SDRmn
SCLr output
SDAr output
SDAr input
Shift
register mn
INTIICr
TSFmn
D5 D4 D3 D2 D1 D0
ACK
Address
Shift operation
Address field transmission
SOmn bit manipulation
CKOmn
bit manipulation
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
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Figure 13-96. Flowchart of Address Field Transmission
Starting IIC communication
Writing 0 to SOmn bit
Address field
transmission completed
Perform initial setting
when SEmn = 0.
SMRmn, SCRmn: Setting communication
SPSm, SDRmn[15:9]: Setting transfer rate
Transfer end interrupt
g
enerated?
No
Yes
Writing address and R/W
data to SIOr (SDRmn[7:0])
Writing 1 to SSmn bit
Parity error (ACK error) flag
PEFmn = 1 ?
No
Yes
ACK reception error
To data transmission flow
and data reception flow
Writing 1 to SOEmn bit
Writing 0 to CKOmn bit
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13.7.2 Data transmission
Data transmission is an operation to transmit data to the target for transfer (slave) after transmission of an address
field. After all data are transmitted to the slave, a stop condition is generated and the bus is released.
Simplified I2C IIC10 IIC20
Target channel Channel 2 of SAU0 Channel 0 of SAU1
Pins used SCL10, SDA10Note SCL20, SDA20Note
INTIIC10 INTIIC20 Interrupt
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag Parity error detection flag (PEFmn)
Transfer data length 8 bits
Transfer rate Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock (MCK) frequency of target channel
However, the following condition must be satisfied in each mode of I2C.
• Max. 400 kHz (first mode)
• Max. 100 kHz (standard mode)
Data level Forward output (default: high level)
Parity bit No parity bit
Stop bit Appending 1 bit (for ACK reception timing)
Data direction MSB first
Note To perform communication via simplified I2C, set the N-ch open-drain output (VDD tolerance) mode (POM03,
POM143 = 1) for the port output mode registers (POM0, POM14) (see 4.3 Registers Controlling Port
Function for details). When communicating with an external device with a different potential, set the N-ch
open-drain output (VDD tolerance) mode (POM04, POM142 = 1) also for the clock input/output pins (SCL10,
SCL20) (see 4.4.4 Connecting to external device with different potential (2.5 V, 3 V) for details).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
<R>
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(1) Register setting
Figure 13-97. Example of Contents of Registers for Data Transmission of Simplified I2C (IIC10, IIC20)
(a) Serial output register m (SOm) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
CKOm2
0/1Note
CKOm1
×
CKOm0
0/1Note
0
0
0
0
1
SOm2
0/1Note
SOm1
×
SOm0
0/1Note
(b) Serial output enable register m (SOEm) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm2
0/1
SOEm1
×
SOEm0
0/1
(c) Serial channel start register m (SSm) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
×
SSm2
0/1
SSm1
×
SSm0
0/1
(d) Serial mode register mn (SMRmn) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1
CCSmn
0
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
1
MDmn1
0
MDmn0
0
(e) Serial communication operation setting register mn (SCRmn) … Do not manipulate the bits of this
register, except the TXEmn and
RXEmn bits, during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
1
RXEmn
0
DAPmn
0
CKPmn
0
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0
0
SLCmn1
0
SLCmn0
1
0
DLSmn2
1
DLSmn1
1
DLSmn0
1
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting
0
Transmit data setting
Note The value varies depending on the communication data during communication operation.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
: Setting is fixed in the IIC mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOr
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(2) Processing flow
Figure 13-98. Timing Chart of Data Transmission
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6
SSmn
SEmn
SOEmn
SDRmn
SCLr output
SDAr output
SDAr input
Shift
register mn
INTIICr
TSFmn
D5 D4 D3 D2 D1 D0
ACK
Shift operation
“L”
“H”
“H”
Transmit data 1
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
Figure 13-99. Flowchart of Data Transmission
Starting data transmission
Data transmission
completed
Transfer end interrupt
g
enerated?
No
Yes
Writing data to SIOr
(SDRmn[7:0])
No
Yes
ACK reception error
S
top con
di
t
i
on generat
i
on
Data transfer completed?
Yes
No
Address field
transmission completed
Parity error (ACK error) flag
PEFmn = 1 ?
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13.7.3 Data reception
Data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field.
After all data are received to the slave, a stop condition is generated and the bus is released.
Simplified I2C IIC10 IIC20
Target channel Channel 2 of SAU0 Channel 0 of SAU1
Pins used SCL10, SDA10Note SCL20, SDA20Note
INTIIC10 INTIIC20 Interrupt
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 8 bits
Transfer rate Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock (MCK) frequency of target channel
However, the following condition must be satisfied in each mode of I2C.
• Max. 400 kHz (first mode)
• Max. 100 kHz (standard mode)
Data level Forward output (default: high level)
Parity bit No parity bit
Stop bit Appending 1 bit (ACK transmission)
Data direction MSB first
Note To perform communication via simplified I2C, set the N-ch open-drain output (VDD tolerance) mode (POM03,
POM143 = 1) for the port output mode registers (POM0, POM14) (see 4.3 Registers Controlling Port
Function for details). When communicating with an external device with a different potential, set the N-ch
open-drain output (VDD tolerance) mode (POM04, POM142 = 1) also for the clock input/output pins (SCL10,
SCL20) (see 4.4.4 Connecting to external device with different potential (2.5 V, 3 V) for details).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
<R>
<R>
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(1) Register setting
Figure 13-100. Example of Contents of Registers for Data Reception of Simplified I2C (IIC10, IIC20)
(a) Serial output register m (SOm) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
CKOm2
0/1Note
CKOm1
×
CKOm0
0/1Note
0
0
0
0
1
SOm2
0/1Note
SOm1
×
SOm0
0/1Note
(b) Serial output enable register m (SOEm) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
0
SOEm2
0/1
SOEm1
×
SOEm0
0/1
(c) Serial channel start register m (SSm) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
×
SSm2
0/1
SSm1
×
SSm0
0/1
(d) Serial mode register mn (SMRmn) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1
CCSmn
0
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
1
MDmn1
0
MDmn0
0
(e) Serial communication operation setting register mn (SCRmn) … Do not manipulate the bits of this
register, except the TXEmn and
RXEmn bits, during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
0
RXEmn
1
DAPmn
0
CKPmn
0
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0
0
SLCmn1
0
SLCmn0
1
0
DLSmn2
1
DLSmn1
1
DLSmn0
1
(f) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting
0
Dummy transmit data setting (FFH)
Note The value varies depending on the communication data during communication operation.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
: Setting is fixed in the IIC mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOr
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(2) Processing flow
Figure 13-101. Timing Chart of Data Reception
(a) When starting data reception
D7 D6 D5 D4 D3 D2 D1 D0
SSmn
SEmn
SOEmn
SDRmn
SCLr output
SDAr output
SDAr input
Shift
register mn
INTIICr
TSFmn
ACK
STmn
TXEmn = 0 / RXEmn = 1
TXEmn,
RXEmn TXEmn = 1 / RXEmn = 0
Shift operation
“H”
Dummy data (FFH)
Receive data
(b) When receiving last data
D7 D6 D5 D4 D3 D2 D1 D0D2 D1 D0
STmn
SEmn
SOEmn
SDRmn
SCLr output
SDAr output
SDAr input
Shift
register mn
INTIICr
TSFmn
Receive data
Receive data
Output is enabled by serial
communication operation
Output is stopped by serial communication operation
NACKACK
TXEmn = 0 / RXEmn = 1
TXEmn,
RXEmn
Stop condition
Reception of last byte
IIC operation stop
SOmn bit
manipulation
CKOmn bit
manipulation
SOmn bit
manipulation
Shift operation
Dummy data (FFH)
Shift operation
Dummy data (FFH)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
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Figure 13-102. Flowchart of Data Reception
Caution ACK is not output when the last data is received (NACK). Communication is then completed
by setting “1” to the STmn bit to stop operation and generating a stop condition.
Starting data reception
Data reception
completed
Transfer end interrupt
g
enerated? No
Yes
Writing dummy data (FFH)
to SIOr (SDRmn[7:0])
S
top con
di
t
i
on generat
i
on
Yes
No
Reading SIOr (SDRmn[7:0])
Address field transmission completed
Writing 1 to STmn bit
Writing 0 to TXEmn bit, and 1 to RXEmn bit
Writing 1 to SSmn bit
Last byte received? Yes
Writing 0 to SOEmn bit
(Stopping output by serial
communication operation)
No
Data transfer completed?
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13.7.4 Stop condition generation
After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is
released.
(1) Processing flow
Figure 13-103. Timing Chart of Stop Condition Generation
Stop condition
STmn
SEmn
SOEmn
SCLr output
SDAr output
Operation
stop
SOmn bit
manipulation
CKOmn bit
manipulation
SOmn bit
manipulation
Note
Note During the receive operation, the SOEmn bit is set to 0 before receiving the last data.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
Figure 13-104. Flowchart of Stop Condition Generation
Starting generation of stop condition.
End of IIC communication
Writing 1 to STmn bit to clear
SEmn to 0.
Writing 0 to SOEmn bit
Writing 1 to SOmn bit
Writing 1 to CKOmn bit
Writing 0 to SOmn bit
Completion of data
transmission/data reception
Wait Secure a wait time so that the specifications of
I2C on the slave side are satisfied.
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13.7.5 Calculating transfer rate
The transfer rate for simplified I2C (IIC10, IIC20) communication can be calculated by the following expressions.
(Transfer rate) = {Operation clock (MCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2
Caution Setting SDRmn[15:9] = 0000000B is prohibited. Setting SDRmn[15:9] = 0000001B or more.
Remarks 1. The value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn register (0000001B to
1111111B) and therefore is 1 to 127.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
The operation clock (MCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial
mode register mn (SMRmn).
<R>
<R>
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Table 13-4. Selection of Operation Clock
SMRmn
Register
SPSm Register Operation Clock (MCK)Note 1
CKSmn PRS
m13
PRS
m12
PRS
m11
PRS
m10
PRS
m03
PRS
m02
PRS
m01
PRS
m00
fCLK = 20 MHz
X X X X 0 0 0 0 fCLK 20 MHz
X X X X 0 0 0 1 fCLK/2 10 MHz
X X X X 0 0 1 0 fCLK/22 5 MHz
X X X X 0 0 1 1 fCLK/23 2.5 MHz
X X X X 0 1 0 0 fCLK/24 1.25 MHz
X X X X 0 1 0 1 fCLK/25 625 kHz
X X X X 0 1 1 0 fCLK/26 313 kHz
X X X X 0 1 1 1 fCLK/27 156 kHz
X X X X 1 0 0 0 fCLK/28 78.1 kHz
X X X X 1 0 0 1 fCLK/29 39.1 kHz
X X X X 1 0 1 0 fCLK/210 19.5 kHz
X X X X 1 0 1 1 fCLK/211 9.77 kHz
0
X X X X 1 1 1 1 INTTM02 if m = 0,
INTTM03 if m = 1Note 2
0 0 0 0 X X X X fCLK 20 MHz
0 0 0 1 X X X X fCLK/2 10 MHz
0 0 1 0 X X X X fCLK/22 5 MHz
0 0 1 1 X X X X fCLK/23 2.5 MHz
0 1 0 0 X X X X fCLK/24 1.25 MHz
0 1 0 1 X X X X fCLK/25 625 kHz
0 1 1 0 X X X X fCLK/26 313 kHz
0 1 1 1 X X X X fCLK/27 156 kHz
1 0 0 0 X X X X fCLK/28 78.1 kHz
1 0 0 1 X X X X fCLK/29 39.1 kHz
1 0 1 0 X X X X fCLK/210 19.5 kHz
1 0 1 1 X X X X fCLK/211 9.77 kHz
1
1 1 1 1 X X X X INTTM02 if m = 0,
INTTM03 if m = 1Note 2
Other than above Setting prohibited
Notes 1. When changing the clock selected for fCLK (by changing the system clock control register (CKC)
value), do so after having stopped (STm = 000FH) the operation of the serial array unit (SAU).
When selecting INTTM02 and INTTM03 for the operation clock, also stop the timer array unit (TAU)
(TT0 = 00FFH).
2. SAU can be operated at a fixed division ratio of the subsystem clock, regardless of the fCLK
frequency (main system clock, subsystem clock), by operating the interval timer for which fSUB/4
has been selected as the count clock (setting TIS02 (if m = 0) or TIS03 (if m = 1) of the TIS0
register to 1) and selecting INTTM02 and INTTM03 by using the SPSm register in channels 2 and
3 of TAU. When changing fCLK, however, SAU and TAU must be stopped as described in Note 1
above.
Remarks 1. X: Don’t care
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
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Here is an example of setting an IIC transfer rate where MCK = fCLK = 20 MHz.
fCLK = 20 MHz IIC Transfer Mode
(Desired Transfer Rate) Operation Clock (MCK) SDRmn[15:9] Calculated
Transfer Rate
Error from Desired Transfer
Rate
100 kHz fCLK 99 100 kHz 0.0%
400 kHz fCLK 24 400 kHz 0.0%
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13.7.6 Procedure for processing errors that occurred during simplified I2C (IIC10, IIC20) communication
The procedure for processing errors that occurred during simplified I2C (IIC10, IIC20) communication is described
in Figures 13-105 and 13-106.
Figure 13-105. Processing Procedure in Case of Parity Error or Overrun Error
Software Manipulation Hardware Status Remark
Reads SDRmn register. BFF = 0, and channel n is enabled to
receive data.
This is to prevent an overrun error if
the next reception is completed
during error processing.
Reads SSRmn register. Error type is identified and the read
value is used to clear error flag.
Writes SIRmn register. Error flag is cleared. Only error generated at the point of
reading can be cleared, by writing
the value read from the SSRmn
register to the SIRmn register
without modification.
Figure 13-106. Processing Procedure in Case of Parity Error (ACK error) in Simplified I2C Mode
Software Manipulation Hardware Status Remark
Reads SDRmn register. BFF = 0, and channel n is enabled to
receive data.
This is to prevent an overrun error if
the next reception is completed
during error processing.
Reads SSRmn register. Error type is identified and the read
value is used to clear error flag.
Writes SIRmn register. Error flag is cleared. Only error generated at the point of
reading can be cleared, by writing
the value read from the SSRmn
register to the SIRmn register
without modification.
Sets STmn bit to 1. SEmn = 0, and channel n stops
operation.
Creates stop condition.
Creates start condition.
Slave is not ready for reception
because ACK is not returned.
Therefore, a stop condition is
created, the bus is released, and
communication is started again from
the start condition. Or, a restart
condition is generated and
transmission can be redone from
address transmission.
Sets SSmn bit to 1. SEmn = 1, and channel n is enabled to
operate.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 02, 10
<R>
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13.8 Relationship Between Register Settings and Pins
Tables 13-5 to 13-12 show the relationship between register settings and pins for each channel of serial array units
0 and 1.
Table 13-5. Relationship Between Register Settings and Pins
(Channel 0 of Unit 0: CSI00, UART0 Transmission)
Pin Function SE
00
Note 1
MD
002
MD
001
SOE
00
SO
00
CKO
00
TXE
00
RXE
00
PM
10
P10 PM
11
Note 2
P11
Note 2
PM
12
P12 Operation Mode
SCK00/
EX24/P10
SI00/EX25/
RxD0/P11
Note 2
SO00/EX26/
TxD0/P12
0 0 EX25/P11 0
0 1
0 1 1 0 0 ×
Note 3
×
Note 3
×
Note 3
×
Note 3
×
Note 3
×
Note 3
Operation stop
mode
EX24/P10
EX25/P11/
RxD0
EX26/P12
0 1 1 0 1 1 × 1 × ×
Note 3
×
Note 3
Slave CSI00
reception
SCK00
(input)
SI00 P12
1 0/1
Note 4
1 1 0 1
× ×
Note 3
×
Note 3
0 1 Slave CSI00
transmission
SCK00
(input)
P11 SO00
1 0/1
Note 4
1 1 1 1
× 1 × 0 1 Slave CSI00
transmission/
reception
SCK00
(input)
SI00 SO00
0 1 0/1
Note 4
0 1 0 1 1
× × Note
3
×
Note 3
Master CSI00
reception
SCK00
(output)
SI00 P12
1 0/1
Note 4
0/1
Note 4
1 0 0 1
×
Note 3
×
Note 3
0 1 Master CSI00
transmission
SCK00
(output)
P11 SO00
0 0
1 0/1
Note 4
0/1
Note 4
1 1 0 1 1
× 0 1 Master CSI00
transmission/
reception
SCK00
(output)
SI00 SO00
1
0 1 1 0/1
Note 4
1 1 0
×
Note 3
×
Note 3
×
Note 3
×
Note 3
0 1 UART0
transmissionNote 5
P10 P11/RxD0 TxD0
Notes 1. The SE0 register is a read-only status register which is set using the SS0 and ST0 registers.
2. When channel 1 of unit 0 is set to UART0 reception, this pin becomes an RxD0 function pin (refer to Table
13-6). In this case, operation stop mode or UART0 transmission must be selected for channel 0 of unit 0.
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 13.3 (12) Serial output
register m (SOm).
5. When using UART0 transmission and reception in a pair, set channel 1 of unit 0 to UART0 reception (refer
to Table 13-6).
Remark X: Don’t care
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Table 13-6. Relationship Between Register Settings and Pins (Channel 1 of Unit 0: CSI01, UART0 Reception)
Pin Function SE
01
Note 1
MD
012
MD
011
SOE
01
SO01 CKO
01
TXE
01
RXE
01
PM
43
P43 PM44 P44 PM
45
P45 PM
11
Note 2
P11
Note 2
Operation
Mode SCK01/
P43
SI01/P44 SO01/
P45
SI00/EX25/
RxD0/
P11Note 2
0 0 0
0 1
0 1 1 0 0
×
Note 3
×
Note 3
×
Note 3
×
Note 3
×
Note 3
×
Note 3
×
Note 3
×
Note 3
Operation
stop
mode
P43 P44 P45 SI00/EX25/
P11
0 1 1 0 1 1 × 1 × ×
Note 3
×
Note 3
×
Note 3
×
Note 3
Slave
CSI01
reception
SCK01
(input)
SI01 P45 SI00/EX25/
P11
1 0/1
Note 4
1 1 0 1 × ×
Note 3
×
Note 3
0 1 ×
Note 3
×
Note 3
Slave
CSI01
transmission
SCK01
(input)
P44 SO01 SI00/EX25/
P11
1 0/1
Note 4
1 1 1 1 × 1 × 0 1 ×
Note 3
×
Note 3
Slave
CSI01
transmission
/reception
SCK01
(input)
SI01 SO01 SI00/EX25/
P11
0 1 0/1
Note 4
0 1 0 1 1 × ×
Note 3
×
Note 3
×
Note 3
×
Note 3
Master
CSI01
reception
SCK01
(output)
SI01 P45 SI00/EX25/
P11
1 0/1
Note 4
0/1
Note 4
1 0 0 1 ×
Note 3
×
Note 3
0 1 ×
Note 3
×
Note 3
Master
CSI01
transmission
SCK01
(output)
P44 SO01 SI00/EX25/
P11
0 0
1 0/1
Note 4
0/1
Note 4
1 1 0 1 1 × 0 1 ×
Note 3
×
Note 3
Master
CSI01
transmission
/reception
SCK01
(output)
SI01 SO01 SI00/EX25/
P11
1
0 1 0 1 1 0 1 ×
Note 3
×
Note 3
×
Note 3
×
Note 3
×
Note 3
×
Note 3
1 × UART0
reception
Notes 5, 6
P43 P44 P45 RxD0
Notes 1. The SE0 register is a read-only status register which is set using the SS0 and ST0 registers.
2. When channel 1 of unit 0 is set to UART0 reception, this pin becomes an RxD0 function pin. In this case,
set channel 0 of unit 0 to operation stop mode or UART0 transmission (refer to Table 13-5).
When channel 0 of unit 0 is set to CSI00, this pin cannot be used as an RxD0 function pin. In this case, set
channel 1 of unit 0 to operation stop mode or CSI01.
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 13.3 (12) Serial output
register m (SOm).
5. When using UART0 transmission and reception in a pair, set channel 0 of unit 0 to UART0 transmission
(refer to Table 13-5).
6. The SMR00 register of channel 0 of unit 0 must also be set during UART0 reception. For details, refer to
13.6.2 (1) Register setting.
Remark X: Don’t care
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Table 13-7. Relationship Between Register Settings and Pins
(Channel 2 of Unit 0: CSI10, UART1 Transmission, IIC10)
Pin Function SE
02
Note 1
MD
022
MD
021
SOE
02
SO
02
CKO
02
TXE
02
RXE
02
PM
04
P04 PM03
Note 2
P03
Note 2
PM02 P02 Operation Mode
SCK10/
SCL10/P04
SI10/SDA10/
RxD1/P03
Note 2
SO10/
TxD1/P02
0 0 P03
0 1 P03/RxD1
0
1 0
0 1 1 0 0 ×
Note 3
×
Note 3
×
Note 3
×
Note 3
×
Note 3
×
Note 3
Operation stop
mode
P04
P03
P02
0 1 1 0 1 1 × 1 × ×
Note 3
×
Note 3
Slave CSI10
reception
SCK10
(input)
SI10 P02
1 0/1
Note 4
1 1 0 1 × ×
Note 3
×
Note 3
0 1 Slave CSI10
transmission
SCK10
(input)
P03 SO10
1 0/1
Note 4
1 1 1 1 × 1 × 0 1
Slave CSI10
transmission /reception
SCK10
(input)
SI10 SO10
0 1 0/1
Note 4
0 1 0 1 1 × ×
Note 3
×
Note 3
Master CSI10
reception
SCK10
(output)
SI10 P02
1 0/1
Note 4
0/1
Note 4
1 0 0 1 ×
Note 3
×
Note 3
0 1 Master CSI10
transmission
SCK10
(output)
P03 SO10
0 0
1 0/1
Note 4
0/1
Note 4
1 1 0 1 1 × 0 1
Master CSI10
transmission /reception
SCK10
(output)
SI10 SO10
1
0 1 1 0/1
Note 4
1 1 0 ×
Note 3
×
Note 3
×
Note 3
×
Note 3
0 1 UART1
transmissionNote 5
P04 P03/RxD1 TxD1
0 0
1 0
0 0 0/1
Note 6
0/1
Note 6
0 1
0 1 0 1 ×
Note 3
×
Note 3
IIC10
start condition
SCL10 SDA10 P02
1 0/1
Note 4
0/1
Note 4
1 0 0 1 0 1 ×
Note 3
×
Note 3
IIC10 address field
transmission
SCL10 SDA10 P02
1 0/1
Note 4
0/1
Note 4
1 0 0 1 0 1 ×
Note 3
×
Note 3
IIC10 data
transmission
SCL10 SDA10 P02
1
1 0/1
Note 4
0/1
Note 4
0 1 0 1 0 1 ×
Note 3
×
Note 3
IIC10 data
reception
SCL10 SDA10 P02
0 0
1 0
0
1 0
0 0/1
Note 7
0/1
Note 7
0 1
0 1 0 1 ×
Note 3
×
Note 3
IIC10
stop condition
SCL10 SDA10 P02
Notes 1. The SE0 register is a read-only status register which is set using the SS0 and ST0 registers.
2. When channel 3 of unit 0 is set to UART1 reception, this pin becomes an RxD1 function pin (refer to Table
13-8). In this case, operation stop mode or UART1 transmission must be selected for channel 2 of unit 0.
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 13.3 (12) Serial output
register m (SOm).
5. When using UART1 transmission and reception in a pair, set channel 3 of unit 0 to UART1 reception (refer
to Table 13-8).
6. Set the CKO02 bit to 1 before a start condition is generated. Clear the SO02 bit from 1 to 0 when the start
condition is generated.
7. Set the CKO02 bit to 1 before a stop condition is generated. Clear the SO02 bit from 0 to 1 when the stop
condition is generated.
Remark X: Don’t care
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Table 13-8. Relationship Between Register Settings and Pins (Channel 3 of Unit 0: UART1 Reception)
Pin Function
SE03Note 1 MD032 MD031 TXE03 RXE03
PM03Note 2 P03Note 2 Operation
Mode SI10/SDA10/RxD1/P03
Note 2
0 0 1 0 0
×Note 3 ×Note 3 Operation
stop mode
SI10/SDA10/P03Note 2
1 0 1 0 1 1 × UART1
reception
Notes 4, 5
RxD1
Notes 1. The SE0 register is a read-only status register which is set using the SS0 and ST0 registers.
2. When channel 3 of unit 0 is set to UART1 reception, this pin becomes an RxD1 function pin. In this case,
set channel 2 of unit 0 to operation stop mode or UART1 transmission (refer to Table 13-7).
When channel 2 of unit 0 is set to CSI10 or IIC10, this pin cannot be used as an RxD1 function pin. In this
case, set channel 3 of unit 0 to operation stop mode.
3. This pin can be set as a port function pin.
4. When using UART1 transmission and reception in a pair, set channel 2 of unit 0 to UART1 transmission
(refer to Table 13-7).
5. The SMR02 register of channel 2 of unit 0 must also be set during UART1 reception. For details, refer to
13.6.2 (1) Register setting.
Remark X: Don’t care
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User’s Manual U17894EJ9V0UD 527
Table 13-9. Relationship Between Register Settings and Pins
(Channel 0 of Unit 1: CSI20, UART2 Transmission, IIC20)
Pin Function SE
10
Note 1
MD
102
MD
101
SOE
10
SO
10
CKO
10
TXE
10
RXE
10
PM
142
P142 PM
143
Note 2
P143
Note 2
PM
144
P144 Operation Mode
SCK20/
SCL20/P142
SI20/SDA20/
RxD2/P143
Note 2
SO20/
TxD2/P144
0 0 P143
0 1 P143/RxD2
0
1 0
0 1 1 0 0 ×
Note 3
×
Note 3
×
Note 3
×
Note 3
×
Note 3
×
Note 3
Operation stop
mode
P142
P143
P144
0 1 1 0 1 1 × 1 × ×
Note 3
×
Note 3
Slave CSI20
reception
SCK20
(input)
SI20 P144
1 0/1
Note 4
1 1 0 1 × ×
Note 3
×
Note 3
0 1 Slave CSI20
transmission
SCK20
(input)
P143 SO20
1 0/1
Note 4
1 1 1 1 × 1 × 0 1
Slave CSI20
transmission/reception
SCK20
(input)
SI20 SO20
0 1 0/1
Note 4
0 1 0 1 1 × ×
Note 3
×
Note 3
Master CSI20
reception
SCK20
(output)
SI20 P144
1 0/1
Note 4
0/1
Note 4
1 0 0 1 ×
Note 3
×
Note 3
0 1 Master CSI20
transmission
SCK20
(output)
P143 SO20
0 0
1 0/1
Note 4
0/1
Note 4
1 1 0 1 1 × 0 1
Master CSI20
transmission/reception
SCK20
(output)
SI20 SO20
1
0 1 1 0/1
Note 4
1 1 0 ×
Note 3
×
Note 3
×
Note 3
×
Note 3
0 1 UART2
transmission
Note 5
P142 P143/RxD2 TxD2
0 0
1 0
0 0 0/1
Note 6
0/1
Note 6
0 1
0 1 0 1 ×
Note 3
×
Note 3
IIC20
start condition
SCL20 SDA20 P144
1 0/1
Note 4
0/1
Note 4
1 0 0 1 0 1 ×
Note 3
×
Note 3
IIC20 address field
transmission
SCL20 SDA20 P144
1 0/1
Note 4
0/1
Note 4
1 0 0 1 0 1 ×
Note 3
×
Note 3
IIC20 data
transmission
SCL20 SDA20 P144
1
1 0/1
Note 4
0/1
Note 4
0 1 0 1 0 1 ×
Note 3
×
Note 3
IIC20 data
reception
SCL20 SDA20 P144
0 0
1 0
0
1 0
0 0/1
Note 7
0/1
Note 7
0 1
0 1 0 1 ×
Note 3
×
Note 3
IIC20
stop condition
SCL20 SDA20 P144
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
2. When channel 1 of unit 1 is set to UART2 reception, this pin becomes an RxD2 function pin (refer to Table
13-10). In this case, operation stop mode or UART2 transmission must be selected for channel 0 of unit 1.
3. This pin can be set as a port function pin.
4. This is 0 or 1, depending on the communication operation. For details, refer to 13.3 (12) Serial output
register m (SOm).
5. When using UART2 transmission and reception in a pair, set channel 1 of unit 1 to UART2 reception (refer
to Table 13-10).
6. Set the CKO10 bit to 1 before a start condition is generated. Clear the SO10 bit from 1 to 0 when the start
condition is generated.
7. Set the CKO10 bit to 1 before a stop condition is generated. Clear the SO10 bit from 0 to 1 when the stop
condition is generated.
Remark X: Don’t care
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Table 13-10. Relationship Between Register Settings and Pins (Channel 1 of Unit 1: UART2 Reception)
Pin Function
SE11Note 1 MD112 MD111 TXE11 RXE11
PM143Note 2 P143Note 2 Operation
Mode SI20/SDA20/RxD2/P143Note 2
0 0 1 0 0
×Note 3 ×Note 3 Operation
stop mode
SI20/SDA20/P143
1 0 1 0 1 1 × UART2
reception
Notes 4, 5
RxD2
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
2. When channel 1 of unit 1 is set to UART2 reception, this pin becomes an RxD2 function pin. In this case,
set channel 0 of unit 1 to operation stop mode or UART2 transmission (refer to Table 13-9).
When channel 0 of unit 1 is set to CSI20 or IIC20, this pin cannot be used as an RxD2 function pin. In this
case, set channel 1 of unit 1 to operation stop mode.
3. This pin can be set as a port function pin.
4. When using UART2 transmission and reception in a pair, set channel 0 of unit 1 to UART2 transmission
(refer to Table 13-9).
5. The SMR10 register of channel 0 of unit 1 must also be set during UART2 reception. For details, refer to
13.6.2 (1) Register setting.
Remark X: Don’t care
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User’s Manual U17894EJ9V0UD 529
Table 13-11. Relationship Between Register Settings and Pins (Channel 2 of Unit 1: UART3 Transmission)
Pin Function
SE12 Note
1
MD122 MD121 SOE12 SO12 TXE12 RXE12 PM13 P13 Operation
Mode EX27/TxD3/P13
0 0 1 0 1 0 0 ×
Note 2
×
Note 2
Operation
stop mode
EX27/P13
1 0 1 1
0/1Note 3 1 0 0 1 UART3
transmission
Note 4
TxD3
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
2. This pin can be set as a port function pin.
3. This is 0 or 1, depending on the communication operation. For details, refer to 13.3 (12) Serial output
register m (SOm).
4. When using UART3 transmission and reception in a pair, set channel 3 of unit 1 to UART3 reception (refer
to Table 13-12).
Remark X: Don’t care
Table 13-12. Relationship Between Register Settings and Pins (Channel 3 of Unit 1: UART3 Reception)
Pin Function
SE13Note 1 MD132 MD131 TXE13 RXE13 PM14 P14 Operation
Mode EX28/RxD3/P14
0 0 1 0 0
×Note 2 ×Note 2 Operation
stop
mode
EX28/P14
1 0 1 0 1 1 × UART3
reception
Notes 3, 4
RxD3
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
2. This pin can be set as a port function pin.
3. When using UART3 transmission and reception in a pair, set channel 2 of unit 1 to UART3 transmission
(refer to Table 13-11).
4. The SMR12 register of channel 2 of unit 1 must also be set during UART3 reception. For details, refer to
13.6.2 (1) Register setting.
Remark X: Don’t care
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CHAPTER 14 SERIAL INTERFACE IIC0
14.1 Functions of Serial Interface IIC0
Serial interface IIC0 has the following two modes.
(1) Operation stop mode
This mode is used when serial transfers are not performed. It can therefore be used to reduce power
consumption.
(2) I2C bus mode (multimaster supported)
This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCL0) line and a
serial data bus (SDA0) line.
This mode complies with the I2C bus format and the master device can generated “start condition”, “address”,
“transfer direction specification”, “data”, and “stop condition” data to the slave device, via the serial data bus.
The slave device automatically detects these received status and data by hardware. This function can simplify
the part of application program that controls the I2C bus.
Since the SCL0 and SDA0 pins are used for open drain outputs, IIC0 requires pull-up resistors for the serial
clock line and the serial data bus line.
Figure 14-1 shows a block diagram of serial interface IIC0.
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User’s Manual U17894EJ9V0UD 531
Figure 14-1. Block Diagram of Serial Interface IIC0
Internal bus
IIC status register 0 (IICS0)
IIC control register 0 (IICC0)
Slave address
register 0 (SVA0)
Noise
eliminator
Noise
eliminator
Bus status
detector
Match
signal
IIC shift
register 0 (IIC0)
SO latch
IICE0
DQ
Set
Clear
CL01,
CL00
TRC0
DFC0
DFC0
SDA0/
P61
SCL0/
P60
Data hold
time correction
circuit
Start
condition
generator
Stop
condition
generator
ACK
generator Wakeup
controller
ACK detector
Output control
Stop condition
detector
Serial clock
counter
Interrupt request
signal generator
Serial clock
controller
Serial clock
wait controller
Prescaler
INTIIC0
IIC shift register 0 (IIC0)
IICC0.STT0, SPT0
IICS0.MSTS0, EXC0, COI0
IICS0.MSTS0,
EXC0, COI0
fCLK
LREL0
WREL0
SPIE0
WTIM0
ACKE0
STT0 SPT0
MSTS0
ALD0 EXC0 COI0 TRC0
ACKD0
STD0 SPD0
Start condition
detector
Internal bus
CLD0 DAD0 SMC0 DFC0 CL01 CL00 CLX0
IIC clock select
register 0 (IICCL0)
STCF
IICBSY STCEN IICRSV
IIC flag register 0
(IICF0)
IIC function expansion
register 0 (IICX0)
N-ch open-
drain output
PM61
Output latch
(P61)
N-ch open-
drain output
PM60
Output latch
(P60)
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Figure 14-2 shows a serial bus configuration example.
Figure 14-2. Serial Bus Configuration Example Using I2C Bus
Master CPU1
Slave CPU1
Address 0
SDA0
SCL0
Serial data bus
Serial clock
+ V
DD
+ V
DD
SDA0
SCL0
SDA0
SCL0
SDA0
SCL0
SDA0
SCL0
Master CPU2
Slave CPU2
Address 1
Slave CPU3
Address 2
Slave IC
Address 3
Slave IC
Address N
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14.2 Configuration of Serial Interface IIC0
Serial interface IIC0 includes the following hardware.
Table 14-1. Configuration of Serial Interface IIC0
Item Configuration
Registers IIC shift register 0 (IIC0)
Slave address register 0 (SVA0)
Control registers Peripheral enable register 0 (PER0)
IIC control register 0 (IICC0)
IIC status register 0 (IICS0)
IIC flag register 0 (IICF0)
IIC clock select register 0 (IICCL0)
IIC function expansion register 0 (IICX0)
Port mode register 6 (PM6)
Port register 6 (P6)
(1) IIC shift register 0 (IIC0)
IIC0 is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial
clock. IIC0 can be used for both transmission and reception.
The actual transmit and receive operations can be controlled by writing and reading operations to IIC0.
Cancel the wait state and start data transfer by writing data to IIC0 during the wait period.
IIC0 can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears IIC0 to 00H.
Figure 14-3. Format of IIC Shift Register 0 (IIC0)
Symbol
IIC0
Address: FFF50H After reset: 00H R/W
76543210
Cautions 1. Do not write data to IIC0 during data transfer.
2. Write or read IIC0 only during the wait period. Accessing IIC0 in a communication state
other than during the wait period is prohibited. When the device serves as the master,
however, IIC0 can be written only once after the communication trigger bit (STT0) is set to
1.
(2) Slave address register 0 (SVA0)
This register stores local addresses when in slave mode.
SVA0 can be set by an 8-bit memory manipulation instruction.
However, rewriting to this register is prohibited while STD0 = 1 (while the start condition is detected).
Reset signal generation clears SVA0 to 00H.
Figure 14-4. Format of Slave Address Register 0 (SVA0)
Symbol
SVA0
Address: FFF53H After reset: 00H R/W
76543210
0
Note
Note Bit 0 is fixed to 0.
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(3) SO latch
The SO latch is used to retain the SDA0 pin’s output level.
(4) Wakeup controller
This circuit generates an interrupt request (INTIIC0) when the address received by this register matches the
address value set to slave address register 0 (SVA0) or when an extension code is received.
(5) Prescaler
This selects the sampling clock to be used.
(6) Serial clock counter
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to
verify that 8-bit data was transmitted or received.
(7) Interrupt request signal generator
This circuit controls the generation of interrupt request signals (INTIIC0).
An I2C interrupt request is generated by the following two triggers.
• Falling edge of eighth or ninth clock of the serial clock (set by WTIM0 bit)
• Interrupt request generated when a stop condition is detected (set by SPIE0 bit)
Remark WTIM0 bit: Bit 3 of IIC control register 0 (IICC0)
SPIE0 bit: Bit 4 of IIC control register 0 (IICC0)
(8) Serial clock controller
In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock.
(9) Serial clock wait controller
This circuit controls the wait timing.
(10) ACK generator, stop condition detector, start condition detector, and ACK detector
These circuits generate and detect each status.
(11) Data hold time correction circuit
This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
(12) Start condition generator
This circuit generates a start condition when the STT0 bit is set to 1.
However, in the communication reservation disabled status (IICRSV bit = 1), when the bus is not released
(IICBSY bit = 1), start condition requests are ignored and the STCF bit is set to 1.
(13) Stop condition generator
This circuit generates a stop condition when the SPT0 bit is set to 1.
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User’s Manual U17894EJ9V0UD 535
(14) Bus status detector
This circuit detects whether or not the bus is released by detecting start conditions and stop conditions.
However, as the bus status cannot be detected immediately following operation, the initial status is set by the
STCEN bit.
Remark STT0 bit: Bit 1 of IIC control register 0 (IICC0)
SPT0 bit: Bit 0 of IIC control register 0 (IICC0)
IICRSV bit: Bit 0 of IIC flag register 0 (IICF0)
IICBSY bit: Bit 6 of IIC flag register 0 (IICF0)
STCF bit: Bit 7 of IIC flag register 0 (IICF0)
STCEN bit: Bit 1 of IIC flag register 0 (IICF0)
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14.3 Registers to Controlling Serial Interface IIC0
Serial interface IIC0 is controlled by the following eight registers.
• Peripheral enable register 0 (PER0)
• IIC control register 0 (IICC0)
• IIC flag register 0 (IICF0)
• IIC status register 0 (IICS0)
• IIC clock select register 0 (IICCL0)
• IIC function expansion register 0 (IICX0)
• Port mode register 6 (PM6)
• Port register 6 (P6)
(1) Peripheral enable register 0 (PER0)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro
that is not used is stopped in order to reduce the power consumption and noise.
When serial interface IIC0 is used, be sure to set bit 4 (IIC0EN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 14-5. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> 1 <0>
PER0 RTCEN DACEN ADCEN IIC0EN SAU1EN SAU0EN 0 TAU0EN
IIC0EN Control of serial interface IIC0 input clock
0 Stops supply of input clock.
• SFR used by serial interface IIC0 cannot be written.
• Serial interface IIC0 is in the reset status.
1 Supplies input clock.
• SFR used by serial interface IIC0 can be read/written.
Cautions 1. When setting serial interface IIC0, be sure to set IIC0EN to 1 first. If IIC0EN = 0, writing to a
control register of serial interface IIC0 is ignored, and, even if the register is read, only the
default value is read (except for port mode register 6 (PM6) and port register 6 (P6)).
2. Be sure to clear bit 1 of the PER0 register to 0.
(2) IIC control register 0 (IICC0)
This register is used to enable/stop I2C operations, set wait timing, and set other I2C operations.
IICC0 can be set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE0, WTIM0, and
ACKE0 bits while IICE0 bit = 0 or during the wait period. These bits can be set at the same time when the
IICE0 bit is set from “0” to “1”.
Reset signal generation clears this register to 00H.
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Figure 14-6. Format of IIC Control Register 0 (IICC0) (1/4)
Address: FFF52H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IICC0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
IICE0 I2C operation enable
0 Stop operation. Reset IIC status register 0 (IICS0)Note 1. Stop internal operation.
1 Enable operation.
Be sure to set this bit (1) while the SCL0 and SDA0 lines are at high level.
Condition for clearing (IICE0 = 0) Condition for setting (IICE0 = 1)
• Cleared by instruction
• Reset
• Set by instruction
LREL0Note 2 Exit from communications
0 Normal operation
1 This exits from the current communications and sets standby mode. This setting is automatically cleared
to 0 after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCL0 and SDA0 lines are set to high impedance.
The following flags of IIC control register 0 (IICC0) and IIC status register 0 (IICS0) are cleared to 0.
• STT0 • SPT0 • MSTS0 • EXC0 • COI0 • TRC0 • ACKD0 • STD0
The standby mode following exit from communications remains in effect until the following communications entry
conditions are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 = 0) Condition for setting (LREL0 = 1)
• Automatically cleared after execution
• Reset
• Set by instruction
WREL0Note 2 Wait cancellation
0 Do not cancel wait
1 Cancel wait. This setting is automatically cleared after wait is canceled.
When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC0 =
1), the SDA0 line goes into the high impedance state (TRC0 = 0).
Condition for clearing (WREL0 = 0) Condition for setting (WREL0 = 1)
• Automatically cleared after execution
• Reset
• Set by instruction
Notes 1. The IICS0 register, the STCF and IICBSY bits of the IICF0 register, and the CLD0 and DAD0
bits of the IICCL0 register are reset.
2. The signal of this bit is invalid while IICE0 is 0.
Caution The start condition is detected immediately after I2C is enabled to operate (IICE0 = 1)
while the SCL0 line is at high level and the SDA0 line is at low level. Immediately after
enabling I2C to operate (IICE0 = 1), set LREL0 (1) by using a 1-bit memory manipulation
instruction.
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Figure 14-6. Format of IIC Control Register 0 (IICC0) (2/4)
SPIE0Note 1 Enable/disable generation of interrupt request when stop condition is detected
0 Disable
1 Enable
Condition for clearing (SPIE0 = 0) Condition for setting (SPIE0 = 1)
• Cleared by instruction
• Reset
• Set by instruction
WTIM0Note 1 Control of wait and interrupt request generation
0 Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
1 Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of
this bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is
inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local
address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ACK) is issued. However,
when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM0 = 0) Condition for setting (WTIM0 = 1)
• Cleared by instruction
• Reset
• Set by instruction
A
CKE
0
Notes 1,
2
Acknowledgment control
0 Disable acknowledgment.
1 Enable acknowledgment. During the ninth clock period, the SDA0 line is set to low level.
Condition for clearing (ACKE0 = 0) Condition for setting (ACKE0 = 1)
• Cleared by instruction
• Reset
• Set by instruction
Notes 1. The signal of this bit is invalid while IICE0 is 0. Set this bit during that period.
2. The set value is invalid during address transfer and if the code is not an extension code.
When the device serves as a slave and the addresses match, an acknowledgment is generated
regardless of the set value.
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Figure 14-6. Format of IIC Control Register 0 (IICC0) (3/4)
STT0Note Start condition trigger
0 Do not generate a start condition.
1 When bus is released (in standby state, when IICBSY = 0):
Generate a start condition (for starting as master). When the SCL0 line is high level, the SDA0 line is
changed from high level to low level and then the start condition is generated. Next, after the rated
amount of time has elapsed, SCL0 is changed to low level (wait state).
When a third party is communicating:
• When communication reservation function is enabled (IICRSV = 0)
Functions as the start condition reservation flag. When set to 1, automatically generates a start
condition after the bus is released.
• When communication reservation function is disabled (IICRSV = 1)
STCF is set to 1 and STT0 is cleared. No start condition is generated.
In the wait state (when master device):
Generates a restart condition after releasing the wait.
Cautions concerning set timing
• For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when
ACKE0 has been cleared to 0 and slave has been notified of final reception.
• For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1
during the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as SPT0.
• Setting STT0 to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (STT0 = 0) Condition for setting (STT0 = 1)
• Cleared by setting SST0 to 1 while communication
reservation is prohibited.
• Cleared by loss in arbitration
• Cleared after start condition is generated by master
device
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
• Set by instruction
Note The signal of this bit is invalid while IICE0 is 0.
Remarks 1. Bit 1 (STT0) becomes 0 when it is read after data setting.
2. IICRSV: Bit 0 of IIC flag register (IICF0)
STCF: Bit 7 of IIC flag register (IICF0)
<R>
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Figure 14-6. Format of IIC Control Register 0 (IICC0) (4/4)
SPT0 Stop condition trigger
0 Stop condition is not generated.
1 Stop condition is generated (termination of master device’s transfer).
After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until it goes to high
level. Next, after the rated amount of time has elapsed, the SDA0 line changes from low level to high
level and a stop condition is generated.
Cautions concerning set timing
• For master reception: Cannot be set to 1 during transfer.
Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave
has been notified of final reception.
• For master transmission: A stop condition cannot be generated normally during the acknowledge period.
Therefore, set it during the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as STT0.
• SPT0 can be set to 1 only when in master modeNote.
• When WTIM0 has been cleared to 0, if SPT0 is set to 1 during the wait period that follows output of eight clocks,
note that a stop condition will be generated during the high-level period of the ninth clock. WTIM0 should be
changed from 0 to 1 during the wait period following the output of eight clocks, and SPT0 should be set to 1 during
the wait period that follows the output of the ninth clock.
• Setting SPT0 to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (SPT0 = 0) Condition for setting (SPT0 = 1)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
• Set by instruction
Note Set SPT0 to 1 only in master mode. However, SPT0 must be set to 1 and a stop condition
generated before the first stop condition is detected following the switch to the operation enabled
status.
Caution When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set to 1 during the
ninth clock and wait is canceled, after which TRC0 is cleared and the SDA0 line is set to
high impedance.
Remark Bit 0 (SPT0) becomes 0 when it is read after data setting.
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(3) IIC status register 0 (IICS0)
This register indicates the status of I2C.
IICS0 is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait
period.
Reset signal generation clears this register to 00H.
Figure 14-7. Format of IIC Status Register 0 (IICS0) (1/3)
Address: FFF56H After reset: 00H R
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IICS0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
MSTS0 Master device status
0 Slave device status or communication standby status
1 Master device communication status
Condition for clearing (MSTS0 = 0) Condition for setting (MSTS0 = 1)
• When a stop condition is detected
• When ALD0 = 1 (arbitration loss)
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
• When a start condition is generated
ALD0 Detection of arbitration loss
0 This status means either that there was no arbitration or that the arbitration result was a “win”.
1 This status indicates the arbitration result was a “loss”. MSTS0 is cleared.
Condition for clearing (ALD0 = 0) Condition for setting (ALD0 = 1)
• Automatically cleared after IICS0 is readNote
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
• When the arbitration result is a “loss”.
EXC0 Detection of extension code reception
0 Extension code was not received.
1 Extension code was received.
Condition for clearing (EXC0 = 0) Condition for setting (EXC0 = 1)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
• When the higher four bits of the received address
data is either “0000” or “1111” (set at the rising edge
of the eighth clock).
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits
other than IICS0. Therefore, when using the ALD0 bit, read the data of this bit before the data
of the other bits.
Remark LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0: Bit 7 of IIC control register 0 (IICC0)
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Figure 14-7. Format of IIC Status Register 0 (IICS0) (2/3)
COI0 Detection of matching addresses
0 Addresses do not match.
1 Addresses match.
Condition for clearing (COI0 = 0) Condition for setting (COI0 = 1)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
• When the received address matches the local
address (slave address register 0 (SVA0))
(set at the rising edge of the eighth clock).
TRC0 Detection of transmit/receive status
0 Receive status (other than transmit status). The SDA0 line is set for high impedance.
1 Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at
the falling edge of the first byte’s ninth clock).
Condition for clearing (TRC0 = 0) Condition for setting (TRC0 = 1)
<Both master and slave>
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Cleared by WREL0 = 1Note (wait cancel)
• When ALD0 changes from 0 to 1 (arbitration loss)
• Reset
<Master>
• When “1” is output to the first byte’s LSB (transfer
direction specification bit)
<Slave>
• When a start condition is detected
• When “0” is input to the first byte’s LSB (transfer
direction specification bit)
<When not used for communication>
<Master>
• When a start condition is generated
• When “0” is output to the first byte’s LSB (transfer
direction specification bit)
<Slave>
• When “1” is input to the first byte’s LSB (transfer
direction specification bit)
Note If the wait state is canceled by setting bit 5 (WREL0) of IIC control register 0 (IICC0) to 1 at the
ninth clock when bit 3 (TRC0) of IIC status register 0 (IICS0) is 1, TRC0 is cleared, and the
SDA0 line goes into a high-impedance state.
Remark LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0: Bit 7 of IIC control register 0 (IICC0)
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Figure 14-7. Format of IIC Status Register 0 (IICS0) (3/3)
ACKD0 Detection of acknowledge (ACK)
0 Acknowledge was not detected.
1 Acknowledge was detected.
Condition for clearing (ACKD0 = 0) Condition for setting (ACKD0 = 1)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
• After the SDA0 line is set to low level at the rising
edge of SCL0’s ninth clock
STD0 Detection of start condition
0 Start condition was not detected.
1 Start condition was detected. This indicates that the address transfer period is in effect.
Condition for clearing (STD0 = 0) Condition for setting (STD0 = 1)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
following address transfer
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
• When a start condition is detected
SPD0 Detection of stop condition
0 Stop condition was not detected.
1 Stop condition was detected. The master device’s communication is terminated and the bus is
released.
Condition for clearing (SPD0 = 0) Condition for setting (SPD0 = 1)
• At the rising edge of the address transfer byte’s first
clock following setting of this bit and detection of a
start condition
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
• When a stop condition is detected
Remark LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0: Bit 7 of IIC control register 0 (IICC0)
(4) IIC flag register 0 (IICF0)
This register sets the operation mode of I2C and indicates the status of the I2C bus.
IICF0 can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STCF and IICBSY bits are
read-only.
The IICRSV bit can be used to enable/disable the communication reservation function.
STCEN can be used to set the initial value of the IICBSY bit.
IICRSV and STCEN can be written only when the operation of I2C is disabled (bit 7 (IICE0) of IIC control
register 0 (IICC0) = 0). When operation is enabled, the IICF0 register can be read.
Reset signal generation clears this register to 00H.
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Figure 14-8. Format of IIC Flag Register 0 (IICF0)
<7>
STCF
Condition for clearing (STCF = 0)
• Cleared by STT0 = 1
• When IICE0 = 0 (operation stop)
• Reset
Condition for setting (STCF = 1)
• Generating start condition unsuccessful and STT0
cleared to 0 when communication reservation is
disabled (IICRSV = 1).
STCF
0
1
Generate start condition
Start condition generation unsuccessful: clear STT0 flag
STT0 clear flag
IICF0
Symbol <6>
IICBSY
5
0
4
0
3
0
2
0
<1>
STCEN
<0>
IICRSV
Address: FFF51H After reset: 00H R/W
Note
Condition for clearing (IICBSY = 0)
• Detection of stop condition
• When IICE0 = 0 (operation stop)
• Reset
Condition for setting (IICBSY = 1)
• Detection of start condition
• Setting of IICE0 when STCEN = 0
IICBSY
0
1
Bus release status (communication initial status when STCEN = 1)
Bus communication status (communication initial status when STCEN = 0)
I
2
C bus status flag
Condition for clearing (STCEN = 0)
• Cleared by instruction
• Detection of start condition
• Reset
Condition for setting (STCEN = 1)
• Set by instruction
STCEN
0
1
After operation is enabled (IICE0 = 1), enable generation of a start condition upon detection of
a stop condition.
After operation is enabled (IICE0 = 1), enable generation of a start condition without detecting
a stop condition.
Initial start enable trigger
Condition for clearing (IICRSV = 0)
• Cleared by instruction
• Reset
Condition for setting (IICRSV = 1)
• Set by instruction
IICRSV
0
1
Enable communication reservation
Disable communication reservation
Communication reservation function disable bit
Note Bits 6 and 7 are read-only.
Cautions 1. Write to STCEN only when the operation is stopped (IICE0 = 0).
2. As the bus release status (IICBSY = 0) is recognized regardless of the actual bus
status when STCEN = 1, when generating the first start condition (STT0 = 1), it is
necessary to verify that no third party communications are in progress in order to
prevent such communications from being destroyed.
3. Write to IICRSV only when the operation is stopped (IICE0 = 0).
Remark STT0: Bit 1 of IIC control register 0 (IICC0)
IICE0: Bit 7 of IIC control register 0 (IICC0)
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(5) IIC clock select register 0 (IICCL0)
This register is used to set the transfer clock for the I2C bus.
IICCL0 can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are
read-only. The SMC0, CL01, and CL00 bits are set in combination with bit 0 (CLX0) of IIC function expansion
register 0 (IICX0) (see 14.5.4 Transfer clock setting method).
Set IICCL0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0.
Reset signal generation clears this register to 00H.
Figure 14-9. Format of IIC Clock Select Register 0 (IICCL0)
Address: FFF54H After reset: 00H R/WNote
Symbol 7 6 <5> <4> <3> <2> 1 0
IICCL0 0 0 CLD0 DAD0 SMC0 DFC0 CL01 CL00
CLD0 Detection of SCL0 pin level (valid only when IICE0 = 1)
0 The SCL0 pin was detected at low level.
1 The SCL0 pin was detected at high level.
Condition for clearing (CLD0 = 0) Condition for setting (CLD0 = 1)
• When the SCL0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
• When the SCL0 pin is at high level
DAD0 Detection of SDA0 pin level (valid only when IICE0 = 1)
0 The SDA0 pin was detected at low level.
1 The SDA0 pin was detected at high level.
Condition for clearing (DAD0 = 0) Condition for setting (DAD0 = 1)
• When the SDA0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
• When the SDA0 pin is at high level
SMC0 Operation mode switching
0 Operates in standard mode.
1 Operates in fast mode.
DFC0 Digital filter operation control
0 Digital filter off.
1 Digital filter on.
Digital filter can be used only in fast mode.
In fast mode, the transfer clock does not vary regardless of DFC0 bit set (1)/clear (0).
The digital filter is used for noise elimination in fast mode.
Note Bits 4 and 5 are read-only.
Remark IICE0: Bit 7 of IIC control register 0 (IICC0)
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(6) IIC function expansion register 0 (IICX0)
This register sets the function expansion of I2C.
IICX0 can be set by a 1-bit or 8-bit memory manipulation instruction. The CLX0 bit is set in combination with
bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock select register 0 (IICCL0) (see 14.5.4 Transfer clock
setting method).
Set IICX0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0.
Reset signal generation clears this register to 00H.
Figure 14-10. Format of IIC Function Expansion Register 0 (IICX0)
Address: FFF55H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 <0>
IICX0 0 0 0 0 0 0 0 CLX0
Table 14-2. Selection Clock Setting
IICX0 IICCL0
Bit 0 Bit 3 Bit 1 Bit 0
CLX0 SMC0 CL01 CL00
Transfer Clock (fCLK/m) Settable Selection Clock
(fCLK) Range
Operation Mode
0 0 0 0 fCLK/88 4.00 MHz to 8.4 MHz
0 0 0 1 fCLK/172 8.38 MHz to 16.76 MHz
0 0 1 0 fCLK/344 16.76 MHz to 20 MHz
0 0 1 1 fCLK/44 2.00 MHz to 4.2 MHz
Normal mode (SMC0 bit = 0)
0 1 0 × fCLK/48 7.60 MHz to 16.76 MHz
0 1 1 0 fCLK/96 16.00 MHz to 20 MHz
0 1 1 1 fCLK/24 4.00 MHz to 8.4 MHz
Fast mode (SMC0 bit = 1)
1 0 × × Setting prohibited
1 1 0 × fCLK/48 8.00 MHz to 8.38 MHz
1 1 1 0 Setting prohibited 16.00 MHz to 16.76 MHz
1 1 1 1 fCLK/24 4.00 MHz to 4.19 MHz
Fast mode (SMC0 bit = 1)
Caution Determine the transfer clock frequency of I2C by using CLX0, SMC0, CL01, and CL00 before
enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0) to 1). To change
the transfer clock frequency, clear IICE0 once to 0.
Remarks 1. ×: don’t care
2. fCLK: CPU/peripheral hardware clock frequency
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(7) Port mode register 6 (PM6)
This register sets the input/output of port 6 in 1-bit units.
When using the P60/SCL0 pin as clock I/O and the P61/SDA0 pin as serial data I/O, clear PM60 and PM61,
and the output latches of P60 and P61 to 0.
Set IICE0 (bit 7 of IIC control register 0 (IICC0)) to 1 before setting the output mode because the P60/SCL0
and P61/SDA0 pins output a low level (fixed) when IICE0 is 0.
PM6 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 14-11. Format of Port Mode Register 6 (PM6)
PM60PM61PM62PM63PM64PM65PM66PM67
P6n pin I/O mode selection (n = 0 to 7)
Output mode (output buffer on)
Input mode (output buffer off)
PM6n
0
1
01234567
PM6
Address: FFF26H After reset: FFH R/W
Symbol
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14.4 I2C Bus Mode Functions
14.4.1 Pin configuration
The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows.
(1) SCL0....... This pin is used for serial clock input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
(2) SDA0 ...... This pin is used for serial data input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up
resistor is required.
Figure 14-12. Pin Configuration Diagram
Master device
Clock output
(Clock input)
Data output
Data input
V
SS
V
SS
SCL0
SDA0
V
DD
V
DD
(Clock output)
Clock input
Data output
Data input
V
SS
V
SS
Slave device
SCL0
SDA0
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14.5 I2C Bus Definitions and Control Methods
The following section describes the I2C bus’s serial data communication format and the signals used by the I2C bus.
Figure 14-13 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the
I2C bus’s serial data bus.
Figure 14-13. I2C Bus Serial Data Transfer Timing
SCL0
SDA0
Start
condition
Address R/W ACK Data
1-7 8 9 1-8
ACK Data ACK Stop
condition
9 1-8 9
The master device generates the start condition, slave address, and stop condition.
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device
that receives 8-bit data).
The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0’s low
level period can be extended and a wait can be inserted.
14.5.1 Start conditions
A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level.
The start conditions for the SCL0 pin and SDA0 pin are signals that the master device generates to the slave device
when starting a serial transfer. When the device is used as a slave, start conditions can be detected.
Figure 14-14. Start Conditions
SCL0
SDA0
H
A start condition is output when bit 1 (STT0) of IIC control register 0 (IICC0) is set (to 1) after a stop condition has
been detected (SPD0: Bit 0 = 1 in IIC status register 0 (IICS0)). When a start condition is detected, bit 1 (STD0) of
IICS0 is set (to 1).
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14.5.2 Addresses
The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to
the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique
address.
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address
data matches the data values stored in slave address register 0 (SVA0). If the address data matches the SVA0
values, the slave device is selected and communicates with the master device until the master device generates a
start condition or stop condition.
Figure 14-15. Address
SCL0
SDA0
INTIIC0
123456789
A6 A5 A4 A3 A2 A1 A0 R/W
Address
Note
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
operation.
The slave address and the eighth bit, which specifies the transfer direction as described in 14.5.3 Transfer
direction specification below, are together written to IIC shift register 0 (IIC0) and are then output. Received
addresses are written to IIC0.
The slave address is assigned to the higher 7 bits of IIC0.
14.5.3 Transfer direction specification
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction.
When this transfer direction specification bit has a value of “0”, it indicates that the master device is transmitting
data to a slave device. When the transfer direction specification bit has a value of “1”, it indicates that the master
device is receiving data from a slave device.
Figure 14-16. Transfer Direction Specification
SCL0
SDA0
INTIIC0
123456789
A6 A5 A4 A3 A2 A1 A0 R/W
Transfer direction specification
Note
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
operation.
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14.5.4 Transfer clock setting method
(1) Selection clock setting method on the master side
The I2C transfer clock frequency (fSCL) is calculated using the following expression.
fSCL = 1/(m × T + tR + tF)
m = 24, 44, 48, 88, 96, 172, 344 (see Table 14-3 Selection Clock Setting)
T: 1/fCLK
tR: SCL0 rise time
tF: SCL0 fall time
For example, the I2C transfer clock frequency (fSCL) when fCLK = 4.19 MHz, m = 88, tR = 200 ns, and tF = 50 ns
is calculated using following expression.
fSCL = 1/(88 × 238.7 ns + 200 ns + 50 ns) ≅ 47.0 kHz
m × T + t
R
+ t
F
m/2 × Tm/2 × T t
F
t
R
SCL0
SCL0 inversion SCL0 inversion SCL0 inversion
The selection clock is set using a combination of bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock select
register 0 (IICCL0) and bit 0 (CLX0) of IIC function expansion register 0 (IICX0).
(2) Selection clock setting method on the slave side
To use as slave, set the bits 3, 1, and 0 (SMC0, CL01, CL00) of the IIC clock selection register (IICL0) and the
bit 0 (CLX0) of the IIC function expansion register 0 (IICX0) according to the fCLK (Selectable Selection Clock
Range) and IIC Operation Mode (Normal or Fast ) as defined in Table 14-3. Selection Clock Setting.
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Table 14-3. Selection Clock Setting
IICX0 IICCL0
Bit 0 Bit 3 Bit 1 Bit 0
CLX0 SMC0 CL01 CL00
Transfer Clock (fCLK/m) Settable Selection Clock
(fCLK) Range
Operation Mode
0 0 0 0 fCLK/88 4.00 MHz to 8.4 MHz
0 0 0 1 fCLK/172 8.38 MHz to 16.76 MHz
0 0 1 0 fCLK/344 16.76 MHz to 20 MHz
0 0 1 1 fCLK/44 2.00 MHz to 4.2 MHz
Normal mode (SMC0 bit = 0)
0 1 0 × fCLK/48 7.60 MHz to 16.76 MHz
0 1 1 0 fCLK/96 16.00 MHz to 20 MHz
0 1 1 1 fCLK/24 4.00 MHz to 8.4 MHz
Fast mode (SMC0 bit = 1)
1 0 × × Setting prohibited
1 1 0 × fCLK/48 8.00 MHz to 8.38 MHz
1 1 1 0 Setting prohibited 16.00 MHz to 16.76 MHz
1 1 1 1 fCLK/24 4.00 MHz to 4.19 MHz
Fast mode (SMC0 bit = 1)
Caution Determine the transfer clock frequency of I2C by using CLX0, SMC0, CL01, and CL00 before
enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0) to 1). To change
the transfer clock frequency, clear IICE0 once to 0.
Remarks 1. ×: don’t care
2. fCLK: CPU/peripheral hardware clock frequency
14.5.5 Acknowledge (ACK)
ACK is used to check the status of serial data at the transmission and reception sides.
The reception side returns ACK each time it has received 8-bit data.
The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception
side, it is assumed that reception has been correctly performed and processing is continued. Whether ACK has been
detected can be checked by using bit 2 (ACKD0) of IIC status register 0 (IICS0).
When the master receives the last data item, it does not return ACK and instead generates a stop condition. If a
slave does not return ACK after receiving data, the master outputs a stop condition or restart condition and stops
transmission. If ACK is not returned, the possible causes are as follows.
<1> Reception was not performed normally.
<2> The final data item was received.
<3> The reception side specified by the address does not exist.
To generate ACK, the reception side makes the SDA0 line low at the ninth clock (indicating normal reception).
Automatic generation of ACK is enabled by setting bit 2 (ACKE0) of IIC control register 0 (IICC0) to 1. Bit 3 (TRC0)
of the IICS0 register is set by the data of the eighth bit that follows 7-bit address information. Usually, set ACKE0 to 1
for reception (TRC0 = 0).
If a slave can receive no more data during reception (TRC0 = 0) or does not require the next data item, then the
slave must inform the master, by clearing ACKE0 to 0, that it will not receive any more data.
When the master does not require the next data item during reception (TRC0 = 0), it must clear ACKE0 to 0 so that
ACK is not generated. In this way, the master informs a slave at the transmission side that it does not require any
more data (transmission will be stopped).
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Figure 14-17. ACK
SCL0
SDA0
123456789
A6 A5 A4 A3 A2 A1 A0 R/W ACK
When the local address is received, ACK is automatically generated, regardless of the value of ACKE0. When an
address other than that of the local address is received, ACK is not generated (NACK).
When an extension code is received, ACK is generated if ACKE0 is set to 1 in advance.
How ACK is generated when data is received differs as follows depending on the setting of the wait timing.
• When 8-clock wait state is selected (bit 3 (WTIM0) of IICC0 register = 0):
By setting ACKE0 to 1 before releasing the wait state, ACK is generated at the falling edge of the eighth clock of
the SCL0 pin.
• When 9-clock wait state is selected (bit 3 (WTIM0) of IICC0 register = 1):
ACK is generated by setting ACKE0 to 1 in advance.
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14.5.6 Stop condition
When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition.
A stop condition is a signal that the master device generates to the slave device when serial transfer has been
completed. When the device is used as a slave, stop conditions can be detected.
Figure 14-18. Stop Condition
SCL0
SDA0
H
A stop condition is generated when bit 0 (SPT0) of IIC control register 0 (IICC0) is set to 1. When the stop
condition is detected, bit 0 (SPD0) of IIC status register 0 (IICS0) is set to 1 and INTIIC0 is generated when bit 4
(SPIE0) of IICC0 is set to 1.
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14.5.7 Wait
The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or
receive data (i.e., is in a wait state).
Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been
canceled for both the master and slave devices, the next data transfer can begin.
Figure 14-19. Wait (1/2)
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
(master transmits, slave receives, and ACKE0 = 1)
Master
IIC0
SCL0
Slave
IIC0
SCL0
ACKE0
Transfer lines
SCL0
SDA0
6789 123
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of ninth clock
IIC0 data write (cancel wait)
Wait after output
of eighth clock
Wait from slave Wait from master
FFH is written to IIC0 or WREL0 is set to 1
678 9 123
D2 D1 D0 D7 D6 D5ACK
H
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Figure 14-19. Wait (2/2)
(2) When master and slave devices both have a nine-clock wait
(master transmits, slave receives, and ACKE0 = 1)
Master
IIC0
SCL0
Slave
IIC0
SCL0
ACKE0
Transfer lines
SCL0
SDA0
H
6789 1 23
Master and slave both wait
after output of ninth clock
Wait from
master and
slave Wait from slave
IIC0 data write (cancel wait)
FFH is written to IIC0 or WREL0 is set to 1
6789 123
D2 D1 D0 ACK D7 D6 D5
Generate according to previously set ACKE0 value
Remark ACKE0: Bit 2 of IIC control register 0 (IICC0)
WREL0: Bit 5 of IIC control register 0 (IICC0)
A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of IIC control register 0 (IICC0).
Normally, the receiving side cancels the wait state when bit 5 (WREL0) of IICC0 is set to 1 or when FFH is written
to IIC shift register 0 (IIC0), and the transmitting side cancels the wait state when data is written to IIC0.
The master device can also cancel the wait state via either of the following methods.
• By setting bit 1 (STT0) of IICC0 to 1
• By setting bit 0 (SPT0) of IICC0 to 1
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14.5.8 Canceling wait
The I2C usually cancels a wait state by the following processing.
• Writing data to IIC shift register 0 (IIC0)
• Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait)
• Setting bit 1 (STT0) of IIC0 register (generating start condition)Note
• Setting bit 0 (SPT0) of IIC0 register (generating stop condition)Note
Note Master only
When the above wait canceling processing is executed, the I2C cancels the wait state and communication is
resumed.
To cancel a wait state and transmit data (including addresses), write the data to IIC0.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL0) of the IIC0 control
register 0 (IICC0) to 1.
To generate a restart condition after canceling a wait state, set bit 1 (STT0) of IICC0 to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPT0) of IICC0 to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to IIC0 after canceling a wait state by setting WREL0 to 1, an incorrect value may be
output to SDA0 because the timing for changing the SDA0 line conflicts with the timing for writing IIC0.
In addition to the above, communication is stopped if IICE0 is cleared to 0 when communication has been aborted,
so that the wait state can be canceled.
If the I2C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL0) of
IICC0, so that the wait state can be canceled.
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14.5.9 Interrupt request (INTIIC0) generation timing and wait control
The setting of bit 3 (WTIM0) of IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated
and the corresponding wait control, as shown in Table 14-4.
Table 14-4. INTIIC0 Generation Timing and Wait Control
During Slave Device Operation During Master Device Operation WTIM0
Address Data Reception Data Transmission Address Data Reception Data Transmission
0 9Notes 1, 2 8
Note 2 8
Note 2 9 8 8
1 9Notes 1, 2 9
Note 2 9
Note 2 9 9 9
Notes 1. The slave device’s INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when
there is a match with the address set to slave address register 0 (SVA0).
At this point, ACK is generated regardless of the value set to IICC0’s bit 2 (ACKE0). For a slave device
that has received an extension code, INTIIC0 occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIIC0 is generated at the falling edge of the 9th
clock, but wait does not occur.
2. If the received address does not match the contents of slave address register 0 (SVA0) and extension
code is not received, neither INTIIC0 nor a wait occurs.
Remark The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and
wait control are both synchronized with the falling edge of these clock signals.
(1) During address transmission/reception
• Slave device operation: Interrupt and wait timing are determined depending on the conditions described in
Notes 1 and 2 above, regardless of the WTIM0 bit.
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
the WTIM0 bit.
(2) During data reception
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
(3) During data transmission
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
(4) Wait cancellation method
The four wait cancellation methods are as follows.
• Writing data to IIC shift register 0 (IIC0)
• Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait)
• Setting bit 1 (STT0) of IIC0 register (generating start condition)Note
• Setting bit 0 (SPT0) of IIC0 register (generating stop condition)Note
Note Master only.
When an 8-clock wait has been selected (WTIM0 = 0), the presence/absence of ACK generation must be
determined prior to wait cancellation.
(5) Stop condition detection
INTIIC0 is generated when a stop condition is detected (only when SPIE0 = 1).
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14.5.10 Address match detection method
In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave
address.
Address match can be detected automatically by hardware. An INTIIC0 occurs when the address set to the slave
address register 0 (SVA0) matches the slave address sent by the master device, or when an extension code has been
received.
14.5.11 Error detection
In I2C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by IIC shift register 0
(IIC0) of the transmitting device, so the IIC0 data prior to transmission can be compared with the transmitted IIC0 data
to enable detection of transmission errors. A transmission error is judged as having occurred when the compared
data values do not match.
14.5.12 Extension code
(1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag
(EXC0) is set to 1 for extension code reception and an interrupt request (INTIIC0) is issued at the falling edge
of the eighth clock. The local address stored in slave address register 0 (SVA0) is not affected.
(2) The settings below are specified if 11110xx0 is transferred from the master by using a 10-bit address transfer
when SVA0 is set to 11110xx0. Note that INTIIC0 occurs at the falling edge of the eighth clock.
• Higher four bits of data match: EXC0 = 1
• Seven bits of data match: COI0 = 1
Remark EXC0: Bit 5 of IIC status register 0 (IICS0)
COI0: Bit 4 of IIC status register 0 (IICS0)
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension
code, such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave
device, set bit 6 (LREL0) of the IIC control register 0 (IICC0) to 1 to set the standby mode for the next
communication operation.
Table 14-5. Bit Definitions of Major Extension Codes
Slave Address R/W Bit Description
0 0 0 0 0 0 0 0 General call address
1 1 1 1 0 x x 0 10-bit slave address specification (during address
authentication)
1 1 1 1 0 x x 1 10-bit slave address specification (after address match, when
read command is issued)
Remark See the I2C bus specifications issued by NXP Semiconductors for details of extension codes
other than those described above.
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14.5.13 Arbitration
When several master devices simultaneously generate a start condition (when STT0 is set to 1 before STD0 is set
to 1), communication among the master devices is performed as the number of clocks are adjusted until the data
differs. This kind of operation is called arbitration.
When one of the master devices loses in arbitration, an arbitration loss flag (ALD0) in IIC status register 0 (IICS0)
is set (1) via the timing by which the arbitration loss occurred, and the SCL0 and SDA0 lines are both set to high
impedance, which releases the bus.
The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a
stop condition is detected, etc.) and the ALD0 = 1 setting that has been made by software.
For details of interrupt request timing, see 14.5.9 Interrupt request (INTIIC0) generation timing and wait
control.
Remark STD0: Bit 1 of IIC status register 0 (IICS0)
STT0: Bit 1 of IIC control register 0 (IICC0)
Figure 14-20. Arbitration Timing Example
SCL0
SDA0
SCL0
SDA0
SCL0
SDA0
Hi-Z
Hi-Z
Master 1 loses arbitration
Master 1
Master 2
Transfer lines
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Table 14-6. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration Interrupt Request Generation Timing
During address transmission
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK transfer period after data transmission
When restart condition is detected during data transfer
At falling edge of eighth or ninth clock following byte transferNote 1
When stop condition is detected during data transfer When stop condition is generated (when SPIE0 = 1)Note 2
When data is at low level while attempting to generate a restart
condition
At falling edge of eighth or ninth clock following byte transferNote 1
When stop condition is detected while attempting to generate a
restart condition
When stop condition is generated (when SPIE0 = 1)Note 2
When data is at low level while attempting to generate a stop
condition
When SCL0 is at low level while attempting to generate a
restart condition
At falling edge of eighth or ninth clock following byte transferNote 1
Notes 1. When WTIM0 (bit 3 of IIC control register 0 (IICC0)) = 1, an interrupt request occurs at the falling edge
of the ninth clock. When WTIM0 = 0 and the extension code’s slave address is received, an interrupt
request occurs at the falling edge of the eighth clock.
2. When there is a chance that arbitration will occur, set SPIE0 = 1 for master device operation.
Remark SPIE0: Bit 4 of IIC control register 0 (IICC0)
14.5.14 Wakeup function
The I2C bus slave function is a function that generates an interrupt request signal (INTIIC0) when a local address
and extension code have been received.
This function makes processing more efficient by preventing unnecessary INTIIC0 signal from occurring when
addresses do not match.
When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while
addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has
generated a start condition) to a slave device.
However, when a stop condition is detected, bit 4 (SPIE0) of IIC control register 0 (IICC0) is set regardless of the
wakeup function, and this determines whether interrupt requests are enabled or disabled.
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14.5.15 Communication reservation
(1) When communication reservation function is enabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 0)
To start master device communications when not currently using a bus, a communication reservation can be
made to enable transmission of a start condition when the bus is released. There are two modes under which
the bus is not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
released by setting bit 6 (LREL0) of IIC control register 0 (IICC0) to 1 and saving communication).
If bit 1 (STT0) of IICC0 is set to 1 while the bus is not used (after a stop condition is detected), a start condition
is automatically generated and wait state is set.
If an address is written to IIC shift register 0 (IIC0) after bit 4 (SPIE0) of IICC0 was set to 1, and it was detected
by generation of an interrupt request signal (INTIIC0) that the bus was released (detection of the stop
condition), then the device automatically starts communication as the master. Data written to IIC0 before the
stop condition is detected is invalid.
When STT0 has been set to 1, the operation mode (as start condition or as communication reservation) is
determined according to the bus status.
• If the bus has been released ........................................ a start condition is generated
• If the bus has not been released (standby mode)......... communication reservation
Check whether the communication reservation operates or not by using MSTS0 (bit 7 of IIC status register 0
(IICS0)) after STT0 is set to 1 and the wait time elapses.
The wait periods, which should be set via software, are listed in Table 14-6.
Table 14-7. Wait Periods
CLX0 SMC0 CL01 CL00 Wait Period
0 0 0 0 43 clocks
0 0 0 1 85 clocks
0 0 1 0 101 clocks
0 0 1 1 23 clocks
0 1 0 0
0 1 0 1
27 clocks
0 1 1 0 51 clocks
0 1 1 1
1 1 0 0
1 1 0 1
15 clocks
1 1 1 0 27 clocks
1 1 1 1 9 clocks
Figure 14-21 shows the communication reservation timing.
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Figure 14-21. Communication Reservation Timing
21 3456 21 3456789
SCL0
SDA0
Program processing
Hardware processing
Write to
IIC0
Set SPD0
and
INTIIC0
STT0 = 1
Communi-
cation
reservation
Set
STD0
Generate by master device with bus mastership
Remark IIC0: IIC shift register 0
STT0: Bit 1 of IIC control register 0 (IICC0)
STD0: Bit 1 of IIC status register 0 (IICS0)
SPD0: Bit 0 of IIC status register 0 (IICS0)
Communication reservations are accepted via the timing shown in Figure 14-22. After bit 1 (STD0) of IIC
status register 0 (IICS0) is set to 1, a communication reservation can be made by setting bit 1 (STT0) of IIC
control register 0 (IICC0) to 1 before a stop condition is detected.
Figure 14-22. Timing for Accepting Communication Reservations
SCL0
SDA0
STD0
SPD0
Standby mode (Communication can be reserved
by setting STT to 1 during this period.)
Figure 14-23 shows the communication reservation protocol.
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Figure 14-23. Communication Reservation Protocol
DI
SET1 STT0
Define communication
reservation
Wait
MSTS0 = 0?
(Communication reservation)
Note
Yes
No
(Generate start condition)
Cancel communication
reservation
MOV IIC0, #××H
EI
Sets STT0 flag (communication reservation)
Defines that communication reservation is in effect
(defines and sets user flag to any part of RAM)
Secures wait period set by software (see Table 14-7).
Confirmation of communication reservation
Clears user flag
IIC0 write operation
Note The communication reservation operation executes a write to IIC shift register 0 (IIC0) when a stop
condition interrupt request occurs.
Remark STT0: Bit 1 of IIC control register 0 (IICC0)
MSTS0: Bit 7 of IIC status register 0 (IICS0)
IIC0: IIC shift register 0
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(2) When communication reservation function is disabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 1)
When bit 1 (STT0) of IIC control register 0 (IICC0) is set to 1 when the bus is not used in a communication
during bus communication, this request is rejected and a start condition is not generated. The following two
statuses are included in the status where bus is not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
released by setting bit 6 (LREL0) of IICC0 to 1 and saving communication)
To confirm whether the start condition was generated or request was rejected, check STCF (bit 7 of IICF0). It
takes up to 5 clocks until STCF is set to 1 after setting STT0 = 1. Therefore, secure the time by software.
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14.5.16 Cautions
(1) When STCEN (bit 1 of IIC flag register 0 (IICF0)) = 0
Immediately after I2C operation is enabled (IICE0 = 1), the bus communication status (IICBSY (bit 6 of IICF0) =
1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition
has been detected to a master device communication mode, first generate a stop condition to release the bus,
then perform master device communication.
When using multiple masters, it is not possible to perform master device communication when the bus has not
been released (when a stop condition has not been detected).
Use the following sequence for generating a stop condition.
<1> Set IIC clock select register 0 (IICCL0).
<2> Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1.
<3> Set bit 0 (SPT0) of IICC0 to 1.
(2) When STCEN = 1
Immediately after I2C operation is enabled (IICE0 = 1), the bus released status (IICBSY = 0) is recognized
regardless of the actual bus status. To generate the first start condition (STT0 (bit 1 of IIC control register 0
(IICC0)) = 1), it is necessary to confirm that the bus has been released, so as to not disturb other
communications.
(3) If other I2C communications are already in progress
If I2C operation is enabled and the device participates in communication already in progress when the SDA0
pin is low and the SCL0 pin is high, the macro of I2C recognizes that the SDA0 pin has gone low (detects a
start condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned,
but this interferes with other I2C communications. To avoid this, start I2C in the following sequence.
<1> Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an interrupt request signal (INTIIC0) when the
stop condition is detected.
<2> Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I2C.
<3> Wait for detection of the start condition.
<4> Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after setting IICE0 to 1), to forcibly
disable detection.
(4) Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1, and 0 of IICL0), and CLX0 (bit 0
of IICX0) before enabling the operation (IICE0 = 1). To change the transfer clock frequency, clear IICE0 to 0
once.
(5) Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and before they are cleared to 0 is
prohibited.
(6) When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt request is generated when
the stop condition is detected. Transfer is started when communication data is written to IIC0 after the interrupt
request is generated. Unless the interrupt is generated when the stop condition is detected, the device stops
in the wait state because the interrupt request is not generated when communication is started. However, it is
not necessary to set SPIE0 to 1 when MSTS0 (bit 7 of IICS0) is detected by software.
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14.5.17 Communication operations
The following shows three operation procedures with the flowchart.
(1) Master operation in single master system
The flowchart when using the 78K0R/KG3 as the master in a single master system is shown below.
This flowchart is broadly divided into the initial settings and communication processing. Execute the initial
settings at startup. If communication with the slave is required, prepare the communication and then execute
communication processing.
(2) Master operation in multimaster system
In the I2C bus multimaster system, whether the bus is released or used cannot be judged by the I2C bus
specifications when the bus takes part in a communication. Here, when data and clock are at a high level for a
certain period (1 frame), the 78K0R/KG3 takes part in a communication with bus released state.
This flowchart is broadly divided into the initial settings, communication waiting, and communication processing.
The processing when the 78K0R/KG3 looses in arbitration and is specified as the slave is omitted here, and
only the processing as the master is shown. Execute the initial settings at startup to take part in a
communication. Then, wait for the communication request as the master or wait for the specification as the
slave. The actual communication is performed in the communication processing, and it supports the
transmission/reception with the slave and the arbitration with other masters.
(3) Slave operation
An example of when the 78K0R/KG3 is used as the I2C bus slave is shown below.
When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait
for the INTIIC0 interrupt occurrence (communication waiting). When an INTIIC0 interrupt occurs, the
communication status is judged and its result is passed as a flag over to the main processing.
By checking the flags, necessary communication processing is performed.
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(1) Master operation in single-master system
Figure 14-24. Master Operation in Single-Master System
SPT0 = 1
SPT0 = 1
WREL0 = 1
START
END
ACKE0 = 0
WTIM0 = WREL0 = 1
No
No
Yes
No
No
No
Yes
Yes
Yes
Yes
STCEN = 1?
ACKE0 = 1
WTIM0 = 0
TRC0 = 1?
ACKD0 = 1?
ACKD0 = 1?
No
Yes
No
Yes
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
STT0 = 1
IICX0 ← 0XH
IICCL0 ← XXH
IICF0 ← 0XH
Setting STCEN, IICRSV = 0
Setting port
Initializing I
2
C bus
Note
SVA0 ← XXH
Writing IIC0
Writing IIC0
Reading IIC0
INTIIC0
interrupt occurs?
End of transfer?
End of transfer?
Restart?
Sets the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 14.3 (7) Port mode register 6 (PM6)).
Selects a transfer clock.
Sets a local address.
Sets a start condition.
Prepares for starting communication
(generates a start condition).
Starts communication
(specifies an address and transfer
direction).
Waits for detection of acknowledge.
Waits for data transmission.
Starts transmission.
Communication processing Initial setting
Starts reception.
Waits for data
reception.
INTIIC0
interrupt occurs?
Waits for detection
of acknowledge.
Prepares for starting communication
(generates a stop condition).
Waits for detection of the stop condition.
INTIIC0
Interrupt occurs?
INTIIC0
interrupt occurs?
INTIIC0
interrupt occurs?
Sets the port from input mode to output mode and enables the output of the I
2
C bus
(see 14.3 (7) Port mode register 6 (PM6)).
IICC0 ← 0XX111XXB
ACKE0 = WTIM0 = SPIE0 = 1
IICC0 ← 1XX111XXB
IICE0 = 1
Setting port
Note Release (SCL0 and SDA0 pins = high level) the I2C bus in conformance with the specifications of the
product that is communicating. If EEPROM is outputting a low level to the SDA0 pin, for example, set the
SCL0 pin in the output port mode, and output a clock pulse from the output port until the SDA0 pin is
constantly at high level.
Remark Conform to the specifications of the product that is communicating, with respect to the transmission and
reception formats.
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(2) Master operation in multi-master system
Figure 14-25. Master Operation in Multi-Master System (1/3)
IICX0 ← 0XH
IICCL0 ← XXH
IICF0 ← 0XH
Setting STCEN and IICRSV
Setting port
SPT0 = 1
SVA0 ← XXH
SPIE0 = 1
START
Slave operation
Slave operation
Releases the bus for a specific period.
Bus status is
being checked.
Yes
Checking bus status
Note
Master operation
starts?
Enables reserving
communication.
Disables reserving
communication.
SPD0 = 1?
STCEN = 1?
IICRSV = 0?
A
Sets the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 14.3 (7) Port mode register 6 (PM6)).
Selects a transfer clock.
Sets a local address.
Sets a start condition.
(Communication start request)
(No communication start request)
• Waiting to be specified as a slave by other master
• Waiting for a communication start request (depends on user program)
Prepares for starting
communication
(generates a stop condition).
Waits for detection
of the stop condition.
No
Yes
Yes
No
INTIIC0
interrupt occurs?
INTIIC0
interrupt occurs?
Yes
No Yes
No
SPD0 = 1?
Yes
No
Slave operation
No
INTIIC0
interrupt occurs?
Yes
No
1
B
SPIE0 = 0
Yes
No
Waits for a communication request.
Waits for a communication Initial setting
Setting port Sets the port from input mode to output mode and enables the output of the I
2
C bus
(see 14.3 (7) Port mode register 6 (PM6)).
IICC0 ← 1XX111XXB
IICE0 = 1
IICC0 ← 0XX111XXB
ACKE0 = WTIM0 = SPIE0 = 1
Note Confirm that the bus is released (CLD0 bit = 1, DAD0 bit = 1) for a specific period (for example, for a period
of one frame). If the SDA0 pin is constantly at low level, decide whether to release the I2C bus (SCL0 and
SDA0 pins = high level) in conformance with the specifications of the product that is communicating.
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Figure 14-25. Master Operation in Multi-Master System (2/3)
STT0 = 1
Wait
Slave operation
Yes
MSTS0 = 1?
EXC0 = 1 or COI0 =1?
Prepares for starting communication
(generates a start condition).
Secures wait time by software
(see Table 14-7).
Waits for bus release
(communication being reserved).
Wait state after stop condition
was detected and start condition
was generated by the communication
reservation function.
No
INTIIC0
interrupt occurs?
Yes
Yes
No
No
A
C
STT0 = 1
Wait
Slave operation
Yes
IICBSY = 0?
EXC0 = 1 or COI0 =1?
Prepares for starting communication
(generates a start condition).
Disables reserving communication.
Enables reserving communication.
Secures wait time by software
(see Table 14-7).
Waits for bus release
Detects a stop condition.
No
No
INTIIC0
interrupt occurs?
Yes
Yes
No
Yes
STCF = 0? No
B
D
C
D
Communication processing Communication processing
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Figure 14-25. Master Operation in Multi-Master System (3/3)
Writing IIC0
WTIM0 = 1
WREL0 = 1
Reading IIC0
ACKE0 = 1
WTIM0 = 0
WTIM0 = WREL0 = 1
ACKE0 = 0
Writing IIC0
Yes
TRC0 = 1?
Restart?
MSTS0 = 1?
Starts communication
(specifies an address and transfer direction).
Starts transmission.
No
Yes
Waits for data reception.
Starts reception.
Yes
No
INTIIC0
interrupt occurs?
Yes
No
Transfer end?
Waits for detection of ACK.
Yes
No
INTIIC0
interrupt occurs?
Waits for data transmission.
Does not participate
in communication.
Yes
No
INTIIC0
interrupt occurs?
No
Yes
ACKD0 = 1?
No
Yes
No
C
2
Yes
MSTS0 = 1? No
Yes
Transfer end?
No
Yes
ACKD0 = 1? No
2
Yes
MSTS0 = 1? No
2
Waits for detection of ACK.
Yes
No
INTIIC0
interrupt occurs?
Yes
MSTS0 = 1? No
C
2
Yes
EXC0 = 1 or COI0 = 1? No
1
2
SPT0 = 1
STT0 = 1
Slave operation
END
Communication processingCommunication processing
Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission
and reception formats.
2. To use the device as a master in a multi-master system, read the MSTS0 bit each time interrupt
INTIIC0 has occurred to check the arbitration result.
3. To use the device as a slave in a multi-master system, check the status by using the IICS0 and IICF0
registers each time interrupt INTIIC0 has occurred, and determine the processing to be performed
next.
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(3) Slave operation
The processing procedure of the slave operation is as follows.
Basically, the slave operation is event-driven. Therefore, processing by the INTIIC0 interrupt (processing that
must substantially change the operation status such as detection of a stop condition during communication) is
necessary.
In the following explanation, it is assumed that the extension code is not supported for data communication. It
is also assumed that the INTIIC0 interrupt servicing only performs status transition processing, and that actual
data communication is performed by the main processing.
IIC0
Interrupt servicing
Main processing
INTIIC0 Flag
Setting
Data
Setting
Therefore, data communication processing is performed by preparing the following three flags and passing
them to the main processing instead of INTIIC0.
<1> Communication mode flag
This flag indicates the following two communication statuses.
• Clear mode: Status in which data communication is not performed
• Communication mode: Status in which data communication is performed (from valid address detection
to stop condition detection, no detection of ACK from master, address
mismatch)
<2> Ready flag
This flag indicates that data communication is enabled. Its function is the same as the INTIIC0 interrupt
for ordinary data communication. This flag is set by interrupt servicing and cleared by the main
processing. Clear this flag by interrupt servicing when communication is started. However, the ready flag
is not set by interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted
without the flag being cleared (an address match is interpreted as a request for the next data).
<3> Communication direction flag
This flag indicates the direction of communication. Its value is the same as TRC0.
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The main processing of the slave operation is explained next.
Start serial interface IIC0 and wait until communication is enabled. When communication is enabled, execute
communication by using the communication mode flag and ready flag (processing of the stop condition and
start condition is performed by an interrupt. Here, check the status by using the flags).
The transmission operation is repeated until the master no longer returns ACK. If ACK is not returned from the
master, communication is completed.
For reception, the necessary amount of data is received. When communication is completed, ACK is not
returned as the next data. After that, the master generates a stop condition or restart condition. Exit from the
communication status occurs in this way.
Figure 14-26. Slave Operation Flowchart (1)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
WREL0 = 1
ACKD0 = 1?
No
Yes
No
Yes
No
START
Communication
mode flag = 1?
Communication
mode flag = 1?
Communication
direction flag = 1?
Ready flag = 1?
Communication
direction flag = 1?
Reading IIC0
Clearing ready flag
Clearing ready flag
Communication
direction flag = 1?
Clearing communication
mode flag
WREL0 = 1
Writing IIC0
SVA0 ← XXH Sets a local address.
IICX0 ← 0XH
IICCL0 ← XXH
Selects a transfer clock.
IICF0 ← 0XH
Setting IICRSV
Sets a start condition.
Starts
transmission.
Starts
reception.
Communication
mode flag = 1?
Ready flag = 1?
Setting port Sets the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 14.3 (7) Port mode register 6 (PM6)).
Communication processing Initial setting
Sets the port from input mode to output mode and enables the output of the I
2
C bus
(see 14.3 (7) Port mode register 6 (PM6)).
Setting port
IICC0 ← 0XX011XXB
ACKE = WTIM = 1, SPIE = 0
IICC0 ← 1XX011XXB
IICE = 1
Remark Conform to the specifications of the product that is in communication, regarding the transmission and
reception formats.
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An example of the processing procedure of the slave with the INTIIC0 interrupt is explained below (processing
is performed assuming that no extension code is used). The INTIIC0 interrupt checks the status, and the
following operations are performed.
<1> Communication is stopped if the stop condition is issued.
<2> If the start condition is issued, the address is checked and communication is completed if the address
does not match. If the address matches, the communication mode is set, wait is cancelled, and
processing returns from the interrupt (the ready flag is cleared).
<3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I2C bus
remaining in the wait state.
Remark <1> to <3> above correspond to <1> to <3> in Figure 14-27 Slave Operation Flowchart (2).
Figure 14-27. Slave Operation Flowchart (2)
Yes
Yes
Yes
No
No
No
INTIIC0 generated
Set ready flag
Interrupt servicing completed
SPD0 = 1?
STD0 = 1?
COI0 = 1?
Communication direction flag
← TRC0
Set communication mode flag
Clear ready flag
Clear communication direction
flag, ready flag, and
communication mode flag
<1>
<2>
<3>
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14.5.18 Timing of I2C interrupt request (INTIIC0) occurrence
The timing of transmitting or receiving data and generation of interrupt request signal INTIIC0, and the value of the
IICS0 register when the INTIIC0 signal is generated are shown below.
Remark ST: Start condition
AD6 to AD0: Address
R/W: Transfer direction specification
ACK: Acknowledge
D7 to D0: Data
SP: Stop condition
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(1) Master device operation
(a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception)
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
SPT0 = 1
↓
3 4 5 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B
3: IICS0 = 1000×000B (Sets WTIM0 to 1)Note
4: IICS0 = 1000××00B (Sets SPT0 to 1)Note
5: IICS0 = 00000001B
Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt
request signal.
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
SPT0 = 1
↓
3 4 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×100B
3: IICS0 = 1000××00B (Sets SPT0 to 1)
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart)
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
STT0 = 1
↓
SPT0 = 1
↓
3 4 7 2 1 5 6
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets WTIM0 to 1)Note 1
3: IICS0 = 1000××00B (Clears WTIM0 to 0Note 2, sets STT0 to 1)
4: IICS0 = 1000×110B
5: IICS0 = 1000×000B (Sets WTIM0 to 1)Note 3
6: IICS0 = 1000××00B (Sets SPT0 to 1)
7: IICS0 = 00000001B
Notes 1. To generate a start condition, set WTIM0 to 1 and change the timing for generating the INTIIC0
interrupt request signal.
2. Clear WTIM0 to 0 to restore the original setting.
3. To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0
interrupt request signal.
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
STT0 = 1
↓
SPT0 = 1
↓
3 4 5 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000××00B (Sets STT0 to 1)
3: IICS0 = 1000×110B
4: IICS0 = 1000××00B (Sets SPT0 to 1)
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission)
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
SPT0 = 1
↓
3 4 5 2 1
1: IICS0 = 1010×110B
2: IICS0 = 1010×000B
3: IICS0 = 1010×000B (Sets WTIM0 to 1)Note
4: IICS0 = 1010××00B (Sets SPT0 to 1)
5: IICS0 = 00000001B
Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt
request signal.
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
SPT0 = 1
↓
3 4 2 1
1: IICS0 = 1010×110B
2: IICS0 = 1010×100B
3: IICS0 = 1010××00B (Sets SPT0 to 1)
4: IICS0 = 00001001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(2) Slave device operation (slave address data reception)
(a) Start ~ Address ~ Data ~ Data ~ Stop
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001×000B
3: IICS0 = 0001×000B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001×100B
3: IICS0 = 0001××00B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, matches with SVA0)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001×000B
3: IICS0 = 0001×110B
4: IICS0 = 0001×000B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1 (after restart, matches with SVA0)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001××00B
3: IICS0 = 0001×110B
4: IICS0 = 0001××00B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, does not match address (= extension code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001×000B
3: IICS0 = 0010×010B
4: IICS0 = 0010×000B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1 (after restart, does not match address (= extension code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 5 6 2 1 4
1: IICS0 = 0001×110B
2: IICS0 = 0001××00B
3: IICS0 = 0010×010B
4: IICS0 = 0010×110B
5: IICS0 = 0010××00B
6: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, does not match address (= not extension code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001×000B
3: IICS0 = 00000110B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1 (after restart, does not match address (= not extension code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001××00B
3: IICS0 = 00000110B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(3) Slave device operation (when receiving extension code)
The device is always participating in communication when it receives an extension code.
(a) Start ~ Code ~ Data ~ Data ~ Stop
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0010×010B
2: IICS0 = 0010×000B
3: IICS0 = 0010×000B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 5 2 1
1: IICS0 = 0010×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010×100B
4: IICS0 = 0010××00B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, matches SVA0)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 0010×010B
2: IICS0 = 0010×000B
3: IICS0 = 0001×110B
4: IICS0 = 0001×000B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1 (after restart, matches SVA0)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 6 2 1 5
1: IICS0 = 0010×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010××00B
4: IICS0 = 0001×110B
5: IICS0 = 0001××00B
6: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, extension code reception)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 0010×010B
2: IICS0 = 0010×000B
3: IICS0 = 0010×010B
4: IICS0 = 0010×000B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1 (after restart, extension code reception)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 7 2 1 5 6
1: IICS0 = 0010×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010××00B
4: IICS0 = 0010×010B
5: IICS0 = 0010×110B
6: IICS0 = 0010××00B
7: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, does not match address (= not extension code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 2 1
1: IICS0 = 00100010B
2: IICS0 = 00100000B
3: IICS0 = 00000110B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1 (after restart, does not match address (= not extension code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 00100010B
2: IICS0 = 00100110B
3: IICS0 = 00100×00B
4: IICS0 = 00000110B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(4) Operation without communication
(a) Start ~ Code ~ Data ~ Data ~ Stop
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
1
1: IICS0 = 00000001B
Remark : Generated only when SPIE0 = 1
(5) Arbitration loss operation (operation as slave after arbitration loss)
When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request
signal INTIIC0 has occurred to check the arbitration result.
(a) When arbitration loss occurs during transmission of slave address data
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0101×110B
2: IICS0 = 0001×000B
3: IICS0 = 0001×000B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0101×110B
2: IICS0 = 0001×100B
3: IICS0 = 0001××00B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(b) When arbitration loss occurs during transmission of extension code
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0110×010B
2: IICS0 = 0010×000B
3: IICS0 = 0010×000B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 5 2 1
1: IICS0 = 0110×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010×100B
4: IICS0 = 0010××00B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(6) Operation when arbitration loss occurs (no communication after arbitration loss)
When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request
signal INTIIC0 has occurred to check the arbitration result.
(a) When arbitration loss occurs during transmission of slave address data (when WTIM0 = 1)
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
2 1
1: IICS0 = 01000110B
2: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
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(b) When arbitration loss occurs during transmission of extension code
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
2 1
1: IICS0 = 0110×010B
Sets LREL0 = 1 by software
2: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(c) When arbitration loss occurs during transmission of data
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 2 1
1: IICS0 = 10001110B
2: IICS0 = 01000000B
3: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
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(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 2 1
1: IICS0 = 10001110B
2: IICS0 = 01000100B
3: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
(d) When loss occurs due to restart condition during data transfer
(i) Not extension code (Example: does not match with SVA0)
ST AD6 to AD0 R/W ACK D7 to Dn AD6 to AD0 ACK SPST R/W D7 to D0 ACK
3 2 1
1: IICS0 = 1000×110B
2: IICS0 = 01000110B
3: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
n = 6 to 0
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(ii) Extension code
ST AD6 to AD0 R/W ACK D7 to Dn AD6 to AD0 ACK SPST R/W D7 to D0 ACK
3 2 1
1: IICS0 = 1000×110B
2: IICS0 = 01100010B
Sets LREL0 = 1 by software
3: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
n = 6 to 0
(e) When loss occurs due to stop condition during data transfer
ST AD6 to AD0 R/W ACK D7 to Dn SP
2 1
1: IICS0 = 10000110B
2: IICS0 = 01000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
n = 6 to 0
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(f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK SPACK D7 to D0 ACK
STT0 = 1
↓
3 4 5 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets WTIM0 to 1)
3: IICS0 = 1000×100B (Clears WTIM0 to 0)
4: IICS0 = 01000000B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK SPACK D7 to D0 ACK
STT0 = 1
↓
3 4 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×100B (Sets STT0 to 1)
3: IICS0 = 01000100B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(g) When arbitration loss occurs due to a stop condition when attempting to generate a restart
condition
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 ACK SP
STT0 = 1
↓
3 4 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets WTIM0 to 1)
3: IICS0 = 1000××00B (Sets STT0 to 1)
4: IICS0 = 01000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 ACK SP
STT0 = 1
↓
2 3 1
1: IICS0 = 1000×110B
2: IICS0 = 1000××00B (Sets STT0 to 1)
3: IICS0 = 01000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK SPACK D7 to D0 ACK
SPT0 = 1
↓
3 4 5 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets WTIM0 to 1)
3: IICS0 = 1000×100B (Clears WTIM0 to 0)
4: IICS0 = 01000100B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK SPACK D7 to D0 ACK
SPT0 = 1
↓
3 4 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×100B (Sets SPT0 to 1)
3: IICS0 = 01000100B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 14 SERIAL INTERFACE IIC0
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14.6 Timing Charts
When using the I2C bus mode, the master device outputs an address via the serial bus to select one of several
slave devices as its communication partner.
After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of IIC status register 0 (IICS0)),
which specifies the data transfer direction, and then starts serial communication with the slave device.
Figures 14-28 and 14-29 show timing charts of the data communication.
The shift operation of IIC shift register 0 (IIC0) is synchronized with the falling edge of the serial clock (SCL0). The
transmit data is transferred to the SO0 latch and is output (MSB first) via the SDA0 pin.
Data input via the SDA0 pin is captured into IIC0 at the rising edge of SCL0.
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Figure 14-28. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) (1/3)
(1) Start condition ~ address
IIC0
ACKD0
STD0
SPD0
WTIM0
H
H
L
L
L
L
H
H
L
L
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
SCL0
SDA0
Processing by master device
Transfer lines
Processing by slave device
123456789 4321
AD6 AD5 AD4 AD3 AD2 AD1 AD0 W ACK D4D5D6D7
IIC0 ← address IIC0 ← data Note 1
IIC0 ← FFH
Transmitting
Start condition
Receiving
Note 2
Note 2
Notes 1. Write data to IIC0, not setting WREL0, in order to cancel a wait state during master transmission.
2. To cancel a slave wait state, write “FFH” to IIC0 or set WREL0.
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Figure 14-28. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) (2/3)
(2) Data
IIC0
ACKD0
STD0
SPD0
WTIM0
H
H
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
SCL0
SDA0
Processing by master device
Transfer lines
198 23456789 321
D7D0 D6 D5 D4 D3 D2 D1 D0 D5D6D7
IIC0 ← data Note 1
IIC0 ← FFH Note 2 IIC0 ← FFH Note 2
IIC0 ← data Note 1
Receiving
Note 2 Note 2
ACKACK
Processing by slave device
Transmitting
Notes 1. Write data to IIC0, not setting WREL0, in order to cancel a wait state during master transmission.
2. To cancel a slave wait state, write “FFH” to IIC0 or set WREL0.
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Figure 14-28. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) (3/3)
(3) Stop condition
IIC0
ACKD0
STD0
SPD0
WTIM0
H
H
L
L
L
L
H
H
L
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
SCL0
SDA0
Processing by master device
Transfer lines
123456789 21
D7 D6 D5 D4 D3 D2 D1 D0 AD5AD6
IIC0 ← data Note 1 IIC0 ← address
IIC0 ← FFH Note 2 IIC0 ← FFH Note 2
Stop
condition
Start
condition
Note 2 Note 2
(When SPIE0 = 1)
Receiving
(When SPIE0 = 1)
ACK
Transmitting
Processing by slave device
Notes 1. Write data to IIC0, not setting WREL0, in order to cancel a wait state during master transmission.
2. To cancel a slave wait state, write “FFH” to IIC0 or set WREL0.
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Figure 14-29. Example of Slave to Master Communication
(When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3)
(1) Start condition ~ address
IIC0
ACKD0
STD0
SPD0
WTIM0
H
H
L
L
L
H
L
ACKE0
MSTS0
STT0
L
L
SPT0
WREL0
INTIIC0
TRC0
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
SCL0
SDA0
Processing by master device
Transfer lines
Processing by slave device
123456789 4 56321
AD6 AD5 AD4 AD3 AD2 AD1 AD0 D4 D3 D2D5D6D7
IIC0 ← address IIC0 ← FFH Note 1
Note 1
IIC0 ← data Note 2
Transmitting
Transmitting
Receiving
Receiving
ACK
R
Notes 1. To cancel a master wait state, write “FFH” to IIC0 or set WREL0.
2. Write data to IIC0, not setting WREL0, in order to cancel a wait state during slave transmission.
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Figure 14-29. Example of Slave to Master Communication
(When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3)
(2) Data
IIC0
ACKD0
STD0
SPD0
WTIM0
H
H
H
L
L
L
L
L
L
L
H
H
L
L
L
L
L
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
SCL0
SDA0
Processing by master device
Transfer lines
1
89 2345678 9 321
D7
D0 ACK D6 D5 D4 D3 D2 D1 D0 ACK D5D6D7
Note 1 Note 1
Receiving
Transmitting
IIC0 ← data Note 2 IIC0 ← data Note 2
IIC0 ← FFH Note 1 IIC0 ← FFH Note 1
Processing by slave device
Notes 1. To cancel a master wait state, write “FFH” to IIC0 or set WREL0.
2. Write data to IIC0, not setting WREL0, in order to cancel a wait state during slave transmission.
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Figure 14-29. Example of Slave to Master Communication
(When 8-Clock Wait Is Changed to 9-Clock Wait for Master, 9-Clock Wait Is Selected for Slave) (3/3)
(3) Stop condition
IIC0
ACKD0
STD0
SPD0
WTIM0
H
H
L
L
L
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
SCL0
SDA0
Processing by master device
Transfer lines
12345678 9 1
D7 D6 D5 D4 D3 D2 D1 D0 AD6
IIC0 ← address
IIC0 ← FFH Note 1
Note 1
Notes 1, 3
IIC0 ← data Note 2
Receiving
Transmitting Receiving
Stop
condition
Start
condition
(When SPIE0 = 1)
NACK
(When SPIE0 = 1)
Processing by slave device
IIC0 ← FFH Note 1
Note 3
Notes 1. To cancel a wait state, write “FFH” to IIC0 or set WREL0.
2. Write data to IIC0, not setting WREL0, in order to cancel a wait state during slave transmission.
3. If a wait state during slave transmission is canceled by setting WREL0, TRC0 will be cleared.
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CHAPTER 15 MULTIPLIER
15.1 Functions of Multiplier
The multiplier has the following functions.
• Can execute calculation of 16 bits × 16 bits = 32 bits.
Figure 15-1 shows the block diagram of the multiplier.
Figure 15-1. Block Diagram of Multiplier
Internal bus
Internal bus
Multiplication input data
register A (MULA)
Multiplication input data
register B (MULB)
32-bit multiplier
16-bit higher multiplication
result storage register (MULOH)
16-bit lower multiplication result
storage register (MULOL)
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15.2 Configuration of Multiplier
(1) 16-bit higher multiplication result storage register and 16-bit lower multiplication result storage
register (MULOH, MULOL)
These two registers, MULOH and MULOL, are used to store a 32-bit multiplication result. The higher 16 bits
of the multiplication result are stored in MULOH and the lower 16 bits, in MULOL, so that a total of 32 bits of
the multiplication result can be stored.
These registers hold the result of multiplication after the lapse of one CPU clock.
MULOH and MULOL can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears these registers to 0000H.
Figure 15-2. Format of 16-bit higher multiplication result storage register and 16-bit lower multiplication
result storage register (MULOH, MULOL)
Symbol
Address: FFFF4H, FFFF5H After reset: 0000H R
FFFF5H FFFF4H
MULOH
Symbol
Address: FFFF6H, FFFF7H After reset: 0000H R
FFFF7H FFFF6H
MULOL
(2) Multiplication input data registers A, B (MULA, MULB)
These are 16-bit registers that store data for multiplication. The multiplier multiplies the values of MULA and
MULB.
MULA and MULB can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears these registers to 0000H.
Figure 15-3. Format of Multiplication input data registers A, B (MULA, MULB)
Symbol
Address: FFFF0H, FFFF1H After reset: 0000H R/W
FFFF1H FFFF0H
MULA
Symbol
Address: FFFF2H, FFFF3H After reset: 0000H R/W
FFFF3H FFFF2H
MULB
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15.3 Operation of Multiplier
The result of the multiplication can be obtained by storing the values in the MULA and MULB registers and then
reading the MULOH and MULOL registers after waiting for 1 clock. The result can also be obtained after 1 clock or
more has elapsed, even when fixing either of MULA or MULB and rewrite the other of these. The result can be read
without problem, regardless of whether MULOH or MULOL is read in first.
A source example is shown below.
Example
MOVW MULA, #1234H
MOVW MULB, #5678H
NOP ; 1 clock wait. Doesn’t have to be NOP
MOVW AX, MULOH ; The result obtained on upper side
PUSH AX
MOVW AX, MULOL ; The result obtained on lower side
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CHAPTER 16 DMA CONTROLLER
The 78K0R/KG3 has an internal DMA (Direct Memory Access) controller.
Data can be automatically transferred between the peripheral hardware supporting DMA, SFRs, and internal RAM
without via CPU.
As a result, the normal internal operation of the CPU and data transfer can be executed in parallel with transfer
between the SFR and internal RAM, and therefore, a large capacity of data can be processed. In addition, real-time
control using communication, timer, and A/D can also be realized.
16.1 Functions of DMA Controller
{ Number of DMA channels: 2
{ Transfer unit: 8 or 16 bits
{ Maximum transfer unit: 1024 times
{ Transfer type: 2-cycle transfer (One transfer is processed in 2 clocks and the CPU stops during that
processing.)
{ Transfer mode: Single-transfer mode
{ Transfer request: Selectable from the following peripheral hardware interrupts
• A/D converter
• Serial interface (CIS00, CSI01, CSI10, UART0, UART1, UART3, or IIC10)
• Timer (channel 0, 1, 4, or 5)
{ Transfer target: Between SFR and internal RAM
Here are examples of functions using DMA.
• Successive transfer of serial interface
• Batch transfer of analog data
• Capturing A/D conversion result at fixed interval
• Capturing port value at fixed interval
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16.2 Configuration of DMA Controller
The DMA controller includes the following hardware.
Table 16-1. Configuration of DMA Controller
Item Configuration
Address registers • DMA SFR address registers 0, 1 (DSA0, DSA1)
• DMA RAM address registers 0, 1 (DRA0, DRA1)
Count register • DMA byte count registers 0, 1 (DBC0, DBC1)
Control registers • DMA mode control registers 0, 1 (DMC0, DMC1)
• DMA operation control register 0, 1 (DRC0, DRC1)
(1) DMA SFR address register n (DSAn)
This is an 8-bit register that is used to set an SFR address that is the transfer source or destination of DMA
channel n.
Set the lower 8 bits of the SFR addresses FFF00H to FFFFFHNote.
This register is not automatically incremented but fixed to a specific value.
In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address.
DSAn can be read or written in 8-bit units. However, it cannot be written during DMA transfer.
Reset signal generation clears this register to 00H.
Note Except for address FFFFEH because the PMC register is allocated there.
Figure 16-1. Format of DMA SFR Address Register n (DSAn)
Address: FFFB0H (DSA0), FFFB1H (DSA1) After reset: 00H R/W
7 6 5 4 3 2 1 0
DSAn
Remark n: DMA channel number (n = 0, 1)
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(2) DMA RAM address register n (DRAn)
This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA
channel n.
Addresses of the internal RAM area other than the general-purpose registers (FEF00H to FFEDFH in the
case of the
μ
PD78F1162 and 78F1162A) can be set to this register.
Set the lower 16 bits of the RAM address.
This register is automatically incremented when DMA transfer has been started. It is incremented by +1 in
the 8-bit transfer mode and by +2 in the 16-bit transfer mode. DMA transfer is started from the address set to
this DRAn register. When the data of the last address has been transferred, DRAn stops with the value of the
last address +1 in the 8-bit transfer mode, and the last address +2 in the 16-bit transfer mode.
In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address.
DRAn can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA transfer.
Reset signal generation clears this register to 0000H.
Figure 16-2. Format of DMA RAM Address Register n (DRAn)
Address: FFFB2H, FFFB3H (DRA0), FFFB4H, FFFB5H (DRA1) After reset: 0000H R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRAn
(n = 0, 1)
Remark n: DMA channel number (n = 0, 1)
DRA0H: FFFB3H
DRA1H: FFFB5H
DRA0L: FFFB2H
DRA1L: FFFB4H
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(3) DMA byte count register n (DBCn)
This is a 10-bit register that is used to set the number of times DMA channel n executes transfer. Be sure to
set the number of times of transfer to this DBCn register before executing DMA transfer (up to 1024 times).
Each time DMA transfer has been executed, this register is automatically decremented. By reading this
DBCn register during DMA transfer, the remaining number of times of transfer can be learned.
DBCn can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA transfer.
Reset signal generation clears this register to 0000H.
Figure 16-3. Format of DMA Byte Count Register n (DBCn)
Address: FFFB6H, FFFB7H (DBC0), FFFB8H, FFFB9H (DBC1) After reset: 0000H R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBCn 0 0 0 0 0 0
(n = 0, 1)
DBCn[9:0]
Number of Times of Transfer
(When DBCn is Written)
Remaining Number of Times of Transfer
(When DBCn is Read)
000H 1024 Completion of transfer or waiting for 1024 times of DMA transfer
001H 1 Waiting for remaining one time of DMA transfer
002H 2 Waiting for remaining two times of DMA transfer
003H 3 Waiting for remaining three times of DMA transfer
•
•
•
•
•
•
•
•
•
3FEH 1022 Waiting for remaining 1022 times of DMA transfer
3FFH 1023 Waiting for remaining 1023 times of DMA transfer
Cautions 1. Be sure to clear bits 15 to 10 to “0”.
2. If the general-purpose register is specified or the internal RAM space is exceeded as a
result of continuous transfer, the general-purpose register or SFR space are written or
read, resulting in loss of data in these spaces. Be sure to set the number of times of
transfer that is within the internal RAM space.
Remark n: DMA channel number (n = 0, 1)
DBC0H: FFFB7H
DBC1H: FFFB9H
DBC0L: FFFB6H
DBC1L: FFFB8H
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16.3 Registers Controlling DMA Controller
DMA controller is controlled by the following registers.
• DMA mode control register n (DMCn)
• DMA operation control register n (DRCn)
Remark n: DMA channel number (n = 0, 1)
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(1) DMA mode control register n (DMCn)
DMCn is a register that is used to set a transfer mode of DMA channel n. It is used to select a transfer
direction, data size, setting of pending, and start source. Bit 7 (STGn) is a software trigger that starts DMA.
Rewriting bits 6, 5, and 3 to 0 of DMCn is prohibited during operation (when DSTn = 1).
DMCn can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 16-4. Format of DMA Mode Control Register n (DMCn) (1/2)
Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H R/W
Symbol <7> <6> <5> <4> 3 2 1 0
DMCn STGn DRSn DSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0
STGnNote 1 DMA transfer start software trigger
0 No trigger operation
1 DMA transfer is started when DMA operation is enabled (DENn = 1).
DMA transfer is performed once by writing 1 to STGn when DMA operation is enabled (DENn = 1).
When this bit is read, 0 is always read.
DRSn Selection of DMA transfer direction
0 SFR to internal RAM
1 Internal RAM to SFR
DSn Specification of transfer data size for DMA transfer
0 8 bits
1 16 bits
DWAITn Note 2 Pending of DMA transfer
0 Executes DMA transfer upon DMA start request (not held pending).
1 Holds DMA start request pending if any.
DMA transfer that has been held pending can be started by clearing the value of DWAITn to 0.
It takes 2 clocks to actually hold DMA transfer pending when the value of DWAITn is set to 1.
Notes 1. The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 values.
2. When DMA transfer is held pending while using both DMA channels, be sure to hold the DMA
transfer pending for both channels (by setting DWAIT0 and DWAIT1 to 1).
Remark n: DMA channel number (n = 0, 1)
<R>
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Figure 16-4. Format of DMA Mode Control Register n (DMCn) (2/2)
Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H R/W
Symbol <7> <6> <5> <4> 3 2 1 0
DMCn STGn DRSn DSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0
Selection of DMA start sourceNote
IFCn
3
IFCn
2
IFCn
1
IFCn
0 Trigger signal Trigger contents
0 0 0 0 − Disables DMA transfer by interrupt.
(Only software trigger is enabled.)
0 0 1 0 INTTM00 End of timer channel 0 count or capture
end interrupt
0 0 1 1 INTTM01 End of timer channel 1 count or capture
end interrupt
0 1 0 0 INTTM04 End of timer channel 4 count or capture
end interrupt
0 1 0 1 INTTM05 End of timer channel 5 count or capture
end interrupt
0 1 1 0 INTST0/INTCSI00 UART0 transmission transfer end or
buffer empty interrupt/CSI00 transfer end
or buffer empty interrupt
0 1 1 1 INTSR0/INTCSI01 UART0 reception transfer end
interrupt/CSI01 transfer end or buffer
empty interrupt
1 0 0 0 INTST1/INTCSI10/INTIIC10 UART1 transmission transfer end or
buffer empty interrupt/CSI10 transfer end
or buffer empty interrupt/
IIC10 transfer end interrupt
1 0 0 1 INTSR1 UART1 reception transfer end interrupt
1 0 1 0 INTST3 UART3 transmission transfer end or
buffer empty interrupt
1 0 1 1 INTSR3 UART3 reception transfer end interrupt
1 1 0 0 INTAD A/D conversion end interrupt
Other than above Setting prohibited
Note The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 values.
Remark n: DMA channel number (n = 0, 1)
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(2) DMA operation control register n (DRCn)
DRCn is a register that is used to enable or disable transfer of DMA channel n.
Rewriting bit 7 (DENn) of this register is prohibited during operation (when DSTn = 1).
DRCn can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 16-5. Format of DMA Operation Control Register n (DRCn)
Address: FFFBCH (DRC0), FFFBDH (DRC1) After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 <0>
DRCn DENn 0 0 0 0 0 0 DSTn
DENn DMA operation enable flag
0 Disables operation of DMA channel n (stops operating cock of DMA).
1 Enables operation of DMA channel n.
DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1).
DSTn DMA transfer mode flag
0 DMA transfer of DMA channel n is completed.
1 DMA transfer of DMA channel n is not completed (still under execution).
DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1).
When a software trigger (STGn) or the start source trigger set by IFCn3 to IFCn0 is input, DMA transfer is started.
When DMA transfer is completed after that, this bit is automatically cleared to 0.
Write 0 to this bit to forcibly terminate DMA transfer under execution.
Caution The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is terminated
without waiting for generation of the interrupt (INTDMAn) of DMAn, therefore, set DSTn to 0
and then DENn to 0 (for details, refer to 16.5.7 Forcible termination by software).
Remark n: DMA channel number (n = 0, 1)
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16.4 Operation of DMA Controller
16.4.1 Operation procedure
<1> The DMA controller is enabled to operate when DENn = 1. Before writing the other registers, be sure to set
DENn to 1. Use 80H to write with an 8-bit manipulation instruction.
<2> Set an SFR address, a RAM address, the number of times of transfer, and a transfer mode of DMA transfer
to the DSAn, DRAn, CBCn, and DMCn registers.
<3> The DMA controller waits for a DMA trigger when DSTn = 1. Use 81H to write with an 8-bit manipulation
instruction.
<4> When a software trigger (STGn) or a start source trigger specified by IFCn3 to IFCn0 is input, a DMA transfer
is started.
<5> Transfer is completed when the number of times of transfer set by the DBCn register reaches 0, and transfer
is automatically terminated by occurrence of an interrupt (INTDMAn).
<6> Stop the operation of the DMA controller by clearing DENn to 0 when the DMA controller is not used.
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No
No
DSTn = 1
DSTn = 0
INTDMAn = 1
DMA trigger = 1?
DBCn = 0000H ?
Yes
Yes
DENn = 1
Setting DSAn, DRAn, DBCn, and DMCn
Transmitting DMA request
Receiving DMA acknowledge
DMA transfer
DRAn = DRAn + 1 (or + 2)
DBCn = DBCn − 1
DENn = 0
Set by software program
Operation by DMA
controller (hardware)
Set by software program
Figure 16-6. Operation Procedure
Remark n: DMA channel number (n = 0, 1)
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16.4.2 Transfer mode
The following four modes can be selected for DMA transfer by using bits 6 and 5 (DRSn and DSn) of the DMCn
register.
DRSn DSn DMA Transfer Mode
0 0 Transfer from SFR of 1-byte data (fixed address) to RAM (address is incremented by +1)
0 1 Transfer from SFR of 2-byte data (fixed address) to RAM (address is incremented by +2)
1 0 Transfer from RAM of 1-byte data (address is incremented by +1) to SFR (fixed address)
1 1 Transfer from RAM of 2-byte data (address is incremented by +2) to SFR (fixed address)
By using these transfer modes, up to 1024 bytes of data can be consecutively transferred by using the serial
interface, data resulting from A/D conversion can be consecutively transferred, and port data can be scanned at fixed
time intervals by using a timer.
16.4.3 Termination of DMA transfer
When DBCn = 00H and DMA transfer is completed, the DSTn bit is automatically cleared to 0. An interrupt request
(INTDMAn) is generated and transfer is terminated.
When the DSTn bit is cleared to 0 to forcibly terminate DMA transfer, the DBCn and DRAn registers hold the value
when transfer is terminated.
The interrupt request (INTDMAn) is not generated if transfer is forcibly terminated.
Remark n: DMA channel number (n = 0, 1)
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16.5 Example of Setting of DMA Controller
16.5.1 CSI consecutive transmission
A flowchart showing an example of setting for CSI consecutive transmission is shown below.
• Consecutive transmission (256 bytes) of CSI00
• DMA channel 0 is used for DMA transfer.
• DMA start source: INTCSI00 (software trigger (STG0) only for the first start source)
• Interrupt of CSI00 is specified by IFC03 to IFC00 (bits 3 to 0 of the DMC0 register) = 0110B.
• Transfers FF100H to FF1FFH (256 bytes) of RAM to FFF10H of the data register (SIO00) of CSI.
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Figure 16-7. Setting Example of CSI Consecutive Transmission
Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DEN0 flag is enabled only when DST0 = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMA0 (INTDMA0), set DST0 to 0 and then DEN0 to 0 (for details, refer to
16.5.7 Forcible termination by software).
The fist trigger for consecutive transmission is not started by the interrupt of CSI. In this example, it start by a
software trigger.
CSI transmission of the second time and onward is automatically executed.
A DMA interrupt (INTDMA0) occurs when the last transmit data has been written to the data register.
Setting for CSI transfer
DEN0 = 1
DSA0 = 10H
DRA0 = F100H
DBC0 = 0100H
DMC0 = 46H
DEN0 = 0
DST0 = 1
STG0 = 1
Start
DMA is started.
INTCSI00 occurs.
RETI
End
User program
processing
Occurrence of
INTDMA0
DST0 = 0Note
DMA0 transfer
CSI
transmission
Hardware operation
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16.5.2 CSI master reception
A flowchart showing an example of setting for CSI master reception is shown below.
• Master reception (256 bytes) of CSI00
• DMA channel 0 is used to read received data and DMA channel 1 is used to write dummy data.
• DMA start source: INTCSI00
(If the same start source is specified for DMA channels 0 and 1, the data of channel 0 is transferred, and then
that of channel 1.)
• Interrupt of CSI00 is specified by IFC03 to IFC00 = IFC13 to IFC10 (bits 3 to 0 of the DMCn register) = 0110B.
• Data is transferred (received) from FFF10H of the CSI data register (SIO00) to FF100H to FF1FFH of RAM (256
bytes). (In successive reception mode, the data that is to be received when the first buffer empty interrupt occurs
is invalid because the data has not been received.)
• Transfers dummy data FF101H to FF1FFH (255 bytes) of RAM to FFF10H of the data register (SIO00) of CSI.
(Dummy data is written to the first byte by using software (an instruction).)
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Figure 16-8. Setting Example of CSI Master Reception
Note The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMAn (INTDMAn), set DSTn to 0 and then DENn to 0 (for details, refer to
16.5.7 Forcible termination by software).
Because no CSI interrupt is generated when reception starts during CSI master reception, dummy data is written
using software in this example.
The received data is automatically transferred from the first byte. (In successive reception mode, the data that is to
be received when the first buffer empty interrupt occurs is invalid because the valid data has not been received.)
A DMA interrupt (INTDMA1) occurs when the last dummy data has been writing to the data register. A DMA
interrupt (INTDMA0) occurs when the last received data has been read from the data register. To restart the DMA
transfer, the CSI transfer must be completed.
Setting for CSI transfer
DEN0 = 1
DEN1 = 1
DSA0 = 10H
DRA0 = F100H
DBC0 = 0100H
DMC0 = 06H
DEN0 = 0
DST0 = 1
DST1 = 1
Start
RETI
End
User program
processing
DST0 = 0 Note DMA0 transfer CSI reception
DMA1 transfer Writing dummy data
Hardware operation
DSA1 = 10H
DRA1 = F101H
DBC1 = 00FFH
DMC1 = 46H
INTCSI00 occurs.
DST1 = 0 Note
DEN1 = 0
RETI
Write dummy data to
SIO00 (= SDR00 [7:0])
INTDMA1 occurs. INTDMA0 occurs.
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16.5.3 CSI transmission/reception
A flowchart showing an example of setting for CSI transmission/reception is shown below.
• Transmission/reception (256 bytes) of CSI00
• DMA channel 0 is used to read received data and DMA channel 1 is used to write transmit data.
• DMA start source: INTCSI00
(If the same start source is specified for DMA channels 0 and 1, the data of channel 0 is transferred, and then
that of channel 1)
• Interrupt of CSI00 is specified by IFC03 to IFC00 = IFC13 to IFC10 (bits 3 to 0 of the DMCn register) = 0110B.
• Data is transferred (received) from FFF10H of the CSI data register (SIO00) to FF100H to FF1FFH of RAM (256
bytes). (In successive transmission/reception mode, the data that is to be received when the first buffer empty
interrupt occurs is invalid because the data has not been received.)
• Transfers FF201H to FF2FFH (255 bytes) of RAM to FFF10H of the data register (SIO00) of CSI (transmission)
(Transmit data is written to the first byte by using software (an instruction).)
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Figure 16-9. Setting Example of CSI Transmission/reception
Note The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMAn (INTDMAn), set DSTn to 0 and then DENn to 0 (for details, refer to
16.5.7 Forcible termination by software).
During CSI transfers, no CSI interrupt is generated when the transmitted data of the first byte is written. Therefore,
the transmitted data is written using software in this example. The data of the second and following bytes is
automatically transmitted.
The received data is automatically transferred from the first byte. (In successive transmission/reception, the data
that is to be received when the first buffer empty interrupt occurs is invalid because the valid data has not been
received.)
A DMA interrupt (INTDMA1) occurs when the last transmit data has been writing to the data register. A DMA
interrupt (INTDMA0) occurs when the last received data has been read from the data register. To restart the DMA
transfer, the CSI transfer must be completed.
Setting for CSI transfer
DEN0 = 1
DEN1 = 1
DSA0 = 10H
DRA0 = F100H
DBC0 = 0100H
DMC0 = 06H
DEN0 = 0
DST0 = 1
DST1 = 1
Start
RETI
End
User program
processing
DST0 = 0 Note DMA0 transfer CSI reception
DMA1 transfer CSI transmission
Hardware operation
DSA1 = 10H
DRA1 = F201H
DBC1 = 00FFH
DMC1 = 46H
INTCSI00 occurs.
DST1 = 0 Note
DEN1 = 0
RETI
Write transmit data to
SIO00 (= SDR00 [7:0])
INTDMA1 occurs. INTDMA0 occurs.
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16.5.4 Consecutive capturing of A/D conversion results
A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below.
• Consecutive capturing of A/D conversion results.
• DMA channel 1 is used for DMA transfer.
• DMA start source: INTAD
• Interrupt of A/D is specified by IFC13 to IFC10 (bits 3 to 0 of the DMC1 register) = 1100B.
• Transfers FFF1EH and FFF1FH (2 bytes) of the 10-bit A/D conversion result register to 2048 bytes of FF380H to
FFB7FH of RAM.
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Figure 16-10. Setting Example of Consecutively Capturing A/D Conversion Results
Note The DST1 flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DEN1 flag is enabled only when DST1 = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMA1 (INTDMA1), set DST1 to 0 and then DEN1 to 0 (for details, refer to
16.5.7 Forcible termination by software).
Hardware operation
DEN1 = 1
DSA1 = 1EH
DRA1 = F380H
DBC1 = 0000H
DMC1 = 2CH
DST1 = 1
Starting A/D conversion
DEN1 = 0
RETI
End
INTDMA1 occurs.
DST1 = 0Note
INTAD occurs.
DMA1 transfer
Start
User program
processing
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16.5.5 UART consecutive reception + ACK transmission
A flowchart illustrating an example of setting for UART consecutive reception + ACK transmission is shown below.
• Consecutively receives data from UART0 and outputs ACK to P10 on completion of reception.
• DMA channel 0 is used for DMA transfer.
• DMA start source: Software trigger (DMA transfer on occurrence of an interrupt is disabled.)
• Transfers FFF12H of UART receive data register 0 (RXD0) to 64 bytes of FFE00H to FFE3FH of RAM.
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DEN0 = 1
DSA0 = 12H
DRA0 = FE00H
DBC0 = 0040H
DMC0 = 00H
DEN0 = 0Note
Setting for UART reception
DST0 = 1
User program
processing
STG0 = 1
P10 = 1
P10 = 0
INTSR0 occurs.
INTDMA0
occurs.
DST0 = 0
DMA0 transfer
RETI
Hardware operation
Start
End
RETI
INTSR0 interrupt routine
Figure 16-11. Setting Example of UART Consecutive Reception + ACK Transmission
Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DEN0 flag is enabled only when DST0 = 0. To terminate a DMA transfer without waiting for
occurrence of the interrupt of DMA0 (INTDMA0), set DST0 to 0 and then DEN0 to 0 (for details, refer to
16.5.7 Forcible termination by software).
Remark This is an example where a software trigger is used as a DMA start source.
If ACK is not transmitted and if only data is consecutively received from UART, the UART reception
end interrupt (INTSR0) can be used to start DMA for data reception.
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Starting DMA transfer
DWAITn = 0
DWAITn = 1
Wait for 2 clocks
P10 = 1
Wait for 9 clocks
P10 = 0
Main program
16.5.6 Holding DMA transfer pending by DWAITn
When DMA transfer is started, transfer is performed while an instruction is executed. At this time, the operation of
the CPU is stopped and delayed for the duration of 2 clocks. If this poses a problem to the operation of the set
system, a DMA transfer can be held pending by setting DWAITn to 1. The DMA transfer for a transfer trigger that
occurred while DMA transfer was held pending is executed after the pending status is canceled. However, because
only one transfer trigger can be held pending for each channel, even if multiple transfer triggers occur for one channel
during the pending status, only one DMA transfer is executed after the pending status is canceled.
To output a pulse with a width of 10 clocks of the operating frequency from the P00 pin, for example, the clock
width increases to 12 if a DMA transfer is started midway. In this case, the DMA transfer can be held pending by
setting DWAITn to 1.
After setting DWAITn to 1, it takes two clocks until a DMA transfer is held pending.
Figure 16-12. Example of Setting for Holding DMA Transfer Pending by DWAITn
Caution When DMA transfer is held pending while using both DMA channels, be sure to hold the DMA
transfer pending for both channels (by setting DWAIT0 and DWAIT1 to 1). If the DMA transfer
of one channel is executed while that of the other channel is held pending, DMA transfer might
not be held pending for the latter channel.
Remarks 1. n: DMA channel number (n = 0, 1)
2. 1 clock: 1/fCLK (fCLK: CPU clock)
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DSTn = 0
DENn = 0
DSTn = 0 ? No 2 clock wait
Yes
DSTn = 0
DENn = 0
16.5.7 Forced termination by software
After DSTn is set to 0 by software, it takes up to 2 clocks until a DMA transfer is actually stopped and DSTn is set
to 0. To forcibly terminate a DMA transfer by software without waiting for occurrence of the interrupt (INTDMAn) of
DMAn, therefore, perform either of the following processes.
<When using one DMA channel>
• Set DSTn to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software, confirm by polling
that DSTn has actually been cleared to 0, and then set DENn to 0 (use DRCn = 00H to write with an 8-bit
manipulation instruction).
• Set DSTn to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software and then set DENn
to 0 (use DRCn = 00H to write with an 8-bit manipulation instruction) two or more clocks after.
<When using both DMA channels>
• To forcibly terminate DMA transfer by software when using both DMA channels (by setting DSTn to 0), clear the
DSTn bit to 0 after the DMA transfer is held pending by setting the DWAIT0 and DWAIT1 bits of both channels to
1. Next, clear the DWAIT0 and DWAIT1 bits of both channels to 0 to cancel the pending status, and then clear
the DENn bit to 0.
Figure 16-13. Forced Termination of DMA Transfer (1/2)
Example 1 Example 2
Remarks 1. n: DMA channel number (n = 0, 1)
2. 1 clock: 1/fCLK (fCLK: CPU clock)
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Figure 16-13. Forced Termination of DMA Transfer (2/2)
Example 3
• Procedure for forcibly terminating the DMA • Procedure for forcibly terminating the DMA
transfer for one channel if both channels are used transfer for both channels if both channels are used
DWAIT0 = 1
DWAIT1 = 1
DSTn = 0
DWAIT0 = 0
DWAIT1 = 0
DENn = 0
DWAIT0 = 1
DWAIT1 = 1
DST0 = 0
DST1 = 0
DWAIT0 = 0
DWAIT1 = 0
DEN0 = 0
DEN1 = 0
Caution In example 3, the system is not required to wait two clock cycles after DWAITn is set to 1. In
addition, the system does not have to wait two clock cycles after clearing DSTn to 0, because
more than two clock cycles elapse from when DSTn is cleared to 0 to when DENn is cleared to
0.
Remarks 1. n: DMA channel number (n = 0, 1)
2. 1 clock: 1/fCLK (fCLK: CPU clock)
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16.6 Cautions on Using DMA Controller
(1) Priority of DMA
During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending
DMA transfer is started after the ongoing DMA transfer is completed. If two DMA requests are generated at
the same time, however, DMA channel 0 takes priority over DMA channel 1.
If a DMA request and an interrupt request are generated at the same time, the DMA transfer takes
precedence, and then interrupt servicing is executed.
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(2) DMA response time
The response time of DMA transfer is as follows.
Table 16-2. Response Time of DMA Transfer
Minimum Time Maximum Time
Response time Note 3 clocks 10 clocks
Note This is the time required to execute an instruction from internal ROM (without accessing data in
external memory). However, DMA transfers might be further delayed in the cases below. The
number of clock cycles by which transfers are delayed varies depending on the condition.
Condition Maximum Response Time
Executing an
instruction from
internal ROM
When external memory
data is accessed
8 + (3 × (external wait + internal wait)) clocks
When external memory
data is not accessed
16 clocks Executing an
instruction from
internal RAM When external memory
data is accessed
16 + (3 × (external wait + internal wait)) clocks
Executing an instruction from
external memory
16 + (12 × (external wait + internal wait)) clocks
Cautions 1. The above response time does not include the two clock cycles required for a
DMA transfer.
2. When executing a DMA pending instruction (see 16.6 (4)), the maximum
response time is extended by the execution time of that instruction to be held
pending.
3. Do not specify successive transfer triggers for a channel within a period equal
to the maximum response time plus one clock cycle, because they might be
ignored.
Remarks 1. Internal Wait : Number of clock cycles the system waits according to the clock
selected for the CLKOUT pin of the external bus interface
CLKOUT Pin Selection
Clock
Number of Wait States
fCLK 3 clocks
fCLK/2 5 to 6 clocks
fCLK/3 7 to 9 clocks
fCLK/4 9 to 12 clocks
2. External wait: Low level period of the WAIT pin of the external bus interface (in 1/fCLK
units). For details, see 5.6 Number of Instruction Wait Clocks for
External Wait Pin.
3. 1 clock: 1/fCLK (fCLK: CPU clock)
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(3) Operation in standby mode
The DMA controller operates as follows in the standby mode.
Table 16-3. DMA Operation in Standby Mode
Status DMA Operation
HALT mode Normal operation
STOP mode Stops operation.
If DMA transfer and STOP instruction execution contend, DMA transfer may be
damaged. Therefore, stop DMA before executing the STOP instruction.
(4) DMA pending instruction
Even if a DMA request is generated, DMA transfer is held pending immediately after the following instructions.
• CALL !addr16
• CALL $!addr20
• CALL !!addr20
• CALL rp
• CALLT [addr5]
• BRK
• Bit manipulation instructions for registers IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, MK0L, MK0H, MK1L, MK1H,
MK2L, MK2H, PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L,
PR12H and PSW each.
(5) Operation if address in general-purpose register area or other than those of internal RAM area is
specified
The address indicated by DRA0n is incremented during DMA transfer. If the address is incremented to an
address in the general-purpose register area or exceeds the area of the internal RAM, the following operation
is performed.
z In mode of transfer from SFR to RAM
The data of that address is lost.
z In mode of transfer from RAM to SFR
Undefined data is transferred to SFR.
In either case, malfunctioning may occur or damage may be done to the system. Therefore, make sure that
the address is within the internal RAM area other than the general-purpose register area.
Internal RAM
General-purpose registers
DMA transfer enabled area
FFF00H
FFEFFH
FFEE0H
FFEDFH
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CHAPTER 17 INTERRUPT FUNCTIONS
17.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Maskable interrupts
These interrupts undergo mask control. Maskable interrupts can be divided into four priority groups by setting the
priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,
PR11H, PR12L, PR12H).
Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If
two or more interrupt requests, each having the same priority, are simultaneously generated, then they are
processed according to the priority of vectored interrupt servicing. For the priority order, see Table 17-1.
A standby release signal is generated and STOP and HALT modes are released.
External interrupt requests and internal interrupt requests are provided as maskable interrupts.
External: 13, internal: 28
(2) Software interrupt
This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts
are disabled. The software interrupt does not undergo interrupt priority control.
17.2 Interrupt Sources and Configuration
The 78K0R/KG3 has a total of 42 interrupt sources including maskable interrupts and software interrupts. In
addition, they also have up to five reset sources (see Table 17-1). The vector codes that store the program start
address when branching due to the generation of a reset or various interrupt requests are two bytes each, so
interrupts jump to a 64 K address of 00000H to 0FFFFH.
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Table 17-1. Interrupt Source List (1/2)
Interrupt Source
Interrupt
Type
Default
PriorityNote 1 Name Trigger
Internal/
External
Vector
Table
Address
Basic
Configuration
TypeNote 2
0 INTWDTI
Watchdog timer intervalNote 3
(75% of overflow time)
0004H
1 INTLVI Low-voltage detectionNote 4
Internal
0006H
(A)
2 INTP0 0008H
3 INTP1 000AH
4 INTP2 000CH
5 INTP3 000EH
6 INTP4 0010H
7 INTP5
Pin input edge detection External
0012H
(B)
8 INTST3
UART3 transmission transfer end or buffer
empty interrupt
0014H
9 INTSR3 UART3 reception transfer end 0016H
10 INTSRE3
UART3 reception communication error
occurrence
0018H
11 INTDMA0 End of DMA0 transfer 001AH
12 INTDMA1 End of DMA1 transfer 001CH
13 INTST0
/INTCSI00
UART0 transmission transfer end or buffer
empty interrupt/CSI00 transfer end or buffer
empty interrupt
001EH
14 INTSR0
/INTCSI01
UART0 reception transfer end/
CSI01 transfer end or buffer empty interrupt
0020H
15 INTSRE0
UART0 reception communication error
occurrence
0022H
16 INTST1
/INTCSI10
/INTIIC10
UART1 transmission transfer end or buffer
empty interrupt/
CSI10 transfer end or buffer empty interrupt/
IIC10 transfer end
0024H
17 INTSR1 UART1 reception transfer end 0026H
18 INTSRE1
UART1
reception communication error
occurrence
0028H
19 INTIIC0 End of IIC0 communication 002AH
20 INTTM00 End of timer channel 0 count or capture 002CH
21 INTTM01 End of timer channel 1 count or capture 002EH
22 INTTM02 End of timer channel 2 count or capture 0030H
Maskable
23 INTTM03 End of timer channel 3 count or capture
Internal
0032H
(A)
Notes 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 40 indicates the lowest priority.
2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 17-1.
3. When bit 7 (WDTINT) of the option byte (000C0H) is set to 1.
4. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0.
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Table 17-1. Interrupt Source List (2/2)
Interrupt Source
Interrupt
Type
Default
PriorityNote 1 Name Trigger
Internal/
External
Vector
Table
Address
Basic
Configuration
TypeNote 2
24 INTAD End of A/D conversion 0034H
25 INTRTC
Fixed-cycle signal of real-time counter/alarm
match detection
0036H
26 INTRTCI Interval signal detection of real-time counter
Internal
0038H
(A)
27 INTKR Key return signal detection External 003AH (C)
28 INTST2
/INTCSI20
/INTIIC20
UART2 transmission transfer end or buffer
empty interrupt/CSI20 transfer end or buffer
empty interrupt/IIC20 transfer end
003CH
29 INTSR2 UART2 reception transfer end 003EH
30 INTSRE2
UART2 reception communication error
occurrence
0040H
31 INTTM04 End of timer channel 4 count or capture 0042H
32 INTTM05 End of timer channel 5 count or capture 0044H
33 INTTM06 End of timer channel 6 count or capture 0046H
34 INTTM07 End of timer channel 7 count or capture
Internal
0048H
(A)
35 INTP6 004AH
36 INTP7 004CH
37 INTP8 004EH
38 INTP9 0050H
39 INTP10 0052H
Maskable
40 INTP11
Pin input edge detection External
0054H
(B)
Software − BRK Execution of BRK instruction − 007EH (D)
RESET RESET pin input
POC Power-on-clear
LVI Low-voltage detectionNote 3
WDT Overflow of watchdog timer
Reset −
TRAP Execution of illegal instructionNote 4
− 0000H −
Notes 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 40 indicates the lowest priority.
2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 17-1.
3. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 1.
4. When the instruction code in FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
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Figure 17-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal maskable interrupt
IF
MK IE PR1 ISP1
PR0 ISP0
Internal bus
Interrupt
request Priority controller
Vector table
address generator
Standby release
signal
(B) External maskable interrupt (INTPn)
IF
MK IE PR1 ISP1
PR0 ISP0
Internal bus
External interrupt edge
enable register
(EGP, EGN)
INTPn pin
input
Edge
detector
Priority controller
Vector table
address generator
Standby release
signal
Remarks 1. IF: Interrupt request flag
IE: Interrupt enable flag
ISP0: In-service priority flag 0
ISP1: In-service priority flag 1
MK: Interrupt mask flag
PR0: Priority specification flag 0
PR1: Priority specification flag 1
2. n = 0 to 11
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Figure 17-1. Basic Configuration of Interrupt Function (2/2)
(C) External maskable interrupt (INTKR)
IF
MK IE PR1 ISP1
PR0 ISP0
Internal bus
Key return mode
register
(KRM)
Priority controller
Vector table
address generator
Standby release
signal
Key Interrupt
detector
KRMm
KRm pin
input
(D) Software interrupt
Vector table
address generator
Internal bus
Interrupt
request
Remarks 1. IF: Interrupt request flag
IE: Interrupt enable flag
ISP0: In-service priority flag 0
ISP1: In-service priority flag 1
MK: Interrupt mask flag
PR0: Priority specification flag 0
PR1: Priority specification flag 1
2. m = 0 to 7
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17.3 Registers Controlling Interrupt Functions
The following 6 types of registers are used to control the interrupt functions.
• Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)
• Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)
• Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,
PR11H, PR12L, PR12H)
• External interrupt rising edge enable registers (EGP0, EGP1)
• External interrupt falling edge enable registers (EGN0, EGN1)
• Program status word (PSW)
Table 17-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding
to interrupt request sources.
Table 17-2. Flags Corresponding to Interrupt Request Sources (1/2)
Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Interrupt
Source Register Register Register
INTWDTI WDTIIF WDTIMK WDTIPR0, WDTIPR1
INTLVI LVIIF LVIMK LVIPR0, LVIPR1
INTP0 PIF0 PMK0 PPR00, PPR10
INTP1 PIF1 PMK1 PPR01, PPR11
INTP2 PIF2 PMK2 PPR02, PPR12
INTP3 PIF3 PMK3 PPR03, PPR13
INTP4 PIF4 PMK4 PPR04, PPR14
INTP5 PIF5
IF0L
PMK5
MK0L
PPR05, PPR15
PR00L,
PR10L
INTST3 STIF3 STMK3 STPR03, STPR13
INTSR3 SRIF3 SRMK3 SRPR03, SRPR13
INTSRE3 SREIF3 SREMK3 SREPR03, SREPR13
INTDMA0 DMAIF0 DMAMK0 DMAPR00, DMAPR10
INTDMA1 DMAIF1 DMAMK1 DMAPR01, DMAPR11
INTST0Note 1 STIF0Note 1 STMK0Note 1 STPR00, STPR10Note 1
INTCSI00Note 1 CSIIF00Note 1 CSIMK00Note 1 CSIPR000, CSIPR100Note 1
INTSR0Note 2 SRIF0Note 2 SRMK0Note 2 SRPR00, SRPR10Note 2
INTCSI01Note 2 CSIIF01Note 2 CSIMK01Note 2 CSIPR001, CSIPR101Note 2
INTSRE0 SREIF0
IF0H
SREMK0
MK0H
SREPR00, SREPR10
PR00H,
PR10H
Notes 1. Do not use UART0 and CSI00 at the same time because they share flags for the interrupt request
sources. If one of the interrupt sources INTST0 and INTCSI00 is generated, bit 5 of IF1H is set to 1. Bit
5 of MK0H, PR00H, and PR10H supports these three interrupt sources.
2. Do not use UART0 and CSI01 at the same time because they share flags for the interrupt request
sources. If one of the interrupt sources INTSR0 and INTCSI01 is generated, bit 6 of IF0H is set to 1. Bit
6 of MK0H, PR00H, and PR10H supports these three interrupt sources.
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Table 17-2. Flags Corresponding to Interrupt Request Sources (2/2)
Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag
Interrupt
Source Register Register Register
INTST1Note 1 STIF1Note 1 STMK1Note 1 STPR01, STPR11Note 1
INTCSI10Note 1 CSIIF10Note 1 CSIMK10Note 1 CSIPR010, CSIPR110Note 1
INTIIC10Note 1 IICIF10Note 1 IICMK10Note 1 IICPR010, IICPR110Note 1
INTSR1 SRIF1 SRMK1 SRPR01, SRPR11
INTSRE1 SREIF1 SREMK1 SREPR01, SREPR11
INTIIC0 IICIF0 IICMK0 IICPR00, IICPR10
INTTM00 TMIF00 TMMK00 TMPR000, TMPR100
INTTM01 TMIF01 TMMK01 TMPR001, TMPR101
INTTM02 TMIF02 TMMK02 TMPR002, TMPR102
INTTM03 TMIF03
IF1L
TMMK03
MK1L
TMPR003, TMPR103
PR01L,
PR11L
INTAD ADIF ADMK ADPR0, ADPR1
INTRTC RTCIF RTCMK RTCPR0, RTCPR1
INTRTCI RTCIIF RTCIMK RTCIPR0, RTCIPR1
INTKR KRIF KRMK KRPR0, KRPR1
INTST2Note 2 STIF2Note 2 STMK2Note 2 STPR02, STPR12Note 2
INTCSI20Note 2 CSIIF20Note 2 CSIMK20Note 2 CSIPR020, CSIPR120Note 2
INTIIC20Note 2 IICIF20Note 2 IICMK20Note 2 IICPR020, IICPR120Note 2
INTSR2 SRIF2 SRMK2 SRPR02, SRPR12
INTSRE2 SREIF2 SREMK2 SREPR02, SREPR12
INTTM04 TMIF04
IF1H
TMMK04
MK1H
TMPR004, TMPR104
PR01H,
PR11H
INTTM05 TMIF05 TMMK05 TMPR005, TMPR105
INTTM06 TMIF06 TMMK06 TMPR006, TMPR106
INTTM07 TMIF07 TMMK07 TMPR007, TMPR107
INTP6 PIF6 PMK6 PPR06, PPR16
INTP7 PIF7 PMK7 PPR07, PPR17
INTP8 PIF8 PMK8 PPR08, PPR18
INTP9 PIF9 PMK9 PPR09, PPR19
INTP10 PIF10
IF2L
PMK10
MK2L
PPR010, PPR110
PR02L,
PR12L
INTP11 PIF11 IF2H PMK11 MK2H PPR011, PPR111
PR02H,
PR12H
Notes 1. Do not use UART1, CSI10, and IIC10 at the same time because they share flags for the interrupt
request sources. If one of the interrupt sources INTST1, INTCSI10, and INTIIC10 is generated, bit 0 of
IF1L is set to 1. Bit 0 of MK1L, PR01L, and PR11L supports these three interrupt sources.
2. Do not use UART2, CSI20, and IIC20 at the same time because they share flags for the interrupt
request sources. If one of the interrupt sources INTST2, INTCSI20, and INTIIC20 is generated, bit 4 of
IF1H is set to 1. Bit 4 of MK1H, PR01H, and PR11H supports these three interrupt sources.
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(1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt
routine is entered.
IF0L, IF0H, IF1L, IF1H, IF2L, and IF2H can be set by a 1-bit or 8-bit memory manipulation instruction. When
IF0L and IF0H, IF1L and IF1H, and IF2L and IF2H are combined to form 16-bit registers IF0, IF1, and IF2, they
can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 17-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (1/2)
Address: FFFE0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF0L PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF WDTIIF
Address: FFFE1H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF0H SREIF0
SRIF0
CSIIF01
STIF0
CSIIF00
DMAIF1 DMAIF0 SREIF3 SRIF3 STIF3
Address: FFFE2H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF1L TMIF03 TMIF02 TMIF01 TMIF00 IICIF0 SREIF1 SRIF1 STIF1
CSIIF10
IICIF10
Address: FFFE3H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF1H TMIF04 SREIF2 SRIF2 STIF2
CSIIF20
IICIF20
KRIF RTCIIF RTCIF ADIF
Address: FFFD0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF2L PIF10 PIF9 PIF8 PIF7 PIF6 TMIF07 TMIF06 TMIF05
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Figure 17-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (2/2)
Address: FFFD1H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 <0>
IF2H 0 0 0 0 0 0 0 PIF11
XXIFX Interrupt request flag
0 No interrupt request signal is generated
1 Interrupt request is generated, interrupt request status
Cautions 1. Be sure to clear bits 1 to 7 of IF2H to 0.
2. When operating a timer, serial interface, or A/D converter after standby release, operate it
once after clearing the interrupt request flag. An interrupt request flag may be set by noise.
3. When manipulating a flag of the interrupt request flag register, use a 1-bit memory
manipulation instruction (CLR1). When describing in C language, use a bit manipulation
instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler
must be a 1-bit memory manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction
such as “IF0L &= 0xfe;” and compiled, it becomes the assembler of three instructions.
mov a, IF0L
and a, #0FEH
mov IF0L, a
In this case, even if the request flag of another bit of the same interrupt request flag register
(IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the flag is cleared
to 0 at “mov IF0L, a”. Therefore, care must be exercised when using an 8-bit memory
manipulation instruction in C language.
(2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing.
MK0L, MK0H, MK1L, MK1H, MK2L, and MK2H can be set by a 1-bit or 8-bit memory manipulation instruction.
When MK0L and MK0H, MK1L and MK1H, and MK2L and MK2H are combined to form 16-bit registers MK0,
MK1, and MK2, they can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
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Figure 17-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)
Address: FFFE4H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK0L PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK WDTIMK
Address: FFFE5H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK0H SREMK0
SRMK0
CSIMK01
STMK0
CSIMK00
DMAMK1 DMAMK0 SREMK3 SRMK3 STMK3
Address: FFFE6H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK1L TMMK03 TMMK02 TMMK01 TMMK00 IICMK0 SREMK1 SRMK1 STMK1
CSIMK10
IICMK10
Address: FFFE7H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK1H TMMK04 SREMK2 SRMK2 STMK2
CSIMK20
IICMK20
KRMK RTCIMK RTCMK ADMK
Address: FFFD4H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK2L PMK10 PMK9 PMK8 PMK7 PMK6 TMMK07 TMMK06 TMMK05
Address: FFFD5H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 <0>
MK2H 1 1 1 1 1 1 1 PMK11
XXMKX Interrupt servicing control
0 Interrupt servicing enabled
1 Interrupt servicing disabled
Caution Be sure to set bits 1 to 7 of MK2H to 1.
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(3) Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,
PR11H, PR12L, PR12H)
The priority specification flag registers are used to set the corresponding maskable interrupt priority level.
A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, 2L, or 2H).
PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, and PR12H can be
set by a 1-bit or 8-bit memory manipulation instruction. If PR00L and PR00H, PR01L and PR01H, PR02L and
PR02H, PR10L and PR10H, PR11L and PR11H, and PR12L and PR12H are combined to form 16-bit registers
PR00, PR01, PR02, PR10, PR11, and PR12, they can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 17-4. Format of Priority Specification Flag Registers
(PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (1/2)
Address: FFFE8H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR00L PPR05 PPR04 PPR03 PPR02 PPR01 PPR00 LVIPR0 WDTIPR0
Address: FFFECH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR10L PPR15 PPR14 PPR13 PPR12 PPR11 PPR10 LVIPR1 WDTIPR1
Address: FFFE9H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR00H SREPR00
SRPR00
CSIPR001
STPR00
CSIPR000
DMAPR01 DMAPR00 SREPR03 SRPR03 STPR03
Address: FFFEDH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR10H SREPR10
SRPR10
CSIPR101
STPR10
CSIPR100
DMAPR11 DMAPR10 SREPR13 SRPR13 STPR13
Address: FFFEAH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR01L TMPR003 TMPR002 TMPR001 TMPR000 IICPR00 SREPR01 SRPR01 STPR01
CSIPR010
IICPR010
Address: FFFEEH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR11L TMPR103 TMPR102 TMPR101 TMPR100 IICPR10 SREPR11 SRPR11 STPR11
CSIPR110
IICPR110
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Figure 17-4. Format of Priority Specification Flag Registers
(PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (2/2)
Address: FFFEBH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR01H TMPR004 SREPR02 SRPR02 STPR02
CSIPR020
IICPR020
KRPR0 RTCIPR0 RTCPR0 ADPR0
Address: FFFEFH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR11H TMPR104 SREPR12 SRPR12 STPR12
CSIPR120
IICPR120
KRPR1 RTCIPR1 RTCPR1 ADPR1
Address: FFFD8H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR02L PPR010 PPR09 PPR08 PPR07 PPR06 TMPR007 TMPR006 TMPR005
Address: FFFDCH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR12L PPR110 PPR19 PPR18 PPR17 PPR16 TMPR107 TMPR106 TMPR105
Address: FFFD9H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 <0>
PR02H 1 1 1 1 1 1 1 PPR011
Address: FFFDDH After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 <0>
PR12H 1 1 1 1 1 1 1 PPR111
XXPR1X XXPR0X Priority level selection
0 0 Specify level 0 (high priority level)
0 1 Specify level 1
1 0 Specify level 2
1 1 Specify level 3 (low priority level)
Caution Be sure to set bits 1 to 7 of PR02H and PR12H to 1.
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(4) External interrupt rising edge enable registers (EGP0, EGP1), external interrupt falling edge enable
registers (EGN0, EGN1)
These registers specify the valid edge for INTP0 to INTP11.
EGP0, EGP1, EGN0, and EGN1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 17-5. Format of External Interrupt Rising Edge Enable Registers (EGP0, EGP1)
and External Interrupt Falling Edge Enable Registers (EGN0, EGN1)
Address: FFF38H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGP0 EGP7 EGP6 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0
Address: FFF39H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGN0 EGN7 EGN6 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0
Address: FFF3AH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGP1 0 0 0 0 EGP11 EGP10 EGP9 EGP8
Address: FFF3BH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGN1 0 0 0 0 EGN11 EGN10 EGN9 EGN8
EGPn EGNn INTPn pin valid edge selection (n = 0 to 11)
0 0 Edge detection disabled
0 1 Falling edge
1 0 Rising edge
1 1 Both rising and falling edges
Table 17-3 shows the ports corresponding to EGPn and EGNn.
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Table 17-3. Ports Corresponding to EGPn and EGNn
Detection Enable Register Edge Detection Port Interrupt Request Signal
EGP0 EGN0 P120 INTP0
EGP1 EGN1 P46 INTP1
EGP2 EGN2 P47 INTP2
EGP3 EGN3 P30 INTP3
EGP4 EGN4 P31 INTP4
EGP5 EGN5 P16 INTP5
EGP6 EGN6 P140 INTP6
EGP7 EGN7 P141 INTP7
EGP8 EGN8 P74 INTP8
EGP9 EGN9 P75 INTP9
EGP10 EGN10 P76 INTP10
EGP11 EGN11 P77 INTP11
Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be
detected when the external interrupt function is switched to the port function.
Remark n = 0 to 11
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(5) Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for an
interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that
controls multiple interrupt servicing are mapped to the PSW.
Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated
instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed,
the contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt
request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are
transferred to the ISP0 and ISP1 flags. The PSW contents are also saved into the stack with the PUSH PSW
instruction. They are restored from the stack with the RETI, RETB, and POP PSW instructions.
Reset signal generation sets PSW to 06H.
Figure 17-6. Configuration of Program Status Word
<7>
IE
<6>
Z
<5>
RBS1
<4>
AC
<3>
RBS0
<2>
ISP1
<1>
ISP0
0
CYPSW
After reset
06H
ISP1
0
0
1
1
Enables interrupt of level 0
(while interrupt of level 1 or 0 is being serviced).
Enables interrupt of level 0 and 1
(while interrupt of level 2 is being serviced).
Enables interrupt of level 0 to 2
(while interrupt of level 3 is being serviced).
Enables all interrupts
(waits for acknowledgment of an interrupt).
IE
0
1
Disabled
Enabled
Priority of interrupt currently being serviced
Interrupt request acknowledgment enable/disable
Used when normal instruction is executed
ISP0
0
1
0
1
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17.4 Interrupt Servicing Operations
17.4.1 Maskable interrupt acknowledgment
A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag
corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are
in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not
acknowledged during servicing of a higher priority interrupt request.
The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed
in Table 17-4 below.
For the interrupt request acknowledgment timing, see Figures 17-8 and 17-9.
Table 17-4. Time from Generation of Maskable Interrupt Until Servicing
Minimum Time Maximum TimeNote
Servicing time 9 clocks 14 clocks
Note If an interrupt request is generated just before the RET instruction, the wait time becomes longer.
Remark 1 clock: 1/fCLK (fCLK: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same
priority level, the request with the highest default priority is acknowledged first.
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 17-7 shows the interrupt request acknowledgment algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then
PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged
interrupt are transferred to the ISP1 and ISP0 flags. The vector table data determined for each interrupt request is the
loaded into the PC and branched.
Restoring from an interrupt is possible by using the RETI instruction.
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Figure 17-7. Interrupt Request Acknowledgment Processing Algorithm
Yes
No
Yes
No
Yes
No
No
Yes
No
IE = 1?
Vectored interrupt servicing
Start
××IF = 1?
××MK = 0?
(××PR1, ××PR0)
≤ (ISP1, ISP0)
Yes (interrupt request generation)
No (Low priority)
Interrupt request held pending
Interrupt request held pending
Interrupt request held pending
Interrupt request held pending
Interrupt request held pending
Higher priority
than other interrupt requests
simultaneously
generated?
Higher default priorityNote
than other interrupt requests
simultaneously
generated?
××IF: Interrupt request flag
××MK: Interrupt mask flag
××PR0: Priority specification flag 0
××PR1: Priority specification flag 1
IE: Flag that controls acknowledgment of maskable interrupt request (1 = Enable, 0 = Disable)
ISP0, ISP1: Flag that indicates the priority level of the interrupt currently being serviced (see Figure 17-6)
Note For the default priority, refer to Table 17-1 Interrupt Source List.
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Figure 17-8. Interrupt Request Acknowledgment Timing (Minimum Time)
9 clocks
Instruction Instruction
CPU processing
××IF
6 clocks
PSW and PC saved,
jump to interrupt
servicing
Interrupt servicing
program
Remark 1 clock: 1/fCLK (fCLK: CPU clock)
Figure 17-9. Interrupt Request Acknowledgment Timing (Maximum Time)
14 clocks
Instruction RET instruction
CPU processing
××IF
6 clocks6 clocks
PSW and PC saved,
jump to interrupt
servicing
Interrupt servicing
program
Remark 1 clock: 1/fCLK (fCLK: CPU clock)
17.4.2 Software interrupt request acknowledgment
A software interrupt acknowledge is acknowledged by BRK instruction execution. Software interrupts cannot be
disabled.
If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program
status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH,
0007FH) are loaded into the PC and branched.
Restoring from a software interrupt is possible by using the RETB instruction.
Caution Do not use the RETI instruction for restoring from the software interrupt.
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17.4.3 Multiple interrupt servicing
Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt.
Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected
(IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0).
Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during
interrupt servicing to enable interrupt acknowledgment.
Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to
interrupt priority control. Two types of priority control are available: default priority control and programmable priority
control. Programmable priority control is used for multiple interrupt servicing.
In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt
currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority
lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged
for multiple interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled
state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the
pending interrupt request is acknowledged following execution of at least one main processing instruction execution.
Table 17-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 17-10
shows multiple interrupt servicing examples.
Table 17-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing
During Interrupt Servicing
Maskable Interrupt Request
Priority Level 0
(PR = 00)
Priority Level 1
(PR = 01)
Priority Level 2
(PR = 10)
Priority Level 3
(PR = 11)
Multiple Interrupt Request
Interrupt Being Serviced IE = 1 IE = 0 IE = 1 IE = 0 IE = 1 IE = 0 IE = 1 IE = 0
Software
Interrupt
Request
ISP1 = 0
ISP0 = 0
{ × × × × × × × {
ISP1 = 0
ISP0 = 1
{ × { × × × × × {
ISP1 = 1
ISP0 = 0
{ × { × { × × × {
Maskable interrupt
ISP1 = 1
ISP0 = 1
{ × { × { × { × {
Software interrupt { × { × { × { × {
Remarks 1. {: Multiple interrupt servicing enabled
2. ×: Multiple interrupt servicing disabled
3. ISP0, ISP1, and IE are flags contained in the PSW.
ISP1 = 0, ISP0 = 0: An interrupt of level 1 or level 0 is being serviced.
ISP1 = 0, ISP0 = 1: An interrupt of level 2 is being serviced.
ISP1 = 1, ISP0 = 0: An interrupt of level 3 is being serviced.
ISP1 = 1, ISP0 = 1: Wait for An interrupt acknowledgment.
IE = 0: Interrupt request acknowledgment is disabled.
IE = 1: Interrupt request acknowledgment is enabled.
4. PR is a flag contained in PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,
PR11H, PR12L, and PR12H.
PR = 00: Specify level 0 with ××PR1× = 0, ××PR0× = 0 (higher priority level)
PR = 01: Specify level 1 with ××PR1× = 0, ××PR0× = 1
PR = 10: Specify level 2 with ××PR1× = 1, ××PR0× = 0
PR = 11: Specify level 3 with ××PR1× = 1, ××PR0× = 1 (lower priority level)
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Figure 17-10. Examples of Multiple Interrupt Servicing (1/2)
Example 1. Multiple interrupt servicing occurs twice
Main processing INTxx servicing INTyy servicing INTzz servicing
EI EI EI
RETI RETI
RETI
INTxx
(PR = 11)
INTyy
(PR = 10)
INTzz
(PR = 01)
IE = 0 IE = 0 IE = 0
IE = 1 IE = 1
IE = 1
During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple
interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be
issued to enable interrupt request acknowledgment.
Example 2. Multiple interrupt servicing does not occur due to priority control
Main processing INTxx servicing INTyy servicing
INTxx
(PR = 10)
INTyy
(PR = 11)
EI
RETI
IE = 0
IE = 0
EI
1 instruction execution
RETI
IE = 1
IE = 1
Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower
than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending,
and is acknowledged following execution of one main processing instruction.
PR = 00: Specify level 0 with ××PR1× = 0, ××PR0× = 0 (higher priority level)
PR = 01: Specify level 1 with ××PR1× = 0, ××PR0× = 1
PR = 10: Specify level 2 with ××PR1× = 1, ××PR0× = 0
PR = 11: Specify level 3 with ××PR1× = 1, ××PR0× = 1 (lower priority level)
IE = 0: Interrupt request acknowledgment is disabled.
IE = 1: Interrupt request acknowledgment is enabled.
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User’s Manual U17894EJ9V0UD 653
Figure 17-10. Examples of Multiple Interrupt Servicing (2/2)
Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled
Main processing INTxx servicing INTyy servicing
EI
1 instruction execution
RETI
RETI
INTxx
(PR = 11)
INTyy
(PR = 00)
IE = 0
IE = 0
IE = 1
IE = 1
Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt
request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request
is held pending, and is acknowledged following execution of one main processing instruction.
PR = 00: Specify level 0 with ××PR1× = 0, ××PR0× = 0 (higher priority level)
PR = 01: Specify level 1 with ××PR1× = 0, ××PR0× = 1
PR = 10: Specify level 2 with ××PR1× = 1, ××PR0× = 0
PR = 11: Specify level 3 with ××PR1× = 1, ××PR0× = 1 (lower priority level)
IE = 0: Interrupt request acknowledgment is disabled.
IE = 1: Interrupt request acknowledgment is enabled.
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17.4.4 Interrupt request hold
There are instructions where, even if an interrupt request is issued while the instruction are being executed,
interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions
(interrupt request hold instructions) are listed below.
• MOV PSW, #byte
• MOV PSW, A
• MOV1 PSW. bit, CY
• SET1 PSW. bit
• CLR1 PSW. bit
• RETB
• RETI
• POP PSW
• BTCLR PSW. bit, $addr20
• EI
• DI
• SKC
• SKNC
• SKZ
• SKNZ
• SKH
• SKNH
• Manipulation instructions for the IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, MK0L, MK0H, MK1L, MK1H, MK2L, MK2H,
PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, and PR12H
registers.
Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However,
the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared.
Therefore, even if a maskable interrupt request is generated during execution of the BRK
instruction, the interrupt request is not acknowledged.
Figure 17-11 shows the timing at which interrupt requests are held pending.
Figure 17-11. Interrupt Request Hold
Instruction N Instruction M PSW and PC saved, jump
to interrupt servicing
Interrupt servicing
program
CPU processing
××IF
Remarks 1. Instruction N: Interrupt request hold instruction
2. Instruction M: Instruction other than interrupt request hold instruction
3. The ××PR (priority level) values do not affect the operation of ××IF (interrupt request).
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CHAPTER 18 KEY INTERRUPT FUNCTION
18.1 Functions of Key Interrupt
A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling
edge to the key interrupt input pins (KR0 to KR7).
Table 18-1. Assignment of Key Interrupt Detection Pins
Flag Description
KRM0 Controls KR0 signal in 1-bit units.
KRM1 Controls KR1 signal in 1-bit units.
KRM2 Controls KR2 signal in 1-bit units.
KRM3 Controls KR3 signal in 1-bit units.
KRM4 Controls KR4 signal in 1-bit units.
KRM5 Controls KR5 signal in 1-bit units.
KRM6 Controls KR6 signal in 1-bit units.
KRM7 Controls KR7 signal in 1-bit units.
18.2 Configuration of Key Interrupt
The key interrupt includes the following hardware.
Table 18-2. Configuration of Key Interrupt
Item Configuration
Control register Key return mode register (KRM)
Port mode register 7 (PM7)
Figure 18-1. Block Diagram of Key Interrupt
INTKR
Key return mode register (KRM)
KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0
KR7/P77/EX23/INTP11
KR6/P76/EX22/INTP10
KR5/P75/EX21/INTP9
KR4/P74/EX20/INTP8
KR3/P73/EX19
KR2/P72/EX18
KR1/P71/EX17
KR0/P70/EX16
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18.3 Register Controlling Key Interrupt
(1) Key return mode register (KRM)
This register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals, respectively.
KRM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 18-2. Format of Key Return Mode Register (KRM)
KRM7
Does not detect key interrupt signal
Detects key interrupt signal
KRMn
0
1
Key interrupt mode control
KRM KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0
Address: FFF37H After reset: 00H R/W
Symbol 765432 0
Cautions 1. If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of the
corresponding pull-up resistor register 7 (PU7) to 1.
2. An interrupt will be generated if the target bit of the KRM register is set while a low level is
being input to the key interrupt input pin. To ignore this interrupt, set the KRM register after
disabling interrupt servicing by using the interrupt mask flag. Afterward, clear the interrupt
request flag and enable interrupt servicing after waiting for the key interrupt input low-level
width (250 ns or more).
3. The bits not used in the key interrupt mode can be used as normal ports.
Remark n = 0 to 7
(2) Port mode register 7 (PM7)
This register sets the input or output of port 7 in 1-bit units.
When using the P70/KR0/EX16, P71/KR1/EX17, P72/KR2/EX18, P73/KR3/EX19, P74/KR4/EX20/INTP8,
P75/KR5/EX21/INTP9, P76/KR6/EX22/INTP10, P77/KR7/EX23/INTP11 pins as the key interrupt function, set
both PM70 to PM77 to 1. The output latches of P70 to P77 at this time may be 0 or 1.
PM7 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 18-3. Format of Port Mode Register 7 (PM7)
Address: FFF27H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70
PM7n P7n pin I/O mode selection (n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
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CHAPTER 19 STANDBY FUNCTION
19.1 Standby Function and Configuration
19.1.1 Standby function
The standby function reduces the operating current of the system, and the following two modes are available.
(1) HALT mode
HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the
high-speed system clock oscillator, internal high-speed oscillator, or subsystem clock oscillator is operating
before the HALT mode is set, oscillation of each clock continues. In this mode, the operating current is not
decreased as much as in the STOP mode, but the HALT mode is effective for restarting operation immediately
upon interrupt request generation and carrying out intermittent operations frequently.
(2) STOP mode
STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator and
internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating
current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is
released when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately
upon interrupt request generation.
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is
set are held. The I/O port output latches and output buffer statuses are also held.
Cautions 1. The STOP mode can be used only when the CPU is operating on the main system clock. The
STOP mode cannot be set while the CPU operates with the subsystem clock. The HALT
mode can be used when the CPU is operating on either the main system clock or the
subsystem clock.
2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation
operating with main system clock before executing STOP instruction.
3. The following sequence is recommended for operating current reduction of the A/D converter
when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D
converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute
the STOP instruction.
4. It can be selected by the option byte whether the internal low-speed oscillator continues
oscillating or stops in the HALT or STOP mode. For details, see CHAPTER 24 OPTION BYTE.
19.1.2 Registers controlling standby function
The standby function is controlled by the following two registers.
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
Remark For the registers that start, stop, or select the clock, see CHAPTER 6 CLOCK GENERATOR.
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(1) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case,
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or subsystem clock is being
used as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used
as the CPU clock with the X1 clock oscillating.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, WDT, and executing an illegal instruction), the STOP
instruction and MSTOP (bit 7 of CSC register) = 1 clear this register to 00H.
Figure 19-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFFA2H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
OSTC MOST
8
MOST
9
MOST
10
MOST
11
MOST
13
MOST
15
MOST
17
MOST
18
Oscillation stabilization time status
MOST
8
MOST
9
MOST
10
MOST
11
MOST
13
MOST
15
MOST
17
MOST
18 fX = 10 MHz fX = 20 MHz
0 0 0 0 0 0 0 0 28/fX max. 25.6
μ
s max. 12.8
μ
s max.
1 0 0 0 0 0 0 0 28/fX min. 25.6
μ
s min. 12.8
μ
s min.
1 1 0 0 0 0 0 0 29/fX min. 51.2
μ
s min. 25.6
μ
s min.
1 1 1 0 0 0 0 0 210/fX min. 102.4
μ
s min. 51.2
μ
s min.
1 1 1 1 0 0 0 0 211/fX min. 204.8
μ
s min. 102.4
μ
s min.
1 1 1 1 1 0 0 0 213/fX min. 819.2
μ
s min. 409.6
μ
s min.
1 1 1 1 1 1 0 0 215/fX min. 3.27 ms min. 1.64 ms min.
1 1 1 1 1 1 1 0 217/fX min. 13.11 ms min. 6.55 ms min.
1 1 1 1 1 1 1 1 218/fX min. 26.21 ms min. 13.11 ms min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST8 and
remain 1.
2. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
3. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark f
X: X1 clock oscillation frequency
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(2) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP
mode is released.
When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired
oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can
be checked up to the time set using OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 07H.
Figure 19-2. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFFA3H After reset: 07H R/W
Symbol 7 6 5 4 3 2 1 0
OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0
Oscillation stabilization time selection
OSTS2 OSTS1 OSTS0
fX = 10 MHz fX = 20 MHz
0 0 0 28/fX 25.6
μ
s Setting prohibited
0 0 1 29/fX 51.2
μ
s 25.6
μ
s
0 1 0 210/fX 102.4
μ
s 51.2
μ
s
0 1 1 211/fX 204.8
μ
s 102.4
μ
s
1 0 0 213/fX 819.2
μ
s 409.6
μ
s
1 0 1 215/fX 3.27 ms 1.64 ms
1 1 0 217/fX 13.11 ms 6.55 ms
1 1 1 218/fX 26.21 ms 13.11 ms
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before
executing the STOP instruction.
2. Setting the oscillation stabilization time to 20
μ
s or less is prohibited.
3. Before changing the setting of the OSTS register, confirm that the count operation of the
OSTC register is completed.
4. Do not change the value of the OSTS register during the X1 clock oscillation stabilization
time.
5. The oscillation stabilization time counter counts up to the oscillation stabilization time set
by OSTS. If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock, set the oscillation stabilization time as
follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is
set to OSTC after STOP mode is released.
6. The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark f
X: X1 clock oscillation frequency
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19.2 Standby Function Operation
19.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU
clock before the setting was the high-speed system clock, internal high-speed oscillation clock, or subsystem
clock.
The operating statuses in the HALT mode are shown below.
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Table 19-1. Operating Statuses in HALT Mode (1/2)
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock HALT Mode Setting
Item
When CPU Is Operating on
Internal High-Speed
Oscillation Clock (fIH)
When CPU Is Operating on
X1 Clock (fX)
When CPU Is Operating on
External Main System Clock
(fEX)
System clock Clock supply to the CPU is stopped
fIH Operation continues (cannot
be stopped)
Status before HALT mode was set is retained
fX Operation continues (cannot
be stopped)
Cannot operate
Main system clock
fEX
Status before HALT mode
was set is retained
Cannot operate Operation continues (cannot
be stopped)
Subsystem clock fXT Status before HALT mode was set is retained
fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H)
• WDTON = 0: Stops
• WDTON = 1 and WDSTBYON = 1: Oscillates
• WDTON = 1 and WDSTBYON = 0: Stops
CPU Operation stopped
Flash memory Operable in low-current consumption mode
RAM Operation stopped. However, status before HALT mode was set is retained at voltage higher
than POC detection voltage.
Port (latch) Status before HALT mode was set is retained
External bus interface Operation stopped. Status of each pin CKOUT: Continuously outputs internal system clock
AD15 to AD0 or D15 to D0: High impedance
A19 to A0: Retains status before HALT mode was set
RD, WR0, WR1: High level
ASTB: Low level
WAIT: High impedance
Timer array unit (TAU)
Real-time counter (RTC)
Operable
Watchdog timer Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H)
• WDTON = 0: Stops
• WDTON = 1 and WDSTBYON = 1: Operates
• WDTON = 1 and WDSTBYON = 0: Stops
Clock output/buzzer output
A/D converter
D/A converter
Serial array unit (SAU)
Serial interface (IIC0)
Operable
Multiplier Operation stopped
DMA controller
Power-on-clear function
Low-voltage detection function
External interrupt
Key interrupt function
Operable
Remarks 1. fIH: Internal high-speed oscillation clock
fX: X1 clock
f
EX: External main system clock
f
XT: XT1 clock
fIL: Internal low-speed oscillation clock
2. A
XX: Address bus
D
XX: Data bus
ADXX: Multiplexed address/data bus
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Table 19-1. Operating Statuses in HALT Mode (2/2)
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock HALT Mode Setting
Item When CPU Is Operating on XT1 Clock (fXT)
System clock Clock supply to the CPU is stopped
fIH
fX
Status before HALT mode was set is retained
Main system clock
fEX Operates or stops by external clock input
Subsystem clock fXT Operation continues (cannot be stopped)
fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H)
• WDTON = 0: Stops
• WDTON = 1 and WDSTBYON = 1: Oscillates
• WDTON = 1 and WDSTBYON = 0: Stops
CPU Operation stopped
Flash memory Operable in low-current consumption mode
RAM Operation stopped. However, status before HALT mode was set is retained at voltage higher
than POC detection voltage.
Port (latch) Status before HALT mode was set is retained
External bus interface Operation stopped. Status of each pin CKOUT: Continuously outputs internal system clock
AD15 to AD0 or D15 to D0: High impedance
A19 to A0: Retains status before HALT mode was set
RD, WR0, WR1: High level
ASTB: Low level
WAIT: High impedance
Timer array unit (TAU)
Real-time counter (RTC)
Operable
Watchdog timer Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H)
• WDTON = 0: Stops
• WDTON = 1 and WDSTBYON = 1: Operates
• WDTON = 1 and WDSTBYON = 0: Stops
Clock output/buzzer output Operable
A/D converter Cannot operate
D/A converter
Serial array unit (SAU)
Operable
Serial interface (IIC0) Cannot operate
Multiplier Operation stopped
DMA controller
Power-on-clear function
Low-voltage detection function
External interrupt
Key interrupt function
Operable
Remarks 1. fIH: Internal high-speed oscillation clock
f
X: X1 clock
f
EX: External main system clock
fXT: XT1 clock
f
IL: Internal low-speed oscillation clock
2. A
XX: Address bus
DXX: Data bus
ADXX: Multiplexed address/data bus
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(2) HALT mode release
The HALT mode can be released by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment
is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next
address instruction is executed.
Figure 19-3. HALT Mode Release by Interrupt Request Generation
HALT
instruction
WaitNote Normal operationHALT modeNormal operation
Oscillation
High-speed system clock,
internal high-speed oscillation clock,
or subsystem clock
Status of CPU
Standby
release signal
Interrupt
request
Note The wait time is as follows:
• When vectored interrupt servicing is carried out
When main system clock is used: 10 to 12 clocks
When subsystem clock is used: 8 to 10 clocks
• When vectored interrupt servicing is not carried out
When main system clock is used: 5 or 6 clocks
When subsystem clock is used: 3 or 4 clocks
Remark The broken lines indicate the case when the interrupt request which has released the standby
mode is acknowledged.
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(b) Release by reset signal generation
When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 19-4. HALT Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
HALT
instruction
Reset signal
High-speed
system clock
(X1 oscillation)
HALT mode
Reset
period
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Normal operation
(high-speed
system clock)
Oscillation stabilization time
(28/fX to 211/fX, 213/fX, 215/fX, 217/fX, 218/fX)
Normal operation
(internal high-speed
oscillation clock)
Oscillation
stopped
Starting X1 oscillation is
specified by software.
Reset processing
(1.92 to 6.17 ms)
(2) When internal high-speed oscillation clock is used as CPU clock
HALT
instruction
Reset signal
Internal high-speed
oscillation clock
Normal operation
(internal high-speed
oscillation clock) HALT mode
Reset
period
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Wait for oscillation
accuracy stabilization
Reset processing
(1.92 to 6.17 ms)
(3) When subsystem clock is used as CPU clock
HALT
instruction
Reset signal
Subsystem clock
(XT1 oscillation)
Normal operation
(subsystem clock) HALT mode
Reset
period
Normal operation mode
(internal high-speed
oscillation clock)
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Oscillation
stopped
Starting XT1 oscillation is
specified by software.
Reset processing
(1.92 to 6.17 ms)
Remark f
X: X1 clock oscillation frequency
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19.2.2 STOP mode
(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the
setting was the main system clock.
Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt
source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is
immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after
execution of the STOP instruction and the system returns to the operating mode as soon as the
wait time set using the oscillation stabilization time select register (OSTS) has elapsed.
The operating statuses in the STOP mode are shown below.
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Table 19-2. Operating Statuses in STOP Mode
When STOP Instruction Is Executed While CPU Is Operating on Main System Clock STOP Mode Setting
Item
When CPU Is Operating on
Internal High-Speed
Oscillation Clock (fIH)
When CPU Is Operating on
X1 Clock (fX)
When CPU Is Operating on
External Main System Clock
(fEX)
System clock Clock supply to the CPU is stopped
fIH
fX
Main system clock
fEX
Stopped
Subsystem clock fXT Status before STOP mode was set is retained
fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H)
• WDTON = 0: Stops
• WDTON = 1 and WDSTBYON = 1: Oscillates
• WDTON = 1 and WDSTBYON = 0: Stops
CPU Operation stopped
Flash memory Operation stopped
RAM Operation stopped. However, status before STOP mode was set is retained at voltage higher
than POC detection voltage.
Port (latch) Status before STOP mode was set is retained
External bus interface Operation stopped. Status of each pin CKOUT: Low level
AD15 to AD0 or D15 to D0: High impedance
A19 to A0: Retains status before STOP mode was set
RD, WR0, WR1: High level
ASTB: Low level
WAIT: High impedance
Timer array unit (TAU) Operation stopped
Real-time counter (RTC) Operable
Watchdog timer Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H)
• WDTON = 0: Stops
• WDTON = 1 and WDSTBYON = 1: Operates
• WDTON = 1 and WDSTBYON = 0: Stops
Clock output/buzzer output Operable only when subsystem clock is selected as the count clock
A/D converter Operation stopped.
D/A converter Operation stopped (the pin in Hi-Z status)
Serial array unit (SAU)
Serial interface (IIC0)
Multiplier
DMA controller
Operation stopped
Power-on-clear function
Low-voltage detection function
External interrupt
Key interrupt function
Operable
Remarks 1. fIH: Internal high-speed oscillation clock
f
X: X1 clock
f
EX: External main system clock
f
XT: XT1 clock
f
IL: Internal low-speed oscillation clock
2. A
XX: Address bus
D
XX: Data bus
ADXX: Multiplexed address/data bus
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User’s Manual U17894EJ9V0UD 667
Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral
hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is
released, restart the peripheral hardware.
2. To stop the internal low-speed oscillation clock in the STOP mode, use an option byte to stop
the watchdog timer operation in the HALT/STOP mode (bit 0 (WDSTBYON) of 000C0H = 0), and
then execute the STOP instruction.
3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates
with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the
internal high-speed oscillation clock before the execution of the STOP instruction. Before
changing the CPU clock from the internal high-speed oscillation clock to the high-speed system
clock (X1 oscillation) after the STOP mode is released, check the oscillation stabilization time
with the oscillation stabilization time counter status register (OSTC).
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(2) STOP mode release
Figure 19-5. Operation Timing When STOP Mode Is Released (Release by Unmasked Interrupt Request)
STOP mode
STOP mode release
High-speed system
clock (X1 oscillation)
High-speed system
clock (external clock
input)
Internal high-speed
oscillation clock
High-speed system
clock (X1 oscillation)
is selected as CPU
clock when STOP
instruction is executed
High-speed system
clock (external clock
input) is selected as
CPU clock when STOP
instruction is executed
Internal high-speed
oscillation clock is
selected as CPU clock
when STOP instruction
is executed
Wait for oscillation accuracy stabilization
HALT status
(oscillation stabilization time set by OSTS)
Note1
Clock switched by software
Clock switched by software
High-speed system clock
High-speed system clock
Wait
Note 2
Wait
Note 2
Supply of the CPU clock is stopped (when f
CLK
= f
IH
: 23 to 61 s)
High-speed system clock
Supply of the CPU clock is stopped (when f
CLK
= f
EX
: 23 to 61 s)
Internal high-speed
oscillation clock
μ
μ
Notes 1. When the oscillation stabilization time set by OSTS is equal to or shorter than 61
μ
s, the HALT status
is retained to a maximum of “61
μ
s + wait time.”
2. The wait time is as follows:
• When vectored interrupt servicing is carried out: 10 to 12 clocks
• When vectored interrupt servicing is not carried out: 5 or 6 clocks
Remark f
EX: External main system clock frequency
fIH: Internal high-speed oscillation clock frequency
f
CLK: CPU/peripheral hardware clock frequency
The STOP mode can be released by the following two sources.
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(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation
stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried
out. If interrupt acknowledgment is disabled, the next address instruction is executed.
Figure 19-6. STOP Mode Release by Interrupt Request Generation (1/2)
(1) When high-speed system clock (X1 oscillation) is used as CPU clock
Normal operation
(high-speed
system clock)
Normal operation
(high-speed
system clock)
OscillatesOscillates
STOP
instruction
STOP mode
Time set by
OSTS
Note 1
Standby release signal
Oscillation stabilization wait
(HALT mode status)
Oscillation stopped
High-speed
system clock
(X1 oscillation)
Status of CPU
Oscillation stabilization time (set by OSTS)
Interrupt
request
(2) When high-speed system clock (external clock input) is used as CPU clock
Interrupt
request
STOP
instruction
Standby release signal
Status of CPU
High-speed
system clock
(external clock input)
Oscillates
Normal operation
(high-speed
system clock) STOP mode
Oscillation stopped Oscillates
Normal operation
(high-speed
system clock)
Wait
Note 3
Supply of the CPU
clock is stopped
(23 to 61 s
Note 2
)
μ
Notes 1. When the oscillation stabilization time set by OSTS is equal to or shorter than 61
μ
s, the HALT
status is retained to a maximum of “61
μ
s + wait time”.
2. When fCLK = fEX
3. The wait time is as follows:
• When vectored interrupt servicing is carried out: 10 to 12 clocks
• When vectored interrupt servicing is not carried out: 5 or 6 clocks
Remarks 1. The broken lines indicate the case when the interrupt request that has released the standby
mode is acknowledged.
2. fEX: External main system clock frequency
f
CLK: CPU/peripheral hardware clock frequency
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Figure 19-6. STOP Mode Release by Interrupt Request Generation (2/2)
(3) When internal high-speed oscillation clock is used as CPU clock
Standby release signal
Status of CPU
Internal high-speed
oscillation clock
Normal operation
(internal high-speed
oscillation clock)
Oscillates
STOP mode
Oscillation stopped
Wait for oscillation
accuracy stabilization
Interrupt
request
STOP
instruction
Wait
Note 2
Normal operation
(internal high-speed
oscillation clock)
Supply of the CPU
clock is stopped
(23 to 61 s
Note 1
)
Oscillates
μ
Notes 1. When fCLK = fIH
2. The wait time is as follows:
• When vectored interrupt servicing is carried out: 10 to 12 clocks
• When vectored interrupt servicing is not carried out: 5 or 6 clocks
Remarks 1. The broken lines indicate the case when the interrupt request that has released the standby
mode is acknowledged.
2. fIH: Internal high-speed oscillation clock frequency
f
CLK: CPU/peripheral hardware clock frequency
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(b) Release by reset signal generation
When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 19-7. STOP Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
STOP
instruction
Reset signal
High-speed
system clock
(X1 oscillation)
Normal operation
(high-speed
system clock) STOP mode
Reset
period
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Oscillation stabilization time
(28/fX to 211/fX, 213/fX, 215/fX, 217/fX, 218/fX)
Oscillation
stopped
Starting X1 oscillation is
specified by software.
Oscillation stopped
Reset processing
(1.92 to 6.17 ms)
(2) When internal high-speed oscillation clock is used as CPU clock
STOP
instruction
Reset signal
Internal high-speed
oscillation clock
Normal operation
(internal high-speed
oscillation clock)
STOP mode
Reset
period
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Oscillation
stopped
Status of CPU
Oscillates
Oscillation stopped
Wait for oscillation
accuracy stabilization
Reset processing
(1.92 to 6.17 ms)
Remark f
X: X1 clock oscillation frequency
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CHAPTER 20 RESET FUNCTION
The following five operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage of low-voltage detector (LVI) or input voltage (EXLVI) from
external input pin, and detection voltage
(5) Internal reset by execution of illegal instructionNote
External and internal resets start program execution from the address at 0000H and 0001H when the reset signal
is generated.
A reset is effected when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI
circuit voltage detection or execution of illegal instructionNote, and each item of hardware is set to the status shown in
Tables 20-1 and 20-2. Each pin is high impedance during reset signal generation or during the oscillation stabilization
time just after a reset release, except for P130, which is low-level output.
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high
level is input to the RESET pin and program execution is started with the internal high-speed oscillation clock after
reset processing. A reset by the watchdog timer is automatically released, and program execution starts using the
internal high-speed oscillation clock (see Figures 20-2 to 20-4) after reset processing. Reset by POC and LVI circuit
supply voltage detection is automatically released when VDD ≥ VPOC or VDD ≥ VLVI after the reset, and program
execution starts using the internal high-speed oscillation clock (see CHAPTER 21 POWER-ON-CLEAR CIRCUIT
and CHAPTER 22 LOW-VOLTAGE DETECTOR) after reset processing.
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
Cautions 1. For an external reset, input a low level for 10
μ
s or more to the RESET pin.
(If an external reset is effected upon power application, the period during which the supply
voltage is outside the operating range (VDD < 1.8 V) is not counted in the 10
μ
s. However, the
low-level input may be continued before POC is released.)
2. During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and internal
low-speed oscillation clock stop oscillating. External main system clock input becomes
invalid.
3. When the STOP mode is released by a reset, the RAM contents in the STOP mode are held
during reset input. However, because SFR and 2nd SFR are initialized, the port pins become
high-impedance, except for P130, which is set to low-level output.
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User’s Manual U17894EJ9V0UD 673
Figure 20-1. Block Diagram of Reset Function
LVIRFWDRF
Reset control flag
register (RESF)
Internal bus
Watchdog timer reset signal
RESET
Power-on clear circuit reset signal
Low-voltage detector reset signal Reset signal
Reset signal to LVIM/LVIS register
Clear
Set
Clear
Set
TRAP
Reset signal by execution of illegal instruction
Set
Clear
RESF register read signal
Caution An LVI circuit internal reset does not reset the LVI circuit.
Remarks 1. LVIM: Low-voltage detection register
2. LVIS: Low-voltage detection level select register
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Figure 20-2. Timing of Reset by RESET Input
Hi-Z
Normal operationCPU status Reset period
(oscillation stop)
Normal operation
(internal high-speed oscillation clock)
RESET
Internal reset signal
Port pin
(except P130)
Port pin
(P130) Note
High-speed system clock
(when X1 oscillation is selected)
Internal high-speed
oscillation clock
Starting X1 oscillation is specified by software.
Reset processing
(1.92 to 6.17 ms)
Wait for oscillation
accuracy stabilization
Delay
(5 s (MAX.))
μ
Delay
(5 s (MAX.))
μ
Note Set P130 to high-level output by software.
Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
Figure 20-3. Timing of Reset Due to Execution of Illegal Instruction or Watchdog Timer Overflow
Normal operation
Reset period
(oscillation stop)
(100 ns (TYP.))
CPU status
Execution of illegal
instruction/
watchdog timer
overflow
Internal reset signal
Hi-Z
Port pin
(except P130)
Port pin
(P130) Note
High-speed system clock
(when X1 oscillation is selected)
Internal high-speed
oscillation clock
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Wait for oscillation
accuracy stabilization
Reset processing
(
61 to 162 s
)
μ
Note Set P130 to high-level output by software.
Caution A watchdog timer internal reset resets the watchdog timer.
Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
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User’s Manual U17894EJ9V0UD 675
Figure 20-4. Timing of Reset in STOP Mode by RESET Input
Normal
operation
CPU status Reset period
(oscillation stop)
RESET
Internal reset signal
STOP instruction execution
Stop status
(oscillation stop)
High-speed system clock
(when X1 oscillation is selected)
Internal high-speed
oscillation clock
Hi-Z
Port pin
(except P130)
Port pin
(P130) Note
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Wait for oscillation
accuracy stabilization
Reset processing
(1.92 to 6.17 ms)
Delay
(5 s (MAX.))
Delay
(5 s (MAX.))
μ
μ
Note Set P130 to high-level output by software.
Remarks 1. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the CPU reset signal.
2. For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 21
POWER-ON-CLEAR CIRCUIT and CHAPTER 22 LOW-VOLTAGE DETECTOR.
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Table 20-1. Operation Statuses During Reset Period
Item During Reset Period
System clock Clock supply to the CPU is stopped.
fIH Operation stopped
fX Operation stopped (X1 and X2 pins are input port mode)
Main system clock
fEX Clock input invalid (pin is input port mode)
Subsystem clock fXT Operation stopped (XT1 and XT2 pins are input port mode)
fIL
CPU
Operation stopped
Flash memory Operable in low-current consumption mode
RAM Operation stopped
Port (latch)
External bus interface
Timer array unit (TAU)
Real-time counter (RTC)
Watch timer
Watchdog timer
Clock output/buzzer output
A/D converter
D/A converter
Serial array unit (SAU)
Serial interface (IIC0)
Multiplier
Operation stopped
Power-on-clear function Operable
Low-voltage detection function Operation stopped (however, operation continues at LVI reset)
External interrupt
Key interrupt function
Operation stopped
Remark fIH: Internal high-speed oscillation clock
f
X: X1 oscillation clock
f
EX: External main system clock
fXT: XT1 oscillation clock
f
IL: Internal low-speed oscillation clock
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User’s Manual U17894EJ9V0UD 677
Table 20-2. Hardware Statuses After Reset Acknowledgment (1/3)
Hardware After Reset
AcknowledgmentNote 1
Program counter (PC) The contents of the
reset vector table
(0000H, 0001H) are set.
Stack pointer (SP) Undefined
Program status word (PSW) 06H
Data memory UndefinedNote 2 RAM
General-purpose registers UndefinedNote 2
Port registers (P0 to P8, P11 to P15) (output latches) 00H
PM0 to PM8, PM11, PM12, PM14, PM15 FFH Port mode registers
PM13 FEH
Port input mode registers 0, 4, 14 (PIM0, PIM4, PIM14) 00H
Port output mode registers 0, 4, 14 (POM0, POM4, POM14) 00H
Pull-up resistor option registers (PU0, PU1, PU3 to PU8, PU12 to PU14) 00H
Memory extension mode control register (MEM) 00H
Clock operation mode control register (CMC) 00H
Clock operation status control register (CSC) C0H
Processor mode control register (PMC) 00H
System clock control register (CKC) 09H
Oscillation stabilization time counter status register (OSTC) 00H
Oscillation stabilization time select register (OSTS) 07H
Noise filter enable registers 0, 1 (NFEN0, NFEN1) 00H
Peripheral enable registers 0, 1 (PER0, PER1) 00H
Internal high-speed oscillator trimming register (HIOTRM) 10H
Operation speed mode control register (OSMC) 00H
Timer data registers 00, 01, 02, 03, 04, 05, 06, 07 (TDR00, TDR01, TDR02,
TDR03, TDR04, TDR05, TDR06, TDR07)
0000H
Timer mode registers 00, 01, 02, 03, 04, 05, 06, 07 (TMR00, TMR01, TMR02,
TMR03, TMR04, TMR05, TMR06, TMR07)
0000H
Timer status registers 00, 01, 02, 03, 04, 05, 06, 07 (TSR00, TSR01, TSR02,
TSR03, TSR04, TSR05, TSR06, TSR07)
0000H
Timer input select register 0 (TIS0) 00H
Timer counter registers 00, 01, 02, 03, 04, 05, 06, 07 (TCR00, TCR01, TCR02,
TCR03, TCR04, TCR05, TCR06, TCR07)
FFFFH
Timer channel enable status register 0 (TE0) 0000H
Timer channel start register 0 (TS0) 0000H
Timer channel stop register 0 (TT0) 0000H
Timer clock select register 0 (TPS0) 0000H
Timer output register 0 (TO0) 0000H
Timer output enable register 0 (TOE0) 0000H
Timer output level register 0 (TOL0) 0000H
Timer array unit
(TAU)
Timer output mode register 0 (TOM0) 0000H
Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
2. When a reset is executed in the standby mode, the pre-reset status is held even after reset.
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Table 20-2. Hardware Statuses After Reset Acknowledgment (2/3)
Hardware Status After Reset
AcknowledgmentNote 1
Subcount register (RSUBC) 0000H
Second count register (SEC) 00H
Minute count register (MIN) 00H
Hour count register (HOUR) 12H
Day count register (DAY) 01H
Week count register (WEEK) 00H
Month count register (MONTH) 01H
Year count register (YEAR) 00H
Watch error correction register (SUBCUD) 00H
Alarm minute register (ALARMWM) 00H
Alarm hour register (ALARMWH) 12H
Alarm week register ALARMWW) 00H
Real-time counter control register 0 (RTCC0) 00H
Real-time counter control register 1 (RTCC1) 00H
Real-time counter
Real-time counter control register 2 (RTCC2) 00H
Clock output/buzzer
output controller
Clock output select registers 0, 1 (CKS0, CKS1) 00H
Watchdog timer Enable register (WDTE) 1AH/9AHNote 2
10-bit A/D conversion result register (ADCR) 0000H
8-bit A/D conversion result register (ADCRH) 00H
Mode register (ADM) 00H
Analog input channel specification register (ADS) 00H
A/D converter
A/D port configuration register (ADPC) 10H
8-bit D/A conversion value setting registers 0, 1 (DACS0, DACS1) 00H D/A converter
D/A converter mode register (DAM) 00H
Serial data registers 00, 01, 02, 03, 10, 11, 12, 13 (SDR00, SDR01,
SDR02, SDR03, SDR10, SDR11, SDR12, SDR13)
0000H
Serial status registers 00, 01, 02, 03, 10, 11, 12, 13 (SSR00, SSR01,
SSR02, SSR03, SSR10, SSR11, SSR12, SSR13)
0000H
Serial flag clear trigger registers 00, 01, 02, 03, 10, 11, 12, 13 (SIR00,
SIR01, SIR02, SIR03, SIR10, SIR11, SIR12, SIR13)
0000H
Serial mode registers 00, 01, 02, 03, 10, 11, 12, 13 (SMR00, SMR01,
SMR02, SMR03, SMR10, SMR11, SMR12, SMR13)
0020H
Serial communication operation setting registers 00, 01, 02, 03, 10, 11, 12,
13 (SCR00, SCR01, SCR02, SCR03, SCR10, SCR11, SCR12,
SCR13)
0087H
Serial channel enable status registers 0, 1 (SE0, SE1) 0000H
Serial channel start registers 0, 1 (SS0, SS1) 0000H
Serial channel stop registers 0, 1 (ST0, ST1) 0000H
Serial clock select registers 0, 1 (SPS0, SPS1) 0000H
Serial output registers 0, 1 (SO0, SO1) 0F0FH
Serial output registers 0, 1 (SO0, SO1) 0000H
Serial output level registers 0, 1 (SOL0, SOL1) 0000H
Serial array unit (SAU)
Input switch control register (ISC) 00H
Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
2. The reset value of WDTE is determined by the option byte setting.
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User’s Manual U17894EJ9V0UD 679
Table 20-2. Hardware Statuses After Reset Acknowledgment (3/3)
Hardware Status After Reset
AcknowledgmentNote 1
Shift register 0 (IIC0) 00H
Control register 0 (IICC0) 00H
Slave address register 0 (SVA0) 00H
Clock select register 0 (IICCL0) 00H
Function expansion register 0 (IICX0) 00H
Status register 0 (IICS0) 00H
Serial interface IIC0
Flag register 0 (IICF0) 00H
Multiplication input data register A (MULA) 0000H
Multiplication input data register B (MULB) 0000H
Higher multiplication result storage register (MULOH) 0000H
Multiplier
Lower multiplication result storage register (MULOL) 0000H
Key interrupt Key return mode register (KRM) 00H
Reset function Reset control flag register (RESF) 00HNote 2
Low-voltage detection register (LVIM) 00HNote 3 Low-voltage detector
Low-voltage detection level select register (LVIS) 0EHNote 2
Regulator Regulator mode control register (RMC) 00H
SFR address registers 0, 1 (DSA0, DSA1) 00H
RAM address registers 0L, 0H, 1L, 1H (DRA0L, DRA0H, DRA1L, DRA1H) 00H
Byte count registers 0L, 0H, 1L, 1H (DBC0L, DBC0H, DBC1L, DBC1H) 00H
Mode control registers 0, 1 (DMC0, DMC1) 00H
DMA controller
Operation control registers 0, 1 (DRC0, DRC1) 00H
Request flag registers 0L, 0H, 1L, 1H, 2L, 2H (IF0L, IF0H, IF1L, IF1H,
IF2L, IF2H)
00H
Mask flag registers 0L, 0H, 1L, 1H, 2L, 2H (MK0L, MK0H, MK1L,
MK1H, MK2L, MK2H)
FFH
Priority specification flag registers 00L, 00H, 01L, 01H, 02L, 02H, 10L,
10H, 11L, 11H, 12L, 12H (PR00L, PR00H, PR01L, PR01H, PR10L,
PR10H, PR11L, PR11H, PR02L, PR02H, PR12L, PR12H)
FFH
External interrupt rising edge enable registers 0, 1 (EGP0, EGP1) 00H
Interrupt
External interrupt falling edge enable registers 0, 1 (EGN0, EGN1) 00H
BCD correction circuit BCD correction result register (BCDADJ) Undefined
Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
2. These values vary depending on the reset source.
Reset Source
Register
RESET Input Reset by POC Reset by Execution of
Illegal Instruction
Reset by WDT Reset by LVI
TRAP bit Set (1) Held Held
WDRF bit Held Set (1) Held
RESF
LVIRF bit
Cleared (0) Cleared (0)
Held Held Set (1)
LVIS Cleared (0EH) Cleared (0EH) Cleared (0EH) Cleared (0EH) Held
3. This value varies depending on the reset source and the option byte.
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20.1 Register for Confirming Reset Source
Many internal reset generation sources exist in the 78K0R/KG3. The reset control flag register (RESF) is used to
store which source has generated the reset request.
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset by power-on-clear (POC) circuit, and reading RESF set RESF to 00H.
Figure 20-5. Format of Reset Control Flag Register (RESF)
Address: FFFA8H After reset: 00HNote 1 R
Symbol 7 6 5 4 3 2 1 0
RESF TRAP 0 0 WDRF 0 0 0 LVIRF
TRAP Internal reset request by execution of illegal instructionNote 2
0 Internal reset request is not generated, or RESF is cleared.
1 Internal reset request is generated.
WDRF Internal reset request by watchdog timer (WDT)
0 Internal reset request is not generated, or RESF is cleared.
1 Internal reset request is generated.
LVIRF Internal reset request by low-voltage detector (LVI)
0 Internal reset request is not generated, or RESF is cleared.
1 Internal reset request is generated.
Notes 1. The value after reset varies depending on the reset source.
2. When instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
Cautions 1. Do not read data by a 1-bit memory manipulation instruction.
2. When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, LVIRF flag may
become 1 from the beginning depending on the power-on waveform.
The status of RESF when a reset request is generated is shown in Table 20-3.
Table 20-3. RESF Status When Reset Request Is Generated
Reset Source
Flag
RESET Input Reset by POC Reset by Execution
of Illegal Instruction
Reset by WDT Reset by LVI
TRAP Set (1) Held Held
WDRF Held Set (1) Held
LVIRF
Cleared (0) Cleared (0)
Held Held Set (1)
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CHAPTER 21 POWER-ON-CLEAR CIRCUIT
21.1 Functions of Power-on-Clear Circuit
The power-on-clear circuit (POC) has the following functions.
• Generates internal reset signal at power on.
The reset signal is released when the supply voltage (VDD) exceeds 1.59 V ±0.09 V.
Caution If the low-voltage detector (LVI) is set to ON by an option byte by default, the reset signal is not
released until the supply voltage (VDD) exceeds 2.07 V ±0.2 V.
• Compares supply voltage (VDD) and detection voltage (VPOC = 1.59 V ±0.09 V), generates internal reset signal
when VDD < VPOC.
Caution If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF)
is cleared to 00H.
Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag
that indicates the reset source is located in the reset control flag register (RESF) for when an internal
reset signal is generated by the watchdog timer (WDT), low-voltage detector (LVI), or illegal
instruction execution. RESF is not cleared to 00H and the flag is set to 1 when an internal reset
signal is generated by WDT, LVI or illegal instruction execution. For details of RESF, see CHAPTER
20 RESET FUNCTION.
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21.2 Configuration of Power-on-Clear Circuit
The block diagram of the power-on-clear circuit is shown in Figure 21-1.
Figure 21-1. Block Diagram of Power-on-Clear Circuit
−
+
Reference
voltage
source
Internal reset signal
V
DD
V
DD
21.3 Operation of Power-on-Clear Circuit
• An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the
detection voltage (VPOC = 1.59 V ±0.09 V), the reset status is released.
Caution If the low-voltage detector (LVI) is set to ON by an option byte by default, the reset signal is not
released until the supply voltage (VDD) exceeds 2.07 V ±0.2 V.
• The supply voltage (VDD) and detection voltage (VPOC = 1.59 V ±0.09 V) are compared. When VDD < VPOC, the
internal reset signal is generated.
The timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is shown
below.
CHAPTER 21 POWER-ON-CLEAR CIRCUIT
User’s Manual U17894EJ9V0UD 683
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (1/2)
(1) When LVI is OFF upon power application (option byte: LVIOFF = 1)
Internal high-speed
oscillation clock (f
IH
)
High-speed
system clock (f
MX
)
(when X1 oscillation
is selected)
Starting oscillation is
specified by software.
V
POC
= 1.59 V (TYP.)
V
LVI
Operation
stops
Wait for voltage
stabilization
Normal operation
(internal high-speed
oscillation clock)
Note 5
Operation stops
Reset period
(oscillation
stop)
Reset period
(oscillation
stop)
Wait for oscillation
accuracy stabilization
Note 4
Normal operation
(internal high-speed
oscillation clock)
Note 5
Starting oscillation is
specified by software. Starting oscillation is
specified by software.
CPU
0 V
Supply voltage
(V
DD
)
1.8 V
Note 1
Wait for voltage
stabilization
Normal operation
(internal high-speed
oscillation clock)
Note 5
0.5 V/ms (MIN.)
Note 2
Set LVI to be
used for reset
Set LVI to be
used for reset
Set LVI to be
used for interrupt
Internal reset signal
Reset processing
Reset processing (43 to 160 s)
Reset processing
Wait for oscillation
accuracy stabilization
Note 3
Wait for oscillation
accuracy stabilization
Note 3
1.92 to 6.17 ms
μ
1.92 to 6.17 ms
Notes 1. The operation guaranteed range is 1.8 V ≤ VDD ≤ 5.5 V. To make the state at lower than 1.8 V reset
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
2. If the rate at which the voltage rises to 1.8 V after power application is slower than 0.5 V/ms (MIN.),
input a low level to the RESET pin before the voltage reaches to 1.8 V, or set LVI to ON by default by
using an option byte (option byte: LVIOFF = 0).
3. The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
4. The internal reset processing time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
5. The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 22
LOW-VOLTAGE DETECTOR).
Remark V
LVI: LVI detection voltage
V
POC: POC detection voltage
CHAPTER 21 POWER-ON-CLEAR CIRCUIT
User’s Manual U17894EJ9V0UD
684
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (2/2)
(2) When LVI is ON upon power application (option byte: LVIOFF = 0)
Internal high-speed
oscillation clock (f
IH
)
High-speed
system clock (f
MX
)
(when X1 oscillation
is selected)
Starting oscillation is
specified by software.
Internal reset signal
V
LVI
= 2.07 V (TYP.)
VPOC = 1.59 V (TYP.)
V
LVI
Operation
stops
Note 4
Normal operation
(internal high-speed
oscillation clock)
Note 2
Normal operation
(internal high-speed
oscillation clock)
Note 2
Operation stops
Reset period
(oscillation
stop)
Normal operation
(internal high-speed
oscillation clock)
Note 2
Starting oscillation is
specified by software.
Starting oscillation is
specified by software.
CPU
0 V
Supply voltage
(V
DD
)
1.8 V
Note 1
Reset processing
(43 to 160 s)
POC processing
Reset processing (43 to 160 s)
Set LVI
(V
LVI
= 2.07 V)
to be used for
reset (default)
Set LVI
(V
LVI
= 2.07 V)
to be used for
reset (default)
Change LVI
detection
voltage (V
LVI
)
Set LVI to be
used for interrupt
Wait for oscillation
accuracy stabilization
Note 3
Wait for oscillation
accuracy stabilization
Note 3
Wait for oscillation
accuracy stabilization
Note 3
μ
μ
Reset period
(oscillation
stop)
Reset processing
(43 to 160 s)
POC processing
μ
Note 4
Notes 1. The operation guaranteed range is 1.8 V ≤ VDD ≤ 5.5 V. To make the state at lower than 1.8 V reset
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
2. The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
3. The internal reset processing time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
4. The following times are required between reaching the POC detection voltage (1.59 V (TYP.)) and
starting normal operation.
• When the time to reach 2.07 V (TYP.) from 1.59 V (TYP.) is less than 6.17 ms:
A POC processing time of 1.92 to 6.33 ms is required between reaching 1.59 V (TYP.) and
starting normal operation.
• When the time to reach 2.07 V (TYP.) from 1.59 V (TYP.) is greater than 6.17 ms:
A reset processing time of 43 to 160
μ
s is required between reaching 2.07 V (TYP.) and starting
normal operation.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 22
LOW-VOLTAGE DETECTOR).
Remark V
LVI: LVI detection voltage
V
POC: POC detection voltage
CHAPTER 21 POWER-ON-CLEAR CIRCUIT
User’s Manual U17894EJ9V0UD 685
21.4 Cautions for Power-on-Clear Circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection
voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
Figure 21-3. Example of Software Processing After Reset Release (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
;Check the reset source, etc.Note 2
Note 1
Reset
Initialization
processing <1>
50 ms has passed?
(TMIF0n = 1?)
Initialization
processing <2>
Setting timer array unit
(to measure 50 ms)
; Initial setting for port,
Setting of division ratio of system clock,
such as setting of timer or A/D converter
Yes
No
Power-on-clear
Clearing WDT
;f
CLK = Internal high-speed oscillation clock (8.4 MHz (MAX.)) (default)
Source: fCLK (8.4 MHz (MAX.))/212,
where comparison value = 102: ≅ 50 ms
Timer starts (TS0n = 1).
Notes 1. If reset is generated again during this period, initialization processing <2> is not started.
2. A flowchart is shown on the next page.
Remark n = 0 to 7
CHAPTER 21 POWER-ON-CLEAR CIRCUIT
User’s Manual U17894EJ9V0UD
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Figure 21-3. Example of Software Processing After Reset Release (2/2)
• Checking reset source
Yes
No
Check reset source
Power-on-clear/external
reset generated
Reset processing by
watchdog timer
Reset processing by
low-voltage detector
No
WDRF of RESF
register = 1?
LVIRF of RESF
register = 1?
Yes
No
Reset processing by
illegal instruction executionNote
TRAP of RESF
register = 1?
Yes
Note When instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
User’s Manual U17894EJ9V0UD 687
CHAPTER 22 LOW-VOLTAGE DETECTOR
22.1 Functions of Low-Voltage Detector
The low-voltage detector (LVI) has the following functions.
• The LVI circuit compares the supply voltage (VDD) with the detection voltage (VLVI) or the input voltage from an
external input pin (EXLVI) with the detection voltage (VEXLVI = 1.21 V ±0.1 V), and generates an internal resetNote
or internal interrupt signal.
• The low-voltage detector (LVI) can be set to ON by an option byte by default. If it is set to ON to raise the power
supply from the POC detection voltage or lower, the internal reset signalNote is generated when the supply
voltage (VDD) < detection voltage (VLVI = 2.07 V ±0.2 V). After that, the internal reset signalNote is generated
when the supply voltage (VDD) < detection voltage (VLVI = 2.07 V ±0.1 V).
• The supply voltage (VDD) or the input voltage from the external input pin (EXLVI) can be selected to be detected
by software.
• A reset or an interrupt can be selected to be generated after detection by software.
• Detection levels (VLVI,16 levels) of supply voltage can be changed by software.
• Operable in STOP mode.
Note See the timing in Figure 21-2 (2) When LVI is ON upon power application (option byte: LVIOFF = 0)
for the reset processing time until the normal operation is entered after the LVI reset is released.
The reset and interrupt signals are generated as follows depending on selection by software.
Selection of Level Detection of Supply Voltage (VDD)
(LVISEL = 0)
Selection Level Detection of Input Voltage from
External Input Pin (EXLVI) (LVISEL = 1)
Selects reset (LVIMD = 1). Selects interrupt (LVIMD = 0). Selects reset (LVIMD = 1). Selects interrupt (LVIMD = 0).
Generates an internal reset
signal when VDD < VLVI and
releases the reset signal when
VDD ≥ VLVI.
Generates an internal interrupt
signal when VDD drops lower
than VLVI (VDD < VLVI) or when
VDD becomes VLVI or higher
(VDD ≥ VLVI).
Generates an internal reset
signal when EXLVI < VEXLVI
and releases the reset signal
when EXLVI ≥ VEXLVI.
Generates an internal interrupt
signal when EXLVI drops
lower than VEXLVI (EXLVI <
VEXLVI) or when EXLVI
becomes VEXLVI or higher
(EXLVI ≥ VEXLVI).
Remark LVISEL: Bit 2 of low-voltage detection register (LVIM)
LVIMD: Bit 1 of LVIM
While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input
pin is more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0
of LVIM).
When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if
reset occurs. For details of RESF, see CHAPTER 20 RESET FUNCTION.
CHAPTER 22 LOW-VOLTAGE DETECTOR
User’s Manual U17894EJ9V0UD
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22.2 Configuration of Low-Voltage Detector
The block diagram of the low-voltage detector is shown in Figure 22-1.
Figure 22-1. Block Diagram of Low-Voltage Detector
LVIS1 LVIS0 LVION
−
+
Reference
voltage
source
VDD
Internal bus
N-ch
Low-voltage detection level
select register (LVIS)
Low-voltage detection register
(LVIM)
LVIS2
LVIS3 LVIF
INTLVI
Internal reset signal
4
LVISEL
EXLVI/P120/
INTP0
LVIMD
VDD
Low-voltage detection
level selector
Selector
Selector
22.3 Registers Controlling Low-Voltage Detector
The low-voltage detector is controlled by the following registers.
• Low-voltage detection register (LVIM)
• Low-voltage detection level select register (LVIS)
• Port mode register 12 (PM12)
(1) Low-voltage detection register (LVIM)
This register sets low-voltage detection and the operation mode.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
CHAPTER 22 LOW-VOLTAGE DETECTOR
User’s Manual U17894EJ9V0UD 689
Figure 22-2. Format of Low-Voltage Detection Register (LVIM)
<0>
LVIF
<1>
LVIMD
<2>
LVISEL
3
0
4
0
5
0
6
0
<7>
LVION
Symbol
LVIM
Address: FFFA9H After reset: 00H
Note 1
R/W
Note 2
LVIONNotes 3, 4 Enables low-voltage detection operation
0 Disables operation
1 Enables operation
LVISELNote 3 Voltage detection selection
0 Detects level of supply voltage (VDD)
1 Detects level of input voltage from external input pin (EXLVI)
LVIMDNote 3 Low-voltage detection operation mode (interrupt/reset) selection
0 • LVISEL = 0: Generates an internal interrupt signal when the supply voltage (VDD) drops
lower than the detection voltage (VLVI) (VDD < VLVI) or when VDD becomes
VLVI or higher (VDD ≥ VLVI).
• LVISEL = 1: Generates an interrupt signal when the input voltage from an external
input pin (EXLVI) drops lower than the detection voltage (VEXLVI) (EXLVI <
VEXLVI) or when EXLVI becomes VEXLVI or higher (EXLVI ≥ VEXLVI).
1 • LVISEL = 0: Generates an internal reset signal when the supply voltage (VDD) <
detection voltage (VLVI) and releases the reset signal when VDD ≥ VLVI.
• LVISEL = 1: Generates an internal reset signal when the input voltage from an
external input pin (EXLVI) < detection voltage (VEXLVI) and releases the
reset signal when EXLVI ≥ VEXLVI.
LVIF Low-voltage detection flag
0 • LVISEL = 0: Supply voltage (VDD) ≥ detection voltage (VLVI), or when LVI operation is
disabled
• LVISEL = 1: Input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI),
or when LVI operation is disabled
1 • LVISEL = 0: Supply voltage (VDD) < detection voltage (VLVI)
• LVISEL = 1: Input voltage from external input pin (EXLVI) < detection voltage (VEXLVI)
Notes 1. The reset value changes depending on the reset source and the setting of the option byte.
This register is not cleared (00H) by LVI reset.
It is set to “82H” when a reset signal other than LVI is applied if option byte LVIOFF = 0, and to “00H”
if option byte LVIOFF = 1.
2. Bit 0 is read-only.
3. LVION, LVIMD, and LVISEL are cleared to 0 in the case of a reset other than an LVI reset. These
are not cleared to 0 in the case of an LVI reset.
CHAPTER 22 LOW-VOLTAGE DETECTOR
User’s Manual U17894EJ9V0UD
690
Note 4. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use software to wait
for the following periods of time, between when LVION is set to 1 and when the voltage is confirmed
with LVIF.
• Operation stabilization time (10
μ
s (MAX.))
• Minimum pulse width (200
μ
s (MIN.))
• Detection delay time (200
μ
s (MAX.))
The LVIF value for these periods may be set/cleared regardless of the voltage level, and can
therefore not be used. Also, the LVIIF interrupt request flag may be set to 1 in these periods.
Cautions 1. To stop LVI, follow either of the procedures below.
• When using 8-bit memory manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
2. Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
3. When LVI is used in interrupt mode (LVIMD = 0) and LVISEL is set to 0, an interrupt request
signal (INTLVI) that disables LVI operation (clears LVION) when the supply voltage (VDD) is
less than or equal to the detection voltage (VLVI) (if LVISEL = 1, input voltage of external
input pin (EXLVI) is less than or equal to the detection voltage (VEXLVI)) is generated and
LVIIF may be set to 1.
CHAPTER 22 LOW-VOLTAGE DETECTOR
User’s Manual U17894EJ9V0UD 691
(2) Low-voltage detection level select register (LVIS)
This register selects the low-voltage detection level.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation input sets this register to 0EH.
Figure 22-3. Format of Low-Voltage Detection Level Select Register (LVIS)
0
LVIS0
1
LVIS1
2
LVIS2
3
LVIS3
4
0
5
0
6
0
7
0
Symbol
LVIS
Address: FFFAAH After reset: 0EH
Note
R/W
LVIS3 LVIS2 LVIS1 LVIS0 Detection level
0 0 0 0 VLVI0 (4.22 ±0.1 V)
0 0 0 1 VLVI1 (4.07 ±0.1 V)
0 0 1 0 VLVI2 (3.92 ±0.1 V)
0 0 1 1 VLVI3 (3.76 ±0.1 V)
0 1 0 0 VLVI4 (3.61 ±0.1 V)
0 1 0 1 VLVI5 (3.45 ±0.1 V)
0 1 1 0 VLVI6 (3.30 ±0.1 V)
0 1 1 1 VLVI7 (3.15 ±0.1 V)
1 0 0 0 VLVI8 (2.99 ±0.1 V)
1 0 0 1 VLVI9 (2.84 ±0.1 V)
1 0 1 0 VLVI10 (2.68 ±0.1 V)
1 0 1 1 VLVI11 (2.53 ±0.1 V)
1 1 0 0 VLVI12 (2.38 ±0.1 V)
1 1 0 1 VLVI13 (2.22 ±0.1 V)
1 1 1 0 VLVI14 (2.07 ±0.1 V)
1 1 1 1 VLVI15 (1.91 ±0.1 V)
Note The reset value changes depending on the reset source.
If the LVIS register is reset by LVI, it is not reset but holds the current value. The value of this
register is reset to “0EH” if a reset other than by LVI is effected.
Caution 1. Be sure to clear bits 4 to 7 to “0”.
CHAPTER 22 LOW-VOLTAGE DETECTOR
User’s Manual U17894EJ9V0UD
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Cautions 2. Change the LVIS value with either of the following methods.
• When changing the value after stopping LVI
<1> Stop LVI (LVION = 0).
<2> Change the LVIS register.
<3> Set to the mode used as an interrupt (LVIMD = 0).
<4> Mask LVI interrupts (LVIMK = 1).
<5> Enable LVI operation (LVION = 1).
<6> Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
because an LVIIF flag may be set when LVI operation is enabled.
• When changing the value after setting to the mode used as an interrupt (LVIMD =
0)
<1> Mask LVI interrupts (LVIMK = 1).
<2> Set to the mode used as an interrupt (LVIMD = 0).
<3> Change the LVIS register.
<4> Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
because an LVIIF flag may be set when the LVIS register is changed.
3. When an input voltage from the external input pin (EXLVI) is detected, the detection
voltage (VEXLVI) is fixed. Therefore, setting of LVIS is not necessary.
(3) Port mode register 12 (PM12)
When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this
time, the output latch of P120 may be 0 or 1.
PM12 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 22-4. Format of Port Mode Register 12 (PM12)
0
PM120
1
1
2
1
3
1
4
1
5
1
6
1
7
1
Symbol
PM12
Address: FFF2CH After reset: FFH R/W
PM120 P120 pin I/O mode selection
0 Output mode (output buffer on)
1 Input mode (output buffer off)
CHAPTER 22 LOW-VOLTAGE DETECTOR
User’s Manual U17894EJ9V0UD 693
22.4 Operation of Low-Voltage Detector
The low-voltage detector can be used in the following two modes.
(1) Used as reset (LVIMD = 1)
• If LVISEL = 0, compares the supply voltage (VDD) and detection voltage (VLVI), generates an internal reset
signal when VDD < VLVI, and releases internal reset when VDD ≥ VLVI.
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (VEXLVI),
generates an internal reset signal when EXLVI < VEXLVI, and releases internal reset when EXLVI ≥ VEXLVI.
Remark The low-voltage detector (LVI) can be set to ON by an option byte by default. If it is set to ON to
raise the power supply from the POC detection voltage or lower, the internal reset signal is
generated when the supply voltage (VDD) < detection voltage (VLVI = 2.07 V ±0.2 V). After that, the
internal reset signal is generated when the supply voltage (VDD) < detection voltage (VLVI = 2.07 V
±0.1 V).
(2) Used as interrupt (LVIMD = 0)
• If LVISEL = 0, compares the supply voltage (VDD) and detection voltage (VLVI). When VDD drops lower than
VLVI (VDD < VLVI) or when VDD becomes VLVI or higher (VDD ≥ VLVI), generates an interrupt signal (INTLVI).
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (VEXLVI = 1.21
V ±0.1 V). When EXLVI drops lower than VEXLVI (EXLVI < VEXLVI) or when EXLVI becomes VEXLVI or higher
(EXLVI ≥ VEXLVI), generates an interrupt signal (INTLVI).
While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input
pin is more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0
of LVIM).
Remark LVIMD: Bit 1 of low-voltage detection register (LVIM)
LVISEL: Bit 2 of LVIM
CHAPTER 22 LOW-VOLTAGE DETECTOR
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22.4.1 When used as reset
(1) When detecting level of supply voltage (VDD)
(a) When LVI default start function stopped is set (option byte: LVIOFF = 1)
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
(VDD)) (default value).
<3> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level
selection register (LVIS).
<4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<5> Use software to wait for the following periods of time (Total 410
μ
s).
• Operation stabilization time (10
μ
s (MAX.))
• Minimum pulse width (200
μ
s (MIN.))
• Detection delay time (200
μ
s (MAX.))
<6> Wait until it is checked that (supply voltage (VDD) ≥ detection voltage (VLVI)) by bit 0 (LVIF) of LVIM.
<7> Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected).
Figure 22-5 shows the timing of the internal reset signal generated by the low-voltage detector. The
numbers in this timing chart correspond to <1> to <7> above.
Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately
after the processing in <4>.
2. If supply voltage (VDD) ≥ detection voltage (VLVI) when LVIMD is set to 1, an internal
reset signal is not generated.
• When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
• When using 1-bit memory manipulation instruction:
Clear LVIMD to 0 and then LVION to 0.
CHAPTER 22 LOW-VOLTAGE DETECTOR
User’s Manual U17894EJ9V0UD 695
Figure 22-5. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Bit: LVISEL = 0, Option Byte: LVIOFF = 1)
L
Set LVI to be
used for reset
Time
Supply voltage (VDD)
VLVI
V
POC
= 1.59 V (TYP.)
LVIMK flag
(set by software)
LVIF flag
LVIRF flagNote 3
LVI reset signal
POC reset signal
Internal reset signal
LVION flag
(set by software)
LVIMD flag
(set by software)
LVISEL flag
(set by software)
HNote 1
<1>
<3>
<2>
<4>
<5> Wait time
<6>
Note 2
<7>
Cleared by
software
Cleared by
software
Not cleared
Not cleared
Not cleared
Not cleared
Clear
Clear
Clear
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. The LVIIF flag of the interrupt request flag registers and the LVIF flag may be set (1).
3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 20
RESET FUNCTION.
Remark <1> to <7> in Figure 22-5 above correspond to <1> to <7> in the description of “When starting
operation” in 22.4.1 (1) (a) When LVI default start function stopped is set (option byte: LVIOFF = 1).
CHAPTER 22 LOW-VOLTAGE DETECTOR
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(b) When LVI default start function enabled is set (option byte: LVIOFF = 0)
• When starting operation
Start in the following initial setting state.
• Set bit 7 (LVION) of LVIM to 1 (enables LVI operation)
• Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
(VDD))
• Set the low-voltage detection level selection register (LVIS) to 0EH (default value: VLVI = 2.07 V ±0.1 V).
• Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected)
• Set bit 0 (LVIF) of LVIM to 0 (“Supply voltage (VDD) ≥ detection voltage (VLVI)”)
Figure 22-6 shows the timing of the internal reset signal generated by the low-voltage detector.
• When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
• When using 1-bit memory manipulation instruction:
Clear LVIMD to 0 and then LVION to 0.
Caution Even when the LVI default start function is used, if it is set to LVI operation prohibition by
the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU starts
after reset release. There is a period when low-voltage detection cannot be performed
normally, however, when a reset occurs due to WDT and illegal instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
μ
s max.,
LVION = 1 is set upon reset occurrence, and the CPU starts operating without waiting for
the LVI stabilization time.
CHAPTER 22 LOW-VOLTAGE DETECTOR
User’s Manual U17894EJ9V0UD 697
Figure 22-6. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Bit: LVISEL = 0, Option Byte: LVIOFF = 0)
VLVI value after a change
L
H
H
Supply voltage (VDD)
LVIMK flag
(set by software)
LVIF flag
LVIRF flag
LVI reset signal
POC reset signal
Internal reset signal
LVION flag
(set by software)
LVIMD flag
(set by software)
LVISEL flag
(set by software)
V
LVI
= 2.07 V (TYP.)
V
POC
= 1.59 V (TYP.)
HNote 1
Time
Not
cleared
Not cleared
Not cleared
Clear
Clear
Cleared by
software
Cleared by
software
Cleared by
software
Not
cleared
Note 2
Interrupt operation mode is set by setting
LVIMD to 0 (LVI interrupt is masked)
Change LVI detection
voltage (VLVI)
Reset mode is set by
setting LVIMD to 1
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. LVIRF is bit 0 of the reset control flag register (RESF).
When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, the LVIRF flag may
become 1 from the beginning due to the power-on waveform.
For details of RESF, see CHAPTER 20 RESET FUNCTION.
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(2) When detecting level of input voltage from external input pin (EXLVI)
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from
external input pin (EXLVI)).
<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<4> Use software to wait for the following periods of time (Total 410
μ
s).
• Operation stabilization time (10
μ
s (MAX.))
• Minimum pulse width (200
μ
s (MIN.))
• Detection delay time (200
μ
s (MAX.))
<5> Wait until it is checked that (input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI =
1.21 V (TYP.))) by bit 0 (LVIF) of LVIM.
<6> Set bit 1 (LVIMD) of LVIM to 1 (generates reset signal when the level is detected).
Figure 22-7 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers
in this timing chart correspond to <1> to <6> above.
Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately
after the processing in <3>.
2. If input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI = 1.21 V (TYP.))
when LVIMD is set to 1, an internal reset signal is not generated.
3. Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
• When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
• When using 1-bit memory manipulation instruction:
Clear LVIMD to 0 and then LVION to 0.
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Figure 22-7. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Bit: LVISEL = 1)
VEXLVI
Set LVI to be
used for reset
LVIMK flag
(set by software)
LVIF flag
LVIRF flagNote 3
LVI reset signal
Internal reset signal
LVION flag
(set by software)
LVIMD flag
(set by software)
LVISEL flag
(set by software)
<1>
<2>
<3>
<4> Wait time
<5>
<6>
Note 2
Not cleared Not cleared
Not cleared Not cleared
Not cleared Not cleared
Not cleared
Not cleared
Not cleared
Cleared by
software
Cleared by
software
Time
HNote 1
Input voltage from
external input pin (EXLVI)
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. The LVIIF flag of the interrupt request flag registers and the LVIF flag may be set (1).
3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 20
RESET FUNCTION.
Remark <1> to <6> in Figure 22-7 above correspond to <1> to <6> in the description of “When starting
operation” in 22.4.1 (2) When detecting level of input voltage from external input pin (EXLVI).
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22.4.2 When used as interrupt
(1) When detecting level of supply voltage (VDD)
(a) When LVI default start function stopped is set (option byte: LVIOFF = 1)
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
(VDD)) (default value).
Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value).
<3> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level
selection register (LVIS).
<4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<5> Use software to wait for the following periods of time (Total 410
μ
s).
• Operation stabilization time (10
μ
s (MAX.))
• Minimum pulse width (200
μ
s (MIN.))
• Detection delay time (200
μ
s (MAX.))
<6> Confirm that “supply voltage (VDD) ≥ detection voltage (VLVI)” when detecting the falling edge of VDD,
or “supply voltage (VDD) < detection voltage (VLVI)” when detecting the rising edge of VDD, at bit 0
(LVIF) of LVIM.
<7> Clear the interrupt request flag of LVI (LVIIF) to 0.
<8> Release the interrupt mask flag of LVI (LVIMK).
<9> Execute the EI instruction (when vector interrupts are used).
Figure 22-8 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in
this timing chart correspond to <1> to <8> above.
• When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
• When using 1-bit memory manipulation instruction:
Clear LVION to 0.
CHAPTER 22 LOW-VOLTAGE DETECTOR
User’s Manual U17894EJ9V0UD 701
Figure 22-8. Timing of Low-Voltage Detector Interrupt Signal Generation
(Bit: LVISEL = 0, Option Byte: LVIOFF = 1)
L
L
Supply voltage (V
DD
)
LVIMK flag
(set by software)
LVIF flag
INTLVI
LVIIF flag
Internal reset signal
LVION flag
(set by software)
LVISEL flag
(set by software)
LVIMD flag
(set by software)
V
LVI
VPOC = 1.59 V (TYP.)
Time
<1>
Note 1
<2>
<8> Cleared by software
Note 3 Note 3
<5> Wait time
<4>
<6>
Note 2
Note 2
Note 2
<7>
Cleared by software
<3>
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1).
3. If LVI operation is disabled when the supply voltage (VDD) is less than or equal to the detection voltage
(VLVI), an interrupt request signal (INTLVI) is generated and LVIIF may be set to 1.
Remark <1> to <8> in Figure 22-8 above correspond to <1> to <8> in the description of “When starting
operation” in 22.4.2 (1) (a) When LVI default start function stopped is set (option byte: LVIOFF = 1).
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(b) When LVI default start function enabled is set (option byte: LVIOFF = 0)
• When starting operation
<1> Start in the following initial setting state.
• Set bit 7 (LVION) of LVIM to 1 (enables LVI operation)
• Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply
voltage (VDD))
• Set the low-voltage detection level selection register (LVIS) to 0EH (default value: VLVI = 2.07 V
±0.1 V).
• Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected)
• Set bit 0 (LVIF) of LVIM to 0 (Detects falling edge “Supply voltage (VDD) ≥ detection voltage
(VLVI)”)
<2> Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default
value).
<3> Release the interrupt mask flag of LVI (LVIMK).
<4> Execute the EI instruction (when vector interrupts are used).
Figure 22-9 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in
this timing chart correspond to <1> to <3> above.
• When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
• When using 1-bit memory manipulation instruction:
Clear LVION to 0.
Cautions 1. Even when the LVI default start function is used, if it is set to LVI operation prohibition by
the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU starts
after reset release. There is a period when low-voltage detection cannot be performed
normally, however, when a reset occurs due to WDT and illegal instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
μ
s max.,
LVION = 1 is set upon reset occurrence, and the CPU starts operating without waiting
for the LVI stabilization time.
2. When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, the LVIRF flag
may become 1 from the beginning due to the power-on waveform.
For details of RESF, see CHAPTER 20 RESET FUNCTION.
CHAPTER 22 LOW-VOLTAGE DETECTOR
User’s Manual U17894EJ9V0UD 703
Figure 22-9. Timing of Low-Voltage Detector Interrupt Signal Generation
(Bit: LVISEL = 0, Option Byte: LVIOFF = 0)
L
Supply voltage (V
DD
)
LVIMK flag
(set by software)
LVIF flag
INTLVI
LVIIF flag
Internal reset signal
LVION flag
(set by software)
LVISEL flag
(set by software)
LVIMD flag
(set by software)
V
LVI
= 2.07 V (TYP.)
Mask LVI interrupts
(LVIMK = 1)
V
POC
= 1.59 V (TYP.)
<1>
Note 1
<3> Cleared by software
Cleared by software
Note 2 Note 2
Note 3
<2>
Time
Change LVI detection
voltage (VLVI)
Cancelling the LVI interrupt
mask (LVIMK = 0)
V
LVI
value after a change
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. If LVI operation is disabled when the supply voltage (VDD) is less than or equal to the detection voltage
(VLVI), an interrupt request signal (INTLVI) is generated and LVIIF may be set to 1.
3. The LVIIF flag may be set when the LVI detection voltage is changed.
Remark <1> to <3> in Figure 22-9 above correspond to <1> to <3> in the description of “When starting
operation” in 22.4.2 (1) (b) When LVI default start function enabled is set (option byte: LVIOFF = 0).
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(2) When detecting level of input voltage from external input pin (EXLVI)
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from
external input pin (EXLVI)).
Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value).
<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<4> Use software to wait for the following periods of time (Total 410
μ
s).
• Operation stabilization time (10
μ
s (MAX.))
• Minimum pulse width (200
μ
s (MIN.))
• Detection delay time (200
μ
s (MAX.))
<5> Confirm that “input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI = 1.21 V (TYP.))”
when detecting the falling edge of EXLVI, or “input voltage from external input pin (EXLVI) < detection
voltage (VEXLVI = 1.21 V (TYP.))” when detecting the rising edge of EXLVI, at bit 0 (LVIF) of LVIM.
<6> Clear the interrupt request flag of LVI (LVIIF) to 0.
<7> Release the interrupt mask flag of LVI (LVIMK).
<8> Execute the EI instruction (when vector interrupts are used).
Figure 22-10 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in
this timing chart correspond to <1> to <7> above.
Caution The input voltage from the external input pin (EXLVI) must be EXLVI < VDD.
• When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
• When using 1-bit memory manipulation instruction:
Clear LVION to 0.
CHAPTER 22 LOW-VOLTAGE DETECTOR
User’s Manual U17894EJ9V0UD 705
Figure 22-10. Timing of Low-Voltage Detector Interrupt Signal Generation
(Bit: LVISEL = 1)
V
EXLVI
L
LVIMK flag
(set by software)
LVIF flag
INTLVI
LVIIF flag
LVION flag
(set by software)
LVISEL flag
(set by software)
LVIMD flag
(set by software)
Input voltage from
external input pin (EXLVI)
Time
<1>
Note 1
<7> Cleared by software
<2>
<3>
<5>
Note 2
Note 2
Note 2
<6>
Cleared by software
<4> Wait time
Note 3 Note 3
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1).
3. If LVI operation is disabled when the input voltage of external input pin (EXLVI) is less than or equal to
the detection voltage (VEXLVI), an interrupt request signal (INTLVI) is generated and LVIIF may be set to
1.
Remark <1> to <7> in Figure 22-10 above correspond to <1> to <7> in the description of “When starting
operation” in 22.4.2 (2) When detecting level of input voltage from external input pin (EXLVI).
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22.5 Cautions for Low-Voltage Detector
(1) Measures method when supply voltage (VDD) frequently fluctuates in the vicinity of the LVI detection
voltage (VLVI)
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection
voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used.
Operation example 1: When used as reset
The system may be repeatedly reset and released from the reset status.
The time from reset release through microcontroller operation start can be set arbitrarily by the following
action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports (see Figure 22-11).
Remark If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to “1”, the meanings of the above
words change as follows.
• Supply voltage (VDD) → Input voltage from external input pin (EXLVI)
• Detection voltage (VLVI) → Detection voltage (VEXLVI = 1.21 V)
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Figure 22-11. Example of Software Processing After Reset Release (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage
;Check the reset source, etc.
Note
; Setting of detection level by LVIS
The low-voltage detector operates (LVION = 1).
Reset
Initialization
processing <1>
50 ms has passed?
(TMIF0n = 1?)
Initialization
processing <2>
Setting timer array unit
(to measure 50 ms)
; Initial setting for port,
Setting of division ratio of system clock,
such as setting of timer or A/D converter
Yes
No
Setting LVI
Clearing WDT
Detection
voltage or higher
(LVIF = 0?)
Yes
Restarting timer array unit
(TT0n = 1 → TS0n = 1)
No
; The timer counter is cleared and the timer is started.
LVI reset
;f
CLK
= Internal high-speed oscillation clock (8.4 MHz (MAX.)) (default)
Source: f
CLK
(8.4 MHz (MAX.))/2
12
,
Where comparison value = 102: ≅ 50 ms
Timer starts (TS0n = 1).
Note A flowchart is shown on the next page.
Remarks 1. n = 0 to 7
2. If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to “1”, the meanings of the above
words change as follows.
• Supply voltage (VDD) → Input voltage from external input pin (EXLVI)
• Detection voltage (VLVI) → Detection voltage (VEXLVI = 1.21 V)
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Figure 22-11. Example of Software Processing After Reset Release (2/2)
• Checking reset source
Yes
No
Check reset source
Power-on-clear/external
reset generated
Reset processing by
watchdog timer
Reset processing by
low-voltage detector
Yes
WDRF of RESF
register = 1?
LVIRF of RESF
register = 1?
Yes
No
Reset processing by
illegal instruction executionNote
TRAP of RESF
register = 1?
No
Note When instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
Remark If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to “1”, the meanings of the above
words change as follows.
• Supply voltage (VDD) → Input voltage from external input pin (EXLVI)
• Detection voltage (VLVI) → Detection voltage (VEXLVI = 1.21 V)
CHAPTER 22 LOW-VOLTAGE DETECTOR
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Operation example 2: When used as interrupt
Interrupt requests may be generated frequently.
Take the following action.
<Action>
Confirm that “supply voltage (VDD) ≥ detection voltage (VLVI)” when detecting the falling edge of VDD, or
“supply voltage (VDD) < detection voltage (VLVI)” when detecting the rising edge of VDD, in the servicing routine
of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 1 (LVIIF) of
interrupt request flag register 0L (IF0L) to 0.
For a system with a long supply voltage fluctuation period near the LVI detection voltage, take the above
action after waiting for the supply voltage fluctuation time.
Remark If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to “1”, the meanings of the above
words change as follows.
• Supply voltage (VDD) → Input voltage from external input pin (EXLVI)
• Detection voltage (VLVI) → Detection voltage (VEXLVI = 1.21 V)
(2) Delay from the time LVI reset source is generated until the time LVI reset has been generated or released
There is some delay from the time supply voltage (VDD) < LVI detection voltage (VLVI) until the time LVI reset has
been generated.
In the same way, there is also some delay from the time LVI detection voltage (VLVI) ≤ supply voltage (VDD) until
the time LVI reset has been released (see Figure 22-12).
See the timing in Figure 21-2 (2) When LVI is ON upon power application (option byte: LVIOFF = 0) for the
reset processing time until the normal operation is entered after the LVI reset is released.
Figure 22-12. Delay from the Time LVI Reset Source Is Generated until the Time LVI Reset Has Been Generated or Released
Supply voltage (V
DD
)
V
LVI
LVIF flag
LVI reset signal
<1>
Time
<2> <1> <2>
<1> : Minimum pulse width (200
μ
s (MIN.))
<2> : Detection delay time (200
μ
s (MAX.))
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CHAPTER 23 REGULATOR
23.1 Regulator Overview
The 78K0R/KG3 contains a circuit for operating the device with a constant voltage. At this time, in order to stabilize
the regulator output voltage, connect the REGC pin to VSS via a capacitor (0.47 to 1
μ
F). However, when using the
STOP mode that has been entered since operation of the internal high-speed oscillation clock and external main
system clock, 0.47
μ
F is recommended. Also, use a capacitor with good characteristics, since it is used to stabilize
internal voltage.
The regulator output voltage is normally 2.5 V (TYP.), and in the low consumption current mode, 1.8 V (TYP.).
23.2 Registers Controlling Regulator
(1) Regulator mode control register (RMC)
This register sets the output voltage of the regulator.
RMC is set with an 8-bit memory manipulation instruction.
Reset input sets this register to 00H.
Figure 23-1. Format of Regulator Mode Control Register (RMC)
Address: F00F4H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
RMC
RMC[7:0] Control of output voltage of regulator
5AH Fixed to low consumption current mode (1.8 V)
00H Switches normal current mode (2.5 V) and low consumption current mode (1.8 V) according to the
condition (refer to Table 23-1)
Other than
above
Setting prohibited
Cautions 1. The RMC register can be rewritten only in the low consumption current mode (refer to
Table 23-1). In other words, rewrite this register during CPU operation with the subsystem
clock (fXT) while the high-speed system clock (fMX) and internal high-speed oscillation
clock (fIH) are both stopped.
2. When using the setting fixed to the low consumption current mode, the RMC register can
be used in the following cases.
<When X1 clock is selected as the CPU clock> fX ≤ 5 MHz and fCLK ≤ 5 MHz
<When the internal high-speed oscillation clock, external input clock, or subsystem clock
are selected for the CPU clock> fCLK ≤ 5 MHz
3. The self-programming function is disabled in the low consumption current mode.
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Table 23-1. Regulator Output Voltage Conditions
Mode Output Voltage Condition
During system reset
In STOP mode (except during OCD mode)
When both the high-speed system clock (fMX) and the internal high-speed
oscillation clock (fIH) are stopped during CPU operation with the subsystem clock
(fXT)
Low consumption
current mode
1.8 V
When both the high-speed system clock (fMX) and the internal high-speed
oscillation clock (fIH) are stopped during the HALT mode when the CPU operation
with the subsystem clock (fXT) has been set
Normal current mode 2.5 V Other than above
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CHAPTER 24 OPTION BYTE
24.1 Functions of Option Bytes
Addresses 000C0H to 000C3H of the flash memory of the 78K0R/KG3 form an option byte area.
Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H).
Upon power application or resetting and starting, an option byte is automatically referenced and a specified
function is set. When using the product, be sure to set the following functions by using the option bytes.
To use the boot swap operation during self programming, 000C0H to 000C3H are replaced by 010C0H to 010C3H.
Therefore, set the same values as 000C0H to 000C3H to 010C0H to 010C3H.
Caution Be sure to set FFH to 000C2H (000C2H/010C2H when the boot swap operation is used).
24.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H)
(1) 000C0H/010C0H
{ Operation of watchdog timer
• Operation is stopped or enabled in the HALT or STOP mode.
{ Setting of interval time of watchdog timer
{ Operation of watchdog timer
• Operation is stopped or enabled.
{ Setting of window open period of watchdog timer
{ Setting of interval interrupt of watchdog timer
• Used or not used
Caution Set the same value as 000C0H to 010C0H when the boot swap operation is used because
000C0H is replaced by 010C0H.
(2) 000C1H/010C1H
{ Setting of LVI upon reset release upon power application
• LVI is ON or OFF by default upon reset release (reset by RESET pin excluding LVI, POC, WDT, or illegal
instructions).
Caution Set the same value as 000C1H to 010C1H when the boot swap operation is used because
000C1H is replaced by 010C1H.
(3) 000C2H/010C2H
{ Be sure to set FFH, as these addresses are reserved areas.
Caution Set FFH to 010C2H when the boot swap operation is used because 000C2H is replaced by
010C2H.
CHAPTER 24 OPTION BYTE
User’s Manual U17894EJ9V0UD 713
24.1.2 On-chip debug option byte (000C3H/ 010C3H)
{ Control of on-chip debug operation
• On-chip debug operation is disabled or enabled.
{ Handling of data of flash memory in case of failure in on-chip debug security ID authentication
• Data of flash memory is erased or not erased in case of failure in on-chip debug security ID
authentication.
Caution Set the same value as 000C3H to 010C3H when the boot swap operation is used because
000C3H is replaced by 010C3H.
24.2 Format of User Option Byte
The format of user option byte is shown below.
Figure 24-1. Format of User Option Byte (000C0H/010C0H) (1/2)
Address: 000C0H/010C0HNote 1
7 6 5 4 3 2 1 0
WDTINIT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 WDSTBYON
WDTINIT Use of interval interrupt of watchdog timer
0 Interval interrupt is not used.
1 Interval interrupt is generated when 75% of the overflow time is reached.
WINDOW1 WINDOW0 Watchdog timer window open periodNote 2
0 0 25%
0 1 50%
1 0 75%
1 1 100%
WDTON Operation control of watchdog timer counter
0 Counter operation disabled (counting stopped after reset)
1 Counter operation enabled (counting started after reset)
WDCS2 WDCS1 WDCS0 Watchdog timer overflow time
0 0 0 210/fIL (3.88 ms)
0 0 1 211/fIL (7.76 ms)
0 1 0 212/fIL (15.52 ms)
0 1 1 213/fIL (31.03 ms)
1 0 0 215/fIL (124.12 ms)
1 0 1 217/fIL (496.48 ms)
1 1 0 218/fIL (992.97 ms)
1 1 1 220/fIL (3971.88 ms)
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Figure 24-1. Format of User Option Byte (000C0H/010C0H) (2/2)
Address: 000C0H/010C0HNote 1
7 6 5 4 3 2 1 0
WDTINIT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 WDSTBYON
WDSTBYON Operation control of watchdog timer counter (HALT/STOP mode)
0 Counter operation stopped in HALT/STOP modeNote 2
1 Counter operation enabled in HALT/STOP mode
Notes 1. Set the same value as 000C0H to 010C0H when the boot swap operation is used because 000C0H is
replaced by 010C0H.
2. The window open period is 100% when WDSTBYON = 0, regardless the value of WINDOW1 and
WINDOW0.
Caution The watchdog timer continues its operation during self-programming of the flash memory and
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
Remarks 1. fIL: Internal low-speed oscillation clock frequency
2. ( ): fIL = 264 kHz (MAX.)
Figure 24-2. Format of Option Byte (000C1H/010C1H)
Address: 000C1H/010C1HNote
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 LVIOFF
LVIOFF Setting of LVI on power application
0 LVI is ON by default (LVI default start function enabled) after reset release (upon power application)
1 LVI is OFF by default (LVI default start function stopped) after reset release (upon power
application)
Note Set the same value as 000C1H to 010C1H when the boot swap operation is used because 000C1H is
replaced by 010C1H.
Cautions 1. Be sure to set bits 7 to 1 to “1”.
2. Even when the LVI default start function is used, if it is set to LVI operation prohibition by the
software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU starts after
reset release. There is a period when low-voltage detection cannot be performed normally,
however, when a reset occurs due to WDT and illegal instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
μ
s max.,
LVION = 1 is set upon reset occurrence, and the CPU starts operating without waiting for
the LVI stabilization time.
CHAPTER 24 OPTION BYTE
User’s Manual U17894EJ9V0UD 715
Figure 24-3. Format of Option Byte (000C2H/010C2H)
Address: 000C2H/010C2HNote
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
Note Be sure to set FFH to 000C2H, as these addresses are reserved areas. Also set FFH to 010C2H when the
boot swap operation is used because 000C2H is replaced by 010C2H.
24.3 Format of On-chip Debug Option Byte
The format of on-chip debug option byte is shown below.
Figure 24-4. Format of On-chip Debug Option Byte (000C3H/010C3H)
Address: 000C3H/010C3HNote
7 6 5 4 3 2 1 0
OCDENSET 0 0 0 0 1 0 OCDERSD
OCDENSET OCDERSD Control of on-chip debug operation
0 0 Disables on-chip debug operation.
0 1 Setting prohibited
1 0 Enables on-chip debugging.
Erases data of flash memory in case of failures in authenticating on-chip debug
security ID.
1 1 Enables on-chip debugging.
Does not erases data of flash memory in case of failures in authenticating on-chip
debug security ID.
Note Set the same value as 000C3H to 010C3H when the boot swap operation is used because 000C3H is
replaced by 010C3H.
Caution Bits 7 and 0 (OCDENSET and OCDERSD) can only be specified a value.
Be sure to set 000010B to bits 6 to 1.
Remark The value on bits 3 to 1 will be written over when the on-chip debug function is in use and thus it will
become unstable after the setting.
However, be sure to set the default values (0, 1, and 0) to bits 3 to 1 at setting.
CHAPTER 24 OPTION BYTE
User’s Manual U17894EJ9V0UD
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24.4 Setting of Option Byte
The user option byte and on-chip debug option byte can be set using the RA78K0R or PM+ linker option, in
addition to describing to the source. When doing so, the contents set by using the linker option take precedence,
even if descriptions exist in the source, as mentioned below.
See the RA78K0R Assembler Package User’s Manual for how to set the linker option.
A software description example of the option byte setting is shown below.
OPT CSEG OPT_BYTE
DB 10H ; Does not use interval interrupt of watchdog timer,
; Enables watchdog timer operation,
; Window open period of watchdog timer is 25%,
; Overflow time of watchdog timer is 210/fIL,
; Stops watchdog timer operation during HALT/STOP mode
DB 0FFH ; Stops LVI default start function
DB 0FFH ; Reserved area
DB 85H ; Enables on-chip debug operation, does not erase flash memory
; data when security ID authorization fails
When the boot swap function is used during self programming, 000C0H to 000C3H is switched to 010C0H to
010C3H. Describe to 010C0H to 010C3H, therefore, the same values as 000C0H to 000C3H as follows.
OPT2 CSEG AT 010C0H
DB 10H ; Does not use interval interrupt of watchdog timer,
; Enables watchdog timer operation,
; Window open period of watchdog timer is 25%,
; Overflow time of watchdog timer is 210/fIL,
; Stops watchdog timer operation during HALT/STOP mode
DB 0FFH ; Stops LVI default start function
DB 0FFH ; Reserved area
DB 85H ; Enables on-chip debug operation, does not erase flash memory
; data when security ID authorization fails
Caution To specify the option byte by using assembly language, use OPT_BYTE as the relocation attribute
name of the CSEG pseudo instruction. To specify the option byte to 010C0H to 010C3H in order
to use the boot swap function, use the relocation attribute AT to specify an absolute address.
User’s Manual U17894EJ9V0UD 717
CHAPTER 25 FLASH MEMORY
The 78K0R/KG3 incorporates the flash memory to which a program can be written, erased, and overwritten while
mounted on the board.
25.1 Writing with Flash Memory Programmer
The following dedicated flash memory programmer can be used to write data to the internal flash memory of the
78K0R/KG3.
• PG-FP4, FL-PR4
• PG-FP5, FL-PR5
• QB-MINI2
Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer.
(1) On-board programming
The contents of the flash memory can be rewritten after the 78K0R/KG3 has been mounted on the target system.
The connectors that connect the dedicated flash memory programmer must be mounted on the target system.
(2) Off-board programming
Data can be written to the flash memory with a dedicated program adapter (FA series) before the 78K0R/KG3 is
mounted on the target system.
Remark The FL-PR4, FL-PR5, and FA series are products of Naito Densei Machida Mfg. Co., Ltd.
CHAPTER 25 FLASH MEMORY
User’s Manual U17894EJ9V0UD
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Table 25-1. Wiring Between 78K0R/KG3 and Dedicated Flash Memory Programmer
Pin Configuration of Dedicated Flash Memory
Programmer
GF Package GC Package
Signal Name I/O Pin Function Pin Name Pin No. Pin Name Pin No.
SI/RxDNotes 1, 2 Input Receive signal TOOL0/P40 89 TOOL0/P40 12
SO/TxDNote 2 Output Transmit signal
SCK Output Transfer clock − − − −
CLK Output Clock output − − − −
/RESET Output Reset signal RESET 90 RESET 13
FLMD0 Output Mode signal FLMD0 93 FLMD0 16
VDD 99 VDD 22
EVDD0 100 EVDD0 23
EVDD1 30 EVDD1 53
VDD I/O
VDD voltage generation/
power monitoring
AVREF0 50 AVREF0 73
AVREF1 47 AVREF1 70
VSS 97 VSS 20
EVSS0 98 EVSS0 21
EVSS1 20 EVSS1 43
GND − Ground
AVSS 51 AVSS 74
Notes 1. This pin is not required to be connected when using PG-FP5 or FL-PR5.
2. Connect SI/RxD or SO/TxD when using QB-MINI2.
CHAPTER 25 FLASH MEMORY
User’s Manual U17894EJ9V0UD 719
Examples of the recommended connection when using the adapter for flash memory writing are shown below.
Figure 25-1. Example of Wiring Adapter for Flash Memory Writing (GF Package)
GND
VDD
VDD2
INTERFACE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VDD (2.7 to 5.5. V)
GND
SI/RxD
Notes 1, 2
SO/TxD
Note 2
FLMD0/RESETCLKSCK
Notes 1. This pin is not required to be connected when using PG-FP5 or FL-PR5.
2. Connect SI/RxD or SO/TxD when using QB-MINI2.
CHAPTER 25 FLASH MEMORY
User’s Manual U17894EJ9V0UD
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Figure 25-2. Example of Wiring Adapter for Flash Memory Writing (GC Package)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
GND
VDD
VDD2
WRITER INTERFACE
V
DD
(2.7 to 5.5 V)
GND
SI/RxD
Notes 1, 2
SO/TxD
Note 2
SCK CLK /RESET FLMD0
Notes 1. This pin is not required to be connected when using PG-FP5 or FL-PR5.
2. Connect SI/RxD or SO/TxD when using QB-MINI2.
CHAPTER 25 FLASH MEMORY
User’s Manual U17894EJ9V0UD 721
25.2 Programming Environment
The environment required for writing a program to the flash memory of the 78K0R/KG3 is illustrated below.
Figure 25-3. Environment for Writing Program to Flash Memory
RS-232C
USB
78K0R/KG3
FLMD0
V
DD
V
SS
RESET
TOOL0 (dedicated single-line UART)
Host machine
Dedicated flash
memory programmer
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
XXXXX XXXXXX
XXXX
XXXX YYYY
STAT VE
PG-FP4, FL-PR4
PG-FP5, FL-PR5 QB-MINI2
A host machine that controls the dedicated flash memory programmer is necessary.
To interface between the dedicated flash memory programmer and the 78K0R/KG3, the TOOL0 pin is used for
manipulation such as writing and erasing via a dedicated single-line UART. To write the flash memory off-board, a
dedicated program adapter (FA series) is necessary.
25.3 Communication Mode
Communication between the dedicated flash memory programmer and the 78K0R/KG3 is established by serial
communication using the TOOL0 pin via a dedicated single-line UART of the 78K0R/KG3.
Transfer rate: 115,200 bps to 1,000,000 bps
Figure 25-4. Communication with Dedicated Flash Memory Programmer
V
DD
/EV
DD0
/EV
DD1
V
SS
/EV
SS0
/EV
SS1
RESET
TOOL0
FLMD0 FLMD0
V
DD
GND
/RESET
SI/RxD
Notes 1, 2
SO/TxD
Note 2
Dedicated flash
memory programmer
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
XXXXX XXXXXX
XXXX
XXXX YYYY
STATVE
78K0R/KG3
PG-FP4, FL-PR4
PG-FP5, FL-PR5 QB-MINI2
Notes 1. This pin is not required to be connected when using PG-FP5 or FL-PR5.
2. Connect SI/RxD or SO/TxD when using QB-MINI2.
The dedicated flash memory programmer generates the following signals for the 78K0R/KG3. See the manual of
PG-FP4, FL-PR4, PG-FP5, FL-PR5, or MINICUBE2 for details.
CHAPTER 25 FLASH MEMORY
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Table 25-2. Pin Connection
Dedicated Flash Memory Programmer 78K0R/KG3 Connection
Signal Name I/O Pin Function Pin Name
FLMD0 Output Mode signal FLMD0
VDD I/O VDD voltage generation/power monitoring VDD, EVDD0, EVDD1, AVREF0, AVREF1
GND − Ground VSS, EVSS0, EVSS1, AVSS
CLK Output Clock output − ×
/RESET Output Reset signal RESET
SI/RxDNotes 1, 2 Input Receive signal TOOL0
SO/TxDNote 2 Output Transmit signal
SCK Output Transfer clock − ×
Notes 1. This pin is not required to be connected when using PG-FP5 or FL-PR5.
2. Connect SI/RxD or SO/TxD when using QB-MINI2.
Remark : Be sure to connect the pin.
×: The pin does not have to be connected.
25.4 Connection of Pins on Board
To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be
provided on the target system. First provide a function that selects the normal operation mode or flash memory
programming mode on the board.
When the flash memory programming mode is set, all the pins not used for programming the flash memory are in
the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately
after reset, the pins must be handled as described below.
25.4.1 FLMD0 pin
(1) In flash memory programming mode
Directly connect this pin to a flash memory programmer when data is written by the flash memory programmer.
This supplies a writing voltage of the VDD level to the FLMD0 pin.
The FLMD0 pin does not have to be pulled down externally because it is internally pulled down by reset. To pull
it down externally, use a resistor of 1 kΩ to 200 kΩ.
(2) In normal operation mode
It is recommended to leave this pin open during normal operation.
The FLMD0 pin must always be kept at the VSS level before reset release but does not have to be pulled down
externally because it is internally pulled down by reset. However, pulling it down must be kept selected (i.e.,
FLMDPUP = “0”, default value) by using bit 7 (FLMDPUP) of the background event control register (BECTL) (see
25.5 (1) Back ground event control register). To pull it down externally, use a resistor of 200 kΩ or smaller.
Self programming and the rewriting of flash memory with the programmer can be prohibited using hardware, by
directly connecting this pin to the VSS pin.
CHAPTER 25 FLASH MEMORY
User’s Manual U17894EJ9V0UD 723
(3) In self programming mode
It is recommended to leave this pin open when using the self programming function. To pull it down externally,
use a resistor of 100 kΩ to 200 kΩ.
In the self programming mode, the setting is switched to pull up in the self programming library.
Figure 25-5. FLMD0 Pin Connection Example
78K0R/KG3
FLMD0
Dedicated flash memory programmer
connection pin
25.4.2 TOOL0 pin
In the flash memory programming mode, connect this pin directly to the dedicated flash memory programmer or
pull it up by connecting it to EVDD0 or EVDD1 via an external resistor.
When on-chip debugging is enabled in the normal operation mode, pull this pin up by connecting it to EVDD0 or
EVDD1 via an external resistor, and be sure to keep inputting the VDD level to the TOOL0 pin before reset is released
(pulling down this pin is prohibited).
Remark The SAU and IIC0 pins are not used for communication between the 78K0R/KG3 and dedicated flash
memory programmer, because single-line UART is used.
25.4.3 RESET pin
Signal conflict will occur if the reset signal of the dedicated flash memory programmer is connected to the RESET
pin that is connected to the reset signal generator on the board. To prevent this conflict, isolate the connection with
the reset signal generator.
The flash memory will not be correctly programmed if the reset signal is input from the user system while the flash
memory programming mode is set . Do not input any signal other than the reset signal of the dedicated flash memory
programmer.
Figure 25-6. Signal Conflict (RESET Pin)
Input pin
Dedicated flash memory programmer
connection pin
Another device
Signal conflict
Output pin
In the flash memory programming mode, a signal output by another device
will conflict with the signal output by the dedicated flash memory
programmer. Therefore, isolate the signal of another device.
78K0R/KG3
CHAPTER 25 FLASH MEMORY
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25.4.4 Port pins
When the flash memory programming mode is set, all the pins not used for flash memory programming enter the
same status as that immediately after reset. If external devices connected to the ports do not recognize the port
status immediately after reset, the port pin must be connected to VDD or VSS via a resistor.
25.4.5 REGC pin
Connect the REGC pin to GND via a capacitor (0.47 to 1
μ
F) in the same manner as during normal operation.
However, when using the STOP mode that has been entered since operation of the internal high-speed oscillation
clock and external main system clock, 0.47
μ
F is recommended. Also, use a capacitor with good characteristics,
since it is used to stabilize internal voltage.
25.4.6 X1 and X2 pins
Connect X1 and X2 in the same status as in the normal operation mode.
Remark In the flash memory programming mode, the internal high-speed oscillation clock (fIH) is used.
25.4.7 Power supply
To use the supply voltage output of the flash memory programmer, connect the VDD pin to VDD of the flash memory
programmer, and the VSS pin to GND of the flash memory programmer.
To use the on-board supply voltage, connect in compliance with the normal operation mode.
However, when using the on-board supply voltage, be sure to connect the VDD and VSS pins to VDD and GND of the
flash memory programmer to use the power monitor function with the flash memory programmer.
Supply the same other power supplies (EVDD0, EVDD1, EVSS0, EVSS1, AVREF0, AVREF1, and AVSS) as those in the
normal operation mode.
25.5 Registers that Control Flash Memory
(1) Background event control register (BECTL)
Even if the FLMD0 pin is not controlled externally, it can be controlled by software with the BECTL register to set
the self-programming mode.
However, depending on the processing of the FLMD0 pin, it may not be possible to set the self-programming
mode by software. When using BECTL, leaving the FLMD0 pin open is recommended. When pulling it down
externally, use a resistor with a resistance of 100 kΩ or more. In addition, in the normal operation mode, use
BECTL with the pull down selection. In the self-programming mode, the setting is switched to pull up in the self-
programming library.
The BECTL register is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets this register to 00H.
Figure 25-7. Format of Background Event Control Register (BECTL)
Address: FFFBEH After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 0
BECTL FLMDPUP 0 0 0 0 0 0 0
FLMDPUP Software control of FLMD0 pin
0 Selects pull-down
1 Selects pull-up
CHAPTER 25 FLASH MEMORY
User’s Manual U17894EJ9V0UD 725
25.6 Programming Method
25.6.1 Controlling flash memory
The following figure illustrates the procedure to manipulate the flash memory.
Figure 25-8. Flash Memory Manipulation Procedure
Start
Manipulate flash memory
End?
Yes
Controlling FLMD0 pin and RESET pin
No
End
Flash memory programming
mode is set
25.6.2 Flash memory programming mode
To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the 78K0R/KG3
in the flash memory programming mode. To set the mode, set the FLMD0 pin and TOOL0 pin to VDD and clear the
reset signal.
Change the mode by using a jumper when writing the flash memory on-board.
Figure 25-9. Flash Memory Programming Mode
V
DD
RESET
5.5 V
0 V
V
DD
0 V
FLMD0 V
DD
0 V
TOOL0 V
DD
0 V
Flash memory programming mode
CHAPTER 25 FLASH MEMORY
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726
Table 25-3. Relationship Between FLMD0 Pin and Operation Mode After Reset Release
FLMD0 Operation Mode
0 Normal operation mode
VDD Flash memory programming mode
25.6.3 Selecting communication mode
Communication mode of the 78K0R/KG3 is as follows.
Table 25-4. Communication Modes
Standard SettingNote 1 Communication
Mode Port Speed Note 2 Frequency Multiply Rate
Pins Used
1-line mode
(single-line
UART)
UART 115,200 bps,
250,000 bps,
500,000 bps,
1 Mbps
− − TOOL0
Notes 1. Selection items for Standard settings on GUI of the flash memory programmer.
2. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART
communication, thoroughly evaluate the slew as well as the baud rate error.
25.6.4 Communication commands
The 78K0R/KG3 communicates with the dedicated flash memory programmer by using commands. The signals
sent from the flash memory programmer to the 78K0R/KG3 are called commands, and the signals sent from the
78K0R/KG3 to the dedicated flash memory programmer are called response.
Figure 25-10. Communication Commands
Command
Response
78K0R/KG3
Dedicated flash
memory
programmer
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
XXXXX XXXXXX
XXXX
XXXX YYYY
STATVE
PG-FP4, FL-PR4
PG-FP5, FL-PR5 QB-MINI2
The flash memory control commands of the 78K0R/KG3 are listed in the table below. All these commands are
issued from the programmer and the 78K0R/KG3 perform processing corresponding to the respective commands.
CHAPTER 25 FLASH MEMORY
User’s Manual U17894EJ9V0UD 727
Table 25-5. Flash Memory Control Commands
Classification Command Name Function
Verify Verify Compares the contents of a specified area of the flash memory with
data transmitted from the programmer.
Chip Erase Erases the entire flash memory. Erase
Block Erase Erases a specified area in the flash memory.
Blank check Block Blank Check Checks if a specified block in the flash memory has been correctly
erased.
Write Programming Writes data to a specified area in the flash memory.
Silicon Signature Gets 78K0R/KG3 information (such as the part number and flash
memory configuration).
Version Get Gets the 78K0R/KG3 firmware version.
Getting information
Checksum Gets the checksum data for a specified area.
Security Security Set Sets security information.
Reset Used to detect synchronization status of communication. Others
Baud Rate Set Sets baud rate when UART communication mode is selected.
The 78K0R/KG3 returns a response for the command issued by the dedicated flash memory programmer. The
response names sent from the 78K0R/KG3 are listed below.
Table 25-6. Response Names
Response Name Function
ACK Acknowledges command/data.
NAK Acknowledges illegal command/data.
CHAPTER 25 FLASH MEMORY
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25.7 Security Settings
The 78K0R/KG3 supports a security function that prohibits rewriting the user program written to the internal flash
memory, so that the program cannot be changed by an unauthorized person.
The operations shown below can be performed using the Security Set command. The security setting is valid
when the programming mode is set next.
• Disabling batch erase (chip erase)
Execution of the block erase and batch erase (chip erase) commands for entire blocks in the flash memory is
prohibited by this setting during on-board/off-board programming. Once execution of the batch erase (chip
erase) command is prohibited, all of the prohibition settings (including prohibition of batch erase (chip erase)) can
no longer be cancelled.
Caution After the security setting for the batch erase is set, erasure cannot be performed for the device.
In addition, even if a write command is executed, data different from that which has already
been written to the flash memory cannot be written, because the erase command is disabled.
• Disabling block erase
Execution of the block erase command for a specific block in the flash memory is prohibited during on-board/off-
board programming. However, blocks can be erased by means of self programming.
• Disabling write
Execution of the write and block erase commands for entire blocks in the flash memory is prohibited during on-
board/off-board programming. However, blocks can be written by means of self programming.
• Disabling rewriting boot cluster 0
Execution of the write command, block erase command, and batch erase (chip erase) command for boot cluster
0 (00000H to 00FFFH) in the flash memory is prohibited by this setting.
The batch erase (chip erase), block erase, write commands, and rewriting boot cluster 0 are enabled by the default
setting when the flash memory is shipped. Security can be set by on-board/off-board programming and self
programming. Each security setting can be used in combination.
All the security settings are cleared by executing the batch erase (chip erase) command.
Table 25-7 shows the relationship between the erase and write commands when the 78K0R/KG3 security function
is enabled.
Remark To prohibit writing and erasing during self-programming, use the flash shield window function (see 25.9.2
for details).
CHAPTER 25 FLASH MEMORY
User’s Manual U17894EJ9V0UD 729
Table 25-7. Relationship Between Enabling Security Function and Command
(1) During on-board/off-board programming
Executed Command Valid Security
Batch Erase (Chip Erase) Block Erase Write
Prohibition of batch erase (chip erase) Cannot be erased in batch Can be performedNote.
Prohibition of block erase Can be performed.
Prohibition of writing
Can be erased in batch.
Blocks cannot be
erased.
Cannot be performed.
Prohibition of rewriting boot cluster 0 Cannot be erased in batch Boot cluster 0 cannot be
erased.
Boot cluster 0 cannot be
written.
Note Confirm that no data has been written to the write area. Because data cannot be erased after batch erase
(chip erase) is prohibited, do not write data if the data has not been erased.
(2) During self programming
Executed Command Valid Security
Block Erase Write
Prohibition of batch erase (chip erase)
Prohibition of block erase
Prohibition of writing
Blocks can be erased. Can be performed.
Prohibition of rewriting boot cluster 0 Boot cluster 0 cannot be erased. Boot cluster 0 cannot be written.
Remark To prohibit writing and erasing during self-programming, use the flash shield window function (see 25.9.2
for details).
Table 25-8. Setting Security in Each Programming Mode
(1) On-board/off-board programming
Security Security Setting How to Disable Security Setting
Prohibition of batch erase (chip erase) Cannot be disabled after set.
Prohibition of block erase
Prohibition of writing
Execute batch erase (chip erase)
command
Prohibition of rewriting boot cluster 0
Set via GUI of dedicated flash memory
programmer, etc.
Cannot be disabled after set.
(2) Self programming
Security Security Setting How to Disable Security Setting
Prohibition of batch erase (chip erase) Cannot be disabled after set.
Prohibition of block erase
Prohibition of writing
Prohibition of rewriting boot cluster 0
Set by using information library.
Execute batch erase (chip erase)
command during on-board/off-board
programming (cannot be disabled during
self programming)
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25.8 Processing Time of Each Command When Using PG-FP4 or PG-FP5 (Reference Values)
The processing time of each command (reference values) when using PG-FP4 or PG-FP5 as the dedicated flash
memory programmer is shown below.
Table 25-9. Processing Time of Each Command When Using PG-FP4 (Reference Values)
Port: UART
Speed: 115200 bps Speed: 1 Mbps
PG-FP4
Command
μ
PD78F1162,
μ
PD78F1162A
μ
PD78F1163,
μ
PD78F1163A
μ
PD78F1164,
μ
PD78F1164A
μ
PD78F1165,
μ
PD78F1165A
μ
PD78F1166,
μ
PD78F1166A
μ
PD78F1167,
μ
PD78F1167A
μ
PD78F1168,
μ
PD78F1168A
μ
PD78F1162,
μ
PD78F1162A
μ
PD78F1163,
μ
PD78F1163A
μ
PD78F1164,
μ
PD78F1164A
μ
PD78F1165,
μ
PD78F1165A
μ
PD78F1166,
μ
PD78F1166A
μ
PD78F1167,
μ
PD78F1167A
μ
PD78F1168,
μ
PD78F1168A
Signature 1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
Blankcheck
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1.5 s
(TYP.)
1.5 s
(TYP.)
2 s
(TYP.)
2.5 s
(TYP.)
0.5 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1.5 s
(TYP.)
2 s
(TYP.)
2.5 s
(TYP.)
Erase 1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1.5 s
(TYP.)
1.5 s
(TYP.)
2 s
(TYP.)
2.5 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1.5 s
(TYP.)
1.5 s
(TYP.)
2 s
(TYP.)
2.5 s
(TYP.)
Program 9.5 s
(TYP.)
13.5 s
(TYP.)
19 s
(TYP.)
26.5 s
(TYP.)
35 s
(TYP.)
51.5 s
(TYP.)
68.5 s
(TYP.)
3.5 s
(TYP.)
5 s
(TYP.)
6.5 s
(TYP.)
9 s
(TYP.)
12 s
(TYP.)
17.5 s
(TYP.)
23 s
(TYP.)
Verify 8.5 s
(TYP.)
12 s
(TYP.)
16 s
(TYP.)
23.5 s
(TYP.)
31 s
(TYP.)
46 s
(TYP.)
61 s
(TYP.)
2.5 s
(TYP.)
3.5 s
(TYP.)
4.5 s
(TYP.)
6 s
(TYP.)
8 s
(TYP.)
11.5 s
(TYP.)
15.5 s
(TYP.)
E.P.V 10.5 s
(TYP.)
14.5 s
(TYP.)
20 s
(TYP.)
28 s
(TYP.)
36.5 s
(TYP.)
53.5 s
(TYP.)
71 s
(TYP.)
4.5 s
(TYP.)
6 s
(TYP.)
7.5 s
(TYP.)
10.5 s
(TYP.)
13.5 s
(TYP.)
19.5 s
(TYP.)
25.5 s
(TYP.)
Checksum 1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1.5 s
(TYP.)
1.5 s
(TYP.)
2 s
(TYP.)
2.5 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1.5 s
(TYP.)
1.5 s
(TYP.)
2 s
(TYP.)
2.5 s
(TYP.)
Security 1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
Table 25-10. Processing Time of Each Command When Using PG-FP5 (Reference Values)
Port: UART
Speed: 115200 bps Speed: 1 Mbps
PG-FP5
Command
μ
PD78F1162,
μ
PD78F1162A
μ
PD78F1163,
μ
PD78F1163A
μ
PD78F1164,
μ
PD78F1164A
μ
PD78F1165,
μ
PD78F1165A
μ
PD78F1166,
μ
PD78F1166A
μ
PD78F1167,
μ
PD78F1167A
μ
PD78F1168,
μ
PD78F1168A
μ
PD78F1162,
μ
PD78F1162A
μ
PD78F1163,
μ
PD78F1163A
μ
PD78F1164,
μ
PD78F1164A
μ
PD78F1165,
μ
PD78F1165A
μ
PD78F1166,
μ
PD78F1166A
μ
PD78F1167,
μ
PD78F1167A
μ
PD78F1168,
μ
PD78F1168A
Signature
read
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
Blank
check
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
2 s
(TYP.)
2.5 s
(TYP.)
0.5 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
2 s
(TYP.)
2.5 s
(TYP.)
Erase 1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1.5 s
(TYP.)
2 s
(TYP.)
2.5 s
(TYP.)
0.5 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1.5 s
(TYP.)
2 s
(TYP.)
2.5 s
(TYP.)
Program 9 s
(TYP.)
13.5 s
(TYP.)
17.5 s
(TYP.)
26 s
(TYP.)
34 s
(TYP.)
51 s
(TYP.)
67.5 s
(TYP.)
3 s
(TYP.)
4.5 s
(TYP.)
6 s
(TYP.)
8.5 s
(TYP.)
11 s
(TYP.)
16.5 s
(TYP.)
22 s
(TYP.)
Verify 8 s
(TYP.)
12 s
(TYP.)
15.5 s
(TYP.)
23 s
(TYP.)
30.5 s
(TYP.)
45.5 s
(TYP.)
60 s
(TYP.)
2.5 s
(TYP.)
3.5 s
(TYP.)
4 s
(TYP.)
5.5 s
(TYP.)
7.5 s
(TYP.)
11 s
(TYP.)
14 s
(TYP.)
Auto-
procedure
9.5 s
(TYP.)
13.5 s
(TYP.)
18 s
(TYP.)
26.5 s
(TYP.)
35 s
(TYP.)
52 s
(TYP.)
69 s
(TYP.)
3.5 s
(TYP.)
5 s
(TYP.)
6 s
(TYP.)
9 s
(TYP.)
12 s
(TYP.)
18 s
(TYP.)
23.5 s
(TYP.)
Checksum 1 s
(TYP.)
1 s
(TYP.)
1 s
(TYP.)
1.5 s
(TYP.)
1.5 s
(TYP.)
2 s
(TYP.)
2.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
1 s
(TYP.)
1.5 s
(TYP.)
1.5 s
(TYP.)
2 s
(TYP.)
2.5 s
(TYP.)
Security
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
0.5 s
(TYP.)
CHAPTER 25 FLASH MEMORY
User’s Manual U17894EJ9V0UD 731
25.9 Flash Memory Programming by Self-Programming
The 78K0R/KG3 supports a self-programming function that can be used to rewrite the flash memory via a user
program. Because this function allows a user application to rewrite the flash memory by using the 78K0R/KG3 self-
programming library, it can be used to upgrade the program in the field.
If an interrupt occurs during self-programming, self-programming can be temporarily stopped and interrupt
servicing can be executed. If an unmasked interrupt request is generated in the EI state, the request branches
directly from the self-programming library to the interrupt routine. After the self-programming mode is later restored,
self-programming can be resumed. However, the interrupt response time is different from that of the normal operation
mode.
Remark For details of the self-programming function and the 78K0R/KG3 self-programming library, refer to
78K0R Microcontroller Self Programming Library Type01 User’s Manual (To be prepared).
Cautions 1. The self-programming function cannot be used when the CPU operates with the subsystem
clock.
2. In the self-programming mode, call the self-programming start library (FlashStart).
3. To prohibit an interrupt during self-programming, in the same way as in the normal operation
mode, execute the self-programming library in the state where the IE flag is cleared (0) by the
DI instruction. To enable an interrupt, clear (0) the interrupt mask flag to accept in the state
where the IE flag is set (1) by the EI instruction, and then execute the self-programming
library.
4. The self-programming function is disabled in the low consumption current mode. For details
of the low consumption current mode, see CHAPTER 23 REGULATOR.
5. Disable DMA operation (DENn = 0) during the execution of self programming library
functions.
CHAPTER 25 FLASH MEMORY
User’s Manual U17894EJ9V0UD
732
The following figure illustrates a flow of rewriting the flash memory by using a self programming library.
Figure 25-11. Flow of Self Programming (Rewriting Flash Memory)
FlashStart
FlashEnv
CheckFLMD
FlashBlockBlankCheck
Yes
No
FlashBlockErase
FlashWordWrite
FlashBlockVerify
FlashEnd
Yes
No
No
FlashBlockErase
FlashWordWrite
FlashBlockVerify
Yes
Start of self programming
Normal completion
Setting operating environment
Normal completion?
End of self programming
Normal completion?
Normal completion?
Error
Remark For details of the self programming library, refer to 78K0R Microcontroller Self Programming Library
Type01 User’s Manual (To be prepared).
CHAPTER 25 FLASH MEMORY
User’s Manual U17894EJ9V0UD 733
25.9.1 Boot swap function
If rewriting the boot area failed by temporary power failure or other reasons, restarting a program by resetting or
overwriting is disabled due to data destruction in the boot area.
The boot swap function is used to avoid this problem.
Before erasing boot cluster 0Note, which is a boot program area, by self-programming, write a new boot program to
boot cluster 1 in advance. When the program has been correctly written to boot cluster 1, swap this boot cluster 1 and
boot cluster 0 by using the set information function of the firmware of the 78K0R/KG3, so that boot cluster 1 is used as
a boot area. After that, erase or write the original boot program area, boot cluster 0.
As a result, even if a power failure occurs while the boot programming area is being rewritten, the program is
executed correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next.
Note A boot cluster is a 4 KB area and boot clusters 0 and 1 are swapped by the boot swap function.
Figure 25-12. Boot Swap Function
Boot program
(boot cluster 0)
New boot program
(boot cluster 1)
User program Self-programming
to boot cluster 1
Self-programming
to boot cluster 0
Execution of boot
swap by firmware
User program
Boot program
(boot cluster 0)
User program
New user program
(boot cluster 0)
New boot program
(boot cluster 1)
User program
New boot program
(boot cluster 1)
Boot program
(boot cluster 0)
User program
XXXXXH
02000H
00000H
01000H
Boot Boot Boot
Boot
In an example of above figure, it is as follows.
Boot cluster 0: Boot program area before boot swap
Boot cluster 1: Boot program area after boot swap
CHAPTER 25 FLASH MEMORY
User’s Manual U17894EJ9V0UD
734
Figure 25-13. Example of Executing Boot Swapping
Boot
cluster 1
Booted by boot cluster 0
Booted by boot cluster 1
Block number
Erasing block 2
Boot
cluster 0
Program
Program
01000H
00000H
01000H
00000H
Erasing block 3
Writing blocks 2 and 3 Boot swap
3
2
1
0
Boot program
Boot program
Program
Boot program
Boot program
Boot program
Boot program
Boot program
Boot program
New boot program
New boot program
Boot program
Boot program
New boot program
New boot program
Erasing block 2 Erasing block 3
Boot program
New boot program
New boot program New boot program
New boot program
Writing blocks 2 and 3
New program
New program
New boot program
New boot program
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
CHAPTER 25 FLASH MEMORY
User’s Manual U17894EJ9V0UD 735
25.9.2 Flash shield window function
The flash shield window function is provided as one of the security functions for self programming. It disables
writing to and erasing areas outside the range specified as a window only during self programming.
The window range can be set by specifying the start and end blocks. The window range can be set or changed
during both on-board/off-board programming and self programming.
Writing to and erasing areas outside the window range are disabled during self programming. During on-board/off-
board programming, however, areas outside the range specified as a window can be written and erased.
Figure 25-14. Flash Shield Window Setting Example
(Target Devices:
μ
PD78F1162, 78F1162A, Start Block: 04H, End Block: 06H)
Block
00H
Block
01H
Block
02H
Block
03H
Block
05H
Block
06H
(end block)
Block
04H
(start block)
Block
1FH
Block
1EH
√: On-board/off-board programming
×: Self programming
√: On-board/off-board programming
√: Self programming
√: On-board/off-board programming
×: Self programming
Flash memory
area
Flash shield
range
Methods by which writing can be performed
Window range
Flash shield
range
0FFFFH
03800H
037FFH
02000H
01FFFH
00000H
Caution If the rewrite-prohibited area of the boot cluster 0 overlaps with the flash shield window range,
prohibition to rewrite the boot cluster 0 takes priority.
Table 25-11. Relationship Between Flash Shield Window Function Setting/Change Methods and Commands
Execution Commands Programming Conditions Window Range
Setting/Change Methods Block Erase Write
Self-programming Specify the starting and
ending blocks by the set
information library.
Block erasing is enabled
only within the window
range.
Writing is enabled only
within the range of
window range.
On-board/off-board
programming
Specify the starting and
ending blocks on GUI of
dedicated flash memory
programmer, etc.
Block erasing is enabled
also outside the window
range.
Writing is enabled also
outside the window
range.
Remark See 25.7 Security Settings to prohibit writing/erasing during on-board/off-board programming.
User’s Manual U17894EJ9V0UD
736
CHAPTER 26 ON-CHIP DEBUG FUNCTION
26.1 Connecting QB-MINI2 to 78K0R/KG3
The 78K0R/KG3 uses the VDD, FLMD0, RESET, TOOL0, TOOL1Note 1, and VSS pins to communicate with the host
machine via an on-chip debug emulator (QB-MINI2).
Caution The 78K0R/KG3 has an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when
this function is used, and product reliability therefore cannot be guaranteed. NEC Electronics is
not liable for problems occurring when the on-chip debug function is used.
Figure 26-1. Connection Example of QB-MINI2 and 78K0R/KG3
V
DD
FLMD0
TOOL0
RESET_IN
CLK_IN
RXD
FLMD0
RESET
V
DD
RESET_OUT
QB-MINI2 target connector
GND
TOOL1
V
SS
EV
DD0
, EV
DD1
TXD
78K0R/KG3
Target reset
Note 1
Note 2
Note 2
Notes 1. Connection is not required for communication in 1-line mode but required for communication in 2-line
mode. At this time, perform necessary connections according to Table 2-2 Connection of Unused Pins
since TOOL1 is an unused pin when QB-MINI2 is unconnected.
2. Connecting the dotted line is not necessary since RXD and TXD are shorted within QB-MIN2. When
using the other flash memory programmer, RXD and TXD may not be shorted within the programmer. In
this case, they must be shorted on the target system.
Caution When communicating in 2-line mode, a clock with a frequency of half that of the CPU clock
frequency is output from the TOOL1 pin. A resistor or ferrite bead can be used as a
countermeasure against fluctuation of the power supply caused by that clock.
Remark The FLMD0 pin is recommended to be open for self-programming in on-chip debugging. To pull down
externally, use a resistor of 100 kΩ or more.
1-line mode (single line UART) using the TOOL0 pin or 2-line mode using the TOOL0 and TOOL1 pins is used for
serial communication. For flash memory programming, 1-line mode is used. 1-line mode or 2-line mode is used for
on-chip debugging. Table 26-1 lists the differences between 1-line mode and 2-line mode.
CHAPTER 26 ON-CHIP DEBUG FUNCTION
User’s Manual U17894EJ9V0UD 737
Table 26-1. Differences Between 1-Line Mode and 2-Line Mode
Communication
Mode
Flash Memory
Programming
Function
Debugging Function
1-line mode Available • Pseudo real-time RAM monitor (RRM) function not supported
2-line mode None • Pseudo real-time RAM monitor (RRM) function supported
Remark 2-line mode is not used for flash programming, however, even if TOOL1 pin is connected with CLK_IN of
QB-MINI2, writing is performed normally with no problem.
26.2 On-Chip Debug Security ID
The 78K0R/KG3 has an on-chip debug operation control bit in the flash memory at 000C3H (see CHAPTER 24
OPTION BYTE) and an on-chip debug security ID setting area at 000C4H to 000CDH, to prevent third parties from
reading memory content.
When the boot swap function is used, also set a value that is the same as that of 010C3H and 010C4H to 010CDH
in advance, because 000C3H, 000C4H to 000CDH and 010C3H, and 010C4H to 010CDH are switched.
For details on the on-chip debug security ID, refer to the QB-MINI2 On-Chip Debug Emulator with Programming
Function User’s Manual (U18371).
Table 26-2. On-Chip Debug Security ID
Address On-Chip Debug Security ID
000C4H to 000CDH
010C4H to 010CDH
Any ID code of 10 bytes
26.3 Securing of User Resources
To perform communication between the 78K0R/KG3 and QB-MINI2, as well as each debug function, the securing
of memory space must be done beforehand.
If NEC Electronics assembler RA78K0R or compiler CC78K0R is used, the items can be set by using linker options.
(1) Securing of memory space
The shaded portions in Figure 26-2 are the areas reserved for placing the debug monitor program, so user
programs or data cannot be allocated in these spaces. When using the on-chip debug function, these spaces
must be secured so as not to be used by the user program. Moreover, this area must not be rewritten by the
user program.
CHAPTER 26 ON-CHIP DEBUG FUNCTION
User’s Manual U17894EJ9V0UD
738
Figure 26-2. Memory Spaces Where Debug Monitor Programs Are Allocated
(1 KB)
: Area used for on-chip debugging
Note 1
Note 2
Internal ROM
Use prohibited
Internal RAM
Internal ROM
area
Boot cluster 1
Debug monitor area
(10 bytes)
Debug monitor area
(2 bytes)
Debug monitor area
(2 bytes)
Security ID area
(10 bytes)
Debug monitor area
(10 bytes)
Security ID area
(10 bytes)
On-chip debug option byte area
(1 byte)
On-chip debug option byte area
(1 byte)
Note 2
Stack area for debugging
(6 bytes)
Note 3
02000H
010D8H
010CEH
010C4H
010C3H
01002H
01000H
000D8H
000CEH
000C4H
000C3H
00002H
00000H
Internal RAM
area
Boot cluster 0
Notes 1. Address differs depending on products as follows.
Products Internal ROM Address
μ
PD78F1162, 78F1162A 64 KB 0FC00H to 0FFFFH
μ
PD78F1163, 78F1163A 96 KB 17C00H to 17FFFH
μ
PD78F1164, 78F1164A 128 KB 1FC00H to 1FFFFH
μ
PD78F1165, 78F1165A 192 KB 2FC00H to 2FFFFH
μ
PD78F1166, 78F1166A 256 KB 3FC00H to 3FFFFH
μ
PD78F1167, 78F1167A 384 KB 5FC00H to 5FFFFH
μ
PD78F1168, 78F1168A 512 KB 7FC00H to 7FFFFH
2. In debugging, reset vector is rewritten to address allocated to a monitor program.
3. Since this area is allocated immediately before the stack area, the address of this area varies depending
on the stack increase and decrease. That is, 6 extra bytes are consumed for the stack area used.
For details of the way to secure of the memory space, refer to the QB-MINI2 On-Chip Debug Emulator with
Programming Function User’s Manual (U18371E).
User’s Manual U17894EJ9V0UD 739
CHAPTER 27 BCD CORRECTION CIRCUIT
27.1 BCD Correction Circuit Function
The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD
code with this circuit.
The decimal correction operation result is obtained by performing addition/subtraction having the A register as the
operand and then adding/ subtracting the BCDADJ register.
27.2 Registers Used by BCD Correction Circuit
The BCD correction circuit uses the following registers.
• BCD correction result register (BCDADJ)
(1) BCD correction result register (BCDADJ)
The BCDADJ register stores correction values for obtaining the add/subtract result as BCD code through
add/subtract instructions using the A register as the operand.
The value read from the BCDADJ register varies depending on the value of the A register when it is read and
those of the CY and AC flags.
BCDADJ is read by an 8-bit memory manipulation instruction.
Reset input sets this register to undefined.
Figure 27-1. Format of BCD Correction Result Register (BCDADJ)
Address: F00FEH After reset: undefined R
Symbol 7 6 5 4 3 2 1 0
BCDADJ
CHAPTER 27 BCD CORRECTION CIRCUIT
User’s Manual U17894EJ9V0UD
740
27.3 BCD Correction Circuit Operation
The basic operation of the BCD correction circuit is as follows.
(1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a
BCD code value
<1> The BCD code value to which addition is performed is stored in the A register.
<2> By adding the value of the A register and the second operand (value of one more BCD code to be added)
as are in binary, the binary operation result is stored in the A register and the correction value is stored in
the BCDADJ register.
<3> Decimal correction is performed by adding in binary the value of the A register (addition result in binary)
and the BCDADJ register (correction value), and the correction result is stored in the A register and CY
flag.
Caution The value read from the BCDADJ register varies depending on the value of the A
register when it is read and those of the CY and AC flags. Therefore, execute the
instruction <3> after the instruction <2> instead of executing any other instructions. To
perform BCD correction in the interrupt enabled state, saving and restoring the A
register is required within the interrupt function. PSW (CY flag and AC flag) is restored
by the RETI instruction.
An example is shown below.
Examples 1: 99 + 89 = 188
Instruction A Register CY Flag AC Flag BCDADJ
Register
MOV A, #99H ; <1> 99H − − −
ADD A, #89H ; <2> 22H 1 1 66H
ADD A, !BCDADJ ; <3> 88H 1 0 −
Examples 2: 85 + 15 = 100
Instruction A Register CY Flag AC Flag BCDADJ
Register
MOV A, #85H ; <1> 85H − − −
ADD A, #15H ; <2> 9AH 0 0 66H
ADD A, !BCDADJ ; <3> 00H 1 1 −
Examples 3: 80 + 80 = 160
Instruction A Register CY Flag AC Flag BCDADJ
Register
MOV A, #80H ; <1> 80H − − −
ADD A, #80H ; <2> 00H 1 0 60H
ADD A, !BCDADJ ; <3> 60H 1 0 −
<R>
CHAPTER 27 BCD CORRECTION CIRCUIT
User’s Manual U17894EJ9V0UD 741
(2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by
using a BCD code value
<1> The BCD code value from which subtraction is performed is stored in the A register.
<2> By subtracting the value of the second operand (value of BCD code to be subtracted) from the A register
as is in binary, the calculation result in binary is stored in the A register, and the correction value is stored
in the BCDADJ register.
<3> Decimal correction is performed by subtracting the value of the BCDADJ register (correction value) from
the A register (subtraction result in binary) in binary, and the correction result is stored in the A register
and CY flag.
Caution The value read from the BCDADJ register varies depending on the value of the A
register when it is read and those of the CY and AC flags. Therefore, execute the
instruction <3> after the instruction <2> instead of executing any other instructions. To
perform BCD correction in the interrupt enabled state, saving and restoring the A
register is required within the interrupt function. PSW (CY flag and AC flag) is restored
by the RETI instruction.
An example is shown below.
Example: 91 − 52 = 39
Instruction A Register CY Flag AC Flag BCDADJ
Register
MOV A, #91H ; <1> 91H − − −
SUB A, #52H ; <2> 3FH 0 1 06H
SUB A, !BCDADJ ; <3> 39H 0 0 −
User’s Manual U17894EJ9V0UD
742
CHAPTER 28 INSTRUCTION SET
This chapter lists the instructions in the 78K0R microcontroller instruction set. For details of each operation and
instruction code, refer to the separate document 78K0R Microcontrollers Instructions User’s Manual (U17792E).
Remark The shaded parts of the tables in Table 28-5 Operation List indicate the operation or instruction format
that is newly added for the 78K0R microcontrollers.
CHAPTER 28 INSTRUCTION SET
User’s Manual U17894EJ9V0UD 743
28.1 Conventions Used in Operation List
28.1.1 Operand identifiers and specification methods
Operands are described in the “Operand” column of each instruction in accordance with the description method of
the instruction operand identifier (refer to the assembler specifications for details). When there are two or more
description methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, !!, $, $!, [ ], and ES: are
keywords and are described as they are. Each symbol has the following meaning.
• #: Immediate data specification
• !: 16-bit absolute address specification
• !!: 20-bit absolute address specification
• $: 8-bit relative address specification
• $!: 16-bit relative address specification
• [ ]: Indirect address specification
• ES:: Extension address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, !!, $, $!, [ ], and ES: symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 28-1. Operand Identifiers and Specification Methods
Identifier Description Method
r
rp
sfr
sfrp
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special-function register symbol (SFR symbol) FFF00H to FFFFFH
Special-function register symbols (16-bit manipulatable SFR symbol. Even addresses onlyNote) FFF00H to
FFFFFH
saddr
saddrp
FFE20H to FFF1FH Immediate data or labels
FFE20H to FFF1FH Immediate data or labels (even addresses onlyNote)
addr20
addr16
addr5
00000H to FFFFFH Immediate data or labels
0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructionsNote)
0080H to 00BFH Immediate data or labels (even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
RBn RB0 to RB3
Note Bit 0 = 0 when an odd address is specified.
Remark The special function registers can be described to operand sfr as symbols. See Table 3-5 SFR List for the
symbols of the special function registers.
The extended special function registers can be described to operand !addr16 as symbols. See Table 3-6
Extended SFR (2nd SFR) List for the symbols of the extended special function registers.
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28.1.2 Description of operation column
The operation when the instruction is executed is shown in the “Operation” column using the following symbols.
Table 28-2. Symbols in “Operation” Column
Symbol Function
A A register; 8-bit accumulator
X X register
B B register
C C register
D D register
E E register
H H register
L L register
ES ES register
CS CS register
AX AX register pair; 16-bit accumulator
BC BC register pair
DE DE register pair
HL HL register pair
PC Program counter
SP Stack pointer
PSW Program status word
CY Carry flag
AC Auxiliary carry flag
Z Zero flag
RBS Register bank select flag
IE Interrupt request enable flag
() Memory contents indicated by address or register contents in parentheses
XH, XL
XS, XH, XL
16-bit registers: XH = higher 8 bits, XL = lower 8 bits
20-bit registers: XS = (bits 19 to 16), XH = (bits 15 to 8), XL = (bits 7 to 0)
∧ Logical product (AND)
∨ Logical sum (OR)
∨ Exclusive logical sum (exclusive OR)
−
Inverted data
addr16 16-bit immediate data
addr20 20-bit immediate data
jdisp8 Signed 8-bit data (displacement value)
jdisp16 Signed 16-bit data (displacement value)
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28.1.3 Description of flag operation column
The change of the flag value when the instruction is executed is shown in the “Flag” column using the following
symbols.
Table 28-3. Symbols in “Flag” Column
Symbol Change of Flag Value
(Blank)
0
1
×
R
Unchanged
Cleared to 0
Set to 1
Set/cleared according to the result
Previously saved value is restored
28.1.4 PREFIX instruction
Instructions with “ES:” have a PREFIX instruction code as a prefix to extend the accessible data area to the 1 MB
space (00000H to FFFFFH), by adding the ES register value to the 64 KB space from F0000H to FFFFFH. When a
PREFIX instruction code is attached as a prefix to the target instruction, only one instruction immediately after the
PREFIX instruction code is executed as the addresses with the ES register value added.
A interrupt and DMA transfer are not acknowledged between a PREFIX instruction code and the instruction
immediately after.
Table 28-4. Use Example of PREFIX Instruction Code
Opcode Instruction
1 2 3 4 5
MOV !addr16, #byte CFH !addr16 #byte −
MOV ES:!addr16, #byte 11H CFH !addr16 #byte
MOV A, [HL] 8BH − − − −
MOV A, ES:[HL] 11H 8BH − − −
Caution Set the ES register value with MOV ES, A, etc., before executing the PREFIX instruction.
<R>
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28.2 Operation List
Table 28-5. Operation List (1/17)
Clocks Flag Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
r, #byte 2 1 − r ← byte
saddr, #byte 3 1 − (saddr) ← byte
sfr, #byte 3 1 − sfr ← byte
!addr16, #byte 4 1 − (addr16) ← byte
A, r Note 3 1 1 − A ← r
r, A Note 3 1 1 − r ← A
A, saddr 2 1 − A ← (saddr)
saddr, A 2 1 − (saddr) ← A
A, sfr 2 1 − A ← sfr
sfr, A 2 1 − sfr ← A
A, !addr16 3 1 4 A ← (addr16)
!addr16, A 3 1 − (addr16) ← A
PSW, #byte 3 3 − PSW ← byte × × ×
A, PSW 2 1 − A ← PSW
PSW, A 2 3 − PSW ← A × × ×
ES, #byte 2 1 − ES ← byte
ES, saddr 3 1 − ES ← (saddr)
A, ES 2 1 − A ← ES
ES, A 2 1 − ES ← A
CS, #byte 3 1 − CS ← byte
A, CS 2 1 − A ← CS
CS, A 2 1 − CS ← A
A, [DE] 1 1 4 A ← (DE)
[DE], A 1 1 − (DE) ← A
[DE + byte], #byte 3 1 − (DE + byte) ← byte
A, [DE + byte] 2 1 4 A ← (DE + byte)
[DE + byte], A 2 1 − (DE + byte) ← A
A, [HL] 1 1 4 A ← (HL)
[HL], A 1 1 − (HL) ← A
8-bit data
transfer
MOV
[HL + byte], #byte 3 1 − (HL + byte) ← byte
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
3. Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
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Table 28-5. Operation List (2/17)
Clocks Flag Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
A, [HL + byte] 2 1 4 A ← (HL + byte)
[HL + byte], A 2 1 − (HL + byte) ← A
A, [HL + B] 2 1 4 A ← (HL + B)
[HL + B], A 2 1 − (HL + B) ← A
A, [HL + C] 2 1 4 A ← (HL + C)
[HL + C], A 2 1 − (HL + C) ← A
word[B], #byte 4 1 − (B + word) ← byte
A, word[B] 3 1 4 A ← (B + word)
word[B], A 3 1 − (B + word) ← A
word[C], #byte 4 1 − (C + word) ← byte
A, word[C] 3 1 4 A ← (C + word)
word[C], A 3 1 − (C + word) ← A
word[BC], #byte 4 1 − (BC + word) ← byte
A, word[BC] 3 1 4 A ← (BC + word)
word[BC], A 3 1 − (BC + word) ← A
[SP + byte], #byte 3 1 − (SP + byte) ← byte
A, [SP + byte] 2 1 − A ← (SP + byte)
[SP + byte], A 2 1 − (SP + byte) ← A
B, saddr 2 1 − B ← (saddr)
B, !addr16 3 1 4 B ← (addr16)
C, saddr 2 1 − C ← (saddr)
C, !addr16 3 1 4 C ← (addr16)
X, saddr 2 1 − X ← (saddr)
X, !addr16 3 1 4 X ← (addr16)
ES:!addr16, #byte 5 2 − (ES, addr16) ← byte
A, ES:!addr16 4 2 5 A ← (ES, addr16)
ES:!addr16, A 4 2 − (ES, addr16) ← A
A, ES:[DE] 2 2 5 A ← (ES, DE)
ES:[DE], A 2 2 − (ES, DE) ← A
ES:[DE + byte],#byte 4 2 − ((ES, DE) + byte) ← byte
A, ES:[DE + byte] 3 2 5 A ← ((ES, DE) + byte)
8-bit data
transfer
MOV
ES:[DE + byte], A 3 2 − ((ES, DE) + byte) ← A
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
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Table 28-5. Operation List (3/17)
Clocks Flag Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
A, ES:[HL] 2 2 5 A ← (ES, HL)
ES:[HL], A 2 2 − (ES, HL) ← A
ES:[HL + byte],#byte 4 2 − ((ES, HL) + byte) ← byte
A, ES:[HL + byte] 3 2 5 A ← ((ES, HL) + byte)
ES:[HL + byte], A 3 2 − ((ES, HL) + byte) ← A
A, ES:[HL + B] 3 2 5 A ← ((ES, HL) + B)
ES:[HL + B], A 3 2 − ((ES, HL) + B) ← A
A, ES:[HL + C] 3 2 5 A ← ((ES, HL) + C)
ES:[HL + C], A 3 2 − ((ES, HL) + C) ← A
ES:word[B], #byte 5 2 − ((ES, B) + word) ← byte
A, ES:word[B] 4 2 5 A ← ((ES, B) + word)
ES:word[B], A 4 2 − ((ES, B) + word) ← A
ES:word[C], #byte 5 2 − ((ES, C) + word) ← byte
A, ES:word[C] 4 2 5 A ← ((ES, C) + word)
ES:word[C], A 4 2 − ((ES, C) + word) ← A
ES:word[BC], #byte 5 2 − ((ES, BC) + word) ← byte
A, ES:word[BC] 4 2 5 A ← ((ES, BC) + word)
ES:word[BC], A 4 2 − ((ES, BC) + word) ← A
B, ES:!addr16 4 2 5 B ← (ES, addr16)
C, ES:!addr16 4 2 5 C ← (ES, addr16)
MOV
X, ES:!addr16 4 2 5 X ← (ES, addr16)
A, r Note 3 1 (r = X)
2 (other
than r = X)
1 − A ←→ r
A, saddr 3 2 − A ←→ (saddr)
A, sfr 3 2 − A ←→ sfr
A, !addr16 4 2 − A ←→ (addr16)
A, [DE] 2 2 − A ←→ (DE)
A, [DE + byte] 3 2 − A ←→ (DE + byte)
A, [HL] 2 2 − A ←→ (HL)
A, [HL + byte] 3 2 − A ←→ (HL + byte)
A, [HL + B] 2 2 − A ←→ (HL + B)
8-bit data
transfer
XCH
A, [HL + C] 2 2 − A ←→ (HL + C)
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
3. Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
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Table 28-5. Operation List (4/17)
Clocks Flag Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
A, ES:!addr16 5 3 − A ←→ (ES, addr16)
A, ES:[DE] 3 3 − A ←→ (ES, DE)
A, ES:[DE + byte] 4 3 − A ←→ ((ES, DE) + byte)
A, ES:[HL] 3 3 − A ←→ (ES, HL)
A, ES:[HL + byte] 4 3 − A ←→ ((ES, HL) + byte)
A, ES:[HL + B] 3 3 − A ←→ ((ES, HL) + B)
XCH
A, ES:[HL + C] 3 3 − A ←→ ((ES, HL) + C)
A 1 1 − A ← 01H
X 1 1 − X ← 01H
B 1 1 − B ← 01H
C 1 1 − C ← 01H
saddr 2 1 − (saddr) ← 01H
!addr16 3 1 − (addr16) ← 01H
ONEB
ES:!addr16 4 2 − (ES, addr16) ← 01H
A 1 1 − A ← 00H
X 1 1 − X ← 00H
B 1 1 − B ← 00H
C 1 1 − C ← 00H
saddr 2 1 − (saddr) ← 00H
!addr16 3 1 − (addr16) ← 00H
CLRB
ES:!addr16 4 2 − (ES,addr16) ← 00H
[HL + byte], X 3 1 − (HL + byte) ← X × ×
8-bit data
transfer
MOVS
ES:[HL + byte], X 4 2 − (ES, HL + byte) ← X × ×
rp, #word 3 1 − rp ← word
saddrp, #word 4 1 − (saddrp) ← word
sfrp, #word 4 1 − sfrp ← word
AX, saddrp 2 1 − AX ← (saddrp)
saddrp, AX 2 1 − (saddrp) ← AX
AX, sfrp 2 1 − AX ← sfrp
sfrp, AX 2 1 − sfrp ← AX
AX, rp Note 3 1 1 − AX ← rp
16-bit
data
transfer
MOVW
rp, AX Note 3 1 1 − rp ← AX
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
3. Except rp = AX
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
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Table 28-5. Operation List (5/17)
Clocks Flag Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
AX, !addr16 3 1 4 AX ← (addr16)
!addr16, AX 3 1 − (addr16) ← AX
AX, [DE] 1 1 4 AX ← (DE)
[DE], AX 1 1 − (DE) ← AX
AX, [DE + byte] 2 1 4 AX ← (DE + byte)
[DE + byte], AX 2 1 − (DE + byte) ← AX
AX, [HL] 1 1 4 AX ← (HL)
[HL], AX 1 1 − (HL) ← AX
AX, [HL + byte] 2 1 4 AX ← (HL + byte)
[HL + byte], AX 2 1 − (HL + byte) ← AX
AX, word[B] 3 1 4 AX ← (B + word)
word[B], AX 3 1 − (B + word) ← AX
AX, word[C] 3 1 4 AX ← (C + word)
word[C], AX 3 1 − (C + word) ← AX
AX, word[BC] 3 1 4 AX ← (BC + word)
word[BC], AX 3 1 − (BC + word) ← AX
AX, [SP + byte] 2 1 − AX ← (SP + byte)
[SP + byte], AX 2 1 − (SP + byte) ← AX
BC, saddrp 2 1 − BC ← (saddrp)
BC, !addr16 3 1 4 BC ← (addr16)
DE, saddrp 2 1 − DE ← (saddrp)
DE, !addr16 3 1 4 DE ← (addr16)
HL, saddrp 2 1 − HL ← (saddrp)
HL, !addr16 3 1 4 HL ← (addr16)
AX, ES:!addr16 4 2 5 AX ← (ES, addr16)
ES:!addr16, AX 4 2 − (ES, addr16) ← AX
AX, ES:[DE] 2 2 5 AX ← (ES, DE)
ES:[DE], AX 2 2 − (ES, DE) ← AX
AX, ES:[DE + byte] 3 2 5 AX ← ((ES, DE) + byte)
ES:[DE + byte], AX 3 2 − ((ES, DE) + byte) ← AX
AX, ES:[HL] 2 2 5 AX ← (ES, HL)
16-bit
data
transfer
MOVW
ES:[HL], AX 2 2 − (ES, HL) ← AX
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
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Table 28-5. Operation List (6/17)
Clocks Flag Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
AX, ES:[HL + byte] 3 2 5 AX ← ((ES, HL) + byte)
ES:[HL + byte], AX 3 2 − ((ES, HL) + byte) ← AX
AX, ES:word[B] 4 2 5 AX ← ((ES, B) + word)
ES:word[B], AX 4 2 − ((ES, B) + word) ← AX
AX, ES:word[C] 4 2 5 AX ← ((ES, C) + word)
ES:word[C], AX 4 2 − ((ES, C) + word) ← AX
AX, ES:word[BC] 4 2 5 AX ← ((ES, BC) + word)
ES:word[BC], AX 4 2 − ((ES, BC) + word) ← AX
BC, ES:!addr16 4 2 5 BC ← (ES, addr16)
DE, ES:!addr16 4 2 5 DE ← (ES, addr16)
MOVW
HL, ES:!addr16 4 2 5 HL ← (ES, addr16)
XCHW AX, rp Note 3 1 1 − AX ←→ rp
AX 1 1 − AX ← 0001H ONEW
BC 1 1 − BC ← 0001H
AX 1 1 − AX ← 0000H
16-bit
data
transfer
CLRW
BC 1 1 − BC ← 0000H
A, #byte 2 1 − A, CY ← A + byte × × ×
saddr, #byte 3 2 − (saddr), CY ← (saddr) + byte × × ×
A, r Note 4 2 1 − A, CY ← A + r × × ×
r, A 2 1 − r, CY ← r + A × × ×
A, saddr 2 1 − A, CY ← A + (saddr) × × ×
A, !addr16 3 1 4 A, CY ← A + (addr16) × × ×
A, [HL] 1 1 4 A, CY ← A + (HL) × × ×
A, [HL + byte] 2 1 4 A, CY ← A + (HL + byte) × × ×
A, [HL + B] 2 1 4 A, CY ← A + (HL + B) × × ×
A, [HL + C] 2 1 4 A, CY ← A + (HL + C) × × ×
A, ES:!addr16 4 2 5 A, CY ← A + (ES, addr16) × × ×
A, ES:[HL] 2 2 5 A,CY ← A + (ES, HL) × × ×
A, ES:[HL + byte] 3 2 5 A,CY ← A + ((ES, HL) + byte) × × ×
A, ES:[HL + B] 3 2 5 A,CY ← A + ((ES, HL) + B) × × ×
8-bit
operation
ADD
A, ES:[HL + C] 3 2 5 A,CY ← A + ((ES, HL) + C) × × ×
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
3. Except rp = AX
4. Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
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Table 28-5. Operation List (7/17)
Clocks Flag Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
A, #byte 2 1 − A, CY ← A + byte + CY × × ×
saddr, #byte 3 2 − (saddr), CY ← (saddr) + byte + CY × × ×
A, r Note 3 2 1 − A, CY ← A + r + CY × × ×
r, A 2 1 − r, CY ← r + A + CY × × ×
A, saddr 2 1 − A, CY ← A + (saddr) + CY × × ×
A, !addr16 3 1 4 A, CY ← A + (addr16) + CY × × ×
A, [HL] 1 1 4 A, CY ← A + (HL) + CY × × ×
A, [HL + byte] 2 1 4 A, CY ← A + (HL + byte) + CY × × ×
A, [HL + B] 2 1 4 A, CY ← A + (HL + B) + CY × × ×
A, [HL + C] 2 1 4 A, CY ← A + (HL + C) + CY × × ×
A, ES:!addr16 4 2 5 A, CY ← A + (ES, addr16) + CY × × ×
A, ES:[HL] 2 2 5 A, CY ← A + (ES, HL) + CY × × ×
A, ES:[HL + byte] 3 2 5 A, CY ← A + ((ES, HL) + byte) + CY × × ×
A, ES:[HL + B] 3 2 5 A, CY ← A + ((ES, HL) + B) + CY × × ×
ADDC
A, ES:[HL + C] 3 2 5 A, CY ← A + ((ES, HL) + C) + CY × × ×
A, #byte 2 1 − A, CY ← A − byte × × ×
saddr, #byte 3 2 − (saddr), CY ← (saddr) − byte × × ×
A, r Note 3 2 1 − A, CY ← A − r × × ×
r, A 2 1 − r, CY ← r − A × × ×
A, saddr 2 1 − A, CY ← A − (saddr) × × ×
A, !addr16 3 1 4 A, CY ← A − (addr16) × × ×
A, [HL] 1 1 4 A, CY ← A − (HL) × × ×
A, [HL + byte] 2 1 4 A, CY ← A − (HL + byte) × × ×
A, [HL + B] 2 1 4 A, CY ← A − (HL + B) × × ×
A, [HL + C] 2 1 4 A, CY ← A − (HL + C) × × ×
A, ES:!addr16 4 2 5 A, CY ← A − (ES:addr16) × × ×
A, ES:[HL] 2 2 5 A, CY ← A − (ES:HL) × × ×
A, ES:[HL + byte] 3 2 5 A, CY ← A − ((ES:HL) + byte) × × ×
A, ES:[HL + B] 3 2 5 A, CY ← A − ((ES:HL) + B) × × ×
8-bit
operation
SUB
A, ES:[HL + C] 3 2 5 A, CY ← A − ((ES:HL) + C) × × ×
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
3. Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
CHAPTER 28 INSTRUCTION SET
User’s Manual U17894EJ9V0UD 753
Table 28-5. Operation List (8/17)
Clocks Flag Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
A, #byte 2 1 − A, CY ← A − byte − CY × × ×
saddr, #byte 3 2 − (saddr), CY ← (saddr) − byte − CY × × ×
A, r Note 3 2 1 − A, CY ← A − r − CY × × ×
r, A 2 1 − r, CY ← r − A − CY × × ×
A, saddr 2 1 − A, CY ← A − (saddr) − CY × × ×
A, !addr16 3 1 4 A, CY ← A − (addr16) − CY × × ×
A, [HL] 1 1 4 A, CY ← A − (HL) − CY × × ×
A, [HL + byte] 2 1 4 A, CY ← A − (HL + byte) − CY × × ×
A, [HL + B] 2 1 4 A, CY ← A − (HL + B) − CY × × ×
A, [HL + C] 2 1 4 A, CY ← A − (HL + C) − CY × × ×
A, ES:!addr16 4 2 5 A, CY ← A − (ES:addr16) − CY × × ×
A, ES:[HL] 2 2 5 A, CY ← A − (ES:HL) − CY × × ×
A, ES:[HL + byte] 3 2 5 A, CY ← A − ((ES:HL) + byte) − CY × × ×
A, ES:[HL + B] 3 2 5 A, CY ← A − ((ES:HL) + B) − CY × × ×
SUBC
A, ES:[HL + C] 3 2 5 A, CY ← A − ((ES:HL) + C) − CY × × ×
A, #byte 2 1 − A ← A ∧ byte ×
saddr, #byte 3 2 − (saddr) ← (saddr) ∧ byte ×
A, r Note 3 2 1 − A ← A ∧ r ×
r, A 2 1 − r ← r ∧ A ×
A, saddr 2 1 − A ← A ∧ (saddr) ×
A, !addr16 3 1 4 A ← A ∧ (addr16) ×
A, [HL] 1 1 4 A ← A ∧ (HL) ×
A, [HL + byte] 2 1 4 A ← A ∧ (HL + byte) ×
A, [HL + B] 2 1 4 A ← A ∧ (HL + B) ×
A, [HL + C] 2 1 4 A ← A ∧ (HL + C) ×
A, ES:!addr16 4 2 5 A ← A ∧ (ES:addr16) ×
A, ES:[HL] 2 2 5 A ← A ∧ (ES:HL) ×
A, ES:[HL + byte] 3 2 5 A ← A ∧ ((ES:HL) + byte) ×
A, ES:[HL + B] 3 2 5 A ← A ∧ ((ES:HL) + B) ×
8-bit
operation
AND
A, ES:[HL + C] 3 2 5 A ← A ∧ ((ES:HL) + C) ×
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
3. Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
CHAPTER 28 INSTRUCTION SET
User’s Manual U17894EJ9V0UD
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Table 28-5. Operation List (9/17)
Clocks Flag Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
A, #byte 2 1 − A ← A ∨ byte ×
saddr, #byte 3 2 − (saddr) ← (saddr) ∨ byte ×
A, r Note 3 2 1 − A ← A ∨ r ×
r, A 2 1 − r ← r ∨ A ×
A, saddr 2 1 − A ← A ∨ (saddr) ×
A, !addr16 3 1 4 A ← A ∨ (addr16) ×
A, [HL] 1 1 4 A ← A ∨ (HL) ×
A, [HL + byte] 2 1 4 A ← A ∨ (HL + byte) ×
A, [HL + B] 2 1 4 A ← A ∨ (HL + B) ×
A, [HL + C] 2 1 4 A ← A ∨ (HL + C) ×
A, ES:!addr16 4 2 5 A ← A ∨ (ES:addr16) ×
A, ES:[HL] 2 2 5 A ← A ∨ (ES:HL) ×
A, ES:[HL + byte] 3 2 5 A ← A ∨ ((ES:HL) + byte) ×
A, ES:[HL + B] 3 2 5 A ← A ∨ ((ES:HL) + B) ×
OR
A, ES:[HL + C] 3 2 5 A ← A ∨ ((ES:HL) + C) ×
A, #byte 2 1 − A ← A ∨ byte ×
saddr, #byte 3 2 − (saddr) ← (saddr) ∨ byte ×
A, r Note 3 2 1 − A ← A ∨ r ×
r, A 2 1 − r ← r ∨ A ×
A, saddr 2 1 − A ← A ∨ (saddr) ×
A, !addr16 3 1 4 A ← A ∨ (addr16) ×
A, [HL] 1 1 4 A ← A ∨ (HL) ×
A, [HL + byte] 2 1 4 A ← A ∨ (HL + byte) ×
A, [HL + B] 2 1 4 A ← A ∨ (HL + B) ×
A, [HL + C] 2 1 4 A ← A ∨ (HL + C) ×
A, ES:!addr16 4 2 5 A ← A ∨ (ES:addr16) ×
A, ES:[HL] 2 2 5 A ← A ∨ (ES:HL) ×
A, ES:[HL + byte] 3 2 5 A ← A ∨ ((ES:HL) + byte) ×
A, ES:[HL + B] 3 2 5 A ← A ∨ ((ES:HL) + B) ×
8-bit
operation
XOR
A, ES:[HL + C] 3 2 5 A ← A ∨ ((ES:HL) + C) ×
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
3. Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
CHAPTER 28 INSTRUCTION SET
User’s Manual U17894EJ9V0UD 755
Table 28-5. Operation List (10/17)
Clocks Flag Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
A, #byte 2 1 − A − byte × × ×
saddr, #byte 3 1 − (saddr) − byte × × ×
A, r Note 3 2 1 − A − r × × ×
r, A 2 1 − r − A × × ×
A, saddr 2 1 − A − (saddr) × × ×
A, !addr16 3 1 4 A − (addr16) × × ×
A, [HL] 1 1 4 A − (HL) × × ×
A, [HL + byte] 2 1 4 A − (HL + byte) × × ×
A, [HL + B] 2 1 4 A − (HL + B) × × ×
A, [HL + C] 2 1 4 A − (HL + C) × × ×
!addr16, #byte 4 1 4 (addr16) − byte × × ×
A, ES:!addr16 4 2 5 A − (ES:addr16) × × ×
A, ES:[HL] 2 2 5 A − (ES:HL) × × ×
A, ES:[HL + byte] 3 2 5 A − ((ES:HL) + byte) × × ×
A, ES:[HL + B] 3 2 5 A − ((ES:HL) + B) × × ×
A, ES:[HL + C] 3 2 5 A − ((ES:HL) + C) × × ×
CMP
ES:!addr16, #byte 5 2 5 (ES:addr16) − byte × × ×
A 1 1 − A − 00H × × ×
X 1 1 − X − 00H × × ×
B 1 1 − B − 00H × × ×
C 1 1 − C − 00H × × ×
saddr 2 1 − (saddr) − 00H × × ×
!addr16 3 1 4 (addr16) − 00H × × ×
CMP0
ES:!addr16 4 2 5 (ES:addr16) − 00H × × ×
X, [HL + byte] 3 1 4 X − (HL + byte) × × ×
8-bit
operation
CMPS
X, ES:[HL + byte] 4 2 5 X − ((ES:HL) + byte) × × ×
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
3. Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
CHAPTER 28 INSTRUCTION SET
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Table 28-5. Operation List (11/17)
Clocks Flag
Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
AX, #word 3 1 − AX, CY ← AX + word × × ×
AX, AX 1 1 − AX, CY ← AX + AX × × ×
AX, BC 1 1 − AX, CY ← AX + BC × × ×
AX, DE 1 1 − AX, CY ← AX + DE × × ×
AX, HL 1 1 − AX, CY ← AX + HL × × ×
AX, saddrp 2 1 − AX, CY ← AX + (saddrp) × × ×
AX, !addr16 3 1 4 AX, CY ← AX + (addr16) × × ×
AX, [HL+byte] 3 1 4 AX, CY ← AX + (HL + byte) × × ×
AX, ES:!addr16 4 2 5 AX, CY ← AX + (ES:addr16) × × ×
ADDW
AX, ES: [HL+byte] 4 2 5 AX, CY ← AX + ((ES:HL) + byte) × × ×
AX, #word 3 1 − AX, CY ← AX − word × × ×
AX, BC 1 1 − AX, CY ← AX − BC × × ×
AX, DE 1 1 − AX, CY ← AX − DE × × ×
AX, HL 1 1 − AX, CY ← AX − HL × × ×
AX, saddrp 2 1 − AX, CY ← AX − (saddrp) × × ×
AX, !addr16 3 1 4 AX, CY ← AX − (addr16) × × ×
AX, [HL+byte] 3 1 4 AX, CY ← AX − (HL + byte) × × ×
AX, ES:!addr16 4 2 5 AX, CY ← AX − (ES:addr16) × × ×
SUBW
AX, ES: [HL+byte] 4 2 5 AX, CY ← AX − ((ES:HL) + byte) × × ×
AX, #word 3 1 − AX − word × × ×
AX, BC 1 1 − AX − BC × × ×
AX, DE 1 1 − AX − DE × × ×
AX, HL 1 1 − AX − HL × × ×
AX, saddrp 2 1 − AX − (saddrp) × × ×
AX, !addr16 3 1 4 AX − (addr16) × × ×
AX, [HL+byte] 3 1 4 AX − (HL + byte) × × ×
AX, ES:!addr16 4 2 5 AX − (ES:addr16) × × ×
16-bit
operation
CMPW
AX, ES: [HL+byte] 4 2 5 AX − ((ES:HL) + byte) × × ×
Multiply MULU X 1 1 − AX ← A × X
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
CHAPTER 28 INSTRUCTION SET
User’s Manual U17894EJ9V0UD 757
Table 28-5. Operation List (12/17)
Clocks Flag Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
r 1 1
− r ← r + 1 × ×
saddr 2 2
− (saddr) ← (saddr) + 1 × ×
!addr16 3 2 − (addr16) ← (addr16) + 1 × ×
[HL+byte] 3 2 − (HL+byte) ← (HL+byte) + 1 × ×
ES:!addr16 4 3 − (ES, addr16) ← (ES, addr16) + 1 × ×
INC
ES: [HL+byte] 4 3 − ((ES:HL) + byte) ← ((ES:HL) + byte) + 1 × ×
r 1 1
− r ← r − 1 × ×
saddr 2 2
− (saddr) ← (saddr) − 1 × ×
!addr16 3 2 − (addr16) ← (addr16) − 1 × ×
[HL+byte] 3 2 − (HL+byte) ← (HL+byte) − 1 × ×
ES:!addr16 4 3 − (ES, addr16) ← (ES, addr16) − 1 × ×
DEC
ES: [HL+byte] 4 3 − ((ES:HL) + byte) ← ((ES:HL) + byte) − 1 × ×
rp 1 1
− rp ← rp + 1
saddrp 2 2 − (saddrp) ← (saddrp) + 1
!addr16 3 2 − (addr16) ← (addr16) + 1
[HL+byte] 3 2 − (HL+byte) ← (HL+byte) + 1
ES:!addr16 4 3 − (ES, addr16) ← (ES, addr16) + 1
INCW
ES: [HL+byte] 4 3 − ((ES:HL) + byte) ← ((ES:HL) + byte) + 1
rp 1 1
− rp ← rp − 1
saddrp 2 2 − (saddrp) ← (saddrp) − 1
!addr16 3 2 − (addr16) ← (addr16) − 1
[HL+byte] 3 2 − (HL+byte) ← (HL+byte) − 1
ES:!addr16 4 3 − (ES, addr16) ← (ES, addr16) − 1
Increment/
decrement
DECW
ES: [HL+byte] 4 3 − ((ES:HL) + byte) ← ((ES:HL) + byte) − 1
SHR A, cnt 2 1 − (CY ← A0, Am−1 ← Am, A7 ← 0) × cnt ×
SHRW AX, cnt 2 1 − (CY ← AX0, AXm−1 ← AXm, AX15 ← 0) × cnt ×
A, cnt 2 1 − (CY ← A7, Am ← Am−1, A0 ← 0) × cnt ×
B, cnt 2 1 − (CY ← B7, Bm ← Bm−1, B0 ← 0) × cnt ×
SHL
C, cnt 2 1 − (CY ← C7, Cm ← Cm−1, C0 ← 0) × cnt ×
AX, cnt 2 1 − (CY ← AX15, AXm ← AXm−1, AX0 ← 0) × cnt ×
SHLW
BC, cnt 2 1 − (CY ← BC15, BCm ← BCm−1, BC0 ← 0) × cnt ×
SAR A, cnt 2 1 − (CY ← A0, Am−1 ← Am, A7 ← A7) × cnt ×
Shift
SARW AX, cnt 2 1 −
(CY
←
AX
0
, AX
m
−
1
←
AX
m
, AX
15
←
AX
15
)
×
cnt
×
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. cnt indicates the bit shift count.
4. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
CHAPTER 28 INSTRUCTION SET
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Table 28-5. Operation List (13/17)
Clocks Flag
Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
ROR A, 1 2 1 − (CY, A7 ← A0, Am−1 ← Am) × 1 ×
ROL A, 1 2 1 − (CY, A0 ← A7, Am + 1 ← Am) × 1 ×
RORC A, 1 2 1 − (CY ← A0, A7 ← CY, Am−1 ← Am) × 1 ×
ROLC A, 1 2 1 − (CY ← A7, A0 ← CY, Am + 1 ← Am) × 1 ×
AX,1 2 1 −
(CY
←
AX
15
, AX
0
←
CY, AX
m + 1
←
AX
m
)
×
1
×
Rotate
ROLWC
BC,1 2 1 −
(CY
←
BC
15
, BC
0
←
CY, BC
m + 1
←
BC
m
)
×
1
×
CY, saddr.bit 3 1 − CY ← (saddr).bit ×
CY, sfr.bit 3 1 − CY ← sfr.bit ×
CY, A.bit 2 1 − CY ← A.bit ×
CY, PSW.bit 3 1 − CY ← PSW.bit ×
CY,[HL].bit 2 1 4 CY ← (HL).bit ×
saddr.bit, CY 3 2 − (saddr).bit ← CY
sfr.bit, CY 3 2 − sfr.bit ← CY
A.bit, CY 2 1 − A.bit ← CY
PSW.bit, CY 3 4 − PSW.bit ← CY × ×
[HL].bit, CY 2 2 − (HL).bit ← CY
CY, ES:[HL].bit 3 2 5 CY ← (ES, HL).bit ×
MOV1
ES:[HL].bit, CY 3 3 − (ES, HL).bit ← CY
CY, saddr.bit 3 1 − CY ← CY ∧ (saddr).bit ×
CY, sfr.bit 3 1 − CY ← CY ∧ sfr.bit ×
CY, A.bit 2 1 − CY ← CY ∧ A.bit ×
CY, PSW.bit 3 1 − CY ← CY ∧ PSW.bit ×
CY,[HL].bit 2 1 4 CY ← CY ∧ (HL).bit ×
AND1
CY, ES:[HL].bit 3 2 5 CY ← CY ∧ (ES, HL).bit ×
CY, saddr.bit 3 1 − CY ← CY ∨ (saddr).bit ×
CY, sfr.bit 3 1 − CY ← CY ∨ sfr.bit ×
CY, A.bit 2 1 − CY ← CY ∨ A.bit ×
CY, PSW.bit 3 1 − CY ← CY ∨ PSW.bit ×
CY, [HL].bit 2 1 4 CY ← CY ∨ (HL).bit ×
Bit
manipulate
OR1
CY, ES:[HL].bit 3 2 5 CY ← CY ∨ (ES, HL).bit ×
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
CHAPTER 28 INSTRUCTION SET
User’s Manual U17894EJ9V0UD 759
Table 28-5. Operation List (14/17)
Clocks Flag
Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
CY, saddr.bit 3 1 − CY ← CY ∨ (saddr).bit ×
CY, sfr.bit 3 1 − CY ← CY ∨ sfr.bit ×
CY, A.bit 2 1 − CY ← CY ∨ A.bit ×
CY, PSW.bit 3 1 − CY ← CY ∨ PSW.bit ×
CY, [HL].bit 2 1 4 CY ← CY ∨ (HL).bit ×
XOR1
CY, ES:[HL].bit 3 2 5 CY ← CY ∨ (ES, HL).bit ×
saddr.bit 3 2
− (saddr).bit ← 1
sfr.bit 3 2
− sfr.bit ← 1
A.bit 2 1
− A.bit ← 1
!addr16.bit 4 2 − (addr16).bit ← 1
PSW.bit 3 4
− PSW.bit ← 1 × × ×
[HL].bit 2 2
− (HL).bit ← 1
ES:!addr16.bit 5 3 − (ES, addr16).bit ← 1
SET1
ES:[HL].bit 3 3 − (ES, HL).bit ← 1
saddr.bit 3 2
− (saddr.bit) ← 0
sfr.bit 3 2
− sfr.bit ← 0
A.bit 2 1
− A.bit ← 0
!addr16.bit 4 2 − (addr16).bit ← 0
PSW.bit 3 4
− PSW.bit ← 0 × × ×
[HL].bit 2 2
− (HL).bit ← 0
ES:!addr16.bit 5 3 − (ES, addr16).bit ← 0
CLR1
ES:[HL].bit 3 3 − (ES, HL).bit ← 0
SET1 CY 2 1 − CY ← 1 1
CLR1 CY 2 1 − CY ← 0 0
Bit
manipulate
NOT1 CY 2 1 − CY ← CY ×
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
CHAPTER 28 INSTRUCTION SET
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Table 28-5. Operation List (15/17)
Clocks Flag
Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
rp 2 3 − (SP − 2) ← (PC + 2)S, (SP − 3) ← (PC + 2)H,
(SP − 4) ← (PC + 2)L, PC ← CS, rp,
SP ← SP − 4
$!addr20 3 3 − (SP − 2) ← (PC + 3)S, (SP − 3) ← (PC + 3)H,
(SP − 4) ← (PC + 3)L, PC ← PC + 3 +
jdisp16,
SP ← SP − 4
!addr16 3 3 − (SP − 2) ← (PC + 3)S, (SP − 3) ← (PC + 3)H,
(SP − 4) ← (PC + 3)L, PC ← 0000, addr16,
SP ← SP − 4
CALL
!!addr20 4 3 − (SP − 2) ← (PC + 4)S, (SP − 3) ← (PC + 4)H,
(SP − 4) ← (PC + 4)L, PC ← addr20,
SP ← SP − 4
CALLT [addr5] 2 5 − (SP − 2) ← (PC + 2)S, (SP − 3) ← (PC + 2)H,
(SP − 4) ← (PC + 2)L , PCS ← 0000,
PCH ← (0000, addr5 + 1),
PCL ← (0000, addr5),
SP ← SP − 4
BRK − 2 5 − (SP − 1) ← PSW, (SP − 2) ← (PC + 2)S,
(SP − 3) ← (PC + 2)H, (SP − 4) ← (PC + 2)L,
PCS ← 0000,
PCH ← (0007FH), PCL ← (0007EH),
SP ← SP − 4, IE ← 0
RET − 1 6 − PCL ← (SP), PCH ← (SP + 1),
PCS ← (SP + 2), SP ← SP + 4
RETI − 2 6 − PCL ← (SP), PCH ← (SP + 1),
PCS ← (SP + 2), PSW ← (SP + 3),
SP ← SP + 4
R R R
Call/
return
RETB − 2 6 − PCL ← (SP), PCH ← (SP + 1),
PCS ← (SP + 2), PSW ← (SP + 3),
SP ← SP + 4
R R R
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
CHAPTER 28 INSTRUCTION SET
User’s Manual U17894EJ9V0UD 761
Table 28-5. Operation List (16/17)
Clocks Flag Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
PSW 2 1 − (SP − 1) ← PSW, (SP − 2) ← 00H,
SP ← SP − 2
PUSH
rp 1 1
− (SP − 1) ← rpH, (SP − 2)← rpL,
SP ← SP − 2
PSW 2 3 − PSW ← (SP + 1), SP ← SP + 2 R R R POP
rp 1 1
− rpL ← (SP), rpH ← (SP + 1), SP ← SP + 2
SP, #word 4 1 − SP ← word
SP, AX 2 1 − SP ← AX
AX, SP 2 1 − AX ← SP
HL, SP 3 1 − HL ← SP
BC, SP 3 1 − BC ← SP
MOVW
DE, SP 3 1 − DE ← SP
ADDW SP, #byte 2 1 − SP ← SP + byte
Stack
manipulate
SUBW SP, #byte 2 1 − SP ← SP − byte
AX 2 3
− PC ← CS, AX
$addr20 2 3 − PC ← PC + 2 + jdisp8
$!addr20 3 3 − PC ← PC + 3 + jdisp16
!addr16 3 3 − PC ← 0000, addr16
Unconditional
branch
BR
!!addr20 4 3 − PC ← addr20
BC $addr20 2 2/4Note 3 − PC ← PC + 2 + jdisp8 if CY = 1
BNC $addr20 2 2/4Note 3 − PC ← PC + 2 + jdisp8 if CY = 0
BZ $addr20 2 2/4Note 3 − PC ← PC + 2 + jdisp8 if Z = 1
BNZ $addr20 2 2/4Note 3 − PC ← PC + 2 + jdisp8 if Z = 0
BH $addr20 3 2/4Note 3 − PC ← PC+3+jdisp8 if (Z ∨ CY)=0
BNH $addr20 3 2/4Note 3 − PC ← PC+3+jdisp8 if (Z ∨ CY)=1
saddr.bit,
$addr20
4 3/5Note 3 − PC ← PC + 4 + jdisp8 if (saddr).bit = 1
sfr.bit, $addr20 4 3/5Note 3 − PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr20 3 3/5Note 3 − PC ← PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr20 4 3/5Note 3 − PC ← PC + 4 + jdisp8 if PSW.bit = 1
[HL].bit, $addr20 3 3/5Note 3 6/7 PC ← PC + 3 + jdisp8 if (HL).bit = 1
Conditional
branch
BT
ES:[HL].bit,
$addr20
4 4/6Note 3 7/8 PC ← PC + 4 + jdisp8
if (ES, HL).bit = 1
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
3. This indicates the number of clocks “when condition is not met/when condition is met”.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
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CHAPTER 28 INSTRUCTION SET
User’s Manual U17894EJ9V0UD
762
Table 28-5. Operation List (17/17)
Clocks Flag Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
saddr.bit, $addr20 4 3/5Note 3 − PC ← PC + 4 + jdisp8 if (saddr).bit = 0
sfr.bit, $addr20 4 3/5Note 3 − PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr20 3 3/5Note 3 − PC ← PC + 3 + jdisp8 if A.bit = 0
PSW.bit, $addr20 4 3/5Note 3 − PC ← PC + 4 + jdisp8 if PSW.bit = 0
[HL].bit, $addr20 3 3/5Note 3 6/7 PC ← PC + 3 + jdisp8 if (HL).bit = 0
BF
ES:[HL].bit, $addr20 4 4/6Note 3 7/8 PC ← PC + 4 + jdisp8 if (ES, HL).bit = 0
saddr.bit, $addr20 4 3/5Note 3 − PC ← PC + 4 + jdisp8 if (saddr).bit = 1
then reset (saddr).bit
sfr.bit, $addr20 4 3/5Note 3 − PC ← PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
A.bit, $addr20 3 3/5Note 3 − PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PSW.bit, $addr20 4 3/5Note 3 − PC ← PC + 4 + jdisp8 if PSW.bit = 1
then reset PSW.bit
× × ×
[HL].bit, $addr20 3 3/5Note 3 − PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
Conditional
branch
BTCLR
ES:[HL].bit, $addr20 4 4/6Note 3 − PC ← PC + 4 + jdisp8 if (ES, HL).bit = 1
then reset (ES, HL).bit
SKC − 2 1 − Next instruction skip if CY = 1
SKNC − 2 1 − Next instruction skip if CY = 0
SKZ − 2 1 − Next instruction skip if Z = 1
SKNZ − 2 1 − Next instruction skip if Z = 0
SKH − 2 1 − Next instruction skip if (Z ∨ CY) = 0
Conditional
skip
SKNH − 2 1 − Next instruction skip if (Z ∨ CY) = 1
SEL RBn 2 1
− RBS[1:0] ← n
NOP − 1 1
− No Operation
EI − 3 4
− IE ← 1(Enable Interrupt)
DI − 3 4
− IE ← 0(Disable Interrupt)
HALT − 2 3
− Set HALT Mode
CPU
control
STOP − 2 3
− Set STOP Mode
Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no
data access.
2. When the program memory area is accessed.
3. This indicates the number of clocks “when condition is not met/when condition is met”.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When
fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks
plus 3, maximum (except when branching to the external memory area).
3. n indicates the number of register banks (n = 0 to 3)
4. In products where the external memory area is adjacent to the internal flash area, the number of waits is
added to the number of instruction execution clocks placed in the last address (16-byte max.) in the flash
memory, in order to use the external bus interface function. This should be done because, during pre-
reading of the instruction code, an external memory wait being inserted due to an external memory area
exceeding the flash space is accessed. For the number of waits, refer to 5.4 Number of Instruction
Wait Clocks for Data Access.
<R>
<R>
User’s Manual U17894EJ9V0UD 763
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
Target products Conventional-specification products:
μ
PD78F1162, 78F1163, 78F1164, 78F1165, 78F1166,
78F1167, 78F1168
Expanded-specification products:
μ
PD78F1162A, 78F1163A, 78F1164A, 78F1165A,
78F1166A, 78F1167A, 78F1168A
Caution The 78K0R/KG3 has an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when
this function is used, and product reliability therefore cannot be guaranteed. NEC Electronics is
not liable for problems occurring when the on-chip debug function is used.
Absolute Maximum Ratings (TA = 25°C) (1/2)
Parameter Symbols Conditions Ratings Unit
VDD −0.5 to +6.5 V
EVDD0, EVDD1 EVDD0 = EVDD1 −0.5 to +6.5 V
VSS −0.5 to +0.3 V
EVSS0, EVSS1 EVSS0 = EVSS1 −0.5 to +0.3 V
AVREF0 −0.5 to VDD + 0.3Note 1 V
AVREF1 −0.5 to VDD + 0.3Note 1 V
Supply voltage
AVSS −0.5 to +0.3 V
REGC pin input voltage VIREGC REGC −0.3 to +3.6
and −0.3 to VDD + 0.3Note 2
V
VI1 P00 to P06, P10 to P17, P30, P31, P40 to P47,
P50 to P57, P64 to P67, P70 to P77, P80 to P87,
P120 to P124, P131, P140 to P145, EXCLK,
RESET, FLMD0
−0.3 to EVDD0, EVDD1 + 0.3
and −0.3 to VDD + 0.3Note 1
V
VI2 P60 to P63 (N-ch open-drain) −0.3 to +6.5 V
VI3 P20 to P27, P150 to P157 −0.3 to AVREF0 + 0.3
and −0.3 to VDD + 0.3Note 1
V
Input voltage
VI4 P110, P111 −0.3 to AVREF1 + 0.3
and −0.3 to VDD + 0.3Note 1
V
VO1 P00 to P06, P10 to P17, P30, P31, P40 to P47,
P50 to P57, P60 to P67, P70 to P77, P80 to P87,
P120, P130, P131, P140 to P145
−0.3 to EVDD0, EVDD1 + 0.3Note 1 V
VO2 P20 to P27, P150 to P157 −0.3 to AVREF0 + 0.3 V
Output voltage
VO3 P110, P111 −0.3 to AVREF1 + 0.3 V
Notes 1. Must be 6.5 V or lower.
2. Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F). This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
764
Standard Products
Absolute Maximum Ratings (TA = 25°C) (2/2)
Parameter Symbols Conditions Ratings Unit
Analog input voltage VAN ANI0 to ANI15 −0.3 to AVREF0 + 0.3Note
and −0.3 to VDD + 0.3Note
V
Analog output voltage VAO ANO0, ANO1 −0.3 to AVREF1 + 0.3 V
Per pin P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P120, P130, P131,
P140 to P145
−10 mA
P00 to P04, P40 to P47, P120,
P130, P131, P140 to P145
−25 mA
IOH1
Total of all pins
−80 mA
P05, P06, P10 to P17, P30, P31,
P50 to P57, P64 to P67,
P70 to P77, P80 to P87
−55 mA
Per pin −0.5 mA
Output current, high
IOH2
Total of all pins
P20 to P27, P110, P111,
P150 to P157 −2 mA
Per pin P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P60 to P67, P70 to P77,
P80 to P87, P120, P130, P131,
P140 to P145
30 mA
P00 to P04, P40 to P47, P120,
P130, P131, P140 to P145
60 mA
IOL1
Total of all pins
200 mA
P05, P06, P10 to P17, P30, P31,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87
140 mA
Per pin 1 mA
Output current, low
IOL2
Total of all pins
P20 to P27, P110, P111,
P150 to P157 5 mA
In normal operation mode
Operating ambient
temperature
TA
In flash memory programming mode
−40 to +85 °C
Storage temperature Tstg −65 to +150 °C
Note Must be 6.5 V or lower.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 765
Standard Products
X1 Oscillator Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Resonator Recommended
Circuit
Parameter Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 2.0 20.0
Ceramic resonator
C1
X2X1
C2
V
SS
X1 clock oscillation
frequency (fX)Note 1.8 V ≤ VDD < 2.7 V 2.0 5.0
MHz
2.7 V ≤ VDD ≤ 5.5 V 2.0 20.0
Crystal resonator
C1
X2X1
C2
VSS
X1 clock oscillation
frequency (fX)Note 1.8 V ≤ VDD < 2.7 V 2.0 5.0
MHz
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the
above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. Since the CPU is started by the internal high-speed oscillation clock after a reset release,
check the X1 clock oscillation stabilization time using the oscillation stabilization time counter
status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC
register and oscillation stabilization time select register (OSTS) after sufficiently evaluating
the oscillation stabilization time with the resonator to be used.
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
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Standard Products
Internal Oscillator Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Oscillators Parameters Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 7.6 8.0 8.4 MHz
8 MHz internal
oscillator
Internal high-
speed oscillation
clock frequency
(fIH)Note 1
1.8 V ≤ VDD < 2.7 V 5.0 8.0 8.4 MHz
2.7 V ≤ VDD ≤ 5.5 V 216 240 264 kHz Normal current mode
1.8 V ≤ VDD < 2.7 V 192 240 264 kHz
240 kHz internal
oscillator
Internal low-speed
oscillation clock
frequency (fIL)
Low consumption current modeNote 2 192 240 264 kHz
Notes 1. This only indicates the oscillator characteristics of when HIOTRM is set to 10H. Refer to AC
Characteristics for instruction execution time.
2. Regulator output is set to low consumption current mode in the following cases:
• When the RMC register is set to 5AH.
• During system reset.
• In STOP mode (except during OCD mode).
• When both the high-speed system clock (fMX) and the internal high-speed oscillation clock (fIH) are
stopped during CPU operation with the subsystem clock (fXT).
• When both the high-speed system clock (fMX) and the internal high-speed oscillation clock (fIH) are
stopped during the HALT mode when the CPU operation with the subsystem clock (fXT) has been set.
Remark For details on the normal current mode and low consumption current mode according to the regulator
output voltage, refer to CHAPTER 23 REGULATOR.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 767
Standard Products
XT1 Oscillator Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Resonator Recommended
Circuit
Parameter Conditions MIN. TYP. MAX. Unit
Crystal resonator
XT1XT2
C4 C3
Rd
VSS
XT1 clock oscillation
frequency (fXT)Note
32 32.768 35 kHz
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the
above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption,
and is more prone to malfunction due to noise than the X1 oscillator. Particular care is
therefore required with the wiring method when the XT1 clock is used.
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CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
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Standard Products
Recommended Oscillator Constants
(1) X1 oscillation: Ceramic resonator (AMPH = 0, RMC = 00H, TA = −40 to +85°C)
Recommended Circuit Constants Oscillation Voltage Range Manufacturer Part Number SMD/
Lead
Frequency
(MHz) C1 (pF) C2 (pF) MIN. (V) MAX. (V)
CSTCC2M00G56-R0 SMD 2.0 Internal (47) Internal (47) 1.8
CSTCR4M00G55-R0 SMD Internal (39) Internal (39) 1.8
CSTLS4M00G56-B0 Lead
4.0
Internal (47) Internal (47) 1.8
CSTCR4M19G55-R0 SMD Internal (39) Internal (39) 1.8
CSTLS4M19G56-B0 Lead
4.194
Internal (47) Internal (47) 1.8
CSTCR4M91G55-R0 SMD Internal (39) Internal (39) 1.8
CSTLS4M91G53-B0 Internal (15) Internal (15) 1.8
CSTLS4M91G56-B0
Lead
4.915
Internal (47) Internal (47) 2.1
CSTCR5M00G53-R0 Internal (15) Internal (15) 1.8
CSTCR5M00G55-R0
SMD
Internal (39) Internal (39) 1.8
CSTLS5M00G53-B0 Internal (15) Internal (15) 1.8
CSTLS5M00G56-B0
Lead
5.0
Internal (47) Internal (47) 2.1
CSTCR6M00G53-R0 Internal (15) Internal (15) 1.8
CSTCR6M00G55-R0
SMD
Internal (39) Internal (39) 1.9
CSTLS6M00G53-B0 Internal (15) Internal (15) 1.8
CSTLS6M00G56-B0
Lead
6.0
Internal (47) Internal (47) 2.2
CSTCE8M00G52-R0 Internal (10) Internal (10) 1.8
CSTCE8M00G55-R0
SMD
Internal (33) Internal (33) 1.9
CSTLS8M00G53-B0 Internal (15) Internal (15) 1.8
CSTLS8M00G56-B0
Lead
8.0
Internal (47) Internal (47) 2.4
CSTCE8M38G52-R0 Internal (10) Internal (10) 1.8
CSTCE8M38G55-R0
SMD
Internal (33) Internal (33) 1.9
CSTLS8M38G53-B0 Internal (15) Internal (15) 1.8
CSTLS8M38G56-B0
Lead
8.388
Internal (47) Internal (47) 2.4
CSTCE10M0G52-R0 Internal (10) Internal (10) 1.8
CSTCE10M0G55-R0
SMD
Internal (33) Internal (33) 2.1
Murata
Manufacturing
Co., Ltd.
CSTLS10M0G53-B0 Lead
10.0
Internal (15) Internal (15) 1.8
5.5
DCRHTC(P)2.00LL 2.0 Internal (30) Internal (30)
DCRHTC(P)4.00LL
Lead
4.0 Internal (30) Internal (30)
DECRHTC4.00 SMD 4.0 Internal (15) Internal (15)
TOKO, Inc.
DCRHYC(P)8.00A Lead 8.0 Internal (22) Internal (22)
1.8 5.5
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer. If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on
the implementation circuit.
When doing so, check the conditions for using the AMPH bit, RMC register, and whether to enter
or exit the STOP mode.
The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use
the 78K0R/KG3 so that the internal operation conditions are within the specifications of the DC
and AC characteristics.
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 769
Standard Products
(2) X1 oscillation: Crystal resonator (AMPH = 0, RMC = 00H, TA = −40 to +85°C)
Recommended Circuit
Constants
Oscillation Voltage Range
Manufacturer Part Number SMD/
Lead
Frequency
(MHz)
C1 (pF) C2 (pF) MIN. (V) MAX. (V)
HC49SFWB04194D0PPTZZ
CX49GFWB04194D0PPTZZ
Lead
CX1255GB04194D0PPTZZ SMD
4.194 10 10 1.8
HC49SFWB05000D0PPTZZ
CX49GFWB05000D0PPTZZ
Lead
CX1255GB05000D0PPTZZ
CX8045GB05000D0PPTZZ
SMD
5.0 10 10 1.8
HC49SFWB08380D0PPTZZ
CX49GFWB08380D0PPTZZ
Lead
CX1255GB08380D0PPTZZ
CX8045GB08380D0PPTZZ
CX5032GB08380D0PPTZZ
SMD
8.38 10 10 1.8
HC49SFWB10000D0PPTZZ
CX49GFWB10000D0PPTZZ
Lead
CX1255GB10000D0PPTZZ
CX8045GB10000D0PPTZZ
CX5032GB10000D0PPTZZ
CX5032SB10000D0PPTZZ
KYOCERA
KINSEKI
Co., Ltd.
CX3225GB10000D0PPTZZ
SMD
10.0 10 10 1.8
5.5
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer. If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on
the implementation circuit.
When doing so, check the conditions for using the AMPH bit, RMC register, and whether to enter
or exit the STOP mode.
The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use
the 78K0R/KG3 so that the internal operation conditions are within the specifications of the DC
and AC characteristics.
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
770
Standard Products
(3) X1 oscillation: Ceramic resonator (AMPH = 1, RMC = 00H, TA = −40 to +85°C)
Recommended Circuit Constants Oscillation Voltage Range Manufacturer Part Number SMD/
Lead
Frequency
(MHz) C1 (pF) C2 (pF) MIN. (V) MAX. (V)
CSTCE12M0G55-R0 SMD 12.0 Internal (33) Internal (33) 1.8
CSTCE16M0V53-R0 SMD Internal (15) Internal (15) 1.8
CSTLS16M0X51-B0 Lead
16.0
Internal (5) Internal (5) 1.8
CSTCE20M0V53-R0 SMD Internal (15) Internal (15) 1.9
CSTCG20M0V53-R0 Small
SMD
Internal (15) Internal (15) 2.0
Murata
Manufacturing
Co., Ltd.
CSTLS20M0X51-B0 Lead
20.0
Internal (5) Internal (5) 1.9
5.5
DCRHYC(P)12.00A Lead 12.0 Internal (22) Internal (22)
DCRHZ(P)16.00A-15 Lead 16.0 Internal (15) Internal (15)
1.8
DCRHZ(P)20.00A-15 Lead Internal (15) Internal (15) 2.0
TOKO, Inc.
DECRHZ20.00 SMD
20.0
Internal (10) Internal (10) 1.8
5.5
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer. If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on
the implementation circuit.
When doing so, check the conditions for using the AMPH bit, RMC register, and whether to enter
or exit the STOP mode.
The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use
the 78K0R/KG3 so that the internal operation conditions are within the specifications of the DC
and AC characteristics.
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 771
Standard Products
(4) X1 oscillation: Crystal resonator (AMPH = 1, RMC = 00H, TA = −40 to +85°C)
Recommended Circuit
Constants
Oscillation Voltage Range
Manufacturer Part Number SMD/
Lead
Frequency
(MHz)
C1 (pF) C2 (pF) MIN. (V) MAX. (V)
HC49SFWB16000D0PPTZZ
CX49GFWB16000D0PPTZZ
Lead
CX1255GB16000D0PPTZZ
CX8045GB16000D0PPTZZ
CX5032GB16000D0PPTZZ
CX5032SB16000D0PPTZZ
CX3225GB16000D0PPTZZ
CX3225SB16000D0PPTZZ
CX2520SB16000D0PPTZZ
SMD
16.0 10 10 1.8
HC49SFWB20000D0PPTZZ
CX49GFWB20000D0PPTZZ
Lead
CX1255GB20000D0PPTZZ
CX8045GB20000D0PPTZZ
CX5032GB20000D0PPTZZ
CX5032SB20000D0PPTZZ
CX3225GB20000D0PPTZZ
CX3225SB20000D0PPTZZ
CX2520SB20000D0PPTZZ
KYOCERA
KINSEKI
Co., Ltd.
CX2016SB20000D0PPTZZ
SMD
20.0 10 10 2.3
5.5
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer. If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on
the implementation circuit.
When doing so, check the conditions for using the AMPH bit, RMC register, and whether to enter
or exit the STOP mode.
The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use
the 78K0R/KG3 so that the internal operation conditions are within the specifications of the DC
and AC characteristics.
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
772
Standard Products
(5) XT1 oscillation: Crystal resonator (TA = −40 to +85°C)
Recommended Circuit Constants Oscillation Voltage RangeManufacturer Part
Number
SMD/
Lead
Frequency
(kHz)
Load Capacitance
CL (pF) C3 (pF) C4 (pF) Rd (kΩ) MIN. (V) MAX. (V)
6.0 5 5 0 SP-T2A SMD
12.5 18 18 0
7.0 7 7 0 SSP-T7 Small
SMD 12.5 18 18 0
6.0 5 5 0
Seiko
Instruments
Inc.
VT-200 Lead
32.768
12.5 18 18 0
1.8 5.5
12 15 0 CM200S SMD 9.0
12 15 100
15 15 0 CM315 SMD 9.0
15 15 100
15 12 0
CITIZEN
FINETECH
MIYOTA CO.,
LTD.
CM519 SMD
32.768
9.0
15 12 100
1.8 5.5
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer. If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on
the implementation circuit.
When doing so, check the conditions for using the RMC register, and whether to enter or exit the
STOP mode.
The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use
the 78K0R/KG3 so that the internal operation conditions are within the specifications of the DC
and AC characteristics.
(6) XT1 oscillation: Crystal resonator (TA = −20 to +70°C)
Recommended Circuit Constants Oscillation Voltage RangeManufacturer Part
Number
SMD/
Lead
Frequency
(kHz)
Load Capacitance
CL (pF) C3 (pF) C4 (pF) Rd (kΩ) MIN. (V) MAX. (V)
22 18 0 12.5
22 18 100
12 15 0
CITIZEN
FINETECH
MIYOTA CO.,
LTD.
CFS-206 Lead 32.768
9.0
12 15 100
1.8 5.5
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer. If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on
the implementation circuit.
When doing so, check the conditions for using the RMC register, and whether to enter or exit the
STOP mode.
The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use
the 78K0R/KG3 so that the internal operation conditions are within the specifications of the DC
and AC characteristics.
<R>
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 773
Standard Products
DC Characteristics (1/16)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V −3.0 mA
2.7 V ≤ VDD < 4.0 V −1.0 mA
Per pin for P00 to P06, P10 to P17,
P30, P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77, P80 to P87,
P120, P130, P131, P140 to P145 1.8 V ≤ VDD < 2.7 V −1.0 mA
4.0 V ≤ VDD ≤ 5.5 V −20.0 mA
2.7 V ≤ VDD < 4.0 V −10.0 mA
Total of P00 to P04, P40 to P47,
P120, P130, P131, P140 to P145
(When duty = 70%Note 2) 1.8 V ≤ VDD < 2.7 V −5.0 mA
4.0 V ≤ VDD ≤ 5.5 V −30.0 mA
2.7 V ≤ VDD < 4.0 V −19.0 mA
Total of P05, P06, P10 to P17, P30,
P31, P50 to P57, P64 to P67,
P70 to P77, P80 to P87
(When duty = 70%Note 2) 1.8 V ≤ VDD < 2.7 V −10.0 mA
4.0 V ≤ VDD ≤ 5.5 V −50.0 mA
2.7 V ≤ VDD < 4.0 V −29.0 mA
IOH1
Total of all pins
(When duty = 60%Note 2)
1.8 V ≤ VDD < 2.7 V −15.0 mA
Per pin for P20 to P27, P150 to P157 AVREF0 ≤ VDD −0.1 mA
Output current,
highNote 1
IOH2
Per pin for P110, P111 AVREF1 ≤ VDD −0.1 mA
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from EVDD0 or
EVDD1 pin to an output pin.
2. Specification under conditions where the duty factor is 60% or 70%.
The output current value that has changed the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 50% and IOH = −20.0 mA
Total output current of pins = (−20.0 × 0.7)/(50 × 0.01) = −28.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Caution P02 to P04, P43, P45, P142 to P144 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
774
Standard Products
DC Characteristics (2/16)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V 8.5 mA
2.7 V ≤ VDD < 4.0 V 1.0 mA
Per pin for P00 to P02, P05, P06,
P10 to P17, P30, P31, P40 to P47,
P50 to P57, P64 to P67, P70 to P77,
P80 to P87, P120, P130, P131,
P140, P141, P144, P145
1.8 V ≤ VDD < 2.7 V 0.5 mA
4.0 V ≤ VDD ≤ 5.5 V 8.5 mA
2.7 V ≤ VDD < 4.0 V 1.5 mA
Per pin for P03, P04, P142, P143
1.8 V ≤ VDD < 2.7 V 0.6 mA
4.0 V ≤ VDD ≤ 5.5 V 15.0 mA
2.7 V ≤ VDD < 4.0 V 3.0 mA
Per pin for P60 to P63
1.8 V ≤ VDD < 2.7 V 2.0 mA
4.0 V ≤ VDD ≤ 5.5 V 20.0 mA
2.7 V ≤ VDD < 4.0 V 15.0 mA
Total of P00 to P04, P40 to P47,
P120, P130, P131, P140 to P145
(When duty = 70%Note 2) 1.8 V ≤ VDD < 2.7 V 9.0 mA
4.0 V ≤ VDD ≤ 5.5 V 45.0 mA
2.7 V ≤ VDD < 4.0 V 35.0 mA
Total of P05, P06, P10 to P17, P30,
P31, P50 to P57, P60 to P67,
P70 to P77, P80 to P87
(When duty = 70%Note 2) 1.8 V ≤ VDD < 2.7 V 20.0 mA
4.0 V ≤ VDD ≤ 5.5 V 65.0 mA
2.7 V ≤ VDD < 4.0 V 50.0 mA
IOL1
Total of all pins
(When duty = 60%Note 2)
1.8 V ≤ VDD < 2.7 V 29.0 mA
Per pin for P20 to P27, P150 to P157 AVREF0 ≤ VDD 0.4 mA
Output current,
lowNote 1
IOL2
Per pin for P110, P111 AVREF1 ≤ VDD 0.4 mA
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from an output
pin to EVSS0, EVSS1, VSS, and AVSS pin.
2. Specification under conditions where the duty factor is 60% or 70%.
The output current value that has changed the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 50% and IOL = 20.0 mA
Total output current of pins = (20.0 × 0.7)/(50 × 0.01) = 28.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 775
Standard Products
DC Characteristics (3/16)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VIH1 P01, P02, P12, P13, P15, P41, P45, P52 to P57,
P64 to P67, P80 to P87, P121 to P124, P144
0.7VDD VDD V
VIH2 P00, P03 to P06, P10, P11, P14,
P16, P17, P30, P31, P40, P42 to
P44, P46, P47, P50, P51, P70 to
P77, P120, P131, P140 to P143,
P145, EXCLK, RESET
Normal input buffer 0.8VDD VDD V
TTL input buffer
4.0 V ≤ VDD ≤ 5.5 V
2.2 VDD V
TTL input buffer
2.7 V ≤ VDD < 4.0 V
2.0 VDD V
VIH3 P03, P04, P43, P44, P142, P143
TTL input buffer
1.8 V ≤ VDD < 2.7 V
1.6 VDD V
2.7 V ≤ AVREF0 ≤ VDDVIH4 P20 to P27, P150 to P157
AVREF0 = VDD < 2.7 V
0.7AVREF0 AVREF0 V
2.7 V ≤ AVREF1 ≤ VDDVIH5 P110, P111
AVREF1 = VDD < 2.7 V
0.7AVREF1 AVREF1 V
VIH6 P60 to P63 0.7VDD 6.0 V
Input voltage,
high
VIH7 FLMD0 0.9VDD
Note
V
DD V
Note Must be 0.9VDD or higher when used in the flash memory programming mode.
Cautions 1. The maximum value of VIH of pins P02 to P04, P43, P45, and P142 to P144 is VDD, even in the N-
ch open-drain mode.
2. For P122/EXCLK, the value of VIH and VIL differs according to the input port mode or external
clock mode.
Make sure to satisfy the DC characteristics of EXCLK in external clock input mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
776
Standard Products
DC Characteristics (4/16)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VIL1 P01, P02, P12, P13, P15, P41, P45, P52 to P57,
P64 to P67, P80 to P87, P121 to P124, P144
0 0.3VDD V
VIL2 P00, P03 to P06, P10, P11, P14,
P16, P17, P30, P31, P40, P42 to
P44, P46, P47, P50, P51, P70 to
P77, P120, P131, P140 to P143,
P145, EXCLK, RESET
Normal input buffer 0 0.2VDD V
TTL input buffer
4.0 V ≤ VDD ≤ 5.5 V
0 0.8 V
TTL input buffer
2.7 V ≤ VDD < 4.0 V
0 0.5 V
VIL3 P03, P04, P43, P44, P142, P143
TTL input buffer
1.8 V ≤ VDD < 2.7 V
0 0.2 V
2.7 V ≤ AVREF0 ≤ VDDVIL4 P20 to P27, P150 to P157
AVREF0 = VDD < 2.7 V
0 0.3AVREF0 V
2.7 V ≤ AVREF1 ≤ VDDVIL5 P110, P111
AVREF1 = VDD < 2.7 V
0 0.3AVREF1 V
VIL6 P60 to P63 0 0.3VDD V
Input voltage,
low
VIL7 FLMD0Note 0 0.1VDD V
Note When disabling writing of the flash memory, connect the FLMD0 pin processing directly to VSS, and maintain
a voltage less than 0.1VDD.
Cautions 1. The maximum value of VIH of pins P02 to P04, P43, P45, and P142 to P144 is VDD, even in the N-
ch open-drain mode.
2. For P122/EXCLK, the value of VIH and VIL differs according to the input port mode or external
clock mode.
Make sure to satisfy the DC characteristics of EXCLK in external clock input mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 777
Standard Products
DC Characteristics (5/16)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V,
IOH1 = −3.0 mA
VDD − 0.7 V VOH1 P00 to P06, P10 to P17, P30, P31,
P40 to P47, P50 to P57, P64 to P67,
P70 to P77, P80 to P87, P120, P130,
P131, P140 to P145
1.8 V ≤ VDD ≤ 5.5 V,
IOH1 = −1.0 mA
VDD − 0.5 V
P20 to P27, P150 to P157 AVREF0 ≤ VDD,
IOH2 = −0.1 mA
AVREF0 −
0.5
V
Output voltage,
high
VOH2
P110, P111 AVREF1 ≤ VDD,
IOH2 = −0.1 mA
AVREF1 −
0.5
V
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 8.5 mA
0.7 V
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 1.0 mA
0.5 V
P00 to P02, P05, P06, P10 to P17,
P30, P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77, P80 to P87,
P120, P130, P131, P140, P141,
P144, P145 1.8 V ≤ VDD ≤ 5.5 V,
IOL1 = 0.5 mA
0.4 V
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 8.5 mA
0.7 V
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 1.5 mA
0.5 V
VOL1
P03, P04, P142, P143
1.8 V ≤ VDD ≤ 5.5 V,
IOL1 = 0.6 mA
0.4 V
P20 to P27, P150 to P157 AVREF0 ≤ VDD,
IOL2 = 0.4 mA
0.4 V
VOL2
P110, P111 AVREF1 ≤ VDD,
IOL2 = 0.4 mA
0.4 V
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 15.0 mA
2.0 V
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 5.0 mA
0.4 V
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 3.0 mA
0.4 V
Output voltage,
low
VOL3 P60 to P63
1.8 V ≤ VDD ≤ 5.5 V,
IOL1 = 2.0 mA
0.4 V
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
778
Standard Products
DC Characteristics (6/16)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ILIH1 P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P60 to P67, P70 to P77,
P80 to P87, P120, P131,
P140 to P145, FLMD0, RESET
VI = VDD 1
μ
A
VI = AVREF0,
2.7 V ≤ AVREF0 ≤ VDD
ILIH2 P20 to P27, P150 to P157
VI = AVREF0,
AVREF0 = VDD < 2.7 V
1
μ
A
VI = AVREF1,
2.7 V ≤ AVREF1 ≤ VDD
ILIH3 P110, P111
VI = AVREF1,
AVREF1 = VDD < 2.7 V
1
μ
A
In input port 1
μ
A
Input leakage
current, high
ILIH4 P121 to P124
(X1, X2, XT1, XT2)
VI = VDD
In resonator
connection
10
μ
A
ILIL1 P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P60 to P67, P70 to P77,
P80 to P87, P120, P131,
P140 to P145, FLMD0, RESET
VI = VSS −1
μ
A
VI = VSS,
2.7 V ≤ AVREF0 ≤ VDD
ILIL2 P20 to P27, P150 to P157
VI = VSS,
AVREF0 = VDD < 2.7 V
−1
μ
A
VI = VSS,
2.7 V ≤ AVREF1 ≤ VDD
ILIL3 P110, P111
VI = VSS,
AVREF1 = VDD < 2.7 V
−1
μ
A
In input port −1
μ
A
Input leakage
current, low
ILIL4 P121 to P124
(X1, X2, XT1, XT2)
VI = VSS
In resonator
connection
−10
μ
A
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 779
Standard Products
DC Characteristics (7/16)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
On-chip pull-up
resistance
RU P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P120, P131,
P140 to P145
VI = VSS, In input port 10 20 100 kΩ
FLMD0 pin
external pull-down
resistanceNote
RFLMD0 When enabling the self-programming mode setting with
software
100 kΩ
Note It is recommended to leave the FLMD0 pin open. If the pin is required to be pulled down externally, set
RFLMD0 to 100 kΩ or more.
78K0R/KG3
FLMD0 pin
R
FLMD0
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
780
Standard Products
DC Characteristics (8/16)
μ
PD78F1162, 78F1162A, 78F1163, 78F1163A, 78F1164, 78F1164A, 78F1165, 78F1165A, 78F1166, 78F1166A
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Square wave input 7.0 12.2 mA
fMX = 20 MHzNote 2,
VDD = 5.0 V Resonator connection 7.3 12.5 mA
Square wave input 7.0 12.2 mA
fMX = 20 MHzNote 2,
VDD = 3.0 V Resonator connection 7.3 12.5 mA
Square wave input 3.8 6.2 mA
fMX = 10 MHzNotes 2, 3,
VDD = 5.0 V Resonator connection 3.9 6.3 mA
Square wave input 3.8 6.2 mA
fMX = 10 MHzNotes 2, 3,
VDD = 3.0 V Resonator connection 3.9 6.3 mA
Square wave input 2.1 3.0 mA
Normal current
mode Resonator connection 2.2 3.1 mA
Square wave input 1.5 2.1 mA
fMX = 5 MHzNotes 2, 3,
VDD = 3.0 V
Low consumption
current modeNote 4 Resonator connection 1.5 2.1 mA
Square wave input 1.4 2.1 mA
Normal current
mode Resonator connection 1.4 2.1 mA
Square wave input 1.4 2.0 mA
fMX = 5 MHzNotes 2, 3,
VDD = 2.0 V
Low consumption
current modeNote 4 Resonator connection 1.4 2.0 mA
VDD = 5.0 V 3.1 5.0 mA
Supply
current
IDD1Note 1 Operating
mode
fIH = 8 MHzNote 5
VDD = 3.0 V 3.1 5.0 mA
Notes 1. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, D/A
converter, LVI circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. When internal high-speed oscillator and subsystem clock are stopped.
3. When AMPH (bit 0 of clock operation mode control register (CMC)) = 0 and FSEL (bit 0 of operation speed
mode control register (OSMC)) = 0.
4. When the RMC register is set to 5AH.
5. When high-speed system clock and subsystem clock are stopped. When FSEL (bit 0 of operation speed
mode control register (OSMC)) = 0 is set.
Remarks 1. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
f
IH: Internal high-speed oscillation clock frequency
2. For details on the normal current mode and low consumption current mode according to the regulator
output voltage, refer to CHAPTER 23 REGULATOR.
3. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 781
Standard Products
DC Characteristics (9/16)
μ
PD78F1162, 78F1162A, 78F1163, 78F1163A, 78F1164, 78F1164A, 78F1165, 78F1165A, 78F1166, 78F1166A
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V 6.4 24.0
μ
A
VDD = 3.0 V 6.4 24.0
μ
A
fSUB = 32.768 kHzNote 2,
TA = −40 to +70°C
VDD = 2.0 V 6.3 21.0
μ
A
VDD = 5.0 V 6.4 31.0
μ
A
VDD = 3.0 V 6.4 31.0
μ
A
Supply
current
IDD1Note 1 Operating
mode
fSUB = 32.768 kHzNote 2,
TA = −40 to +85°C
VDD = 2.0 V 6.3 28.0
μ
A
Notes 1. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, D/A
converter, LVI circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. When internal high-speed oscillator and high-speed system clock are stopped. When watchdog timer is
stopped.
Remarks 1. f
SUB : Subsystem clock frequency (XT1 clock oscillation frequency)
2. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
782
Standard Products
DC Characteristics (10/16)
μ
PD78F1162, 78F1162A, 78F1163, 78F1163A, 78F1164, 78F1164A, 78F1165, 78F1165A, 78F1166, 78F1166A
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Square wave input 1.0 2.7 mA
fMX = 20 MHzNote 2,
VDD = 5.0 V Resonator connection 1.3 3.0 mA
Square wave input 1.0 2.7 mA
fMX = 20 MHzNote 2,
VDD = 3.0 V Resonator connection 1.3 3.0 mA
Square wave input 0.52 1.4 mA
fMX = 10 MHzNotes 2, 3,
VDD = 5.0 V Resonator connection 0.62 1.5 mA
Square wave input 0.52 1.4 mA
fMX = 10 MHzNotes 2, 3,
VDD = 3.0 V Resonator connection 0.62 1.5 mA
Square wave input 0.36 0.75 mA
Normal current
mode Resonator connection 0.41 0.8 mA
Square wave input 0.22 0.5 mA
fMX = 5 MHzNotes 2, 3,
VDD = 3.0 V
Low consumption
current modeNote 4 Resonator connection 0.27 0.55 mA
Square wave input 0.22 0.5 mA
Normal current
mode Resonator connection 0.27 0.55 mA
Square wave input 0.22 0.5 mA
fMX = 5 MHzNotes 2, 3,
VDD = 2.0 V
Low consumption
current modeNote 4 Resonator connection 0.27 0.55 mA
VDD = 5.0 V 0.45 1.2 mA
Supply
current
IDD2Note 1 HALT
mode
fIH = 8 MHzNote 5
VDD = 3.0 V 0.45 1.2 mA
Notes 1. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. The maximum value include the peripheral operation
current. However, not including the current flowing into the A/D converter, D/A converter, LVI circuit, I/O
port, and on-chip pull-up/pull-down resistors. During HALT instruction execution by flash memory.
2. When internal high-speed oscillator and subsystem clock are stopped.
3. When AMPH (bit 0 of clock operation mode control register (CMC)) = 0 and FSEL (bit 0 of operation speed
mode control register (OSMC)) = 0.
4. When the RMC register is set to 5AH.
5. When high-speed system clock and subsystem clock are stopped. When FSEL (bit 0 of operation speed
mode control register (OSMC)) = 0 is set.
Remarks 1. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
f
IH: Internal high-speed oscillation clock frequency
2. For details on the normal current mode and low consumption current mode according to the regulator
output voltage, refer to CHAPTER 23 REGULATOR.
3. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 783
Standard Products
DC Characteristics (11/16)
μ
PD78F1162, 78F1162A, 78F1163, 78F1163A, 78F1164, 78F1164A, 78F1165, 78F1165A, 78F1166, 78F1166A
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V 2.2 14.0
μ
A
VDD = 3.0 V 2.2 14.0
μ
A
fSUB = 32.768 kHzNote 2,
TA = −40 to +70°C
VDD = 2.0 V 2.1 13.8
μ
A
VDD = 5.0 V 2.2 21.0
μ
A
VDD = 3.0 V 2.2 21.0
μ
A
IDD2Note 1 HALT
mode
fSUB = 32.768 kHzNote 2,
TA = −40 to +85°C
VDD = 2.0 V 2.1 20.8
μ
A
TA = −40 to +70°C 1.1 9.0
μ
A
Supply
current
IDD3Note 3 STOP
mode TA = −40 to +85°C 1.1 16.0
μ
A
Notes 1. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. The maximum value include the peripheral operation
current. However, not including the current flowing into the A/D converter, D/A converter, LVI circuit, I/O
port, and on-chip pull-up/pull-down resistors. During HALT instruction execution by flash memory.
2. When internal high-speed oscillator and high-speed system clock are stopped. When watchdog timer is
stopped.
3. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. When subsystem clock is stopped. When watchdog
timer is stopped.
Remarks 1. fSUB : Subsystem clock frequency (XT1 clock oscillation frequency)
2. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
784
Standard Products
DC Characteristics (12/16)
μ
PD78F1167, 78F1167A, 78F1168, 78F1168A
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Square wave input 7.0 12.2 mA
fMX = 20 MHzNote 2,
VDD = 5.0 V
Resonator connection 7.3 12.5 mA
Square wave input 7.0 12.2 mA
fMX = 20 MHzNote 2,
VDD = 3.0 V Resonator connection 7.3 12.5 mA
Square wave input 3.8 6.2 mA
fMX = 10 MHzNotes 2, 3,
VDD = 5.0 V
Resonator connection 3.9 6.3 mA
Square wave input 3.8 6.2 mA
fMX = 10 MHzNotes 2, 3,
VDD = 3.0 V Resonator connection 3.9 6.3 mA
Square wave input 2.1 3.0 mA
Normal current
mode Resonator connection 2.2 3.1 mA
Square wave input 1.5 2.1 mA
fMX = 5 MHzNotes 2, 3,
VDD = 3.0 V
Low consumption
current modeNote 4 Resonator connection 1.5 2.1 mA
Square wave input 1.4 2.1 mA
Normal current
mode Resonator connection 1.4 2.1 mA
Square wave input 1.4 2.0 mA
fMX = 5 MHzNotes 2, 3,
VDD = 2.0 V
Low consumption
current modeNote 4 Resonator connection 1.4 2.0 mA
VDD = 5.0 V
3.1 5.0 mA
Supply
current
IDD1Note 1 Operating
mode
fIH = 8 MHzNote 5
VDD = 3.0 V 3.1 5.0 mA
Notes 1. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, D/A
converter, LVI circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. When internal high-speed oscillator and subsystem clock are stopped.
3. When AMPH (bit 0 of clock operation mode control register (CMC)) = 0 and FSEL (bit 0 of operation speed
mode control register (OSMC)) = 0.
4. When the RMC register is set to 5AH.
5. When high-speed system clock and subsystem clock are stopped. When FSEL (bit 0 of operation speed
mode control register (OSMC)) = 0 is set.
Remarks 1. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
f
IH: Internal high-speed oscillation clock frequency
2. For details on the normal current mode and low consumption current mode according to the regulator
output voltage, refer to CHAPTER 23 REGULATOR.
3. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 785
Standard Products
DC Characteristics (13/16)
μ
PD78F1167, 78F1167A, 78F1168, 78F1168A
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V 6.4 36.0
μ
A
VDD = 3.0 V 6.4 36.0
μ
A
fSUB = 32.768 kHzNote 2,
TA = −40 to +70°C
VDD = 2.0 V 6.3 32.8
μ
A
VDD = 5.0 V 6.4 51.0
μ
A
VDD = 3.0 V 6.4 51.0
μ
A
Supply
current
IDD1Note 1 Operating
mode
fSUB = 32.768 kHzNote 2,
TA = −40 to +85°C
VDD = 2.0 V 6.3 47.8
μ
A
Notes 1. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, D/A
converter, LVI circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. When internal high-speed oscillator and high-speed system clock are stopped. When watchdog timer is
stopped.
Remarks 1. fSUB : Subsystem clock frequency (XT1 clock oscillation frequency)
2. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
786
Standard Products
DC Characteristics (14/16)
μ
PD78F1167, 78F1167A, 78F1168, 78F1168A
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Square wave input 1.0 2.7 mA
fMX = 20 MHzNote 2,
VDD = 5.0 V
Resonator connection 1.3 3.0 mA
Square wave input 1.0 2.7 mA
fMX = 20 MHzNote 2,
VDD = 3.0 V Resonator connection 1.3 3.0 mA
Square wave input 0.52 1.4 mA
fMX = 10 MHzNotes 2, 3,
VDD = 5.0 V
Resonator connection 0.62 1.5 mA
Square wave input 0.52 1.4 mA
fMX = 10 MHzNotes 2, 3,
VDD = 3.0 V Resonator connection 0.62 1.5 mA
Square wave input 0.36 0.75 mA
Normal current
mode Resonator connection 0.41 0.8 mA
Square wave input 0.22 0.5 mA
fMX = 5 MHzNotes 2, 3,
VDD = 3.0 V
Low consumption
current modeNote 4 Resonator connection 0.27 0.55 mA
Square wave input 0.22 0.5 mA
Normal current
mode Resonator connection 0.27 0.55 mA
Square wave input 0.22 0.5 mA
fMX = 5 MHzNotes 2, 3,
VDD = 2.0 V
Low consumption
current modeNote 4 Resonator connection 0.27 0.55 mA
VDD = 5.0 V
0.45 1.2 mA
Supply
current
IDD2Note 1 HALT
mode
fIH = 8 MHzNote 5
VDD = 3.0 V 0.45 1.2 mA
Notes 1. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. The maximum value include the peripheral operation
current. However, not including the current flowing into the A/D converter, D/A converter, LVI circuit, I/O
port, and on-chip pull-up/pull-down resistors. During HALT instruction execution by flash memory.
2. When internal high-speed oscillator and subsystem clock are stopped.
3. When AMPH (bit 0 of clock operation mode control register (CMC)) = 0 and FSEL (bit 0 of operation speed
mode control register (OSMC)) = 0.
4. When the RMC register is set to 5AH.
5. When high-speed system clock and subsystem clock are stopped. When FSEL (bit 0 of operation speed
mode control register (OSMC)) = 0 is set.
Remarks 1. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
f
IH: Internal high-speed oscillation clock frequency
2. For details on the normal current mode and low consumption current mode according to the regulator
output voltage, refer to CHAPTER 23 REGULATOR.
3. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 787
Standard Products
DC Characteristics (15/16)
μ
PD78F1167, 78F1167A, 78F1168, 78F1168A
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V 2.2 26.0
μ
A
VDD = 3.0 V 2.2 26.0
μ
A
fSUB = 32.768 kHzNote 2,
TA = −40 to +70°C
VDD = 2.0 V 2.1 25.8
μ
A
VDD = 5.0 V 2.2 41.0
μ
A
VDD = 3.0 V 2.2 41.0
μ
A
IDD2Note 1 HALT
mode
fSUB = 32.768 kHzNote 2,
TA = −40 to +85°C
VDD = 2.0 V 2.1 40.8
μ
A
TA = −40 to +70°C 1.1 21.0
μ
A
Supply
current
IDD3Note 3 STOP
mode TA = −40 to +85°C 1.1 36.0
μ
A
Notes 1. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. The maximum value include the peripheral operation
current. However, not including the current flowing into the A/D converter, D/A converter, LVI circuit, I/O
port, and on-chip pull-up/pull-down resistors. During HALT instruction execution by flash memory.
2. When internal high-speed oscillator and high-speed system clock are stopped. When watchdog timer is
stopped.
3. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. When subsystem clock is stopped. When watchdog
timer is stopped.
Remarks 1. fSUB : Subsystem clock frequency (XT1 clock oscillation frequency)
2. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
788
Standard Products
DC Characteristics (16/16)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 3.0 V 0.2 1.0
RTC operating
current
IRTCNotes 1, 2 fSUB = 32.768 kHz
VDD = 2.0 V 0.2 1.0
μ
A
Watchdog timer
operating
current
IWDTNotes 2, 3 fIL = 240 kHz 5 10
μ
A
A/D converter
operating
current
IADCNote 4 During conversion at maximum speed,
2.3 V ≤ AVREF0
0.86 1.9 mA
D/A converter
operating
current
IDACNote 5 Per 1 channel 1.0 2.5 mA
LVI operating
current
ILVINote 6 9 18
μ
A
Notes 1. Current flowing only to the real-time counter (excluding the operating current of the XT1 oscillator). The
current value of the 78K0R/KG3 is the TYP. value, the sum of the TYP. values of either IDD1 or IDD2, and IRTC,
when the real-time counter operates in operation mode or HALT mode. The IDD1 and IDD2 MAX. values also
include the real-time counter operating current.
2. When internal high-speed oscillator and high-speed system clock are stopped.
3. Current flowing only to the watchdog timer (including the operating current of the 240 kHz internal oscillator).
The current value of the 78K0R/KG3 is the sum of IDD1, I DD2 or I DD3 and IWDT when fCLK = fSUB/2 or when the
watchdog timer operates in STOP mode.
4. Current flowing only to the A/D converter (AVREF0 pin). The current value of the 78K0R/KG3 is the sum of
IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
5. Current flowing only to the D/A converter (AVREF1 pin). The current value of the 78K0R/KG3 is the sum of
IDD1 or IDD2 and IDAC when the D/A converter operates in an operation mode or the HALT mode.
6. Current flowing only to the LVI circuit. The current value of the 78K0R/KG3 is the sum of IDD1, IDD2 or IDD3
and ILVI when the LVI circuit operates in the operation mode, HALT or STOP mode.
Remarks 1. fIL: Internal low-speed oscillation clock frequency
f
SUB: Subsystem clock frequency (XT1 clock oscillation frequency)
f
CLK: CPU/peripheral hardware clock frequency
2. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 789
Standard Products
AC Characteristics
(1) Basic operation (1/6)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 0.05 8
μ
s
Normal
current mode 1.8 V ≤ VDD < 2.7 V 0.2 8
μ
s
Main system clock
(fMAIN) operation
Low consumption current mode 0.2 8
μ
s
Subsystem clock (fSUB) operation 57.2 61 62.5
μ
s
Instruction cycle
(minimum instruction
execution time)
TCY
In the self
programming mode
Normal
current mode
2.7 V ≤ VDD ≤ 5.5 V 0.05 0.5
μ
s
Normal current mode 2.0 20.0 MHz 2.7 V ≤ VDD ≤ 5.5 V
Low consumption current mode 2.0 5.0 MHz
External main system
clock frequency
fEX
1.8 V ≤ VDD < 2.7 V 2.0 5.0 MHz
Normal current mode 24 ns 2.7 V ≤ VDD ≤ 5.5 V
Low consumption current mode 96 ns
External main system
clock input high-level
width, low-level width
tEXH, tEXL
1.8 V ≤ VDD < 2.7 V 96 ns
TI00 to TI07 input
high-level width, low-
level width
tTIH,
tTIL
1/fMCK + 10 ns
2.7 V ≤ VDD ≤ 5.5 V 10 MHz
TO00 to TO07 output
frequency
fTO
1.8 V ≤ VDD < 2.7 V 5 MHz
2.7 V ≤ VDD ≤ 5.5 V 10 MHz
PCLBUZ0, PCLBUZ1
output frequency
fPCL
1.8 V ≤ VDD < 2.7 V 5 MHz
Interrupt input high-
level width, low-level
width
tINTH,
tINTL
1
μ
s
Key interrupt input
low-level width
tKR 250 ns
RESET low-level
width
tRSL 10
μ
s
Remarks 1. f
MCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKS0n bit of the TMR0n register. n: Channel number (n = 0 to 7))
2. For details on the normal current mode and low consumption current mode according to the regulator
output voltage, refer to CHAPTER 23 REGULATOR.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
790
Standard Products
(1) Basic operation (2/6)
Minimum instruction execution time during main system clock operation (FSEL = 0, RMC = 00H)
8.0
1.0
0.2
0.1
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
2.7
0.01
1.8
Guaranteed range of main system
clock operation (FSEL = 0, RMC = 00H)
2.1
The range enclosed in dotted lines
applies when the internal high-speed
oscillator is selected.
Supply voltage VDD [V]
Cycle time TCY [ s]
μ
Remark FSEL: Bit 0 of the operation speed mode control register (OSMC)
RMC: Regulator mode control register
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 791
Standard Products
(1) Basic operation (3/6)
Minimum instruction execution time during main system clock operation (FSEL = 1, RMC = 00H)
8.0
1.0
0.2
0.1
0.05
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
2.7
0.01
1.8
Guaranteed range of main system
clock operation (FSEL = 1, RMC = 00H)
The range enclosed in dotted lines
applies when the internal high-speed
oscillator is selected.
Supply voltage VDD [V]
Cycle time TCY [ s]
μ
Remark FSEL: Bit 0 of the operation speed mode control register (OSMC)
RMC: Regulator mode control register
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
792
Standard Products
(1) Basic operation (4/6)
Minimum instruction execution time during main system clock operation (FSEL = 0, RMC = 5AH)
8.0
1.0
0.2
0.1
0.05
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
0.01
1.8
Supply voltage V
DD
[V]
Cycle time T
CY
[ s]
μ
Guaranteed range of main system
clock operation (FSEL = 0, RMC = 5AH)
The range enclosed in dotted lines
applies when the internal high-speed
oscillator is selected.
Remarks 1. FSEL: Bit 0 of the operation speed mode control register (OSMC)
RMC: Regulator mode control register
2. The entire voltage range is 5 MHz (MAX.) when RMC is set to 5AH.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 793
Standard Products
(1) Basic operation (5/6)
Minimum instruction execution time during self programming mode (RMC = 00H)
8.0
1.0
0.5
0.1
0.05
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
0.01
2.7
Cycle time T
CY
[ s]
μ
Supply voltage V
DD
[V]
Guaranteed range of self programming mode
(RMC = 00H)
The range enclosed in dotted lines applies when
the internal high-speed oscillator is selected.
Remarks 1. RMC: Regulator mode control register
2. The self programming function cannot be used when RMC is set to 5AH or the CPU operates with the
subsystem clock.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
794
Standard Products
(1) Basic operation (6/6)
AC Timing Test Points (Excluding external bus interface)
V
IH
V
IL
Test points V
IH
V
IL
External Main System Clock Timing
EXCLK 0.8V
DD
(MIN.)
0.2V
DD
(MAX.)
1/f
EX
t
EXL
t
EXH
TI Timing
TI00 to TI07
t
TIL
t
TIH
Interrupt Request Input Timing
INTP0 to INTP11
t
INTL
t
INTH
Key Interrupt Input Timing
KR0 to KR7
t
KR
RESET Input Timing
RESET
t
RSL
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 795
Standard Products
(2) External bus interface (1/3)
(a) Read/write cycle (CLKOUT synchronous)
• Conventional-specification products (
μ
PD78F116x)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
CLKOUT cycle tCYK <1> 2.7 V ≤ VDD ≤ 5.5 V 100 ns
CLKOUT high-level width tWKH <2> 2.7 V ≤ VDD ≤ 5.5 V 0.4tCYK − 30 0.6tCYK ns
CLKOUT low-level width tWKL <3> 2.7 V ≤ VDD ≤ 5.5 V 0.4tCYK − 30 0.6tCYK ns
ASTB high-level width tWASH1 <4> 2.7 V ≤ VDD ≤ 5.5 V 0.8tCYK − 40 1.2tCYK ns
RD low-level width tWRDL1 <5> 2.7 V ≤ VDD ≤ 5.5 V (0.8 + m + w) tCYK − 40 (1.2 + m + w) tCYK ns
WR0, WR1 low-level width tWWRL1 <6> 2.7 V ≤ VDD ≤ 5.5 V (0.8 + w) tCYK − 40 (1.2 + w) tCYK ns
Delay time from CLKOUT↑ to ASTB tDKAS1 <7> 2.7 V ≤ VDD ≤ 5.5 V 2 50 ns
Delay time from CLKOUT↑ to RD tDKRD1 <8> 2.7 V ≤ VDD ≤ 5.5 V 2 50 ns
Delay time from CLKOUT↑ to
WR0, WR1
tDKWR1 <9> 2.7 V ≤ VDD ≤ 5.5 V 2 50 ns
Delay time from CLKOUT↑ to address tDKA1 <10> 2.7 V ≤ VDD ≤ 5.5 V 2 55 ns
Data output delay time from CLKOUT↑ tDKOD1 <11> 2.7 V ≤ VDD ≤ 5.5 V 2 55 ns
Data output hold time from CLKOUT↑ tHKOD1 <12> 2.7 V ≤ VDD ≤ 5.5 V 2 ns
Data input setup time to CLKOUT↑ tSKDI1 <13> 2.7 V ≤ VDD ≤ 5.5 V 40 ns
Data input hold time from CLKOUT↑ tHKDI1 <14> 2.7 V ≤ VDD ≤ 5.5 V 0 ns
WAIT setup time to CLKOUT↑ tSKWT1 <15> 2.7 V ≤ VDD ≤ 5.5 V 45 ns
WAIT hold time from CLKOUT↑ tHKWT1 <16> 2.7 V ≤ VDD ≤ 5.5 V 0 ns
Delay time from address output stop to
RD↓
tDAR1 <17> 2.7 V ≤ VDD ≤ 5.5 V 0 ns
Remarks 1. C
L: The pin load capacitance is 15 pF.
2. Test points: VOH = 0.8VDD, VOL = 0.2VDD
3. m = 0: Multiplexed bus mode
m = 1: Separate bus mode
w: Number of waits with WAIT
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
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Standard Products
• Expanded-specification products (
μ
PD78F116xA)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 100 ns CLKOUT cycle tCYK <1>
1.8 V ≤ VDD < 2.7 V 200 ns
2.7 V ≤ VDD ≤ 5.5 V 0.4tCYK − 30 0.6tCYK ns CLKOUT high-level width tWKH <2>
1.8 V ≤ VDD < 2.7 V 0.4tCYK − 50 0.6tCYK ns
2.7 V ≤ VDD ≤ 5.5 V 0.4tCYK − 30 0.6tCYK ns CLKOUT low-level width tWKL <3>
1.8 V ≤ VDD < 2.7 V 0.4tCYK − 50 0.6tCYK ns
2.7 V ≤ VDD ≤ 5.5 V 0.8tCYK − 40 1.2tCYK ns ASTB high-level width tWASH1 <4>
1.8 V ≤ VDD < 2.7 V 0.8tCYK − 60 1.2tCYK ns
2.7 V ≤ VDD ≤ 5.5 V (0.8 + m + w) tCYK − 40 (1.2 + m + w) tCYK ns RD low-level width tWRDL1 <5>
1.8 V ≤ VDD < 2.7 V (0.8 + m + w) tCYK − 60 (1.2 + m + w) tCYK ns
2.7 V ≤ VDD ≤ 5.5 V (0.8 + w) tCYK − 40 (1.2 + w) tCYK ns WR0, WR1 low-level width tWWRL1 <6>
1.8 V ≤ VDD < 2.7 V (0.8 + w) tCYK − 60 (1.2 + w) tCYK ns
2.7 V ≤ VDD ≤ 5.5 V 2 50 ns
Delay time from CLKOUT↑ to
ASTB
tDKAS1 <7>
1.8 V ≤ VDD < 2.7 V 2 80 ns
2.7 V ≤ VDD ≤ 5.5 V 2 50 ns
Delay time from CLKOUT↑ to
RD
tDKRD1 <8>
1.8 V ≤ VDD < 2.7 V 2 80 ns
2.7 V ≤ VDD ≤ 5.5 V 2 50 ns
Delay time from CLKOUT↑ to
WR0, WR1
tDKWR1 <9>
1.8 V ≤ VDD < 2.7 V 2 80 ns
2.7 V ≤ VDD ≤ 5.5 V 2 55 ns
Delay time from CLKOUT↑ to
address
tDKA1 <10>
1.8 V ≤ VDD < 2.7 V 2 90 ns
2.7 V ≤ VDD ≤ 5.5 V 2 55 ns
Data output delay time from
CLKOUT↑
tDKOD1 <11>
1.8 V ≤ VDD < 2.7 V 2 90 ns
2.7 V ≤ VDD ≤ 5.5 V 2 ns
Data output hold time from
CLKOUT↑
tHKOD1 <12>
1.8 V ≤ VDD < 2.7 V 2 ns
2.7 V ≤ VDD ≤ 5.5 V 40 ns
Data input setup time to
CLKOUT↑
tSKDI1 <13>
1.8 V ≤ VDD < 2.7 V 85 ns
2.7 V ≤ VDD ≤ 5.5 V 0 ns
Data input hold time from
CLKOUT↑
tHKDI1 <14>
1.8 V ≤ VDD < 2.7 V 0 ns
2.7 V ≤ VDD ≤ 5.5 V 45 ns WAIT setup time to CLKOUT↑ tSKWT1 <15>
1.8 V ≤ VDD < 2.7 V 85 ns
2.7 V ≤ VDD ≤ 5.5 V 0 ns
WAIT hold time from
CLKOUT↑
tHKWT1 <16>
1.8 V ≤ VDD < 2.7 V 0 ns
2.7 V ≤ VDD ≤ 5.5 V 0 ns
Delay time from address
output stop to RD↓
tDAR1 <17>
1.8 V ≤ VDD < 2.7 V 0 ns
Remarks 1. C
L: The pin load capacitance is 15 pF.
2. Test points: VOH = 0.8VDD, VOL = 0.2VDD
3. m = 0: Multiplexed bus mode
m = 1: Separate bus mode
w: Number of waits with WAIT
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 797
Standard Products
(2) External bus interface (2/3)
Read/write cycle (CLKOUT synchronous): In separate bus mode
WR0, WR1
D7 to D0
D15 to D0
A19 to A0
CLKOUT
WAIT
RD
<5>
<8> <8>
<9> <9>
<10>
<11>
<13> <14>
<6>
<1>
<2> <3>
<12>
<10>
<16>
<16><15>
<15>
<16>
<16><15>
<15>
Data Data
Address Address
Read/write cycle (CLKOUT synchronous): In multiplexed bus mode
WR0, WR1
ASTB
AD7 to AD0
AD15 to AD0
A19 to A8
A19 to A16
CLKOUT
WAIT
RD
<4>
<4>
<7>
<7><7> <7>
<5>
<8>
<17>
<8>
<9> <9>
<12>
<12>
<11>
<10> <10>
<11>
<11>
<13> <14>
<6>
<1>
<2> <3>
<15>
<16>
<16>
<15>
<15>
<16>
<16>
<15>
Address Data Data
Address
Address Address
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
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Standard Products
(2) External bus interface (3/3)
(b) Read/write cycle (CLKOUT asynchronous)
• Conventional-specification products (
μ
PD78F116x)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
CLKOUT cycle tCYK2 <18> 2.7 V ≤ VDD ≤ 5.5 V 100 ns
RD low-level width tWRDL2 <19> 2.7 V ≤ VDD ≤ 5.5 V 1.8tCYK2 − 40 2.2tCYK2 ns
WR0, WR1 low-level width tWWRL2 <20> 2.7 V ≤ VDD ≤ 5.5 V 0.8tCYK2 − 40 1.2tCYK2 ns
Data input setup time to RD↑ tSRDDI2 <21> 2.7 V ≤ VDD ≤ 5.5 V 90 ns
Data input hold time from RD↑ tHRDDI2 <22> 2.7 V ≤ VDD ≤ 5.5 V 0 ns
Data output setup time to WR0, WR1↓ tSWROD2 <23> 2.7 V ≤ VDD ≤ 5.5 V tCYK2 − 5 ns
Data output hold time from WR0, WR1↑ tHKOD2 <24> 2.7 V ≤ VDD ≤ 5.5 V 2 ns
Delay time from RD↓ to address tDRDA2 <25> 2.7 V ≤ VDD ≤ 5.5 V 5 ns
Address setup time to WR0, WR1↓ tSWRA2 <26> 2.7 V ≤ VDD ≤ 5.5 V tCYK2 − 5 ns
• Expanded-specification products (
μ
PD78F116xA)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 100 ns CLKOUT cycle tCYK2 <18>
1.8 V ≤ VDD < 2.7 V 200 ns
2.7 V ≤ VDD ≤ 5.5 V 1.8tCYK2 − 40 2.2tCYK2 ns RD low-level width tWRDL2 <19>
1.8 V ≤ VDD < 2.7 V 1.8tCYK2 − 60 2.2tCYK2 ns
2.7 V ≤ VDD ≤ 5.5 V 0.8tCYK2 − 40 1.2tCYK2 ns WR0, WR1 low-level width tWWRL2 <20>
1.8 V ≤ VDD < 2.7 V 0.8tCYK2 − 60 1.2tCYK2 ns
2.7 V ≤ VDD ≤ 5.5 V 90 ns Data input setup time to RD↑ tSRDDI2 <21>
1.8 V ≤ VDD < 2.7 V 170 ns
2.7 V ≤ VDD ≤ 5.5 V 0 ns Data input hold time from RD↑ tHRDDI2 <22>
1.8 V ≤ VDD < 2.7 V 0 ns
2.7 V ≤ VDD ≤ 5.5 V tCYK2 − 5 ns Data output setup time to WR0, WR1↓ tSWROD2 <23>
1.8 V ≤ VDD < 2.7 V tCYK2 − 15 ns
2.7 V ≤ VDD ≤ 5.5 V 2 ns Data output hold time from WR0, WR1↑ tHKOD2 <24>
1.8 V ≤ VDD < 2.7 V 2 ns
2.7 V ≤ VDD ≤ 5.5 V 5 ns Delay time from RD↓ to address tDRDA2 <25>
1.8 V ≤ VDD < 2.7 V 15 ns
2.7 V ≤ VDD ≤ 5.5 V tCYK2 − 5 ns Address setup time to WR0, WR1↓ tSWRA2 <26>
1.8 V ≤ VDD < 2.7 V tCYK2 − 15 ns
Cautions 1. CLKOUT output is not used during CLKOUT asynchronous operation, but a CPU wait occurs
according to the setting of bits 4 and 5 (EW0, EW1) of the memory expansion mode control
register (MEM). When fCLK is sufficiently high, insert a wait by setting the EW0 and EW1 bits.
2. Do not use the WAIT pin during CLKOUT asynchronous operation.
Use the separate bus mode during CLKOUT asynchronous operation.
Remarks 1. fCLK: CPU/peripheral hardware clock frequency
2. CL: The pin load capacitance is 15 pF.
3. Test points: VOH = 0.8VDD, VOL = 0.2VDD
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 799
Standard Products
Read/write cycle (CLKOUT asynchronous): In separate bus mode
WR0, WR1
D7 to D0
D15 to D0
A19 to A0
CLKOUT
RD
<19>
<24>
<25>
<21> <22>
<20>
<23>
Data Data
Address Address
<26>
<18>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
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Standard Products
(3) Serial interface: Serial array unit (1/18)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(a) During communication at same potential (UART mode) (dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fMCK/6 bps Transfer rate
fCLK = 20 MHz, fMCK = fCLK 3.3 Mbps
UART mode connection diagram (during communication at same potential)
78K0R/KG3 User's device
TxDq
RxDq
Rx
Tx
UART mode bit width (during communication at same potential) (reference)
Baud rate error tolerance
High-/Low-bit width
1/Transfer rate
TxDq
RxDq
Caution Select the normal input buffer for RxDi and the normal output mode for TxDi by using the PIMg and
POMg registers.
Remarks 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 14),
i: UART number for which communication at different potential can be selected (i = 1, 2)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3))
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 801
Standard Products
(3) Serial interface: Serial array unit (2/18)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(b) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V 200 Note 1 ns
2.7 V ≤ VDD < 4.0 V 300 Note 1 ns
SCKp cycle time tKCY1
1.8 V ≤ VDD < 2.7 V 600 Note 1 ns
4.0 V ≤ VDD ≤ 5.5 V tKCY1/2 − 20 ns
2.7 V ≤ VDD < 4.0 V tKCY1/2 − 35 ns
SCKp high-/low-level width tKH1,
tKL1
1.8 V ≤ VDD < 2.7 V tKCY1/2 − 80 ns
4.0 V ≤ VDD ≤ 5.5 V 70 ns
2.7 V ≤ VDD < 4.0 V 100 ns
SIp setup time (to SCKp↑)Note 2 tSIK1
1.8 V ≤ VDD < 2.7 V 190 ns
SIp hold time (from SCKp↑)Note 3 tKSI1 30 ns
Delay time from SCKp↓ to
SOp outputNote 4
tKSO1 C = 30 pFNote 5 40 ns
Notes 1. The value must also be 4/fCLK or more.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for SIj and the normal output mode for SOj and SCKj by using the
PIMg and POMg registers.
Remarks 1. p: CSI number (p = 00, 01, 10, 20), g: PIM and POM number (g = 0, 4, 14),
j: CSI number for which communication at different potential can be selected (j = 01, 10, 20)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
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Standard Products
(3) Serial interface: Serial array unit (3/18)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(c) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V 6/fMCK ns
16 MHz < fMCK 8/fMCK ns 2.7 V ≤ VDD < 4.0 V
fMCK ≤ 16 MHz 6/fMCK ns
16 MHz < fMCK 8/fMCK ns
SCKp cycle time tKCY2
1.8 V ≤ VDD < 2.7 V
fMCK ≤ 16 MHz 6/fMCK ns
SCKp high-/low-level width tKH2,
tKL2
f
KCY2/2 ns
SIp setup time
(to SCKp↑)Note 1
tSIK2 80 ns
SIp hold time
(from SCKp↑)Note 2
tKSI2 1/fMCK + 50 ns
4.0 V ≤ VDD ≤ 5.5 V 2/fMCK + 45 ns
2.7 V ≤ VDD < 4.0 V 2/fMCK + 57 ns
Delay time from SCKp↓ to
SOp outputNote 3
tKSO2 C = 30 pFNote 4
1.8 V ≤ VDD < 2.7 V 2/fMCK + 125 ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output line.
Caution Select the normal input buffer for SIj and SCKj and the normal output mode for SOj by using the
PIMg and POMg registers.
Remarks 1. p: CSI number (p = 00, 01, 10, 20), g: PIM and POM number (g = 0, 4, 14),
j: CSI number for which communication at different potential can be selected (j = 01, 10, 20)
2. f
MCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 2))
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 803
Standard Products
(3) Serial interface: Serial array unit (4/18)
CSI mode connection diagram (during communication at same potential)
78K0R/KG3 User's device
SCKp
SOp
SCK
SI
SIp SO
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1)
SIp Input data
Output data
SOp
t
KCY1, 2
t
KL1, 2
t
KH1, 2
t
SIK1, 2
t
KSI1, 2
t
KSO1, 2
SCKp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0)
SIp Input data
Output data
SOp
t
KCY1, 2
t
KH1, 2
t
KL1, 2
t
SIK1, 2
t
KSI1, 2
t
KSO1, 2
SCKp
Remarks 1. p: CSI number (p = 00, 01, 10, 20)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
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Standard Products
(3) Serial interface: Serial array unit (5/18)
(d) During communication at same potential (simplified I2C mode)
• Conventional-specification products (
μ
PD78F116x)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. MAX. Unit
SCLr clock frequency fSCL 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
400 Note kHz
Hold time when SCLr = “L” tLOW 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
995 ns
Hold time when SCLr = “H” tHIGH 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
995 ns
Data setup time (reception) tSU:DAT 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1/fMCK + 120 ns
Data hold time (transmission) tHD:DAT 2.7 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
0 160 ns
Note The value must also be fMCK/4 or less.
• Expanded-specification products (
μ
PD78F116xA)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
400 Note kHz SCLr clock frequency fSCL
1.8 V ≤ VDD < 2.7 V
Cb = 100 pF, Rb = 5 kΩ
300 Note kHz
2.7 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
995 ns
Hold time when SCLr = “L” tLOW
1.8 V ≤ VDD < 2.7 V
Cb = 100 pF, Rb = 5 kΩ
1500 ns
2.7 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
995 ns
Hold time when SCLr = “H” tHIGH
1.8 V ≤ VDD < 2.7 V
Cb = 100 pF, Rb = 5 kΩ
1500 ns
2.7 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1/fMCK + 120 ns Data setup time (reception) tSU:DAT
1.8 V ≤ VDD < 2.7 V
Cb = 100 pF, Rb = 5 kΩ
1/fMCK + 230 ns
2.7 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
0 160 ns
Data hold time (transmission) tHD:DAT
1.8 V ≤ VDD < 2.7 V
Cb = 100 pF, Rb = 5 kΩ
0 210 ns
Note The value must also be fMCK/4 or less.
(Remarks are given on the next page.)
<R>
<R>
<R>
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 805
Standard Products
(3) Serial interface: Serial array unit (6/18)
Simplified I2C mode connection diagram (during communication at same potential)
78K0R/KG3 User's device
SDAr
SCLr
SDA
SCL
V
DD
R
b
Simplified I2C mode serial transfer timing (during communication at same potential)
SDAr
t
LOW
t
HIGH
t
HD:DAT
SCLr
t
SU:DAT
Caution Select the normal input buffer and the N-ch open-drain output (VDD tolerance) mode for SDAr and
the normal output mode for SCLr by using the PIMg and POMg registers.
Remarks 1. R
b[Ω]: Communication line (SDAr) pull-up resistance,
Cb[F]: Communication line (SCLr, SDAr) load capacitance
2. r: IIC number (r = 10, 20), g: PIM and POM number (g = 0, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0, 2), mn = 02, 10)
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
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Standard Products
(3) Serial interface: Serial array unit (7/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(e) During communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator
output) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fMCK/6 bps
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V fCLK = 20 MHz, fMCK = fCLK 3.3 Mbps
fMCK/6 bps
Transfer rate Reception
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V fCLK = 20 MHz, fMCK = fCLK 3.3 Mbps
Caution Select the TTL input buffer for RxDq and the N-ch open-drain output (VDD tolerance) mode for TxDq
by using the PIMg and POMg registers.
Remarks 1. q: UART number (q = 1, 2), g: PIM and POM number (g = 0, 14)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3))
3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in UART mode.
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
4. UART0 and UART3 cannot communicate at different potential. Use UART1 and UART2 for
communication at different potential.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 807
Standard Products
(3) Serial interface: Serial array unit (8/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(e) During communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator
output) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Note 1
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V fCLK = 16.8 MHz, fMCK = fCLK,
Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V
2.8Note 2 Mbps
Note 3
Transfer rate Transmission
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V fCLK = 19.2 MHz, fMCK = fCLK,
Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V
1.2Note 4 Mbps
Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ VDD = EVDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
1
Maximum transfer rate = [bps]
{−Cb × Rb × ln (1 − 2.2
Vb)} × 3
1
Transfer rate × 2 − {−Cb × Rb × ln (1 − 2.2
Vb)}
Baud rate error (theoretical value) =
× 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD = EVDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 − 2.0
Vb)} × 3
[bps]
1
Transfer rate × 2 − {−Cb × Rb × ln (1 − 2.2
Vb)}
Baud rate error (theoretical value) =
× 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for RxDq and the N-ch open-drain output (VDD tolerance) mode for TxDq
by using the PIMg and POMg registers.
(Remarks are given on the next page.)
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
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Standard Products
(3) Serial interface: Serial array unit (9/18)
Remarks 1. Rb[Ω]: Communication line (TxDq) pull-up resistance,
C
b[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
2. q: UART number (q = 1, 2), g: PIM and POM number (g = 0, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3))
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in UART mode.
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
5. UART0 and UART3 cannot communicate at different potential. Use UART1 and UART2 for
communication at different potential.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 809
Standard Products
(3) Serial interface: Serial array unit (10/18)
UART mode connection diagram (during communication at different potential)
78K0R/KG3 User's device
TxDq
RxDq
Rx
Tx
V
b
R
b
UART mode bit width (during communication at different potential) (reference)
TxDq
RxDq
Baud rate error tolerance
Baud rate error tolerance
Low-bit width
High-/Low-bit width
High-bit width
1/Transfer rate
1/Transfer rate
Caution Select the TTL input buffer for RxDq and the N-ch open-drain output (VDD tolerance) mode for TxDq
by using the PIMg and POMg registers.
Remarks 1. R
b[Ω]: Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage
2. q: UART number (q = 1, 2), g: PIM and POM number (g = 0, 14)
3. UART0 and UART3 cannot communicate at different potential. Use UART1 and UART2 for
communication at different potential.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
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Standard Products
(3) Serial interface: Serial array unit (11/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(f) During communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal
clock output) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
400 Note 1 ns SCKp cycle time tKCY1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
800 Note 1 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
tKCY1/2 − 75 ns SCKp high-level width tKH1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 − 170 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
tKCY1/2 − 20 ns SCKp low-level width tKL1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 − 35 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
150 ns
SIp setup time
(to SCKp↑) Note 2
tSIK1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
275 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
30 ns
SIp hold time
(from SCKp↑) Note 2
tKSI1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
30 ns
4.0 V ≤ VDD < 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
120 ns
Delay time from SCKp↓ to
SOp output Note 2
tKSO1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
215 ns
Notes 1. The value must also be 4/fCLK or more.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Caution Select the TTL input buffer for SIp and the N-ch open-drain output (VDD tolerance) mode for SOp and
SCKp by using the PIMg and POMg registers.
Remarks 1. p: CSI number (p = 01, 10, 20), g: PIM and POM number (g = 0, 4, 14)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
3. R
b[Ω]: Communication line (SCKp, SOp) pull-up resistance,
C
b[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
5. CSI00 cannot communicate at different potential. Use CSI01, CSI10, and CSI20 for communication at
different potential.
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 811
Standard Products
(3) Serial interface: Serial array unit (12/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(f) During communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal
clock output) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
70 ns
SIp setup time
(to SCKp↓)Note
tSIK1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
100 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
30 ns
SIp hold time
(from SCKp↓)Note
tKSI1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
30 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
40 ns
Delay time from SCKp↑ to
SOp outputNote
tKSO1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
40 ns
Note When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
CSI mode connection diagram (during communication at different potential)
V
b
R
b
78K0R/KG3 User's device
<Master>
SCKp
SOp
SCK
SI
SIp SO
V
b
R
b
Caution Select the TTL input buffer for SIp and the N-ch open-drain output (VDD tolerance) mode for SOp and
SCKp by using the PIMg and POMg registers.
Remarks 1. p: CSI number (p = 01, 10, 20), g: PIM and POM number (g = 0, 4, 14)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
3. R
b[Ω]: Communication line (SCKp, SOp) pull-up resistance,
C
b[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
5. CSI00 cannot communicate at different potential. Use CSI01, CSI10, and CSI20 for communication at
different potential.
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
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Standard Products
(3) Serial interface: Serial array unit (13/18)
CSI mode serial transfer timing (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1)
SIp Input data
Output dataSOp
tKCY1
tKL1 tKH1
tSIK1 tKSI1
tKSO1
SCKp
CSI mode serial transfer timing (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0)
SIp Input data
Output data
SOp
tKCY1
tKL1
tKH1
tSIK1 tKSI1
tKSO1
SCKp
Caution Select the TTL input buffer for SIp and the N-ch open-drain output (VDD tolerance) mode for SOp and
SCKp by using the PIMg and POMg registers.
Remarks 1. p: CSI number (p = 01, 10, 20), g: PIM and POM number (g = 0, 4, 14)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
3. CSI00 cannot communicate at different potential. Use CSI01, CSI10, and CSI20 for communication at
different potential.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 813
Standard Products
(3) Serial interface: Serial array unit (14/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(g) During communication at different potential (2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external
clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
13.6 MHz < fMCK 10/fMCK ns
6.8 MHz < fMCK ≤ 13.6 MHz 8/fMCK ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
fMCK ≤ 6.8 MHz 6/fMCK ns
18.5 MHz < fMCK 16/fMCK ns
14.8 MHz < fMCK ≤ 18.5 MHz 14/fMCK ns
11.1 MHz < fMCK ≤ 14.8 MHz 12/fMCK ns
7.4 MHz < fMCK ≤ 11.1 MHz 10/fMCK ns
3.7 MHz < fMCK ≤ 7.4 MHz 8/fMCK ns
SCKp cycle time tKCY2
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
fMCK ≤ 3.7 MHz 6/fMCK ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V fKCY2/2 − 20 ns
SCKp high-/low-level
width
tKH2,
tKL2 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V fKCY2/2 − 35 ns
SIp setup time
(to SCKp↑)Note 1
tSIK2 90 ns
SIp hold time
(from SCKp↑)Note 2
tKSI2 1/fMCK + 50 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2/fMCK +
120
ns
Delay time from
SCKp↓ to SOp
outputNote 3
tKSO2
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2/fMCK +
230
ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
CSI mode connection diagram (during communication at different potential)
78K0R/KG3 User's device
<Slave>
SCKp
SOp
SCK
SI
SIp SO
Vb
Rb
(Caution and Remarks are given on the next page.)
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
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Standard Products
(3) Serial interface: Serial array unit (15/18)
Caution Select the TTL input buffer for SIp and SCKp and the N-ch open-drain output (VDD tolerance) mode
for SOp by using the PIMg and POMg registers.
Remarks 1. p: CSI number (p = 01, 10, 20), g: PIM and POM number (g = 0, 4, 14)
2. R
b[Ω]: Communication line (SOp) pull-up resistance,
C
b[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 2))
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
5. CSI00 cannot communicate at different potential. Use CSI01, CSI10, and CSI20 for communication at
different potential.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 815
Standard Products
(3) Serial interface: Serial array unit (16/18)
CSI mode serial transfer timing (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1)
SIp Input data
Output data
SOp
t
KCY2
t
KL2
t
KH2
t
SIK2
t
KSI2
t
KSO2
SCKp
CSI mode serial transfer timing (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0)
SIp Input data
Output data
SOp
t
KCY2
t
KL2
t
KH2
t
SIK2
t
KSI2
t
KSO2
SCKp
Caution Select the TTL input buffer for SIp and SCKp and the N-ch open-drain output (VDD tolerance) mode
for SOp by using the PIMg and POMg registers.
Remarks 1. p: CSI number (p = 01, 10, 20), g: PIM and POM number (g = 0, 4, 14)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
3. CSI00 cannot communicate at different potential. Use CSI01, CSI10, and CSI20 for communication at
different potential.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
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Standard Products
(3) Serial interface: Serial array unit (17/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(h) During communication at different potential (2.5 V, 3 V) (simplified I2C mode)
Parameter Symbol Conditions MIN. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 1.4 kΩ
400 Note kHz SCLr clock frequency fSCL
2.7 V ≤ VDD ≤ 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
400 Note kHz
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 1.4 kΩ
1065 ns Hold time when SCLr = “L” tLOW
2.7 V ≤ VDD ≤ 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1065 ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 1.4 kΩ
445 ns
Hold time when SCLr = “H” tHIGH
2.7 V ≤ VDD ≤ 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
445 ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 1.4 kΩ
1/fMCK + 190 ns Data setup time (reception) tSU:DAT
2.7 V ≤ VDD ≤ 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1/fMCK + 190 ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 1.4 kΩ
0 160 ns Data hold time (transmission) tHD:DAT
2.7 V ≤ VDD ≤ 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
0 160 ns
Note The value must also be fMCK/4 or less.
Caution Select the TTL input buffer and the N-ch open-drain output (VDD tolerance) mode for SDAr and the
N-ch open-drain output (VDD tolerance) mode for SCLr by using the PIMg and POMg registers.
Remarks 1. R
b[Ω]: Communication line (SDAr, SCLr) pull-up resistance,
C
b[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage
2. r: IIC number (r = 10, 20), g: PIM, POM number (g = 0, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0, 2), mn = 02, 10)
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in simplified I2C mode.
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
<R>
<R>
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 817
Standard Products
(3) Serial interface: Serial array unit (18/18)
Simplified I2C mode connection diagram (during communication at different potential)
78K0R/KG3 User's device
SDAr
SCLr
SDA
SCL
Vb
Rb
Vb
Rb
Simplified I2C mode serial transfer timing (during communication at different potential)
SDAr
tLOW tHIGH
tHD:DAT
SCLr
tSU:DAT
1/fSCL
Caution Select the TTL input buffer and the N-ch open-drain output (VDD tolerance) mode for SDAr and the
N-ch open-drain output (VDD tolerance) mode for SCLr by using the PIMg and POMg registers.
Remarks 1. R
b[Ω]: Communication line (SDAr, SCLr) pull-up resistance, Vb[V]: Communication line voltage
2. r: IIC number (r = 10, 20), g: PIM and POM number (g = 0, 14)
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
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Standard Products
(4) Serial interface: IIC0
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(a) IIC0
Standard Mode Fast Mode Parameter Symbol Conditions
MIN. MAX. MIN. MAX.
Unit
6.7 MHz ≤ fCLK 0 100 0 400 kHz
4.0 MHz ≤ fCLK < 6.7 MHz 0 100 0 340 kHz
3.2 MHz ≤ fCLK < 4.0 MHz 0 100 − − kHz
SCL0 clock frequency fSCL
2.0 MHz ≤ fCLK < 3.2 MHz 0 85 − − kHz
Setup time of restart conditionNote 1 tSU:STA 4.7 0.6
μ
s
Hold time tHD:STA 4.0 0.6
μ
s
Hold time when SCL0 = “L” tLOW 4.7 1.3
μ
s
Hold time when SCL0 = “H” tHIGH 4.0 0.6
μ
s
Data setup time (reception) tSU:DAT 250 100 ns
3.45Note 3 0.9Note 4
μ
s CL00 = 1 and CL01 = 1 0
5.50Note 5
0
1.5Note 6
μ
s
0.9Note 7
μ
s
CL00 = 0 and CL01 = 0, or
CL00 = 1 and CL01 = 0
0 3.45 0
0.95Note 8
μ
s
Data hold time (transmission)Note 2 tHD:DAT
CL00 = 0 and CL01 = 1 0 3.45 0 0.9
μ
s
Setup time of stop condition tSU:STO 4.0 0.6
μ
s
Bus-free time tBUF 4.7 1.3
μ
s
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
3. When 3.2 MHz ≤ fCLK ≤ 4.19 MHz.
4. When 6.7 MHz ≤ fCLK ≤ 8.38 MHz.
5. When 2.0 MHz ≤ fCLK < 3.2 MHz. At this time, use the SCL0 clock within 85 kHz.
6. When 4.0 MHz ≤ fCLK < 6.7 MHz. At this time, use the SCL0 clock within 340 kHz.
7. When 8.0 MHz ≤ fCLK ≤ 16.76 MHz.
8. When 7.6 MHz ≤ fCLK < 8.0 MHz.
Remark CL00, CL01, DFC0: Bits 0, 1, and 2 of the IIC clock select register 0 (IICCL0)
IIC0 serial transfer timing
t
LOW
t
BUF
t
HIGH
t
HD:STA
Stop
condition
Start
condition
Restart
condition
Stop
condition
t
SU:DAT
t
SU:STA
t
SU:STO
t
HD:STA
t
HD:DAT
SCL0
SDA0
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 819
Standard Products
(5) Serial interface: On-chip debug (UART)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(a) On-chip debug (UART)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fCLK/212 fCLK/6 bps Transfer rate
Flash memory programming mode 2.66 Mbps
2.7 V ≤ VDD ≤ 5.5 V 10 MHz TOOL1 output frequency fTOOL1
1.8 V ≤ VDD < 2.7 V 2.5 MHz
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
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Standard Products
A/D Converter Characteristics (1/2)
(TA = −40 to +85°C, 2.3 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 2.3 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD, VSS = EVSS0 =
EVSS1 = AVSS = 0 V)
(a) Conventional-specification products (
μ
PD78F116x)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 10 bit
4.0 V ≤ AVREF0 ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVREF0 < 4.0 V ±0.6 %FSR
Overall errorNotes 1, 2 AINL
2.3 V ≤ AVREF0 < 2.7 V ±0.7 %FSR
4.0 V ≤ AVREF0 ≤ 5.5 V 6.1 66.6
μ
s
2.7 V ≤ AVREF0 < 4.0 V 12.2 66.6
μ
s
Conversion time tCONV
2.3 V ≤ AVREF0 < 2.7 V 27 66.6
μ
s
4.0 V ≤ AVREF0 ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVREF0 < 4.0 V ±0.6 %FSR
Zero-scale errorNotes 1, 2 EZS
2.3 V ≤ AVREF0 < 2.7 V ±0.6 %FSR
4.0 V ≤ AVREF0 ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVREF0 < 4.0 V ±0.6 %FSR
Full-scale errorNotes 1, 2 EFS
2.3 V ≤ AVREF0 < 2.7 V ±0.6 %FSR
4.0 V ≤ AVREF0 ≤ 5.5 V ±2.5 LSB
2.7 V ≤ AVREF0 < 4.0 V ±4.5 LSB
Integral linearity errorNote 1 ILE
2.3 V ≤ AVREF0 < 2.7 V ±4.5 LSB
4.0 V ≤ AVREF0 ≤ 5.5 V ±1.5 LSB
2.7 V ≤ AVREF0 < 4.0 V ±2.0 LSB
Differential linearity errorNote 1 DLE
2.3 V ≤ AVREF0 < 2.7 V ±2.0 LSB
Analog input voltage VAIN 2.3 V ≤ AVREF0 ≤ 5.5 V AVSS AVREF0 V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 821
Standard Products
A/D Converter Characteristics (2/2)
(TA = −40 to +85°C, 2.3 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 2.3 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD, VSS = EVSS0 =
EVSS1 = AVSS = 0 V)
(b) Expanded-specification products (
μ
PD78F116xA)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 10 bit
4.0 V ≤ AVREF0 ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVREF0 < 4.0 V ±0.5 %FSR
Overall errorNotes 1, 2 AINL
2.3 V ≤ AVREF0 < 2.7 V ±0.7 %FSR
4.0 V ≤ AVREF0 ≤ 5.5 V 6.1 66.6
μ
s
2.7 V ≤ AVREF0 < 4.0 V 12.2 66.6
μ
s
Conversion time tCONV
2.3 V ≤ AVREF0 < 2.7 V 27 66.6
μ
s
4.0 V ≤ AVREF0 ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVREF0 < 4.0 V ±0.5 %FSR
Zero-scale errorNotes 1, 2 EZS
2.3 V ≤ AVREF0 < 2.7 V ±0.5 %FSR
4.0 V ≤ AVREF0 ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVREF0 < 4.0 V ±0.5 %FSR
Full-scale errorNotes 1, 2 EFS
2.3 V ≤ AVREF0 < 2.7 V ±0.5 %FSR
4.0 V ≤ AVREF0 ≤ 5.5 V ±2.5 LSB
2.7 V ≤ AVREF0 < 4.0 V ±3.5 LSB
Integral linearity errorNote 1 ILE
2.3 V ≤ AVREF0 < 2.7 V ±3.5 LSB
4.0 V ≤ AVREF0 ≤ 5.5 V ±1.5 LSB
2.7 V ≤ AVREF0 < 4.0 V ±1.5 LSB
Differential linearity errorNote 1 DLE
2.3 V ≤ AVREF0 < 2.7 V ±1.5 LSB
Analog input voltage VAIN 2.3 V ≤ AVREF0 ≤ 5.5 V AVSS AVREF0 V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
822
Standard Products
Temperature Sensor (Expanded-Specification Products (
μ
PD78F116xA) Only)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 2.7 V ≤ AVREF0 ≤ VDD, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Augmentation factor per 10°C TC 1 3.5 15 /10°C
KTV-40 TA = −40°C 30 80 130
−
KTV25 TA = +25°C 65 101 140
−
Temperature sensor detection
value
KTV85 TA = +85°C 100 122 150 −
Remark The temperature sensor detection value is obtained by using the following expression.
A/D conversion value with sensor
that depends on temperature
Temperature
sensor detection
value
= A/D conversion value with sensor
that does not depend on temperature
× 256 ≅ TC
10 (
Temperature
during sensor
operation
−Low reference
temperature ) +
Temperature sensor
detection value at a
low reference
temperature
Temperature
Temperature sensor
detection value
KTV
25
KTV
−40
KTV
85
−40
˚C
+25
˚C
+85
˚C
D/A Converter Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD, VSS = EVSS0 =
EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 bit
Rload = 2 MΩ ±1.2 %FSR
Rload = 4 MΩ ±0.8 %FSR
Overall error AINL
Rload = 10 MΩ ±0.6 %FSR
4.0 V ≤ AVREF1 ≤ 5.5 V 3
μ
s
2.7 V ≤ AVREF1 < 4.0 V 3
μ
s
Settling time tSET Cload = 20 pF
1.8 V ≤ AVREF1 < 2.7 V 6
μ
s
D/A output resistance value RO Per D/A converter channel 6.4 kΩ
Remark When the D/A converter is in normal mode, D/A conversion is started after one fCLK clock has elapsed since
the DACSn register was written. The output level is determined when the settling time has elapsed after
the D/A conversion was started.
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 823
Standard Products
POC Circuit Characteristics (TA = −40 to +85°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOC0 1.5 1.59 1.68 V
Power supply voltage rise
inclination
tPTH Change inclination of VDD: 0 V → VPOC0 0.5 V/ms
Minimum pulse width tPW When the voltage drops 200
μ
s
Detection delay time 200
μ
s
POC Circuit Timing
Supply voltage
(V
DD
)
Time
Detection voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
t
PTH
t
PW
Supply Voltage Rise Time (TA = −40 to +85°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Maximum time to rise to
1.8 V (VDD (MIN.))Note
(VDD: 0 V → 1.8 V)
tPUP1 LVI default start function stopped
is set (LVIOFF (option byte) = 1),
when RESET input is not used
3.6 ms
Maximum time to rise to
1.8 V (VDD (MIN.))Note
(releasing RESET input → VDD: 1.8 V)
tPUP2 LVI default start function stopped
is set (LVIOFF (option byte) = 1),
when RESET input is used
1.88 ms
Note Make sure to raise the power supply in a shorter time than this.
Supply Voltage Rise Time Timing
• When RESET pin input is not used • When RESET pin input is used (when external reset is
released by the RESET pin, after POC has been released)
Supply voltage
(V
DD
)
Time
1.8 V
0 V
POC internal
signal
t
PUP1
Supply voltage
(V
DD
)
Time
1.8 V
t
PUP2
0 V
POC internal
signal
RESET pin
Internal reset
signal
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
824
Standard Products
LVI Circuit Characteristics (TA = −40 to +85°C, VPOC ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VLVI0 4.12 4.22 4.32 V
VLVI1 3.97 4.07 4.17 V
VLVI2 3.82 3.92 4.02 V
VLVI3 3.66 3.76 3.86 V
VLVI4 3.51 3.61 3.71 V
VLVI5 3.35 3.45 3.55 V
VLVI6 3.20 3.30 3.40 V
VLVI7 3.05 3.15 3.25 V
VLVI8 2.89 2.99 3.09 V
VLVI9 2.74 2.84 2.94 V
VLVI10 2.58 2.68 2.78 V
VLVI11 2.43 2.53 2.63 V
VLVI12 2.28 2.38 2.48 V
VLVI13 2.12 2.22 2.32 V
VLVI14 1.97 2.07 2.17 V
Supply voltage level
VLVI15 1.81 1.91 2.01 V
External input pinNote 1 VEXLVI EXLVI < VDD, 1.8 V ≤ VDD ≤ 5.5 V 1.11 1.21 1.31 V
Detection
voltage
Power supply voltage
on power application
VPUPLVI When LVI default start function enabled
is set
1.87 2.07 2.27 V
Minimum pulse width tLW 200
μ
s
Detection delay time 200
μ
s
Operation stabilization wait timeNote 2 tLWAIT 10
μ
s
Notes 1. The EXLVI/P120/INTP0 pin is used.
2. Time required from setting bit 7 (LVION) of the low-voltage detection register (LVIM) to 1 to operation
stabilization
Remark V
LVI(n − 1) > VLVIn: n = 1 to 15
LVI Circuit Timing
Supply voltage
(VDD)
Time
Detection voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
tLW
tLWAIT
LVION ← 1
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD 825
Standard Products
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR 1.5Note 5.5 V
Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC
reset is effected, but data is not retained when a POC reset is effected.
V
DD
STOP instruction execution
Standby release signal
(interrupt request)
STOP mode
Data retention mode
V
DDDR
Operation mode
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U17894EJ9V0UD
826
Standard Products
Flash Memory Programming Characteristics
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
(a) Conventional-specification products (
μ
PD78F116x)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD supply current IDD TYP. = 10 MHz, MAX. = 20 MHz 4.5 15 mA
CPU/peripheral hardware
clock frequency
fCLK 2 20 MHz
Used for updating programs
When using flash memory programmer
and NEC Electronics self programming
library
Retained
for 15
years
100 Times
Number of rewrites (number
of deletes per block)
CWRT
Used for updating data
When using NEC Electronics EEPROM
emulation library (usable ROM size: 6
KB of 3 consecutive blocks)
Retained
for 3 years
10,000 Times
Remark When updating data multiple times, use the flash memory as one for updating data.
(b) Expanded-specification products (
μ
PD78F116xA)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD supply current IDD TYP. = 10 MHz, MAX. = 20 MHz 4.5 15 mA
CPU/peripheral hardware
clock frequency
fCLK 2 20 MHz
Used for updating programs
When using flash memory programmer
and NEC Electronics self programming
library
Retained
for 15
years
1000 Times
Number of rewrites (number
of deletes per block)
CWRT
Used for updating data
When using NEC Electronics EEPROM
emulation library (usable ROM size: 6
KB of 3 consecutive blocks)
Retained
for 5 years
10,000 Times
Remark When updating data multiple times, use the flash memory as one for updating data.
<R>
User’s Manual U17894EJ9V0UD 827
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
Target products
μ
PD78F1162A(A), 78F1163A(A), 78F1164A(A), 78F1165A(A), 78F1166A(A), 78F1167A(A),
78F1168A(A)
Caution The 78K0R/KG3 has an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when
this function is used, and product reliability therefore cannot be guaranteed. NEC Electronics is
not liable for problems occurring when the on-chip debug function is used.
Absolute Maximum Ratings (TA = 25°C) (1/2)
Parameter Symbols Conditions Ratings Unit
VDD −0.5 to +6.5 V
EVDD0, EVDD1 EVDD0 = EVDD1 −0.5 to +6.5 V
VSS −0.5 to +0.3 V
EVSS0, EVSS1 EVSS0 = EVSS1 −0.5 to +0.3 V
AVREF0 −0.5 to VDD + 0.3Note 1 V
AVREF1 −0.5 to VDD + 0.3Note 1 V
Supply voltage
AVSS −0.5 to +0.3 V
REGC pin input voltage VIREGC REGC −0.3 to +3.6
and −0.3 to VDD + 0.3Note 2
V
VI1 P00 to P06, P10 to P17, P30, P31, P40 to P47,
P50 to P57, P64 to P67, P70 to P77, P80 to P87,
P120 to P124, P131, P140 to P145, EXCLK,
RESET, FLMD0
−0.3 to EVDD0, EVDD1 + 0.3
and −0.3 to VDD + 0.3Note 1
V
VI2 P60 to P63 (N-ch open-drain) −0.3 to +6.5 V
VI3 P20 to P27, P150 to P157 −0.3 to AVREF0 + 0.3
and −0.3 to VDD + 0.3Note 1
V
Input voltage
VI4 P110, P111 −0.3 to AVREF1 + 0.3
and −0.3 to VDD + 0.3Note 1
V
VO1 P00 to P06, P10 to P17, P30, P31, P40 to P47,
P50 to P57, P60 to P67, P70 to P77, P80 to P87,
P120, P130, P131, P140 to P145
−0.3 to EVDD0, EVDD1 + 0.3Note 1 V
VO2 P20 to P27, P150 to P157 −0.3 to AVREF0 + 0.3 V
Output voltage
VO3 P110, P111 −0.3 to AVREF1 + 0.3 V
Notes 1. Must be 6.5 V or lower.
2. Connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F). This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
828
(A) Grade Products
Absolute Maximum Ratings (TA = 25°C) (2/2)
Parameter Symbols Conditions Ratings Unit
Analog input voltage VAN ANI0 to ANI15 −0.3 to AVREF0 + 0.3Note
and −0.3 to VDD + 0.3Note
V
Analog output voltage VAO ANO0, ANO1 −0.3 to AVREF1 + 0.3 V
Per pin P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P120, P130, P131,
P140 to P145
−10 mA
P00 to P04, P40 to P47, P120,
P130, P131, P140 to P145
−25 mA
IOH1
Total of all pins
−80 mA
P05, P06, P10 to P17, P30, P31,
P50 to P57, P64 to P67,
P70 to P77, P80 to P87
−55 mA
Per pin −0.5 mA
Output current, high
IOH2
Total of all pins
P20 to P27, P110, P111,
P150 to P157 −2 mA
Per pin P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P60 to P67, P70 to P77,
P80 to P87, P120, P130, P131,
P140 to P145
30 mA
P00 to P04, P40 to P47, P120,
P130, P131, P140 to P145
60 mA
IOL1
Total of all pins
200 mA
P05, P06, P10 to P17, P30, P31,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87
140 mA
Per pin 1 mA
Output current, low
IOL2
Total of all pins
P20 to P27, P110, P111,
P150 to P157 5 mA
In normal operation mode
Operating ambient
temperature
TA
In flash memory programming mode
−40 to +85 °C
Storage temperature Tstg −65 to +150 °C
Note Must be 6.5 V or lower.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 829
(A) Grade Products
X1 Oscillator Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Resonator Recommended
Circuit
Parameter Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 2.0 20.0
Ceramic resonator
C1
X2X1
C2
V
SS
X1 clock oscillation
frequency (fX)Note 1.8 V ≤ VDD < 2.7 V 2.0 5.0
MHz
2.7 V ≤ VDD ≤ 5.5 V 2.0 20.0
Crystal resonator
C1
X2X1
C2
VSS
X1 clock oscillation
frequency (fX)Note 1.8 V ≤ VDD < 2.7 V 2.0 5.0
MHz
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the
above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. Since the CPU is started by the internal high-speed oscillation clock after a reset release,
check the X1 clock oscillation stabilization time using the oscillation stabilization time counter
status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC
register and oscillation stabilization time select register (OSTS) after sufficiently evaluating
the oscillation stabilization time with the resonator to be used.
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
830
(A) Grade Products
Internal Oscillator Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Oscillators Parameters Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 7.6 8.0 8.4 MHz
8 MHz internal
oscillator
Internal high-
speed oscillation
clock frequency
(fIH)Note 1
1.8 V ≤ VDD < 2.7 V 5.0 8.0 8.4 MHz
2.7 V ≤ VDD ≤ 5.5 V 216 240 264 kHz Normal current mode
1.8 V ≤ VDD < 2.7 V 192 240 264 kHz
240 kHz internal
oscillator
Internal low-speed
oscillation clock
frequency (fIL)
Low consumption current modeNote 2 192 240 264 kHz
Notes 1. This only indicates the oscillator characteristics of when HIOTRM is set to 10H. Refer to AC
Characteristics for instruction execution time.
2. Regulator output is set to low consumption current mode in the following cases:
• When the RMC register is set to 5AH.
• During system reset.
• In STOP mode (except during OCD mode).
• When both the high-speed system clock (fMX) and the internal high-speed oscillation clock (fIH) are
stopped during CPU operation with the subsystem clock (fXT).
• When both the high-speed system clock (fMX) and the internal high-speed oscillation clock (fIH) are
stopped during the HALT mode when the CPU operation with the subsystem clock (fXT) has been set.
Remark For details on the normal current mode and low consumption current mode according to the regulator
output voltage, refer to CHAPTER 23 REGULATOR.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 831
(A) Grade Products
XT1 Oscillator Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Resonator Recommended
Circuit
Parameter Conditions MIN. TYP. MAX. Unit
Crystal resonator
XT1XT2
C4 C3
Rd
VSS
XT1 clock oscillation
frequency (fXT)Note
32 32.768 35 kHz
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the
above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption,
and is more prone to malfunction due to noise than the X1 oscillator. Particular care is
therefore required with the wiring method when the XT1 clock is used.
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
832
(A) Grade Products
Recommended Oscillator Constants
(1) X1 oscillation: Ceramic resonator (AMPH = 0, RMC = 00H, TA = −40 to +85°C)
Recommended Circuit Constants Oscillation Voltage Range Manufacturer Part Number SMD/
Lead
Frequency
(MHz) C1 (pF) C2 (pF) MIN. (V) MAX. (V)
CSTCC2M00G56-R0 SMD 2.0 Internal (47) Internal (47) 1.8
CSTCR4M00G55-R0 SMD Internal (39) Internal (39) 1.8
CSTLS4M00G56-B0 Lead
4.0
Internal (47) Internal (47) 1.8
CSTCR4M19G55-R0 SMD Internal (39) Internal (39) 1.8
CSTLS4M19G56-B0 Lead
4.194
Internal (47) Internal (47) 1.8
CSTCR4M91G55-R0 SMD Internal (39) Internal (39) 1.8
CSTLS4M91G53-B0 Internal (15) Internal (15) 1.8
CSTLS4M91G56-B0
Lead
4.915
Internal (47) Internal (47) 2.1
CSTCR5M00G53-R0 Internal (15) Internal (15) 1.8
CSTCR5M00G55-R0
SMD
Internal (39) Internal (39) 1.8
CSTLS5M00G53-B0 Internal (15) Internal (15) 1.8
CSTLS5M00G56-B0
Lead
5.0
Internal (47) Internal (47) 2.1
CSTCR6M00G53-R0 Internal (15) Internal (15) 1.8
CSTCR6M00G55-R0
SMD
Internal (39) Internal (39) 1.9
CSTLS6M00G53-B0 Internal (15) Internal (15) 1.8
CSTLS6M00G56-B0
Lead
6.0
Internal (47) Internal (47) 2.2
CSTCE8M00G52-R0 Internal (10) Internal (10) 1.8
CSTCE8M00G55-R0
SMD
Internal (33) Internal (33) 1.9
CSTLS8M00G53-B0 Internal (15) Internal (15) 1.8
CSTLS8M00G56-B0
Lead
8.0
Internal (47) Internal (47) 2.4
CSTCE8M38G52-R0 Internal (10) Internal (10) 1.8
CSTCE8M38G55-R0
SMD
Internal (33) Internal (33) 1.9
CSTLS8M38G53-B0 Internal (15) Internal (15) 1.8
CSTLS8M38G56-B0
Lead
8.388
Internal (47) Internal (47) 2.4
CSTCE10M0G52-R0 Internal (10) Internal (10) 1.8
CSTCE10M0G55-R0
SMD
Internal (33) Internal (33) 2.1
Murata
Manufacturing
Co., Ltd.
CSTLS10M0G53-B0 Lead
10.0
Internal (15) Internal (15) 1.8
5.5
DCRHTC(P)2.00LL 2.0 Internal (30) Internal (30)
DCRHTC(P)4.00LL
Lead
4.0 Internal (30) Internal (30)
DECRHTC4.00 SMD 4.0 Internal (15) Internal (15)
TOKO, Inc.
DCRHYC(P)8.00A Lead 8.0 Internal (22) Internal (22)
1.8 5.5
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer. If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on
the implementation circuit.
When doing so, check the conditions for using the AMPH bit, RMC register, and whether to enter
or exit the STOP mode.
The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use
the 78K0R/KG3 so that the internal operation conditions are within the specifications of the DC
and AC characteristics.
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 833
(A) Grade Products
(2) X1 oscillation: Crystal resonator (AMPH = 0, RMC = 00H, TA = −40 to +85°C)
Recommended Circuit
Constants
Oscillation Voltage Range
Manufacturer Part Number SMD/
Lead
Frequency
(MHz)
C1 (pF) C2 (pF) MIN. (V) MAX. (V)
HC49SFWB04194D0PPTZZ
CX49GFWB04194D0PPTZZ
Lead
CX1255GB04194D0PPTZZ SMD
4.194 10 10 1.8
HC49SFWB05000D0PPTZZ
CX49GFWB05000D0PPTZZ
Lead
CX1255GB05000D0PPTZZ
CX8045GB05000D0PPTZZ
SMD
5.0 10 10 1.8
HC49SFWB08380D0PPTZZ
CX49GFWB08380D0PPTZZ
Lead
CX1255GB08380D0PPTZZ
CX8045GB08380D0PPTZZ
CX5032GB08380D0PPTZZ
SMD
8.38 10 10 1.8
HC49SFWB10000D0PPTZZ
CX49GFWB10000D0PPTZZ
Lead
CX1255GB10000D0PPTZZ
CX8045GB10000D0PPTZZ
CX5032GB10000D0PPTZZ
CX5032SB10000D0PPTZZ
KYOCERA
KINSEKI
Co., Ltd.
CX3225GB10000D0PPTZZ
SMD
10.0 10 10 1.8
5.5
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer. If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on
the implementation circuit.
When doing so, check the conditions for using the AMPH bit, RMC register, and whether to enter
or exit the STOP mode.
The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use
the 78K0R/KG3 so that the internal operation conditions are within the specifications of the DC
and AC characteristics.
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
834
(A) Grade Products
(3) X1 oscillation: Ceramic resonator (AMPH = 1, RMC = 00H, TA = −40 to +85°C)
Recommended Circuit Constants Oscillation Voltage Range Manufacturer Part Number SMD/
Lead
Frequency
(MHz) C1 (pF) C2 (pF) MIN. (V) MAX. (V)
CSTCE12M0G55-R0 SMD 12.0 Internal (33) Internal (33) 1.8
CSTCE16M0V53-R0 SMD Internal (15) Internal (15) 1.8
CSTLS16M0X51-B0 Lead
16.0
Internal (5) Internal (5) 1.8
CSTCE20M0V53-R0 SMD Internal (15) Internal (15) 1.9
CSTCG20M0V53-R0 Small
SMD
Internal (15) Internal (15) 2.0
Murata
Manufacturing
Co., Ltd.
CSTLS20M0X51-B0 Lead
20.0
Internal (5) Internal (5) 1.9
5.5
DCRHYC(P)12.00A Lead 12.0 Internal (22) Internal (22)
DCRHZ(P)16.00A-15 Lead 16.0 Internal (15) Internal (15)
1.8
DCRHZ(P)20.00A-15 Lead Internal (15) Internal (15) 2.0
TOKO, Inc.
DECRHZ20.00 SMD
20.0
Internal (10) Internal (10) 1.8
5.5
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer. If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on
the implementation circuit.
When doing so, check the conditions for using the AMPH bit, RMC register, and whether to enter
or exit the STOP mode.
The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use
the 78K0R/KG3 so that the internal operation conditions are within the specifications of the DC
and AC characteristics.
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 835
(A) Grade Products
(4) X1 oscillation: Crystal resonator (AMPH = 1, RMC = 00H, TA = −40 to +85°C)
Recommended Circuit
Constants
Oscillation Voltage Range
Manufacturer Part Number SMD/
Lead
Frequency
(MHz)
C1 (pF) C2 (pF) MIN. (V) MAX. (V)
HC49SFWB16000D0PPTZZ
CX49GFWB16000D0PPTZZ
Lead
CX1255GB16000D0PPTZZ
CX8045GB16000D0PPTZZ
CX5032GB16000D0PPTZZ
CX5032SB16000D0PPTZZ
CX3225GB16000D0PPTZZ
CX3225SB16000D0PPTZZ
CX2520SB16000D0PPTZZ
SMD
16.0 10 10 1.8
HC49SFWB20000D0PPTZZ
CX49GFWB20000D0PPTZZ
Lead
CX1255GB20000D0PPTZZ
CX8045GB20000D0PPTZZ
CX5032GB20000D0PPTZZ
CX5032SB20000D0PPTZZ
CX3225GB20000D0PPTZZ
CX3225SB20000D0PPTZZ
CX2520SB20000D0PPTZZ
KYOCERA
KINSEKI
Co., Ltd.
CX2016SB20000D0PPTZZ
SMD
20.0 10 10 2.3
5.5
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer. If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on
the implementation circuit.
When doing so, check the conditions for using the AMPH bit, RMC register, and whether to enter
or exit the STOP mode.
The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use
the 78K0R/KG3 so that the internal operation conditions are within the specifications of the DC
and AC characteristics.
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
836
(A) Grade Products
(5) XT1 oscillation: Crystal resonator (TA = −40 to +85°C)
Recommended Circuit Constants Oscillation Voltage RangeManufacturer Part
Number
SMD/
Lead
Frequency
(kHz)
Load Capacitance
CL (pF) C3 (pF) C4 (pF) Rd (kΩ) MIN. (V) MAX. (V)
6.0 5 5 0 SP-T2A SMD
12.5 18 18 0
7.0 7 7 0 SSP-T7 Small
SMD 12.5 18 18 0
6.0 5 5 0
Seiko
Instruments
Inc.
VT-200 Lead
32.768
12.5 18 18 0
1.8 5.5
12 15 0 CM200S SMD 9.0
12 15 100
15 15 0 CM315 SMD 9.0
15 15 100
15 12 0
CITIZEN
FINETECH
MIYOTA CO.,
LTD.
CM519 SMD
32.768
9.0
15 12 100
1.8 5.5
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer. If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on
the implementation circuit.
When doing so, check the conditions for using the RMC register, and whether to enter or exit the
STOP mode.
The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use
the 78K0R/KG3 so that the internal operation conditions are within the specifications of the DC
and AC characteristics.
(6) XT1 oscillation: Crystal resonator (TA = −20 to +70°C)
Recommended Circuit Constants Oscillation Voltage RangeManufacturer Part
Number
SMD/
Lead
Frequency
(kHz)
Load Capacitance
CL (pF) C3 (pF) C4 (pF) Rd (kΩ) MIN. (V) MAX. (V)
22 18 0 12.5
22 18 100
12 15 0
CITIZEN
FINETECH
MIYOTA CO.,
LTD.
CFS-206 Lead 32.768
9.0
12 15 100
1.8 5.5
Caution The oscillator constants shown above are reference values based on evaluation in a specific
environment by the resonator manufacturer. If it is necessary to optimize the oscillator
characteristics in the actual application, apply to the resonator manufacturer for evaluation on
the implementation circuit.
When doing so, check the conditions for using the RMC register, and whether to enter or exit the
STOP mode.
The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use
the 78K0R/KG3 so that the internal operation conditions are within the specifications of the DC
and AC characteristics.
<R>
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 837
(A) Grade Products
DC Characteristics (1/16)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V −3.0 mA
2.7 V ≤ VDD < 4.0 V −1.0 mA
Per pin for P00 to P06, P10 to P17,
P30, P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77, P80 to P87,
P120, P130, P131, P140 to P145 1.8 V ≤ VDD < 2.7 V −1.0 mA
4.0 V ≤ VDD ≤ 5.5 V −12.0 mA
2.7 V ≤ VDD < 4.0 V −7.0 mA
Total of P00 to P04, P40 to P47,
P120, P130, P131, P140 to P145
(When duty = 70%Note 2) 1.8 V ≤ VDD < 2.7 V −5.0 mA
4.0 V ≤ VDD ≤ 5.5 V −18.0 mA
2.7 V ≤ VDD < 4.0 V −15.0 mA
Total of P05, P06, P10 to P17, P30,
P31, P50 to P57, P64 to P67,
P70 to P77, P80 to P87
(When duty = 70%Note 2) 1.8 V ≤ VDD < 2.7 V −10.0 mA
4.0 V ≤ VDD ≤ 5.5 V −23.0 mA
2.7 V ≤ VDD < 4.0 V −20.0 mA
IOH1
Total of all pins
(When duty = 60%Note 2)
1.8 V ≤ VDD < 2.7 V −15.0 mA
Per pin for P20 to P27, P150 to P157 AVREF0 ≤ VDD −0.1 mA
Output current,
highNote 1
IOH2
Per pin for P110, P111 AVREF1 ≤ VDD −0.1 mA
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from EVDD0 or
EVDD1 pin to an output pin.
2. Specification under conditions where the duty factor is 60% or 70%.
The output current value that has changed the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 50% and IOH = −20.0 mA
Total output current of pins = (−20.0 × 0.7)/(50 × 0.01) = −28.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Caution P02 to P04, P43, P45, P142 to P144 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
838
(A) Grade Products
DC Characteristics (2/16)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V 8.5 mA
2.7 V ≤ VDD < 4.0 V 1.0 mA
Per pin for P00 to P02, P05, P06,
P10 to P17, P30, P31, P40 to P47,
P50 to P57, P64 to P67, P70 to P77,
P80 to P87, P120, P130, P131,
P140, P141, P144, P145
1.8 V ≤ VDD < 2.7 V 0.5 mA
4.0 V ≤ VDD ≤ 5.5 V 8.5 mA
2.7 V ≤ VDD < 4.0 V 1.5 mA
Per pin for P03, P04, P142, P143
1.8 V ≤ VDD < 2.7 V 0.6 mA
4.0 V ≤ VDD ≤ 5.5 V 15.0 mA
2.7 V ≤ VDD < 4.0 V 3.0 mA
Per pin for P60 to P63
1.8 V ≤ VDD < 2.7 V 2.0 mA
4.0 V ≤ VDD ≤ 5.5 V 20.0 mA
2.7 V ≤ VDD < 4.0 V 15.0 mA
Total of P00 to P04, P40 to P47,
P120, P130, P131, P140 to P145
(When duty = 70%Note 2) 1.8 V ≤ VDD < 2.7 V 9.0 mA
4.0 V ≤ VDD ≤ 5.5 V 45.0 mA
2.7 V ≤ VDD < 4.0 V 35.0 mA
Total of P05, P06, P10 to P17, P30,
P31, P50 to P57, P60 to P67,
P70 to P77, P80 to P87
(When duty = 70%Note 2) 1.8 V ≤ VDD < 2.7 V 20.0 mA
4.0 V ≤ VDD ≤ 5.5 V 65.0 mA
2.7 V ≤ VDD < 4.0 V 50.0 mA
IOL1
Total of all pins
(When duty = 60%Note 2)
1.8 V ≤ VDD < 2.7 V 29.0 mA
Per pin for P20 to P27, P150 to P157 AVREF0 ≤ VDD 0.4 mA
Output current,
lowNote 1
IOL2
Per pin for P110, P111 AVREF1 ≤ VDD 0.4 mA
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from an output
pin to EVSS0, EVSS1, VSS, and AVSS pin.
2. Specification under conditions where the duty factor is 60% or 70%.
The output current value that has changed the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 50% and IOL = 20.0 mA
Total output current of pins = (20.0 × 0.7)/(50 × 0.01) = 28.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Caution P02 to P04, P43, P45, P142 to P144 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 839
(A) Grade Products
DC Characteristics (3/16)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VIH1 P01, P02, P12, P13, P15, P41, P45, P52 to P57,
P64 to P67, P80 to P87, P121 to P124, P144
0.7VDD VDD V
VIH2 P00, P03 to P06, P10, P11, P14,
P16, P17, P30, P31, P40, P42 to
P44, P46, P47, P50, P51, P70 to
P77, P120, P131, P140 to P143,
P145, EXCLK, RESET
Normal input buffer 0.8VDD VDD V
TTL input buffer
4.0 V ≤ VDD ≤ 5.5 V
2.2 VDD V
TTL input buffer
2.7 V ≤ VDD < 4.0 V
2.0 VDD V
VIH3 P03, P04, P43, P44, P142, P143
TTL input buffer
1.8 V ≤ VDD < 2.7 V
1.6 VDD V
2.7 V ≤ AVREF0 ≤ VDDVIH4 P20 to P27, P150 to P157
AVREF0 = VDD < 2.7 V
0.7AVREF0 AVREF0 V
2.7 V ≤ AVREF1 ≤ VDDVIH5 P110, P111
AVREF1 = VDD < 2.7 V
0.7AVREF1 AVREF1 V
VIH6 P60 to P63 0.7VDD 6.0 V
Input voltage,
high
VIH7 FLMD0 0.9VDD
Note
V
DD V
Note Must be 0.9VDD or higher when used in the flash memory programming mode.
Cautions 1. The maximum value of VIH of pins P02 to P04, P43, P45, and P142 to P144 is VDD, even in the N-
ch open-drain mode.
2. For P122/EXCLK, the value of VIH and VIL differs according to the input port mode or external
clock mode.
Make sure to satisfy the DC characteristics of EXCLK in external clock input mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
840
(A) Grade Products
DC Characteristics (4/16)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VIL1 P01, P02, P12, P13, P15, P41, P45, P52 to P57,
P64 to P67, P80 to P87, P121 to P124, P144
0 0.3VDD V
VIL2 P00, P03 to P06, P10, P11, P14,
P16, P17, P30, P31, P40, P42 to
P44, P46, P47, P50, P51, P70 to
P77, P120, P131, P140 to P143,
P145, EXCLK, RESET
Normal input buffer 0 0.2VDD V
TTL input buffer
4.0 V ≤ VDD ≤ 5.5 V
0 0.8 V
TTL input buffer
2.7 V ≤ VDD < 4.0 V
0 0.5 V
VIL3 P03, P04, P43, P44, P142, P143
TTL input buffer
1.8 V ≤ VDD < 2.7 V
0 0.2 V
2.7 V ≤ AVREF0 ≤ VDDVIL4 P20 to P27, P150 to P157
AVREF0 = VDD < 2.7 V
0 0.3AVREF0 V
2.7 V ≤ AVREF1 ≤ VDDVIL5 P110, P111
AVREF1 = VDD < 2.7 V
0 0.3AVREF1 V
VIL6 P60 to P63 0 0.3VDD V
Input voltage,
low
VIL7 FLMD0Note 0 0.1VDD V
Note When disabling writing of the flash memory, connect the FLMD0 pin processing directly to VSS, and maintain
a voltage less than 0.1VDD.
Cautions 1. The maximum value of VIH of pins P02 to P04, P43, P45, and P142 to P144 is VDD, even in the N-
ch open-drain mode.
2. For P122/EXCLK, the value of VIH and VIL differs according to the input port mode or external
clock mode.
Make sure to satisfy the DC characteristics of EXCLK in external clock input mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 841
(A) Grade Products
DC Characteristics (5/16)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V,
IOH1 = −3.0 mA
VDD − 0.7 V VOH1 P00 to P06, P10 to P17, P30, P31,
P40 to P47, P50 to P57, P64 to P67,
P70 to P77, P80 to P87, P120, P130,
P131, P140 to P145
1.8 V ≤ VDD ≤ 5.5 V,
IOH1 = −1.0 mA
VDD − 0.5 V
P20 to P27, P150 to P157 AVREF0 ≤ VDD,
IOH2 = −0.1 mA
AVREF0 −
0.5
V
Output voltage,
high
VOH2
P110, P111 AVREF1 ≤ VDD,
IOH2 = −0.1 mA
AVREF1 −
0.5
V
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 8.5 mA
0.7 V
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 1.0 mA
0.5 V
P00 to P02, P05, P06, P10 to P17,
P30, P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77, P80 to P87,
P120, P130, P131, P140, P141,
P144, P145 1.8 V ≤ VDD ≤ 5.5 V,
IOL1 = 0.5 mA
0.4 V
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 8.5 mA
0.7 V
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 1.5 mA
0.5 V
VOL1
P03, P04, P142, P143
1.8 V ≤ VDD ≤ 5.5 V,
IOL1 = 0.6 mA
0.4 V
P20 to P27, P150 to P157 AVREF0 ≤ VDD,
IOL2 = 0.4 mA
0.4 V
VOL2
P110, P111 AVREF1 ≤ VDD,
IOL2 = 0.4 mA
0.4 V
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 15.0 mA
2.0 V
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 5.0 mA
0.4 V
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 3.0 mA
0.4 V
Output voltage,
low
VOL3 P60 to P63
1.8 V ≤ VDD ≤ 5.5 V,
IOL1 = 2.0 mA
0.4 V
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
842
(A) Grade Products
DC Characteristics (6/16)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ILIH1 P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P60 to P67, P70 to P77,
P80 to P87, P120, P131,
P140 to P145, FLMD0, RESET
VI = VDD 1
μ
A
VI = AVREF0,
2.7 V ≤ AVREF0 ≤ VDD
ILIH2 P20 to P27, P150 to P157
VI = AVREF0,
AVREF0 = VDD < 2.7 V
1
μ
A
VI = AVREF1,
2.7 V ≤ AVREF1 ≤ VDD
ILIH3 P110, P111
VI = AVREF1,
AVREF1 = VDD < 2.7 V
1
μ
A
In input port 1
μ
A
Input leakage
current, high
ILIH4 P121 to P124
(X1, X2, XT1, XT2)
VI = VDD
In resonator
connection
10
μ
A
ILIL1 P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P60 to P67, P70 to P77,
P80 to P87, P120, P131,
P140 to P145, FLMD0, RESET
VI = VSS −1
μ
A
VI = VSS,
2.7 V ≤ AVREF0 ≤ VDD
ILIL2 P20 to P27, P150 to P157
VI = VSS,
AVREF0 = VDD < 2.7 V
−1
μ
A
VI = VSS,
2.7 V ≤ AVREF1 ≤ VDD
ILIL3 P110, P111
VI = VSS,
AVREF1 = VDD < 2.7 V
−1
μ
A
In input port −1
μ
A
Input leakage
current, low
ILIL4 P121 to P124
(X1, X2, XT1, XT2)
VI = VSS
In resonator
connection
−10
μ
A
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 843
(A) Grade Products
DC Characteristics (7/16)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
On-chip pull-up
resistance
RU P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P120, P131,
P140 to P145
VI = VSS, In input port 10 20 100 kΩ
FLMD0 pin
external pull-down
resistanceNote
RFLMD0 When enabling the self-programming mode setting with
software
100 kΩ
Note It is recommended to leave the FLMD0 pin open. If the pin is required to be pulled down externally, set
RFLMD0 to 100 kΩ or more.
78K0R/KG3
FLMD0 pin
R
FLMD0
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
844
(A) Grade Products
DC Characteristics (8/16)
μ
PD78F1162A(A), 78F1163A(A), 78F1164A(A), 78F1165A(A), 78F1166A(A)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Square wave input 7.0 12.2 mA
fMX = 20 MHzNote 2,
VDD = 5.0 V Resonator connection 7.3 12.5 mA
Square wave input 7.0 12.2 mA
fMX = 20 MHzNote 2,
VDD = 3.0 V Resonator connection 7.3 12.5 mA
Square wave input 3.8 6.2 mA
fMX = 10 MHzNotes 2, 3,
VDD = 5.0 V Resonator connection 3.9 6.3 mA
Square wave input 3.8 6.2 mA
fMX = 10 MHzNotes 2, 3,
VDD = 3.0 V Resonator connection 3.9 6.3 mA
Square wave input 2.1 3.0 mA
Normal current
mode Resonator connection 2.2 3.1 mA
Square wave input 1.5 2.1 mA
fMX = 5 MHzNotes 2, 3,
VDD = 3.0 V
Low consumption
current modeNote 4 Resonator connection 1.5 2.1 mA
Square wave input 1.4 2.1 mA
Normal current
mode Resonator connection 1.4 2.1 mA
Square wave input 1.4 2.0 mA
fMX = 5 MHzNotes 2, 3,
VDD = 2.0 V
Low consumption
current modeNote 4 Resonator connection 1.4 2.0 mA
VDD = 5.0 V 3.1 5.0 mA
Supply
current
IDD1Note 1 Operating
mode
fIH = 8 MHzNote 5
VDD = 3.0 V 3.1 5.0 mA
Notes 1. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, D/A
converter, LVI circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. When internal high-speed oscillator and subsystem clock are stopped.
3. When AMPH (bit 0 of clock operation mode control register (CMC)) = 0 and FSEL (bit 0 of operation speed
mode control register (OSMC)) = 0.
4. When the RMC register is set to 5AH.
5. When high-speed system clock and subsystem clock are stopped. When FSEL (bit 0 of operation speed
mode control register (OSMC)) = 0 is set.
Remarks 1. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
f
IH: Internal high-speed oscillation clock frequency
2. For details on the normal current mode and low consumption current mode according to the regulator
output voltage, refer to CHAPTER 23 REGULATOR.
3. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 845
(A) Grade Products
DC Characteristics (9/16)
μ
PD78F1162A(A), 78F1163A(A), 78F1164A(A), 78F1165A(A), 78F1166A(A)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V 6.4 24.0
μ
A
VDD = 3.0 V 6.4 24.0
μ
A
fSUB = 32.768 kHzNote 2,
TA = −40 to +70°C
VDD = 2.0 V 6.3 21.0
μ
A
VDD = 5.0 V 6.4 31.0
μ
A
VDD = 3.0 V 6.4 31.0
μ
A
Supply
current
IDD1Note 1 Operating
mode
fSUB = 32.768 kHzNote 2,
TA = −40 to +85°C
VDD = 2.0 V 6.3 28.0
μ
A
Notes 1. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, D/A
converter, LVI circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. When internal high-speed oscillator and high-speed system clock are stopped. When watchdog timer is
stopped.
Remarks 1. f
SUB : Subsystem clock frequency (XT1 clock oscillation frequency)
2. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
846
(A) Grade Products
DC Characteristics (10/16)
μ
PD78F1162A(A), 78F1163A(A), 78F1164A(A), 78F1165A(A), 78F1166A(A)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Square wave input 1.0 2.7 mA
fMX = 20 MHzNote 2,
VDD = 5.0 V Resonator connection 1.3 3.0 mA
Square wave input 1.0 2.7 mA
fMX = 20 MHzNote 2,
VDD = 3.0 V Resonator connection 1.3 3.0 mA
Square wave input 0.52 1.4 mA
fMX = 10 MHzNotes 2, 3,
VDD = 5.0 V Resonator connection 0.62 1.5 mA
Square wave input 0.52 1.4 mA
fMX = 10 MHzNotes 2, 3,
VDD = 3.0 V Resonator connection 0.62 1.5 mA
Square wave input 0.36 0.75 mA
Normal current
mode Resonator connection 0.41 0.8 mA
Square wave input 0.22 0.5 mA
fMX = 5 MHzNotes 2, 3,
VDD = 3.0 V
Low consumption
current modeNote 4 Resonator connection 0.27 0.55 mA
Square wave input 0.22 0.5 mA
Normal current
mode Resonator connection 0.27 0.55 mA
Square wave input 0.22 0.5 mA
fMX = 5 MHzNotes 2, 3,
VDD = 2.0 V
Low consumption
current modeNote 4 Resonator connection 0.27 0.55 mA
VDD = 5.0 V 0.45 1.2 mA
Supply
current
IDD2Note 1 HALT
mode
fIH = 8 MHzNote 5
VDD = 3.0 V 0.45 1.2 mA
Notes 1. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. The maximum value include the peripheral operation
current. However, not including the current flowing into the A/D converter, D/A converter, LVI circuit, I/O
port, and on-chip pull-up/pull-down resistors. During HALT instruction execution by flash memory.
2. When internal high-speed oscillator and subsystem clock are stopped.
3. When AMPH (bit 0 of clock operation mode control register (CMC)) = 0 and FSEL (bit 0 of operation speed
mode control register (OSMC)) = 0.
4. When the RMC register is set to 5AH.
5. When high-speed system clock and subsystem clock are stopped. When FSEL (bit 0 of operation speed
mode control register (OSMC)) = 0 is set.
Remarks 1. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
f
IH: Internal high-speed oscillation clock frequency
2. For details on the normal current mode and low consumption current mode according to the regulator
output voltage, refer to CHAPTER 23 REGULATOR.
3. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 847
(A) Grade Products
DC Characteristics (11/16)
μ
PD78F1162A(A), 78F1163A(A), 78F1164A(A), 78F1165A(A), 78F1166A(A)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V 2.2 14.0
μ
A
VDD = 3.0 V 2.2 14.0
μ
A
fSUB = 32.768 kHzNote 2,
TA = −40 to +70°C
VDD = 2.0 V 2.1 13.8
μ
A
VDD = 5.0 V 2.2 21.0
μ
A
VDD = 3.0 V 2.2 21.0
μ
A
IDD2Note 1 HALT
mode
fSUB = 32.768 kHzNote 2,
TA = −40 to +85°C
VDD = 2.0 V 2.1 20.8
μ
A
TA = −40 to +70°C 1.1 9.0
μ
A
Supply
current
IDD3Note 3 STOP
mode TA = −40 to +85°C 1.1 16.0
μ
A
Notes 1. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. The maximum value include the peripheral operation
current. However, not including the current flowing into the A/D converter, D/A converter, LVI circuit, I/O
port, and on-chip pull-up/pull-down resistors. During HALT instruction execution by flash memory.
2. When internal high-speed oscillator and high-speed system clock are stopped. When watchdog timer is
stopped.
3. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. When subsystem clock is stopped. When watchdog
timer is stopped.
Remarks 1. fSUB : Subsystem clock frequency (XT1 clock oscillation frequency)
2. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
848
(A) Grade Products
DC Characteristics (12/16)
μ
PD78F1167A(A), 78F1168A(A)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Square wave input 7.0 12.2 mA
fMX = 20 MHzNote 2,
VDD = 5.0 V
Resonator connection 7.3 12.5 mA
Square wave input 7.0 12.2 mA
fMX = 20 MHzNote 2,
VDD = 3.0 V Resonator connection 7.3 12.5 mA
Square wave input 3.8 6.2 mA
fMX = 10 MHzNotes 2, 3,
VDD = 5.0 V
Resonator connection 3.9 6.3 mA
Square wave input 3.8 6.2 mA
fMX = 10 MHzNotes 2, 3,
VDD = 3.0 V Resonator connection 3.9 6.3 mA
Square wave input 2.1 3.0 mA
Normal current
mode Resonator connection 2.2 3.1 mA
Square wave input 1.5 2.1 mA
fMX = 5 MHzNotes 2, 3,
VDD = 3.0 V
Low consumption
current modeNote 4 Resonator connection 1.5 2.1 mA
Square wave input 1.4 2.1 mA
Normal current
mode Resonator connection 1.4 2.1 mA
Square wave input 1.4 2.0 mA
fMX = 5 MHzNotes 2, 3,
VDD = 2.0 V
Low consumption
current modeNote 4 Resonator connection 1.4 2.0 mA
VDD = 5.0 V
3.1 5.0 mA
Supply
current
IDD1Note 1 Operating
mode
fIH = 8 MHzNote 5
VDD = 3.0 V 3.1 5.0 mA
Notes 1. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, D/A
converter, LVI circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. When internal high-speed oscillator and subsystem clock are stopped.
3. When AMPH (bit 0 of clock operation mode control register (CMC)) = 0 and FSEL (bit 0 of operation speed
mode control register (OSMC)) = 0.
4. When the RMC register is set to 5AH.
5. When high-speed system clock and subsystem clock are stopped. When FSEL (bit 0 of operation speed
mode control register (OSMC)) = 0 is set.
Remarks 1. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
f
IH: Internal high-speed oscillation clock frequency
2. For details on the normal current mode and low consumption current mode according to the regulator
output voltage, refer to CHAPTER 23 REGULATOR.
3. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 849
(A) Grade Products
DC Characteristics (13/16)
μ
PD78F1167A(A), 78F1168A(A)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V 6.4 36.0
μ
A
VDD = 3.0 V 6.4 36.0
μ
A
fSUB = 32.768 kHzNote 2,
TA = −40 to +70°C
VDD = 2.0 V 6.3 32.8
μ
A
VDD = 5.0 V 6.4 51.0
μ
A
VDD = 3.0 V 6.4 51.0
μ
A
Supply
current
IDD1Note 1 Operating
mode
fSUB = 32.768 kHzNote 2,
TA = −40 to +85°C
VDD = 2.0 V 6.3 47.8
μ
A
Notes 1. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, D/A
converter, LVI circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. When internal high-speed oscillator and high-speed system clock are stopped. When watchdog timer is
stopped.
Remarks 1. fSUB : Subsystem clock frequency (XT1 clock oscillation frequency)
2. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
850
(A) Grade Products
DC Characteristics (14/16)
μ
PD78F1167A(A), 78F1168A(A)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Square wave input 1.0 2.7 mA
fMX = 20 MHzNote 2,
VDD = 5.0 V
Resonator connection 1.3 3.0 mA
Square wave input 1.0 2.7 mA
fMX = 20 MHzNote 2,
VDD = 3.0 V Resonator connection 1.3 3.0 mA
Square wave input 0.52 1.4 mA
fMX = 10 MHzNotes 2, 3,
VDD = 5.0 V
Resonator connection 0.62 1.5 mA
Square wave input 0.52 1.4 mA
fMX = 10 MHzNotes 2, 3,
VDD = 3.0 V Resonator connection 0.62 1.5 mA
Square wave input 0.36 0.75 mA
Normal current
mode Resonator connection 0.41 0.8 mA
Square wave input 0.22 0.5 mA
fMX = 5 MHzNotes 2, 3,
VDD = 3.0 V
Low consumption
current modeNote 4 Resonator connection 0.27 0.55 mA
Square wave input 0.22 0.5 mA
Normal current
mode Resonator connection 0.27 0.55 mA
Square wave input 0.22 0.5 mA
fMX = 5 MHzNotes 2, 3,
VDD = 2.0 V
Low consumption
current modeNote 4 Resonator connection 0.27 0.55 mA
VDD = 5.0 V
0.45 1.2 mA
Supply
current
IDD2Note 1 HALT
mode
fIH = 8 MHzNote 5
VDD = 3.0 V 0.45 1.2 mA
Notes 1. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. The maximum value include the peripheral operation
current. However, not including the current flowing into the A/D converter, D/A converter, LVI circuit, I/O
port, and on-chip pull-up/pull-down resistors. During HALT instruction execution by flash memory.
2. When internal high-speed oscillator and subsystem clock are stopped.
3. When AMPH (bit 0 of clock operation mode control register (CMC)) = 0 and FSEL (bit 0 of operation speed
mode control register (OSMC)) = 0.
4. When the RMC register is set to 5AH.
5. When high-speed system clock and subsystem clock are stopped. When FSEL (bit 0 of operation speed
mode control register (OSMC)) = 0 is set.
Remarks 1. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
f
IH: Internal high-speed oscillation clock frequency
2. For details on the normal current mode and low consumption current mode according to the regulator
output voltage, refer to CHAPTER 23 REGULATOR.
3. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 851
(A) Grade Products
DC Characteristics (15/16)
μ
PD78F1167A(A), 78F1168A(A)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V 2.2 26.0
μ
A
VDD = 3.0 V 2.2 26.0
μ
A
fSUB = 32.768 kHzNote 2,
TA = −40 to +70°C
VDD = 2.0 V 2.1 25.8
μ
A
VDD = 5.0 V 2.2 41.0
μ
A
VDD = 3.0 V 2.2 41.0
μ
A
IDD2Note 1 HALT
mode
fSUB = 32.768 kHzNote 2,
TA = −40 to +85°C
VDD = 2.0 V 2.1 40.8
μ
A
TA = −40 to +70°C 1.1 21.0
μ
A
Supply
current
IDD3Note 3 STOP
mode TA = −40 to +85°C 1.1 36.0
μ
A
Notes 1. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. The maximum value include the peripheral operation
current. However, not including the current flowing into the A/D converter, D/A converter, LVI circuit, I/O
port, and on-chip pull-up/pull-down resistors. During HALT instruction execution by flash memory.
2. When internal high-speed oscillator and high-speed system clock are stopped. When watchdog timer is
stopped.
3. Total current flowing into VDD, EVDD0, EVDD1, AVREF0, and AVREF1, including the input leakage current flowing
when the level of the input pin is fixed to VDD or VSS. When subsystem clock is stopped. When watchdog
timer is stopped.
Remarks 1. fSUB : Subsystem clock frequency (XT1 clock oscillation frequency)
2. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
852
(A) Grade Products
DC Characteristics (16/16)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD,
VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 3.0 V 0.2 1.0
RTC operating
current
IRTCNotes 1, 2 fSUB = 32.768 kHz
VDD = 2.0 V 0.2 1.0
μ
A
Watchdog timer
operating
current
IWDTNotes 2, 3 fIL = 240 kHz 5 10
μ
A
A/D converter
operating
current
IADCNote 4 During conversion at maximum speed,
2.3 V ≤ AVREF0
0.86 1.9 mA
D/A converter
operating
current
IDACNote 5 Per 1 channel 1.0 2.5 mA
LVI operating
current
ILVINote 6 9 18
μ
A
Notes 1. Current flowing only to the real-time counter (excluding the operating current of the XT1 oscillator). The
current value of the 78K0R/KG3 is the TYP. value, the sum of the TYP. values of either IDD1 or IDD2, and IRTC,
when the real-time counter operates in operation mode or HALT mode. The IDD1 and IDD2 MAX. values also
include the real-time counter operating current.
2. When internal high-speed oscillator and high-speed system clock are stopped.
3. Current flowing only to the watchdog timer (including the operating current of the 240 kHz internal oscillator).
The current value of the 78K0R/KG3 is the sum of IDD1, I DD2 or I DD3 and IWDT when fCLK = fSUB/2 or when the
watchdog timer operates in STOP mode.
4. Current flowing only to the A/D converter (AVREF0 pin). The current value of the 78K0R/KG3 is the sum of
IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
5. Current flowing only to the D/A converter (AVREF1 pin). The current value of the 78K0R/KG3 is the sum of
IDD1 or IDD2 and IDAC when the D/A converter operates in an operation mode or the HALT mode.
6. Current flowing only to the LVI circuit. The current value of the 78K0R/KG3 is the sum of IDD1, IDD2 or IDD3
and ILVI when the LVI circuit operates in the operation mode, HALT or STOP mode.
Remarks 1. fIL: Internal low-speed oscillation clock frequency
f
SUB: Subsystem clock frequency (XT1 clock oscillation frequency)
f
CLK: CPU/peripheral hardware clock frequency
2. Temperature condition of the TYP. value is TA = 25°C
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 853
(A) Grade Products
AC Characteristics
(1) Basic operation (1/6)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤
VDD, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 0.05 8
μ
s
Normal
current mode 1.8 V ≤ VDD < 2.7 V 0.2 8
μ
s
Main system clock
(fMAIN) operation
Low consumption current mode 0.2 8
μ
s
Subsystem clock (fSUB) operation 57.2 61 62.5
μ
s
Instruction cycle
(minimum instruction
execution time)
TCY
In the self
programming mode
Normal
current mode
2.7 V ≤ VDD ≤ 5.5 V 0.05 0.5
μ
s
Normal current mode 2.0 20.0 MHz 2.7 V ≤ VDD ≤ 5.5 V
Low consumption current mode 2.0 5.0 MHz
External main system
clock frequency
fEX
1.8 V ≤ VDD < 2.7 V 2.0 5.0 MHz
Normal current mode 24 ns 2.7 V ≤ VDD ≤ 5.5 V
Low consumption current mode 96 ns
External main system
clock input high-level
width, low-level width
tEXH, tEXL
1.8 V ≤ VDD < 2.7 V 96 ns
TI00 to TI07 input
high-level width, low-
level width
tTIH,
tTIL
1/fMCK + 10 ns
2.7 V ≤ VDD ≤ 5.5 V 10 MHz
TO00 to TO07 output
frequency
fTO
1.8 V ≤ VDD < 2.7 V 5 MHz
2.7 V ≤ VDD ≤ 5.5 V 10 MHz
PCLBUZ0, PCLBUZ1
output frequency
fPCL
1.8 V ≤ VDD < 2.7 V 5 MHz
Interrupt input high-
level width, low-level
width
tINTH,
tINTL
1
μ
s
Key interrupt input
low-level width
tKR 250 ns
RESET low-level
width
tRSL 10
μ
s
Remarks 1. f
MCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKS0n bit of the TMR0n register. n: Channel number (n = 0 to 7))
2. For details on the normal current mode and low consumption current mode according to the regulator
output voltage, refer to CHAPTER 23 REGULATOR.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
854
(A) Grade Products
(1) Basic operation (2/6)
Minimum instruction execution time during main system clock operation (FSEL = 0, RMC = 00H)
8.0
1.0
0.2
0.1
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
2.7
0.01
1.8
Guaranteed range of main system
clock operation (FSEL = 0, RMC = 00H)
2.1
The range enclosed in dotted lines
applies when the internal high-speed
oscillator is selected.
Supply voltage VDD [V]
Cycle time TCY [ s]
μ
Remark FSEL: Bit 0 of the operation speed mode control register (OSMC)
RMC: Regulator mode control register
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 855
(A) Grade Products
(1) Basic operation (3/6)
Minimum instruction execution time during main system clock operation (FSEL = 1, RMC = 00H)
8.0
1.0
0.2
0.1
0.05
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
2.7
0.01
1.8
Guaranteed range of main system
clock operation (FSEL = 1, RMC = 00H)
The range enclosed in dotted lines
applies when the internal high-speed
oscillator is selected.
Supply voltage VDD [V]
Cycle time TCY [ s]
μ
Remark FSEL: Bit 0 of the operation speed mode control register (OSMC)
RMC: Regulator mode control register
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
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(A) Grade Products
(1) Basic operation (4/6)
Minimum instruction execution time during main system clock operation (FSEL = 0, RMC = 5AH)
8.0
1.0
0.2
0.1
0.05
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
0.01
1.8
Supply voltage V
DD
[V]
Cycle time T
CY
[ s]
μ
Guaranteed range of main system
clock operation (FSEL = 0, RMC = 5AH)
The range enclosed in dotted lines
applies when the internal high-speed
oscillator is selected.
Remarks 1. FSEL: Bit 0 of the operation speed mode control register (OSMC)
RMC: Regulator mode control register
2. The entire voltage range is 5 MHz (MAX.) when RMC is set to 5AH.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 857
(A) Grade Products
(1) Basic operation (5/6)
Minimum instruction execution time during self programming mode (RMC = 00H)
8.0
1.0
0.5
0.1
0.05
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
0.01
2.7
Cycle time T
CY
[ s]
μ
Supply voltage V
DD
[V]
Guaranteed range of self programming mode
(RMC = 00H)
The range enclosed in dotted lines applies when
the internal high-speed oscillator is selected.
Remarks 1. RMC: Regulator mode control register
2. The self programming function cannot be used when RMC is set to 5AH or the CPU operates with the
subsystem clock.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
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(A) Grade Products
(1) Basic operation (6/6)
AC Timing Test Points (Excluding external bus interface)
V
IH
V
IL
Test points V
IH
V
IL
External Main System Clock Timing
EXCLK 0.8V
DD
(MIN.)
0.2V
DD
(MAX.)
1/f
EX
t
EXL
t
EXH
TI Timing
TI00 to TI07
t
TIL
t
TIH
Interrupt Request Input Timing
INTP0 to INTP11
t
INTL
t
INTH
Key Interrupt Input Timing
KR0 to KR7
t
KR
RESET Input Timing
RESET
t
RSL
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 859
(A) Grade Products
(2) External bus interface (1/3)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(a) Read/write cycle (CLKOUT synchronous)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 100 ns CLKOUT cycle tCYK <1>
1.8 V ≤ VDD < 2.7 V 200 ns
2.7 V ≤ VDD ≤ 5.5 V 0.4tCYK − 30 0.6tCYK ns CLKOUT high-level width tWKH <2>
1.8 V ≤ VDD < 2.7 V 0.4tCYK − 50 0.6tCYK ns
2.7 V ≤ VDD ≤ 5.5 V 0.4tCYK − 30 0.6tCYK ns CLKOUT low-level width tWKL <3>
1.8 V ≤ VDD < 2.7 V 0.4tCYK − 50 0.6tCYK ns
2.7 V ≤ VDD ≤ 5.5 V 0.8tCYK − 40 1.2tCYK ns ASTB high-level width tWASH1 <4>
1.8 V ≤ VDD < 2.7 V 0.8tCYK − 60 1.2tCYK ns
2.7 V ≤ VDD ≤ 5.5 V (0.8 + m + w) tCYK − 40 (1.2 + m + w) tCYK ns RD low-level width tWRDL1 <5>
1.8 V ≤ VDD < 2.7 V (0.8 + m + w) tCYK − 60 (1.2 + m + w) tCYK ns
2.7 V ≤ VDD ≤ 5.5 V (0.8 + w) tCYK − 40 (1.2 + w) tCYK ns WR0, WR1 low-level width tWWRL1 <6>
1.8 V ≤ VDD < 2.7 V (0.8 + w) tCYK − 60 (1.2 + w) tCYK ns
2.7 V ≤ VDD ≤ 5.5 V 2 50 ns
Delay time from CLKOUT↑ to
ASTB
tDKAS1 <7>
1.8 V ≤ VDD < 2.7 V 2 80 ns
2.7 V ≤ VDD ≤ 5.5 V 2 50 ns
Delay time from CLKOUT↑ to
RD
tDKRD1 <8>
1.8 V ≤ VDD < 2.7 V 2 80 ns
2.7 V ≤ VDD ≤ 5.5 V 2 50 ns
Delay time from CLKOUT↑ to
WR0, WR1
tDKWR1 <9>
1.8 V ≤ VDD < 2.7 V 2 80 ns
2.7 V ≤ VDD ≤ 5.5 V 2 55 ns
Delay time from CLKOUT↑ to
address
tDKA1 <10>
1.8 V ≤ VDD < 2.7 V 2 90 ns
2.7 V ≤ VDD ≤ 5.5 V 2 55 ns
Data output delay time from
CLKOUT↑
tDKOD1 <11>
1.8 V ≤ VDD < 2.7 V 2 90 ns
2.7 V ≤ VDD ≤ 5.5 V 2 ns
Data output hold time from
CLKOUT↑
tHKOD1 <12>
1.8 V ≤ VDD < 2.7 V 2 ns
2.7 V ≤ VDD ≤ 5.5 V 40 ns
Data input setup time to
CLKOUT↑
tSKDI1 <13>
1.8 V ≤ VDD < 2.7 V 85 ns
2.7 V ≤ VDD ≤ 5.5 V 0 ns
Data input hold time from
CLKOUT↑
tHKDI1 <14>
1.8 V ≤ VDD < 2.7 V 0 ns
2.7 V ≤ VDD ≤ 5.5 V 45 ns WAIT setup time to CLKOUT↑ tSKWT1 <15>
1.8 V ≤ VDD < 2.7 V 85 ns
2.7 V ≤ VDD ≤ 5.5 V 0 ns
WAIT hold time from
CLKOUT↑
tHKWT1 <16>
1.8 V ≤ VDD < 2.7 V 0 ns
2.7 V ≤ VDD ≤ 5.5 V 0 ns
Delay time from address
output stop to RD↓
tDAR1 <17>
1.8 V ≤ VDD < 2.7 V 0 ns
Remarks 1. CL: The pin load capacitance is 15 pF.
2. Test points: VOH = 0.8VDD, VOL = 0.2VDD
3. m = 0: Multiplexed bus mode
m = 1: Separate bus mode
w: Number of waits with WAIT
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
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(A) Grade Products
(2) External bus interface (2/3)
Read/write cycle (CLKOUT synchronous): In separate bus mode
WR0, WR1
D7 to D0
D15 to D0
A19 to A0
CLKOUT
WAIT
RD
<5>
<8> <8>
<9> <9>
<10>
<11>
<13> <14>
<6>
<1>
<2> <3>
<12>
<10>
<16>
<16><15>
<15>
<16>
<16><15>
<15>
Data Data
Address Address
Read/write cycle (CLKOUT synchronous): In multiplexed bus mode
WR0, WR1
ASTB
AD7 to AD0
AD15 to AD0
A19 to A8
A19 to A16
CLKOUT
WAIT
RD
<4>
<4>
<7>
<7><7> <7>
<5>
<8>
<17>
<8>
<9> <9>
<12>
<12>
<11>
<10> <10>
<11>
<11>
<13> <14>
<6>
<1>
<2> <3>
<15>
<16>
<16>
<15>
<15>
<16>
<16>
<15>
Address Data Data
Address
Address Address
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 861
(A) Grade Products
(2) External bus interface (3/3)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(b) Read/write cycle (CLKOUT asynchronous)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 100 ns CLKOUT cycle tCYK2 <18>
1.8 V ≤ VDD < 2.7 V 200 ns
2.7 V ≤ VDD ≤ 5.5 V 1.8tCYK2 − 40 2.2tCYK2 ns RD low-level width tWRDL2 <19>
1.8 V ≤ VDD < 2.7 V 1.8tCYK2 − 60 2.2tCYK2 ns
2.7 V ≤ VDD ≤ 5.5 V 0.8tCYK2 − 40 1.2tCYK2 ns WR0, WR1 low-level width tWWRL2 <20>
1.8 V ≤ VDD < 2.7 V 0.8tCYK2 − 60 1.2tCYK2 ns
2.7 V ≤ VDD ≤ 5.5 V 90 ns Data input setup time to RD↑ tSRDDI2 <21>
1.8 V ≤ VDD < 2.7 V 170 ns
2.7 V ≤ VDD ≤ 5.5 V 0 ns Data input hold time from RD↑ tHRDDI2 <22>
1.8 V ≤ VDD < 2.7 V 0 ns
2.7 V ≤ VDD ≤ 5.5 V tCYK2 − 5 ns Data output setup time to WR0, WR1↓ tSWROD2 <23>
1.8 V ≤ VDD < 2.7 V tCYK2 − 15 ns
2.7 V ≤ VDD ≤ 5.5 V 2 ns Data output hold time from WR0, WR1↑ tHKOD2 <24>
1.8 V ≤ VDD < 2.7 V 2 ns
2.7 V ≤ VDD ≤ 5.5 V 5 ns Delay time from RD↓ to address tDRDA2 <25>
1.8 V ≤ VDD < 2.7 V 15 ns
2.7 V ≤ VDD ≤ 5.5 V tCYK2 − 5 ns Address setup time to WR0, WR1↓ tSWRA2 <26>
1.8 V ≤ VDD < 2.7 V tCYK2 − 15 ns
Cautions 1. CLKOUT output is not used during CLKOUT asynchronous operation, but a CPU wait occurs
according to the setting of bits 4 and 5 (EW0, EW1) of the memory expansion mode control
register (MEM). When fCLK is sufficiently high, insert a wait by setting the EW0 and EW1 bits.
2. Do not use the WAIT pin during CLKOUT asynchronous operation.
Use the separate bus mode during CLKOUT asynchronous operation.
Remarks 1. f
CLK: CPU/peripheral hardware clock frequency
2. CL: The pin load capacitance is 15 pF.
3. Test points: VOH = 0.8VDD, VOL = 0.2VDD
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
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(A) Grade Products
Read/write cycle (CLKOUT asynchronous): In separate bus mode
WR0, WR1
D7 to D0
D15 to D0
A19 to A0
CLKOUT
RD
<19>
<24>
<25>
<21> <22>
<20>
<23>
Data Data
Address Address
<26>
<18>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 863
(A) Grade Products
(3) Serial interface: Serial array unit (1/18)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(a) During communication at same potential (UART mode) (dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fMCK/6 bps Transfer rate
fCLK = 20 MHz, fMCK = fCLK 3.3 Mbps
UART mode connection diagram (during communication at same potential)
78K0R/KG3 User's device
TxDq
RxDq
Rx
Tx
UART mode bit width (during communication at same potential) (reference)
Baud rate error tolerance
High-/Low-bit width
1/Transfer rate
TxDq
RxDq
Caution Select the normal input buffer for RxDi and the normal output mode for TxDi by using the PIMg and
POMg registers.
Remarks 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 14),
i: UART number for which communication at different potential can be selected (i = 1, 2)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3))
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
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(A) Grade Products
(3) Serial interface: Serial array unit (2/18)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(b) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V 200 Note 1 ns
2.7 V ≤ VDD < 4.0 V 300 Note 1 ns
SCKp cycle time tKCY1
1.8 V ≤ VDD < 2.7 V 600 Note 1 ns
4.0 V ≤ VDD ≤ 5.5 V tKCY1/2 − 20 ns
2.7 V ≤ VDD < 4.0 V tKCY1/2 − 35 ns
SCKp high-/low-level width tKH1,
tKL1
1.8 V ≤ VDD < 2.7 V tKCY1/2 − 80 ns
4.0 V ≤ VDD ≤ 5.5 V 70 ns
2.7 V ≤ VDD < 4.0 V 100 ns
SIp setup time (to SCKp↑)Note 2 tSIK1
1.8 V ≤ VDD < 2.7 V 190 ns
SIp hold time (from SCKp↑)Note 3 tKSI1 30 ns
Delay time from SCKp↓ to
SOp outputNote 4
tKSO1 C = 30 pFNote 5 40 ns
Notes 1. The value must also be 4/fCLK or more.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for SIj and the normal output mode for SOj and SCKj by using the
PIMg and POMg registers.
Remarks 1. p: CSI number (p = 00, 01, 10, 20), g: PIM and POM number (g = 0, 4, 14),
j: CSI number for which communication at different potential can be selected (j = 01, 10, 20)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 865
(A) Grade Products
(3) Serial interface: Serial array unit (3/18)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(c) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V 6/fMCK ns
16 MHz < fMCK 8/fMCK ns 2.7 V ≤ VDD < 4.0 V
fMCK ≤ 16 MHz 6/fMCK ns
16 MHz < fMCK 8/fMCK ns
SCKp cycle time tKCY2
1.8 V ≤ VDD < 2.7 V
fMCK ≤ 16 MHz 6/fMCK ns
SCKp high-/low-level width tKH2,
tKL2
f
KCY2/2 ns
SIp setup time
(to SCKp↑)Note 1
tSIK2 80 ns
SIp hold time
(from SCKp↑)Note 2
tKSI2 1/fMCK + 50 ns
4.0 V ≤ VDD ≤ 5.5 V 2/fMCK + 45 ns
2.7 V ≤ VDD < 4.0 V 2/fMCK + 57 ns
Delay time from SCKp↓ to
SOp outputNote 3
tKSO2 C = 30 pFNote 4
1.8 V ≤ VDD < 2.7 V 2/fMCK + 125 ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output line.
Caution Select the normal input buffer for SIj and SCKj and the normal output mode for SOj by using the
PIMg and POMg registers.
Remarks 1. p: CSI number (p = 00, 01, 10, 20), g: PIM and POM number (g = 0, 4, 14),
j: CSI number for which communication at different potential can be selected (j = 01, 10, 20)
2. f
MCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 2))
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
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(A) Grade Products
(3) Serial interface: Serial array unit (4/18)
CSI mode connection diagram (during communication at same potential)
78K0R/KG3 User's device
SCKp
SOp
SCK
SI
SIp SO
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1)
SIp Input data
Output data
SOp
t
KCY1, 2
t
KL1, 2
t
KH1, 2
t
SIK1, 2
t
KSI1, 2
t
KSO1, 2
SCKp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0)
SIp Input data
Output data
SOp
t
KCY1, 2
t
KH1, 2
t
KL1, 2
t
SIK1, 2
t
KSI1, 2
t
KSO1, 2
SCKp
Remarks 1. p: CSI number (p = 00, 01, 10, 20)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
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(A) Grade Products
(3) Serial interface: Serial array unit (5/18)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(d) During communication at same potential (simplified I2C mode)
Parameter Symbol Conditions MIN. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
400 Note kHz SCLr clock frequency fSCL
1.8 V ≤ VDD < 2.7 V
Cb = 100 pF, Rb = 5 kΩ
300 Note kHz
2.7 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
995 ns
Hold time when SCLr = “L” tLOW
1.8 V ≤ VDD < 2.7 V
Cb = 100 pF, Rb = 5 kΩ
1500 ns
2.7 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
995 ns
Hold time when SCLr = “H” tHIGH
1.8 V ≤ VDD < 2.7 V
Cb = 100 pF, Rb = 5 kΩ
1500 ns
2.7 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1/fMCK + 120 ns Data setup time (reception) tSU:DAT
1.8 V ≤ VDD < 2.7 V
Cb = 100 pF, Rb = 5 kΩ
1/fMCK + 230 ns
2.7 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
0 160 ns
Data hold time (transmission) tHD:DAT
1.8 V ≤ VDD < 2.7 V
Cb = 100 pF, Rb = 5 kΩ
0 210 ns
Note The value must also be fMCK/4 or less.
(Remarks are given on the next page.)
<R>
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
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(A) Grade Products
(3) Serial interface: Serial array unit (6/18)
Simplified I2C mode connection diagram (during communication at same potential)
78K0R/KG3 User's device
SDAr
SCLr
SDA
SCL
V
DD
R
b
Simplified I2C mode serial transfer timing (during communication at same potential)
SDAr
t
LOW
t
HIGH
t
HD:DAT
SCLr
t
SU:DAT
Caution Select the normal input buffer and the N-ch open-drain output (VDD tolerance) mode for SDAr and
the normal output mode for SCLr by using the PIMg and POMg registers.
Remarks 1. R
b[Ω]: Communication line (SDAr) pull-up resistance,
Cb[F]: Communication line (SCLr, SDAr) load capacitance
2. r: IIC number (r = 10, 20), g: PIM and POM number (g = 0, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0, 2), mn = 02, 10)
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
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(A) Grade Products
(3) Serial interface: Serial array unit (7/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(e) During communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator
output) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fMCK/6 bps
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V fCLK = 20 MHz, fMCK = fCLK 3.3 Mbps
fMCK/6 bps
Transfer rate Reception
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V fCLK = 20 MHz, fMCK = fCLK 3.3 Mbps
Caution Select the TTL input buffer for RxDq and the N-ch open-drain output (VDD tolerance) mode for TxDq
by using the PIMg and POMg registers.
Remarks 1. q: UART number (q = 1, 2), g: PIM and POM number (g = 0, 14)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3))
3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in UART mode.
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
4. UART0 and UART3 cannot communicate at different potential. Use UART1 and UART2 for
communication at different potential.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
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(A) Grade Products
(3) Serial interface: Serial array unit (8/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(e) During communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator
output) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Note 1
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V fCLK = 16.8 MHz, fMCK = fCLK,
Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V
2.8Note 2 Mbps
Note 3
Transfer rate Transmission
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V fCLK = 19.2 MHz, fMCK = fCLK,
Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V
1.2Note 4 Mbps
Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ VDD = EVDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
1
Maximum transfer rate = [bps]
{−Cb × Rb × ln (1 − 2.2
Vb)} × 3
1
Transfer rate × 2 − {−Cb × Rb × ln (1 − 2.2
Vb)}
Baud rate error (theoretical value) =
× 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD = EVDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 − 2.0
Vb)} × 3
[bps]
1
Transfer rate × 2 − {−Cb × Rb × ln (1 − 2.2
Vb)}
Baud rate error (theoretical value) =
× 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for RxDq and the N-ch open-drain output (VDD tolerance) mode for TxDq
by using the PIMg and POMg registers.
(Remarks are given on the next page.)
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 871
(A) Grade Products
(3) Serial interface: Serial array unit (9/18)
Remarks 1. Rb[Ω]: Communication line (TxDq) pull-up resistance,
C
b[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
2. q: UART number (q = 1, 2), g: PIM and POM number (g = 0, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3))
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in UART mode.
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
5. UART0 and UART3 cannot communicate at different potential. Use UART1 and UART2 for
communication at different potential.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
872
(A) Grade Products
(3) Serial interface: Serial array unit (10/18)
UART mode connection diagram (during communication at different potential)
78K0R/KG3 User's device
TxDq
RxDq
Rx
Tx
V
b
R
b
UART mode bit width (during communication at different potential) (reference)
TxDq
RxDq
Baud rate error tolerance
Baud rate error tolerance
Low-bit width
High-/Low-bit width
High-bit width
1/Transfer rate
1/Transfer rate
Caution Select the TTL input buffer for RxDq and the N-ch open-drain output (VDD tolerance) mode for TxDq
by using the PIMg and POMg registers.
Remarks 1. R
b[Ω]: Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage
2. q: UART number (q = 1, 2), g: PIM and POM number (g = 0, 14)
3. UART0 and UART3 cannot communicate at different potential. Use UART1 and UART2 for
communication at different potential.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 873
(A) Grade Products
(3) Serial interface: Serial array unit (11/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(f) During communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal
clock output) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
400 Note 1 ns SCKp cycle time tKCY1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
800 Note 1 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
tKCY1/2 − 75 ns SCKp high-level width tKH1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 − 170 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
tKCY1/2 − 20 ns SCKp low-level width tKL1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 − 35 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
150 ns
SIp setup time
(to SCKp↑) Note 2
tSIK1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
275 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
30 ns
SIp hold time
(from SCKp↑) Note 2
tKSI1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
30 ns
4.0 V ≤ VDD < 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
120 ns
Delay time from SCKp↓ to
SOp output Note 2
tKSO1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
215 ns
Notes 1. The value must also be 4/fCLK or more.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Caution Select the TTL input buffer for SIp and the N-ch open-drain output (VDD tolerance) mode for SOp and
SCKp by using the PIMg and POMg registers.
Remarks 1. p: CSI number (p = 01, 10, 20), g: PIM and POM number (g = 0, 4, 14)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
3. R
b[Ω]: Communication line (SCKp, SOp) pull-up resistance,
C
b[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
5. CSI00 cannot communicate at different potential. Use CSI01, CSI10, and CSI20 for communication at
different potential.
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
874
(A) Grade Products
(3) Serial interface: Serial array unit (12/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(f) During communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal
clock output) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
70 ns
SIp setup time
(to SCKp↓)Note
tSIK1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
100 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
30 ns
SIp hold time
(from SCKp↓)Note
tKSI1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
30 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
40 ns
Delay time from SCKp↑ to
SOp outputNote
tKSO1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
40 ns
Note When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
CSI mode connection diagram (during communication at different potential)
Vb
Rb
78K0R/KG3 User's device
<Master>
SCKp
SOp
SCK
SI
SIp SO
Vb
Rb
Caution Select the TTL input buffer for SIp and the N-ch open-drain output (VDD tolerance) mode for SOp and
SCKp by using the PIMg and POMg registers.
Remarks 1. p: CSI number (p = 01, 10, 20), g: PIM and POM number (g = 0, 4, 14)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
3. R
b[Ω]: Communication line (SCKp, SOp) pull-up resistance,
C
b[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
5. CSI00 cannot communicate at different potential. Use CSI01, CSI10, and CSI20 for communication at
different potential.
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 875
(A) Grade Products
(3) Serial interface: Serial array unit (13/18)
CSI mode serial transfer timing (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1)
SIp Input data
Output dataSOp
t
KCY1
t
KL1
t
KH1
t
SIK1
t
KSI1
t
KSO1
SCKp
CSI mode serial transfer timing (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0)
SIp Input data
Output data
SOp
t
KCY1
t
KL1
t
KH1
t
SIK1
t
KSI1
t
KSO1
SCKp
Caution Select the TTL input buffer for SIp and the N-ch open-drain output (VDD tolerance) mode for SOp and
SCKp by using the PIMg and POMg registers.
Remarks 1. p: CSI number (p = 01, 10, 20), g: PIM and POM number (g = 0, 4, 14)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
3. CSI00 cannot communicate at different potential. Use CSI01, CSI10, and CSI20 for communication at
different potential.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
876
(A) Grade Products
(3) Serial interface: Serial array unit (14/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(g) During communication at different potential (2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external
clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
13.6 MHz < fMCK 10/fMCK ns
6.8 MHz < fMCK ≤ 13.6 MHz 8/fMCK ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
fMCK ≤ 6.8 MHz 6/fMCK ns
18.5 MHz < fMCK 16/fMCK ns
14.8 MHz < fMCK ≤ 18.5 MHz 14/fMCK ns
11.1 MHz < fMCK ≤ 14.8 MHz 12/fMCK ns
7.4 MHz < fMCK ≤ 11.1 MHz 10/fMCK ns
3.7 MHz < fMCK ≤ 7.4 MHz 8/fMCK ns
SCKp cycle time tKCY2
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
fMCK ≤ 3.7 MHz 6/fMCK ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V fKCY2/2 − 20 ns
SCKp high-/low-level
width
tKH2,
tKL2 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V fKCY2/2 − 35 ns
SIp setup time
(to SCKp↑)Note 1
tSIK2 90 ns
SIp hold time
(from SCKp↑)Note 2
tKSI2 1/fMCK + 50 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2/fMCK +
120
ns
Delay time from
SCKp↓ to SOp
outputNote 3
tKSO2
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2/fMCK +
230
ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
CSI mode connection diagram (during communication at different potential)
78K0R/KG3 User's device
<Slave>
SCKp
SOp
SCK
SI
SIp SO
V
b
R
b
(Caution and Remarks are given on the next page.)
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 877
(A) Grade Products
(3) Serial interface: Serial array unit (15/18)
Caution Select the TTL input buffer for SIp and SCKp and the N-ch open-drain output (VDD tolerance) mode
for SOp by using the PIMg and POMg registers.
Remarks 1. p: CSI number (p = 01, 10, 20), g: PIM and POM number (g = 0, 4, 14)
2. R
b[Ω]: Communication line (SOp) pull-up resistance,
C
b[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 2))
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
5. CSI00 cannot communicate at different potential. Use CSI01, CSI10, and CSI20 for communication at
different potential.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
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878
(A) Grade Products
(3) Serial interface: Serial array unit (16/18)
CSI mode serial transfer timing (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1)
SIp Input data
Output data
SOp
t
KCY2
t
KL2
t
KH2
t
SIK2
t
KSI2
t
KSO2
SCKp
CSI mode serial transfer timing (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0)
SIp Input data
Output data
SOp
t
KCY2
t
KL2
t
KH2
t
SIK2
t
KSI2
t
KSO2
SCKp
Caution Select the TTL input buffer for SIp and SCKp and the N-ch open-drain output (VDD tolerance) mode
for SOp by using the PIMg and POMg registers.
Remarks 1. p: CSI number (p = 01, 10, 20), g: PIM and POM number (g = 0, 4, 14)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
3. CSI00 cannot communicate at different potential. Use CSI01, CSI10, and CSI20 for communication at
different potential.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 879
(A) Grade Products
(3) Serial interface: Serial array unit (17/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(h) During communication at different potential (2.5 V, 3 V) (simplified I2C mode)
Parameter Symbol Conditions MIN. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 1.4 kΩ
400 Note kHz SCLr clock frequency fSCL
2.7 V ≤ VDD ≤ 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
400 Note kHz
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 1.4 kΩ
1065 ns Hold time when SCLr = “L” tLOW
2.7 V ≤ VDD ≤ 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1065 ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 1.4 kΩ
445 ns
Hold time when SCLr = “H” tHIGH
2.7 V ≤ VDD ≤ 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
445 ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 1.4 kΩ
1/fMCK + 190 ns Data setup time (reception) tSU:DAT
2.7 V ≤ VDD ≤ 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
1/fMCK + 190 ns
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 1.4 kΩ
0 160 ns Data hold time (transmission) tHD:DAT
2.7 V ≤ VDD ≤ 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ
0 160 ns
Note The value must also be fMCK/4 or less.
Caution Select the TTL input buffer and the N-ch open-drain output (VDD tolerance) mode for SDAr and the
N-ch open-drain output (VDD tolerance) mode for SCLr by using the PIMg and POMg registers.
Remarks 1. R
b[Ω]: Communication line (SDAr, SCLr) pull-up resistance,
C
b[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage
2. r: IIC number (r = 10, 20), g: PIM, POM number (g = 0, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0, 2), mn = 02, 10)
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in simplified I2C mode.
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
<R>
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
880
(A) Grade Products
(3) Serial interface: Serial array unit (18/18)
Simplified I2C mode connection diagram (during communication at different potential)
78K0R/KG3 User's device
SDAr
SCLr
SDA
SCL
Vb
Rb
Vb
Rb
Simplified I2C mode serial transfer timing (during communication at different potential)
SDAr
t
LOW
t
HIGH
t
HD:DAT
SCLr
t
SU:DAT
1/f
SCL
Caution Select the TTL input buffer and the N-ch open-drain output (VDD tolerance) mode for SDAr and the
N-ch open-drain output (VDD tolerance) mode for SCLr by using the PIMg and POMg registers.
Remarks 1. R
b[Ω]: Communication line (SDAr, SCLr) pull-up resistance, Vb[V]: Communication line voltage
2. r: IIC number (r = 10, 20), g: PIM and POM number (g = 0, 14)
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 881
(A) Grade Products
(4) Serial interface: IIC0
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(a) IIC0
Standard Mode Fast Mode Parameter Symbol Conditions
MIN. MAX. MIN. MAX.
Unit
6.7 MHz ≤ fCLK 0 100 0 400 kHz
4.0 MHz ≤ fCLK < 6.7 MHz 0 100 0 340 kHz
3.2 MHz ≤ fCLK < 4.0 MHz 0 100 − − kHz
SCL0 clock frequency fSCL
2.0 MHz ≤ fCLK < 3.2 MHz 0 85 − − kHz
Setup time of restart conditionNote 1 tSU:STA 4.7 0.6
μ
s
Hold time tHD:STA 4.0 0.6
μ
s
Hold time when SCL0 = “L” tLOW 4.7 1.3
μ
s
Hold time when SCL0 = “H” tHIGH 4.0 0.6
μ
s
Data setup time (reception) tSU:DAT 250 100 ns
3.45Note 3 0.9Note 4
μ
s CL00 = 1 and CL01 = 1 0
5.50Note 5
0
1.5Note 6
μ
s
0.9Note 7
μ
s
CL00 = 0 and CL01 = 0, or
CL00 = 1 and CL01 = 0
0 3.45 0
0.95Note 8
μ
s
Data hold time (transmission)Note 2 tHD:DAT
CL00 = 0 and CL01 = 1 0 3.45 0 0.9
μ
s
Setup time of stop condition tSU:STO 4.0 0.6
μ
s
Bus-free time tBUF 4.7 1.3
μ
s
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
3. When 3.2 MHz ≤ fCLK ≤ 4.19 MHz.
4. When 6.7 MHz ≤ fCLK ≤ 8.38 MHz.
5. When 2.0 MHz ≤ fCLK < 3.2 MHz. At this time, use the SCL0 clock within 85 kHz.
6. When 4.0 MHz ≤ fCLK < 6.7 MHz. At this time, use the SCL0 clock within 340 kHz.
7. When 8.0 MHz ≤ fCLK ≤ 16.76 MHz.
8. When 7.6 MHz ≤ fCLK < 8.0 MHz.
Remark CL00, CL01, DFC0: Bits 0, 1, and 2 of the IIC clock select register 0 (IICCL0)
IIC0 serial transfer timing
t
LOW
t
BUF
t
HIGH
t
HD:STA
Stop
condition
Start
condition
Restart
condition
Stop
condition
t
SU:DAT
t
SU:STA
t
SU:STO
t
HD:STA
t
HD:DAT
SCL0
SDA0
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
882
(A) Grade Products
(5) Serial interface: On-chip debug (UART)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = AVSS = 0 V)
(a) On-chip debug (UART)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fCLK/212 fCLK/6 bps Transfer rate
Flash memory programming mode 2.66 Mbps
2.7 V ≤ VDD ≤ 5.5 V 10 MHz TOOL1 output frequency fTOOL1
1.8 V ≤ VDD < 2.7 V 2.5 MHz
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 883
(A) Grade Products
A/D Converter Characteristics
(TA = −40 to +85°C, 2.3 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 2.3 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD, VSS = EVSS0 =
EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 10 bit
4.0 V ≤ AVREF0 ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVREF0 < 4.0 V ±0.5 %FSR
Overall errorNotes 1, 2 AINL
2.3 V ≤ AVREF0 < 2.7 V ±0.7 %FSR
4.0 V ≤ AVREF0 ≤ 5.5 V 6.1 66.6
μ
s
2.7 V ≤ AVREF0 < 4.0 V 12.2 66.6
μ
s
Conversion time tCONV
2.3 V ≤ AVREF0 < 2.7 V 27 66.6
μ
s
4.0 V ≤ AVREF0 ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVREF0 < 4.0 V ±0.5 %FSR
Zero-scale errorNotes 1, 2 EZS
2.3 V ≤ AVREF0 < 2.7 V ±0.5 %FSR
4.0 V ≤ AVREF0 ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVREF0 < 4.0 V ±0.5 %FSR
Full-scale errorNotes 1, 2 EFS
2.3 V ≤ AVREF0 < 2.7 V ±0.5 %FSR
4.0 V ≤ AVREF0 ≤ 5.5 V ±2.5 LSB
2.7 V ≤ AVREF0 < 4.0 V ±3.5 LSB
Integral linearity errorNote 1 ILE
2.3 V ≤ AVREF0 < 2.7 V ±3.5 LSB
4.0 V ≤ AVREF0 ≤ 5.5 V ±1.5 LSB
2.7 V ≤ AVREF0 < 4.0 V ±1.5 LSB
Differential linearity errorNote 1 DLE
2.3 V ≤ AVREF0 < 2.7 V ±1.5 LSB
Analog input voltage VAIN 2.3 V ≤ AVREF0 ≤ 5.5 V AVSS AVREF0 V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
884
(A) Grade Products
Temperature Sensor
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 2.7 V ≤ AVREF0 ≤ VDD, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Augmentation factor per 10°C TC 1 3.5 15 /10°C
KTV-40 TA = −40°C 30 80 130
−
KTV25 TA = +25°C 65 101 140
−
Temperature sensor detection
value
KTV85 TA = +85°C 100 122 150 −
Remark The temperature sensor detection value is obtained by using the following expression.
A/D conversion value with sensor
that depends on temperature
Temperature
sensor detection
value
= A/D conversion value with sensor
that does not depend on temperature
× 256 ≅ TC
10 (
Temperature
during sensor
operation
−Low reference
temperature ) +
Temperature sensor
detection value at a
low reference
temperature
Temperature
Temperature sensor
detection value
KTV
25
KTV
−40
KTV
85
−40
˚C
+25
˚C
+85
˚C
D/A Converter Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, 1.8 V ≤ AVREF0 ≤ VDD, 1.8 V ≤ AVREF1 ≤ VDD, VSS = EVSS0 =
EVSS1 = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 bit
Rload = 2 MΩ ±1.2 %FSR
Rload = 4 MΩ ±0.8 %FSR
Overall error AINL
Rload = 10 MΩ ±0.6 %FSR
4.0 V ≤ AVREF1 ≤ 5.5 V 3
μ
s
2.7 V ≤ AVREF1 < 4.0 V 3
μ
s
Settling time tSET Cload = 20 pF
1.8 V ≤ AVREF1 < 2.7 V 6
μ
s
D/A output resistance value RO Per D/A converter channel 6.4 kΩ
Remark When the D/A converter is in normal mode, D/A conversion is started after one fCLK clock has elapsed since
the DACSn register was written. The output level is determined when the settling time has elapsed after
the D/A conversion was started.
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 885
(A) Grade Products
POC Circuit Characteristics (TA = −40 to +85°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOC0 1.5 1.59 1.68 V
Power supply voltage rise
inclination
tPTH Change inclination of VDD: 0 V → VPOC0 0.5 V/ms
Minimum pulse width tPW When the voltage drops 200
μ
s
Detection delay time 200
μ
s
POC Circuit Timing
Supply voltage
(V
DD
)
Time
Detection voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
t
PTH
t
PW
Supply Voltage Rise Time (TA = −40 to +85°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Maximum time to rise to
1.8 V (VDD (MIN.))Note
(VDD: 0 V → 1.8 V)
tPUP1 LVI default start function stopped
is set (LVIOFF (option byte) = 1),
when RESET input is not used
3.6 ms
Maximum time to rise to
1.8 V (VDD (MIN.))Note
(releasing RESET input → VDD: 1.8 V)
tPUP2 LVI default start function stopped
is set (LVIOFF (option byte) = 1),
when RESET input is used
1.88 ms
Note Make sure to raise the power supply in a shorter time than this.
Supply Voltage Rise Time Timing
• When RESET pin input is not used • When RESET pin input is used (when external reset is
released by the RESET pin, after POC has been released)
Supply voltage
(V
DD
)
Time
1.8 V
0 V
POC internal
signal
t
PUP1
Supply voltage
(V
DD
)
Time
1.8 V
t
PUP2
0 V
POC internal
signal
RESET pin
Internal reset
signal
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
886
(A) Grade Products
LVI Circuit Characteristics (TA = −40 to +85°C, VPOC ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VLVI0 4.12 4.22 4.32 V
VLVI1 3.97 4.07 4.17 V
VLVI2 3.82 3.92 4.02 V
VLVI3 3.66 3.76 3.86 V
VLVI4 3.51 3.61 3.71 V
VLVI5 3.35 3.45 3.55 V
VLVI6 3.20 3.30 3.40 V
VLVI7 3.05 3.15 3.25 V
VLVI8 2.89 2.99 3.09 V
VLVI9 2.74 2.84 2.94 V
VLVI10 2.58 2.68 2.78 V
VLVI11 2.43 2.53 2.63 V
VLVI12 2.28 2.38 2.48 V
VLVI13 2.12 2.22 2.32 V
VLVI14 1.97 2.07 2.17 V
Supply voltage level
VLVI15 1.81 1.91 2.01 V
External input pinNote 1 VEXLVI EXLVI < VDD, 1.8 V ≤ VDD ≤ 5.5 V 1.11 1.21 1.31 V
Detection
voltage
Power supply voltage
on power application
VPUPLVI When LVI default start function enabled
is set
1.87 2.07 2.27 V
Minimum pulse width tLW 200
μ
s
Detection delay time 200
μ
s
Operation stabilization wait timeNote 2 tLWAIT 10
μ
s
Notes 1. The EXLVI/P120/INTP0 pin is used.
2. Time required from setting bit 7 (LVION) of the low-voltage detection register (LVIM) to 1 to operation
stabilization
Remark V
LVI(n − 1) > VLVIn: n = 1 to 15
LVI Circuit Timing
Supply voltage
(VDD)
Time
Detection voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
tLW
tLWAIT
LVION ← 1
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD 887
(A) Grade Products
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR 1.5Note 5.5 V
Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC
reset is effected, but data is not retained when a POC reset is effected.
V
DD
STOP instruction execution
Standby release signal
(interrupt request)
STOP mode
Data retention mode
V
DDDR
Operation mode
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
User’s Manual U17894EJ9V0UD
888
(A) Grade Products
Flash Memory Programming Characteristics
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD0 = EVDD1 ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD supply current IDD TYP. = 10 MHz, MAX. = 20 MHz 4.5 15 mA
CPU/peripheral hardware
clock frequency
fCLK 2 20 MHz
Used for updating programs
When using flash memory programmer
and NEC Electronics self programming
library
Retained
for 15
years
100 Times
Number of rewrites (number
of deletes per block)
CWRT
Used for updating data
When using NEC Electronics EEPROM
emulation library (usable ROM size: 6
KB of 3 consecutive blocks)
Retained
for 5 years
10,000 Times
Remark When updating data multiple times, use the flash memory as one for updating data.
User’s Manual U17894EJ9V0UD 889
CHAPTER 31 PACKAGE DRAWINGS
S
y
e
Sxb
M
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
D
E
A3
S
0.125
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
20.00 0.20
14.00 0.20
22.00 0.20
16.00 0.20
1.60 MAX.
0.10 0.05
1.40 0.05
0.04
0.08
0.075
0.025
0.25
c
e
x
y
ZD
ZE
0.65
0.13
0.10
0.575
0.825
L
Lp
L1
0.50
0.60 0.15
5
3
1.00 0.20
P100GF-65-GAS
3
NOTE
Each lead centerline is located within 0.13 mm of
its true position at maximum material condition.
detail of lead end
0.30
b+
+
+
30
50
1
100 31
51
81
80
100-PIN PLASTIC LQFP (14x20)
CHAPTER 31 PACKAGE DRAWINGS
User’s Manual U17894EJ7V0UD
890
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
S
y
e
Sxb M
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
D
E
A3
S
0.125
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
14.00±0.20
14.00±0.20
16.00±0.20
16.00±0.20
1.60 MAX.
0.10±0.05
1.40±
+
+
+
0.05
0.25
c
e
x
θ
θ
y
ZD
ZE
0.50
0.08
0.08
1.00
1.00
L
Lp
L1
0.50
0.60±0.15
1.00±0.20
P100GC-50-UEU-1
NEC Electronics Corporation 2007
3°3°
5°
detail of lead end
0.20 0.07
0.075
0.025
0.03
b
25
50
1
100 26
51
75
76
User’s Manual U17894EJ9V0UD 891
CHAPTER 32 RECOMMENDED SOLDERING CONDITIONS
These products should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Caution For soldering methods and conditions other than those recommended below, contact an NEC
Electronics sales representative.
Table 32-1. Surface Mounting Type Soldering Conditions (1/2)
• 100-pin plastic LQFP (14 × 20)
μ
PD78F1162GF-GAS-AX,
μ
PD78F1162AGF-GAS-AX,
μ
PD78F1162AGF(A)-GAS-AX,
μ
PD78F1163GF-GAS-AX,
μ
PD78F1163AGF-GAS-AX,
μ
PD78F1163AGF(A)-GAS-AX,
μ
PD78F1164GF-GAS-AX,
μ
PD78F1164AGF-GAS-AX,
μ
PD78F1164AGF(A)-GAS-AX,
μ
PD78F1165GF-GAS-AX,
μ
PD78F1165AGF-GAS-AX,
μ
PD78F1165AGF(A)-GAS-AX,
μ
PD78F1166GF-GAS-AX,
μ
PD78F1166AGF-GAS-AX,
μ
PD78F1166AGF(A)-GAS-AX,
μ
PD78F1167GF-GAS-AX,
μ
PD78F1167AGF-GAS-AX,
μ
PD78F1167AGF(A)-GAS-AX,
μ
PD78F1168GF-GAS-AX,
μ
PD78F1168AGF-GAS-AX,
μ
PD78F1168AGF(A)-GAS-AX
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),
Count: 3 times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for
10 to 72 hours)
IR60-107-3
Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature), Exposure
limit: 7 daysNote (after that, prebake at 125°C for 10 to 72 hours)
WS60-107-1
Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) −
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
CHAPTER 32 RECOMMENDED SOLDERING CONDITIONS
User’s Manual U17446EJ3V1UD
892
Table 32-1. Surface Mounting Type Soldering Conditions (2/2)
• 100-pin plastic LQFP (14 × 14)
μ
PD78F1162GC-UEU-AX,
μ
PD78F1162AGC-UEU-AX,
μ
PD78F1162AGC(A)-UEU-AX,
μ
PD78F1163GC-UEU-AX,
μ
PD78F1163AGC-UEU-AX,
μ
PD78F1163AGC(A)-UEU-AX,
μ
PD78F1164GC-UEU-AX,
μ
PD78F1164AGC-UEU-AX,
μ
PD78F1164AGC(A)-UEU-AX,
μ
PD78F1165GC-UEU-AX,
μ
PD78F1165AGC-UEU-AX,
μ
PD78F1165AGC(A)-UEU-AX,
μ
PD78F1166GC-UEU-AX,
μ
PD78F1166AGC-UEU-AX,
μ
PD78F1166AGC(A)-UEU-AX,
μ
PD78F1167GC-UEU-AX,
μ
PD78F1167AGC-UEU-AX,
μ
PD78F1167AGC(A)-UEU-AX,
μ
PD78F1168GC-UEU-AX,
μ
PD78F1168AGC-UEU-AX,
μ
PD78F1168AGC(A)-UEU-AX
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),
Count: 3 times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for
10 to 72 hours)
IR60-107-3
Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) −
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
User’s Manual U17894EJ9V0UD 893
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for the development of systems that employ the 78K0R/KG3.
Figure A-1 shows the development tool configuration.
• Support for PC98-NX series
Unless otherwise specified, products supported by IBM PC/ATTM compatibles are compatible with PC98-NX
series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles.
• WindowsTM
Unless otherwise specified, “Windows” means the following OSs.
• Windows 98
• Windows NTTM
• Windows 2000
• Windows XP
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U17894EJ9V0UD
894
Figure A-1. Development Tool Configuration (1/2)
(1) When using the in-circuit emulator QB-78K0RKX3
Language processing software
• Assembler package
• C compiler package
• Device fileNote 1
Debugging software
• Integrated debuggerNote 3
• System simulator
Host machine
(PC or EWS)
QB-78K0RKX3Note 3
Emulation probe
Target system
Flash memory
programmerNote 3
Flash memory
write adapter
Flash memory
• Software package
• Project manager
Software package
Flash memory
write environment
Control software
(Windows only)Note 2
Power supply unit
Note 3
USB interface cableNote 3
Notes 1. Download the device file for 78K0R/KG3 (DF781188) from the download site for development tools
(http://www.necel.com/micro/ods/eng/index.html).
2. The project manager PM+ is included in the assembler package.
The PM+ is only used for Windows.
3. In-circuit emulator QB-78K0RKX3 is supplied with integrated debugger ID78K0R-QB, on-chip debug
emulator with programming function QB-MINI2, power supply unit, and USB interface cable. Any other
products are sold separately.
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U17894EJ9V0UD 895
Figure A-1. Development Tool Configuration (2/2)
(2) When using the on-chip debug emulator with programming function QB-MINI2
Language processing software
• Assembler package
• C compiler package
• Device file
Note 1
Debugging software
• Integrated debugger
Note 1
• System simulator
Host machine
(PC or EWS)
USB interface cable
Note 3
QB-MINI2
Note 3
Target connector
Target system
• Software package
• Project manager
Software package
<When using QB-MINI2 as
a flash memory programmer>
Control software
(Windows only)
Note 2
<When using QB-MINI2 as
an on-chip degug emulator>
Connection cable
(16-pin cable)
Note 3
QB-MINI2
Note 3
Connection cable
(16-pin cable)
Note 3
Notes 1. Download the device file for 78K0R/KG3 (DF781188) and the integrated debugger (ID78K0R-QB) from
the download site for development tools (http://www.necel.com/micro/ods/eng/index.html).
2. The project manager PM+ is included in the assembler package.
The PM+ is only used for Windows.
3. On-chip debug emulator QB-MINI2 is supplied with USB interface cable, connection cables (10-pin
cable and 16-pin cable), and 78K0-OCD board. Any other products are sold separately. In addition,
download the software for operating the QB-MINI2 from the download site for MINICUBE2
(http://www.necel.com/micro/en/development/asia/minicube2/minicube2.html).
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U17894EJ9V0UD
896
A.1 Software Package
Development tools (software) common to the 78K0R microcontrollers are combined in
this package.
SP78K0R
78K0R Series software package
Part number:
μ
S××××SP78K0R
Remark ×××× in the part number differs depending on the host machine and OS used.
μ
S××××SP78K0R
×××× Host Machine OS Supply Medium
AB17 Windows (Japanese version)
BB17
PC-9800 series,
IBM PC/AT compatibles Windows (English version)
CD-ROM
A.2 Language Processing Software
This assembler converts programs written in mnemonics into object codes executable
with a microcontroller.
This assembler is also provided with functions capable of automatically creating symbol
tables and branch instruction optimization.
This assembler should be used in combination with a device file (DF781188).
<Precaution when using RA78K0R in PC environment>
This assembler package is a DOS-based application. It can also be used in Windows,
however, by using the Project Manager (included in assembler package) on Windows.
RA78K0R
Assembler package
Part number:
μ
S××××RA78K0R
This compiler converts programs written in C language into object codes executable with
a microcontroller.
This compiler should be used in combination with an assembler package and device file
(both sold separately).
<Precaution when using CC78K0R in PC environment>
This C compiler package is a DOS-based application. It can also be used in Windows,
however, by using the Project Manager (included in assembler package) on Windows.
CC78K0R
C compiler package
Part number:
μ
S××××CC78K0R
This file contains information peculiar to the device.
This device file should be used in combination with a tool (RA78K0R, CC78K0R, SM+ for
78K0R, and ID78K0R-QB) (all sold separately).
The corresponding OS and host machine differ depending on the tool to be used.
DF781188Note
Device file
Part number:
μ
S××××DF781188
Note The DF781188 can be used in common with the RA78K0R, CC78K0R, SM+ for 78K0R, and ID78K0R-QB.
Download the DF781188 from the download site for development tools
(http://www.necel.com/micro/ods/eng/index.html).
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U17894EJ9V0UD 897
Remark ×××× in the part number differs depending on the host machine and OS used.
μ
S××××RA78K0R
μ
S××××CC78K0R
×××× Host Machine OS Supply Medium
AB17 Windows (Japanese version)
BB17
PC-9800 series,
IBM PC/AT compatibles Windows (English version)
CD-ROM
μ
S××××DF781188
×××× Host Machine OS Supply Medium
AB13 Windows (Japanese version)
BB13
PC-9800 series,
IBM PC/AT compatibles Windows (English version)
3.5-inch 2HD FD
A.3 Control Software
PM+
Project manager
This is control software designed to enable efficient user program development in the
Windows environment. All operations used in development of a user program, such as
starting the editor, building, and starting the debugger, can be performed from the project
manager.
<Caution>
The project manager is included in the assembler package (RA78K0R).
It can only be used in Windows.
A.4 Flash Memory Programming Tools
A.4.1 When using flash memory programmers PG-FP5, FL-PR5, PG-FP4 and FL-PR4
PG-FP5, FL-PR5, PG-FP4, FL-PR4
Flash memory programmer
Flash memory programmer dedicated to microcontrollers with on-chip flash
memory.
FA-78F1168GF-GAS-RX (RoHS supported),
FA-78F1168GC-UEU-RX (RoHS supported)
Flash memory programming adapter
Flash memory programming adapter used connected to the flash memory
programmer for use.
• FA-78F1168GF-GAS-RX: 100-pin plastic LQFP (GF-GAS type)
• FA-78F1168GC-UEU-RX: 100-pin plastic LQFP (GC-UEU type)
Remark The FL-PR4, FL-PR5, FA-78F1168GF-GAS-RX, and FA-78F1168GC-UEU-RX are a product of Naito
Densei Machida Mfg. Co., Ltd.
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U17894EJ9V0UD
898
A.4.2 When using on-chip debug emulator with programming function QB-MINI2
QB-MINI2
On-chip debug emulator with
programming function
This is a flash memory programmer dedicated to microcontrollers with on-chip flash
memory. It is available also as on-chip debug emulator which serves to debug hardware
and software when developing application systems using the 78K0R.
The QB-MINI2 is supplied with a USB interface cable and connection cables (10-pin
cable and 16-pin cable), and the 78K0-OCD board. To use 78K0R/KG3, use USB
interface cable and 16-pin connection cable.
Remark Download the software for operating the QB-MINI2 from the download site for MINICUBE2
(http://www.necel.com/micro/en/development/asia/minicube2/minicube2.html).
A.5 Debugging Tools (Hardware)
A.5.1 When using in-circuit emulator QB-78K0RKX3
QB-78K0KX3
In-circuit emulator
This in-circuit emulator serves to debug hardware and software when developing application
systems using the 78K0R/Kx3. It supports to the integrated debugger (ID78K0R-QB). This
emulator should be used in combination with a power supply unit and emulation probe, and the
USB is used to connect this emulator to the host machine.
QB-144-CA-01
Check pin adapter
This check pin adapter is used in waveform monitoring using the oscilloscope, etc.
QB-144-EP-02S
Emulation probe
This emulation probe is flexible type and used to connect the in-circuit emulator and target
system.
QB-100GF-EA-04T,
QB-100GC-EA-01T
Exchange adapter
This exchange adapter is used to perform pin conversion from the in-circuit emulator to target
connector.
• QB-100GF-EA-04T: 100-pin plastic LQFP (GF-GAS type)
• QB-100GC-EA-01T: 100-pin plastic LQFP (GC-UEU type)
QB-100GF-YS-01T,
QB-100GC-YS-01T
Space adapter
This space adapter is used to adjust the height between the target system and in-circuit emulator.
• QB-100GF-YS-01T: 100-pin plastic LQFP (GF-GAS type)
• QB-100GC-YS-01T: 100-pin plastic LQFP (GC-UEU type)
QB-100GF-YQ-01T,
QB-100GC-YQ-01T
YQ connector
This YQ connector is used to connect the target connector and exchange adapter.
• QB-100GF-YQ-01T: 100-pin plastic LQFP (GF-GAS type)
• QB-100GC-YQ-01T: 100-pin plastic LQFP (GC-UEU type)
QB-100GF-HQ-03T,
QB-100GC-HQ-01T
Mount adapter
This mount adapter is used to mount the target device with socket.
• QB-100GF-HQ-03T: 100-pin plastic LQFP (GF-GAS type)
• QB-100GC-HQ-01T: 100-pin plastic LQFP (GC-UEU type)
QB-100GF-NQ-01T,
QB-100GC-NQ-01T
Target connector
This target connector is used to mount on the target system.
• QB-100GF-NQ-01T: 100-pin plastic LQFP (GF-GAS type)
• QB-100GC-NQ-01T: 100-pin plastic LQFP (GC-UEU type)
Remarks 1. The QB-78K0RKX3 is supplied with a power supply unit and USB interface cable. As control
software, integrated debugger ID78K0R-QB and on-chip debug emulator with programming function
QB-MINI2 are supplied.
2. The packed contents differ depending on the part number, as follows.
Packed Contents
Part Number
In-Circuit Emulator Emulation Probe Exchange Adapter YQ Connector Target Connector
QB-78K0RKX3-ZZZ None
QB-78K0RKX3-T100GF QB-100GF-EA-04T QB-100GF-YQ-01T QB-100GF-NQ-01T
QB-78K0RKX3-T100GC
QB-78K0RKX3
QB-144-EP-02S
QB-100GC-EA-01T QB-100GC-YQ-01T QB-100GC-NQ-01T
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U17894EJ9V0UD 899
A.5.2 When using on-chip debug emulator with programming function QB-MINI2
QB-MINI2
On-chip debug emulator with
programming function
This on-chip debug emulator serves to debug hardware and software when developing
application systems using the 78K0R microcontrollers. It is available also as flash
memory programmer dedicated to microcontrollers with on-chip flash memory.
The QB-MINI2 is supplied with a USB interface cable and connection cables (10-pin
cable and 16-pin cable), and the 78K0-OCD board. To use 78K0R/KG3, use USB
interface cable and 16-pin connection cable.
Remark Download the software for operating the QB-MINI2 from the download site for MINICUBE2
(http://www.necel.com/micro/en/development/asia/minicube2/minicube2.html).
A.6 Debugging Tools (Software)
SM+ for 78K0R is Windows-based software.
It is used to perform debugging at the C source level or assembler level while simulating
the operation of the target system on a host machine.
Use of SM+ for 78K0R allows the execution of application logical testing and
performance testing on an independent basis from hardware development, thereby
providing higher development efficiency and software quality.
SM+ for 78K0R should be used in combination with the device file (DF781188).
SM+ for 78K0R
System simulator
Part number:
μ
S××××SM781000
This debugger supports the in-circuit emulators for the 78K0R microcontrollers. The
ID78K0R-QB is Windows-based software.
It has improved C-compatible debugging functions and can display the results of tracing
with the source program using an integrating window function that associates the source
program, disassemble display, and memory display with the trace result.
ID78K0R-QB should be used in combination with the device file.
ID78K0R-QB
Integrated debugger
Part number:
μ
S××××ID78K0R-QB
Remark ×××× in the part number differs depending on the host machine and OS used.
μ
S××××SM781000
μ
S××××ID78K0R-QB
×××× Host Machine OS Supply Medium
AB17 Windows (Japanese version)
BB17
PC-9800 series,
IBM PC/AT compatibles Windows (English version)
CD-ROM
User’s Manual U17894EJ9V0UD
900
APPENDIX B LIST OF CAUTIONS
This appendix lists the cautions described in this document.
“Classification (hard/soft)” in the table is as follows.
Hard: Cautions for microcontroller internal/external hardware
Soft: Cautions for software such as register settings or programs
(1/35)
Chapter
Classification
Function Details of
Function
Cautions Page
AVSS, EVSS0,
EVSS1, VSS
Make AVSS, EVSS0, and EVSS1 the same potential as VSS. pp.22,
23
EVDD0, EVDD1, VDD Make EVDD0 and EVDD1 the same potential as VDD. pp.22,
23
REGC Connect the REGC pin to VSS via a capacitor (0.47 to 1
μ
F). pp.22,
23
Chapter 1
Hard
Outline
P20/ANI0 to
P27/ANI7,
P150/ANI8 to
P157/ANI15
P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 are set as analog inputs in the
order of P157/ANI15, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port
configuration register (ADPC). When using P20/ANI0 to P27/ANI7 and P150/ANI8 to
P157/ANI15 as analog inputs, start designing from P157/ANI15 (see 11.3 (6) A/D port
configuration register (ADPC) for details).
pp.22,
23
P02/SO10/TxD1,
P04/SCK10/
SCL10
To use P02/SO10/TxD1 and P04/SCK10/SCL10 as general-purpose ports, set serial
communication operation setting register 02 (SCR02) to the default status (0087H). In
addition, clear port output mode register 0 (POM0) to 00H.
p.36
P10/SCK00/EX24,
P12/SO00/TxD0/E
X26
To use P10/SCK00/EX24 and P12/SO00/TxD0/EX26 as general-purpose ports, set
serial communication operation setting register 00 (SCR00) to the default status
(0087H).
p.37
Soft
RTCCL, RTCDIV Do not enable outputting RTCCL and RTCDIV at the same time. p.37
ANI0/P20 to
ANI7/P27
ANI0/P20 to ANI7/P27 are set in the digital input (general-purpose port) mode after
release of reset.
p.37
P40/TOOL0 The function of the P40/TOOL0 pin varies as described in (a) to (c) below.
In the case of (b) or (c), make the specified connection.
(a) In normal operation mode and when on-chip debugging is disabled (OCDENSET =
0) by an option byte (000C3H)
=> Use this pin as a port pin (P40).
(b) In normal operation mode and when on-chip debugging is enabled (OCDENSET =
1) by an option byte (000C3H)
=> Connect this pin to EVDD0 or EVDD1 via an external resistor, and always input a
high level to the pin before reset release.
(c) When on-chip debug function is used, or in write mode of flash memory
programmer
=> Use this pin as TOOL0. Directly connect this pin to the on-chip debug
emulator or a flash memory programmer, or pull it up by connecting it to EVDD0
or EVDD1 via an external resistor.
p.39
ANI8/P150 to
ANI15/P157
ANI8/P150 to ANI15/P157 are set in the digital input (general-purpose port) mode after
release of reset.
p.44
Chapter 2
Hard
Pin
functions
REGC Keep the wiring length as short as possible for the broken-line part in the above figure. p.45
APPENDIX B LIST OF CAUTIONS
User’s Manual U17894EJ9V0UD 901
(2/35)
Chapter
Classification
Function Details of
Function
Cautions Page
Set PMC only once during the initial settings prior to operating the DMA controller.
Rewriting PMC other than during the initial settings is prohibited.
p.65
After setting PMC, wait for at least one instruction and access the mirror area. p.65
PMC: Processor
mode control
register
When the
μ
PD78F1162 or 78F1162A is used, be sure to set bit 0 (MAA) of this
register to 0.
p.65
It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for
fetching instructions or as a stack area.
p.65
p.65
Internal data
memory space
While using the self-programming function, the area of FFE20H to FFEFFH cannot
be used as a stack memory. Furthermore, the areas of FCF00H to FD6FFH and
F8700H to F8EFFH also cannot be used with the
μ
PD78F1166 and 78F1166A, and
μ
PD78F1168 and 78F1168A, respectively.
pp.66,
SFR: Special
function register
area
Do not access addresses to which SFRs are not assigned.
79
Memory
space
2nd SFR:
Extended
special function
register
Do not access addresses to which the 2nd SFR is not assigned. pp.66,
85
Since reset signal generation makes the SP contents undefined, be sure to initialize
the SP before using the stack.
p.75
The values of the stack pointer must be set to even numbers. If odd numbers are
specified, the least significant bit is automatically cleared to 0.
p.75
It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space as a
stack area.
p.75
SP: Stack
pointer
While using the self-programming function, the area of FFE20H to FFEFFH cannot
be used as a stack memory. Furthermore, the areas of FCF00H to FD6FFH and
F8700H to F8EFFH also cannot be used with the
μ
PD78F1166 and 78F1166A, and
μ
PD78F1168 and 78F1168A, respectively.
p.75
Chapter 3
Soft
Processor
registers
General-purpose
registers
It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for
fetching instructions or as a stack area.
p.76
P01/TO00 To use P01/TO00 as a general-purpose port, set bit 0 (TO00) of timer output register
0 (TO0) and bit 0 (TOE00) of timer output enable register 0 (TOE0) to “0”, which is
the same as their default status setting.
p.108
P02/SO10/TxD1,
P03/SI10/RxD1/
SDA10,
P04/SCK10/
SCL10
To use P02/SO10/TxD1, P03/SI10/RxD1/SDA10, or P04/SCK10/SCL10 as a
general-purpose port, note the serial array unit 0 setting. For details, refer to the
following tables.
• Table 13-7 Relationship Between Register Settings and Pins (Channel 2 of Unit 0:
CSI10, UART1 Transmission, IIC10)
• Table 13-8 Relationship Between Register Settings and Pins (Channel 3 of Unit 0:
UART1 Reception)
p.108
Chapter 4
Soft
Port
functions
P10/SCK00/
EX24,
P11/SI00/RxD0/
EX25,
P12/SO00/TxD0/
EX26,
P13/TxD3/EX27,
P14/RxD3/EX28
To use P10/SCK00/EX24, P11/SI00/RxD0/EX25, P12/SO00/TxD0/EX26,
P13/TxD3/EX27, or P14/RxD3/EX28 as a general-purpose port, note the serial array
unit setting. For details, refer to the following tables.
• Table 13-5 Relationship Between Register Settings and Pins (Channel 0 of Unit 0:
CSI00, UART0 Transmission)
• Table 13-6 Relationship Between Register Settings and Pins (Channel 1 of Unit 0:
CSI01, UART0 Reception)
• Table 13-11 Relationship Between Register Settings and Pins (Channel 2 of Unit 1:
UART3 Transmission)
• Table 13-12 Relationship Between Register Settings and Pins (Channel 3 of Unit 1:
UART3 Reception)
p.114
APPENDIX B LIST OF CAUTIONS
User’s Manual U17894EJ9V0UD
902
(3/35)
Chapter
Classification
Function Details of
Function
Cautions Page
P16/TI01/TO01/
INTP5/EX30,
P17/TI02/TO02/
EX31
To use P16/TI01/TO01/INTP5/EX30 or P17/TI02/TO02/EX31 as a general-purpose
port, set bits 1 and 2 (TO01, TO02) of timer output register 0 (TO0) and bits 1 and 2
(TOE01, TOE02) of timer output enable register 0 (TOE0) to “0”, which is the same
as their default status setting.
p.114
P15/RTCDIV/
RTCCL/EX29
To use P15/RTCDIV/RTCCL/EX29 as a general-purpose port, set bit 4 (RCLOE0) of
real-time counter control register 0 (RTCC0) and bit 6 (RCLOE2) of real-time counter
control register 2 (RTCC2) to “0”, which is the same as their default status settings.
p.114
Soft
Port 1 Do not enable outputting other alternate functions when the external expansion
output (address bus) function is used.
p.114
Hard
Port 2 See 2.2.15 AVREF0 for the voltage to be applied to the AVREF0 pin when using port 2 as
a digital I/O.
p.120
P31/TI03/TO03/
INTP4
To use P31/TI03/TO03/INTP4 as a general-purpose port, set bit 3 (TO03) of timer
output register 0 (TO0) and bit 3 (TOE03) of timer output enable register 0 (TOE0) to
“0”, which is the same as their default status setting.
p.122
P30/RTC1HZ/
INTP3
To use P30/RTC1HZ/INTP3 as a general-purpose port, set bit 5 (RCLOE1) of real-
time counter control register 0 (RTCC0) to “0”, which is the same as its default status
setting.
p.122
P40/TOOL0,
P41/TOOL1
When a tool is connected, the P40 pin cannot be used as a port pin.
When the on-chip debug function is used, P41 pin can be used as follows by the
mode setting on the debugger.
1-line mode: can be used as a port (P41).
2-line mode: used as a TOOL1 pin and cannot be used as a port (P41).
p.123
P43/SCK01,
P44/SI01,
P45/SO01
To use P43/SCK01, P44/SI01, or P45/SO01 as a general-purpose port, note the
serial array unit 0 setting. For details, refer to Table 13-6 Relationship Between
Register Settings and Pins (Channel 1 of Unit 0: CSI01, UART0 reception).
p.123
P42/TI04/TO04,
P46/INTP1/TI05/
TO05
To use P42/TI04/TO04 or P46/INTP1/TI05/TO05 as a general-purpose port, set bits 4
and 5 (TO04, TO05) of timer output register 0 (TO0) and bits 4 and 5 (TOE04,
TOE05) of timer output enable register 0 (TOE0) to “0”, which is the same as their
default status setting.
p.123
Soft
P60/SCL0,
P61/SDA0
Stop the operation of serial interface IIC0 when using P60/SCL0 and P61/SDA0 as
general-purpose ports.
p.134
Hard
P110, P111 See 2.2.16 AVREF1 for the voltage to be applied to the AVREF1 pin when using P110
and P111 as digital I/O.
p.139
P121 to P124 The function setting on P121 to P124 is available only once after the reset release.
The port once set for connection to an oscillator cannot be used as an input port
unless the reset is performed.
p.140
P131/TI06/TO06 To use P131/TI06/TO06 as a general-purpose port, set bit 6 (TO06) of timer output
register 0 (TO0) and bit 6 (TOE06) of timer output enable register 0 (TOE0) to “0”,
which is the same as their default status setting.
p.143
P142/SCK20/
SCL20,
P143/SI20/RxD2
/SDA20,
P144/SO20/
TxD2
To use P142/SCK20/SCL20, P143/SI20/RxD2/SDA20, or P144/SO20/TxD2 as a
general-purpose port, note the serial array unit 1 setting. For details, refer to the
following tables.
• Table 13-9 Relationship Between Register Settings and Pins (Channel 0 of Unit 1:
CSI20, UART2 Transmission, IIC20)
• Table 13-10 Relationship Between Register Settings and Pins (Channel 1 of Unit 1:
UART2 Reception)
p.145
Chapter 4
Soft
Port
functions
P145/TI07/TO07 To use P145/TI07/TO07 as a general-purpose port, set bit 7 (TO07) of timer output
register 0 (TO0) and bit 7 (TOE07) of timer output enable register 0 (TOE0) to “0”,
which is the same as their default status setting.
p.145
APPENDIX B LIST OF CAUTIONS
User’s Manual U17894EJ9V0UD 903
(4/35)
Chapter
Classification
Function Details of
Function
Cautions Page
Soft
P140/PCLBUZ0/
INTP6,
P141/PCLBUZ1/
INTP7
To use P140/PCLBUZ0/INTP6 or P141/PCLBUZ1/INTP7 as a general-purpose port,
set bit 7 of clock output select registers 0 and 1 (CKS0, CKS1) to “0”, which is the
same as their default status settings.
p.145
Hard
Port 15 See 2.2.15 AVREF0 for the voltage to be applied to the AVREF0 pin when using port 15
as a digital I/O.
p.149
PM0 to PM8,
PM11 to PM15:
Port mode
registers
Be sure to set bit 7 of PM0, bits 2 to 7 of PM3, bits 2 to 7 of PM11, bits 1 to 7 of
PM12, bits 2 to 7 of PM13, and bits 6 and 7 of PM14 to “1”. And be sure to set bit 0
of PM13 to “0”.
p.151
Set the channel used for A/D conversion to the input mode by using port mode
registers 2 and 15 (PM2, PM15).
p.156
Do not set the pin set by ADPC as digital I/O by analog input channel specification
register (ADS).
p.156
ADPC: A/D port
configuration
register
P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 are set as analog inputs in the
order of P157/ANI15, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port
configuration register (ADPC). When using P20/ANI0 to P27/ANI7 and P150/ANI8 to
P157/ANI15 as analog inputs, start designing from P157/ANI15.
p.156
Chapter 4
Soft
Port
functions
1-bit
manipulation
instruction for
port register n
(Pn)
When a 1-bit manipulation instruction is executed on a port that provides both input
and output functions, the output latch value of an input port that is not subject to
manipulation may be written in addition to the targeted bit. Therefore, it is
recommended to rewrite the output latch when switching a port from input mode to
output mode.
p.163
PER1:
Peripheral
enable register 1
When setting the external bus interface, be sure to set EXBEN to 1 first. If EXBEN =
0, writing to a control register of the external bus interface is ignored, and, even if the
register is read, only the default value is read (except for port mode registers 0, 1, 5,
6, 7, 8 (PM0, PM1, PM5, PM6, PM7, PM8) and port registers 0, 1, 5, 6, 7, 8 (P0, P1,
P5, P6, P7, P8)).
p.170
Chapter 5
Soft
External
bus
interface
Number of
instruction
execution clocks
and instruction
wait clocks for
fetch access
The flash memory and external memory are located in consecutive spaces, but start
fetching in the external memory space by using a branch instruction (CALL, BR) in
the flash memory or RAM memory.
p.174
CMC can be written only once after reset release, by an 8-bit memory manipulation
instruction.
p.191
After reset release, set CMC before X1 or XT1 oscillation is started as set by the
clock operation status control register (CSC).
p.191
Be sure to set AMPH to 1 if the X1 clock oscillation frequency exceeds 10 MHz. p.191
CMC: Clock
operation mode
control register
It is recommended to set the default value (00H) to CMC after reset release, even
when the register is used at the default value, in order to prevent malfunctioning
during a program loop.
p.191
After reset release, set the clock operation mode control register (CMC) before
starting X1 oscillation as set by MSTOP or XT1 oscillation as set by XTSTOP.
p.192
To start X1 oscillation as set by MSTOP, check the oscillation stabilization time of the
X1 clock by using the oscillation stabilization time counter status register (OSTC).
p.192
Chapter 6
Soft
Clock
generator
CSC: Clock
operation status
control register
Do not stop the clock selected for the CPU/peripheral hardware clock (fCLK) with the
OSC register.
p.192
APPENDIX B LIST OF CAUTIONS
User’s Manual U17894EJ9V0UD
904
(5/35)
Chapter
Classification
Function Details of
Function
Cautions Page
CSC: Clock
operation status
control register
The setting of the flags of the register to stop clock oscillation (invalidate the external
clock input) and the condition before clock oscillation is to be stopped are as follows.
(See Table 6-2.)
p.193
After the above time has elapsed, the bits are set to 1 in order from MOST8 and
remain 1.
p.194
Soft
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. In the following cases, set the oscillation stabilization time of OSTS to
the value greater than or equal to the count value which is to be checked by the
OSTC register.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or
subsystem clock is being used as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after the STOP mode is released.)
p.194
Hard
OSTC:
Oscillation
stabilization time
counter status
register
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
p.194
To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS
register before executing the STOP instruction.
p.196
Setting the oscillation stabilization time to 20
μ
s or less is prohibited. p.196
To change the setting of the OSTS register, be sure to confirm that the counting
operation of the OSTC register has been completed.
p.196
Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
p.196
Soft
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS.
In the following cases, set the oscillation stabilization time of OSTS to the value
greater than or equal to the count value which is to be checked by the OSTC register.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or
subsystem clock is being used as the CPU clock.
• If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after the STOP mode is released.)
p.196
Hard
OSTS:
Oscillation
stabilization time
select register
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
p.196
Be sure to set bit 3 to 1. p.198
Soft
The clock set by CSS, MCM0, and MDIV2 to MDIV0 is supplied to the CPU and
peripheral hardware. If the CPU clock is changed, therefore, the clock supplied to
peripheral hardware (except the real-time counter, clock output/buzzer output, and
watchdog timer) is also changed at the same time. Consequently, stop each
peripheral function when changing the CPU/peripheral operating hardware clock.
p.198
Chapter 6
Hard
Clock
generator
CKC: System
clock control
register
If the peripheral hardware clock is used as the subsystem clock, the operations of the
A/D converter and IIC0 are not guaranteed. For the operating characteristics of the
peripheral hardware, refer to the chapters describing the various peripheral hardware
as well as CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD
PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS).
p.198
APPENDIX B LIST OF CAUTIONS
User’s Manual U17894EJ9V0UD 905
(6/35)
Chapter
Classification
Function Details of
Function
Cautions Page
PER0, PER1:
Peripheral enable
registers 0, 1
Be sure to clear bit 1 of the PER0 register and bits 1 to 7 of the PER1 register to 0. pp.199,
200
OSMC can be written only once after reset release, by an 8-bit memory manipulation
instruction.
p.201
Write “1” to FSEL before the following two operations.
• Changing the clock prior to dividing fCLK to a clock other than fIH.
• Operating the DMA controller.
p.201
The CPU waits when “1” is written to the FSEL flag.
Interrupt requests issued during a wait will be suspended.
The wait time is 16.6
μ
s to 18.5
μ
s when fCLK = fIH, and 33.3
μ
s to 36.9
μ
s when fCLK =
fIH/2. However, counting the oscillation stabilization time of fX can continue even
while the CPU is waiting.
p.201
To increase fCLK to 10 MHz or higher, set FSEL to “1”, then change fCLK after two or
more clocks have elapsed. Use the external bus interface two clock cycles after
setting FSEL to 1.
p.201
OSMC:
Operation speed
mode control
register
Flash memory can be used at a frequency of 10 MHz or lower if FSEL is 1. p.201
The frequency will vary if the temperature and VDD pin voltage change after accuracy
adjustment.
Moreover, if the HIOTRM register is set to any value other than the initial value (10H),
the oscillation accuracy of the internal high-speed oscillation clock may exceed 8
MHz±5%, depending on the subsequent temperature and VDD voltage change, or
HIOTRM register setting. When the temperature and VDD voltage change, accuracy
adjustment must be executed regularly or before the frequency accuracy is required.
p.202
Soft
Clock
generator
HIOTRM:
Internal high-
speed oscillator
trimming register
The internal high-speed oscillation frequency becomes faster/slower by
increasing/decreasing the HIOTRM value to a value larger/smaller than a certain
value. A reversal, such as the frequency becoming slower/faster by
increasing/decreasing the HIOTRM value does not occur.
p.203
When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed
by the broken lines in the Figures 6-10 and 6-11 to avoid an adverse effect from
wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a
signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing power
consumption.
p.205
X1/XT1
oscillator
−
When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with
XT1, resulting in malfunctioning.
p.206
If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application
until the voltage reaches 1.8 V, input a low level to the RESET pin from power
application until the voltage reaches 1.8 V, or set the LVI default start function
stopped by using the option byte (LVIOFF = 0) (see Figure 6-14). By doing so, the
CPU operates with the same timing as <2> and thereafter in Figure 6-13 after reset
release by the RESET pin.
p.210
Chapter 6
Hard
Clock
generator
operation
when
power
supply
voltage is
turned on
When LVI
default start
function stopped
is set (option
byte: LVIOFF =
1)
It is not necessary to wait for the oscillation stabilization time when an external clock
input from the EXCLK pin is used.
p.210
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A voltage oscillation stabilization time is required after the supply voltage reaches
1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.07 V (TYP.) within
the power supply oscillation stabilization time, the power supply oscillation
stabilization time is automatically generated before reset processing.
p.211
Hard
Clock
generator
operation
when
power
supply
voltage is
turned on
When LVI
default start
function enabled
is set (option
byte: LVIOFF =
0)
It is not necessary to wait for the oscillation stabilization time when an external clock
input from the EXCLK pin is used.
p.211
X1/P121,
X2/EXCLK/P122
The X1/P121 and X2/EXCLK/P122 pins are in the input port mode after a reset
release.
p.212
The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction. Therefore, it is necessary to also set the value of the
OSCSELS bit at the same time. For OSCSELS bit, see 6.6.3 Example of controlling
subsystem clock.
p.212
X1 clock
Set the X1 clock after the supply voltage has reached the operable voltage of the
clock to be used (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD
PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS)).
p.212
The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction. Therefore, it is necessary to also set the value of the
OSCSELS bits at the same time. For OSCSELS bits, see 6.6.3 Example of
controlling subsystem clock.
p.213
External main
system clock
Set the external main system clock after the supply voltage has reached the operable
voltage of the clock to be used (see CHAPTER 29 ELECTRICAL SPECIFICATIONS
(STANDARD PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A)
GRADE PRODUCTS)).
p.213
Be sure to clear bit 1 of the PER0 register and bits 1 to 7 of the PER1 register to 0. p.214
Controlling
high-speed
system
clock
High-speed
system clock Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition,
stop peripheral hardware that is operating on the high-speed system clock.
p.215
If switching the CPU/peripheral hardware clock from the high-speed system clock to
the internal high-speed oscillation clock after restarting the internal high-speed
oscillation clock, do so after 10
μ
s or more have elapsed.
If the switching is made immediately after the internal high-speed oscillation clock is
restarted, the accuracy of the internal high-speed oscillation cannot be guaranteed
for 10
μ
s.
p.216
Controlling
internal
high-speed
oscillation
clock
Internal high-
speed oscillation
clock
Be sure to confirm that MCS = 1 or CLS = 1 when setting HIOSTOP to 1. In addition,
stop peripheral hardware that is operating on the internal high-speed oscillation clock.
p.217
Soft
XT1/P123,
XT2/P124
The XT1/P123 and XT2/P124 pins are in the input port mode after a reset release. p.217
Chapter 6
Hard
Subsystem
clock
control Subsystem clock When the subsystem clock is used as the CPU clock, the subsystem clock is also
supplied to the peripheral hardware (except the real-time counter, clock
output/buzzer output, and watchdog timer). At this time, the operations of the A/D
converter and IIC0 are not guaranteed. For the operating characteristics of the
peripheral hardware, refer to the chapters describing the various peripheral hardware
as well as CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD
PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS).
pp.217,
218
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Function Details of
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The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction.
Therefore, it is necessary to also set the value of the EXCLK and OSCSEL bits at the
same time. For EXCLK and OSCSEL bits, see 6.6.1 (1) Example of setting
procedure when oscillating the X1 clock or 6.6.1 (2) Example of setting procedure
when using the external main system clock.
p.217
Be sure to confirm that CLS = 0 when setting XTSTOP to 1. In addition, stop the
peripheral hardware if it is operating on the subsystem clock.
p.218
Subsystem
clock
control
Subsystem clock
The subsystem clock oscillation cannot be stopped using the STOP instruction. p.218
pp.221
Chapter 6
Soft
CPU clock
status
transition
− Set the clock after the supply voltage has reached the operable voltage of the clock
to be set (see CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD
PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE
PRODUCTS)).
222, 224
TCR0n:
Timer/counter
register 0n
The count value is not captured to TDR0n even when TCR0n is read. p.233
TDR0n: Timer
data register 0n
TDR0n does not perform a capture operation even if a capture trigger is input, when
it is set to the compare function.
p.235
When setting the timer array unit, be sure to set TAU0EN to 1 first. If TAU0EN = 0,
writing to a control register of the timer array unit is ignored, and all read values are
default values (except for timer input select register 0 (TIS0), input switch control
register (ISC), noise filter enable register 1 (NFEN1), port mode registers 0, 1, 3, 4,
13, 14 (PM0, PM1, PM3, PM4, PM13, PM14), and port registers 0, 1, 3, 4, 13, 14
(P0, P1, P3, P4, P13, P14)).
p.237
PER0:
Peripheral
enable register 0
Be sure to clear bit 1 of the PER0 register to 0. p.237
TPS0: Timer
clock select
register 0
Be sure to clear bits 15 to 8 to “0”. p.238
TMR0n: Timer
mode register 0n
Be sure to clear bits 14, 13, 5, and 4 to “0”. p.239
Be sure to clear bits 15 to 8 to “0”. p.244
In the first cycle operation of count clock after writing TS0n, an error at a maximum of
one clock is generated since count start delays until count clock has been generated.
When the information on count start timing is necessary, an interrupt can be
generated at count start by setting MD0n0 = 1.
pp.245,
246
TS0: Timer
channel start
register 0
An input signal sampling error is generated since operation starts upon start trigger
detection (The error is one count clock when TI0n is used).
pp.247,
248
TT0: Timer
channel stop
register 0
Be sure to clear bits 15 to 8 to “0”. p.249
TOE0: Timer
output enable
register 0
Be sure to clear bits 15 to 8 to “0”. p.250
TO0: Timer
output register 0
Be sure to clear bits 15 to 8 to “0”. p.251
Chapter 7
Soft
Timer
array unit
TOL0: Timer
output level
register 0
Be sure to clear bits 15 to 8 to “0”. p.252
APPENDIX B LIST OF CAUTIONS
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TOM0: Timer
output mode
register 0
Be sure to clear bits 15 to 8 to “0”. p.253
ISC: Input switch
control register
Be sure to clear bits 7 to 2 to “0”. p.254
(1) Changing values set in registers TO0, TOE0, TOL0, and TOM0 during timer
operation
Since the timer operations (operations of TCR0n and TDR0n) are independent of the
TO0n output circuit and changing the values set in TO0, TOE0, TOL0, and TOM0
does not affect the timer operation, the values can be changed during timer
operation. To output an expected waveform from the TO0n pin by timer operation,
however, set TO0, TOE0, TOL0, and TOM0 to the values stated in the register
setting example of each operation.
When the values set in TOE0, TOL0, and TOM0 (except for TO0) are changed close
to the timer interrupt (INTTM0n), the waveform output to the TO0n pin may be
different depending on whether the values are changed immediately before or
immediately after the timer interrupt (INTTM0n) signal generation timing.
p.258
(2) Default level of TO0n pin and output level after timer operation start
The following figure shows the TO0n pin output level transition when writing has been
done in the state of TOE0n = 0 before port output is enabled and TOE0n = 1 is set
after changing the default level.
(a) When operation starts with TOM0n = 0 setting (toggle output)
The setting of TOL0n is invalid when TOM0n = 0. When the timer operation
starts after setting the default level, the toggle signal is generated and the output
level of TO0n pin is reversed.
(b) When operation starts with TOM0n = 1 setting (combination operation mode
(PWM output))
When TOM0n = 1, the active level is determined by TOL0n setting.
pp.259,
260
Channel output
(TO0n pin)
operation
(3) Operation of TO0n pin in combination operation mode (TOM0n = 1)
(a) When TOL0n setting has been changed during timer operation
When the TOL0n setting has been changed during timer operation, the setting
becomes valid at the generation timing of TO0n change condition. Rewriting
TOL0n does not change the output level of TO0n. The following figure shows the
operation when the value of TOL0n has been changed during timer operation
(TOM0n = 1).
(b) Set/reset timing
To realize 0%/100% output at PWM output, the TO0n pin/TO0n set timing at
master channel timer interrupt (INTTM0n) generation is delayed by 1 count clock
by the slave channel.
If the set condition and reset condition are generated at the same time, a higher
priority is given to the latter.
Figure 7-29 shows the set/reset operating statuses where the master/slave
channels are set as follows.
pp.260,
261
Chapter 7
Soft
Timer
array unit
Collective
manipulation of
TO0n bits
When TOE0n = 1, even if the output by timer interrupt of each timer (INTTM0n)
contends with writing to TO0n, output is normally done to TO0n pin.
p.263
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Input pulse
interval
measurement
The TI0n pin input is sampled using the operating clock selected with the CKS0n bit
of the TMR0n register, so an error equal to the number of operating clocks occurs.
p.280
Operation of
timer array
unit as
independent
channel
Input signal
high-/low-level
width
measurement
The TI0n pin input is sampled using the operating clock selected with the CKS0n bit
of the TMR0n register, so an error equal to the number of operating clocks occurs.
p.284
PWM function To rewrite both TDR0n of the master channel and TDR0m of the slave channel, a
write access is necessary two times. The timing at which the values of TDR0n and
TDR0m are loaded to TCR0n and TRC0m is upon occurrence of INTTM0n of the
master channel. Thus, when rewriting is performed split before and after occurrence
of INTTM0n of the master channel, the TO0m pin cannot output the expected
waveform. To rewrite both TDR0n of the master and TDR0m of the slave, therefore,
be sure to write both the registers immediately after INTTM0n is generated from the
master channel.
p.288
One-shot pulse
output function
The timing of loading of TDR0n of the master channel is different from that of TDR0m
of the slave channel. If TDR0n and TDR0m are rewritten during operation, therefore,
an illegal waveform is output. Rewrite the TDR0n after INTTM0n is generated and the
TDR0m after INTTM0m is generated.
p.295
Chapter 7
Soft
Operation
of plural
channels of
timer array
unit
Multiple PWM
output function
To rewrite both TDR0n of the master channel and TDR0p of the slave channel 1, write
access is necessary at least twice. Since the values of TDR0n and TDR0p are
loaded to TCR0n and TCR0p after INTTM0n is generated from the master channel, if
rewriting is performed separately before and after generation of INTTM0n from the
master channel, the TO0p pin cannot output the expected waveform. To rewrite both
TDR0n of the master and TDR0p of the slave, be sure to rewrite both the registers
immediately after INTTM0n is generated from the master channel. (This applies also
to TDR0q of the slave channel 2.)
p.302
When using the real-time counter, first set RTCEN to 1, while oscillation of the
subsystem clock (fSUB) is stable. If RTCEN = 0, writing to a control register of the real-
time counter is ignored, and, even if the register is read, only the default value is read.
p.312
PER0:
Peripheral
enable register 0
Be sure to clear bit 1 of the PER0 register to 0. p.312
RTCC0: Real-
time counter
control register 0
If RCLOE0 and RCLOE1 are changed when RTCE = 1, glitches may occur in the
32.768 kHz and 1 Hz output signals.
p.313
RTCC1: Real-
time counter
control register 1
The RIFG and WAFG flags may be cleared when the RTCC1 register is written by
using a 1-bit manipulation instruction. Use, therefore, an 8-bit manipulation instruction
in order to write to the RTCC1 register. To prevent the RIFG and WAFG flags from
being cleared during writing, disable writing by setting “1” to the corresponding bit.
When the value may be rewritten because the RIFG and WAFG flags are not being
used, the RTCC1 register may be written by using a 1-bit manipulation instruction.
p.315
Change ICT2, ICT1, and ICT0 when RINTE = 0.
p.316
When the output from RTCDIV pin is stopped, the output continues after a maximum
of two clocks of fXT and enters the low level. While 512 Hz is output, and when the
output is stopped immediately after entering the high level, a pulse of at least one
clock width of fXT may be generated.
p.316
Chapter 8
Soft
Real-time
counter
RTCC2: Real-
time counter
control register 2
After the real-time counter starts operating, the output width of the RTCDIV pin may
be shorter than as set during the first interval period.
p.316
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When a correction is made by using the SUBCUD register, the value may become
8000H or more.
p.317
This register is also cleared by reset effected by writing the second count register. p.317
RSUBC: Sub-
count register
The value read from this register is not guaranteed if it is read during operation,
because a value that is changing is read.
p.317
HOUR: Hour
count register
Bit 5 (HOUR20) of HOUR indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system
is selected).
p.318
WEEK: Week
count register
The value corresponding to the month count register or the day count register is not
stored in the week count register automatically.
After reset release, set the week count register as follow.
p.321
ALARMWM:
Alarm minute
register
Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the
range is set, the alarm is not detected.
p.324
Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code. If a
value outside the range is set, the alarm is not detected.
p.324
ALARMWH:
Alarm hour
register Bit 5 (WH20) of ALARMWH indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour
system is selected).
p.324
Reading/writing
real-time counter
Complete the series of operations of setting RWAIT to 1 to clearing RWAIT to 0 within
1 second.
pp.328,
329
Chapter 8
Soft
Real-time
counter
1, 512 Hz and
32.768, 16.384
kHz outputs of
real-time counter
First set RTCEN to 1, while oscillation of the subsystem clock (fSUB) is stable. p.331
If a value other than “ACH” is written to WDTE, an internal reset signal is generated. p.339
If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
signal is generated.
p.339
WDTE:
Watchdog timer
enable register
The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)). p.339
When data is written to WDTE for the first time after reset release, the watchdog timer
is cleared in any timing regardless of the window open time, as long as the register is
written before the overflow time, and the watchdog timer starts counting again.
p.340
If the watchdog timer is cleared by writing “ACH” to WDTE, the actual overflow time
may be different from the overflow time set by the option byte by up to 2/fIL seconds.
p.340
The watchdog timer can be cleared immediately before the count value overflows. p.340
The operation of the watchdog timer in the HALT and STOP modes differs as follows
depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H). (See
the table on page 340.)
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP
mode is released. At this time, the counter is cleared to 0 and counting starts. When
operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer
overflow is short, an overflow occurs during the oscillation stabilization time, causing
a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization
time when operating with the X1 oscillation clock and when the watchdog timer is to
be cleared after the STOP mode release by an interval interrupt.
p.341
Chapter 9
Soft
Watchdog
timer
Controlling
operation
The watchdog timer continues its operation during self-programming of the flash
memory and EEPROM emulation. During processing, the interrupt acknowledge time
is delayed. Set the overflow time and window size taking this delay into
consideration.
p.341
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Setting overflow
time
The watchdog timer continues its operation during self-programming of the flash
memory and EEPROM emulation. During processing, the interrupt acknowledge time
is delayed. Set the overflow time and window size taking this delay into
consideration.
p.341
When data is written to WDTE for the first time after reset release, the watchdog
timer is cleared in any timing regardless of the window open time, as long as the
register is written before the overflow time, and the watchdog timer starts counting
again.
p.342
The watchdog timer continues its operation during self-programming of the flash
memory and EEPROM emulation. During processing, the interrupt acknowledge
time is delayed. Set the overflow time and window size taking this delay into
consideration.
p.342
When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period
is 100% regardless of the values of WINDOW1 and WINDOW0.
p.342
Setting window
open period
Do not set the window open period to 25% if the watchdog timer corresponds to
either of the conditions below.
• When used at a supply voltage (VDD) below 2.7 V.
• When stopping all main system clocks (internal high-speed oscillation clock, X1
clock, and external main system clock) by use of the STOP mode or software.
• Low-power consumption mode
p.342
Chapter 9
Soft
Watchdog
timer
Setting interval
interrupt
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU
starts operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer
overflow is short, an overflow occurs during the oscillation stabilization time, causing a
reset.
Consequently, set the overflow time in consideration of the oscillation stabilization
time when operating with the X1 oscillation clock and when the watchdog timer is to
be cleared after the STOP mode release by an interval interrupt.
p.343
Change the output clock after disabling clock output (PCLOEn = 0). p.346
Chapter 10
Soft
Clock
output/
buzzer
output
controller
CKS0, CKS1:
Clock output
select registers
0, 1
If the selected clock (fMAIN or fSUB) stops during clock output (PCLOEn = 1), the output
becomes undefined.
p.346
When setting the A/D converter, be sure to set ADCEN to 1 first. If ADCEN = 0,
writing to a control register of the A/D converter is ignored, and, even if the register is
read, only the default value is read (except for port mode registers 2 and 15 (PM2,
PM15)).
p.351
PER0:
Peripheral
enable register 0
Be sure to clear bit 1 of the PER0 register to 0. p.351
ADM: A/D
converter mode
register
A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and LV0 to
values other than the identical data.
p.352
Chapter 11
Soft
A/D
converter
A/D conversion
time selection
(2.7 V ≤ AVREF0 ≤
5.5 V)
Set the conversion times with the following conditions.
Conventional-specification products (
μ
PD78F116x)
• 4.0 V ≤ AVREF0 ≤ 5.5 V: fAD = 0.6 to 3.6 MHz
• 2.7 V ≤ AVREF0 < 4.0 V: fAD = 0.6 to 1.8 MHz
Functionally expanded products (
μ
PD78F116xA)
• 4.0 V ≤ AVREF0 ≤ 5.5 V: fAD = 0.33 to 3.6 MHz
• 2.7 V ≤ AVREF0 < 4.0 V: fAD = 0.33 to 1.8 MHz
p.353
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Set the conversion times with the following conditions.
• 4.0 V ≤ AVREF0 ≤ 5.5 V: fAD = 0.6 to 3.6 MHz
• 2.7 V ≤ AVREF0 < 4.0 V: fAD = 0.6 to 1.8 MHz
• 2.3 V ≤ AVREF0 < 2.7 V: fAD = 0.6 to 1.44 MHz
p.354
When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D
conversion once (ADCS = 0) beforehand.
p.354
Change LV1 and LV0 from the default value, when 2.3 V ≤ AVREF0 < 2.7 V. p.354
A/D conversion
time selection
(2.3 V ≤ AVREF0 ≤
5.5 V)
The above conversion time does not include clock frequency errors. Select
conversion time, taking clock frequency errors into consideration.
p.354
ADCR: 10-bit
A/D conversion
result register
When writing to the A/D converter mode register (ADM), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the contents
of ADCR may become undefined. Read the conversion result following conversion
completion before writing to ADM, ADS, and ADPC. Using timing other than the
above may cause an incorrect conversion result to be read.
p.356
ADCRH: 8-bit
A/D conversion
result register
When writing to the A/D converter mode register (ADM), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the contents
of ADCRH may become undefined. Read the conversion result following conversion
completion before writing to ADM, ADS, and ADPC. Using timing other than the
above may cause an incorrect conversion result to be read.
p.356
Be sure to clear bits 4 to 6 to “0”. p.357
Set a channel to be used for A/D conversion in the input mode by using port mode
registers 2 and 15 (PM2, PM15).
p.357
ADS: Analog
input channel
specification
register Do not set the pin that is set by ADPC as digital I/O by ADS. p.357
Set a channel to be used for A/D conversion in the input mode by using port mode
registers 2 and 15 (PM2, PM15).
p.358
Do not set the pin that is set by ADPC as digital I/O by ADS. p.358
ADPC: A/D port
configuration
register
P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 are set as analog inputs in the
order of P157/ANI15, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port
configuration register (ADPC). When using P20/ANI0 to P27/ANI7 and P150/ANI8 to
P157/ANI15 as analog inputs, start designing from P157/ANI15.
p.358
PM2, PM15: Port
mode registers 2
and 15
If a pin is set as an analog input port, not the pin level but “0” is always read. p.359
Basic operations
of A/D converter
Make sure the period of <2> to <6> is 1
μ
s or more. p.360
Make sure the period of <2> to <6> is 1
μ
s or more. p.364
<2> may be done between <3> and <5>. p.364
A/D conversion
operation
The period from <7> to <10> differs from the conversion time set using bits 5 to 1
(FR2 to FR0, LV1, LV0) of ADM. The period from <9> to <10> is the conversion time
set using FR2 to FR0, LV1, and LV0.
p.364
Temperature
sensor function
The temperature sensor cannot be used when low current consumption mode is set
(RMC = 5AH) or when the internal high-speed oscillator has been stopped
(HIOSTOP = 1 (bit 0 of CSC register)). The temperature sensor can operate as long
as the internal high-speed oscillator operates (HIOSTOP = 0), even if it is not
selected as the CPU/peripheral hardware clock source.
p.365
Setting of the A/D port configuration register (ADPC), port mode register 2 (PM2) and
port register 2 (P2) is not required when using the temperature sensor. There is no
problem if the pin function is set as digital I/O.
p.366
Chapter 11
Soft
A/D
converter
Registers used
by temperature
sensors
Set the conversion times so as to satisfy the following condition. fAD = 0.6 to 1.8 MHz p.366
APPENDIX B LIST OF CAUTIONS
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When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D
conversion (ADCS = 0) beforehand.
p.366
The above conversion time does not include clock frequency errors. Select
conversion time, taking clock frequency errors into consideration.
p.366
When using a temperature sensor, use the result of the second or later A/D
conversion for temperature sensor 0 (ANI0 side), and the result of the third or later
A/D conversion for temperature sensor 1 (ANI1 side).
p.367
Registers used
by temperature
sensors
Be sure to clear bits 4 to 6 to “0”. p.367
Make sure the period of <2> to <5> is 1
μ
s or more. If ADCS is set to 1 within 1
μ
s,
the result of the third and later conversion becomes valid on the sensor 0 side.
p.371
<2> can be done between <3> and <4>. p.371
The period from <7> to <10> differs from the conversion time set using bits 5 to 1
(FR2 to FR0, LV1, LV0) of ADM. The period from <9> to <10> is the conversion time
set using FR2 to FR0, LV1, and LV0.
p.371
Do not change the AVREF0 voltage during <4> to <13>. Although the temperature
sensor detection value does not depend on the AVREF0 voltage and thus there is no
problem even if the AVREF0 voltage varies at every temperature measurement, it must
be stable during a measurement cycle (from <4> to <13>).
p.371
Procedure for
using
temperature
sensors
Use the result of the second or later A/D conversion for temperature sensor 0 (ANI0
side), and the result of the third or later A/D conversion for temperature sensor 1
(ANI1 side).
p. 372
Operating
current in STOP
mode
Shift to STOP mode after clearing the A/D converter (by clearing bit 7 (ADCS) of the
A/D converter mode register (ADM) to 0). The operating current can be reduced by
clearing bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 at the same time.
To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register
1L (IF1L) to 0 and start operation.
p.375
Soft
Reducing
current when
A/D converter is
stopped
Be sure that the voltage to be applied to AVREF0 normally satisfies the conditions
stated in Table 11-1.
If bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) are set to
0, the current will not be increased by the A/D converter even if a voltage is applied to
AVREF0, while the A/D converter is stopped. If a current flows from the power supply
that supplies a voltage to AVREF0 to an external circuit of the microcontroller as shown
in Figure 11-25, AVREF0 = 0 V = AVSS can be achieved and the external current can
be reduced by satisfying the following conditions (see the main text).
p.375
Hard
Input range of
ANI0 to ANI15
Observe the rated range of the ANI0 to ANI15 input voltage. If a voltage of AVREF0 or
higher and AVSS or lower (even in the range of absolute maximum ratings) is input to
an analog input channel, the converted value of that channel becomes undefined. In
addition, the converted values of the other channels may also be affected.
p.376
Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR or
ADCRH read by instruction upon the end of conversion
ADCR or ADCRH read has priority. After the read operation, the new conversion
result is written to ADCR or ADCRH.
p.376
Chapter 11
Soft
A/D
converter
Conflicting
operations
Conflict between ADCR or ADCRH write and A/D converter mode register (ADM)
write, analog input channel specification register (ADS), or A/D port configuration
register (ADPC) write upon the end of conversion
ADM, ADS, or ADPC write has priority. ADCR or ADCRH write is not performed, nor
is the conversion end interrupt signal (INTAD) generated.
p.376
APPENDIX B LIST OF CAUTIONS
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Hard
Noise
countermeasures
To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF0
pin and pins ANI0 to ANI15.
<1> Connect a capacitor with a low equivalent resistance and a good frequency
response to the power supply.
<2> The higher the output impedance of the analog input source, the greater the
influence. To reduce the noise, connecting external C as shown in Figure 11-26
is recommended.
<3> Do not switch these pins with other pins during conversion.
<4> The accuracy is improved if the HALT mode is set immediately after the start of
conversion.
p.376
Soft
The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27).
The analog input pins (ANI8 to ANI15) are also used as input port pins (P150 to
P157).
When A/D conversion is performed with any of ANI0 to ANI15 selected, do not
access P20 to P27 and P150 to P157 while conversion is in progress; otherwise the
conversion resolution may be degraded. It is recommended to select pins used as
P20 to P27 and P150 to P157 starting with the ANI0/P20 that is the furthest from
AVREF0.
p.377
ANI0/P20 to
ANI7/P27 and
ANI8/P150 to
ANI15/P157
If a digital pulse is applied to the pins adjacent to the pins currently used for A/D
conversion, the expected value of the A/D conversion may not be obtained due to
coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin
undergoing A/D conversion.
p.377
Input impedance
of ANI0 to ANI15
pins
This A/D converter charges a sampling capacitor for sampling during sampling time.
Therefore, only a leakage current flows when sampling is not in progress, and a
current that charges the capacitor flows during sampling. Consequently, the input
impedance fluctuates depending on whether sampling is in progress, and on the
other states.
To make sure that sampling is effective, however, it is recommended to keep the
output impedance of the analog input source to within 10 kΩ, and to connect a
capacitor of about 100 pF to the ANI0 to ANI15 pins (see Figure 11-26).
p.377
Hard
AVREF0 pin input
impedance
A series resistor string of several tens of kΩ is connected between the AVREF0 and
AVSS pins.
Therefore, if the output impedance of the reference voltage source is high, this will
result in a series connection to the series resistor string between the AVREF0 and AVSS
pins, resulting in a large reference voltage error.
p.377
Interrupt request
flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the analog input channel
specification register (ADS) is changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D
conversion result and ADIF for the pre-change analog input may be set just before
the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read
immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the
post-change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D
conversion operation is resumed.
p.378
Chapter 11
Soft
A/D
converter
Conversion
results just after
A/D conversion
start
The first A/D conversion value immediately after A/D conversion starts may not fall
within the rating range if the ADCS bit is set to 1 within 1
μ
s after the ADCE bit was
set to 1. Take measures such as polling the A/D conversion end interrupt request
(INTAD) and removing the first conversion result.
p.378
APPENDIX B LIST OF CAUTIONS
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A/D conversion
result register
(ADCR,
ADCRH) read
operation
When a write operation is performed to the A/D converter mode register (ADM),
analog input channel specification register (ADS), and A/D port configuration register
(ADPC), the contents of ADCR and ADCRH may become undefined. Read the
conversion result following conversion completion before writing to ADM, ADS, and
ADPC. Using a timing other than the above may cause an incorrect conversion
result to be read.
p.378
A/D conversion
result register
(ADCR,
ADCRH) read
operation
When a write operation is performed to the A/D converter mode register (ADM),
analog input channel specification register (ADS), and A/D port configuration register
(ADPC), the contents of ADCR and ADCRH may become undefined. Read the
conversion result following conversion completion before writing to ADM, ADS, and
ADPC. Using a timing other than the above may cause an incorrect conversion
result to be read.
p.378
Chapter 11
Soft
A/D
converter
Starting the A/D
converter
Start the A/D converter after the AVREF0 and AVREF1 voltages (the reference voltages
for the D/A converter) stabilize.
p.379
When setting the D/A converter, be sure to set DACEN to 1 first. If DACEN = 0,
writing to a control register of the D/A converter is ignored, and, even if the register is
read, only the default value is read (except for port mode register 11 (PM11) and port
register 11 (P11)).
p.382
PER0:
Peripheral
enable register 0
Be sure to clear bit 1 of the PER0 register to 0. p.382
Operation in
normal mode
Make the interval for writing DACSn of the same channel by one clock longer than
fCLK. If writing is successively performed, only the value written last will be converted.
p.385
Make the interval for generating a start trigger to the same channel by one clock
longer than fCLK. If a start trigger is successively generated for every fCLK, D/A
conversion will be performed only at the first trigger.
p.386
Operation in
real-time output
mode
Note the following points in the procedure (i to iii) for outputting an arbitrary value in
<3>.
• Do not generate the start trigger of the real-time output mode before enabling D/A
conversion operation in <3> after the value is set to the DACSn register in ii.
• An arbitrary value cannot be output in <3> if the DACEN bit of the PER0 register is
cleared once after the value is set to the DACSn register in ii.
p.386
I/O function of
digital ports
alternately used
as ANO0, ANO1
The digital port I/O function, which is the alternate function of the ANO0 and ANO1
pins, does not operate during D/A conversion.
During D/A conversion, 0 is read from the P11 register in input mode.
p.387
P11, PM11
registers
Do not read/write the P11 register and do not change the setting of the PM11 register
during D/A conversion (otherwise the conversion accuracy may decrease).
p.387
ANO0, ANO1
pins
It is recommended that both the ANO0 and ANO1 pins be used as analog output pins
or digital I/O pins, that is, use these two channels for the same application (if these
pins are used for the different applications, the conversion accuracy may decrease).
p.387
DACSn register In the real-time output mode, set the DACSn register value before the timer trigger is
generated. In addition, do not change the set value of the DACSn register while the
trigger signal is output.
p.387
Soft
Changing
operation mode
Before changing the operation mode, be sure to clear the DACEn bit of the DAM
register to 0 (D/A conversion stop).
p.387
Port alternately
used as ANO0
or ANO1 pin
When using the port that functions alternately as the ANO0 or ANO1 pin, use it as the
port input with few level changes.
p.387
Chapter 12
Hard
D/A
converter
Applying power
to and
disconnecting
power from
AVREF1 and AVREF0
Stop the conversion performed by the D/A converter when supplying AVREF1 or
AVREF0 (the reference voltages for the A/D converter) starts or stops.
p.387
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Soft
Reducing power
consumption in
STOP mode
Because the D/A converter stops operation in the STOP mode, the ANO0 and ANO1
pins go into a high impedance state, and the power consumption can be reduced. In
the standby modes other than the STOP mode, however, the operation continues.
To lower the power consumption, therefore, clear the DACEn bit of the DAM register
to 0 (D/A conversion stop).
p.387
Chapter 12
Hard
D/A
converter
Output
impedance of
D/A converter
Since the output impedance of the D/A converter is high, the current cannot be
obtained from the ANOn pin (n = 0, 1). When the input impedance of the load is low,
insert a follower amplifier between the load and ANOn pin keeping the wiring length
as short as possible (for high impedance). If the wiring becomes too long, take
necessary actions such as surrounding with a ground pattern.
p.387
Configuration
of serial
array unit
SDRmn: Lower
8 bits of the
serial data
register mn
Be sure to clear bit 8 to “0”. p.395
When setting serial array unit m, be sure to set SAUmEN to 1 first. If SAUmEN = 0,
writing to a control register of serial array unit m is ignored, and, even if the register is
read, only the default value is read (except for input switch control register (ISC),
noise filter enable register (NFEN0), port input mode registers (PIM0, PIM4, PIM14),
port output mode registers (POM0, POM4, POM14), port mode registers (PM0, PM1,
PM4, PM14), and port registers (P0, P1, P4, P14)).
p.397
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
p.397
PER0:
Peripheral
enable register 0
Be sure to clear bit 1 of the PER0 register to 0. p.397
Be sure to clear bits 15 to 8 to “0”. p.398
SPSm: Serial
clock select
register m
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
p.398
SMRmn: Serial
mode register
mn
Be sure to clear bits 13 to 9, 7, 4, and 3 to “0”. Be sure to set bit 5 to “1”. p.399
pp.401,
SCRmn: Serial
communication
operation setting
register mn
Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
402, 403
Be sure to clear bit 8 to “0”. p.404
Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used. p.404
Setting SDRmn[15:9] = 0000000B is prohibited when simplified I2C is used. Set
SDRmn[15:9] to 0000001B or greater.
p.404
SDRmn: Higher
7 bits of the
serial data
register mn
Do not write eight bits to the lower eight bits if operation is stopped (SEmn = 0). (If
these bits are written to, the higher seven bits are cleared to 0.)
p.404
SIRmn: Serial
flag clear trigger
register mn
Be sure to clear bits 15 to 3 to “0”. p.407
SSm: Serial
channel start
register m
Be sure to clear bits 15 to 4 to “0”. p.409
Chapter 13
Soft
Registers
controlling
serial array
unit
STm: Serial
channel stop
register m
Be sure to clear bits 15 to 4 to “0”. p.410
APPENDIX B LIST OF CAUTIONS
User’s Manual U17894EJ9V0UD 917
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Function Details of
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Cautions Page
SOEm: Serial
output enable
register m
Be sure to clear bits 15 to 3 of SOE0, and bits 15 to 3 and 1 of SOE1 to “0”. p.411
SOm: Serial
output register m
Be sure to set bits 11 and 3 of SO0, and bits 11 to 9, 3, and 1 of SO1 to “1”. And be
sure to clear bits 15 to 12 and 7 to 4 of SOm to “0”.
p.412
SOLm: Serial
output level
register m
Be sure to clear bits 15 to 3 and 1 to “0”. p.413
ISC: Input switch
control register
Be sure to clear bits 7 to 2 to “0”. p.414
Registers
controlling
serial array
unit
NFEN0: Noise
filter enable
register 0
Be sure to clear bits 7, 5, 3, and 1 to “0”. p.415
If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and,
even if the register is read, only the default value is read (except for input switch
control register (ISC), noise filter enable register (NFEN0), port input mode registers
(PIM0, PIM4, PIM14), port output mode registers (POM0, POM4, POM14), port mode
registers (PM0, PM1, PM4, PM14), and port registers (P0, P1, P4, P14)).
p.418
Operation
stop mode
Stopping the
operation by
units
Be sure to clear bit 1 of the PER0 register to 0. p.418
pp.424,
Master
transmission
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed. 428, 430
Master transmission
(in continuous
transmission mode)
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten
before the transfer end interrupt of the last transmit data.
p.429
Master reception After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
pp.433,
436, 438
Master reception
(in continuous
reception mode)
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before receive of the last bit is started, so that it has been
rewritten before the transfer end interrupt of the last receive data.
p.437
pp.441,
Master
transmission/
reception
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed. 444, 446
Master
transmission/
reception (in
continuous
transmission/
reception mode)
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been
rewritten before the transfer end interrupt of the last transmit data.
p.445
pp.449,
Slave
transmission
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed. 453, 455
Chapter 13
Soft
3-wire serial I/O
(CSI00, CSI01,
CSI10, CSI20)
communication
Slave transmission
(in continuous
transmission mode)
The MDmn0 bit can be rewritten even during operation. However, rewrite it before
transfer of the last bit is started.
p.454
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Slave reception After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
pp.458,
461
pp.463,
Be sure to set transmit data to the SlOp register before the clock from the master is
started. 464, 466,
468, 470
pp.464,
Slave
transmission/
reception
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed. 468, 470
3-wire serial I/O
(CSI00, CSI01,
CSI10, CSI20)
communication
Slave
transmission/
reception (in
continuous
transmission/
reception mode)
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten
before the transfer end interrupt of the last transmit data.
p.469
− When using serial array units 0 and 1 as UARTs, the channels of both the
transmitting side (even-number channel) and the receiving side (odd-number
channel) can be used only as UARTs.
p.474
pp.478,
UART
transmission
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed. 482, 484
UART
transmission (in
continuous
transmission
mode)
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been
rewritten before the transfer end interrupt of the last transmit data.
p.483
For the UART reception, be sure to set SMRmr of channel r that is to be paired with
channel n.
pp.486,
487
UART reception
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
pp.488,
491
UART (UART0,
UART1,
UART2,
UART3)
communication
Calculating baud
rate
Setting SDRmn [15:9] = (0000000B, 0000001B) is prohibited. p.500
Address field
transmission
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
p.508
Data reception ACK is not output when the last data is received (NACK). Communication is then
completed by setting “1” to the STmn bit to stop operation and generating a stop
condition.
p.517
Chapter 13
Soft
Simplified
I2C (IIC10,
IIC20)
communi-
cation
Calculating
transfer rate
Setting SDRmn[15:9] = 0000000B is prohibited. Setting SDRmn[15:9] = 0000001B or
more.
p.519
Do not write data to IIC0 during data transfer. p.533
IIC0: IIC shift
register 0 Write or read IIC0 only during the wait period. Accessing IIC0 in a communication
state other than during the wait period is prohibited. When the device serves as the
master, however, IIC0 can be written only once after the communication trigger bit
(STT0) is set to 1.
p.533
When setting serial interface IIC0, be sure to set IIC0EN to 1 first. If IIC0EN = 0,
writing to a control register of serial interface IIC0 is ignored, and, even if the register
is read, only the default value is read (except for port mode register 6 (PM6) and port
register 6 (P6)).
p.536
Chapter 14
Soft
Serial
interface
IIC0
PER0:
Peripheral
enable register 0
Be sure to clear bit 1 of the PER0 register to 0. p.536
APPENDIX B LIST OF CAUTIONS
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The start condition is detected immediately after I2C is enabled to operate (IICE0 = 1)
while the SCL0 line is at high level and the SDA0 line is at low level. Immediately
after enabling I2C to operate (IICE0 = 1), set LREL0 (1) by using a 1-bit memory
manipulation instruction.
p.537
IICC0: IIC
control register 0
When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set to 1
during the ninth clock and wait is canceled, after which TRC0 is cleared and the
SDA0 line is set to high impedance.
p.540
Write to STCEN only when the operation is stopped (IICE0 = 0). p.544
As the bus release status (IICBSY = 0) is recognized regardless of the actual bus
status when STCEN = 1, when generating the first start condition (STT0 = 1), it is
necessary to verify that no third party communications are in progress in order to
prevent such communications from being destroyed.
p.544
IICF0: IIC flag
register 0
Write to IICRSV only when the operation is stopped (IICE0 = 0). p.544
IICX0: IIC
function
expansion
register 0
Determine the transfer clock frequency of I2C by using CLX0, SMC0, CL01, and
CL00 before enabling the operation (by setting bit 7 (IICE0) of IIC control register 0
(IICC0) to 1). To change the transfer clock frequency, clear IICE0 once to 0.
p.546
Setting transfer
clock
Determine the transfer clock frequency of I2C by using CLX0, SMC0, CL01, and
CL00 before enabling the operation (by setting bit 7 (IICE0) of IIC control register 0
(IICC0) to 1). To change the transfer clock frequency, clear IICE0 once to 0.
p.552
When STCEN =
0
Immediately after I2C operation is enabled (IICE0 = 1), the bus communication status
(IICBSY (bit 6 of IICF0) = 1) is recognized regardless of the actual bus status. When
changing from a mode in which no stop condition has been detected to a master
device communication mode, first generate a stop condition to release the bus, then
perform master device communication.
When using multiple masters, it is not possible to perform master device
communication when the bus has not been released (when a stop condition has not
been detected).
Use the following sequence for generating a stop condition.
<1> Set IIC clock select register 0 (IICCL0).
<2> Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1.
<3> Set bit 0 (SPT0) of IICC0 to 1.
p.566
When STCEN =
1
Immediately after I2C operation is enabled (IICE0 = 1), the bus released status
(IICBSY = 0) is recognized regardless of the actual bus status. To generate the first
start condition (STT0 (bit 1 of IIC control register 0 (IICC0)) = 1), it is necessary to
confirm that the bus has been released, so as to not disturb other communications.
p.566
If other I2C
communications
are already in
progress
If I2C operation is enabled and the device participates in communication already in
progress when the SDA0 pin is low and the SCL0 pin is high, the macro of I2C
recognizes that the SDA0 pin has gone low (detects a start condition). If the value on
the bus at this time can be recognized as an extension code, ACK is returned, but
this interferes with other I2C communications. To avoid this, start I2C in the following
sequence.
<1> Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an interrupt request
signal (INTIIC0) when the stop condition is detected.
<2> Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I2C.
<3> Wait for detection of the start condition.
<4> Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after
setting IICE0 to 1), to forcibly disable detection.
p.566
Chapter 14
Soft
Serial
interface
IIC0
Setting transfer
clock frequency
Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1, and 0
of IICL0), and CLX0 (bit 0 of IICX0) before enabling the operation (IICE0 = 1). To
change the transfer clock frequency, clear IICE0 to 0 once.
p.566
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STT0, SPT0:
Bits 1, 0 of IIC
control register 0
(IICC0)
Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and before
they are cleared to 0 is prohibited.
p.566
Chapter 14
Soft
Serial
interface
IIC0
Reserving
transmission
When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt
request is generated when the stop condition is detected. Transfer is started when
communication data is written to IIC0 after the interrupt request is generated. Unless
the interrupt is generated when the stop condition is detected, the device stops in the
wait state because the interrupt request is not generated when communication is
started. However, it is not necessary to set SPIE0 to 1 when MSTS0 (bit 7 of IICS0)
is detected by software.
p.566
Be sure to clear bits 15 to 10 to “0”. p.609
DBCn: DMA
byte count
register n
If the general-purpose register is specified or the internal RAM space is exceeded as
a result of continuous transfer, the general-purpose register or SFR space are written
or read, resulting in loss of data in these spaces. Be sure to set the number of times
of transfer that is within the internal RAM space.
p.609
DRCn: DMA
operation control
register n
The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is
terminatedwithout waiting for generation of the interrupt (INTDMAn) of DMAn,
therefore, set DSTn to 0 and then DENn to 0 (for details, refer to 16.5.7 Forcible
termination by software).
p.613
Example of
Setting for
Holding DMA
Transfer
Pending by
DWAITn
When DMA transfer is held pending while using both DMA channels, be sure to hold
the DMA transfer pending for both channels (by setting DWAIT0 and DWAIT1 to 1). If
the DMA transfer of one channel is executed while that of the other channel is held
pending, DMA transfer might not be held pending for the latter channel.
p.627
Forced
Termination of
DMA Transfer
In example 3, the system is not required to wait two clock cycles after DWAITn is set
to 1. In addition, the system does not have to wait two clock cycles after clearing
DSTn to 0, because more than two clock cycles elapse from when DSTn is cleared to
0 to when DENn is cleared to 0.
p.629
Soft
Priority During DMA transfer, a request from the other DMA channel is held pending even if
generated. The pending DMA transfer is started after the ongoing DMA transfer is
completed. If two DMA requests are generated at the same time, however, DMA
channel 0 takes priority over DMA channel 1.
If a DMA request and an interrupt request are generated at the same time, the DMA
transfer takes precedence, and then interrupt servicing is executed.
p.630
Hard
Response time The response time of DMA transfer is as follows. (See Table 16-2.) p.631
Chapter 16
Soft
DMA
controller
Operation in
standby mode
The DMA controller operates as follows in the standby mode. (See Table 16-3.) p.632
APPENDIX B LIST OF CAUTIONS
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Chapter
Classification
Function Details of
Function
Cautions Page
DMA pending
instruction
Even if a DMA request is generated, DMA transfer is held pending immediately after
the following instructions.
• CALL !addr16
• CALL $!addr20
• CALL !!addr20
• CALL rp
• CALLT [addr5]
• BRK
• Bit manipulation instructions for registers IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, MK0L,
MK0H, MK1L, MK1H, MK2L, MK2H, PR00L, PR00H, PR01L, PR01H, PR02L,
PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H and PSW each.
p.632
Chapter 16
Soft
DMA
controller
Operation if
address in
general-purpose
register area or
other than those
of internal RAM
area is specified
The address indicated by DRA0n is incremented during DMA transfer. If the address
is incremented to an address in the general-purpose register area or exceeds the
area of the internal RAM, the following operation is performed.
z In mode of transfer from SFR to RAM
The data of that address is lost.
z In mode of transfer from RAM to SFR
Undefined data is transferred to SFR.
In either case, malfunctioning may occur or damage may be done to the system.
Therefore, make sure that the address is within the internal RAM area other than the
general-purpose register area.
p.632
Be sure to clear bits 1 to 7 of IF2H to 0. p.641
When operating a timer, serial interface, or A/D converter after standby release,
operate it once after clearing the interrupt request flag. An interrupt request flag may
be set by noise.
p.641
IF0L, IF0H, IF1L,
IF1H, IF2L, IF2H:
Interrupt request
flag registers
When manipulating a flag of the interrupt request flag register, use a 1-bit memory
manipulation instruction (CLR1). When describing in C language, use a bit
manipulation instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the
compiled assembler must be a 1-bit memory manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation
instruction such as “IF0L &= 0xfe;” and compiled, it becomes the assembler of three
instructions.
mov a, IF0L
and a, #0FEH
mov IF0L, a
In this case, even if the request flag of another bit of the same interrupt request flag
register (IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the
flag is cleared to 0 at “mov IF0L, a”. Therefore, care must be exercised when using
an 8-bit memory manipulation instruction in C language.
p.641
Chapter 17
Soft
Interrupt
functions
MK0L, MK0H,
MK1L, MK1H,
MK2L, MK2H:
Interrupt mask
flag registers
Be sure to set bits 1 to 7 of MK2H to 1. p.642
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PR00L, PR00H,
PR01L, PR01H,
PR02L, PR02H,
PR10L, PR10H,
PR11L, PR11H,
PR12L, PR12H:
Priority
specification flag
registers
Be sure to set bits 1 to 7 of PR02H and PR12H to 1. p.644
EGP0, EGP1:
External
interrupt rising
edge enable
registers, EGN0,
EGN1: External
interrupt falling
edge enable
registers
Select the port mode by clearing EGPn and EGNn to 0 because an edge may be
detected when the external interrupt function is switched to the port function.
p.646
Software
interrupt request
acknowledgment
Do not use the RETI instruction for restoring from the software interrupt. p.650
Chapter 17
Soft
Interrupt
functions
BRK instruction The BRK instruction is not one of the above-listed interrupt request hold instructions.
However, the software interrupt activated by executing the BRK instruction causes
the IE flag to be cleared. Therefore, even if a maskable interrupt request is
generated during execution of the BRK instruction, the interrupt request is not
acknowledged.
p.654
If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of
the corresponding pull-up resistor register 7 (PU7) to 1.
p.656
An interrupt will be generated if the target bit of the KRM register is set while a low
level is being input to the key interrupt input pin. To ignore this interrupt, set the
KRM register after disabling interrupt servicing by using the interrupt mask flag.
Afterward, clear the interrupt request flag and enable interrupt servicing after waiting
for the key interrupt input low-level width (250 ns or more).
p.656
Chapter 18
Soft
Key
interrupt
function
KRM: Key return
mode register
The bits not used in the key interrupt mode can be used as normal ports. p.656
The STOP mode can be used only when the CPU is operating on the main system
clock. The STOP mode cannot be set while the CPU operates with the subsystem
clock. The HALT mode can be used when the CPU is operating on either the main
system clock or the subsystem clock.
p.657
When shifting to the STOP mode, be sure to stop the peripheral hardware operation
operating with main system clock before executing STOP instruction.
p.657
Chapter 19
Soft
Standby
function
−
The following sequence is recommended for operating current reduction of the A/D
converter when the standby function is used: First clear bit 7 (ADCS) and bit 0
(ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion
operation, and then execute the STOP instruction.
p.657
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− It can be selected by the option byte whether the internal low-speed oscillator
continues oscillating or stops in the HALT or STOP mode. For details, see
CHAPTER 24 OPTION BYTE.
p.657
After the above time has elapsed, the bits are set to 1 in order from MOST8 and
remain 1.
p.658
Soft
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. If the STOP mode is entered and then released while the internal high-
speed oscillation clock is being used as the CPU clock, set the oscillation stabilization
time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
p.658
Hard
OSTC:
Oscillation
stabilization time
counter status
register
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
p.658
To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
before executing the STOP instruction.
p.659
Setting the oscillation stabilization time to 20
μ
s or less is prohibited. p.659
Before changing the setting of the OSTS register, confirm that the count operation of
the OSTC register is completed.
p.659
Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
p.659
Soft
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. If the STOP mode is entered and then released while the internal
high-speed oscillation clock is being used as the CPU clock, set the oscillation
stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
p.659
Hard
OSTS:
Oscillation
stabilization time
select register
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
p.659
Because the interrupt request signal is used to clear the standby mode, if there is an
interrupt source with the interrupt request flag set and the interrupt mask flag reset,
the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the
HALT mode immediately after execution of the STOP instruction and the system
returns to the operating mode as soon as the wait time set using the oscillation
stabilization time select register (OSTS) has elapsed.
p.665
To use the peripheral hardware that stops operation in the STOP mode, and the
peripheral hardware for which the clock that stops oscillating in the STOP mode after
the STOP mode is released, restart the peripheral hardware.
p.667
Chapter 19
Soft
Standby
function
STOP mode
To stop the internal low-speed oscillation clock in the STOP mode, use an option
byte to stop the watchdog timer operation in the HALT/STOP mode (bit 0
(WDSTBYON) of 000C0H = 0), and then execute the STOP instruction.
p.667
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Cautions Page
Chapter 19
Soft
Standby
function
STOP mode To shorten oscillation stabilization time after the STOP mode is released when the
CPU operates with the high-speed system clock (X1 oscillation), temporarily switch
the CPU clock to the internal high-speed oscillation clock before the execution of the
STOP instruction. Before changing the CPU clock from the internal high-speed
oscillation clock to the high-speed system clock (X1 oscillation) after the STOP mode
is released, check the oscillation stabilization time with the oscillation stabilization
time counter status register (OSTC).
p.667
For an external reset, input a low level for 10
μ
s or more to the RESET pin.
(If an external reset is effected upon power application, the period during which the
supply voltage is outside the operating range (VDD < 1.8 V) is not counted in the 10
μ
s. However, the low-level input may be continued before POC is released.)
p.672
During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and
internal low-speed oscillation clock stop oscillating. External main system clock input
becomes invalid.
p.672
Hard
−
When the STOP mode is released by a reset, the RAM contents in the STOP mode
are held during reset input. However, because SFR and 2nd SFR are initialized, the
port pins become high-impedance, except for P130, which is set to low-level output.
p.672
Block diagram of
reset function
An LVI circuit internal reset does not reset the LVI circuit. p.673
Watchdog timer
overflow
A watchdog timer internal reset resets the watchdog timer. p.674
Do not read data by a 1-bit memory manipulation instruction. p.680
Chapter 20
Soft
Reset
function
RESF: Reset
control flag
register
When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, LVIRF
flag may become 1 from the beginning depending on the power-on waveform.
p.680
If the low-voltage detector (LVI) is set to ON by an option byte by default, the reset
signal is not released until the supply voltage (VDD) exceeds 2.07 V ±0.2 V.
pp.681,
682
−
If an internal reset signal is generated in the POC circuit, the reset control flag
register (RESF) is cleared to 00H.
p.681
Timing of
generation of
internal reset
signal (LVIOFF =
1)
Set the low-voltage detector by software after the reset status is released (see
CHAPTER 22 LOW-VOLTAGE DETECTOR).
p.683
Timing of
generation of
internal reset
signal (LVIOFF =
0)
Set the low-voltage detector by software after the reset status is released (see
CHAPTER 22 LOW-VOLTAGE DETECTOR).
p.684
Chapter 21
Soft
Power-on-
clear
circuit
Cautions for
power-on-clear
circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the
vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and
released from the reset status. In this case, the time from release of reset to the start
of the operation of the microcontroller can be arbitrarily set by taking the following
action.
p.685
Soft
To stop LVI, follow either of the procedures below.
• When using 8-bit memory manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
p.690
Chapter 22
Hard
Low-
voltage
detector
LVIM: Low-
voltage detection
register
Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
p.690
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LVIM: Low-
voltage detection
register
When LVI is used in interrupt mode (LVIMD = 0) and LVISEL is set to 0, an interrupt
request signal (INTLVI) that disables LVI operation (clears LVION) when the supply
voltage (VDD) is less than or equal to the detection voltage (VLVI) (if LVISEL = 1, input
voltage of external input pin (EXLVI) is less than or equal to the detection voltage
(VEXLVI)) is generated and LVIIF may be set to 1.
p.690
Be sure to clear bits 4 to 7 to “0”. p.691
Change the LVIS value with either of the following methods.
• When changing the value after stopping LVI
<1> Stop LVI (LVION = 0).
<2> Change the LVIS register.
<3> Set to the mode used as an interrupt (LVIMD = 0).
<4> Mask LVI interrupts (LVIMK = 1).
<5> Enable LVI operation (LVION = 1).
<6> Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
because an LVIIF flag may be set when LVI operation is enabled.
• When changing the value after setting to the mode used as an interrupt (LVIMD =
0)
<1> Mask LVI interrupts (LVIMK = 1).
<2> Set to the mode used as an interrupt (LVIMD = 0).
<3> Change the LVIS register.
<4> Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
because an LVIIF flag may be set when the LVIS register is changed.
p.692
LVIS: Low-
voltage detection
level select
register
When an input voltage from the external input pin (EXLVI) is detected, the detection
voltage (VEXLVI) is fixed. Therefore, setting of LVIS is not necessary.
p.692
<1> must always be executed. When LVIMK = 0, an interrupt may occur
immediately after the processing in <4>.
p.694
Used as reset
(when detecting
level of supply
voltage (VDD))
(LVIOFF = 1)
If supply voltage (VDD) ≥ detection voltage (VLVI) when LVIMD is set to 1, an internal
reset signal is not generated.
p.694
Used as reset
(when detecting
level of supply
voltage (VDD))
(LVIOFF = 0)
Even when the LVI default start function is used, if it is set to LVI operation
prohibition by the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
starts after reset release. There is a period when low-voltage detection cannot be
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
μ
s
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
p.696
<1> must always be executed. When LVIMK = 0, an interrupt may occur
immediately after the processing in <3>.
p.698
Soft
If input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI = 1.21 V
(TYP.)) when LVIMD is set to 1, an internal reset signal is not generated.
p.698
Chapter 22
Hard
Low-
voltage
detector
Used as reset
(when detecting
level of input
voltage from
external input
pin (EXLVI))
Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
p.698
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Even when the LVI default start function is used, if it is set to LVI operation
prohibition by the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
starts after reset release. There is a period when low-voltage detection cannot be
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
μ
s
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
p.702
Soft
Used as interrupt
(when detecting
level of supply
voltage (VDD))
(LVIOFF = 0)
When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, the
LVIRF flag may become 1 from the beginning due to the power-on waveform.
For details of RESF, see CHAPTER 20 RESET FUNCTION.
p.702
Hard
Used as interrupt
(when detecting
level of input
voltage from
external input pin
(EXLVI))
The input voltage from the external input pin (EXLVI) must be EXLVI < VDD. p.704
Soft
In a system where the supply voltage (VDD) fluctuates for a certain period in the
vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on
how the low-voltage detector is used.
Operation example 1: When used as reset
The system may be repeatedly reset and released from the reset status.
The time from reset release through microcontroller operation start can be set
arbitrarily by the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each
system by means of a software counter that uses a timer, and then initialize the ports
(see Figure 22-11).
Operation example 2: When used as interrupt
Interrupt requests may be generated frequently.
Take the following action.
<Action>
Confirm that “supply voltage (VDD) ≥ detection voltage (VLVI)” when detecting the
falling edge of VDD, or “supply voltage (VDD) < detection voltage (VLVI)” when detecting
the rising edge of VDD, in the servicing routine of the LVI interrupt by using bit 0
(LVIF) of the low-voltage detection register (LVIM). Clear bit 1 (LVIIF) of interrupt
request flag register 0L (IF0L) to 0.
For a system with a long supply voltage fluctuation period near the LVI detection
voltage, take the above action after waiting for the supply voltage fluctuation time.
pp.706
to 709
Chapter 22
Hard
Low-
voltage
detector
Cautions for low-
voltage detector
There is some delay from the time supply voltage (VDD) < LVI detection voltage (VLVI)
until the time LVI reset has been generated.
In the same way, there is also some delay from the time LVI detection voltage (VLVI)
≤ supply voltage (VDD) until the time LVI reset has been released (see Figure 22-12).
See the timing in Figure 21-2 (2) When LVI is ON upon power application (option
byte: LVIOFF = 0) for the reset processing time until the normal operation is entered
after the LVI reset is released.
p.709
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Cautions Page
The RMC register can be rewritten only in the low consumption current mode (refer
to Table 23-1). In other words, rewrite this register during CPU operation with the
subsystem clock (fXT) while the high-speed system clock (fMX) and internal high-
speed oscillation clock (fIH) are both stopped.
p.710
When using the setting fixed to the low consumption current mode, the RMC register
can be used in the following cases.
<When X1 clock is selected as the CPU clock>
fX ≤ 5 MHz and fCLK ≤ 5 MHz
<When the internal high-speed oscillation clock, external input clock, or subsystem
clock are selected for the CPU clock>
fCLK ≤ 5 MHz
p.710
Chapter 23
Soft
Regulator RMC: Regulator
mode control
register
The self-programming function is disabled in the low consumption current mode. p.710
− Be sure to set FFH to 000C2H (000C2H/010C2H when the boot swap operation is
used).
p.712
000C0H/010C0H Set the same value as 000C0H to 010C0H when the boot swap operation is used
because 000C0H is replaced by 010C0H.
p.712
000C1H/010C1H Set the same value as 000C1H to 010C1H when the boot swap operation is used
because 000C1H is replaced by 010C1H.
p.712
000C2H/010C2H Set FFH to 010C2H when the boot swap operation is used because 000C2H is
replaced by 010C2H.
p.712
000C3H/010C3H Set the same value as 000C3H to 010C3H when the boot swap operation is used
because 000C3H is replaced by 010C3H.
p.713
000C0H/010C0H The watchdog timer continues its operation during self-programming of the flash
memory and EEPROM emulation. During processing, the interrupt acknowledge
time is delayed. Set the overflow time and window size taking this delay into
consideration.
p.714
Be sure to set bits 7 to 1 to “1”. p.714
000C1H/010C1H
Even when the LVI default start function is used, if it is set to LVI operation
prohibition by the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
starts after reset release. There is a period when low-voltage detection cannot be
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
μ
s
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
p.714
000C3H/010C3H Bits 7 and 0 (OCDENSET and OCDERSD) can only be specified a value.
Be sure to set 000010B to bits 6 to 1.
p.715
Chapter 24
Soft
Option
byte
Setting of option
byte
To specify the option byte by using assembly language, use OPT_BYTE as the
relocation attribute name of the CSEG pseudo instruction. To specify the option byte
to 010C0H to 010C3H in order to use the boot swap function, use the relocation
attribute AT to specify an absolute address.
p.716
Chapter 25
Hard
Flash
memory
Security settings After the security setting for the batch erase is set, erasure cannot be performed for
the device.
In addition, even if a write command is executed, data different from that which has
already been written to the flash memory cannot be written, because the erase
command is disabled.
p.728
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Hard
The self-programming function cannot be used when the CPU operates with the
subsystem clock.
p.731
In the self-programming mode, call the self-programming start library (FlashStart). p.731
To prohibit an interrupt during self-programming, in the same way as in the normal
operation mode, execute the self-programming library in the state where the IE flag
is cleared (0) by the DI instruction.
To enable an interrupt, clear (0) the interrupt mask flag to accept in the state where
the IE flag is set (1) by the EI instruction, and then execute the self-programming
library.
p.731
The self-programming function is disabled in the low consumption current mode. For
details of the low consumption current mode, see CHAPTER 23 REGULATOR.
p.731
Flash memory
programming by
self-
programming
Disable DMA operation (DENn = 0) during the execution of self programming library
functions.
p.731
Chapter 25
Soft
Flash
memory
Flash shield
window function
If the rewrite-prohibited area of the boot cluster 0 overlaps with the flash shield
window range, prohibition to rewrite the boot cluster 0 takes priority.
p.735
The 78K0R/KG3 has an on-chip debug function, which is provided for development
and evaluation. Do not use the on-chip debug function in products designated for
mass production, because the guaranteed number of rewritable times of the flash
memory may be exceeded when this function is used, and product reliability
therefore cannot be guaranteed. NEC Electronics is not liable for problems
occurring when the on-chip debug function is used.
p.736
Chapter 26
Hard
On-chip
debug
function
Connecting QB-
MINI2 to
78K0R/KG3
When communicating in 2-line mode, a clock with a frequency of half that of the CPU
clock frequency is output from the TOOL1 pin. A resistor or ferrite bead can be used
as a countermeasure against fluctuation of the power supply caused by that clock.
p.736
Addition The value read from the BCDADJ register varies depending on the value of the A
register when it is read and those of the CY and AC flags. Therefore, execute the
instruction <3> after the instruction <2> instead of executing any other instructions.
To perform BCD correction in the interrupt enabled state, saving and restoring the A
register is required within the interrupt function. PSW (CY flag and AC flag) is
restored by the RETI instruction.
p.740
Chapter 27
Soft
BCD
correction
circuit
Subtraction The value read from the BCDADJ register varies depending on the value of the A
register when it is read and those of the CY and AC flags. Therefore, execute the
instruction <3> after the instruction <2> instead of executing any other instructions.
To perform BCD correction in the interrupt enabled state, saving and restoring the A
register is required within the interrupt function. PSW (CY flag and AC flag) is
restored by the RETI instruction.
p.741
Chapter 28
Soft
Instruction
set
PREFIX
instruction
Set the ES register value with MOV ES, A, etc., before executing the PREFIX
instruction.
p.745
Chapter 29
Hard
Electrical
specifications
(standard
products)
− The 78K0R/KG3 has an on-chip debug function, which is provided for development
and evaluation. Do not use the on-chip debug function in products designated for
mass production, because the guaranteed number of rewritable times of the flash
memory may be exceeded when this function is used, and product reliability
therefore cannot be guaranteed. NEC Electronics is not liable for problems
occurring when the on-chip debug function is used.
p.763
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Cautions Page
pp.763,
Absolute
maximum ratings
Product quality may suffer if the absolute maximum rating is exceeded even
momentarily for any parameter. That is, the absolute maximum ratings are rated
values at which the product is on the verge of suffering physical damage, and
therefore the product must be used under conditions that ensure that the absolute
maximum ratings are not exceeded.
764
p.765
When using the X1 oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current
flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
p.765
X1 oscillator
characteristics
Since the CPU is started by the internal high-speed oscillation clock after a reset
release, check the X1 clock oscillation stabilization time using the oscillation
stabilization time counter status register (OSTC) by the user. Determine the
oscillation stabilization time of the OSTC register and oscillation stabilization time
select register (OSTS) after sufficiently evaluating the oscillation stabilization time
with the resonator to be used.
p.767
When using the XT1 oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current
flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
p.767
XT1 oscillator
characteristics
The XT1 oscillator is designed as a low-amplitude circuit for reducing power
consumption, and is more prone to malfunction due to noise than the X1 oscillator.
Particular care is therefore required with the wiring method when the XT1 clock is
used.
pp.768
The oscillator constants shown above are reference values based on evaluation in a
specific environment by the resonator manufacturer. If it is necessary to optimize the
oscillator characteristics in the actual application, apply to the resonator manufacturer
for evaluation on the implementation circuit.
When doing so, check the conditions for using the AMPH bit, RMC register, and
whether to enter or exit the STOP mode.
The oscillation voltage and oscillation frequency only indicate the oscillator
characteristic. Use the 78K0R/KG3 so that the internal operation conditions are within
the specifications of the DC and AC characteristics.
to 771
Chapter 29
Hard
Electrical
specifications
(standard
products)
Recommended
oscillator
constants
The oscillator constants shown above are reference values based on evaluation in a
specific environment by the resonator manufacturer. If it is necessary to optimize the
oscillator characteristics in the actual application, apply to the resonator manufacturer
for evaluation on the implementation circuit.
When doing so, check the conditions for using the RMC register, and whether to
enter or exit the STOP mode.
The oscillation voltage and oscillation frequency only indicate the oscillator
characteristic. Use the 78K0R/KG3 so that the internal operation conditions are within
the specifications of the DC and AC characteristics.
p.772
APPENDIX B LIST OF CAUTIONS
User’s Manual U17894EJ9V0UD
930
(31/35)
Chapter
Classification
Function Details of
Function
Cautions Page
P02 to P04, P43, P45, P142 to P144 do not output high level in N-ch open-drain
mode.
p.773
The maximum value of VIH of pins P02 to P04, P43, P45, and P142 to P144 is VDD,
even in the N-ch open-drain mode.
pp.775,
776
DC
characteristics
For P122/EXCLK, the value of VIH and VIL differs according to the input port mode or
external clock mode. Make sure to satisfy the DC characteristics of EXCLK in
external clock input mode.
pp.775,
776
CLKOUT output is not used during CLKOUT asynchronous operation, but a CPU
wait occurs according to the setting of bits 4 and 5 (EW0, EW1) of the memory
expansion mode control register (MEM). When fCLK is sufficiently high, insert a wait
by setting the EW0 and EW1 bits.
p.798
Hard
External bus
interface
Do not use the WAIT pin during CLKOUT asynchronous operation.
Use the separate bus mode during CLKOUT asynchronous operation.
p.798
During
communication
at same potential
(UART mode)
(dedicated baud
rate generator
output)
Select the normal input buffer for RxDi and the normal output mode for TxDi by
using the PIMg and POMg registers.
p.800
During
communication
at same potential
(CSI mode)
(master mode,
SCKp... internal
clock output)
Select the normal input buffer for SIj and the normal output mode for SOj and SCKj
by using the PIMg and POMg registers.
p.801
During
communication
at same potential
(CSI mode)
(slave mode,
SCKp... external
clock input)
Select the normal input buffer for SIj and SCKj and the normal output mode for SOj
by using the PIMg and POMg registers.
p.802
During
communication
at same potential
(simplified I2C
mode)
Select the normal input buffer and the N-ch open-drain output (VDD tolerance) mode
for SDAr and the normal output mode for SCLr by using the PIMg and POMg
registers.
p.805
pp.806,
Chapter 29
Soft
Electrical
specifications
(standard
products)
During
communication
at different
potential (2.5 V,
3 V) (UART
mode)
(dedicated baud
rate generator
output)
Select the TTL input buffer for RxDq and the N-ch open-drain output (VDD tolerance)
for TxDq by using the PIMg and POMg registers. 807, 809
APPENDIX B LIST OF CAUTIONS
User’s Manual U17894EJ9V0UD 931
(32/35)
Chapter
Classification
Function Details of
Function
Cautions Page
pp.810,
During
communication
at different
potential (2.5 V,
3 V) (CSI mode)
(master mode,
SCKp... internal
clock output)
Select the TTL input buffer for SIp and the N-ch open-drain output (VDD tolerance)
mode for SOp and SCKp by using the PIMg and POMg registers. 811, 812
pp.814,
During
communication
at different
potential (2.5 V,
3 V) (CSI mode)
(slave mode,
SCKp... external
clock input)
Select the TTL input buffer for SIp and SCKp and the N-ch open-drain output (VDD
tolerance) mode for SOp by using the PIMg and POMg registers. 815
Chapter 29
Soft
Electrical
specifications
(standard
products)
During
communication
at different
potential (2.5 V,
3 V) (simplified
I2C mode)
Select the TTL input buffer and the N-ch open-drain output (VDD tolerance) mode for
SDAr and the N-ch open-drain output (VDD tolerance) mode for SCLr by using the
PIMg and POMg registers.
pp.816,
817
− The 78K0R/KG3 has an on-chip debug function, which is provided for development
and evaluation. Do not use the on-chip debug function in products designated for
mass production, because the guaranteed number of rewritable times of the flash
memory may be exceeded when this function is used, and product reliability
therefore cannot be guaranteed. NEC Electronics is not liable for problems
occurring when the on-chip debug function is used.
p.827
pp.827,
Absolute
maximum ratings
Product quality may suffer if the absolute maximum rating is exceeded even
momentarily for any parameter. That is, the absolute maximum ratings are rated
values at which the product is on the verge of suffering physical damage, and
therefore the product must be used under conditions that ensure that the absolute
maximum ratings are not exceeded.
828
p.829
When using the X1 oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current
flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
p.829
Chapter 30
Hard
Electrical
specifications
((A) grade
products)
X1 oscillator
characteristics
Since the CPU is started by the internal high-speed oscillation clock after a reset
release, check the X1 clock oscillation stabilization time using the oscillation
stabilization time counter status register (OSTC) by the user. Determine the
oscillation stabilization time of the OSTC register and oscillation stabilization time
select register (OSTS) after sufficiently evaluating the oscillation stabilization time
with the resonator to be used.
APPENDIX B LIST OF CAUTIONS
User’s Manual U17894EJ9V0UD
932
(33/35)
Chapter
Classification
Function Details of
Function
Cautions Page
When using the XT1 oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current
flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
p.831
XT1 oscillator
characteristics
The XT1 oscillator is designed as a low-amplitude circuit for reducing power
consumption, and is more prone to malfunction due to noise than the X1 oscillator.
Particular care is therefore required with the wiring method when the XT1 clock is
used.
p.831
pp.832,
The oscillator constants shown above are reference values based on evaluation in a
specific environment by the resonator manufacturer. If it is necessary to optimize the
oscillator characteristics in the actual application, apply to the resonator
manufacturer for evaluation on the implementation circuit.
When doing so, check the conditions for using the AMPH bit, RMC register, and
whether to enter or exit the STOP mode.
The oscillation voltage and oscillation frequency only indicate the oscillator
characteristic. Use the 78K0R/KG3 so that the internal operation conditions are
within the specifications of the DC and AC characteristics.
to 835
Recommended
oscillator
constants
The oscillator constants shown above are reference values based on evaluation in a
specific environment by the resonator manufacturer. If it is necessary to optimize the
oscillator characteristics in the actual application, apply to the resonator
manufacturer for evaluation on the implementation circuit.
When doing so, check the conditions for using the RMC register, and whether to
enter or exit the STOP mode.
The oscillation voltage and oscillation frequency only indicate the oscillator
characteristic. Use the 78K0R/KG3 so that the internal operation conditions are
within the specifications of the DC and AC characteristics.
p.836
P02 to P04, P43, P45, P142 to P144 do not output high level in N-ch open-drain
mode.
pp.837,
838
The maximum value of VIH of pins P02 to P04, P43, P45, and P142 to P144 is VDD,
even in the N-ch open-drain mode.
pp.839,
840
DC
characteristics
For P122/EXCLK, the value of VIH and VIL differs according to the input port mode or
external clock mode. Make sure to satisfy the DC characteristics of EXCLK in
external clock input mode.
pp.839,
840
CLKOUT output is not used during CLKOUT asynchronous operation, but a CPU
wait occurs according to the setting of bits 4 and 5 (EW0, EW1) of the memory
expansion mode control register (MEM). When fCLK is sufficiently high, insert a wait
by setting the EW0 and EW1 bits.
p.861
Hard
External bus
interface
Do not use the WAIT pin during CLKOUT asynchronous operation.
Use the separate bus mode during CLKOUT asynchronous operation.
p.861
Chapter 30
Soft
Electrical
specifications
((A) grade
products)
During
communication
at same potential
(UART mode)
(dedicated baud
rate generator
output)
Select the normal input buffer for RxDi and the normal output mode for TxDi by using
the PIMg and POMg registers.
p.863
APPENDIX B LIST OF CAUTIONS
User’s Manual U17894EJ9V0UD 933
(34/35)
Chapter
Classification
Function Details of
Function
Cautions Page
During
communication
at same potential
(CSI mode)
(master mode,
SCKp... internal
clock input)
Select the normal input buffer for SIj and the normal output mode for SOj and SCKj
by using the PIMg and POMg registers.
p.864
During
communication
at same potential
(CSI mode)
(slave mode,
SCKp... external
clock input)
Select the normal input buffer for SIj and SCKj and the normal output mode for SOj
by using the PIMg and POMg registers.
p.865
During
communication
at same potential
(simplified I2C
mode)
Select the normal input buffer and the N-ch open-drain output (VDD tolerance) mode
for SDAr and the normal output mode for SCLr by using the PIMg and POMg
registers.
p.868
pp.869,
During
communication
at different
potential (2.5 V,
3 V) (UART
mode)
(dedicated baud
rate generator
output)
Select the TTL input buffer for RxDq and the N-ch open-drain output (VDD tolerance)
mode for TxDq by using the PIMg and POMg registers. 870, 872
pp.873,
During
communication
at different
potential (2.5 V,
3 V) (CSI mode)
(master mode,
SCKp... internal
clock output)
Select the TTL input buffer for SIp and the N-ch open-drain output (VDD tolerance)
mode for SOp and SCKp by using the PIMg and POMg registers. 874, 875
pp.877,
During
communication
at different
potential (2.5 V,
3 V) (CSI mode)
(slave mode,
SCKp... external
clock input)
Select the TTL input buffer for SIp and SCKp and the N-ch open-drain output (VDD
tolerance) mode for SOp by using the PIMg and POMg registers. 878
Chapter 30
Soft
Electrical
specifications
((A) grade
products)
During
communication
at different
potential (2.5 V,
3 V) (simplified
I2C mode)
Select the TTL input buffer and the N-ch open-drain output (VDD tolerance) mode for
SDAr and the N-ch open-drain output (VDD tolerance) mode for SCLr by using the
PIMg and POMg registers.
pp.879,
880
APPENDIX B LIST OF CAUTIONS
User’s Manual U17894EJ9V0UD
934
(35/35)
Chapter
Classification
Function Details of
Function
Cautions Page
For soldering methods and conditions other than those recommended below,
contact an NEC Electronics sales representative.
p.891
Chapter 32
Hard
RECOMM
ENDED
SOLDERI
NG
CONDITIO
NS
−
Do not use different soldering methods together (except for partial heating). pp.891,
892
User’s Manual U17894EJ9V0UD 935
APPENDIX C REVISION HISTORY
C.1 Major Revisions in This Edition
(1/5)
Page Description Classification
Throughout
− Change of status of (A) grade products of the expanded-specification products from under
development to mass production
(b)
CHAPTER 1 OUTLINE
p.18 Change of 1.1 Differences Between Conventional-Specification Products (
μ
PD78F116x) and
Expanded-Specification Products (
μ
PD78F116xA)
(c)
CHAPTER 3 CPU ARCHITECTURE
p.62 Change of Table 3-2. Internal ROM Capacity (a)
pp.67 to 73 Change of Figure 3-9 to Figure 3-15 Correspondence Between Data Memory and
Addressing
(c)
p.75 Addition of Caution to 3.2.1 (3) Stack pointer (SP) (c)
CHAPTER 4 PORT FUNCTIONS
p.139 Change of Figure 4-30. Block Diagram of P110 and P111 (c)
CHAPTER 5 EXTERNAL BUS INTERFACE
p.175 Addition of 5.6 Number of Instructed Wait Cycles According to External Wait Cycles (c)
CHAPTER 6 CLOCK GENERATOR
pp.189, 190 Addition of fMAINC to Figure 6-1. Block Diagram of Clock Generator and Remark (c)
p.191 Change of description of AMPH bit in Figure 6-2. Format of Clock Operation Mode Control
Register (CMC)
(c)
p.199 Change of description of RTCEN bit in Figure 6-7. Format of Peripheral Enable Register (1/2) (c)
p.201 Change of Caution 5 in Figure 6-8. Format of Operation Speed Mode Control Register
(OSMC) and addition of Caution 4
(c)
p.221 Change of description of AMPH bit in Table 6-4. CPU Clock Transition and SFR Register
Setting Examples (1/4) (2) and addition of Remark
(c)
p.222 Change of description of AMPH bit in Table 6-4. CPU Clock Transition and SFR Register
Setting Examples (2/4) (4) and addition of Remark
(c)
p.224 Change of (9) CPU clock changing from subsystem clock (D) to high-speed system clock
(C) in Table 6-4. CPU Clock Transition and SFR Register Setting Examples (4/4)
(c)
p.224 Change of (11) • STOP mode (H) set while CPU is operating with internal high-speed
oscillation clock (B) • STOP mode (I) set while CPU is operating with high-speed system
clock (C) in Table 6-4. CPU Clock Transition and SFR Register Setting Examples (4/4)
(c)
p.227 Change of Table 6-6. Maximum Time Required for Main System Clock Switchover (c)
p.227 Change of Table 6-8. Maximum Number of Clocks Required in Type 2 (c)
p.228 Change of Table 6-9. Maximum Number of Clocks Required in Type 3 and addition of Remark (c)
CHAPTER 7 TIMER ARRAY UNIT
p.232 Change of Figure 7-1. Block Diagram of Timer Array Unit (c)
p.239 Change of description of CKS0n bit in Figure 7-6. Format of Timer Mode Register 0n (TMR0n)
(1/3)
(a)
Remark “Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD
936
(2/5)
Page Description Classification
CHAPTER 7 TIMER ARRAY UNIT (continuation)
p.247 Change of Figure 7-13. Start Timing (In One-count Mode) (a)
p.248 Change of Figure 7-14. Start Timing (In Capture & One-count Mode) (a)
p.254 Change of description of ISC1 and ISC0 bits in Figure 7-21. Format of Input Switch Control
Register (ISC)
(a)
CHAPTER 8 REAL-TIME COUNTER
p.309 Change of Table 8-1. Configuration of Real-Time Counter (c)
p.311 Change of 8.3 Registers Controlling Real-Time Counter (c)
p.313 Change of description of AMPM bit in Figure 8-3. Format of Real-Time Counter Control
Register 0 (RTCC0)
(c)
p.318 Change of description of (7) Minute count register (MIN) (c)
p.318 Change of description of (8) Hour count register (HOUR) (c)
p.323 Addition of description of DEV bit to Figure 8-14. Format of Watch Error Correction Register
(SUBCUD)
(c)
p.325 Addition of 8.3 (17) Port mode registers 1, 3 (PM1, PM3) (c)
p.326 Change of Figure 8-19. Procedure for Starting Operation of Real-Time Counter and addition of
Note
(c)
p.331 Addition of Caution to 8.4.5 1 Hz output of real-time counter (c)
p.331 Change of 8.4.6 32.768 kHz output of real-time counter (c)
p.331 Change of 8.4.7 512 Hz, 16.384 kHz output of real-time counter (c)
CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
p.347 Change of Remark in 10.4.1 Operation as output pin (c)
p.347 Change of Figure 10-4. Remote Control Output Application Example (c)
CHAPTER 11 A/D CONVERTER
p.352 Change of Table 11-2. Settings of ADCS and ADCE (c)
p.352 Change of Figure 11-5. Timing Chart When A/D voltage Comparator Is Used (c)
p.375 Change of 11.7 Cautions for A/D Converter (2) Reducing current when A/D converter is
stopped
(c)
p.379 Addition of 11.7 (13) Starting the A/D converter (c)
CHAPTER 12 D/A CONVERTER
p.387 Change of 12.4.3 Cautions (1) (c)
p.387 Change of 12.4.3 Cautions (7) (c)
CHAPTER 13 SERIAL ARRAY UNIT
p.400 Change of MDmn0 bit in Figure 13-6. Format of Serial Mode Register mn (SMRmn) (2/2) (c)
p.402 Addition of Note to Figure 13-7. Format of Serial Communication Operation Setting Register
mn (SCRmn) (2/3)
(c)
p.404 Addition of Caution to Figure 13-8. Format of Serial Data Register mn (SDRmn) (c)
p.414 Change of description of Figure 13-17. Format of Input Switch Control Register (ISC) (a)
p.431 Change of interrupt in 13.5.2 Master reception (c)
p.432 Change of Figure 13-32. Example of Contents of Registers for Master Reception of 3-Wire
Serial I/O (CSI00, CSI01, CSI10, CSI20)
(c)
p.434 Change of Figure 13-35. Procedure for Resuming Master Reception (c)
Remark “Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD 937
(3/5)
Page Description Classification
CHAPTER 13 SERIAL ARRAY UNIT (continuation)
p.436 Change of Figure 13-37. Flowchart of Master Reception (in Single-Reception Mode) (c)
p.437 Addition of Figure 13-38. Timing Chart of Master Reception (in Continuous Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
(c)
p.438 Addition of Figure 13-39. Flowchart of Master Reception (in Continuous Reception Mode) (c)
p.451 Change of Figure 13-51. Procedure for Resuming Slave Transmission (b)
p.453 Change of Figure 13-53. Flowchart of Slave Transmission (in Single-Transmission Mode) (c)
p.455 Change of Figure 13-55. Flowchart of Slave Transmission (in Continuous Transmission
Mode)
(c)
p.457 Change of Figure 13-56. Example of Contents of Registers for Slave Reception of 3-Wire
Serial I/O (CSI00, CSI01, CSI10, CSI20)
(c)
p.459 Change of Figure 13-59. Procedure for Resuming Slave Reception (c)
p.461 Change of Figure 13-61. Flowchart of Slave Reception (in Single-Reception Mode) (c)
p.463 Addition of Caution to Figure 13-62. Example of Contents of Registers for Slave
Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20)
(c)
p.464 Addition of Caution to Figure 13-63. Initial Setting Procedure for Slave Transmission/Reception (c)
p.466 Change of Figure 13-65. Procedure for Resuming Slave Transmission/Reception (c)
p.468 Change of Figure 13-67. Flowchart of Slave Transmission/Reception (in Single-
Transmission/Reception Mode)
(c)
p.470 Change of Figure 13-69. Flowchart of Slave Transmission/Reception (in Continuous
Transmission/Reception Mode)
(c)
p.486 Change of Figure 13-79. Example of Contents of Registers for UART Reception of UART
(UART0, UART1, UART2, UART3) (1/2)
(c)
p.489 Change of Figure 13-82. Procedure for Resuming UART Reception (c)
p.491 Change of Figure 13-84. Flowchart of UART Reception (c)
p.505 Change of 13.7 Operation of Simplified I2C (IIC10, IIC20) Communication (c)
p.506 Change of transfer rate in 13.7.1 Address field transmission (b)
p.511 Change of transfer rate in 13.7.2 Data transmission (b)
p.514 Change of error detection flag and transfer rate in 13.7.3 Data reception (b)
p.519 Addition of Caution to 13.7.5 Calculating transfer rate (c)
p.519 Change of Remark in 13.7.5 Calculating transfer rate (c)
p.522 Addition of Figure 13-105. Processing Procedure in Case of Parity Error or Overrun Error (c)
CHAPTER 14 SERIAL INTERFACE IIC0
p.539 Change of description of STT0 bit in Figure 14-6. Format of IIC Control Register 0 (IICC0) (3/4) (c)
CHAPTER 16 DMA CONTROLLER
p.611 Addition of Note to Figure 16-4. Format of DMA Mode Control Register n (DMCn) (1/2) (c)
p.617 Change of description in 16.5.1 CSI consecutive transmission (c)
p.618 Change of description in Figure 16-7. Setting Example of CSI Consecutive Transmission (c)
pp.619, 620 Addition of 16.5.2 CSI master reception (c)
pp.621, 622 Addition of 16.5.3 CSI transmission/reception (c)
p.627 Change of description in 16.5.6 Holding DMA transfer pending by DWAITn (c)
Remark “Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD
938
(4/5)
Page Description Classification
CHAPTER 16 DMA CONTROLLER (continuation)
p.627 Addition of Note to Figure 16-12. Example of Setting for Holding DMA Transfer Pending by
DWAITn
(c)
pp.628, 629 Change of 16.5.7 Forced termination by software (c)
p.630 Change of (1) Priority of DMA in 16.6 Cautions on Using DMA Controller (c)
p.631 Change of (2) DMA response time in 16.6 Cautions on Using DMA Controller (c)
p.632 Change of description in (4) DMA pending instruction in 16.6 Cautions on Using DMA
Controller
(c)
CHAPTER 17 INTERRUPT FUNCTIONS
p.636 Change of (B) External maskable interrupt (INTPn) in Figure 17-1. Basic Configuration of
Interrupt Function
(c)
p.637 Addition of (C) External maskable interrupt (INTKR) to Figure 17-1. Basic Configuration of
Interrupt Function
(c)
p.654 Addition of instruction to 17.4.4 Interrupt request hold (c)
CHAPTER 18 KEY INTERRUPT FUNCTION
p.655 Change of Table 18-2. Configuration of Key Interrupt (c)
p.656 Addition of 18.3 (2) Port mode register 7 (PM7) (c)
CHAPTER 27 BCD CORRECTION CIRCUIT
p.740 Change of 27.3 BCD Correction Circuit Operation (a)
CHAPTER 28 INSTRUCTION SET
p.745 Change of description in 28.1.4 PREFIX instruction (c)
p.761 Change of Clocks of BT Mnemonic in Table 28-5. Operation List (16/17) (c)
p.762 Change of Clocks of BF Mnemonic in Table 28-5. Operation List (17/17) (c)
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
p.765 Deletion of Remark in X1 Oscillator Characteristics (a)
p.767 Deletion of Remark in XT1 Oscillator Characteristics (a)
pp.768, 770,
772
Change of Caution in Recommended Oscillator Constants (c)
pp.769, 771 Addition of KYOCERA KINSEKI Co., Ltd. to Recommended Oscillator Constants (c)
pp.780 to 788 Addition of Remark to Supply current in DC Characteristics (c)
p.801 Change of (b) During communication at same potential (CSI mode) (master mode, SCKp...
internal clock output) in Serial interface: Serial array unit
(b)
p.802 Change of (c) During communication at same potential (CSI mode) (slave mode, SCKp...
external clock input) in Serial interface: Serial array unit
(b)
p.804 Addition of Note to (d) During communication at same potential (simplified I2C mode) in Serial
interface: Serial array unit
(c)
pp.810, 811 Change of (f) During communication at different potential (2.5 V, 3 V) (CSI mode) (master
mode, SCKp... internal clock output) in Serial interface: Serial array unit
(b)
p.813 Change of (g) During communication at different potential (2.5 V, 3 V) (CSI mode) (slave
mode, SCKp... external clock input) in Serial interface: Serial array unit
(b)
p.816 Addition of Note to (h) During communication at different potential (2.5 V, 3 V) (simplified I2C
mode) in Serial interface: Serial array unit
(b)
Remark “Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD 939
(5/5)
Page Description Classification
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) (continuation)
p.826 Change of Number of rewrites of Expanded-specification products in Flash Memory
Programming Characteristics
(c)
CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)
Throughout Deletion of (TARGET) (d)
p.829 Deletion of Remark in X1 Oscillator Characteristics (a)
p.831 Deletion of Remark in XT1 Oscillator Characteristics (a)
pp.832, 834,
836
Change of Caution in Recommended Oscillator Constants (c)
pp.833, 835 Addition of KYOCERA KINSEKI Co., Ltd. to Recommended Oscillator Constants (c)
pp.844 to
852
Addition of Remark to Supply current in DC Characteristics (c)
p.864 Change of (b) During communication at same potential (CSI mode) (master mode, SCKp...
internal clock output) in Serial interface: Serial array unit
(b)
p.865 Change of (c) During communication at same potential (CSI mode) (slave mode, SCKp...
external clock input) in Serial interface: Serial array unit
(b)
p.867 Addition of Note to (d) During communication at same potential (simplified I2C mode) in Serial
interface: Serial array unit
(c)
pp.873, 874 Change of (f) During communication at different potential (2.5 V, 3 V) (CSI mode) (master
mode, SCKp... internal clock output) in Serial interface: Serial array unit
(b)
p.876 Change of (g) During communication at different potential (2.5 V, 3 V) (CSI mode) (slave
mode, SCKp... external clock input) in Serial interface: Serial array unit
(b)
p.879 Addition of Note to (h) During communication at different potential (2.5 V, 3 V) (simplified I2C
mode) in Serial interface: Serial array unit
(b)
Remark “Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD
940
C.2 Revision History of Preceding Editions
Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition.
(1/24)
Edition Description Chapter
Addition of
μ
PD78F1167 and
μ
PD78F1168 to ROM, RAM capacities
Change of 1.3 Ordering Information
Addition of
μ
PD78F1167 and
μ
PD78F1168 to 1.6 Outline of Functions
CHAPTER 1 OUTLINE
Addition of discription to 2.2.5 (2) (c) TOOL1
Change of discription in Table 2-2 Connection of Unused Pins
CHAPTER 2 PIN
FUNCTIONS
Deletion of Note 2 of the previous edition from Figure 3-5 Memory Map
(
μ
PD78F1166)
Addition of Figure 3-6 Memory Map (
μ
PD78F1167)
Addition of Figure 3-7 Memory Map (
μ
PD78F1168)
Addition of block numbers 00H to FFH to Table 3-1 Correspondence Between
Address Values and Block Numbers of Flash Memory
Addition of
μ
PD78F1167 and
μ
PD78F1168 to Table 3-2 Internal ROM Capacity
Addition of
μ
PD78F1167 and
μ
PD78F1168 to 3.1.2 Mirror area
Addition of
μ
PD78F1167 and
μ
PD78F1168 to Table 3-4 Internal RAM Capacity
Addition of Figure 3-12 Correspondence Between Data Memory and Addressing
(
μ
PD78F1166)
Addition of Figure 3-13 Correspondence Between Data Memory and Addressing
(
μ
PD78F1167)
Addition of Figure 3-14 Correspondence Between Data Memory and Addressing
(
μ
PD78F1168)
Addition of serial output level registers 0 and 1 to Table 3-6 Extended SFR (2nd
SFR) List
CHAPTER 3 CPU
ARCHITECTURE
Addition of Caution 3 to 4.2.2 Port 1
Addition of description to 4.2.3 Port 2
Addition of Caution to 4.2.5 Port 4
Addition of description to 4.2.6 Port 5
Addition of Caution to 4.2.9 Port 8
Addition of description to 4.2.11 Port 12
Addition of Note to 4.3 (2) Port registers (P0 to P8, P11 to P15)
Addition of Note to 4.3 (3) Pull-up resistor option registers (PU0, PU1, PU3 to
PU8, PU12 to PU14)
CHAPTER 4 PORT
FUNCTIONS
Addition of (f) Memory map of
μ
PD78F1167 and (g) Memory map of
μ
PD78F1168, and change of Note in Figure 5-1 Memory Map When Using
External Bus Interface Function
CHAPTER 5
EXTERNAL BUS
INTERFACE
Change of setting in selection of CPU/peripheral hardware clock in 6.3 (5) System
clock control register (CKC) and 6.6.1 (3) Example of setting procedure when
using high-speed system clock as CPU/peripheral hardware clock
Addition of description in 6.3 (8) Internal high-speed oscillator trimming register
(HIOTRM)
2nd edition
Change of Figure 6-14 CPU Clock Status Transition Diagram, and addition of
Note and Remark
CHAPTER 6 CLOCK
GENERATOR
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD 941
(2/24)
Edition Description Chapter
Addition of Tables 6-6 to 6-9 to 6.6.7 Time required for switchover of CPU clock
and main system clock
CHAPTER 6 CLOCK
GENERATOR
Change of bit names of timer mode register 00 (TMR00)
Addition of description in 7.3 (14) Noise filter enable register 1 (NFEN1)
CHAPTER 7 TIMER
ARRAY UNIT
Change of Caution and addition of Remark to 8.3 (4) Real-time counter control
register 2 (RTCC2)
CHAPTER 8 REAL-
TIME COUNTER
Change of Cautions 4 and 5 in 9.4.1 Controlling operation of watchdog timer
Change of Caution in Table 9-3 Setting of Overflow Time of Watchdog Timer
Change of Caution 1 in Table 9-4 Setting Window Open Period of Watchdog
Timer
Addition of Caution to 9.4.4 Setting watchdog timer interval interrupt
CHAPTER 9
WATCHDOG TIMER
Change of settings for ANI1 in Figure 11-9 Format of Analog Input Channel
Specification Register (ADS)
CHAPTER 11 A/D
CONVERTER
Change of register settings, operation procedures, and processing flows
Addition of buffer empty interrupt to [Interrupt function], and [Error detection flag] to
13.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20) and 13.4 Operation of 3-
Wire Serial I/O (CSI00, CSI01, CSI10, CSI20) Communication
Addition of 5-bit data length and receive data and select of reverse to [Data
transmission/reception], and buffer empty interrupt to [Interrupt function], and [Error
detection flag] to 13.1.2 UART (UART0, UART1, UART2, UART3) and 13.5
Operation of UART (UART0, UART1, UART2, UART3) Communication
Addition of [Error detection flag] to 13.1.3 Simplified I2C (IIC10, IIC20) and 13.6
Operation of Simplified I2C (IIC10, IIC20) Communication
Addition of serial output level register m (SOLm) to Table 13-1 Configuration of
Serial Array Unit
Addition of serial output level register 0, 1 (SOL0, 1) to Figures 13-1 Block Diagram
of Serial Array Unit 0 and 13-2 Block Diagram of Serial Array Unit 1
Addition of description of 5-bit data length to 13.2 (2) Lower 8 bits of the serial data
register mn (SDRmn)
Addition of serial output level register m (SOLm) to 13.3 Registers Controlling
Serial Array Unit
Change and addition of Cautions in 13.3 (1) Peripheral enable register 0 (PER0)
Addition of Caution to 13.3 (2) Serial clock select register m (SPSm)
Addition of description to 13.3 (3) Serial mode register mn (SMRmn)
Addition of description of SISmn0 bit to Figure 13-6 Format of Serial Mode
Register mn (SMRmn)
Change of Figure 13-7 Format of Serial Communication Operation Setting
Register mn (SCRmn)
Addition of description to 13.3 (5) Higher 7 bits of the serial data register mn
(SDRmn)
Addition of Caution 2 to Figure 13-8 Format of Serial Data Register mn (SDRmn)
Change of Figure 13-9 Format of Serial Status Register mn (SSRmn)
Addition of description to 13.3 (8) Serial channel enable status register m (SEm)
Change of Figure 13-11 Format of Serial Channel Enable Status Register m
(SEm)
Change of Figure 13-13 Format of Serial Channel Stop Register m (STm)
2nd edition
Addition of description to 13.3 (11) Serial output enable register m (SOEm)
CHAPTER 13 SERIAL
ARRAY UNIT
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD
942
(3/24)
Edition Description Chapter
Addition of description to 13.3 (12) Serial output register m (SOm)
Addition of 13.3 (13) Serial output level register m (SOLm)
Addition of description to 13.3 (15) Noise filter enable register 0 (NFEN0)
Addition of Error detection flag, and change of Transfer rate in 13.4.1 Master
transmission
Addition of MDmn0 bit, change of INTCSlp, and addition of Caution to Figure 13-28
Timing Chart of Master Transmission (in Continuous Transmission Mode)
Addition of Error detection flag, and change of Transfer rate in 13.4.2 Master
reception
Addition of Error detection flag, and change of Interrupt and Transfer rate in 13.4.3
Master transmission/reception
Addition of MDmn0 bit, change of INTCSlp, and addition of Caution to Figure 13-42
Timing Chart of Master Transmission/Reception (in Continuous
Transmission/Reception Mode)
Addition of Error detection flag, and change of Transfer rate in 13.4.4 Slave
transmission
Addition of MDmn0 bit, change of INTCSlp, and addition of Caution to Figure 13-50
Timing Chart of Slave Transmission (in Continuous Transmission Mode)
Addition of Error detection flag, and change of Transfer rate in 13.4.5 Slave
reception
Addition of Error detection flag, and change of Interrupt and Transfer rate in 13.4.6
Slave transmission/reception
Addition of MDmn0 bit, change of INTCSlp, and addition of Caution to Figure 13-64
Timing Chart of Slave Transmission/Reception (in Continuous
Transmission/Reception Mode)
Change of expression in 13.4.7 (1) Master
Addition of Note to 13.4.7 (2) Slave
Addition of Error detection flag, and change of Transfer rate and Data phase in 13.5.1
UART transmission and 13.5.2 UART reception
Addition of MDmn0 bit, change of INTCSlp, and addition of Caution to Figure 13-72
Timing Chart of UART Transmission (in Continuous Transmission Mode)
Addition of Error interrupt and Error detection flag, and change of Transfer rate and
Data phase in 13.5.3 LIN transmission and 13.5.4 LIN reception
Addition of Caution to 13.5.5 (1) Calculating baud rate
Addition of Error detection flag, and change of Transfer rate in 13.6.1 Address field
transmission, 13.6.2 Data transmission, and 13.6.3 Data reception
CHAPTER 13 SERIAL
ARRAY UNIT
Change of Transfer clock in Table 14-2 Selection Clock Setting
Migration of 14.3 (7) I2C transfer clock setting method in the previous edition to
14.5.4 Transfer clock setting method, and addition of description of selection clock
setting method on the slave side
Addition of Table 14-7 Wait Periods
Change of wait time in 14.5.15 (2) When communication reservation function is
disabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 1), and deletion of Table 14-
7 of the previous edition
Addition of descriptions and flow charts to 14.5.17 Communication operations
CHAPTER 14 SERIAL
INTERFACE IIC0
Change of Figure 15-1 Block Diagram of Multiplier
Addition of 15.3 Operation of Multiplier
CHAPTER 15
MULTIPLIER
2nd edition
Addition of description of D/A converter operating status to Table 19-2 Operating
Statuses in STOP Mode
CHAPTER 19
STANDBY FUNCTION
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD 943
(4/24)
Edition Description Chapter
Addition of Note 2 to Figure 20-5 Format of Reset Control Flag Register (RESF) CHAPTER 20 RESET
FUNCTION
Change of value of VPOC CHAPTER 21 POWER-
ON-CLEAR CIRCUIT
Addition of Caution 2 to Figure 22-2 Format of Low-Voltage Detection Register
(LVIM)
CHAPTER 22 LOW-
VOLTAGE DETECTOR
Change of Caution in Figure 23-1 Format of User Option Byte (000C0H/010C0H)
Addition of description and Caution 2 in Figure 23-2 Format of Option Byte
(000C1H/010C1H)
CHAPTER 23 OPTION
BYTE
DC Characteristics
• Change of MIN. value of Input voltage, high
• Change of MAX. value of Input voltage, low
• Change of Max. value of Input leakage current, high
• Change of Max. value of Input leakage current, low
• Addition of D/A output resistance value
AC Characteristics
• Change of value of External main system clock input high-level width, low-level
width
• Change of value of TI00 to TI07 input high-level width, low-level width
• Addition of TO00 to TO07 output frequency
• Addition of PCLBUZ0/1 output frequency
• Addition of figures
Addition of A/D Converter Characteristics
Addition of D/A Converter Characteristics
CHAPTER 25
ELECTRICAL
SPECIFICATIONS
(TARGET)
2nd edition
Addition of APPENDIX A REVISION HISTORY APPENDIX A
REVISION HISTORY
1.1 Features
• Change of status indication of
μ
PD78F1167 and
μ
PD78F1168 to “under planning”
• Addition of On-chip BCD adjustment
• Addition of 8-bit resolution D/A converter
Addition of Caution 2 to 1.4 Pin Configuration (Top View)
Addition of 1.5 78K0R Microcontroller Lineup
Addition of BCD correction circuit and change of direction of arrow on external bus
interface I/O pins in 1.6 Block Diagram
Change of status indication of
μ
PD78F1167 and
μ
PD78F1168 to “under planning” in
1.7 Outline of Functions
CHAPTER 1 OUTLINE
Modification of alternate function of EX25, EX26, SO00, SO01, TxD0, and TxD3
functions in 2.1 (2) Non-port functions
Addition of alternate function description and modification of Caution in 2.2.5 P40 to
P47 (port 4)
Addition of I/O Circuit Type in Table 2-2 Connection of Unused Pins
3rd edition
Addition of Figure 2-1 Pin I/O Circuit List
CHAPTER 2 PIN
FUNCTIONS
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD
944
(5/24)
Edition Description Chapter
Deletion of descriptions of CALLF instruction in CHAPTER 3
Modification of description in 3.1 Memory Space
Addition of Note in Figure 3-5 Memory Map (
μ
PD78F1166) and Figure 3-13
Correspondence Between Data Memory and Addressing (
μ
PD78F1166)
Addition of Note in Figure 3-7 Memory Map (
μ
PD78F1168) and Figure 3-15
Correspondence Between Data Memory and Addressing (
μ
PD78F1168)
Modification of description and addition of diagram example and explanation of PMC
register in 3.1.2 Mirror area
Change of reset value of Hour count register and Alarm hour register in Table 3-5
SFR List
Change of reset value of Day count register and Month count register in Table 3-5
SFR List
Change of reset value of Back ground event control register in Table 3-5 SFR List
Addition of BCD correction carry register and Note to Table 3-5 SFR List
Change of symbols of higher multiplication result storage register and lower
multiplication result storage register in Table 3-5 SFR List
Addition of Regulator mode control register and BCD adjust result register in Table 3-
6 Extended SFR (2nd SFR) List
Addition of SFR name for the lower 8 bits and modifications of R/W attribute and
manipulable bit range for registers SSRmn, SIRmn, SEm, SSm, STm, SPSm, SOEm,
SOLm, TCR0n, TSR0n, TE0, TS0, TT0, TPS0, TO0, TOE0, TOL0, and TOM0 in
Table 3-6 Extended SFR (2nd SFR) List
Change of reset value of Serial output register 0 and Serial output register 1 in Table
3-6 Extended SFR (2nd SFR) List
Change of reset value of Serial output enable register 0 and Serial output enable
register 1 in Table 3-6 Extended SFR (2nd SFR) List
Change of R/W attribute of Timer channel counter register 0n in Table 3-6 Extended
SFR (2nd SFR) List
Addition of 3.3 Instruction Address Addressing
Addition of 3.4 Addressing for Processing Data Addresses
CHAPTER 3 CPU
ARCHITECTURE
Addition of Cautions 1 and 2 to 4.2.1 Port 0
Addition of Cautions 1 and 2 to 4.2.2 Port 1
Addition of Caution to 4.2.4 Port 3
Addition of Cautions 2 and 3 to 4.2.5 Port 4
Modification of Figure 4-28 Block Diagram of P80 to P87 and Figure 4-29 Block
Diagram of P110 and P111
Addition of Caution to 4.2.12 Port 13
Addition of Cautions 1 and 2 to 4.2.13 Port 14
Addition of Caution to Figure 4-39 Format of Port Mode Register
Modification of Note in 4.3 (2) Port registers (P0 to P8, P11 to P15)
Addition of 4.4.4 Connecting to external device with different power supply
voltage (3 V)
CHAPTER 4 PORT
FUNCTIONS
Addition of Note to Figure 5-3 Format of Memory Extension Mode Control
Register (MEM)
Modification of description in 5.6 (5) ASTB pin and (6) EX0 to EX7, EX8 to EX15,
EX16 to EX23, and EX24 to EX31 pins
3rd edition
Modification of Figure 5-9 Example of Synchronous Memory Connection and
Figure 5-10 Example of Asynchronous Memory Connection
CHAPTER 5
EXTERNAL BUS
INTERFACE
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD 945
(6/24)
Edition Description Chapter
Addition of Cautions 3 to Figure 6-3 Format of Clock Operation Status Control
Register (CSC)
Modification of description in 6.3 (3) Oscillation stabilization time counter status
register (OSTC)
Modification of Cautions 2 in Figure 6-4 Format of Oscillation Stabilization Time
Counter Status Register (OSTC)
Modification of Cautions 5 in Figure 6-5 Format of Oscillation Stabilization Time
Select Register (OSTS)
Modification of Cautions 3 in Figure 6-6 Format of System Clock Control
Register (CKC)
Modification of Cautions 1 to 3 in Figure 6-8 Format of Operation Speed Mode
Control Register (OSMC)
Addition of Figure 6-14 Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte:
LVIOFF = 1)) and description
Addition of Figure 6-15 Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Enabled Is Set (Option Byte:
LVIOFF = 0)) and description
Modification of Cautions 1 in 6.6.1 (1) Example of setting procedure when
oscillating the X1 clock
Modification of register name in title of 6.6.1 (2) <2>
Addition of <2> to 6.6.1 (4) (b)
Addition of Caution to 6.6.2 (2) (b)
Modification of Caution in 6.6.3 Example of controlling subsystem clock
Modification of Caution in 6.6.3 (1) Example of setting procedure when oscillating
the subsystem clock
Modification of bit name in 6.6.3 (2) <2> Setting the subsystem clock as the
source clock of the CPU clock (CKC register)
Modification of Caution in 6.6.3 (2) Example of setting procedure when using the
subsystem clock as the CPU clock
Modification of register name in title of 6.6.3 (3) <2>
Addition of an arrow from (C) to (B) in Figure 6-16 CPU Clock Status Transition
Diagram
Modification of Table 6-4 CPU Clock Transition and SFR Register Setting
Examples
Addition of description to Table 6-5 Changing CPU Clock
Modification of description in 6.6.7 Time required for switchover of CPU clock and
main system clock
Deletion of Caution in Table 6-8 Maximum Number of Clocks Required in Type 2
CHAPTER 6 CLOCK
GENERATOR
Change of bit name of TIS0n0 and TIS0n1 bits to CIS0n0 and CIS0n1 bits in
CHAPTER 7
Addition of description in 7.1.1 Functions of each channel when it operates
independently
Addition of description in 7.1.2 Functions of each channel when it operates with
another channel
Addition of description and table to 7.2 (1) Timer/counter register 0n (TCR0n)
3rd edition
Deletion of Caution in 7.2 (2) Timer data register 0n (TDR0n)
CHAPTER 7 TIMER
ARRAY UNIT
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD
946
(7/24)
Edition Description Chapter
Addition of SFR name for the lower 8 bits of registers TSR0n, TE0, TS0, TT0, TPS0,
TO0, TOE0, TOL0, and TOM0 in 7.3 Registers Controlling Timer Array Unit
Addition of description in 7.3 (2) Timer clock select register 0 (TPS0)
Modification of description and change of setting in Figure 7-6 Format of Timer
Mode Register 0n (TMR0n)
Change of R/W attribute in Figure 7-9 Format of Timer Channel Start Register 0
(TS0)
Change of R/W attribute in Figure 7-10 Format of Timer Channel Stop Register 0
(TT0)
Modification of description in 7.3 (9) Timer output enable register 0 (TOE0)
Modification of description in 7.3 (10) Timer output register 0 (TO0)
Modification of description in 7.3 (11) Timer output level register 0 (TOL0)
Modification of Figure 7-16 Format of Input Switch Control Register (ISC)
Modification of Figure 7-20 Example of Basic Timing of Operation as Interval
Timer/Square Wave Output
Addition of Caution to 7.5.4 Operation as input pulse interval measurement
Modification of Figure 7-31 Block Diagram of Operation as Input Pulse Interval
Measurement
Addition of Caution to 7.5.5 Operation as input signal high-/low-level width
measurement
Modification of description in 7.6.1 Operation as PWM function
Change of Remark in 7.6 Operation of Plural Channels of Timer Array Unit
Modification of description in Figure 7-43 Operation Procedure When PWM
Function Is Used
Modification of Figure 7-44 Block Diagram of Operation as One-Shot Pulse
Output Function
Modification of description in 7.6.3 Operation as multiple PWM output function
CHAPTER 7 TIMER
ARRAY UNIT
Modification of Caution and addition of Remark in Figure 8-2 Format of Peripheral
Enable Register 0 (PER0)
Modification of Caution in 8.3 (2) Real-time counter control register 0 (RTCC0)
Modification of Caution in 8.3 (3) Real-time counter control register 1 (RTCC1)
Addition of Remark in Figure 8-4 Format of Real-Time Counter Control Register
1 (RTCC1) and Figure 8-21 Alarm Setting Procedure
Change of reset value and addition of description in 8.3 (8) Hour count register
(HOUR)
Change of reset value of 8.3 (9) Day count register (DAY)
Change of reset value of 8.3 (11) Month count register (MONTH)
Change of reset value of 8.3 (15) Alarm hour register (ALARMWH)
CHAPTER 8 REAL-
TIME COUNTER
Addition of Caution to 11.3 (7) Port mode registers 2 and 15 (PM2, PM15) CHAPTER 11 A/D
CONVERTER
Addition of Caution on PER0 and SPSm registers in 13.4 Operation of 3-Wire
Serial I/O (CSI00, CSI01, CSI10, CSI20) Communication through 13.6 Operation
of Simplified I2C (IIC10, IIC20) Communication
Addition of SFR name for the lower 8 bits of registers SSRmn, SIRmn, Semn, SSm,
STm, SPSm, some and SOLm in 13.3 Registers Controlling Serial Array Unit
3rd edition
Change of R/W attribute of registers SIRmn, SSm, and STm in 13.3 Registers
Controlling Serial Array Unit.
CHAPTER 13 SERIAL
ARRAY UNIT
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD 947
(8/24)
Edition Description Chapter
Change of reset value of 13.3 (12) Serial output register m (Som).
Modification of bit 0 setting in Figure 13-36 (d) Serial mode register mn (SMRmn).
Deletion of description on overrun error in 13.6 Operation of Simplified I2C (IIC10,
IIC20) Communication.
Deletion of description on overrun error in 13.6.1 Address field transmission.
Deletion of description on overrun error in 13.6.2 Data transmission.
Deletion of description on overrun error in 13.6.3 Data reception.
CHAPTER 13 SERIAL
ARRAY UNIT
Addition of 14.5.18 Timing of I2C interrupt request (INTIIC0) occurrence.
Addition of 14.6 Timing Charts.
CHAPTER 14 SERIAL
INTERFACE IIC0
Change of symbols of higher multiplication result storage register and lower
multiplication result storage register in CHAPTER 15.
Addition of Figure 15-2 Format of 16-bit higher multiplication result storage
register and 16-bit lower multiplication result storage register (MULOH,
MULOL).
Addition of Figure 15-3 Format of Multiplication input data registers A, B (MULA,
MULB).
CHAPTER 15
MULTIPLIER
Addition of Note in 16.2 (1) DMA SFR address register n (DSAn). CHAPTER 16 DMA
CONTROLLER
Addition of Note in Table 17-2 Flags Corresponding to Interrupt Request
Sources.
Change of bit name of bits 0 to 2 of the IF2L register in Figure 17-2.
Chang of bit name of bits 0 of the MK0L register in Figure 17-3.
Modification of 17.4.4 Interrupt request hold.
CHAPTER 17
INTERRUPT
FUNCTIONS
Modification of description in 19.1.2 (1) Oscillation stabilization time counter
status register (OSTC).
Change of reset value of 19.1.2 (2) Oscillation stabilization time select register
(OSTS).
Modification of setting in Figure 19-2. Format of Oscillation Stabilization Time
Select Register (OSTS).
Modification of description on fIL of system clock and fX, fEX of main system clock in
Table 19-1 Operating Statuses in HALT Mode.
Modification of description on fIL of system clock, RAM, and real-time counter (RTC)
in Table 19-2 Operating Statuses in STOP Mode.
Modification of Figure 19-5 Operation Timing When STOP Mode Is Released.
Modification of Figure 19-6 STOP Mode Release by Interrupt Request Generation
and addition of (2) When high-speed system clock (external clock input) is used
as CPU clock.
CHAPTER 19
STANDBY FUNCTION
Addition of RESF register read signal to Figure 20-1 Block Diagram of Reset
Function.
Addition of external bus interface to Table 20-1 Operation Statuses During Reset
Period.
Modification of status after reset of hour count register (HOUR), day count register
(DAY), month count register (MONTH), and alarm minute register (ALARMWH) of
real-time counter in Table 20-2 Hardware Statuses After Reset Acknowledgment.
CHAPTER 20 RESET
FUNCTION
3rd edition
Modification and addition of Note 4 in Figure 21-2 Timing of Generation of Internal
Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector.
CHAPTER 21 POWER-
ON-CLEAR CIRCUIT
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD
948
(9/24)
Edition Description Chapter
Addition of 22.4.1 When used as reset.
Addition of 22.4.2 When used as interrupt.
CHAPTER 22 LOW-
VOLTAGE DETECTOR
Addition of chapter. CHAPTER 23
REGULATOR
Modification of Caution in Figure 24-2 Format of Option Byte (000C1H/010C1H). CHAPTER 24 OPTION
BYTE
Addition of 25.5 Registers that Control Flash Memory. CHAPTER 25 FLASH
MEMORY
Addition of chapter. CHAPTER 26 BCD
CORRECTION
CIRCUIT
Addition of chapter. CHAPTER 27
INSTRUCTION SET
DC Characteristics
• Change of MIN. value and addition of Note 1 of input voltage, high (VIH7)
• Change of MAX. value of input voltage, low (VIL5)
• Change of MAX. value and addition of Note 2 of input voltage, low (VIL7)
• Change of condition of output voltage, high (VOH1)
• Change of condition of output voltage, low (VOL1, VOL3)
• Change of condition of Input leakage current, high (ILIH4)
• Change of condition of Input leakage current, low (ILIL4)
Modification of figure of AC timing measurement position in AC Characteristics (1)
Basic operation
A/D Converter Characteristics
• Modification of condition in upper part of table
• Modification of conditions and MAX. value of differential linearity error (DLE)
D/A Converter Characteristics
• Modification of condition in upper part of table
• Addition of D/A converter operating current (IDAC)
• Change of condition of Settling time (tSET)
CHAPTER 28
ELECTRICAL
SPECIFICATIONS
(TARGET)
3rd edition
Addition of chapter. APPENDIX A
REVISION HISTORY
Change of status indication of
μ
PD78F1162,
μ
PD78F1163,
μ
PD78F1167, and
μ
PD78F1168 to “under development”
1.1 Feature
• Addition of single-power supply flash memory security function
• Addition of flash shield window function to self-programming function
CHAPTER 1 OUTLINE
Changes of Figure 3-1 Memory Map (
μ
PD78F1162) through Figure 3-7 Memory
Map (
μ
PD78F1168)
Addition of 3.1.1(4) On-chip debug security ID setting area
Addition of Caution to 3.1.3 Internal data memory space
Addition of Caution to 3.2.4 Special function registers (SFRs)
Change of BCD adjust result register in Table 3-5 SFR List
4th edition
Addition of Caution to 3.2.5 Extended special function registers (2nd SFRs: 2nd
Special Function Registers)
CHAPTER 3 CPU
ARCHITECTURE
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD 949
(10/24)
Edition Description Chapter
Addition of Note to Figure 5-1 (e) Memory map of
μ
PD78F1166 and (g) Memory
map of
μ
PD78F1168
Change of (c) No wait, 16-bit bus CLKOUT = fCLK/2 (EXWEN = 0, MM3 = 1, MM2 =
1) and (d) With wait, 16-bit bus CLKOUT = fCLK/2 (EXWEN = 1, MM3 = 1, MM2 = 1)
in Figure 5-6. Timing to Read External Memory
Change of (a) No wait, 8-bit bus CLKOUT = fCLK (EXWEN = 0, MM3 = 1, MM2 = 0)
and (b) With wait, 8-bit bus CLKOUT = fCLK (EXWEN = 1, MM3 = 1, MM2 = 0) in
Figure 5-7. Timing to Write to External Memory
Changes of Figure 5-9 Example of Synchronous Memory Connection and
Figure 5-10 Example of Asynchronous Memory Connection
CHAPTER 5
EXTERNAL BUS
INTERFACE
Change of Figure 6-1 Block Diagram of Clock Generator
Addition of Caution to Figure 6-7 Format of Peripheral Enable Register
Addition of Note 4 to 6.3 (7) Operation speed mode control register (OSMC)
Change of description of 6.3 (8) Internal high-speed oscillator trimming register
(HIOTRM)
Addition of time until CPU operation start in Figure 6-13 Clock Generator
Operation When Power Supply Voltage Is Turned On (When LVI Default Start
Function Stopped Is Set (Option Byte: LVIOFF = 1))
Change of Figure 6-14 Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Enabled Is Set (Option Byte:
LVIOFF = 0))
Addition of Caution to 6.6.1 (3) <3>
Change of Table 6-4 (6) CPU clock changing from high-speed system clock (C)
to internal high-speed oscillation clock (B)
Change of CSC register bit name in Table 6-4 (9) CPU clock changing from
subsystem clock (D) to high-speed system clock (C)
CHAPTER 6 CLOCK
GENERATOR
Addition of Caution 2 to 7.3 (1) Peripheral enable register 0 (PER0)
Change of Figure 7-6 Format of Timer Mode Register 0n (TMR0n)
Addition of description to 7.3 (4) Timer status register 0n (TSR0n)
Addition of Table 7-3 OVF Bit Operation and Set/Clear Conditions in Each
Operation Mode
Addition of Table 7-4 Operations from Count Operation Enabled State to TCR0n
Count Start, and (a) through (e)
Addition of description to 7.3 (11) Timer output level register 0 (TOL0)
Change of description of 7. 3 (12) Timer output mode register 0 (TOM0)
Change of Figure 7-20 Format of Timer Output Mode Register 0 (TOM0) and
Remark
Change of description of bit 7 and addition of Note in Figure 7-22 Format of Noise
Filter Enable Register 1 (NFEN1)
Addition of 7.4 Channel Output (TO0n pin) Control
Addition of 7.5 Channel Input (TI0n Pin) Control
4th edition
Addition of MD0n0 bit condition to titles in the following figures
• Figure 7-37 Example of Basic Timing of Operation as Interval Timer/Square
Wave Output
(MD0n0 = 1)
• Figure 7-45 Example of Basic Timing of Operation as Frequency Divider
(MD0n0 = 1)
• Figure 7-49 Example of Block Diagram of Operation as Input Pulse Interval
Measurement
(MD0n0 = 0)
CHAPTER 7 TIMER
ARRAY UNIT
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD
950
(11/24)
Edition Description Chapter
Change of description of 7.7.3 Operation as frequency divider
Change of description of 7.8.3 Operation as multiple PWM output function
CHAPTER 7 TIMER
ARRAY UNIT
Change of clear conditions of real-time counter
Change of description and Caution 1 in Figure 8-2 Format of Peripheral Enable
Register 0 (PER0)
Addition of Caution 2 to Figure 8-2 Format of Peripheral Enable Register 0
(PER0)
Addition of Caution to Figure 8-4 Format of Real-Time Counter Control Register
1 (RTCC1)
Addition of Caution to Figure 8-5 Format of Real-Time Counter Control Register
2 (RTCC2)
Change of Note 2 in 8.3 (5) Sub-count register (RSUBC)
Change of bit name in Figure 8-17 Format of Alarm Week Register (ALARMWW)
CHAPTER 8 REAL-
TIME COUNTER
Addition of Caution 2 to 11.3 (1) Peripheral enable register 0 (PER0)
Change of Table 11-2 A/D Conversion Time Selection
CHAPTER 11 A/D
CONVERTER
Addition of Caution 2 to 12.3 (1) Peripheral enable register 0 (PER0) CHAPTER 12 D/A
CONVERTER
Addition of Caution 3 to 13.3 (1) Peripheral enable register 0 (PER0)
Changes of Figure 13-7 Format of Serial Communication Operation Setting
Register mn (SCRmn)
Addition of description to 13.3 (13) Serial output level register m (SOLm)
Changes of bits 1 and 3 in Figure 13-16 Format of Serial Output Level Register m
(SOLm)
Changes of setting of (a) Serial output register m (SOm), (d) Serial output level
register m (SOLm), and Note in Figure 13-66 Example of Contents of Registers
for UART Transmission of UART (UART0, UART1, UART2, UART3)
Changes of setting of (b) Serial output enable register m (SOEm) in Figure 13-74
Example of Contents of Registers for UART Reception of UART (UART0,
UART1, UART2, UART3)
Change of Figure 13-89 Flowchart of Address Field Transmission
Change of Figure 13-92 Flowchart of Data Transmission
CHAPTER 13 SERIAL
ARRAY UNIT
Addition of Caution 2 to 14.3 (1) Peripheral enable register 0 (PER0)
Change of description of 14.5.4 (2) Selection clock setting method on the slave
side
CHAPTER 14 SERIAL
INTERFACE IIC0
Addition of description to <1> and <3> in 16.4.1 Operation procedure
Addition of description to 16.5.5 Forced termination by software
Additions of description and Note to 16.6 (1) Priority of DMA
CHAPTER 16 DMA
CONTROLLER
Additions of reset processing time and clock supply stop time to the following figures
• Figure 19-4 HALT Mode Release by Reset
• Figure 19-6 STOP Mode Release by Interrupt Request Generation
• Figure 19-7 STOP Mode Release by Reset
Change of Figure 19-5 Operation Timing When STOP Mode Is Released
(When Unmasked Interrupt Request Is Generated)
CHAPTER 19
STANDBY FUNCTION
Change of Figure 20-2 Timing of Reset by RESET Input
Change of Figure 20-3 Timing of Reset Due to Watchdog Timer Overflow
4th edition
Change of Figure 20-4 Timing of Reset in STOP Mode by RESET Input
CHAPTER 20 RESET
FUNCTION
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD 951
(12/24)
Edition Description Chapter
Addition of reset processing time to Figure 21-2 Timing of Generation of Internal
Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector
Addition of 21.4 Caution for Power-on-Clear Circuit
CHAPTER 21 POWER-
ON-CLEAR CIRCUIT
Addition of operation stabilization time
Change of Caution 2 in Figure 22-3 Format of Low-Voltage Detection Level
Select Register (LVIS)
Addition of 22.5 Caution for Low Voltage Detector
CHAPTER 22 LOW-
VOLTAGE DETECTOR
Change of description of 24.1.1 (2) 000C1H/010C1H
Change of Figure 24-2 Format of User Option Byte(000C1H/010C1H)
Change of Figure 24-4 Format of On-chip Debug Option Byte(000C3H/010C3H)
CHAPTER 24 OPTION
BYTE
Addition of description to 25. 4.1 (3) During writing by self programming
Addition of description to 25.5 (1) Background event control register (BECTL)
Addition of 25.6 Programming Method
Addition of 25.7 Security Settings
Addition of 25.8 Flash Memory Programming by Self-programming
CHAPTER 25 FLASH
MEMORY
Addition of chapter CHAPTER 26 ON-CHIP
DEBUGGING
Deletion of description of BCD correction carry register (BCDCY bit), etc. CHAPTER 27 BCD
CORRECTION
CIRCUIT
Absolute Maximum Ratings
• Addition of regulator voltage (REGC)
• Change of Input voltage and output voltage
Addition of MIN. value and MAX. value in XT1 Oscillator Characteristics
DC characteristics
• Change of Condition and Note 1 in Output current, high (IOH1)
• Change of Condition and Note 2 in Output current, low (IOL1)
• Change of Condition of Input voltage, high (VIH2)
• Change of Condition of Input voltage, low (VIL2)
• Change of Condition of Output voltage, low (VOL1)
• Addition of Supply current
• Addition of Watchdog Timer operating current (IWDT)
• Addition of A/D Converter operating current (IADC)
• Addition of D/A Converter operating current(IDAC)
• Addition of DMA Controller operating current (IDMA)
• Addition of LVI operating current (ILVI)
Change of MIN. value of Conversion time (tCONV)of A/D Converter Characteristics
Addition of POC Circuit Characteristics
Addition of Supply Voltage Rise Time
Addition of LVI Circuit Characteristics
Addition of Data Memory STOP Mode Low Supply Voltage Data Retention
Characteristics
CHAPTER 29
ELECTRICAL
SPECIFICATIONS
(TARGET)
4th edition
Revision of chapter APPENDIX A
DEVELOPMENT
TOOLS
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD
952
(13/24)
Edition Description Chapter
Deletion of description of Temperature Correction function of Internal High-Speed
Oscillation Clock and Temperature correction tables H, L from the following chapters.
• CHAPTER 3 CPU ARCHITECTURE
• CHAPTER 6 CLOCK GENERATOR
• CHAPTER 11 A/D CONVERTER
• CHAPTER 14 SERIAL INTERFACE IIC0
• CHAPTER 20 RESET FUNCTION
• CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET)
Throughout
Ver.4.2
Change of the device file from DF781166 to DF781188 APPENDIX A
DEVELOPMENT
TOOLS
Deletion of target from the capacitance value of the capacitor connected to the
REGC pin
Throughout
Change of description in 2.2.19 REGC
Modification of P60 to P64, and P110 in Table 2-2 Connection of Unused Pins
Modification of 12-D to 12-G in Figure 2-1. Pin I/O Circuit List (2/2)
CHAPTER 2 PIN
FUNCTIONS
Addition of the BCDADJ register to Table 3-6 Extended SFR (2nd SFR) List (1/5) CHAPTER 3 CPU
ARCHITECTURE
Change of Figure 4-29. Block Diagram of P110 and P111 CHAPTER 4 PORT
FUNCTIONS
Change of Caution 2 in Figure 6-6 Format of System Clock Control Register
(CKC)
Change of description in 6.3 (8) Internal high-speed oscillator trimming register
(HIOTRM) and addition of Caution
Change of Figure 6-9 Format of Internal High-Speed Oscillator Trimming
Register (HIOTRM) and addition of Caution
Change of Figure 6-13 Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte:
LVIOFF = 1))
CHAPTER 6 CLOCK
GENERATOR
Addition of Note to Figure 7-5 Format of Timer Clock Select Register 0 (TPS0)
Change of Table 7-3 OVF Bit Operation and Set/Clear Conditions in Each
Operation Mode and addition of Remark
Change of description in 7.3 (14) Noise filter enable register 1 (NFEN1)
Change of 7.5.1 TI0n edge detection circuit
CHAPTER 7 TIMER
ARRAY UNIT
Addition of Caution 3 to Table 9-4 Setting Window Open Period of Watchdog
Timer
CHAPTER 9
WATCHDOG TIMER
Fixing of the SOEm3, SOm3, and CKOm3 bit settings to “0”
Change of Figure 13-1 Block Diagram of Serial Array Unit 0
Change of Figure 13-2 Block Diagram of Serial Array Unit 1
Addition of settings and Note to Figure 13-5 Format of Serial Clock Select
Register m (SPSm)
Change of Figure 13-14 Format of Serial Output Enable Register m (SOEm)
Addition of description to 13.3 (12) Serial output register m (SOm)
Change of Figure 13-15 Format of Serial Output Register m (SOm)
Addition of Note to transfer rate
5th edition
Change of transfer rate and Note in 13.4.4 Slave transmission
CHAPTER 13 SERIAL
ARRAY UNIT
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD 953
(14/24)
Edition Description Chapter
Change of transfer rate in 13.4.5 Slave reception
Change of transfer rate in 13.4.6 Slave transmission/reception
Change of Note in 13.4.7 (2)
Addition of setting and Note to Table 13-2 Selection of Operation Clock
Change of transfer rate and addition of Note
Change of setting of (e) Serial mode register mr (SMRmr) in Figure 13-74
Example of Contents of Registers for UART Reception of UART (UART0,
UART1, UART2, UART3)
Addition of setting and Note to Table 13-3 Selection of Operation Clock
Addition of setting and Note to Table 13-4 Selection of Operation Clock
CHAPTER 13 SERIAL
ARRAY UNIT
Additions of description to 16.6 (4) DMA pending instruction CHAPTER 16 DMA
CONTROLLER
Change of Figure 19-4 HALT Mode Release by Reset
Change of Figure 19-7 STOP Mode Release by Reset
CHAPTER 19
STANDBY FUNCTION
Change of reset processing in Figure 20-2 Timing of Reset by RESET Input
Change of reset processing in Figure 20-4 Timing of Reset in STOP Mode by
RESET Input
Change of Caution 2 in Figure 20-5 Format of Reset Control Flag Register
(RESF)
CHAPTER 20 RESET
FUNCTION
Change of Figure 21-2 Timing of Generation of Internal Reset Signal by Power-
on-Clear Circuit and Low-Voltage Detector (1/2)
Change of Figure 21-2 Timing of Generation of Internal Reset Signal by Power-
on-Clear Circuit and Low-Voltage Detector (2/2) and addition of Note
Change of Figure 21-3 Example of Software Processing After Reset Release
CHAPTER 21 POWER-
ON-CLEAR CIRCUIT
Change of Note 4 in Figure 22-2 Format of Low-Voltage Detection Register
(LVIM) and addition of Caution 3
Change of Caution 2 in Figure 22-3 Format of Low-Voltage Detection Level
Select Register (LVIS)
Change of <5> in 22.4.1 (1) (a)
Change of Note 2 in Figure 22-5 Timing of Low-Voltage Detector Internal Reset
Signal Generation (Bit: LVISEL = 0, Option Byte: LVIOFF = 1)
Change of description and Caution in 22.4.1 (1) (b)
Change of Figure 22-6 Timing of Low-Voltage Detector Internal Reset Signal
Generation (Bit: LVISEL = 0, Option Byte: LVIOFF = 0) and Note
Change of <4> in 22.4.1 (2)
Change of Note 2 in Figure 22-7 Timing of Low-Voltage Detector Internal Reset
Signal Generation (Bit: LVISEL = 1)
Change of <5> in 22.4.2 (1)
Additions of Note 3 to Figure 22-8 Timing of Low-Voltage Detector Interrupt
Signal Generation (Bit: LVISEL = 0, Option Byte: LVIOFF = 1)
Change of description and Caution in 22.4.2 (1) (b)
Change of Figure 22-9 Timing of Low-Voltage Detector Interrupt Signal Generation
(Bit: LVISEL = 0, Option Byte: LVIOFF = 0) and addition of Note
Change of <4> in 22.4.2 (2)
Addition of Note 3 to Figure 22-10 Timing of Low-Voltage Detector Interrupt
Signal Generation (Bit: LVISEL = 1)
5th edition
Change of Figure 22-11 Example of Software Processing After Reset Release
CHAPTER 22 LOW-
VOLTAGE DETECTOR
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD
954
(15/24)
Edition Description Chapter
Change of 23.1 Regulator Overview
Addition of Note 3 to Figure 23-1 Format of Regulator Mode Control Register
(RMC)
CHAPTER 23
REGULATOR
Change of description in 24.1.1 (2) 000C1H/010C1H
Change of Figure 24-2 Format of User Option Byte (000C1H/010C1H) and
Caution 2
CHAPTER 24 OPTION
BYTE
Change of description in 25.4.5 REGC pin
Addition of Caution 4 to 25.8 Flash Memory Programming by Self-Programming
CHAPTER 25 FLASH
MEMORY
Addition of 26.3 Securing of user resources CHAPTER 26 ON-CHIP
DEBUGGING
5th edition
Throughout modification CHAPTER 29
ELECTRICAL
SPECIFICATIONS
(TARGET)
Change of status of
μ
PD78F1162, 78F1163, 78F1164, 78F1165, and 78F1166 from
under development to mass production
Throughout
Change of 2.2.22 FLMD0 CHAPTER 2 PIN
FUNCTIONS
Addition of register and Note in Table 3-5 SFR List CHAPTER 3 CPU
ARCHITECTURE
Change of Caution on pin used for the serial array unit or the timer array unit
Addition of PIM register and POM register in block diagram
Addition of descriptions to 4.3 (4) Port input mode registers (PIM0, PIM4, PIM14)
and (5) Port output mode registers (POM0, POM4, POM14)
CHAPTER 4 PORT
FUNCTIONS
Addition of description to 5.1 Functions of External Bus Interface
Change of (b) and (d) in Figure 5-6 Timing to Read External Memory
Addition of description to title of Figure 5-7 Timing to Write to External Memory (c)
CHAPTER 5 EXTERNAL
BUS INTERFACE
Addition of Caution 5 to Figure 6-8 Format of Operation Speed Mode Control
Register (OSMC)
CHAPTER 6 CLOCK
GENERATOR
Change of Table 7-1 Configuration of Timer Array Unit
Addition of description to 7.3 (10) Timer output register 0 (TO0)
CHAPTER 7 TIMER
ARRAY UNIT
Addition of description to 8.3 (15) Alarm hour register (ALARMWH) CHAPTER 8 REAL-TIME
COUNTER
Change of SOm register
Change of Figure 13-1 Block Diagram of Serial Array Unit 0
Change of Figure 13-2 Block Diagram of Serial Array Unit 1
Change of description in 13.3 (12) Serial output register m (SOm)
Change of Figure 13-15 Format of Serial Output Register m (SOm)
Addition of 13.4 Operation Stop Mode
Change of Figure 13-50 Timing Chart of Slave Transmission (in Single-
Transmission Mode)
Change of Figure 13-64 Timing Chart of Slave Transmission/Reception (in Single-
Transmission/Reception Mode)
6th edition
Change of setting in (a) Serial output register m (SOm) and (b) Serial output
enable register m (SOEm) in Figure 13-76 Example of Contents of Registers for
UART Reception of UART (UART0, UART1, UART2, UART3)
CHAPTER 13 SERIAL
ARRAY UNIT
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD 955
(16/24)
Edition Description Chapter
Change of Figure 13-79 Procedure for Resuming UART Reception
Change of Figure 13-89 Initial Setting Procedure for Address Field Transmission
Change of Figure 13-90 Timing Chart of Address Field Transmission
Change of Figure 13-91 Flowchart of Address Field Transmission
Change of Figure 13-94 Flowchart of Data Transmission
Change of Figure 13-96 Timing Chart of Data Reception
Change of Figure 13-97 Flowchart of Data Reception and addition of Caution
Change of Figure 13-99 Flowchart of Stop Condition Generation
Addition of 13.9 Relationship Between Register Settings and Pins
CHAPTER 13 SERIAL
ARRAY UNIT
Change of Figure 16-9 Example of Setting for UART Consecutive Reception +
ACK Transmission
CHAPTER 16 DMA
CONTROLLER
Addition of Note to Figure 19-3 HALT Mode Release by Interrupt Request
Generation
Addition of Note to Figure 19-5 Operation Timing When STOP Mode Is Released
(When Unmasked Interrupt Request Is Generated)
Addition of Note to Figure 19-6 STOP Mode Release by Interrupt Request
Generation
CHAPTER 19 STANDBY
FUNCTION
Change of Figure 20-2 Timing of Reset by RESET Input
Change of Figure 20-4 Timing of Reset in STOP Mode by RESET Input
CHAPTER 20 RESET
FUNCTION
Change of value of Minimum pulse width from "MAX." to "MIN."
Change of Caution 2 in Figure 22-3 Format of Low-Voltage Detection Level Select
Register (LVIS)
Change of Figure 22-7 Timing of Low-Voltage Detector Internal Reset Signal
Generation (Bit: LVISEL = 1)
Change of Figure 22-10 Timing of Low-Voltage Detector Interrupt Signal
Generation (Bit: LVISEL = 1)
Change of Figure 22-11 Example of Software Processing After Reset Release
CHAPTER 22 LOW-
VOLTAGE DETECTOR
Change of 25.4.1 FLMD0 pin
Change of Remark in 25.8 Flash Memory Programming by Self-Programming
Change of Figure 25-11 Flow of Self Programming (Rewriting Flash Memory) and
addition of Remark
CHAPTER 25 FLASH
MEMORY
Change of 27.3 BCD Correction Circuit Operation CHAPTER 27 BCD
CORRECTION CIRCUIT
6th edition
Change of specifications of
μ
PD78F1162, 78F1163, 78F1164, 78F1165, and 78F1166
from target specifications to formal specifications
CHAPTER 29
ELECTRICAL
SPECIFICATIONS
Change of SDAmn to SDA10 and SDA20 CHAPTER 4 PORT
FUNCTIONS
Addition of description to title of Figure 5-5 Timing to Write to External Memory (d) CHAPTER 5 EXTERNAL
BUS INTERFACE
Change of Figure 13-83 Flowchart for LIN Transmission
Change of Figure 13-91 Flowchart of Address Field Transmission
Edition 6.1
(revised
edition)
Change of setting in (a) Serial output register m (SOm) in Figure 13-92 Example of
Contents of Registers for Data Transmission of Simplified I2C (IIC10, IIC20)
CHAPTER 13 SERIAL
ARRAY UNIT
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD
956
(17/24)
Edition Description Chapter
Change of setting in (a) Serial output register m (SOm) in Figure 13-95 Example of
Contents of Registers for Data Reception of Simplified I2C (IIC10, IIC20) and
addition of Note
Change of Note 2 in Table 13-8 Relationship Between Register Settings and Pins
(Channel 3 of Unit 0: UART1 Reception)
Change of Note 2 in Table 13-10 Relationship Between Register Settings and
Pins (Channel 1 of Unit 1: UART2 Reception)
Change of Table 13-11 Relationship Between Register Settings and Pins
(Channel 2 of Unit 1: UART3 Transmission)
Change of Table 13-12 Relationship Between Register Settings and Pins
(Channel 3 of Unit 1: UART3 Reception)
CHAPTER 13 SERIAL
ARRAY UNIT
Change of Table 17-1 Interrupt Source List CHAPTER 17
INTERRUPT FUNCTIONS
Change of Caution 1
Change of REGC pin input voltage (VIREGC) of Absolute Maximum Ratings
DC Characteristics
• Change of “Conditions” column of output voltage, high (VOH2)
• Change of “Conditions” column of output voltage, low (VOL2)
• Change of “Conditions” column of input leakage current, high (ILIH2)
• Change of “Conditions” column of input leakage current, high (ILIH3)
• Change of “Conditions” column of input leakage current, low (ILIL2)
• Change of “Conditions” column of input leakage current, low (ILIL3)
• Change of MAX. values of supply current (IDD3)
Change of Note 4
Addition of “(Target)”
Change of AC timing test points in AC Characteristics (1) Basic operation
Edition 6.1
(revised
edition)
AC Characteristics (2) External bus interface
• Change of MIN. and MAX. values of RD low-level width (tWRDL1)
• Change of MIN. and MAX. values of WR0, WR1 low-level width (tWWRL1)
• Addition of Remark 3
• Change of figure of Read/write cycle (CLKOUT synchronous): In separate bus mode
• Change of figure of Read/write cycle (CLKOUT synchronous): In multiplexed bus
mode
CHAPTER 29
ELECTRICAL
SPECIFICATIONS
Change of (b) and (d) in Figure 5-6 Timing to Read External Memory CHAPTER 5 EXTERNAL
BUS INTERFACE
Edition 6.2
(revised
edition) Change of Remark 3 in AC Characteristics (2) External bus interface CHAPTER 29
ELECTRICAL
SPECIFICATIONS
Modification of SOE01 bit value during UART0 reception in Table 13-6 Relationship
Between Register Settings and Pins (Channel 1 of Unit 0: CSI01, UART0
Reception)
Deletion of SOE03, SO03, and CKO03 bits in Table 13-8 Relationship Between
Register Settings and Pins (Channel 3 of Unit 0: UART1 Reception)
Deletion of SOE11, SO11, and CKO11 bits in Table 13-10 Relationship Between
Register Settings and Pins (Channel 1 of Unit 1: UART2 Reception)
Deletion of CKO12 bit in Table 13-11 Relationship Between Register Settings and
Pins (Channel 2 of Unit 1: UART3 Transmission)
Edition 6.3
(revised
edition)
Deletion of SOE13, SO13, and CKO13 bits in Table 13-12 Relationship Between
Register Settings and Pins (Channel 3 of Unit 1: UART3 Reception)
CHAPTER 13 SERIAL
ARRAY UNIT
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD 957
(18/24)
Edition Description Chapter
Addition of expanded-specification products,
μ
PD78F1162A, 78F1163A, 78F1164A,
78F1165A, 78F1166A, 78F1167A, 78F1168A
Addition of (A) grade products of expanded-specification products,
μ
PD78F1162A(A),
78F1163A(A), 78F1164A(A), 78F1165A(A), 78F1166A(A), 78F1167A(A), 78F1168A(A)
−
Change of related documents INTRODUCTION
Addition of 1.1 Differences Between Conventional-Specification Products
(
μ
PD78F116x) and Expanded-Specification Products (
μ
PD78F116xA)
Addition of Caution 4 to 1.5 Pin Configuration (Top View)
Modification of 1.7 Block Diagram
CHAPTER 1 OUTLINE
Change of pins corresponding to EVDD0, EVDD1, and VDD in Table 2-1 Pin I/O Buffer
Power Supplies
Change of description in 2.2.15 AVREF0
Change of description in 2.2.16 AVREF1
Change of description in 2.2.18 RESET
Change of type 37-A to 37-B and type 39 to 2-W and descriptions of AVREF0, AVREF1,
and RESET pin in Table 2-4 Connection of Unused Pins
Change of type 37-A to 37-B and type 39 to 2-W in Figure 2-1 Pin I/O Circuit List
CHAPTER 2 PIN
FUNCTIONS
Addition of Note to Figures 3-1 to 3-7
Change of figure in Remark of 3.1 Memory Space
Change of description in 3.1.1 (1) Vector table area
Change of description in 3.1.2 Mirror area
Change of description and addition and change of Caution in 3.1.3 Internal data
memory space
Addition of Cautions to 3.2.1 (3) Stack pointer (SP)
Change of addresses in Figure 3-20 Configuration of General-Purpose Registers
Modification of and addition of Note 6 to Table 3-5 SFR List
CHAPTER 3 CPU
ARCHITECTURE
Change of pins corresponding to EVDD0, EVDD1, and VDD in Table 4-1 Pin I/O Buffer
Power Supplies
Change of Caution 2 in 4.2.1 Port 0
Change of Cautions 1 and 3 in 4.2.2 Port 1
Addition of Caution 2 to 4.2.4 Port 3
Change of Caution 2 in 4.2.5 Port 4
Change of Figure 4-24 Block Diagram of P52 to P57
Addition of Caution to 4.2.7 Port 6
Addition of description of PU6
Modification of Figure 4-29 Block Diagram of P80 to P87
Change of Caution 1 in and addition of Caution 3 to 4.2.13 Port 14
Addition of Caution 3 to Figure 4-45 Format of A/D Port Configuration Register
(ADPC)
Change of Notes of Table 4-6 Settings of Port Mode Register and Output Latch
When Using Alternate Function
CHAPTER 4 PORT
FUNCTIONS
Change of 5.5 Number of Instruction Execution Clocks and Instruction Wait
Clocks for Fetch Access
8th edition
Change of description in 5.6 (4) WAIT pin (alternate function: P06)
CHAPTER 5 EXTERNAL
BUS INTERFACE
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD
958
(19/24)
Edition Description Chapter
Addition of Note 3 to Figure 6-6 Format of System Clock Control Register (CKC)
Change of Cautions 3 and 5 in Figure 6-8 Format of Operation Speed Mode
Control Register (OSMC)
Change of Figure 6-13 Clock Generator Operation When Power Supply Voltage Is
Turned On (When LVI Default Start Function Stopped Is Set (Option Byte:
LVIOFF = 1))
Change of Figure 6-14 Clock Generator Operation When Power Supply Voltage Is
Turned On (When LVI Default Start Function Enabled Is Set (Option Byte:
LVIOFF = 0)) and description of <1>
Change of 6.6.3 (1) <1> Setting P123/XT1 and P124/XT2 pins (CMC register)
Change of and deletion of Note in Figure 6-15 CPU Clock Status Transition
Diagram
Change of Table 6-6 Maximum Time Required for Main System Clock Switchover
CHAPTER 6 CLOCK
GENERATOR
Change of channel number in 7.1.1 (4) Divider function
Change of description of CCS0n and MASTER0n bits in Figure 7-6 Format of Timer
Mode Register 0n (TMR0n)
Change of description of TOM0n bit in 7.3 (12) Timer output mode register 0
(TOM0)
Change of Figure 7-20 Format of Timer Output Mode Register 0 (TOM0)
Change of description in 7.4.3 (1) Changing values set in registers TO0, TOE0,
TOL0, and TOM0 during timer operation
Addition of description to 7.7.1 (1) Interval timer
Change of Figure 7-35 Block Diagram of Operation as Interval Timer/Square
Wave Output
Addition of (2) When fSUB/4 is selected as count clock to Figure 7-37 Example of
Set Contents of Registers During Operation as Interval Timer/Square Wave
Output
Change of Figure 7-38 Operation Procedure of Interval Timer/Square Wave
Output Function
Change of description during operation in Figure 7-42 Operation Procedure When
External Event Counter Function Is Used
Change of channel number in 7.7.3 Operation as frequency divider
Change of description during operation in Figure 7-46 Operation Procedure When
Frequency Divider Function Is Used
Change of description during operation in Figure 7-50 Operation Procedure When
Input Pulse Interval Measurement Function Is Used
Change of description during operation in Figure 7-54 Operation Procedure When
Input Signal High-/Low-Level Width Measurement Function Is Used
Change of description during operation in Figure 7-59 Operation Procedure When
PWM Function Is Used
Change of description during operation in Figure 7-64 Operation Procedure of One-
Shot Pulse Output Function
Change of description during operation in Figure 7-69 Operation Procedure When
Multiple PWM Output Function Is Used
CHAPTER 7 TIMER
ARRAY UNIT
Change of Note and Caution 1 in Figure 8-2 Format of Peripheral Enable Register
0 (PER0)
8th edition
Change of Figure 8-3 Format of Real-Time Counter Control Register 0 (RTCC0)
CHAPTER 8 REAL-TIME
COUNTER
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD 959
(20/24)
Edition Description Chapter
Change of description and Caution in Figure 8-4 Format of Real-Time Counter
Control Register 1 (RTCC1)
Addition of Caution 3 to Figure 8-5 Format of Real-Time Counter Control Register
2 (RTCC2)
Change of description in 8.3 (7) Minute count register (MIN), (8) Hour count
register (HOUR), (9) Day count register (DAY), (11) Month count register
(MONTH), and (12) Year count register (YEAR)
Change of Table 8-2 Displayed Time Digits
Addition of Caution to Figure 8-11 Format of Week Count Register (WEEK)
Change of description in 8.3 (13) Watch error correction register (SUBCUD)
Deletion of Caution in (16) Alarm week register (ALARMWW)
Addition of Notes to Figure 8-18 Procedure for Starting Operation of Real-Time
Counter
Addition of 8.4.2 Shifting to STOP mode after starting operation
Addition of 8.4.5 1 Hz output of real-time counter
Addition of 8.4.6 32.768 kHz output of real-time counter
Addition of 8.4.7 512 Hz, 16.384 kHz output of real-time counter
Addition of 8.4.8 Example of watch error correction of real-time counter
CHAPTER 8 REAL-TIME
COUNTER
Change of Cautions 1 and 2 in Figure 9-2 Format of Watchdog Timer Enable
Register (WDTE)
Change of Caution 3 in Table 9-4 Setting Window Open Period of Watchdog
Timer
CHAPTER 9
WATCHDOG TIMER
Change of description in 11.2 (9) AVREF0 pin
Change of Table 11-3 A/D Conversion Time Selection
Addition of Caution 3 to Figure 11-10 Format of A/D Port Configuration Register
(ADPC)
Addition of 11.5 Temperature Sensor Function (Expanded-Specification Products
(
μ
PD78F116xA) Only)
Addition of 11.7 (2) Reducing current when A/D converter is stopped
CHAPTER 11 A/D
CONVERTER
Addition of 12.2 (1) AVREF1 pin
Addition of 12.3 (4) Port mode register 11 (PM11)
Change of description in 12.4.1 Operation in normal mode
Change of description in 12.4.2 Operation in real-time output mode
CHAPTER 12 D/A
CONVERTER
Addition of Note to 13.1.3 Simplified I2C (IIC10, IIC20)
Change of Figure 13-1 Block Diagram of Serial Array Unit 0
Change of Figure 13-2 Block Diagram of Serial Array Unit 1
Change of Note 2 in Figure 13-5 Format of Serial Clock Select Register m (SPSm)
Change of and addition of Note to Figure 13-7 Format of Serial Communication
Operation Setting Register mn (SCRmn)
Change of Figure 13-26 Procedure for Stopping Master Transmission
Change of Figure 13-27 Procedure for Resuming Master Transmission
Change of Figure 13-28 Timing Chart of Master Transmission (in Single-
Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0)
8th edition
Change of Figure 13-30 Timing Chart of Master Transmission (in Continuous
Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0)
CHAPTER 13 SERIAL
ARRAY UNIT
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD
960
(21/24)
Edition Description Chapter
Modification of Figure 13-36 Timing Chart of Master Reception (in Single-
Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Change of Figure 13-40 Procedure for Stopping Master Transmission/Reception
Change of Figure 13-41 Procedure for Resuming Master Transmission/Reception
Modification of Figure 13-42 Timing Chart of Master Transmission/Reception (in
Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Modification of Figure 13-44 Timing Chart of Master Transmission/Reception (in
Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Modification of Figure 13-45 Flowchart of Master Transmission/Reception (in
Continuous Transmission/Reception Mode)
Change of transfer rate in 13.5.4 Slave transmission
Change of Figure 13-48 Procedure for Stopping Slave Transmission
Change of Figure 13-49 Procedure for Resuming Slave Transmission
Change of Figure 13-50 Timing Chart of Slave Transmission (in Single-
Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Change of Figure 13-52 Timing Chart of Slave Transmission (in Continuous
Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Change of Figure 13-53 Flowchart of Slave Transmission (in Continuous
Transmission Mode)
Change of transfer rate in 13.5.5 Slave reception
Change of Figure 13-57 Procedure for Resuming Slave Reception
Modification of Figure 13-58 Timing Chart of Slave Reception (in Single-
Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Change of transfer rate in 13.5.6 Slave transmission/reception
Change of Figure 13-62 Procedure for Stopping Slave Transmission/Reception
Change of Figure 13-63 Procedure for Resuming Slave Transmission/Reception
Modification of Figure 13-64 Timing Chart of Slave Transmission/Reception (in
Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Modification of Figure 13-66 Timing Chart of Slave Transmission/Reception (in
Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Modification of Figure 13-67 Flowchart of Slave Transmission/Reception (in
Continuous Transmission/Reception Mode)
Change of Note 2 in Table 13-2 Selection of Operation Clock
Addition of Caution to 13.6 Operation of UART (UART0, UART1, UART2, UART3)
Communication
Change of Figure 13-70 Procedure for Stopping UART Transmission
Change of Figure 13-72 Timing Chart of UART Transmission (in Single-
Transmission Mode)
Change of Figure 13-74 Timing Chart of UART Transmission (in Continuous
Transmission Mode)
Change of 13.6.2 UART reception
Change of (b) Serial output enable register m (SOEm) in Figure 13-76 Example of
Contents of Registers for UART Reception of UART (UART0, UART1, UART2,
UART3)
Modification of Figure 13-80 Timing Chart of UART Reception
Modification of transfer data length in 13.6.3 LIN transmission
8th edition
Change of Note 2 in Figure 13-82 Transmission Operation of LIN
CHAPTER 13 SERIAL
ARRAY UNIT
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD 961
(22/24)
Edition Description Chapter
Modification of transfer data length in 13.6.4 LIN reception
Change of Note 2 in Table 13-3 Selection of Operation Clock
Addition of Note to 13.7 Operation of Simplified I2C (IIC10, IIC20) Communication
Addition of Note to 13.7.1 Address field transmission
Change of Figure 13-89 Initial Setting Procedure for Address Field Transmission
Change of Figure 13-90 Timing Chart of Address Field Transmission
Addition of Note to 13.7.2 Data transmission
Change of Figure 13-93 Timing Chart of Data Transmission
Addition of Note to 13.7.3 Data reception
Change of Figure 13-96 Timing Chart of Data Reception
Change of Figure 13-97 Flowchart of Data Reception and change of Caution
Change of Figure 13-98 Timing Chart of Stop Condition Generation
Change of Note 2 in Table 13-4 Selection of Operation Clock
CHAPTER 13 SERIAL
ARRAY UNIT
Change of Note in Figure 14-6 Format of IIC Control Register 0 (IICC0)
Change of Table 14-2 Selection Clock Setting
Change of Table 14-3 Selection Clock Setting
Change of Table 14-5 Extension Code Bit Definitions
Change of Figure 14-24 Master Operation in Single-Master System
Change of Figure 14-25 Master Operation in Multi-Master System
Change of Figure 14-26 Slave Operation Flowchart
Change of Figures 14-28 and 14-29
CHAPTER 14 SERIAL
INTERFACE IIC0
Change of Figure 16-5 Format of DMA Operation Control Register n (DRCn)
Addition of Note to Table 16-2 Response Time of DMA Transfer
CHAPTER 16 DMA
CONTROLLER
Change of description in 17.2 Interrupt Sources and Configuration
Change of Table 17-1 Interrupt Source List
CHAPTER 17
INTERRUPT FUNCTIONS
Change of Caution 2 in 18.3 (1) Key return mode register (KRM) CHAPTER 18 KEY
INTERRUPT FUNCTION
Change of external bus interface in Table 19-1 Operating Statuses in HALT Mode
Change of Note in Figure 19-3 HALT Mode Release by Interrupt Request
Generation
Change of external bus interface in Table 19-2 Operating Statuses in STOP Mode
Change of Figure 19-5 Operation Timing When STOP Mode Is Released (Release
by Unmasked Interrupt Request)
Addition of Note to Figure 19-6 STOP Mode Release by Interrupt Request
Generation
CHAPTER 19 STANDBY
FUNCTION
Change of (4) of reset signal generation methods CHAPTER 20 RESET
FUNCTION
Deletion of Note in 21.1 Functions of Power-on-Clear Circuit
Deletion of Note in 21.3 Operation of Power-on-Clear Circuit
Deletion of Note 6 in (1) When LVI is OFF upon power application (option byte:
LVIOFF = 1) in Figure 21-2 Timing of Generation of Internal Reset Signal by
Power-on-Clear Circuit and Low-Voltage Detector
8th edition
Deletion of Note 3 in (2) When LVI is ON upon power application (option byte:
LVIOFF = 0) in Figure 21-2 Timing of Generation of Internal Reset Signal by
Power-on-Clear Circuit and Low-Voltage Detector
CHAPTER 21 POWER-
ON-CLEAR CIRCUIT
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD
962
(23/24)
Edition Description Chapter
Deletion of Note in 22.1 Functions of Low-Voltage Detector
Deletion of Note 2 in Figure 22-3 Format of Low-Voltage Detection Level Select
Register (LVIS)
Deletion of Note in 22.4 Operation of Low-Voltage Detector
CHAPTER 22 LOW-
VOLTAGE DETECTOR
Addition of description to 24.4 Setting of Option Byte CHAPTER 24 OPTION
BYTE
Addition of PG-FP5, FL-PR5, and QB-MINI2 as dedicated flash memory programmers
Change of Figure 25-7 Format of Background Event Control Register (BECTL)
Change of Table 25-4 Communication Modes
Addition of 25.8 Processing Time of Each Command When Using PG-FP4 or PG-
FP5 (Reference Values)
Addition of Caution 5 to 25.9 Flash Memory Programming by Self-Programming
Change of description in 25.9.2 Flash shield window function
CHAPTER 25 FLASH
MEMORY
Change of Caution in 26.1 Connecting QB-MINI2 to 78K0R/KG3
Addition of Caution to Figure 26-1 Connection Example of QB-MINI2 and
78K0R/KG3
Change of Table 26-1 Differences Between 1-Line Mode and 2-Line Mode
CHAPTER 26 ON-CHIP
DEBUG FUNCTION
Change of Table 28-1 Operand Identifiers and Specification Methods and change
of Remark
Change of description in 28.1.4 PREFIX instruction
Change of CALLT instruction operation column
Change of Table 28-5 Operation List (17/17)
CHAPTER 28
INSTRUCTION SET
Addition of recommended oscillator constants
Change of “Conditions” column and MAX. values of output current, low (IOL1) in DC
Characteristics
Change of “Conditions” column of output voltage, low (VOL1) in DC Characteristics
Change of typical supply current value of all products, deletion of “(Target)” from
supply currents of
μ
PD78F1167 and 78F1168, and change of values during fSUB in DC
Characteristics
Modification of “Conditions” column of instruction cycle and change of external main
system clock frequency and external main system clock input high-level width, low-
level width in (1) Basic operation in AC Characteristics
Addition of tDAR1 and expanded-specification product specifications to (a) Read/write
cycle (CLKOUT synchronous) in (2) External bus interface
Addition of tDAR1 to timing diagram in Read/write cycle (CLKOUT synchronous): In
multiplexed bus mode in (2) External bus interface
Addition of (b) Read/write cycle (CLKOUT asynchronous) to (2) External bus
interface
Addition of expanded-specification product specifications to (d) During
communication at same potential (simplified I2C mode) in (3) Serial interface:
Serial array unit
Change of overall error and integral linearity error values in A/D Converter
Characteristics
Addition of A/D converter characteristics of expanded-specification products
Addition of temperature sensor
Addition of Remark to D/A Converter Characteristics
8th edition
Change of Supply Voltage Rise Time Timing diagrams
CHAPTER 29
ELECTRICAL
SPECIFICATIONS
(STANDARD PRODUCTS)
APPENDIX C REVISION HISTORY
User’s Manual U17894EJ9V0UD 963
(24/24)
Edition Description Chapter
Change of VDD supply current value and number of rewrites and addition of expanded-
specification product characteristics in Flash Memory Programming Characteristics
CHAPTER 29
ELECTRICAL
SPECIFICATIONS
(STANDARD PRODUCTS)
Addition of chapter CHAPTER 30
ELECTRICAL
SPECIFICATIONS ((A)
GRADE PRODUCTS)
(TARGET)
Addition of chapter CHAPTER 32
RECOMMENDED
SOLDERING
CONDITIONS
Change of A.4.1 When using flash memory programmers PG-FP5, FL-PR5, PG-
FP4 and FL-PR4
Change of A.4.2 When using on-chip debug emulator with programming function
QB-MINI2
Change of A.5.2 When using on-chip debug emulator with programming function
QB-MINI2
APPENDIX A
DEVELOPMENT TOOLS
8th edition
Addition of chapter APPENDIX B LIST OF
CAUTIONS
NEC Electronics Corporation
1753, Shimonumabe, Nakahara-ku,
Kawasaki, Kanagawa 211-8668,
Japan
Tel: 044-435-5111
http://www.necel.com/
[America]
NEC Electronics America, Inc.
2880 Scott Blvd.
Santa Clara, CA 95050-2554, U.S.A.
Tel: 408-588-6000
800-366-9782
http://www.am.necel.com/
[Asia & Oceania]
NEC Electronics (China) Co., Ltd
7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian
District, Beijing 100083, P.R.China
Tel: 010-8235-1155
http://www.cn.necel.com/
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Room 2509-2510, Bank of China Tower,
200 Yincheng Road Central,
Pudong New Area, Shanghai, P.R.China P.C:200120
Tel:021-5888-5400
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Shenzhen Branch
Unit 01, 39/F, Excellence Times Square Building,
No. 4068 Yi Tian Road, Futian District, Shenzhen,
P.R.China P.C:518048
Tel:0755-8282-9800
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NEC Electronics Hong Kong Ltd.
Unit 1601-1613, 16/F., Tower 2, Grand Century Place,
193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: 2886-9318
http://www.hk.necel.com/
NEC Electronics Taiwan Ltd.
7F, No. 363 Fu Shing North Road
Taipei, Taiwan, R. O. C.
Tel: 02-8175-9600
http://www.tw.necel.com/
NEC Electronics Singapore Pte. Ltd.
238A Thomson Road,
#12-08 Novena Square,
Singapore 307684
Tel: 6253-8311
http://www.sg.necel.com/
NEC Electronics Korea Ltd.
11F., Samik Lavied’or Bldg., 720-2,
Yeoksam-Dong, Kangnam-Ku,
Seoul, 135-080, Korea
Tel: 02-558-3737
http://www.kr.necel.com/
For further information,
please contact:
G0706
[Europe]
NEC Electronics (Europe) GmbH
Arcadiastrasse 10
40472 Düsseldorf, Germany
Tel: 0211-65030
http://www.eu.necel.com/
Hanover Office
Podbielskistrasse 166 B
30177 Hannover
Tel: 0 511 33 40 2-0
Munich Office
Werner-Eckert-Strasse 9
81829 München
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Stuttgart Office
Industriestrasse 3
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Tel: 0 711 99 01 0-0
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France
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Sucursal en España
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