intel | PRELIMINARY In 27C400 4M (256K x 16 or 512K x 8) CHMOS EPROM @ Word-Wide or Byte-Wide Configurable @ High Performance m 4M 40-Pin Mask ROM Compatible ~y ns preninyd Access Time ~~ 40-Lead CERDIP Package Ycc = m Low Power Dissipation .@ FAST Programming 50 mA Max Active @ 5 MHz Quick-Pulse Programming 100 A Max Standby Algorithm Programming as Fast as 28 Seconds The Intel 27C-400 is a 5V only 4,194,304 bit Erasable Programmable Read Only Memory, organized as 262,144 words of 16 bits each. A byte enable switch on pin 31 allows the device to be addressed as a 8 by 524,288 bit device. The 27C400 in pin-out and functionally compatible with 40-pin 4M Mask ROMs. The 27C400 employs advanced CHMOS* III-E circuitry for systems requiring low power, high speed perform- ance and noise immunity. . a The 27C400 is equally at home in both TTL or CMOS environments. Programming time is as fast as 28 seconds using Intels Quick Pulse Programming Algorithm. *CHMOS is a patented process of intel Corporation. DATA OUTPUTS Voc Om 99-%s Vpp o> cnn O> Ant OUTPUT ENABLE OE CHIP ENABLE faa AND . OUTPUT BYTE PROGRAM. LOGIC BUFFERS Y DECODER ~. : Y GATING Ag~Ay7 ADDRESS INPUTS 4,194,304 BIT X DECODER CELL MATRIX 290273-1 Figure 1. 27C400 Block Diagram October 1991 5-111 Order Number: 290273-002ntel . 270400 PRELIMINARY Pin Names Ag-Ai7:. ADDRESSES Oo-O15 | OUTPUTS OE OUTPUT ENABLE CE. CHIP ENABLE BYTE WORD/BYTE ENABLE A-1 BYTE SELECT NC NO INTERNAL CONNECT 4Mb 4Mb Mask ROM 270400 Mask ROM Ai7 47 Cit aba Ag Az Ay O42 soBa, Ag As acs 38F Ae A1o As a, 44 vA, Au Ag aos 36EI Ap Ai2 Ag ate 3s As Aig A2 A, 7 oP, Ais Ay a Cs 3p, Ais Ag oe RS saBiag A TEL10 CERDIP-,-31 FT BYTE/Vpp Byte GND own 11 a 200 30 ono GND DE oe 12 2911 oy, /A-1 O45/A-1 Oo % 913 28P0, O7 Og 0, 414 27Bo, Om O; o, 15 26Fg Os Og o 16 25305 O13 Oo 0, C7 24P1 0, Os O10 Og CAs 2310. O12 Og o, Cte 22 PI, Os 01 0, 2420 2119 Vo Voc 290273-2 NOTE: Model Number Prefixes: D = CERDIP. Figure 2. 27C400 Pin Configuration 5-112intel. 27C400 PRELIMINARY ABSOLUTE MAXIMUM RATINGS* Operating Temperature ............. 0C to 70C(1) Temperature under Bias ........... 10C to 80C Storage Temperature............. 65C to 125C Voltage on Any Pin (Except Ag, Voc and BYTE/Vpp) with Respect to GND .......... 0.6V to 6.5V(2) Voltage on Ag, with Respect to GND..... penne eee 0.6V to 13V(2) BYTE/Vpp Supply Voltage with Respect toGND........... 0.6V to 14V(2) Voc Supply Voltage with Respect toGND............ 0.6V to 7V(2) NOTICE: This data sheet contains preliminary intor- mation on new products in production. The specifica- tions are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Siressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and x- tended exposure beyond the Operating Conditions may affect device reliability. READ OPERATION DC CHARACTERISTICS( Vcc = 5.0v + 10% Symbol Parameter Notes | Min | Typ Max Unit Test Condition lu Input Load Current 7 0.01} 1.0 BA | Vin = OV to Voc ILo Output Leakage Current +10 BA | Vout = OV to Voc Isp Voc Standby Current 5 1.0 mA | CE = Viy oe 100 BA | CE = Voc + 0.2V loc Voc Operating Current 3 50 mA | f = 5 MHz, TE = Vit. lour = OMA Ipp Vpp Operating Current 3 10 BA | Vpp = Voc los Output Short Circuit 4,6 100 mA Current ow. VIL Input Low Voltage 0.5 0.8 Vv Vin Input High Voltage 2.0 Voo + O51 V | Vot Output Low Voltage 0.45 Ve | lop = 2.1mA Vou Output High Voltage 2.4 V_| lon = 400 pA NOTES: . 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is 0.5V on input/output pins. During transitions, this level may undershoot to 2.0V for periods <20 ns. Maximum DC voltage on input/output pins is Voc + 0.5V which, during transitions, may overshoot to Voc + 2.0V for periods <20 ns. 3. Maximum active power usage is the sum Ipp + icc. Maximum current value is with outputs Oo-015 unloaded. 4.01 5. BYTE/Vpp = Voc + 0.2V or GND + 0.2V. 6. Sampled, not 100% tested. 7. Typical limits are at Voc = 5V, Ta = 25C. shorted for no more than one second. No more than one output shorted at a time. 5-113intel. a7ca00 PRELIMINARY READ OPERATION AC CHARACTERISTICS() Vcc = 5.0V + 10% Version Voc + 10% 270400 150V 1015) 27C400~-200V10 Unit Symbol Parameter | Notes Min Max Min. Max tacc Address to Output Delay 150 200 ns tcE CE to Output Delay 2 150 | 200 ns tor OE to Output Delay 2 60 70 ns tor OE High to Output High Z 3 50 - 60 ns ton Output Hold from Addresses, | 3 0 0 re CE or OE Change Whichever Occurs First NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE may be delayed up to tce-tog after the falling edge of CE without ut impact on tce- 3. Sampled, not 100% tested. voltages. 4. Includes 045/A-1. 5. Both byte- and word-wide-read mode are available with the 27C400- 200V10, 27C400-150V10 specs are valid only in word-wide-read mode operation. CAPACITANCE) Ta = 25C, f = 1 MHz Symbol! Parameter Typical Max Unit Condition Cin Input Capacitance 4 8 pF Vin = OV Cout Output Capacitance(4) 8 12 pF Vout = OV Cypp Vpp Capacitance 18 25 pF Vpp = OV AC INPUT/OUTPUT REFERENCE WAVEFORM AC TESTING LOAD CIRCUIT 24 2.0 5 x 2.0 _ ie os INPUT Kee POINTS << oat : 1NO14 290273-5 , AC test inputs are driven at Voy (2.4 Vr7L) for a Logic 1 and DEVICE R Vor (0.45 Vir) for a Logic 0. Input timing begins at Vj} (2.0 , UNDER | our Vir) and Vic (0.8 VTL). Output timing ends at Vj and Vic. input TEST . rise and fall times (10% to 80%) < 10 ns. T wo ~ 290273-6 CL = 100 pF C, Includes Jig Capacitance RL = 3.3 ka 5-114intel. 270400 PRELIMINARY AC WAVEFORMS Word-Wide Read Mode _ Ag-17 . VALID ADDRESS CE OE O~15 * 290273-7 NOTE: BYTE/Vpp = Voc + 0.2V Byte-Wide Read Mode Viv Ari M7 V VALID ADDRESS L _ Y ce OM . Vi a lame (Y oo Yi Vou 7 Vo 290273-8 NOTE: BYTE/Vpp = GND + 0.2V 5-115intel. 270400 PRELIMINARY DEVICE OPERATION A The Mode Selection table lists 27C400 operating modes. Read Mode requires a single 5V power supply. All inputs, except Vcc and BYTE/Vpp, and Ag during intgligent Identifier Mode, are TTL-or GMOS. . Table 1. Mode Selection Mode Notes | GE | OE | Ag | Ao | O15/A-1 e , Es Vec | Os-14 Oo-7 Read (Word) 1 1 Va Vi} xX X | Dis Out [ Veo | Voc | Dg-14 Out | Do_7 Out Read (Upper Byte) Vii} Ve | xX | X Vin GND | Voc | HighZ | Dg_75 Out Read (Lower Byte) Vie) Vir) X | X Vit GND | Voc High Z Do-7 Out Output Disable Vi | Vin | X Xx High Zz X Voc High Z High Z Standby Vin | Xx x X |. HighZ x Voc High Z High Z Program 2 Vir | Vin} X xX Dys5 In Vpp Vop | Dg-14in Do-7 In Program Verify Vin | Vir | X X | Dys5 Out Vpp | Vop | Dg-14 Out | Do-7 Out | Program Inhibit Vin | Vig | X x High Z Vpp Vop High Z High Z intgligent Identifier | 2,3 | Vii | Vir | Vio | Vi OB Voc | Voc OOH 89H Manufacturer Vir) Vie} Vio | Vie 0B Voc | Voc 44H EFH Device NOTES: 1. X can be Vi, or Vin. For BTTL/Vpp, X = GND or Voc. aoe DC Programming Characteristics for Vcp, Vpp and Vip voltages. - Ay-Ag, Aio-A17 = ViL- /Vpp is intended for operation under DC Voltage conditions only. Read Mode Two Line Output Control The 270400 has two control functions; both must be enabled to obtain data at the outputs. CE is the pow- er control and device select. OE controls the output buffers to gate data to the outputs. With addresses stable, the address access tirne (tacc) equals the delay from CE to output (tc). Outputs display valid data tog after OEs falling edge, assuming tacc and tce times are met. Word-Wide Mode With BYTE/Vpp at Vcc + 0.2V outputs Oo-7 pres- ent data Dp_7 and outputs Og_15 present data Dg_ 15, after ce and OE are appropriately enabled. Byte-Wide Mode With BYTE/Vpp at GND + 0.2V, outputs Og_14 are tri-stated. If O15/A-1 = ViH, outputs Op_7 present data bits Dg_45. If O15/A-1 = Vi, outputs Oo_7 present data bits Do_7. Read Operation AC Characteristic specifications are currently valid in byte-wide mode only when using the 27C400-200V10. Please contact your local intel sales office for additional information. EPROMs are often used in larger memory arrays. intel provides two control inputs to accommodate multiple memory connections. Two-line control pro- vides. for: a. lowest possible memory power dissipation b. complete assurance that data bus contention will not occur To efficiently use these two control inputs, an ad- dress decoder should enable CE while OE should be connected to ali memory devices and the systems READ control line. This assures that only selected memory devices have active outputs while deselect- ed memory devices are in Standby Mode. Standby Mode Standby Mode substantially reduces Voc current. When = Vip, Outputs are in a high impedance state, independent of OE. 5-116intel. 27C400 PRELIMINARY Program Mode Caution: Exceeding 14V on BYTE/Vpp will permanently damage the device. Initially, and after each erasure, all EPROM bits are, in the 1 state. Data is introduced by selectively programming Os into the desired bit locations. Al- though only Os are programmed the data word can contain both 1s and 0s. Ultraviolet light era- sure is the only way to change Os to 1s. Program Mode is entered when BYTE/Vpp is raised to 12.75V. Data is introduced by applying a 16-bit word to the output pins. Pulsing GE low while OE = Vin programs that data into the device. Program Verity A verify should be performed following a program operation to determine that bits have been correctly programmed. With Voc at.6.25V, a substantial pro- oem margin is ensured. The verify is performed with at Vin. Valid data is available on Op_15 toe after OE falls low. Program Inhibit Program Inhibit mode allows parallel programming of multiple EPROMs with different data. CE-high in- hibits programming of non-targeted devices. Except for CE and OE, parallel EPROMs may have common inputs. inteligent Identifier Mode The intgligent identifier Mode will determine an EPROMs manufacturer and device type, allowing programming equipment to automatically match a device with its proper programming algorithm. This mode is activated when a programmer forces 12V +0.5V on Ag. With CE, OE, Ay-Ag, and Ayo- A17 = Vit, Ao = Vit will present the manufacturer's code and Ag = Vi the device code. This mode functions in the 25C +5C ambient temperature range required during programming. SYSTEM CONSIDERATIONS EPROM power switching characteristics require careful device decoupling. System designers are in- terested in three supply current issuesstandby _ Surrents levels (Igg), active current levels (icc), and transient current peaks produced by falling and ris- ing edges of CE. Transient current magnitudes de- pend on the device outputs capacitive and inductive loading. Two-Line Control and proper decoupling ca- pacitor selection will suppress transient voitage peaks. Each device should have a 0.1 uF ceramic capacitor connected between its Voc and GND. This high frequency, low inherent-inductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 yF elec- trolytic capacitor should be placed at the arrays power supply connection between Vcc and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. ERASURE CHARACTERISTICS ' Erasure begins when EPROMs are exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain fluorescent lamps have wavelengths in the 3000-4000A range. Data shows that constant expo- sure to room level fluorescent lighting can erase an EPROM in approximately 3 years, while it takes ap- proximately t week when exposed to direct sunlight. It the device is exposed to these lighting conditions for extended periods, opaque labels should be placed over the window to prevent unintentional era- sure. The recommended erasure procedure is exposure to uttraviolet light of wavelengths 2537A. The inter- grated dose (UV intensity < exposure time) for era- sure should be a minimum of 15 Wsec/cm?. Erasure time is approximately 15 to 20 minutes using an ul- traviolet lamp with a 12000 uW/cm2 power rating. The EPROM should be placed within 1 inch of the lamp tubes. An EPROM can be permanently dam- aged if the integrated dose exceeds 7258 Wsec/ om? (1 week @ 12000 pW/cm2):- 5-11727C400 PRELIMINARY ADBRESS=FIRST LOCATION Vec=6.25 BYTE/Vpp=12.75V PROGRAM ONE 100 ys PULSE ) INCREMENT X VERIFY ONE WORD LAST vl INCREMENT ADDRESS ADDRESS ee : ? / a YES Vog=BYTE/Vpp=5.0V COMPARE ALL WORDS TO ORIGINAL DATA DEVICE PASSED YES <> PASS FAIL PASS . 290273-8 Quick-Pulse Programming Aigorithm The Quick-Pulse Programming algorithm pro- grams Intels 27C400. Developed to substantially re- duce programming throughput, this algorithm can program the 27C400 as fast as 28 seconds. Actual programming time depends on programmer over- head. The Quick-Pulse Programming algorithm employs a 100 ys pulse followed by a word verification to Figure 3. Quick-Pulse Programming Algorithm determine when the addressed word has been suc- cessfully programmed. The. algorithm terminates. if 25 attempts fail to program a word. . The entire Programm-puise/word verily sequence is performed with /Vpp = 12.75V and Voc = 6.25V. When programming is complete, all words are compared to the original data with Vcc = BYTE/Vpp = 5.0V. 5-118intel. 270400 PRELIMINARY DC PROGRAMMING CHARACTERISTICS T, = 25C + 5C Symbol Parameter Notes Min Typ Max | Unit | Test Conditions to Input Load Current 1 PA | Vin = Vicor Vin lop Vocp Program Current . 1 50 mA | CE = ViL Ipp Vpp Program Current _ 1 50 | mA | CE=Vi_ Vit Input Low Voltage ~0.1 os | Vv Vin Input High Voltage 2.4 6.5 Vv VoL Output Low Voltage (Verify) 0.45 Vv lo. = 2.1 mA Vou Output High Voltage (Verify) 3.5 Vv lon = 2.5mA Vio Ag intgligent Identifer Voltage | 11.5 12.0 | 12.5 Vv Vpp Vpp Program Voltage 2,3 12.5 | 12.75 | 13.0 Vv Vop Voc Supply Voltage (Program) 2 6.0 6.25 6.5 V- AC PROGRAMMING CHARACTERISTICS@ T, = 25C + 5C Symbol Parameter Notes Min Typ Max Unit tvcs Vcp Setup Time 2 2 | ps tyes Vpp Setup Time 2 ps tas Address Setup Time ps tos Data Setup Time ~ 2 ps tpw CE Program Pulse Width 95 100 105 ps tox Data Hold Time ps toes GE Setup Time pS toe Data Valid from OF 5 150 ns toFp GE High to Output High Z 5,6 130 ns taH Address Hold Time 0 ps NOTES: 1. Maximum current is with outputs O9-O,5 unloaded. 2. Vep must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 3. When programming, a 0.1 uF capacitor is required between Vpp and GND to suppress spurious voltage transients, which can damage the device. 4. See AC Input/Output Reference Waveform for timing measurements. 5. toe and tprp are device characteristics but must be accommodated by the programmer. 6. Sampled, not 100% tested. 5-119intel. 270400 PRELIMINARY. PROGRAMMING WAVEFORMS ADDRESSES %-15 BYTE/Vpp Ma Vin ADDRESS STABLE as Vin Vin DATA IN STABLE tos 200273-10 5-120