IS62WV12816EALL
IS62/65WV12816EBLL
Integrated Silicon Solution, Inc.- www.issi.com 1
Rev. C1
07/18/2016
128Kx16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
KEY FEATURES
High-speed access time: 45ns, 55ns
CMOS low power operation
– Operating Current: 18 mA (max) at 85°C
– CMOS Standby Current: 5.4uA (typ) at 25°C
TTL compatible interface levels
Single power supply
–1.65V-2.2V VDD (IS62WV12816EALL)
– 2.2V-3.6V VDD (IS62/65WV12816EBLL)
Three state outputs
Industrial and Automotive temperature support
Lead-free available
DESCRIPTION
The ISSI IS62/65WV12816EALL/EBLL are high-speed, 2M
bit static RAMs organized as 128K words by 16 bits. It is
fabricated using ISSI's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit
design techniques, yields high-performance and low power
consumption devices.
When CS1# is HIGH (deselected) or when CS2 is LOW
(deselected) or when CS1# is LOW, CS2 is HIGH and both
LB# and UB# are HIGH, the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE#) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB#) and Lower Byte (LB#)
access.
The IS62/65WV12816EALL/EBLL are packaged in the
JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-Pin
TSOP (TYPE II)
BLOCK DIAGRAM
COLUMN I/O
CS1#
CS2
WE#
UB#
OE#
LB#
CONTROL
CIRCUIT
I/O
DATA
CIRCUIT
128K x 16
MEMORY
ARRAY
DECODER
VDD
GND
A0 – A16
I/O0 – I/O7
Lower Byte
I/O8 – I/O15
Upper Byte
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
JULY 2016
IS62WV12816EALL
IS62/65WV12816EBLL
Integrated Silicon Solution, Inc.- www.issi.com 2
Rev. C1
07/18/2016
PIN CONFIGURATIONS
48-Pin mini BGA (6mm x 8mm)
(Package Code B)
LB# A0OE3 A1 A2 NC
I/O8 A3UB# A4 CS1# I/O0
I/O9 A5I/O10 A6 I/O1 I/O2
GND NCI/O11 A7 I/O3 VDD
VDD NCI/O12 A16 I/O4 GND
I/O14 A14I/O13 A15 I/O5 I/O6
I/O15 A12NC A13 WE# I/O7
NC A9A8 A10 A11 NC
1 2 3 4 5 6
A
B
C
D
D
F
G
H
48-Pin mini BGA (6mm x 8mm)
2 CS Option (Package Code B2)
LB# A0OE3 A1 A2 CS2
I/O8 A3UB# A4 CS1# I/O0
I/O9 A5I/O10 A6 I/O1 I/O2
GND NCI/O11 A7 I/O3 VDD
VDD NCI/O12 A16 I/O4 GND
I/O14 A14I/O13 A15 I/O5 I/O6
I/O15 A12NC A13 WE# I/O7
NC A9A8 A10 A11 NC
1 2 3 4 5 6
A
B
C
D
D
F
G
H
PIN DESCRIPTIONS
A0-A16
I/O0-I/O15
CS1#,
CS2
OE#
WE#
LB#
UB#
NC
VDD
GND
44-Pin mini TSOP (Type II)
(Package Code T)
A4
A3
A2
A1
A0
CS#
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE#
A16
A15
A14
A13
A12
A5
A6
A7
OE#
UB#
LB#
I/O15
I/O14
I/O13
I/O12
VDD
GND
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
1
2
3
4
5
6
7
8
9
10
12
11
13
14
15
16
32
31
30
29
28
27
26
25
24
23
21
22
20
19
18
17
42
41
40
39
38
37
36
35
34
33
44
43
IS62WV12816EALL
IS62/65WV12816EBLL
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Rev. C1
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FUNCTION DESCRIPTION
SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM
has three different modes supported. Each function is described below with Truth Table.
STANDBY MODE
Device enters standby mode when deselected (CS1# HIGH or CS2 LOW or both UB# and LB# are HIGH). The input
and output pins (I/O0-15) are placed in a high impedance state. The current consumption in this mode will be ISB1 or
ISB2. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input LOW. The input
and output pins (I/O0-15) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB#
and LB# enables a byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the
location specified on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written
into the location.
READ MODE
Read operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input HIGH. When
OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB#
and LB# enables a byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB#
being LOW, data from memory appears on I/O8-15.
In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
TRUTH TABLE
Mode
CS1#
CS2
WE#
OE#
LB#
UB#
I/O0-I/O7
I/O8-I/O15
VDD Current
Not Selected
H
X
X
X
X
X
High-Z
High-Z
ISB1,ISB2
X
L
X
X
X
X
High-Z
High-Z
X
X
X
X
H
H
High-Z
High-Z
Output Disabled
L
H
H
H
L
X
High-Z
High-Z
ICC
L
H
H
H
X
L
High-Z
High-Z
Read
L
H
H
L
L
H
DOUT
High-Z
ICC
L
H
H
L
H
L
High-Z
DOUT
L
H
H
L
L
L
DOUT
DOUT
Write
L
H
L
X
L
H
DIN
High-Z
ICC
L
H
L
X
H
L
High-Z
DIN
L
H
L
X
L
L
DIN
DIN
IS62WV12816EALL
IS62/65WV12816EBLL
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Rev. C1
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ABSOLUTE MAXIMUM RATINGS
AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
Vterm
Terminal Voltage with Respect to GND
–0.2 to +3.9(VDD+0.3V)
V
tBIAS
Temperature Under Bias
–55 to +125
C
VDD
VDD Related to GND
–0.2 to +3.9(VDD+0.3V)
V
tStg
Storage Temperature
–65 to +150
C
IOUT(2)
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.
This condition is not per pin. Total current of all pins must meet this value.
OPERATING RANGE (1)
Range
Device Marking
Ambient Temperature
VDD
Commercial
IS62WV12816EALL
0C to +70C
1.65V-2.2V
Industrial
IS62WV12816EALL
-40C to +85C
1.65V-2.2V
Commercial
IS62WV12816EBLL
0C to +70C
2.2V-3.6V
Industrial
IS62WV12816EBLL
-40C to +85C
2.2V-3.6V
Automotive
IS65WV12816EBLL
-40C to +125C
2.2V-3.6V
Note:
1. Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization.
PIN CAPACITANCE (1)
Parameter
Symbol
Test Condition
Max
Units
Input capacitance
CIN
TA = 25°C, f = 1 MHz, VDD = VDD(typ)
10
pF
DQ capacitance (IO0–IO15)
CI/O
10
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
THERMAL CHARACTERISTICS (1)
Parameter
Symbol
Rating
Units
Thermal resistance from junction to ambient (airflow = 1m/s)
RθJA
TBD
°C/W
Thermal resistance from junction to pins
RθJB
TBD
°C/W
Thermal resistance from junction to case
RθJC
TBD
°C/W
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
IS62WV12816EALL
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Rev. C1
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AC TEST CONDITIONS (OVER THE OPERATING RANGE)
Parameter
Unit
(1.65V~2.2V)
Unit
(2.2V~3.6V)
Input Pulse Level
0V to VDD
0V to VDD
Input Rise and Fall Time
1V/ns
1V/ns
Output Timing Reference Level
0.9V
½ VDD
R1
13500
1005
R2
10800
820
VTM
1.8V
VDD
Output Load Conditions
Refer to Figure 1 and 2
OUTPUT LOAD CONDITIONS FIGURES
R1
R2
VTM
OUTPUT 30pF,
Including
jig
and scope
R1
R2
VTM
OUTPUT 5pF,
Including
jig
and scope
FIGURE 1 FIGURE 2
IS62WV12816EALL
IS62/65WV12816EBLL
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Rev. C1
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ELECTRICAL CHARACTERISTICS
IS62WV12816EALL
DC ELECTRICAL CHARACTERISTICS-I
(OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = -0.1 mA
1.4
—
V
VOL
Output LOW Voltage
IOL = 0.1 mA
—
0.2
V
VIH
(1)
Input HIGH Voltage
1.4
VDD + 0.2
V
VIL
(1)
Input LOW Voltage
–0.2
0.4
V
ILI
Input Leakage
GND < VIN < VDD
–1
1
µA
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
µA
Notes:
1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested.
IS62(5)WV12816EBLL
DC ELECTRICAL CHARACTERISTICS-I
(OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
2.2 ≤ VDD < 2.7, IOH = -0.1 mA
2.0
—
V
2.7 ≤ VDD ≤ 3.6, IOH = -1.0 mA
2.4
—
V
VOL
Output LOW Voltage
2.2 ≤ VDD < 2.7, IOL = 0.1 mA
—
0.4
V
2.7 ≤ VDD ≤ 3.6, IOL = 2.1 mA
—
0.4
V
VIH
(1)
Input HIGH Voltage
2.2 ≤ VDD < 2.7
1.8
VDD + 0.3
V
2.7 ≤ VDD ≤ 3.6
2.2
VDD + 0.3
V
VIL
(1)
Input LOW Voltage
2.2 ≤ VDD < 2.7
–0.3
0.6
V
2.7 ≤ VDD ≤ 3.6
–0.3
0.8
V
ILI
Input Leakage
GND < VIN < VDD
–1
1
µA
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
µA
Notes:
1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested.
IS62WV12816EALL
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Rev. C1
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IS62WV12816EALL
DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Grade
55ns
Unit
Typ (1)
Max
ICC
VDD Dynamic Operating
Supply Current
VDD=VDD(max), IOUT=0mA, f = fmax
CS1# = VIL, CS2 = VIH
Com.
10
15
mA
Ind.
-
18
ICC1
VDD Static Operating
Supply Current
VDD=VDD(max), IOUT = 0mA, f=0
CS1# = VIL, CS2 = VIH
Com.
1
3
mA
Ind.
-
3
ISB2
CMOS Standby Current
(CMOS Inputs)
VDD = VDD(max), f = 0,
CS1# ≥ VDD - 0.2V or
0V ≤ CS2 ≤ 0.2V or
LB# and UB# ≥ VDD - 0.2V
VIN ≤ 0.2V or VIN ≥ VDD - 0.2V
Com.
25°C
5.4
10
µA
45°C
5.6
11
70°C
7.0
13
Ind.
85°C
7.6
16
Note:
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VDD = 1.8V
IS62(5)WV12816EBLL
DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Grade
45/55ns
Unit
Typ(1)
Max
ICC
VDD Dynamic Operating
Supply Current
VDD=VDD(max), IOUT=0mA, f = fmax
CS1# = VIL, CS2 = VIH
Com.
10
15
mA
Ind.
-
18
Auto.
-
25
ICC1
VDD Static Operating
Supply Current
VDD=VDD(max), IOUT = 0mA, f=0
CS1# = VIL, CS2 = VIH
Com.
1
3
mA
Ind.
-
3
Auto.
-
4
ISB2
CMOS Standby Current
(CMOS Inputs)
VDD = VDD(max), f = 0,
CS1# ≥ VDD - 0.2V or
0V ≤ CS2 ≤ 0.2V or
LB# and UB# ≥ VDD - 0.2V
VIN ≤ 0.2V or VIN ≥ VDD - 0.2V
Com.
25°C
5.4
10
µA
45°C
5.6
11
70°C
7.0
13
Ind.
85°C
7.6
16
Auto.
125°C
12.6
32
Note:
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VDD = 3.0V
IS62WV12816EALL
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Rev. C1
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AC CHARACTERISTICS
(6)
(OVER OPERATING RANGE)
READ CYCLE AC CHARACTERISTICS
Parameter
Symbol
45ns
55ns
unit
notes
Min
Max
Min
Max
Read Cycle Time
tRC
45
-
55
-
ns
1,5
Address Access Time
tAA
-
45
-
55
ns
1
Output Hold Time
tOHA
8
-
8
-
ns
1
CS1#, CS2 Access Time
tACS1/tACS2
-
45
-
55
ns
1
OE# Access Time
tDOE
-
22
-
25
ns
1
OE# to High-Z Output
tHZOE
-
18
-
18
ns
2
OE# to Low-Z Output
tLZOE
5
-
5
-
ns
2
CS1#, CS2 to High-Z Output
tHZCS/tHZCS2
-
18
-
18
ns
2
CS1#, CS2 to Low-Z Output
tLZCS/tLZCS2
10
-
10
-
ns
2
UB#, LB# Access Time
tBA
45
55
ns
1,7
UB#, LB# to High-Z Output
tHZB
-
18
-
18
ns
2
UB#, LB# to Low-Z Output
tLZB
10
-
10
-
ns
2
WRITE CYCLE AC CHARACTERISTICS
Parameter
Symbol
45ns
55ns
unit
notes
Min
Max
Min
Max
Write Cycle Time
tWC
45
-
55
-
ns
1,3,5
CS1#, CS2 to Write End
tSCS1/tSCS2
35
-
40
-
ns
1,3
Address Setup Time to Write End
tAW
35
-
40
-
ns
1,3
Address Hold from Write End
tHA
0
-
0
-
ns
1,3
Address Setup Time
tSA
0
-
0
-
ns
1,3
UB#,LB# to Write End
tPWB
35
-
40
-
ns
1,3
WE# Pulse Width
tPWE
35
-
40
-
ns
1,3,4
Data Setup to Write End
tSD
28
-
28
-
ns
1,3
Data Hold from Write End
tHD
0
-
0
-
ns
1,3
WE# LOW to High-Z Output
tHZWE
-
18
-
18
ns
2,3
WE# HIGH to Low-Z Output
tLZWE
10
-
10
-
ns
2,3
Notes:
1. Tested with the load in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. tHZOE, tHZCS, tHZB, and tHZWE transitions are
measured when the output enters a high impedance state. Not 100% tested.
3. The internal write time is defined by the overlap of CS1# = LOW, CS2=HIGH, UB# or LB# = LOW, and WE# = LOW. All four conditions must be
in valid states to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.
4. tPWE > tHZWE + tSD when OE# is LOW.
5. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with standby
mode is acceptable.
6. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS.
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TIMING DIAGRAM
READ CYCLE NO. 1(1) (ADDRESS CONTROLLED, CS1# = OE# = UB# = LB# = LOW, CS2 = WE# = HIGH)
tRC
Address
DOUT
tOHA tOHA
tAA
PREVIOUS DATA VALID DATA VALIDLOW-Z
Note:
1. The device is continuously selected.
READ CYCLE NO.2 (1) (OE# CONTROLLED)
OE#
CS1#
DOUT
tAA
ADDRESS
tRC
tOHA
tDOE
tLZOE
tACS1/tACS2
tLZCS1/
tLZCS2
tHZOE
tHZCS1/
tHZCS2
HIGH-Z DATA VALID
tLZB tHZB
tBA
UB#,LB#
CS2
LOW-Z
Note:
1. Address is valid prior to or coincident with CS1# LOW or CS2 HIGH transition.
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WRITE CYCLE NO.1 (1, 2) (CS1# , CS2 Controlled, OE# = HIGH or LOW)
ADDRESS
CS1#
CS2
WE#
UB#, LB#
DOUT
DIN
tWC
tHA
tAW tPWE
tPWB
tSA
tHZWE tLZWE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
DATA UNDEFINED
tSCS1
(1)
(2)
tSCS2
Notes:
1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before Write
Cycle. tHZOE is the time DOUT goes to High-Z after OE# goes high.
2. During this period, the I/Os are in output state. Do not apply input signals.
WRITE CYCLE NO. 2 (1, 2) (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE)
ADDRESS
CS1#
CS2
WE#
UB#, LB#
DOUT
DIN
tWC
tHA
tAW tPWE
tPWB
tSA
tHZOE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
DATA UNDEFINED
tSCS1
(1)
(2)
tSCS2
OE#
Notes:
1. tHZOE is the time DOUT goes to High-Z after OE# goes high.
2. During this period, the I/Os are in output state. Do not apply input signals.
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WRITE CYCLE NO. 3 (1) (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE)
ADDRESS
CS1#
CS2
WE#
UB#, LB#
DOUT
DIN
tWC
tHA
tAW tPWE
tPWB
tSA
tHZWE tLZWE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
DATA UNDEFINED
tSCS1
(1)
(2)
tSCS2
Notes:
3. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the
previous READ operation will drive IO BUS.
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WRITE CYCLE NO. 4 (1, 2, 3) (UB# & LB# Controlled, OE# = LOW)
ADDRESS
CS2=HIGH
WE#
DOUT
DIN
tSA
tHZWE
tPWB
tHA
DATA IN
VALID
ADDRESS 1 ADDRESS 2
tWC
DATA IN
VALID
DATA UNDEFINED tHD
tSD
HIGH-Z tLZWE
WORD 1 WORD 2
UB#, LB#
tHA
OE#=LOW
CS1#=LOW
tSA
tPWB
tWC
Notes:
1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the
previous READ operation will drive IO BUS.
2. Due to the restriction of note1, OE# is recommended to be HIGH during write period.
3. WE# stays LOW in this example. If WE# toggles, tPWE and tHZWE must be considered.
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Rev. C1
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DATA RETENTION CHARACTERISTICS
Symbol
Parameter
Test Condition
OPTION
Min
Typ(2)
Max
Unit
VDR
VDD for Data
Retention
See Data Retention Waveform
1.5
-
3.6
V
IDR
Data Retention
Current
VDD= VDR(min),
CS1# ≥ VDD – 0.2V,(1) or
0V ≤ CS2 ≤ 0.2V, or
LB# and UB# ≥ VDD -0.2V,
VIN ≤ 0.2V or VIN ≥ VDD - 0.2V
Com.
-
5.4
13
uA
Ind.
-
16
Auto A3
-
32
tSDR
Data Retention
Setup Time
See Data Retention Waveform
0
-
-
ns
tRDR
Recovery Time
See Data Retention Waveform
tRC
-
-
ns
Notes:
1. If CS1# >VDD–0.2V, all other inputs including CS2 and UB# and LB# must meet this condition.
2. Typical values are measured at VDD=1.8V or 3V, TA = 25C, and not 100% tested.
DATA RETENTION WAVEFORM (CS1# CONTROLLED)
GND CS1#
VDR
VDD
CS1# > VDD – 0.2V
Data Retention Mode
tSDR tRDR
DATA RETENTION WAVEFORM (CS2 CONTROLLED)
GND
VDR
VDD
CS2 < 0.2V
Data Retention Mode
tSDR tRDR
CS2
IS62WV12816EALL
IS62/65WV12816EBLL
Integrated Silicon Solution, Inc.- www.issi.com 14
Rev. C1
07/18/2016
DATA RETENTION WAVEFORM (UB# AND LB# CONTROLLED)
GND
UB#/LB#
VDR
VDD
UB# and LB# > VDD – 0.2V
Data Retention Mode
tSDR tRDR
Note:
1. CS2 must satisfy either CS2 ≥ VDD -0.2V or CS2 ≤ 0.2V
2. CS1# must satisfy either CS1# ≥ VDD - 0.2V or CS1# ≤ 0.2V
IS62WV12816EALL
IS62/65WV12816EBLL
Integrated Silicon Solution, Inc.- www.issi.com 15
Rev. C1
07/18/2016
ORDERING INFORMATION
IS62WV12816EALL (1.65V - 2.2V)
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
55
IS62WV12816EALL-55TI
TSOP (Type II)
IS62WV12816EALL-55TLI
TSOP (Type II), Lead-free
IS62WV12816EALL-55BI
mini BGA (6mm x 8mm)
IS62WV12816EALL-55B2I
mini BGA (6mm x 8mm), 2 CS Option
IS62WV12816EALL-55BLI
mini BGA (6mm x 8mm), Lead-free
IS62WV12816EBLL (2.2V - 3.6V)
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
45
IS62WV12816EBLL-45TLI
TSOP (Type II), Lead-free
IS62WV12816EBLL-45BLI
mini BGA (6mm x 8mm), Lead-free
IS62WV12816EBLL-45B2LI
mini BGA (6mm x 8mm), 2 CS Option, Lead-free
55
IS62WV12816EBLL-55TI
TSOP (Type II)
IS62WV12816EBLL-55TLI
TSOP (Type II), Lead-free
IS62WV12816EBLL-55BI
mini BGA (6mm x 8mm)
IS62WV12816EBLL-55BLI
mini BGA (6mm x 8mm), Lead-free
IS62WV12816EBLL-55B2I
mini BGA (6mm x 8mm), 2 CS Option
IS62WV12816EBLL-55B2LI
mini BGA (6mm x 8mm), 2 CS Option, Lead-free
IS65WV12816EBLL (2.2V - 3.6V)
Automotive Range (A3): –40°C to +125°C
Speed (ns)
Order Part No.
Package
55
IS65WV12816EBLL-55CTLA3
TSOP (Type II), Lead-free, Copper Leadframe
IS65WV12816EBLL-55BLA3
mini BGA (6mm x 8mm), Lead-free
IS62WV12816EALL
IS62/65WV12816EBLL
Integrated Silicon Solution, Inc.- www.issi.com 16
Rev. C1
07/18/2016
PACKAGE INFORMATION
IS62WV12816EALL
IS62/65WV12816EBLL
Integrated Silicon Solution, Inc.- www.issi.com 17
Rev. C1
07/18/2016