HN27C4001G Series 524288-word x 8-bit CMOS UV Erasable and Programmable ROM Rev. 2.0 May. 25, 1995. The Hitachi HN27C4001G is a 4-Mbit ultravioiet erasable and electrically programmable ROM, featuring high speed and low power dissipation. Fabricated on abvanced fine process and higt speed circuity technique, the HN27C4001G makes high speed access time possibie. Therefore, it is suitable for high speed microcomputer systems. The HN27C4001G offers high speed programming using page programming mode. Ordering Information Type No. Access time Package ---------------------------------------- HN27C4001G-10 100 ns -------------------------- HN27C4001G-12 120 ns 600-mil 32-pin cerdip (DG-32A) -------------------------- HN27C4001G-15 150 ns ---------------------------------------- Features * High speed: Access time100 ns/120 ns/150 ns(max) * Low power dissipation: Standby mode; 5 W (typ), Active mode; 35 mW/MHz (typ) * Fast high-reliability page programming and fast high-reliability programming: Program voltage; +12.5 V DC Program time; 3.5 sec (min) (Theoretical in Page programming) * Inputs and outputs TTL compatible during both read and program modes * Pin arrangement: 32-pin JEDEC standard * Device identifier mode: Manufacturer code and device code ADE-203-362B(Z) HN27C4001G Series Pin Arrangement VPP 1 32 VCC A16 2 31 A18 A15 3 30 A17 A12 4 29 A14 A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 VSS 15 18 I/O4 16 17 I/O3 Pin Description Pin name Function ---------------------------------------- A0 - A18 Address ---------------------------------------- I/O0 - I/O7 Input/output ---------------------------------------- CE Chip enable ---------------------------------------- OE Output enable ---------------------------------------- VCC Power supply ---------------------------------------- VPP Programming power supply ---------------------------------------- VSS Ground ---------------------------------------- 2 HN27C4001G Series Block Diagram A6 : : A9 4,096 x 1,024 Memory Matrix XDecoder A11 : : A18 I/O0 : : : Y-Gating Input Data Control I/O7 Y-Decoder CE A0 . . . . . . . . . . . . . A5,A10 H OE V CC V PP H H V SS : High threshold inverter Mode Selection CE OE A9 VPP VCC I/O ------------------------------------------------------------- Mode (22) (24) (26) (1) (32) (13 - 15, 17 - 21) ------------------------------------------------------------------------------------ Read VIL VIL X VIL VIH X VIH X X VSS - VCC VCC Dout VSS - VCC VCC High-Z VSS - VCC VCC High-Z ------------------------------------------------------------------------------------ Output disable ------------------------------------------------------------------------------------ Standby ------------------------------------------------------------------------------------ 3 HN27C4001G Series Mode Selection (cont) CE OE A9 VPP VCC I/O (1) (32) (13 - 15, 17 - 21) --------------------------------------------------------- Mode (22) (24) (26) ------------------------------------------------------------------------------------- Page program set VIH VH*2 X VPP VCC High-Z -------------------------------------------------------------------------- Page data latch VIL VH*2 X VPP VCC Din Page -------------------------------------------------------------------------- programming Page program VIL VIH X VPP VCC High-Z -------------------------------------------------------------------------- Page program verify VIH VIL X VIH VIH X VIL VIH X VPP VCC Dout VCC VCC High-Z VPP VCC Din -------------------------------------------------------------------------- Page program reset ------------------------------------------------------------------------------------- Program -------------------------------------------------------------------------- Word Program verify VIH VIL X VPP VCC Dout programming -------------------------------------------------------------------------- Optional verify VIL VIL X VPP VCC Dout -------------------------------------------------------------------------- Program inhibit VIH VIH X VIL VIL VH*2 VPP VCC High-Z VSS - VCC VCC Code ------------------------------------------------------------------------------------- Identifier ------------------------------------------------------------------------------------- Notes: 1. 2. X: Don't care. VH: 12.0 V 0.5 V Absolute Maximum Ratings Parameter Symbol Value Unit ------------------------------------------------------------------------------------ All input and output voltages *1 Vin, Vout -0.6*2 to +7.0 V ------------------------------------------------------------------------------------ A9 , OE input Voltage *1 VID -0.6*2 to +13.0 V ------------------------------------------------------------------------------------ VPP voltage *1 VPP -0.6 to +13.5 V ------------------------------------------------------------------------------------ VCC voltage *1 VCC -0.6 to +7.0 V ------------------------------------------------------------------------------------ Operating temperature range Topr 0 to +70 C ------------------------------------------------------------------------------------ Storage temperature range *3 Tstg -65 to +125 C ------------------------------------------------------------------------------------ Storage temperature under bias Tbias -20 to +80 C ------------------------------------------------------------------------------------ Notes: 1. 2. 3. Relative to VSS. Vin, Vout, VID min = -2.0 V for pulse width < 20 ns Storage temperature range of device before programming. 4 HN27C4001G Series Capacitance (Ta = 25C, f = 1 MHz) Parameter Symbol Min Typ Max Unit Test conditions -------------------------------------------------------------------------------------- Input capacitance Cin -- -- 12 pF Vin = 0 V -------------------------------------------------------------------------------------- Output capacitance Cout -- -- 20 pF Vout = 0 V -------------------------------------------------------------------------------------- Read Operation DC Characteristics (VCC = 5 V 10%, VPP = VSS to VCC, Ta = 0 to +70C) Parameter Symbol Min Typ Max Unit Test conditions -------------------------------------------------------------------------------------- Input leakage current ILI -- -- 2 A Vin = 5.5 V -------------------------------------------------------------------------------------- Output leakage current ILO -- -- 2 A Vout = 5.5 V/0.45 V -------------------------------------------------------------------------------------- VPP current IPP1 -- 1 20 A VPP = 5.5 V -------------------------------------------------------------------------------------- Standby VCC current ISB1 -- -- 1 mA CE = VIH ---------------------------------------------------------- ISB2 -- 1 20 A CE = VCC 0.3 V -------------------------------------------------------------------------------------- Operating VCC current ICC1 -- -- 30 mA Iout = 0 mA, f = 1 MHz ---------------------------------------------------------- ICC2 -- -- 100 mA Iout = 0 mA, f = 10 MHz -------------------------------------------------------------------------------------- Input voltage VIL -0.3*1 -- 0.8 V ---------------------------------------------------------- VIH 2.2 -- VCC+1*2 V -------------------------------------------------------------------------------------- Output voltage VOL -- -- 0.45 V IOL = 2.1 mA ---------------------------------------------------------- VOH 2.4 -- -- V IOH = -400 A -------------------------------------------------------------------------------------- Notes: 1. VIL min = -1.0 V for pulse width < 50 ns VIL min = -2.0 V for pulse width < 20 ns 2. VIH max = VCC +1.5 V for pulse width < 20 ns If VIH is over the specified maximum value, read operation cannot be guaranteed. 5 HN27C4001G Series AC Characteristics (VCC = 5 V 10%, VPP = VSS to VCC, Ta = 0 to +70C) Test Conditions * Input pulse levels: 0.45 to 2.4 V * Input rise and fall times: < 10 ns * Output load: 1 TTL gate +100 pF * Reference levels for measuring timing: 0.8 V, 2.0 V HN27C4001G -------------------------------- -10 -12 -15 -------------------------------- Parameter Symbol Min Max Min Max Min Max Unit Test conditions -------------------------------------------------------------------------------------- Address to output delay tACC -- tCE -- tOE -- tDF 0 tOH 5 100 -- 120 -- 150 ns CE = OE = VIL -------------------------------------------------------------------------------------- CE to output delay 100 -- 120 -- 150 ns OE = VIL -------------------------------------------------------------------------------------- OE to output delay 60 -- 60 -- 70 ns CE = VIL -------------------------------------------------------------------------------------- OE high to output float *1 35 0 40 0 50 ns CE = VIL -------------------------------------------------------------------------------------- Address to output hold -- 5 -- 5 -- ns CE = OE = VIL -------------------------------------------------------------------------------------- Note: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. Read Timing Waveform Address CE Standby mode Active mode Standby mode tCE OE tDF tOE tOH t ACC Data Out Data Out Valid 6 HN27C4001G Series Fast High-Reliability Page Programming This device can be applied the fast high-reliablity page programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. Page Program set Page Program Reset Apply 12 V to OE pin after applying 12.5 V to VPP to set a page program mode. The device operates in a page program mode until reset. Set V PP to V CC level or less to reset a page program mode. START SET PAGE PROG. LATCH MODE VPP= 12.5 0.3 V VCC = 6.25 0.25 V OE = 12.0 0.5 V Address = 0 n=0 m=0 Latch Address + 1 Address m + 1 m NO m=8? YES n + 1 n SET PAGE PROG./VERIFY MODE VPP= 12.5 0.3 V VCC = 6.25 0.25 V Address + 1 Address Program tPW = 50 s 5% VERIFY NO NOGO GO LAST address? n = 10? YES SET READ MODE VCC = 5.0 0.5 V VPP = VCC READ all address NO YES NOGO GO END FAIL Fast High-Reliability Page Programming Flowchart 7 HN27C4001G Series DC Characteristics (VCC = 6.25 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C) Parameter Symbol Min Typ Max Unit Test conditions -------------------------------------------------------------------------------------- Input leakage current ILI -- -- 2 A Vin = 6.5 V/0.45 V -------------------------------------------------------------------------------------- VPP supply current IPP -- -- 70 mA CE=VIL -------------------------------------------------------------------------------------- Operating VCC current ICC -- -- 50 mA -------------------------------------------------------------------------------------- Input voltage VIL -0.1*5 -- 0.8 V ------------------------------------------------------------ VIH 2.2 -- VCC+0.5*6 V ------------------------------------------------------------ VH 11.5 12.0 12.5 V -------------------------------------------------------------------------------------- Output voltage during verify VOL -- -- 0.45 V IOL = 2.1 mA ------------------------------------------------------------ VOH 2.4 -- -- V IOH = -400 A -------------------------------------------------------------------------------------- Notes: 1. VCC must be applied before VPP and removed after VPP. 2. VPP must not exceed 13 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.5 V. 4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low. 5. VIL min = -0.6 V for pulse width < 20 ns. 6. If VIH is over the specified maximum value, programming operation cannot be guaranteed. 8 HN27C4001G Series AC Characteristics (VCC = 6.25 V 0.25 V, VPP = 12.5 V 0.3 V, Ta=25C 5C) Test Conditions * Input pulse levels: 0.45 to 2.4 V * Input rise and fall times: < 20 ns Parameter * Reference levels for measuring timing: Inputs; 0.8 V, 2.0 V, Outputs; 0.8 V, 2.0 V Symbol Min Typ Max Unit Test conditions -------------------------------------------------------------------------------------- Address setup time tAS 2 -- -- s -------------------------------------------------------------------------------------- OE setup time tOES 2 -- -- s -------------------------------------------------------------------------------------- Data setup time tDS 2 -- -- s -------------------------------------------------------------------------------------- Address hold time tAH 0 -- -- s -------------------------------------------------------------------------------------- Data hold time tDH 2 -- -- s -------------------------------------------------------------------------------------- OE high to output float delay tDF*1 0 -- 130 ns -------------------------------------------------------------------------------------- VPP setup time tVPS 2 -- -- s -------------------------------------------------------------------------------------- VCC setup time tVCS 2 -- -- s -------------------------------------------------------------------------------------- CE initial programming pulse width tPW 47.5 50.0 52.5 s -------------------------------------------------------------------------------------- CE setup time tCES 2 -- -- s -------------------------------------------------------------------------------------- Data valid from OE tOE 0 -- 150 ns -------------------------------------------------------------------------------------- CE pulse width during data latch tLW 1 -- -- s -------------------------------------------------------------------------------------- OE = VH setup time tOHS 2 -- -- s -------------------------------------------------------------------------------------- OE = VH hold time tOHH 2 -- -- s -------------------------------------------------------------------------------------- VPP hold time*2 tVRS 1 -- -- s -------------------------------------------------------------------------------------- Notes: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. Page program mode will be reset when VPP is set to VCC or less. 9 HN27C4001G Series Fast High-Reliability Page Programming Timing Waveform Page program mode Program data latch Page program Program verify A3 - A18 t AH t AS 0 A0 - A2 1 t AS 0 7 t DH 0 Data in stable 1 1 7 t OE t DF t DS Data t AH 0 7 1 7 Data out valid t VPS VPP VPP VCC t VCS VCC + 1.25 VCC t OHH VCC t CES t PW t OES t OHS CE t LW OE VH t VRS VIH VIL 10 HN27C4001G Series Fast High-Reliability Programming This device can be applied the fast high-reliability programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. START SET PROG./VERIFY MODE VPP = 12.5 0.3 V V CC = 6.25 0.25 V Address = 0 n=0 n+1 n Program tPW = 50 s 5% Address + 1 VERIFY GO Address NO NOGO n = 10? LAST address? NO YES YES SET READ MODE VCC = 5.0 0.5 V VPP = VCC READ all address NOGO GO END FAIL Fast High-Reliability Programming Flowchart 11 HN27C4001G Series DC Characteristics (VCC = 6.25 V 0.25 V, VPP =12.5 V 0.3 V, Ta=25C 5C) Parameter Symbol Min Typ Max Unit Test conditions -------------------------------------------------------------------------------------- Input leakage current ILI -- -- 2 A Vin = 6.5 V/0.45 V -------------------------------------------------------------------------------------- VPP supply current IPP -- -- 40 mA CE = VIL -------------------------------------------------------------------------------------- Operating VCC current ICC -- -- 50 mA -------------------------------------------------------------------------------------- Input voltage VIL -0.1*5 -- 0.8 V ------------------------------------------------------------------ VIH 2.2 VCC +0.5*6 -- V -------------------------------------------------------------------------------------- Output voltage VOL -- -- 0.45 V IOL = 2.1 mA ------------------------------------------------------------------ VOH 2.4 -- -- V IOH = -400 A -------------------------------------------------------------------------------------- Notes: 1. VCC must be applied before VPP and removed after VPP. 2. VPP must not exceed 13 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.5 V. 4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low. 5. VIL min = -0.6 V for pulse width < 20 ns. 6. If VIH is over the specified maximum value, programming operation cannot be guaranteed. AC Characteristics (VCC = 6.25 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C) Test Conditions * Input pulse levels: 0.45 to 2.4 V * Input rise and fall times: < 20 ns Parameter * Reference levels for measuring timings: 0.8 V, 2.0 V Symbol Min Typ Max Unit Test conditions -------------------------------------------------------------------------------------- Address setup time tAS 2 tOES 2 tDS 2 tAH 0 tDH 2 tDF*1 0 VPP setup time tVPS 2 VCC setup time tVCS 2 CE initial programming pulse width tPW 47.5 tOE 0 -- -- s -------------------------------------------------------------------------------------- OE setup time -- -- s -------------------------------------------------------------------------------------- Data setup time -- -- s -------------------------------------------------------------------------------------- Address hold time -- -- s -------------------------------------------------------------------------------------- Data hold time -- -- s -------------------------------------------------------------------------------------- OE to output float delay -- 130 ns -------------------------------------------------------------------------------------- -- -- s -------------------------------------------------------------------------------------- -- -- s -------------------------------------------------------------------------------------- 50.0 52.5 s -------------------------------------------------------------------------------------- Data valid from OE -- 150 ns -------------------------------------------------------------------------------------- Note: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 12 HN27C4001G Series Fast High-Reliability Programming Timing Waveform Program Program Verify Address t AH t AS Data Data In Stable t DS V PP Data Out Valid t DF t DH V PP V CC t VPS V CC V CC+1.25 V CC t VCS CE t PW t OES t OE OE Optional Page Programming This device can be applied the optional page programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. This programming algorithm is the combination of page programming and byte verify. It can avoid the increase of programming verify time when a programmer with slow machine cycle is used, and shorten the total programming time. Regarding the timing specifications for page programming and byte verify, please refer to the specifications for fast high-reliability page programming and fast high-reliability programming. 13 HN27C4001G Series START SET PAGE PROG. LATCH MODE VPP= 12.5 0.3 V VCC = 6.25 0.25 V OE = 12.0 0.5 V Address = 0 m=0 Latch Address + 1 Address m=1 m NO m=8 YES SET PAGE PROG. MODE VPP = 12.5 0.3 V V CC = 6.25 0.25 V Address + 1 Program tPW = 50 s 5% Address NO LAST address? YES PAGE PROG. RESET VPP = VCC = 6.25 0.25 V SET WORD PROG./VERIFY MODE VPP = 12.5 0.3 V V CC = 6.25 0.25 V Address = 0 n=0 VERIFY GO NOGO n+1 Address + 1 Address n Program tPW = 50 s 5% VERIFY NOGO GO NO LAST address? n = 10? YES SET READ MODE VCC = 5.0 0.5 V VPP = VCC READ all address NO YES NOGO GO END FAIL Optional Page Programming Flowchart 14 HN27C4001G Series DC Characteristics (VCC = 6.25 V 0.25 V, VPP =12.5 V 0.3 V, Ta=25C 5C) Parameter Symbol Min Typ Max Unit Test conditions -------------------------------------------------------------------------------------- Input leakage current ILI -- -- 2 A Vin = 6.5 V/0.45 V -------------------------------------------------------------------------------------- Output voltage during verify VOL -- -- 0.45 V IOL = 2.1 mA ------------------------------------------------------------------ VOH 2.4 -- -- V IOH = -400 A -------------------------------------------------------------------------------------- Operating VCC current ICC -- -- 50 mA -------------------------------------------------------------------------------------- Input voltage VIL -0.1*5 -- 0.8 V ------------------------------------------------------------------ VIH 2.2 -- VCC +0.5*6 V ------------------------------------------------------------------ VH 11.5 12.0 12.5 V -------------------------------------------------------------------------------------- VPP supply current IPP -- -- 70 mA CE = VIL -------------------------------------------------------------------------------------- Notes: 1. VCC must be applied before VPP and removed after VPP. 2. VPP must not exceed 13 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.5 V. 4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low. 5. VIL min = -0.6 V for pulse width < 20 ns. 6. If VIH is over the specified maximum value, programming operation cannot be guaranteed. 15 HN27C4001G Series AC Characteristics (VCC = 6.25 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C) Test Conditions * Input pulse levels: 0.45 to 2.4 V * Input rise and fall times: < 20 ns * Reference levels for measuring timings: 0.8 V, 2.0 V Parameter Symbol Min Typ Max Unit Test conditions -------------------------------------------------------------------------------------- Address setup time tAS 2 -- -- s -------------------------------------------------------------------------------------- OE setup time tOES 2 -- -- s -------------------------------------------------------------------------------------- Data setup time tDS 2 -- -- s -------------------------------------------------------------------------------------- Address hold time tAH 0 -- -- s -------------------------------------------------------------------------------------- Data hold time tDH 2 -- -- s -------------------------------------------------------------------------------------- OE high to output float delay tDF*1 0 -- 130 ns -------------------------------------------------------------------------------------- VPP setup time tVPS 2 -- -- s -------------------------------------------------------------------------------------- VCC setup time tVCS 2 -- -- s -------------------------------------------------------------------------------------- CE initial programming pulse width tPW 47.5 50.0 52.5 s -------------------------------------------------------------------------------------- CE setup time tCES 2 -- -- s -------------------------------------------------------------------------------------- Data valid from OE tOE 0 -- 150 ns -------------------------------------------------------------------------------------- CE pulse width during data latch tLW 1 -- -- s -------------------------------------------------------------------------------------- OE = VH setup time tOHS 2 -- -- s -------------------------------------------------------------------------------------- OE = VH hold time tOHH 2 -- -- s -------------------------------------------------------------------------------------- Page programming reset time *2 tVLW 1 -- -- s -------------------------------------------------------------------------------------- VPP hold time *2 tVRS 1 -- -- s -------------------------------------------------------------------------------------- Notes: 1. 2. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. Page program mode will be reset when VPP is set to VCC or less. 16 HN27C4001G Series Optional Page Programming Timing Waveform Word program mode Page program mode Program data latch Page program Program verify Program A3 - A18 t AH t AS 0 A0, A2 t AH 1 t AS 7 t DH t DS t DS 0 Data in stable Data 1 Data out valid 7 t DF Data in stable t VPS t OE t DF t VPS VPP t AH VPP VCC t VRS t VCS t VLW VCC+ 1.25 VCC VCC t OHH t CES t CES t OHS CE t OES t LW t PW OE t PW VH VIH VIL 17 HN27C4001G Series Erase Mode Description Erasure of HN27C4001G is performed by exposure to ultraviolet light of 2537 A and all the output data are changed to "1" after this erasure procedure. The minimum integrated dose (i.e. UV intensity X exposure time) for erasure is 15 W*sec/cm2. Device Identifier Mode The device identifier mode allows the reading out of binary codes that manufacturer and type of device, from outputs of EPROM. By this mode, the device will be automatically matched its own corresponding programming algorithm, using programming equipment. HN27C4001G Identifier Code A0 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 -------------------------------------------------------------- Hex Identifier (12) (21) (20) (19) (18) (17) (15) (14) (13) Data -------------------------------------------------------------------------------------- Manufacturer code VIL 0 VIH 0 0 0 0 0 1 1 1 07 -------------------------------------------------------------------------------------- Device code 0 1 0 0 0 0 0 20 -------------------------------------------------------------------------------------- Notes: 1. 2. 3. 4. VCC = 5.0 V 10% A9 = 12.0 V 0.5 V CE, OE=VIL A1 - A8, A10 - A18: Don't care. 18 HN27C4001G Series Package Dimensions Unit: mm HN27C4001G Series (DG-32A) 41.91 43.18 Max 32 17 7.00 14.66 15.51 Max 17.00 1 16 15.24 2.54 0.25 0.48 0.10 2.54 Min 5.89 Max 0.38 Min 1.32 + 0.11 0.25 - 0.05 0 - 15 19