HN27C4001G Series
524288-word ×8-bit CMOS UV Erasable and Programmable ROM
Rev. 2.0
May. 25, 1995.
The Hitachi HN27C4001G is a 4-Mbit ultravioiet
erasable and electrically programmable ROM,
featuring high speed and low power dissipation.
Fabricated on abvanced fine process and higt speed
circuity technique, the HN27C4001G makes high
speed access time possibie. Therefore, it is suitable
for high speed microcomputer systems. The
HN27C4001G offers high speed programming
using page programming mode.
Features
High speed:
Access time100 ns/120 ns/150 ns(max)
Low power dissipation:
Standby mode; 5 µW (typ),
Active mode; 35 mW/MHz (typ)
Fast high-reliability page programming and fast
high-reliability programming:
Program voltage; +12.5 V DC
Program time; 3.5 sec (min)
(Theoretical in Page programming)
Inputs and outputs TTL compatible during both
read and program modes
Pin arrangement: 32-pin JEDEC standard
Device identifier mode: Manufacturer code and
device code
ADE-203-362B(Z)
Ordering Information
Type No. Access time Package
————————————————————
HN27C4001G-10 100 ns 600-mil
————————————— 32-pin cerdip
HN27C4001G-12 120 ns (DG-32A)
—————————————
HN27C4001G-15 150 ns
————————————————————
2
HN27C4001G Series
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
SS
V
A18
A17
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
CC
V
PP
Pin Description
Pin name Function
————————————————————
A0 – A18 Address
————————————————————
I/O0 – I/O7 Input/output
————————————————————
CE Chip enable
————————————————————
OE Output enable
————————————————————
VCC Power supply
————————————————————
VPP Programming power supply
————————————————————
VSS Ground
————————————————————
3
HN27C4001G Series
Block Diagram
Mode Selection
CE OE A9 VPP VCC I/O
——————————————————————————————–
Mode (22) (24) (26) (1) (32) (13 – 15, 17 – 21)
——————————————————————————————————————————
Read VIL VIL XV
SS – VCC VCC Dout
——————————————————————————————————————————
Output disable
VIL VIH XV
SS – VCC VCC High-Z
——————————————————————————————————————————
Standby VIH XXV
SS – VCC VCC High-Z
——————————————————————————————————————————
I/O0
:
:
:
I/O7
X-
Decoder
4,096 x 1,024
Memory Matrix
Y-Decoder
CE
OE
Input
Data
Control
Y-Gating
VCC
V
VSS
H
A0 A5,A10
H : High threshold inverter
A6
:
:
A9
A11
:
:
A18
PP
. . . . . . . . . . . . .
H
4
HN27C4001G Series
Mode Selection (cont)
CE OE A9 VPP VCC I/O
——————————————————–—————————––
Mode (22) (24) (26) (1) (32) (13 – 15, 17 – 21)
———————————————————————————–——————————————––
Page program set
VIH VH*2XV
PP VCC High-Z
———————————————————————————–—————————–
Page data latch
VIL VH*2XV
PP VCC Din
Page ———————————————————————————————————–—–
programming
Page program
VIL VIH XV
PP VCC High-Z
———————————————————————————————————–—–
Page program verify
VIH VIL XV
PP VCC Dout
———————————————————————————————————–—–
Page program reset
VIH VIH XV
CC VCC High-Z
—————————————————————————————————————————–––
Program VIL VIH XV
PP VCC Din
———————————————————————————————————–—–
Word Program verify VIH VIL XV
PP VCC Dout
programming ———————————————————————————————————–—–
Optional verify VIL VIL XV
PP VCC Dout
———————————————————————————————————–—–
Program inhibit VIH VIH XV
PP VCC High-Z
—————————————————————————————————————–————––
Identifier VIL VIL VH*2VSS – VCC VCC Code
—————————————————————————————————————–————––
Notes: 1. X: Don’t care.
2. VH: 12.0 V ± 0.5 V
Absolute Maximum Ratings
Parameter Symbol Value Unit
——————————————————————————————————————————
All input and output voltages *1Vin, Vout –0.6*2to +7.0 V
——————————————————————————————————————————
A9 , OE input Voltage *1VID –0.6*2to +13.0 V
——————————————————————————————————————————
VPP voltage *1VPP –0.6 to +13.5 V
——————————————————————————————————————————
VCC voltage *1VCC –0.6 to +7.0 V
——————————————————————————————————————————
Operating temperature range Topr 0 to +70 °C
——————————————————————————————————————————
Storage temperature range *3Tstg –65 to +125 °C
——————————————————————————————————————————
Storage temperature under bias Tbias –20 to +80 °C
——————————————————————————————————————————
Notes: 1. Relative to VSS.
2. Vin, Vout, VID min = –2.0 V for pulse width <20 ns
3. Storage temperature range of device before programming.
5
HN27C4001G Series
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter Symbol Min Typ Max Unit Test conditions
———————————————————————————————————————————
Input capacitance Cin 12 pF Vin = 0 V
———————————————————————————————————————————
Output capacitance Cout 20 pF Vout = 0 V
———————————————————————————————————————————
Read Operation
DC Characteristics (VCC = 5 V ± 10%, VPP = VSS to VCC, Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit Test conditions
———————————————————————————————————————————
Input leakage current ILI 2 µA Vin = 5.5 V
———————————————————————————————————————————
Output leakage current ILO 2 µA Vout = 5.5 V/0.45 V
———————————————————————————————————————————
VPP current IPP1 1 20 µA VPP = 5.5 V
———————————————————————————————————————————
Standby VCC current ISB1 ——1 mACE = VIH
—————————————————————————————
ISB2 1 20 µA CE = VCC ± 0.3 V
———————————————————————————————————————————
Operating VCC current ICC1 30 mA Iout = 0 mA, f = 1 MHz
—————————————————————————————
ICC2 100 mA Iout = 0 mA, f = 10 MHz
———————————————————————————————————————————
Input voltage VIL –0.3*1 0.8 V
—————————————————————————————
VIH 2.2 VCC+1*2V
———————————————————————————————————————————
Output voltage VOL 0.45 V IOL = 2.1 mA
—————————————————————————————
VOH 2.4 V IOH = –400 µA
———————————————————————————————————————————
Notes: 1. VIL min = –1.0 V for pulse width <50 ns
VIL min = –2.0 V for pulse width <20 ns
2. VIH max = VCC +1.5 V for pulse width <20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.
6
HN27C4001G Series
HN27C4001G
————————————————
-10 -12 -15
————————————————
Parameter Symbol Min Max Min Max Min Max Unit Test conditions
———————————————————————————————————————————
Address to output delay tACC 100 120 150 ns CE = OE = VIL
———————————————————————————————————————————
CE to output delay tCE 100 120 150 ns OE = VIL
———————————————————————————————————————————
OE to output delay tOE —60—60—70nsCE = VIL
———————————————————————————————————————————
OE high to output float *1tDF 035040050nsCE = VIL
———————————————————————————————————————————
Address to output hold tOH 5—5—5—nsCE = OE = VIL
———————————————————————————————————————————
Note: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no
longer driven.
Read Timing Waveform
Address
CE
OE
Data Out Data Out Valid
tACC
tCE
tOE tOH
tDF
Standby mode Active mode Standby mode
AC Characteristics (VCC = 5 V ± 10%, VPP = VSS to VCC, Ta = 0 to +70°C)
Test Conditions
Input pulse levels: 0.45 to 2.4 V
Input rise and fall times: < 10 ns
Output load: 1 TTL gate +100 pF
Reference levels for measuring timing:
0.8 V, 2.0 V
Page Program set
Apply 12 V to
OE
pin after applying 12.5 V to
VPP to set a page program mode.
The device operates in a page program mode until
reset.
7
HN27C4001G Series
START
SET PAGE PROG. LATCH MODE
V = 12.5 ± 0.3 V V = 6.25 ± 0.25 V
= 12.0 ± 0.5 V
PP CC
OE
Address = 0
n = 0
m = 0
SET PAGE PROG./VERIFY MODE
V = 12.5 ± 0.3 V V = 6.25 ± 0.25 V
PP CC
Address + 1 Address
NOGO
GO
YES
NOGO
NO NO
VERIFY
END FAIL
READ
all address
LAST
address?
SET READ MODE
V = 5.0 ± 0.5 V V = V
PPCC CC
GO
Program t = 50 s ± 5%
PW µ
YES
Address + 1 Address
n + 1 n
NO
YES
Latch
m=8?
m + 1 m
n = 10?
Fast High-Reliability Page Programming Flowchart
Page Program Reset
Set VPP to VCC level or less to reset a page
program mode.
Fast High-Reliability Page Programming
This device can be applied the fast high-reliablity page programming algorithm shown in the following
flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the
device nor deterioration in reliability of programmed data.
8
HN27C4001G Series
DC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Parameter Symbol Min Typ Max Unit Test conditions
———————————————————————————————————————————
Input leakage current ILI 2 µA Vin = 6.5 V/0.45 V
———————————————————————————————————————————
VPP supply current IPP 70 mA CE=VIL
———————————————————————————————————————————
Operating VCC current ICC 50 mA
———————————————————————————————————————————
Input voltage VIL –0.1*5 0.8 V
——————————————————————————————
VIH 2.2 VCC+0.5*6 V
——————————————————————————————
VH11.5 12.0 12.5 V
———————————————————————————————————————————
Output voltage during verify VOL 0.45 V IOL = 2.1 mA
——————————————————————————————
VOH 2.4 V IOH = –400 µA
———————————————————————————————————————————
Notes: 1. VCC must be applied before VPP and removed after VPP.
2. VPP must not exceed 13 V including overshoot.
3. An influence may be had upon device reliability if the device is installed or removed while
VPP = 12.5 V.
4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low.
5. VIL min = –0.6 V for pulse width <20 ns.
6. If VIH is over the specified maximum value, programming operation cannot be guaranteed.
9
HN27C4001G Series
Parameter Symbol Min Typ Max Unit Test conditions
———————————————————————————————————————————
Address setup time tAS 2——µs
———————————————————————————————————————————
OE setup time tOES 2——µs
———————————————————————————————————————————
Data setup time tDS 2——µs
———————————————————————————————————————————
Address hold time tAH 0——µs
———————————————————————————————————————————
Data hold time tDH 2——µs
———————————————————————————————————————————
OE high to output float delay tDF*10 130 ns
———————————————————————————————————————————
VPP setup time tVPS 2——µs
———————————————————————————————————————————
VCC setup time tVCS 2——µs
———————————————————————————————————————————
CE initial programming pulse width tPW 47.5 50.0 52.5 µs
———————————————————————————————————————————
CE setup time tCES 2——µs
———————————————————————————————————————————
Data valid from OE tOE 0 150 ns
———————————————————————————————————————————
CE pulse width during data latch tLW 1——µs
———————————————————————————————————————————
OE = VHsetup time tOHS 2——µs
———————————————————————————————————————————
OE = VHhold time tOHH 2——µs
———————————————————————————————————————————
VPP hold time*2tVRS 1——µs
———————————————————————————————————————————
Notes: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is
no longer driven.
2. Page program mode will be reset when VPP is set to VCC or less.
AC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta=25°C ± 5°C)
Test Conditions
Input pulse levels: 0.45 to 2.4 V
Input rise and fall times: < 20 ns Reference levels for measuring timing:
Inputs; 0.8 V, 2.0 V,
Outputs; 0.8 V, 2.0 V
10
HN27C4001G Series
Fast High-Reliability Page Programming Timing Waveform
Program data latch Page program Program verify
Data out valid
Data in
stable
Page program mode
ttt
t
tLW
VRS
OES
PW
CES
tOHH
tVCS
tVPS
tOHS
tDS
tDH tOE
tDF
tAS
tAH tAH
tAS
A3 – A18
A0 – A2
Data
V
V
CE
OE
V
V + 1.25
V
PP VPP
CC
CC
CC
CC
VIL
VH
VIH
017
0
017
17017
11
HN27C4001G Series
NOGO
START
Address = 0
n = 0
n + 1 n
SET PROG./VERIFY MODE
V = 12.5 ± 0.3 V V = 6.25 ± 0.25 V
PP CC
Address + 1 Address GO
YES
NOGO
NO NO
VERIFY
END FAIL
READ
all address
n = 10?
LAST
address?
SET READ MODE
V = 5.0 ± 0.5 V V = V
PPCC CC
GO
Program t = 50 s ± 5%
PW µ
YES
Fast High-Reliability Programming Flowchart
Fast High-Reliability Programming
This device can be applied the fast high-reliability
programming algorithm shown in the following
flowchart. This algorithm allows to obtain faster
programming time without any voltage stress to
the device nor deterioration in reliability of
programmed data.
12
HN27C4001G Series
DC Characteristics (VCC = 6.25 V ± 0.25 V, VPP =12.5 V ± 0.3 V, Ta=25°C ± 5°C)
Parameter Symbol Min Typ Max Unit Test conditions
———————————————————————————————————————————
Input leakage current ILI 2 µA Vin = 6.5 V/0.45 V
———————————————————————————————————————————
VPP supply current IPP 40 mA CE = VIL
———————————————————————————————————————————
Operating VCC current ICC 50 mA
———————————————————————————————————————————
Input voltage VIL –0.1*5 0.8 V
—————————————————————————————————
VIH 2.2 VCC +0.5*6V
———————————————————————————————————————————
Output voltage VOL 0.45 V IOL = 2.1 mA
—————————————————————————————————
VOH 2.4 V IOH = –400 µA
———————————————————————————————————————————
Notes: 1. VCC must be applied before VPP and removed after VPP.
2. VPP must not exceed 13 V including overshoot.
3. An influence may be had upon device reliability if the device is installed or removed while
VPP = 12.5 V.
4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low.
5. VIL min = –0.6 V for pulse width <20 ns.
6. If VIH is over the specified maximum value, programming operation cannot be guaranteed.
AC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Test Conditions
• Input pulse levels: 0.45 to 2.4 V
• Input rise and fall times: < 20 ns • Reference levels for measuring timings:
0.8 V, 2.0 V
Parameter Symbol Min Typ Max Unit Test conditions
———————————————————————————————————————————
Address setup time tAS 2—µs
———————————————————————————————————————————
OE setup time tOES 2—µs
———————————————————————————————————————————
Data setup time tDS 2—µs
———————————————————————————————————————————
Address hold time tAH 0—µs
———————————————————————————————————————————
Data hold time tDH 2—µs
———————————————————————————————————————————
OE to output float delay tDF*10 130 ns
———————————————————————————————————————————
VPP setup time tVPS 2—µs
———————————————————————————————————————————
VCC setup time tVCS 2—µs
———————————————————————————————————————————
CE initial programming pulse width tPW 47.5 50.0 52.5 µs
———————————————————————————————————————————
Data valid from OE tOE 0 150 ns
———————————————————————————————————————————
Note: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no
longer driven.
13
HN27C4001G Series
Fast High-Reliability Programming Timing Waveform
Optional Page Programming
Program Program Verify
Address
Data Data In Stable Data Out Valid
tAS
tDS
tVPS
tVCS
tDH tDF
tAH
tPW tOES tOE
VPP VCC
VPP
VCC VCC
V +1.25
CC
CE
tDS
OE
This device can be applied the optional page
programming algorithm shown in the following
flowchart. This algorithm allows to obtain faster
programming time without any voltage stress to
the device nor deterioration in reliability of
programmed data.
This programming algorithm is the combination of
page programming and byte verify. It can avoid the
increase of programming verify time when a
programmer with slow machine cycle is used, and
shorten the total programming time.
Regarding the timing specifications for page
programming and byte verify, please refer to the
specifications for fast high-reliability page
programming and fast high-reliability
programming.
START
SET PAGE PROG. LATCH MODE
V = 12.5 ± 0.3 V V = 6.25 ± 0.25 V
= 12.0 ± 0.5 V
PP CC
OE
Address = 0
n + 1 n
SET PAGE PROG. MODE
V = 12.5 ± 0.3 V V = 6.25 ± 0.25 V
PP CC
Address + 1 Address
NOGO
GO
YES
NOGO
NO
NO
VERIFY
END FAIL
READ
all address
n = 10?
LAST
address?
SET READ MODE
V = 5.0 ± 0.5 V V = V
PPCC CC
GO
Program t = 50 s ± 5%
PW µ
SET WORD PROG./VERIFY MODE
V = 12.5 ± 0.3 V V = 6.25 ± 0.25 V
PP CC
PAGE PROG. RESET
V = V = 6.25 ± 0.25 V
PP CC
Address = 0
n = 0
Address + 1 Address Program t = 50 s ± 5%
PW µ
VERIFY
YES
LAST
address?
GO
NOGO
YES
YES
NO
m=0
Latch
Address + 1 Address
m=1¤ m
m=8
NO
Optional Page Programming Flowchart
14
HN27C4001G Series
DC Characteristics (VCC = 6.25 V ± 0.25 V, VPP =12.5 V ± 0.3 V, Ta=25°C ± 5°C)
Parameter Symbol Min Typ Max Unit Test conditions
———————————————————————————————————————————
Input leakage current ILI 2 µA Vin = 6.5 V/0.45 V
———————————————————————————————————————————
Output voltage during VOL 0.45 V IOL = 2.1 mA
verify —————————————————————————————————
VOH 2.4 V IOH = –400 µA
———————————————————————————————————————————
Operating VCC current ICC 50 mA
———————————————————————————————————————————
Input voltage VIL –0.1*5 0.8 V
—————————————————————————————————
VIH 2.2 VCC +0.5*6V
—————————————————————————————————
VH11.5 12.0 12.5 V
———————————————————————————————————————————
VPP supply current IPP 70 mA CE = VIL
———————————————————————————————————————————
Notes: 1. VCC must be applied before VPP and removed after VPP.
2. VPP must not exceed 13 V including overshoot.
3. An influence may be had upon device reliability if the device is installed or removed
while VPP = 12.5 V.
4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low.
5. VIL min = –0.6 V for pulse width <20 ns.
6. If VIH is over the specified maximum value, programming operation cannot be guaranteed.
15
HN27C4001G Series
AC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Test Conditions
Parameter Symbol Min Typ Max Unit Test conditions
———————————————————————————————————————————
Address setup time tAS 2—µs
———————————————————————————————————————————
OE setup time tOES 2—µs
———————————————————————————————————————————
Data setup time tDS 2—µs
———————————————————————————————————————————
Address hold time tAH 0—µs
———————————————————————————————————————————
Data hold time tDH 2—µs
———————————————————————————————————————————
OE high to output float delay tDF*10 130 ns
———————————————————————————————————————————
VPP setup time tVPS 2—µs
———————————————————————————————————————————
VCC setup time tVCS 2—µs
———————————————————————————————————————————
CE initial programming pulse width tPW 47.5 50.0 52.5 µs
———————————————————————————————————————————
CE setup time tCES 2—µs
———————————————————————————————————————————
Data valid from OE tOE 0 150 ns
———————————————————————————————————————————
CE pulse width during data latch tLW 1—µs
———————————————————————————————————————————
OE = VHsetup time tOHS 2—µs
———————————————————————————————————————————
OE = VHhold time tOHH 2—µs
———————————————————————————————————————————
Page programming reset time *2 tVLW 1—µs
———————————————————————————————————————————
VPP hold time *2 tVRS 1—µs
———————————————————————————————————————————
Notes: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no
longer driven.
2. Page program mode will be reset when VPP is set to VCC or less.
• Input pulse levels: 0.45 to 2.4 V
• Input rise and fall times: < 20 ns
• Reference levels for measuring timings: 0.8 V, 2.0 V
16
HN27C4001G Series
17
HN27C4001G Series
Program data latch Page program Program verify
Page program mode
t
t
tLW OES
PW
tOHH
tVCS
tVPS
tDS tDH
tOE
tDS
tAS
tAH tAH
tAS
A3 – A18
A0, A2
Data
V
V
CE
OE
V
V + 1.25
V
PP VPP
CC
CC
CC
CC
VIL
VH
VIH
tAH
Word program mode
Program
tDF
tVPS tDF
tVRS
tVLW
tCES tCES
tPW
tOHS
Data in
stable
Data
out
valid Data in stable
0
01 7
17
Optional Page Programming Timing Waveform
18
HN27C4001G Series
HN27C4001G Identifier Code
A0 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
———————————————————————————————Hex
Identifier (12) (21) (20) (19) (18) (17) (15) (14) (13) Data
———————————————————————————————————————————
Manufacturer code VIL 00000111 07
———————————————————————————————————————————
Device code VIH 00100000 20
———————————————————————————————————————————
Notes: 1. VCC = 5.0 V ± 10%
2. A9 = 12.0 V ± 0.5 V
3. CE, OE=VIL
4. A1 – A8, A10 – A18: Don’t care.
Erase
Erasure of HN27C4001G is performed by exposure
to ultraviolet light of 2537 Å and all the output data
are changed to “1” after this erasure procedure. The
minimum integrated dose (i.e. UV intensity X
exposure time) for erasure is 15 W•sec/cm2.
Mode Description
Device Identifier Mode
The device identifier mode allows the reading out
of binary codes that manufacturer and type of
device, from outputs of EPROM. By this mode,
the device will be automatically matched its own
corresponding programming algorithm, using
programming equipment.
Package Dimensions
HN27C4001G Series (DG-32A) Unit: mm
0.38 Min
2.54 Min
0.48 ± 0.10
2.54 ± 0.25
1.32
41.91
14.66
0.25
0 – 15°
+ 0.11
– 0.05
15.24
32 17
116
5.89 Max
43.18 Max
15.51 Max
17.00
7.00
19
HN27C4001G Series