Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
General Description
The evaluation kit (EV kit) demonstrates the MAX1121X
family of 24-bit, 64ksps delta-sigma ADCs with integrated
PGA. The EV kit includes a graphical user interface (GUI)
that provides communication from the target device to the
PC. The EV kit can operate in multiple modes:
1) Standalone Mode: In “Standalone” mode, the EV
kit is connected to the PC through a USB cable and
performs a subset of the complete EV kit functions
with limitation for sample rate and size.
2) FPGA Mode: In “FPGA” mode, the EV kit is con-
nected to an Avnet ZedBoard™ through a low-pin-
count FMC connector. ZedBoard features a Xilinx®
Zynq®-7000 SoC that connects to the PC through an
Ethernet port, which allows the GUI to perform differ-
ent operations with full control over mezzanine card
functions. The EV kit with FPGA platform performs
the complete suite of evaluation tests for the target IC
3) User-Supplied SPI Mode: In addition to the USB
and FMC interfaces, the EV kit provides two 12-pin
PMOD-style headers for user-supplied SPI interface,
to connect the signals for RDYB, SCLK, DIN, DOUT,
and CSB.
The EV kit includes Windows XP®-, Windows® 7 and
Windows 8.1-compatible software to exercise the features
of the IC. The EV kit GUI allows different sample sizes,
adjustable sampling rates, on-board or external reference
options, and graphing software that includes the FFT and
histogram of the sampled signals with the ability to save
plots in .jpg or .csv formats.
The ZedBoard board accepts a +12V AC-DC wall adapter.
The EV kit can be powered by the ZedBoard or by a local
12V supply. The EV kit has on-board transformers and
digital isolators to separate the IC from the ZedBoard/
on-board processor.
The MAX11214 EV kit comes installed with a
MAX11214EUG+ in a 24-pin TSSOP package and the
MAX11216 EV kit comes installed with a MAX11216EUG+
in a 24-pin TSSOP package.
Features and Benets
●High-Speed USB, FMC Connector, and PMOD
Connector
●5MHz SPI Interface
●Various Sample Sizes and Sample Rates
●Collects Up to 1 Million Samples (with FPGA Platform)
●Time Domain, Frequency Domain, and Histogram
Plotting
●Save Plots as jpg, bmp or csv
●Sync In and Sync Out for Coherent Sampling
(with FPGA Platform)
●On-Board DAC (MAX542) for DC Signal-Level
Generation
●On-Board Voltage Reference (MAX6126)
●Proven PCB Layout
●Fully Assembled and Tested
●Windows XP-, Windows 7-, and Windows
8.1-Compatible Software
●Savable ADC Configurations
Ordering Information appears at end of data sheet.
ZedBoard is a trademark of Avnet, Inc.
Xilinx and Zynq are registered trademarks and Xilinx is a regis-
tered service mark of Xilinx, Inc.
Windows and Windows XP are registered trademarks and reg-
istered service marks of Microsoft Corporation.
19-7605; Rev 0; 4/15
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
-
+
MAX44241
-
+
MAX44241
MAX11214/216
ADC
U25
-
+
MAX44241
-
+
MAX44241
CH_A
CH_B
CH_C
CH_D
SCLK_ADC
CS_ADC
DIN_ADC
DOUT_ADC
I
S
O
L
A
T
I
O
N
MAX542
DAC
U15
CS_DAC
DIN_DAC
LDAC
F
M
C
H
E
A
D
E
R
U
S
B
FTDI
FPGA -
ZedBoard
User-Supplied
SPI
PC - USB
SYNC IN,
SYNC OUT
ISOLATED
DC-DC
MAX6126
MAX6126
EXT_REFP
ADC_REFP
ADC_REFN
IN+
EXT_REFN
ADC_REFP
DAC_OUT+
ADC_INP
ADC_INN
ADC_REFN
DAC_OUT-
IN-
SCLK_DAC
-
+
MAX9632
DAC_OUT+
DAC_OUT-
MAX9632 x2
RDYB_ADC
MAX1121X EV Kit Photo
System Block Diagram
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Quick Start
Required Equipment
●MAX1121X EV kit
●+12V (500mA) power supply
●Micro-USB cable
●ZedBoard development board (optional – Not Included
with EV kit)
●Function generator (optional)
●Windows XP, Windows 7, or Windows 8.1 PC with a
spare USB port
Note: In the following sections, software-related items are
identified by bolding. Text in bold refers to items directly
from the EV system software. Text in bold and underline
refers to items from the Windows operating system.
Procedure
The EV kit is fully assembled and tested. Follow the steps
below to verify board operation:
1) Visit www.maximintegrated.com/evkitsoftware to
download the latest version of the EV kit software,
MAX11214_16EVK.ZIP. Save the EV kit software to a
temporary folder and uncompress the ZIP file.
2) Install the EV kit software and USB driver on your comput-
er by running the MAX11214_16EVKitSetupV1.1.exe
program inside the temporary folder. The program
files are copied to your PC and icons are created in
the Windows Start | Programs menu. At the end of
the installation process, the installer will launch the
installer for the FTDIChip CDM drivers.
For Standalone mode:
3) Verify that all jumpers are in their default positions for
the EV kit (Table 2).
4) Connect the PC to the EV kit using a micro-USB
cable.
5) Connect the +12V adapter to the EV kit.
6) Start the EV kit software by opening its icon in the
Start | Programs menu. The EV kit software appears
as shown in Figure 1. Verify that the lower left status
bar indicates the EV kit hardware is Connected.
7) From the Device menu, select Standalone and click
Search for USB Device. Then select Standalone
again and select a device in the list. Verify that the
lower left status bar indicates the EV kit hardware is
Connected.
For FPGA mode (when connected to a ZedBoard):
8) Connect the Ethernet cable from the PC to the
ZedBoard and configure the Internet Protocol Version
4 (TCP/Ipv4) properties in the local area connec-
tion to IP address 192.168.1.2 and subnet Mask to
255.255.255.0.
9) Verify that the ZedBoard SD card contains the
boot.bin file for the MAX1121X EV kit.
10) Connect the EV kit FMC connector to the ZedBoard
FMC connector. Gently press them together.
11) Verify that all jumpers are in their default positions for
the ZedBoard (Table 1) and EV kit (Table 2).
12) Connect the 12V wall adapter power supply to the
ZedBoard. Leave the ZedBoard powered off. Connect
the PC to the ZedBoard with an Ethernet cable.
13) Enable the power supply by sliding SW8 to ON.
14) Start the EV kit software by opening its icon in the
Start | Programs menu. The EV kit software appears
as shown in Figure 1. From the Device menu, select
FPGA. Verify that the lower left status bar indicates
the EV kit hardware is Connected.
For either Standalone or FPGA mode:
15) Connect the positive terminal of the function generator
to the IN+ test point on the EV kit. Connect the nega-
tive terminal of the function generator to the IN- test
point on the EV kit. Disable the function generator.
16) Enable the function generator. Configure the signal
source to generate a 1kHz, 1VP-P sinusoidal wave
with +500mV offset.
17) In the Calibration group, select Self Offset/Gain in
the drop-down list and then click Calibrate.
18) Click on the Scope tab.
19) Check the Remove DC checkbox to remove the DC
component of the sampled data.
20) Click the Capture button to read sampled data from
the ADC.
21) The EV kit software appears as shown in Figure 4.
22) Verify the frequency is approximately 1kHz displayed
on the right. The scope graph has buttons in the
upper-right corner that allow zooming in to detail.
FILE DECRIPTION
MAX11214_16EVKitSetupV1.1.exe Application Program
(GUI)
Boot.bin ZedBoard Firmware
(SD Card to boot Zynq)
MAX1121X EV Kit Files
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Table 1. ZedBoard Jumper Settings (Optional)
Table 2. MAX1121X EV Kit User Configuration Jumper Settings*
JUMPER SHUNT
POSITION DESCRIPTION
J2 (Red) 1-2 Connects the +10V rail to test point +10VEXT for external power (op amp + supply)
2-3* Connects the +10V rail to LDO U2 (op amp + supply)
J3 (Red) 1-2 Connects the +15V rail to test point +15EXT for external power (powers U2)
2-3* Connects the +15V rail to isolation transformer (powers U2)
J4 (Red) 1-2 Set ADC DVDD to +3.3V
2-3* Set ADC DVDD to +2.0V
J5 (Red) 1-2* Connect ADC AVSS to GND (unipolar mode – also set J8 for unipolar)
2-3 Connect ADC AVSS to -1.8V (bipolar mode – also set J8 for bipolar)
J6 (Black)
1-2 Apply an offset of ADC_REFP (2.5V default) to amplier U24
2-3 Apply an offset of 2.5V to amplier U24
Open* No offset for amplier U24
J7 (Black)
1-2 Apply an offset of ADC_REFP (2.5V default) to amplier U27
2-3 Apply an offset of 2.5V to amplier U27
Open* No offset for amplier U27
J8 (Red) 1-2 Connect ADC AVDD to +1.8V (bipolar mode)
2-3* Connect ADC AVDD to 3.6V (unipolar mode)
J15 (Red) 1-2* Connects ZedBoard +12V to main power supply (U3). Diode D2 protects supplies.
Open Disconnects ZedBoard +12V from main power supply
J17 (Red)
1-2 Connects U5 input to GND
3-4 Connects U5 input to test point -15VEXT for external power
5-6* Connects U5 input to isolation transformer
J18 (Red)
1-2 Do not connect
3-4 Do not connect
5-6 Connects U5 output to GND, which sets the reference for the -10V supply (op amp - supply)
J20 (Red) 1-2* Connects on-board FTDI chip to 3.3V, necessary for standalone mode
Open Disconnects on-board FTDI chip power. This jumper does not interfere with the ZedBoard.
J21 (Black) 1-2* Drive ADC REFP pin with on-board voltage reference
2-3 Drive ADC REFP pin with external voltage reference
JUMPER SHUNT
POSITION DESCRIPTION
J18 1-2 VDDIO set for 3.3V
JP11 2-3
Boot from SD card
JP10 1-2
JP9 1-2
JP8 2-3
JP7 2-3
JP10 —
J12 — SD card installed
J20 — Connected to 12V wall adapter
SW8 Off ZedBoard power switch, off while connecting boards
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
*Red test points and red jumpers are used for power settings.
Black test points are used for ground points.
White test points are used for all signal points, black jumpers for signal settings.
JUMPER SHUNT
POSITION DESCRIPTION
J22 (Black) 1-2 Ground test point CH_D-
3-4 Ground test point CH_D+
J23 (Black) 1-2* Drive ADC REFN pin with on-board voltage reference
2-3 Drive ADC REFN pin with external voltage reference
J24 (Black) 1-2 Ground test point CH_C-
3-4 Ground test point CH_C+
J25 (Black)
1-2* Connect output of U23 (CH_C) to U24 inverting input
3-4 Connect CH_D- to U24 inverting input
5-6 Connect output of U23 (CH_C) to U24 noninverting input
7-8 Connect CH_D+ to U24 noninverting input
J26, J27
(Black)
1-2* Set both jumpers to align with silkscreen text “EXT” to drive ADC_INP and ADC_INN with
test points IN+ and IN- (also external connector J10 is on same net)
3-4 Set both jumpers to align with silkscreen text “AMP” to drive ADC_INP and ADC_INN with U27 and
U24 ampliers
5-6 Set both jumpers to align with silkscreen text “DAC” to drive ADC_INP and ADC_INN with DAC_
OUT+ and DAC_OUT-
7-8 Set both jumpers to align with silkscreen text “REF” to drive ADC_INP and ADC_INN with ADC_
REFP and ADC_REFN voltage reference
9-10 ADC_INP to ADC_REF/2, ADC_INN to GND
J28 (Black) 1-2 Ground test point CH_A-
3-4 Ground test point CH_A+
J29 (Black)
1-2* Connect output of U26 (CH_A) to U27 inverting input
3-4 Connect CH_B- to U27 inverting input
5-6 Connect output of U26 (CH_A) to U27 noninverting input
7-8 Connect CH_B+ to U27 noninverting input
J30 (Black) 1-2 Ground test point CH_B-
3-4 Ground test point CH_B+
J36 (Black) 1-2 Drive ADC CLK pin with signal from SMA connector J34
2-3* Drive ADC CLK pin with signal from on-board oscillator U20
J37 (Red) 1-2* Connect ADC to the DVDD voltage selection jumper J4
open Attach amp meter between pins 1-2 to measure current consumed by ADC DVDD
J40 (Black) 1-2* Connect ADC RST to DVDD (normal operation)
2-3 Connect ADC RST to GND (reset state)
J44 (Black) 1-2* Sets U18 noninverting input to 0V. Gain = -1 with offset = 0. Drives DAC_OUT-.
2-3 Sets U18 noninverting input to 2.5V. Gain = -1 with offset = 2.5V. Drives DAC_OUT-.
J45 (Black) 1-2* Sets U17 noninverting input to 0V. Gain = -1 with offset = 0. Drives DAC_OUT+.
2-3 Sets U17 noninverting input to 2.5V. Gain = -1 with offset = 2.5V. Drives DAC_OUT+.
J46 (Red) 1-2* Enables main power supply (U3)
Open Disables main power supply (U3)
Table 2. MAX1121X EV Kit User Configuration Jumper Settings* (continued)
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
General Description of Software
The main window of the EV kit software contains sev-
eral tabs: ADC Config, DAC Config, Function Generator,
Scope, DMM, Histogram, FFT, and ADC Registers. The
ADC Config tab and ADC Registers tab provide control
to communicate with the MAX1121X registers. The DAC
Config tab and Function Generator tab provide control to
communicate with the MAX542. The other four tabs are
used for evaluating the sample data read from the ADC.
ADC Cong Tab
The ADC Config tab provides an interface for configur-
ing the IC from a functional perspective. The main block
provides for calibration, GPIO control, input path selec-
tion, data format, filtering, power, and clocking. To read
all the configuration settings, click the Read All button in
the Serial Interface block. When a setting is changed,
the register associated with that setting is automatically
written. The Status Log at the bottom of the GUI shows
the value and register that was changed.
The primary mode for calibration is using the drop-down
list to select a calibration mode, followed by clicking the
Calibrate button. The checkboxes for Self Offset, Self
Gain, System Offset, and System Gain allow for the
user to enable or disable the calibration values. The cali-
bration values can also be changed manually by entering
a hex value in the SPI numeric box.
The Power block allows the user to put the part in a
power-down or standby state by selecting one of these
options in the drop-down list. The configuration set-
tings can be reset back to default by clicking the Reset
Table 3. MAX1121X EV Kit User Off-Board Connectors
CONNECTOR
REFERENCE
DESIGNATOR
DESCRIPTION
J1 USB connector for standalone mode
J9 External reference input for EXT_REFP and EXT_REFN
J10 External input for ADC IN+ and IN-
J12, J16 External power connections, 12V. Both wall adapter and screw terminals are provided. When ZedBoard is
used, these connectors are not necessary if jumper J15 is installed.
J13 External connections for AVDD and AVSS
J14 External enable, driven by GPIO1 via FET
J19 Serial EEPROM signal
J31 Sync clock input, SMA
J32 PMOD A, connects to ADC, 12-pin connector
J33 PMOD B, connects to DAC, 12-pin connector
J34 External clock input, SMA
J35 DAC SPI port signal
J38, J41 Sync clock out, SMA
J39 ADC SPI port signal
J42 Split sync clock in, SMA
J43 FMC connector for use with ZedBoard
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MAX1121X Family Evaluation Kit
Registers button. For the Clock source selection, the IC
internal clock is always a valid option. If the external clock
is selected, a clock must be applied at the IC CLK pin by
setting jumper J36 to either SMA or OSC. Once the above
configurations are completed, start conversion by clicking
Convert in the Serial Interface block. To read the data
and status, click Read Data and Status on the lower right
of the GUI.
To save a configuration, select Save ADC Config As…
in the File menu. This saves all the ADC register values
to an XML file. To load a configuration, select Load ADC
Config in the File menu. When the XML file is loaded, all
the register values in the file are written to the ADC.
Figure 1. MAX1121X EV Kit Software (ADC Config Tab)
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
DAC Cong Tab
In standalone mode, the ADC and DAC cannot oper-
ate concurrently. It is recommended to use FPGA
mode when using the DAC for function generation.
The DAC Config tab sheet provides an interface for
configuring the MAX542 to drive the DAC_OUT+ and
DAC_OUT- pins. Set J45 Offset and J44 Offset to match
the jumper positions on the EV Kit. These jumper posi-
tions apply DC offset to DAC_OUT+ and DAC_OUT-,
see the DAC amplifier section for more details. To write a
value to the DAC, select the output of interest in the drop-
down list, enter a value in the numeric box and then click
DAC Single Shot. The outputs on the right display the
voltage outputs and the decimal code written to the DAC.
The voltage outputs are calculated based on the DAC
code and jumper offsets.
The Calibration section of the DAC Config tab can be
used to calibrate the calculated voltages to be closer to
the measured voltages. Select which output to calibrate
with the radio buttons. Enter the maximum and minimum
voltage for this output in the Ideal (V) numeric boxes. Find
the measured voltages of the output for the maximum
and minimum values using the DAC Single Shot to set
the DAC output to the ideal voltages. Enter the measured
voltages in the Measured (V) numeric boxes and click
Calculate to find the new offset and gain. Check the
Enable Calibration to use these values to calculate the
voltage outputs.
Figure 2. MAX1121X EV Kit Software (DAC Config Tab)
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Function Generator
When using the FPGA mode, the Function Generator
tab allows the user to generate a signal with the DAC.
Select the Number of Samples, DAC Update Rate, and
Signal Frequency. Click Calculate to get the Adjust
Frequency for the DAC signal needed for coherent sam-
pling. Then select the Signal Type, Amplitude, Phase, and
Offset to set up the waveform desired for the DAC. Click
Generate to find the DAC codes for the waveform and
generate the waveform on the DAC. The waveform codes
sent to the DAC is displayed on the graph. The Average,
RMS, Maximum, Minimum, and Peak to Peak are also
calculated and displayed on the right. To save the DAC
code waveform, go to Options > Save Graph > Function
Generator. This saves the settings on the left and the
data in the graph to a csv file.
Figure 3. MAX1121X EV Kit Software (Function Generator Tab)
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Scope Tab
The Scope tab sheet is used to capture data and dis-
play it in the time domain. Sample Rate and Number
of Samples can also be set in this tab if they were not
appropriately adjusted in other tabs. The Display Unit
drop-down list allows counts and voltages. Once the
desired configuration is set, click on the Capture button.
The right side of the tab sheet displays details of the wave-
form, such as Average, Standard Deviation, Maximum,
Minimum, and Fundamental Frequency. Figure 4 displays
the ADC data when a sinusoidal signal is applied at the
inputs on the EV kit.
To save the captured data to a file, go to Options > Save
Graph > Scope. This saves the setting on the left and the
data captured to a csv file.
Figure 4. MAX1121X EV Kit Software (Scope Tab)
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
DMM Tab
The DMM tab sheet provides captured data as a digital
multimeter. Once the desired configuration is set, click on
the Capture button. Figure 5 displays the results shown
by the DMM tab when ADC_INP and ADC_INN (J26 and
J27 set as 7-8) are set to REF, see Table 2 for jumper
positions.
Figure 5. MAX1121X EV Kit Software (DMM Tab)
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Histogram Tab
The Histogram tab sheet is used to display a histogram of
the captured data. Sampling rate and number of samples
can also be set in this tab if they were not appropriately
adjusted in other tabs. Once the desired configuration is
set, click on the Capture button. The right side of the tab
sheet displays details of the histogram such as Average,
Standard Deviation, Maximum, Minimum, Peak-to-Peak
Noise, Effective Resolution, and Noise-Free Resolution.
To use this histogram feature, apply a DC voltage at the
input. Figure 5 displays the results shown by the DMM tab
when ADC_INP and ADC_INN are set to REF, see Table
2 for jumper positions.
To save the histogram data to a file, go to Options > Save
Graph > Histogram. This saves the setting on the left
and the histogram data captured to a csv file.
Figure 6. MAX1121X EV Kit Software (Histogram Tab)
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
FFT Tab
The FFT tab sheet is used to display the frequency domain
FFT of the captured data. Sample Rate and Number of
Samples can also be set in this tab if they were not appro-
priately adjusted in other tabs. Once the desired configura-
tion is set, click on the Capture button. The right side of
the tab displays the performance based on the FFT, such
as Fundamental Frequency, THD, SNR, SINAD, SFDR,
ENOB, and Noise Floor.
To save the FFT data to a file, go to Options > Save
Graph > FFT. This saves the setting on the left and the
FFT data captured to a csv file.
Figure 7. MAX1121X EV Kit Software (FFT Tab)
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
ADC Registers Tab
The ADC Registers tab sheet shows the ADC registers
on the left. The middle section shows the bits and bit
descriptions of the selected register. Click Read All to
read all registers and refresh the window with the register
settings. To write a register first, select the hex value in
the Value (Hex) column, type the desired hex value and
press Enter.
The Command Byte is on the right side of the tab sheet.
This byte precedes all SPI transactions and is described
in the ADC data sheet. To send a command byte, enter a
hex value in the Numeric box and click the Send button.
The command byte has two different formats including
Conversion Mode and Register Access Mode. Select the
radio button for the desired mode to see the bit descrip-
tion in the table.
Figure 8. MAX1121X EV Kit Software (ADC Registers Tab)
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MAX1121X Family Evaluation Kit
Detailed Description of Hardware
This EV kit provides a proven layout to demonstrate the
performance of the MAX1121X 24-bit delta-sigma ADC.
Included in the EV kit are digital isolators (MAX14934),
ultra-low-noise LDOs (MAX8842) to all supply pins of
the IC, an on-board reference (MAX6126), a precision
amplifier (MAX44241) for the analog inputs, 16-bit DAC
(MAX542) with precision amplifiers (MAX9632), and sync-
in and sync-out signals for coherent sampling.
An on-board controller is provided to allow for evaluation
in standalone mode, which has limitations on maximum
sample size and it cannot perform coherent sampling.
The EV kit can be used with FPGA mode to achieve larger
sample depth and coherent sampling.
The ADC has several input options which are selected by
J26 and J27. The external option allows for wires attached
to the screw terminals at J10. The amplifier option allows
for signals at testpoints CH_A to CH_D. The DAC option
allows for inputs to be driven from an on-board DAC. The
REF options connect the inputs to the voltage reference
of the ADC.
User-Supplied SPI
To evaluate the ADC on this EV kit with a user-supplied
SPI bus, disconnect from the FMC bus and remove
jumper J20. Apply the user-supplied SPI signals to SCLK,
CSB, DIN, and DOUT at the PMOD_A header (J32).
Make sure the return ground is connected to PMOD
ground. To communicate to the on-board DAC connect
the user-supplied SPI signals to CSB, SCLK, DIN, and
LDAC at the PMOD_B header (J33). Make sure the return
ground is connected to PMOD ground.
The on-board FTDI chip used for standalone mode does
not conflict with the user-supplied SPI if it is powered off
by removing jumper J20.
Caution: Do not plug this header into a standard PMOD
interface found on other FPGA or microcontroller prod-
ucts. The signal definition is unique to this EV kit.
User-Supplied Reference
For user-supplied reference voltage, set jumpers at J21
and J23 to positions 2-3 and apply external reference to
either J9 or to the EXT_REFN and EXT_REFP testpoints.
User-Supplied AVSS
The AVSS supply is set to GND or -1.8V by Jumper J5.
For user-supplied AVSS, remove the jumper from J5 and
apply AVSS to the screw-terminals/testpoint at J13. Make
sure that this external supply has the correct relation to
system ground.
User-Supplied AVDD
The AVDD supply is set to 3.6V or 1.8V by jumper J8.
For user-supplied AVDD, remove the jumper from J8 and
apply AVDD to the screw-terminals/testpoint at J13. Make
sure that this external supply has the correct relation to
system ground.
Bipolar Powered vs. Unipolar Powered
The ADC supports both unipolar and bipolar ranges. For
unipolar mode, jumper J8 pins 2-3 to power AVDD with
3.6V and jumper J5 pins 1-2 to set AVSS to GND. For
bipolar mode, jumper J8 pins 1-2 to power AVDD with
1.8V and jumper J5 pins 2-3 to set AVSS to -1.8V.
External Clock
When the ADC is configured to use an external clock,
Jumper J36 pins 2-3 to select the on-board oscillator as
the clock source. Jumper J36 pins 1-2 to select the SMA
connector (and user-provided clock) as the clock source.
GPIO
Testpoints are provided for the three GPIO signals from
the ADC, GPIO1, GPIO2, and GPIO3. The ADC Config
tab can configure these as input/output and read/drive the
GPIO pins. GPIO1 connects to a FET which allows J14.1
and TP2 to be connected to ground by driving GPIO1 high
(note that DVDD should be to 3.3V to drive the FET).
ADC Input Ampliers
The input amplifiers allow for significant flexibility. The
amplifier input stage begins with testpoints labeled CH_A
to CH_D. Each set of testpoints has options to ground
either the inverting or noninverting inputs. The jumper
block J29 and J25 allow for bypassing the first stage of
amplifiers, or connecting the first stage to the second
stage. Jumper J7 can provide an offset of 2.5V to the
CH_A/CH_B signals – leave unpopulated to have an
offset of 0V. Similarly, jumper J6 can provide an offset of
2.5V to the CH_C/CH_D signals – leave unpopulated to
have an offset of 0V.
DAC and DAC Ampliers
In Figure 2, the GUI shows a functional diagram of the
DAC and DAC amplifiers. Here jumper J45 can be con-
nected to 2.5V to add a 2.5V offset to the DAC_OUT+
signal, and J44 can be connected to 2.5V to add 2.5V to
the DAC_OUT- signal.
The value at DAC_OUT+ and DAC_OUT- are available to
drive to the ADC by use of jumpers J26 and J27.
Also, please note that the DAC_OUT+ and DAC_OUT-
values shown by the GUI are only valid if the settings at
J44 and J45 are the same on both the PCB and the GUI.
Maxim Integrated
│
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Figure 9. Analog Front-End
MAX11214/MAX11216
Sigma-Delta ADC
-
+
MAX44241 ADC_INP
+2.5V
J29
J27
1
3
5
7
12
34
56
78
MAX44241
CH_A-
CH_A+
CH_B-
CH_B+
-
+
J28
12
34
J30
12
34
MAX44241 2
4
6
8
910
ADC_REFP
J7
IN+
DAC_OUT+
ADC_REFP
-
+
MAX44241 ADC_INN
+2.5V
J25
J26
1
3
5
7
12
34
56
78
MAX44241
CH_C-
CH_C+
CH_D-
CH_D+
-
+
J24
12
34
J22
12
34
MAX44241 2
4
6
8
910
ADC_REFP
J6
IN-
DAC_OUT-
ADC_REFN
ADC_REF/2
Maxim Integrated
│
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Table 4. Analog Input Configurations (Ch A - D)
CONFIGURATION SIGNAL-PATH INPUT
CONFIGURATION INPUT CONNECTORS JUMPER POSITIONS
No. DESCRIPTION
1 Channel A and C
Noninverting, differential,
second-order LPF
(default)
CH_A- and CH_C-
J28: 3-4
J30: 3-4
J24: 3-4
J22: 3-4
J29: 1-2 and 7-8
J25: 1-2 and 7-8
J26: 3-4
J27: 3-4
J7: 1-2 (for bipolar signal) or
Open for unipolar signal
J8: 1-2 (for bipolar signal) or
Open for unipolar signal
2 Channel A and C Inverting, differential,
second-order LPF CH_A+ and CH_C+
J28: 1-2
J30: 3-4
J24: 1-2
J22: 3-4
J29: 1-2 and 7-8
J25: 1-2 and 7-8
J26: 3-4
J27: 3-4
J7: 1-2 (for bipolar signal) or
Open for unipolar signal
J8: 1-2 (for bipolar signal) or
OPEN for unipolar signal
3 Channel B and D Noninverting, differential,
rst-order LPF CH_B+ and CH_D+
J28: 1-2 and 3-4
J30: 1-2
J24: 1-2 and 3-4
J22: 1-2
J29: 3-4 and 7-8
J25: 3-4 and 7-8
J26: 3-4
J27: 3-4
J7: 1-2 (for bipolar signal) or
Open for unipolar signal
J8: 1-2 (for bipolar signal) or
Open for unipolar signal
4 Channel B and D Inverting, differential, rst-
order LPF CH_B- and CH_D-
J28: 1-2 and 3-4
J30: 3-4
J24: 1-2 and 3-4
J22: 3-4
J29: 3-4 and 7-8
J25: 3-4 and 7-8
J26: 3-4
J27: 3-4
J7: 1-2 (for bipolar signal) or
Open for unipolar signal
J8: 1-2 (for bipolar signal) or
Open for unipolar signal
Maxim Integrated
│
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Table 4. Analog Input Configurations (Ch A - D) (continued)
CONFIGURATION SIGNAL-PATH INPUT
CONFIGURATION INPUT CONNECTORS JUMPER POSITIONS
No. DESCRIPTION
5 External Inputs User-supplied signals IN+ and IN-
J28: 1-2 and 3-4
J30: 1-2 and 3-4
J24: 1-2 and 3-4
J22: 1-2 and 3-4
J29: 3-4 and 7-8
J25: 3-4 and 7-8
J26: 1-2
J27: 1-2
J7: Open
J8: Open
6 DAC Output DAC output buffered with
MAX9632
DAC_OUT+ and DAC_
OUT-
J28: 1-2 and 3-4
J30: 1-2 and 3-4
J24: 1-2 and 3-4
J22: 1-2 and 3-4
J29: 3-4 and 7-8
J25: 3-4 and 7-8
J26: 5-6
J27: 5-6
J7: Open
J8: Open
7 ADC Voltage Reference
Voltage reference input
to ADC from MAX6126 or
external source (see J21
and J23)
ADC_REFP and ADC_
REFN
J28: 1-2 and 3-4
J30: 1-2 and 3-4
J24: 1-2 and 3-4
J22: 1-2 and 3-4
J29: 3-4 and 7-8
J25: 3-4 and 7-8
J26: 7-8
J27: 7-8
J7: Open
J8: Open
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│
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Figure 10a. MAX1121X EV Kit Schematic (Sheet 1 of 6)
MAX11216EVKIT U25 IS POPULATED WITH MAX11216EUG+
MAX11214EVKIT U25 IS POPULATED WITH MAX11214EUG+
NOTE: MAX11214EVKIT AND MAX11216EVKIT USE DIFFERENT COMPONENTS FOR U25 AND U20
EXTERNAL CLOCK
SMA CONNECTOR
DNI
MAX11214EVKIT U20 IS POPULATED WITH FXO-HC730-8.192 (8.192MHZ OSCILLATOR)
MAX11214EVKIT U20 IS POPULATED WITH FXO-HC730-4.096 (4.096MHZ OSCILLATOR)
*
PCC02SAAN
10K
1000PF
MAX6126AASA25
73391-0060
BAT54S
BAT54S
TP
0
*
1000PF
28
1000PF
0
49.9
0.01UF
0
1UF
TP
0.01UF
TP
MAX11214EUG+
0.01UF
0.01UF 0.1UF
49.9
0.1UF
0.1UF
49.9
0.1UF
*
OPEN
1000PF0.01UFOPEN
TP
TP
0.1UF
OPEN
TP
4.7UF
0.1UF
TP
PCC02SAAN
0
10K
FXO-HC730-8.192
C93
CB5
C96
ADC_CAPR
CB4
R55
C95
J8
J5
J4
J40
J37
C84
R63
C108 C109
C115
G4
C85 C86
C83
C87
R49
C77
J36
J34
U20
C81
C80
U21
J23
R61
C82
J21
R53
R60
ADC_REFN
R56
ADC_INP
R71
R70
C114
C106
CB6
ADC_INN
GPIO1
R72
U25
J11
D4
D3
ADC_REFP
+3.3V
RDYB_ADC
-1.8V
+3.3V
ADC_INN
ADC_INP
AVSS
AVDD
DVDD_ADC
AVSS
AVDD
+1.8V AVSS
SYNC_ADC
DOUT_ADC
DIN_ADC
EXT_REFP
EXT_REFN
DAC_OUT-
GPIO1
GPIO2
GPIO3
AVDD
AVSS
+3.3V
-1.8V
DAC_OUT+
CS_ADC
+1.8V
DVDD_ADC
EXT_REFP
SCLK_ADC
+2.0V
+2.0V
+3.3V
AGND
ADC_REFP
ADC_REFN
CLK
ADC_REFP
A3.6V
AVSS
EXT_REFN
ADC_REFN
A3.6V
1
14
2 1
3
21
3
21
3
2
1
3
2
13
2
1
3
2
1
21
4
3
3 1
5
3
4
2
1
6
7 1
2
8
5
4
3
3
2
1 3
2
1
4
24
5
13
18
6
7
8
22
2
20
3
23
19
21
16
15
17
10
9
12
11
2
1
2
OUT
OUT
IN
OUT
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
VDD
OUTPUT
GND
E/D
IN
I.C.
I.C.
OUTF
OUTS
GNDS
GND
NR
REFN
REFP
SCLK
CSB
DVDD
CAPREG
DGND
CLK
RDYB/ICLK
AVSS
CAPP
CAPN
AINP
AINN
AVSS
AVDD
GPIO1/MB1
GPIO2
GPIO3/MSYNC
RSTB
SYNC
DGND
DOUT/MB0
DIN
Maxim Integrated
│
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Figure 10b. MAX1121X EV Kit Schematic (Sheet 2 of 6)
(MAX542V-18)
0.1UF1UF
MAX9632AUA+
180PF
1UF
MAX9632AUA+
0.047UF
0.047UF
MAX9632AUA+
10K
MAX542AESD+
0.1UF
TP
TP
0.001UF
TP
10PF
TP
TP
TP
10
10K
10K
0.1UF 1UF
1UF
0.1UF
10
4.7UF 0.1UF 10UF
4.7UF
1UF
0.1UF
0.1UF
MAX6126AASA25
0.1UF
0.1UF
10K
1UF 0.1UF
TP
10K
10K
10K
0.1UF
0.047UF
10K
0.1UF
J44
J45
C52
C31 C32
C39
C23
+2.5V
U10
C46
C67
C45 C62 C63
C50 C49 C64 C65C69C68C47C48
C54
C51
R34
C59
C66
C72
R44
R29
R42
R36 C58
R43
U18
R41
C71
C61R33
R30
R40
U17
U15
U16
C132
G2
DAC-
DAC+
BUFF_OUT2
BUFF_OUT1
BUFF_OUT
-10V
+10V
DAC_OUT-
+10V
-10V
+10V
+2.5V
+10V
-10V
-10V
+10V
-10V
CS_DAC
SCLK_DAC
+10V
-10V
+5V
-10V
+5V
AGND
+5V
DIN_DAC
LDAC
+2.5V
+10V
+2.5V
DAC_OUT+
3
2
1
3
2
1
6
71
2
8
5
4
3
47
8
6
5
1
2
3
47
8
6
5
1
2
3
14
81
5
6
2
9
1310
12
4
3
11
7
47
8
6
5
1
2
3
OUT
IN
I.C.
I.C.
OUTF
OUTS
GNDS
GND
NR
IN
IN
OUT
OUT
IN
IN
IN
IN
IN
N.C.
N.C.
SHDN
VCC
VEE
OUT
IN+
IN-
IN
N.C.
N.C.
SHDN
VCC
VEE
OUT
IN+
IN-
OUT
VDD
INV
DGND
LDAC
DIN
NC
SCLK
CS
REFF
REFS
AGNDS
AGNDF
RFB
N.C.
N.C.
SHDN
VCC
VEE
OUT
IN+
IN-
Maxim Integrated
│
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Figure 10c. MAX1121X EV Kit Schematic (Sheet 3 of 6)
CONFIG
USB
U3
18PF
18PF
12MHZ
+3.3V_USB
10K
12K
LDAC_FPGA
4.7K
28
SYNC_ADC_FPGA
28
28
RDYB_ADC_FPGA
GND
USB+5V
15K
10K
28
28
+1.8V
10118192-0001LF
28
28
28
28
28
0.1UF
FT2232HL
4.7UF
DIN_DAC_FPGA
CS_DAC_FPGA
0.1UF0.1UF
10K
+3.3V_USB
0.1UF
0.1UF
0.1UF0.1UF
0.1UF
10K
2.2K
USB+5V
+3.3V_USB
10K
10K
4.7UF
+3.3V_USB
0.1UF
28
28
DOUT_ADC_FPGA
CS_ADC_FPGA
93LC66BT-I/OT
10K
10K
10K
4.7UF
+3.3V_USB
+1.8V
SCLK_ADC_FPGA
DIN_ADC_FPGA
600
+3.3V_USB
10K
SCLK_DAC_FPGA
+3.3V_USB
USB+5V
C21C18 C22 C29
C14 C17 C30
C15C19
C16C20
L3
CB2
CB3
YB1
C24
DSB1
2
1
RB23
RB26
RB25
R1
R2
J1
RB10
RB15
UB1
RB5
RB4
RB3
RB17
RB19
RB16
RB18
RB14
RB12
RB7
RB9
UB2
SHIELD
5
4
3
2
1
VCC
VSS
DO
DI
CLK
CS
BCBUS7
BCBUS6
BCBUS5
BCBUS4
BCBUS3
BCBUS2
BCBUS1
BCBUS0
ACBUS7
ACBUS6
ACBUS5
ACBUS4
ACBUS3
ACBUS2
ACBUS1
ACBUS0
BDBUS7
BDBUS6
BDBUS5
BDBUS4
BDBUS3
BDBUS2
BDBUS1
BDBUS0
ADBUS7
ADBUS6
ADBUS5
ADBUS4
ADBUS3
ADBUS2
ADBUS1
ADBUS0
OSCO
OSCI
EECS
EECLK
EEDATA
TEST
VREGOUT
VREGIN
RESET#
SUSPEND#
PWREN#
DP
DM
REF
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
IN
RB22
RB21
RB6
RB8
RB11
RB13
RB24
RB20
VCORE
GND
GND
VCCIO
VCORE
VCORE
GND
GND
VCCIO
GND
GND
VCCIO
GND
GND
VCCIO
VPLL
AGND VPHY
4
5
3
2
1
1
3
5
4
49
50
13 36
14
6
60
3
2
61
63
62
8
7
46
45
44
43
41
40
39
38
59
58
57
55
54
53
52
48
24
23
22
21
19
18
17
16
34
33
32
30
29
28
27
26
11
10
9
8
7
6
21
2 6
K A
9
4
64
37
12
56
42
31
20
51
47
35
25
15
11
5
1
10
Maxim Integrated
│
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Figure 10d. MAX1121X EV Kit Schematic (Sheet 4 of 6)
MAX14934FAWE
FPGAINI
SYNCCLK IN
ISOLATED
FMCCONNECTOR
PMODPORT A
SYNCCLK IN SPLIT
SYNCCLKOUTSYNCCLKOUT
SYNCCLK IN
TEST
PMODPORT B
MAX14934FAWE
MAX14934FAWE
SCLK_DAC_FPGA
CS_DAC_FPGA
+3.3V
VDDIO
D3.6V
0.1UF
1UF
SYNC_ADC_FPGA
RDYB_ADC_FPGA
VDDIO
DIN_DAC_FPGA
LDAC
DIN_DAC
CS_DAC
SCLK_DAC_FPGA
DIN_DAC_FPGA
CS_DAC_FPGA
LDAC_FPGA
28
SCLK_DAC
LDAC_FPGA
DOUT_ADC_FPGA
CS_ADC_FPGA
VDDIO
VDDIO
SCK_EEPROM_FPGA
CS_EEPROM_FPGA
SI_EEPROM_FPGA
28
SCLK_ADC_OUT_FPGA
0.1UF
SYNC_CLK_OUT
SYNC_CLK_IN
49.9
RDYB_ADC_FPGA
SYNC_CLK_OUT
SCLK_ADC_FPGA
DIN_ADC_FPGA
DOUT_ADC_FPGA
28
ASP-134604-01
1UF
DIN_ADC_FPGA
GND
AGND
PBC06SAAN
SO_EEPROM_FPGA
PBC10SAAN
SCLK_ADC_FPGA
DOUT_ADC_FPGA
DIN_ADC_FPGA
CS_ADC_FPGA
SCLK_DAC_FPGA
CS_ADC_FPGA
DIN_DAC_FPGA
VADJ
VADJ
LDAC_FPGA
28
SYNC_ADC_FPGA
28
28
28
28
28
1UF
ASP-134604-01
28
28
VDDIO
+3.3V
5V_FPGA
28
28
28
28
28
28
DVDD_ADC
D3.6V
28
CS_DAC_FPGA
93LC66BT-I/OT
SCLK_ADC_OUT_FPGA
RDYB_ADC_FPGA
SO_EEPROM_FPGA
SI_EEPROM_FPGA
SCK_EEPROM_FPGA
CS_EEPROM_FPGA
VDDIO
1UF
0.1UF
28
28
28
SYNC_CLK_IN
28
PBC10SAAN
RDYB_ADC
DOUT_ADC
DIN_ADC
SCLK_ADC
LDAC
CS_ADC
SO_EEPROM_FPGA
74LVC2G125DP
49.9
73391-0060
TP
1000PF
0.1UF
49.9
73391-0060
49.9
73391-0060
49.9
1000PF
74LVC2G125DP
0.1UF
TP
VDDIO
VDDIO
GND
GND
73391-0060
1UF
1UF
1UF
1UF
0.1UF
MAX3002EUP
28
28
28
28
28
DVDD_ADC
D3.6V
DVDD_ADC
DIN_DAC
SCLK_ADC
CS_ADC
DIN_ADC
SYNC_ADC
RDYB_ADC
DOUT_ADC
49.9
3V3_FPGA
ASP-134604-01ASP-134604-01
+12V_FPGA
TSW-106-08-S-D-RA
VDDIO
28
0.1UF
SCLK_ADC_FPGA
SYNC_ADC_FPGA
0.1UF
28
28
SCLK_DAC
CS_DAC
0.1UF
TSW-106-08-S-D-RA
UB3
C116
J38
J41
C111
C131
C130
J42
SYNC_CLK_IN
SYNC_CLK_OUT
J31
J19
C44
C42
C38
I/O VCC1
VCC
I/O VCC2
I/O VCC3
I/O VCC4
I/O VCC5
I/O VCC6
I/O VCC7
I/O VCC8
GND
EN
I/O VL8
I/O VL7
I/O VL6
I/O VL5
I/O VL4
I/O VL3
I/O VL2
VL
I/O VL1
U22
J43 J43
J43 J43
U29
U34
C92
RB33
RB48
C76 C79 C78 C75
RB32
RB31
RB35
C127 C129
C128 C126
RB50
RB49
RB51
J35
J33
U30
R75
R78
U28
R83
R85
R80
R84
C91C97
J39
C98
U12
R57
R58
R65
R52
R54
R50
R51
R47
R48
R46
R37
R27
R31
R35
R24
R25
R22
R23
R19
R21
R59
R62
J32
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND2
GND2
CNNE
VCC2
OUTA
OUTB
OUTC
OUTD
GND1
IND
INC
INB
INA
GND1
VCC1
GND2
GND2
ENNC
VCC2
OUTA
OUTB
OUTC
OUTD
GND1
IND
INC
INB
INA
GND1
VCC1
GND2
GND2
CNNE
VCC2
OUTA
OUTB
OUTC
OUTD
GND1
IND
INC
INB
INA
GND1
VCC1
J1-12
J1-11
J1-10
J1-9
J1-8
J1-7
J1-6
J1-5
J1-4
J1-3
J1-2
J1-1
2A
2OE
2Y
VCC
1Y
GND
1A
1OE
2A
2OE
2Y
VCC
1Y
GND
1A
1OE
VCC
VSS
DO
DI
CLK
CS
J1-12
J1-11
J1-10
J1-9
J1-8
J1-7
J1-6
J1-5
J1-4
J1-3
J1-2
J1-1
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
IN
IN
IN
OUT
OUT
OUT
IN
OUT
OUT
C6
C7
C10
C11
C12
912
9
8
7
6
5
4
3
1
12
13
14
15
16
17
18
20
1110
C40
C39
C38
C37
C36
C35
C34
C33
C32
C31
C30
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C9
C8
C5
C4
C3
C2
C1
D40
D39
D38
D37
D36
D35
D34
D33
D32
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
G40
G39
G38
G37
G36
G35
G34
G33
G32
G31
G30
G29
G28
G27
G26
G25
G24
G23
G22
G21
G20
G19
G18
G17
G16
G15
G14
G13
G12
G11
G10
G9
G8
G7
G6
G5
G4
G3
G2
G1
H40
H39
H38
H37
H36
H35
H34
H33
H32
H31
H30
H29
H28
H27
H26
H25
H24
H23
H22
H21
H20
H19
H18
H17
H16
H15
H14
H13
H12
H11
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
161
11
12
13
14
7
6
5
4
3
15
89
2
10
161
11
12
13
14
7
6
5
4
3
15
98
2
10
161
11
12
13
14
7
6
5
4
3
15
89
2
10
12
11
10
9
8
7
6
5
4
3
2
1
35
62
7
1
1
1
35
62
7
1
1
1
1
3
5
4
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
6
5
4
3
2
1
12
11
10
9
8
7
6
5
4
3
2
1
IN
84
5
3
4
2
5
3
4
2
84
5
3
4
2
5
3
4
2
2 6
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Figure 10e. MAX1121X EV Kit Schematic (Sheet 5 of 6)
TERMINALBLOCKS
ADC_REFN
ADC_INP
10K
1000PF
PBC05DAAN
EXT+
AMP+
10
PBC05DAAN
ADC_INN
10
ADC_REF/2
ADC_REFP
EXT_REFP
EXT_REFN
+10V
-10V
AGND
ADC_REFP
AMP-
49.9
+2.5V
MAX44241AUK+
0.1UF
PBC04DAAN
1UF
TP
TP
EXT_REFN
2N7002
100
TP
AVSS
AVDD
PBC04DAAN
+2.5V
-10V
MAX44241AUK+
-10V
MAX44241AUK+
1000PF
1000PF MAX44241AUK+
-10V
TP
TP
TP
10K
1000PF
10K
1000PF
1UF
+10V
+10V
IN-
ADC_REFP
OSTTA020161
IN-
IN+
+10V
1000PF
10K
0.1UF
1UF
-10V
TP
10K
10K
TP
10K
10K
TP
TP
0
-10V
0.1UF
10K
10K
1000PF
10K
TP
TP
IN+
TP
TP
0
TP
0
0
0
1M
1M
4.99
10K
1UF
4.99
0.1UF
10K
10K
1M
1M
1M
TP
10K
1M
1M
TP
TP
TP
10K
1UF
10K
1000PF
1M
1000PF
+10V
-10V
100K100K
100
GPIO2
GPIO3
1UF
100
GPIO1
AVDD
AVSS
+10V
-10V
DAC_OUT+
0.1UF
1UF
0.1UF
1UF
+10V
DAC_OUT-
TP
TP
OSTTA020161
OSTTA020161
TP
EXT_REFP
0.1UF
10K
+10V
0.1UF
10K
-10V
49.9
OSTTA020161
100K
PBC03SABN
+10V
PBC03SABN
DAC_OUT-
10K
ADC_REFP
EXT-
ADC_REFN
DAC_OUT+
ADC_REF/2
C102
C118
A_INP1
C124
C99
C107
J28
J30
J24
J22
G3
J26
J27
J14
J13
J9
J10
87
65
1
3 4
2
87
65
1
3 4
2
43
21
43
21
43
21
43
21
RB47
RB43
R82
R76
RB62
R67
RB59
R79
RB55
RB57
R73
R74
R77
R66
RB44
RB40
RB42
R69
R64
R68
RB54
RB53
RB52
RB56
RB65
RB63
RB38
RB39
RB37
RB41
RB34
RB36
RB60
RB30
RB27
RB28
C88 C100 C103C90
C112 C121 C119C110
C117 C120 C123C113
C101C104C94C89
RB61RB64
R81
RB66
RB58
RB46
RB45
VSS
VDD
INA-
INA+
OUTA
VSS
VDD
INA-
INA+
OUTA
VSS
VDD
INA-
INA+
OUTA
VSS
VDD
INA-
INA+
OUTA
G
S
D
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
C122
U27
A_INP2
C125
J29
U26
U24
C_INP2
J25
U23
C_INP1
C105
QB1
C133
AVDD
EXT_REFN
EXT_REFP
IN+
GPIO3
GPIO2
IN-
CH_D+
CH_D-
CH_C+
CH_C-
CH_B+
CH_B-
CH_A+
CH_A-
AVSS
TP2
10 9
8 7
6 5
4 3
2 1
10
9
87
65
43
21
2
1
2
1
2
1
2
1
2
2
1
4
3
87
65
43
211
4
3
1
4
3
87
65
43
211
4
3
43
21
43
21
43
21
43
21
1
R87
R86
J7
J6
3 1
3 1
2 5
2 5
2 5
2 5
2 3
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Figure 10f. MAX1121X EV Kit Schematic (Sheet 6 of 6)
ISOLATED
USB POWER
TERMINAL BLOCK
MAX13256ATB+
1K
MBR0520L
10UF
TP
PCC02SAAN
PBC03SABN
0.1UF
MAX15006CATT+
180PF
0
TP
169K
105K
0
1UF
715K
0.1UF
1UF
0.1UF
0.1UF
100K
0.1UF
100K
TP
TP
TP
237K
1UF
237K
MAX8842ELT+
453K
6.04K
1UF
TP
453K
1UF
MAX8842ELT+
TP
1UF
6.04K
0.1UF
MAX15006AATT+
KLDX-0202-B
OSTTA020161
MBR0520L
TP
0.47UF10UF
1K
1K
TGM-H240V8LF
BAS4002A-RPP 600
1UF
600
TP
1UF
TP
600
600
1UF1UF
TP
PBC03SABN
MAX15006CATT+
100K
TP
10UF
TP
1UF
10UF
237K
237K TP
1UF
150K
1UF
MAX8842ELT+
MAX8842ELT+
1UF
TP
1UF
100K
MAX664ESA
0.1UF
100
1UF 0.1UF
MAX15006BATT+
10UF
MAX15006CATT+
0
180PF
BAS4002A-RPP
PCC02SAAN
TP
39K
MBR0520L
TP
10UF
1K
0.1UF
715K
+10V
C7
C13
-10V
G1
C40
R4
C5
R3
R8
U2
DB1
C4C3C2
C9
R5
U5
R20
R18
+3.3V
C12C11
C10
U11
C41C43
DS2
L2
C1
L1
L5
C8
L4
+5V
C28
T1
DS1
U3
R6
U6
C33
C37
-1.8V
C73
+12V
C70
G6
RB1
RB29
R39
R7
RB2
J15
R38
D1
D2
C36
R16
R10
C27
A3.6V
C74
R13
U9
C35
R15
R12
R9
U19
C26
+2.0V
U8
R14
C34
R11
C25
D3.6V
R17
U7
R45
J20
U14
C57
C56
C55
+1.8V
R26
R28
C6
R32
C60C53
U13
J18
-10VEXT
+10VEXT
J2
-15VEXT
+15VEXT
J17
J3
U4
U1
CB1
J16
J46
J12
G5
+12V_FPGA
USB+5V
+3.3V
-10V
+5V
AGND
GND
+5V
+2.0V
VDDIO
+3V3_USB
D3.6V
+5V
+15V +5V
VDDIO
A3.6V
+12V
+5V
+15V
-1.8V
+15V
5V_FPGA
+1.8V
-10V
+10V
21
2
1
3
2
1
3
2
1
21
C A
C A
6
5
1
2
43 6
5
1
2
43
6
5
1
2
43
21
6
5
3
2
1
4
7
6
5
1
2
43
65 43 21
65 43 21
4
32
14
32
1
6
3
2
1
4
5
7
6
3
2
1
4
5
7
6
3
2
1
4
5
7
21
21
21
21
8
7
6
54
3
2
1
K A
2
1
8
10
5
9
7
11
3
64
6
5
3
2
1
4
7
6
1
74
5
3
2
8
C A
K A
3
2
1
FB
OUT
NC
IN
IN
DNG PE
FB
OUT
NC
IN
IN
DNG PE
FB
OUT
NC
IN
IN
DNG PE
8
7
6
5
4
3
2
1
EP
ST1
GND2
ST2
GND1
FAULT
ITH
EN
CLK
VDD2
VDD1
OUT
OUT
NC
IN
IN
DNG PE
OUT
SHDN FB
OUT
NC
IN
GND
VIN-
SHDN2
SHDN1
VSET
GND
VOUT1
VOUT2
SENSE
OUT
SHDN FB
OUT
NC
IN
GND
OUT
SHDN FB
OUT
NC
IN
GND
OUT
IN
OUT
OUT
IN
OUT
OUT
OUT
NC
IN
IN
DNG PE
OUT
OUT
OUT
OUT OUT
OUT
OUT
SHDN FB
OUT
NC
IN
GND
65
1
3 4
2
65
1
3 4
2
~
~ -
+
D4
D3
D2
D1
~
~ -
+
D4
D3
D2
D1
1
3
2
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Figure 11. MAX1121X EV Kit Component Placement Guide—Top Side
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Figure 12. MAX1121X EV Kit PCB Layout—Layer 1
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Figure 13. MAX1121X EV Kit PCB Layout—Layer 2
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Figure 14. MAX1121X EV Kit PCB Layout—Layer 3
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Figure 15. MAX1121X EV Kit PCB Layout—Layer 4
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Figure 16. MAX1121X EV Kit PCB Layout—Layer 5
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Figure 17. MAX1121X EV Kit PCB Layout—Layer 6
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Figure 18. MAX1121X EV Kit Component Placement Guide—Bottom Side
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
Refer to file “evkit_bom_max1121X_evkit_a.csv” attached
to this data sheet for component information.
#Denotes RoHS compliant.
PART TYPE
MAX11214EVKIT# EVKIT
MAX11216EVKIT# EVKIT
Ordering Information
Component List
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2015 Maxim Integrated Products, Inc.
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Evaluates: MAX11214/MAX11216
MAX1121X Family Evaluation Kit
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 4/15 Initial release —
Revision History
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
