VPC3230D - Micronas Semiconductor

VPC 323xD

Comb Filter Video

Processor

Edition July 26, 2001

6251-472-1PD

PRELIMINARY DATA SHEET

MICRONAS

VPC 323xD PR EL IMINARY DA TA SHEET

2Micronas

Contents

Page Section Title

5 1. Introduction

5 1.1. System Architecture

6 1.2. Video Processor Family

7 1.3. VPC Applicat ions

8 2. Functional Description

8 2.1. Anal og Video Front-En d

8 2.1.1. Input Selec tor

8 2.1.2. Clamping

8 2.1.3. Autom atic Ga in Control

8 2.1.4. Analog-to-D igital Converters

8 2. 1. 5 . Digit a lly C o nt rolled C lo c k Os c illator

8 2.1.6. Anal og Video Out put

9 2.2. Adap tive Comb Filter

9 2.3. Color Decoder

10 2.3.1. IF-Compensation

10 2.3.2. Demodulator

10 2.3.3. Ch rominanc e Filter

11 2.3.4. Fr equency Dem odulator

11 2.3.5. Burst Detection / Saturation Control

11 2.3.6. Color Killer Operation

11 2.3.7. Autom ati c standard recognition

12 2.3.8. PAL Com pens ation/1-H Comb Filte r

13 2.3.9. Lu minanc e Notch Filter

13 2.3.10. Skew Filtering

13 2.4. Co mponent Interface Processor CIP

13 2.4.1. Component Analog Front-End

13 2.4.2. Matrix

13 2.4.3. Component YCrCb Control

14 2.4.4. Softmixer

14 2.4.4.1. Static Switc h Mode

14 2.4.4.2. Static Mixer Mode

14 2.4.4.3. Dynamic M ixer Mode

15 2.4.5. 4:4:4 to 4:2:2 Downsampl ing

15 2.4.6. Fas t Blank and Signal Monitoring

15 2.5. Horiz ontal Scaler

15 2.5.1. Hor izontal Lowpass-filter

16 2.5.2. Hor izontal Prescaler

16 2.5.3. Hor izontal Scaling Engine

16 2.5.4. Hor izontal Peaking-filter

17 2.6. Vertical Sca ler

17 2.7. Contrast and Brightness

17 2.8. Bla ckline Detector

17 2.9. Co ntrol and Data Output Signals

17 2.9.1. Line-Loc ked Clock Generat ion

18 2.9.2. Sync Signals

18 2.9.3. DIGIT3000 Output Format

Contents, continued

Page Section Title

PRELIMINAR Y DATA SHEET VPC 323xD

Micronas 3

18 2.9.4. L ine-Locked 4: 2:2 Output Form at

18 2.9.5. L ine-Locked 4: 1:1 Output Form at

18 2.9.6. ITU -R 656 Outpu t Format

20 2.9.7. O utput Code Levels

20 2.9.8. Out put Ports

20 2.9.9. Tes t Pattern Gen erator

20 2.10. PAL+ S upport

20 2.10.1. Out put Signa ls for PA L+/ Colo r+ Supp ort

22 2.11. Vid eo Sync Processing

24 2.12. Picture in Picture (PIP) Processing and Control

24 2.12.1. Configurations

25 2.12.2. PIP Display Modes

25 2.12.3. Predefined Inset Picture Size

29 2.12.4. Acquisition and Display Window

29 2.12.5. Frame and Background Color

29 2.12.6. Vertical Shift of the Main Picture

29 2.12.7. Free Running Display Mode

29 2.12.8. Frame and Field Display Mode

30 2.12.9. Ext ernal Field Memory

31 2.12.10. Fiel d-Buffer-Extension M ode

31 2.12.11. Double-Windows-Extension Mode

32 3. Serial Interface

32 3.1. I2C -Bu s Interf a ce

32 3.2. Control and Status Registers

53 3.2.1. C alculation of Vertical and East-West

Defl ection Coefficients

53 3.2.2. Scaler Adjustment

55 4. Specifications

55 4.1. O utline Dimension s

55 4.2. Pin Connections and Short Descriptions

58 4.3. Pin Descriptions

(pin numbers for PQFP80 package)

61 4.4. Pin Configuration

62 4.5. Pin Circuits

64 4.6. Ele ctrical Characteristics

64 4.6.1. Absol ute Max imum Ratings

64 4.6.2. Recommended Operating Conditions

65 4.6.3. Recommended Crystal Characteristics

66 4.6.4. Characteristics

66 4.6.4.1 . Characteristics, 5 MHz Clock Output

66 4.6.4.2. Charac teristics, 20 MHz Clock Input/Output, External Clock Input (XTAL1)

66 4.6.4.3. Characteristics, Reset Input, Test Input, VGAV Input, YCOEQ Input

67 4.6.4.4 . Characteristics, Power-up Sequence

68 4.6.4.5. Charac teristics, FPDAT Input/Outp ut

68 4.6.4.6 . Characteristics, I2C Bus Interface

VPC 323xD PR EL IMINARY DA TA SHEET

4Micronas

Conte nts, conti nued

Page Section Title

68 4.6.4.7. Characteristics, I2C Bus Address Select I2CSEL Input

69 4.6.4.8. Charac teristics, Analog Video and Compon ent Inputs

69 4.6.4.9. Characteristics, Analog Front-End and A DCs

71 4.6.4.10 . Ch aracteristics, Analog F B Input

72 4.6.4.11 . Ch aracteristics, Output Pin Specification

75 4.6.4.12 . Ch aracteristics, Input Pin Specification

76 4.6.4.13 . Ch aracteristics, Clock Output Specificat ion

78 5. Application Circuit

79 5.1. Appl ication Note : VGA mode with VPC 323xD

80 5.2. Application Note: PIP Mode Programming

80 5.2.1. Procedure t o Program a PIP Mode

80 5.2.2. I2C Registers Programming for PIP Control

82 5.2.3. Examples

82 5.2.3.1. Sel ect Predefined Mod e 2

82 5.2.3.2. Sel ect a Strobe Effect in Expert Mode

83 5.2.3.3. Select Pred efined Mod e 6 for Tuner Scanning

84 6. Dat a Sheet History

PRELIMINAR Y DATA SHEET VPC 323xD

Micronas 5

Comb Filter Video Processo r

1. Introduction

The VPC 323xD is a high-quality, single-chip video

front-end, which i s ta rgeted for 4: 3 an d 16: 9, 50/60-Hz

and 100/120 Hz TV sets. It can be combined with other

members of the DIGIT3000 IC family (such as

DDP 331x) and/or it can be used with 3rd-party prod-

ucts.

The main features of the VPC 323xD are

– high-performance adaptive 4H comb filter Y/C sepa-

rator with adjustable vertical peaking

– multi-standard color decoder PAL/NTSC/SECAM

including all substandar ds

– four CVBS, one S-VHS input, one CVBS output

– two RGB/YCrCb component inputs, one Fast Blank

(FB) input

– integrated high-quali ty A/D converters and associ-

ated clamp and AGC circuits

– multi-standard sync proces sing

– linear horizontal scaling (0.25 ... 4), a s well as

non-linear horizontal scaling ‘Panoramavision’

– PAL+ preproc essing

– li ne-locked c lock, data and sync, or 656-output

interface

– peak ing, contrast, brightness, color saturation and

tint for RGB/YCrCb and CVBS/S-VHS

– high-qual ity soft mixer controlled by Fast Blank

– PIP processing for four picture sizes ( , or

of normal size) wit h 8-bit resolution

– 15 predefined PIP display configurations and expert

mode (fully program mable)

– control interface for ext ernal field memory

–I

2C-bus interface

– one 20.25-MHz crystal, few external components

– 80 -pin PQFP pac kage

1.1. System Architecture

Fig.1–1 shows the block diagram of the video proces-

sor

Fig.1–1:Block diagram of the VPC323xD

---1

------

---

Mixer

CIN

VIN1

VIN2

VIN3

VIN4

VOUT

Adaptive

Comb Color

Decoder Output

Formatter

Matrix

Filter

2D S cale r

Panorama

Mode

PIP I TU-R 656

ITU-R 601

Memory

Control

Sync

AGC

Contrast

Saturation

Brightness

Tint

NTSC

PAL

NTSC

PAL

SECAM

Clock

Generation

CrCb

OUT

Y OUT

YCOE

FIFO

CNTL

H Sync

V Sync

AVO

I2C Bus20.25 MHz

RGB/

Y/G

U/B

LL Clock

Saturation

Tint

Analog

Front-end

Contrast

Brightness

Peaking

Clock

Gen.

I2C Bus

V/R

FB FB

YCrCb

RGB/

YCrCb

2×ADC

Analog

Component

Front-End

4 x ADC

Processing

VPC 323xD PR EL IMINARY DATA SHEET

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1.2. Video Processor Family

The VPC video processor family supports 15 /32-kHz

systems and is available with different comb filter

options. Table 1–1 gives an overview of the VPC video

processor family.

Table 1–1: VPC Processor Family for 100 Hz, Double-Scan and Line-Locked Clock Applications

Features

Type Adaptive

Combfilter

(PAL/NTSC)

Panorama

Vision Analog

Com ponent

Inputs

Vertical Scaler

(PIP) Digital Output

Interface

VPC 3230D 4H ✓2✓ITU-R 601,

ITU-R 656

VPC 3231D ✓2✓ITU-R 601,

ITU-R 656

VPC 3232D 4H ✓✓

ITU-R 601,

ITU-R 656

VPC 3233D ✓✓

ITU-R 601,

ITU-R 656

VPC 3215C 4H ✓ITU-R 601

VPC 3210A 2H ✓ITU-R 601

VPC 3211A ✓ITU-R 601

PRELIMINAR Y DATA SHEET VPC 323xD

Micronas 7

1.3. VPC Applications

Fig. 1–2 depicts several VPC applications. Since the

VPC functions as a video front-end, it must be comple-

mented with additional functionality to form a complete

TV s et.

The DDP 331x cont ains the video back-end wi th vid eo

postprocessing (contrast, peaking, CTI,...), H/V-deflec-

tion, RGB insertion (SCART, Text, PIP,...) and tube

control (cutoff, white-drive, beam current limiter). It

generates a beam scan velocity modulation output

from the digital YCrCb and RGB signals. Note, that this

signal is not generated from the external analog RGB

inputs.

The component interface of the VPC 323xD provides a

high-quality analog RGB interface with c haracter inser-

tion capability. It also allows appropria te processing of

external sources, such as MPEG-2 set-top boxes in

transparent (4:2:2) quality. Furthermore, it transforms

RGB/Fast Blank signals to the common digital video

bus a nd makes t hose signals avail able for 100-Hz up-

conversion or double-scan processing. In some

European countries (Italy), this feature is manda tory.

SRC (e. g. SDA 94xx from Micronas) indicates mem-

ory based image processing, such as scan rate con-

version, vertical processing (Zoom), or PAL+ recon-

struction. The VPC supports memory-based

applications through line-locked clocks, syncs, and

data. A dditionally, the VPC 323xD provid es a 656-ou t-

put interface and FIFO control signals.

Examples:

– Europe: 15 kHz/50 Hz → 32 kHz/100 Hz interlaced

– US: 15 kHz/60 Hz → 32 k Hz/ 60 Hz non-interlaced

Fig. 1–2: VPC 32xxD applications

a) 15-kHz application Europe

b) double-sc an appl ication (US, Japan) with YCrCb i nputs

c) 100-Hz application (Europe) with RGBFB inputs

RGB

H/V

RGB

Defl.

H/V

Defl.

DDP

331x

DDP

331x

DDP

331x

SRC

VPC

323xD

VPC

323xD

RGB

VPC

323xD

CVBS

YCrCb/RGBFB

CVBS

YCrCb

CVBS

YCrCb/RGBFB

a) VPC

323xD FIFO

YCrCb/RGBFB

CVBS

VPC 323xD PR EL IMINARY DATA SHEET

8Micronas

2. Functional Description

2.1. Analog Video Front-End

This block provides the analog interfaces to all video

inputs and mainly carries out analog-to-digital conver-

sion for the following digital video processing. A block

diagram is given in Fig. 2–1.

Most of the functional blocks in the front-end are digi-

tally controlled (clamping, AGC, and clock-DCO). The

control loops are closed by the Fast Processor (‘FP’)

embedded in the decoder.

2.1.1. Input Selector

Up to five analog inputs can be connected. Four inputs

are for composite video or S-VHS luma s