HYUNDAI HY53C256 Series 256K x 1-bit CMOS DRAM DESCRIPTION The HY53C256 is fast dynamic RAM organized 262 ,144 x 1-bit. The HY53C256 utilizes Hyundais CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins to the users. Multiplexed address inputs permit the HY53C256 to be Packaged in a standard 300mil 16pin PDIP, 330mil! 18pin PLCC. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipments. System oriented feature includes single power supply of 5V+ 10% tolerence and direct interfacing capability with high performance logic families such as Schottky TTL. FEATURES * Low power dissipation Max. CMOS standby 5.5mW (L-part) 11.0mWw Max. TTL standby 11.0mW (L-part) 16.5mW Max. operatin Speed Power 70 385mW | 80 330mW 10 275mW + Single power supply of 5V+ 10% TTL compatible inputs and outputs Fast access time Speed tRac tcac tPc 70 70ns 15ns 50ns 80 80ns 20ns 55ns i .10 100ns | 25ns | 60ns * Fast page mode operation * Read-Modity-Write capability * CAS-before-RAS, RAS-only, Hidden retresh * 256 refresh cycles / 4ms PIN DESCRIPTION RAS Row Address Strobe CAS Column Address Strobe WE Write Enable A0-A8 Address Input D Data Input Q Data Output Vec __| Power (+ 5V) Vss Ground This document is a general product description and is sub; 1AA01-20-MAY94 UB?S5088 O00e283 edt ject to ch responsibility for use of circuits described. No Patent licences are impl PIN CONNECTION BLOCK DIAGRAM D Q 9 9 DATA IN BUFFER DATA OUT BUFFER COLUMN CLOCK GENERATOR COLUMN 1 LXPREDECODER [7a ""_ coumn o DECODER ago o Aron 8 REFRES| FRESH ere CONTROLLER SENSE AMP we UO GATE Aa AS Ow B REFRESH Ag 0 COUNTER ms oe U ROW ARRAY e R DECODER | setaey SUBSTRATE BIAS GENERATOR UJ ROW : (9) EY RAS CLOCK J ATOR GENER PF o CC O VSS ange without notice. Hyundai electronics does not assume any ied. 13HYUNDAI HY53C256 Series eee ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT TA Ambient Temperature Oto 70 c TsTG Storage Temperature -55 to 125 Cc Vin, VOUT Voltage on Any Pin Relative to Vss -1.0 to 7.0 Vv Vec Voltage on Vcc Relative to Vss -1.0 to 7.0 Vv los Short Circuit Output Current 50 mA Po Power Dissipation 1.0 Ww TSOLDER Soldering Temperatures Time 2602 10 *Cesec NOTE : Operation at or above Absolute Maximum Ratings can adversely affect device reliability. RECOMMENDED DC OPERATING CONDITIONS A= Voc VIH VIL Low NOTE : All voltages are referenced to Vss. 14 TAAG1-20-MAYO4 @ 4675088 oO0eed4 156HYUNDAI DC CHARACTERISTICS TA= 0C to 70C, Voc= 5 Vt 10%, VSs= OV, unless otherwise noted.) HY53C256 Series SYMBOL | PARAMETER TEST CONDITIONS SPEED/ MIN. [MAX. | UNIT] NOTE P Ii Input Leakage Current Vsss VINS Vcc, -10| 10] pA (Any Input Pins) All other pins not under test= Vss ILo Output Leakage Current | Vsa< VouT< Vec, 10} 10) pA (High impedance State) | RAS & CAS at Vin Icc1 | Voc Supply Current, | tRo= tRc (min.) 70 -| 70} mA] 1,23 Operating 80 -| 60 100 -; 50 Icc2 | Vec Supply Current, RAS & CAS at Vin, - 3} mA} 4 TTL Standby other inputs> Vss L-part - 2 ic3 | Vcc Supply Current, tAc= tRc (min.) 70 -| 70) mA] 1,3 RAS-only refresh 80 -| 60 100 - | 50 Icca | Vec Supply Current, tPc= {Pc (min.) 70 -| 45/ mA] 1,23 Fast Page mode 80 -}; 40 100 -| 3 Ics | Vcc Supply Current, FAS & CAS < Voc-0.2V - 2] mA CMOS Standby L-part - 1 4 Ice | Vcc Supply Current, tRc= tRc (min.) 70 -| 70| mMA{ 13 TAS-betore-RAS retresh 80 -| 60 100 -}| 50 VOL Output Low Voltage lol= 4.2mA -| 04] V Vou | Output High Voltage lOH= -5SmA 2.4 -| Vv | NOTE : 1. Icc1, Icc3, Icc4 and Icce depend on cycle rate. 2. ICc1 and Icc4 depend on out 3. It depends on user whether 4. ICca(max.)= 2mA and Icca( put loading. Specified values ara obtained with the output open. . column address is changed or not at least once while RAS= ViL and CAS= Vin. max.)= 1mA are only applied to L-part Only (HY53C256LS and HY53C256LF). 1AA01-20-MAY94 4675088 OO0e265 Dee 15HYUNDAI AC CHARACTERISTICS (Ta=_0C to 70C, Vec= 5V+ 10%, HY53C256 Series Vss= OV. unless otherwise noted.) NOTE : 1,2. 3 HY53C256S/F/LS/LF # | SYMBOL PARAMETER -70 -80 =10 UNIT | NOTE MIN. | MAX. | MIN. [MAX. | MIN. [MAX. 1] tre Random Read or Write Cycle Time 130 - | 145 - | 175 -| ns 2) tawc Read-Modify-Write Cycle Time 155 - | 175 -| 210 - | ms 3 | tPC Fast Page Mode Cycle Time 50 - | 55 -| 60 - | ns 41 tprwc | Fast Page Mode Read-Modify-Write 75 -| 85 -| 95 - |) ns Cycle Time 5 | tRAG Access Time from RAS -| 70 -| 80 - | 100 | ns | 4,9,10 6.| tcac Access Time from CAS -| 15 -| 20 -| 25) ns | 49 7 | tAA Access Time from Column Address -| 3 -} 40 -| 45] ns | 4,10 8 | tcPA Access Time from CAS Precharge -| 45 -}| 50 -| 55 | ns 4 9 | toi CAS to Output Low Impedance 0 - 0 - 0 -| ns 4 40 | toFF Output Buffer Turn-off Delay Oo} 15 Oo} 20 0} 25; ns 5 11 | tT Transition Time (Rise and Fall) 3} 25 3} 25 3] 25) ns 3 12 | tRP RAS Precharge Time 50 -| 55 -| 65 - | ns 13 | tRAS RAS Pulse Width 70 | 75K | 80 | 75K {| 100 | 75K | ns 74 trasp | RAS Pulse Width (Fast Page Mode) 70 | 75K | 80] 75K | 100 | 75K | ns 15 | tRSH(W) | RAS Hold Time in Write Cycle 25 -| 25 -| 30 - | ns 16 | tCSH CAS Hold Time 70 -| 80 - | 100 -| ns 47 | tcas(w) | CAS Pulse Width in Write Cycle 20 -| 25 -| 30 -| ns 78 | taco | RAS to CAS Delay 25| 55! 25] 60| 25| 75) ns 9 19 | tRAD PAS to Column Address Delay Time 901 35| 20[ 40] 20; 55/ ns 10 20 | tcRP TAS to RAS Precharge Time 15 -{ 15 -| 15 -| ns 21 | tcP TAS Precharge Time 15 -| 15 -| 20 -| ns 22 | taSR Row Address Set-up Time 0 - 0 - 0 - | ns 23 | tRAH Row Address Hold Time 15 -| 15 -| 15 -}) ns 24 | tasc Column Address Set-up Time 0 : 0 - 0 - | ns 25 | tCAH Column Address Hold Time 15 -| 15 -| 20 - | ns 26 | tan Column Address Hold Time from RAS 55 - | 60 -| 70 - | ns 27 | tRAL Column Address to RAS Lead Time 35 - | 40 -| 45 - | ns 28 | trcs Read Command Set-up Time 0 - 0 - 0 -| ns 29 | tRCH Read Command Hold Time 5 - 5 - 5 -| ns 6 Referenced to CAS tRRH Read Command Hold Time 5 - 5 - 5 -| ns 6 Referenced to RAS 31 | twcH | Write Command Hold Time 15 -| 18 -| 20 - | ns 32 | twcr | Write Command Hold Time irom RAS 55 -| 60 -| 70 - | ns 33 | twP Write Command Pulse Width 15 -| 15 -| 20 - | ns 34 | taw. | Write Command to RAS Lead Time 20 -| 2 -| 30 -| ns 35 | tcw | Write Command to TAS Lead Time 20 -| 25 -| 30 - | ns 36 | tos Data-In Set-up Time . 0 - 0 - 0 - | ons 7 37 | tH Data-in Hold Time 15 -| 15 -| 20 - | ns 7 38 | touR | Data-in Hold Time Referenced to RAS 5; -| oo| -| 7o| -[ ms] 39 | tREF Refresh Period (256 cycles) - 4 - 4 - 4| ms 40 | twos | Write Command Set-up Time 0 0 - 0 ns 8 16 1AA01-20-MAY94 GB 4675068 OO0eedb ThoHYUNDAI HY53C256 Series AC CHARACTERISTICS (continued) HY53C256S/F/LS/LF # | SYMBOL PARAMETER -70 -80 ~10 UNIT | NOTE | MIN. [MAX. | MIN. [ MAX. | MIN. | MAX. 41 | tcwo | CAS to WE Delay Time 15 -| 20 -| 25 - | ns 8 42 | tRWD RAS to WE Delay Time 70 - | 80 - | 100 - | ns 8 43 | tawp Column Address to WE Delay Time 35 -| 40 -| 45 -| ns 8 44 | tcsr CAS Set-up Time (CBR Cycle) 10 -}+ 10 -}; 10 -| ns 45 | tcHR | CAS Hold Time (CBR Cycle) 20/ -| 25 -| 30 - | ns 46 | tRPC RAS to CAS Precharge Time 0 - 0 - 0 -| ns 47 | tcpT CAS Precharge Time (CBR Counter Test) | 15 -| 15 -| 20 - | ns 48 | tAsH(R) | RAS Hold Time in Read Cycle 15 -| 20 -| 25 - {| ns 49 | tcas(R) | CAS Pulse Width in Read Cycle 15 | 75K | 20] 75K! 25) 75K | ns 50 | tRRW RAS Pulse Width (RMW) 95 -| 110 -} 135 -| ns 1AA01-20-MAY94 17 4675088 O00e287? ITSHYUNDAI HY53C256 Series NOTE : 1. An initial pause of 200us is required after power-up followed by 8 RAS only refresh cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 CAS-before-RAS in- itialization cycles instead of 8 RAS cycles are required. . AC measurements assume tT= 5ns. Vin(min.) and ViL{max.) are reference levels for measuring timing of input signals. Also, transition times are measured between Vix and VIL. . Measured with a load equivalent to 2 TTL loads and 100pF. . tOFF(max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 6. Either tRCH or tRRH must be satisfied for a read cycle. 7. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in Read- Modity-Write cycles. 8. twos, tRwo, tcwo and tawp are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If twos> twes(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. If tRwD2 tRwo(min.), tcewD> tcwD(min) and tAWD> tawD(min.} the cycle is a Read-Modify-Write cycle and data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminated. 9. Operation within the tRcD(max.) limit insures that tRAC{max.) can be met. tAcD(max.) is specified as a refer- ence point only. If tRCD is greater than the specified thcD(max.) limit, then access time is controlled by CAC. 10. Operation within the tRA{max.) limit insures that tRAC{max.) can be met. tRAD(max.) is specified as a refer- ence point only. If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tA. on on hb CAPACITANCE A= Vec= CINt Cine COUT 18 1AA01-20-MAY94 4675088 0002286 431HYUNDAI HY53C256 Series TIMING DIAGRAM READ CYCLE VALID DATA EARLY WRITE CYCLE WE VALID DATA VOH-- a HIGH-Z vou- 1AA01-20-MAY94 19 M8 4675048 0002285 778 oeHYUNDAI HY53C256 Series READ-MODIFY-WRITE CYCLE A0-8 oO VALID DATA Q VALID DATA FAST PAGE MODE READ CYCLE RAS tROD(18) CAS A0-8 COLUMN COLUMN tARH(30) WE -_TRAG(S) Q -_ VALID DATA VALID DATA VALID DATA 20 1AA01-20-MAY94 mM 4675088 0002290 447HYUNDAI HY53C256 Series FAST PAGE MODE EARLY WRITE CYCLE A0-B COLUMN D VALID DATA VALID DATA VALID DATA VOH- Q HIGH-Z VOL- FAST PAGE MODE READ-MODIFY-WRITE CYCLE RAS CAS A0-8 WE o VALID DAT: VALIO DAT, VALID DAT ICLZ(9) a OO VALID DATA VALID DATA VALIO DATA 1AA01-20-MAY94 21 BH 4675088 0002291 326 omCYUNDAI HY53C256 Series Se ne RAS-ONLY REFRESH CYCLE IRC(1) = . peel tAPC(4B) = 2 TT WILLE LLL LLL LLL NOTE : WE="H" or L" CAS-BEFORE-RAS REFRESH CYCLE HiGH-Z: tAP{12) viH- BAS tAPC(48) 10P(21) \_ 4) ViH- CAS VIL ~ TLL LL we TTL LLL LLL LLL ____ 4 VOH F(s0y VOL NOTE : A0-8="H" or L HIGH-Z 22 Me 4675088 O00ee92e ebe 1AA01-20-MAY94HYUNDAI HY53C256 Series HIDDEN REFRESH CYCLE (READ) ~ TD = Cs TLL mohanl 7, | = nnn ~ TE von | em 1AA01-20-MAY94 Ba 4675088 0002293 174 23HYUNDAI _ HY53C256 Series CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE VIH~ a VIH ~ READ CYCLE tRAH(30) al VOH Q VALID DATA VOL - WRITE CYCLE al o VALIO DATA HGH.2 oO" VOH Q HIKGH-Z 24 1AA01-20-MAY94 Me 4675048 oo0eeI4 O35HYUNDAI HY53C256 Series PACKAGE INFORMATION 300 mil 16 pin Plastic Dual In Line Package (S) P10 fo 4 od ed). UNIT : INGH(mm) oO UoTeCI tayo oy ct 0.775(19.685) 0.755(19.177) 0.188(4.699 0.3008SC(7.620) 0.062(1.575 a 0.100BSC (2.540) 9.160(4.084) 0.145(3.683) 0.270(6.858) 0.050(1.270} > 35(3. 429) 0.250(6.380) jl \ 4 9.401.016) 0.026(0.635) 0.045(1.143) _| 0.021(0.533) _ Bt ell --0.014(0.356) 0.025(0.635) 0.015(0.381) mao 4 0,008(0.200) 330 mil 18 pin Plastic Leaded Chip Carrier (F) UNIT : INGH(mm) 0,293(7.442 .287(7.290) J O 0.493(12.522 0.487(12.370) 0.520(13.208) Sifirirl IN 0.050(1.270) 0.013{0.320) 7 iO! Uy 7 Y 0.222(5.639) 0.140(3.556 0.100(2.540) MIN 0.015(0.381) _ 9.021(0.533) 0.013(0.331) 0.465(11.811) 0.422(10.719) 1AA01-20-MAY94 25 4675088 gO00e29S T7lHYUNDAI ORDERING INFORMATION PART NO SPEED POWER | PACKAGE HY53C256S 70/80/10 PDIP HY53C256LS 70/80/10 | L-part PDIP HY53C256F 70/80/10 PLCC HY53C256LF 70/80/10 | L-part PLCC 26 HY53C256 Series WB 4675088 OO0eeIb 106 1AA01-20-MAY94