2.7 V to 5.5 V, Serial-Input,
Voltage-Output, 16-Bit DACs
Data Sheet
AD5541/AD5542
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
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FEATURES
Full 16-bit performance
3 V and 5 V single-supply operation
Low 0.625 mW power dissipation
1 µs settling time
Unbuffered voltage output capable of driving 60 kΩ
loads directly
SPI-/QSPI-/MICROWIRE-compatible interface standards
Power-on reset clears DAC output to 0 V (unipolar mode)
5 kV HBM ESD classification
Low glitch: 1.1 nV-sec
APPLICATIONS
Digital gain and offset adjustment
Automatic test equipment
Data acquisition systems
Industrial process control
GENERAL DESCRIPTION
The AD5541/AD5542 are single, 16-bit, serial input, voltage
output digital-to-analog converters (DACs) that operate from
a single 2.7 V to 5.5 V supply. The DAC output range extends
from 0 V to VREF.
The DAC output range extends from 0 V to VREF and is guaranteed
monotonic, providing 1 LSB INL accuracy at 16 bits without
adjustment over the full specified temperature range of −40°C to
+85°C. Offering unbuffered outputs, the AD5541/AD5542
achieve a 1 µs settling time with low power consumption and low
offset errors. Providing a low noise performance of 11.8 nV/√Hz
and low glitch, the AD5541/AD5542 is suitable for deployment
across multiple end systems.
The AD5542 can be operated in bipolar mode, which generates
a ±VREF output swing. The AD5542 also includes Kelvin sense
connections for the reference and analog ground pins to reduce
layout sensitivity.
The AD5541/AD5542 utilize a versatile 3-wire interface that is
compatible with SPI, QSPI™, MICROWIRE™ and DSP interface
standards. The AD5541/AD5542 are available in 8-lead and
14-lead SOIC packages.
FUNCTIONAL BLOCK DIAGRAMS
6
1
2
8
7
16-BI T DAC
16-BI T DAC L ATCH
SERIAL INPUT REGISITER
V
DD
DGND
DIN
REF
CS
SCLK
3
4
5
V
OUT
AGND
AD5541
CONTROL
LOGIC
07557-001
Figure 1. AD5541
11
2
3
14
12
16-BI T DAC
16-BI T DAC L ATCH
SERIAL INPUT REGISITER
V
DD
DGND
LDAC
REFF
CS
DIN
6
REFS
5
7
10
V
OUT
13
INV
1
RFB
AGNDF
4
AGNDS
AD5542
CONTROL
LOGIC
07557-002
8
SCLK
R
FB
R
INV
Figure 2. AD5542
Table 1.
Part No.
Description
AD5541A/AD5542A
Single, 16-bit unbuffered nanoDAC™,
±1 LSB INL, LFCSP
AD5024/AD5044/AD5064 Quad 12-/14-/16-bit nanoDAC,
±1 LSB INL, TSSOP
AD5062
Single, 16-bit nanoDAC, ±1 LSB INL,
SOT-23
AD5063
Single, 16-bit nanoDAC, ±1 LSB INL,
SOT-23
PRODUCT HIGHLIGHTS
1. Single-Supply Operation. The AD5541 and AD5542 are fully
specified and guaranteed for a single 2.7 V to 5.5 V supply.
2. Low Power Consumption. These parts consume typically
0.625 mW with a 5 V supply and 0.375 mV at 3 V.
3. 3-Wire Serial Interface.
4. Unbuffered Output Capable of Driving 60 kΩ Loads. This
reduces power consumption because there is no internal
buffer to drive.
5. Power-On Reset Circuitry.
AD5541/AD5542 Data Sheet
Rev. F | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Terminology .................................................................................... 10
Theory of Operation ...................................................................... 11
Digital-to-Analog Section ......................................................... 11
Serial Interface ............................................................................ 11
Unipolar Output Operation ...................................................... 11
Bipolar Output Operation ......................................................... 12
Output Amplifier Selection ....................................................... 12
Force Sense Amplifier Selection ............................................... 12
Reference and Ground ............................................................... 12
Power-On Reset .......................................................................... 13
Power Supply and Reference Bypassing .................................. 13
Microprocessor Interfacing ........................................................... 14
AD5541/AD5542 to ADSP-21xx Interface ............................. 14
AD5541/AD5542 to 68HC11/68L11 Interface....................... 14
AD5541/AD5542 to MICROWIRE Interface ........................ 14
AD5541/AD5542 to 80C51/80L51 Interface .......................... 14
Applications Information .............................................................. 15
Optocoupler Interface ................................................................ 15
Decoding Multiple AD5541/AD5542s .................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 17
REVISION HISTORY
3/12—Rev. E to Rev. F
Change to Figure 19 ......................................................................... 9
Changes to Ordering Guide .......................................................... 17
3/11—Rev. D to Rev. E
Changed +105°C to +85°C, General Description Section .......... 1
2/11—Rev. C to Rev. D
Changes to Features Section, General Description Section,
Product Highlights Section ............................................................. 1
Added Table 1; Renumbered Sequentially .................................... 1
Added Output Noise Spectral Density Parameter and Output
Noise Parameter, Table 2.................................................................. 3
Changes to Ordering Guide .......................................................... 17
4/10—Rev. B to Rev. C
Changes to General Description Section ...................................... 1
Changes to Features List .................................................................. 1
Changes to Product Highlights ....................................................... 1
Changes to Table 1 ............................................................................. 3
Changes to Table 3 ............................................................................. 5
Changes to Figure 16, Figure 17, and Figure 19 ....................... 8, 9
Changes to Theory of Operations Section .................................. 11
Changes to Microprocessor Interfacing Section ........................ 14
Changes to Outline Dimensions .................................................. 16
Changes to Ordering Guide .......................................................... 17
8/08—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Timing Characteristics Section ................................... 4
Changes to Table 3 ............................................................................. 5
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 17
10/99—Rev. 0 to Rev. A
Data Sheet AD5541/AD5542
Rev. F | Page 3 of 20
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
Min
Typ
Max
Unit
Test Conditions
STATIC PERFORMANCE
Resolution 16 Bits
Relative Accuracy (INL) ±0.5 ±1.0 LSB L, C grades
±0.5 ±2.0 LSB B, J grades
±0.5 ±4.0 LSB A grade
Differential Nonlinearity (DNL) ±0.5 ±1.0 LSB Guaranteed monotonic
±1.5
LSB
J grade
Gain Error +0.5 ±2 LSB TA = 25°C
±3 LSB
Gain Error Temperature Coefficient ±0.1 ppm/°C
Unipolar Zero Code Error ±0.3 ±0.7 LSB TA = 25°C
±1.5 LSB
Unipolar Zero Code Temperature Coefficient ±0.05 ppm/°C
AD5542
Bipolar Resistor Matching 1.000 Ω/Ω R
FB
/R
INV
, typically R
FB
= R
INV
= 28 kΩ
±0.0015 ±0.0076 % Ratio error
Bipolar Zero Offset Error ±1 ±5 LSB T
A
= 25°C
±6 LSB
Bipolar Zero Temperature Coefficient ±0.2 ppm/°C
Bipolar Zero Code Offset Error
±1
±5
LSB
TA = 25°C
±6 LSB
Bipolar Gain Error +1 ±5 LSB T
A
= 25°C
±6 LSB
Bipolar Gain Temperature Coefficient ±0.1 ppm/°C
OUTPUT CHARACTERISTICS
Output Voltage Range 0 V
REF
− 1 LSB V Unipolar operation
−V
REF
V
REF
− 1 LSB V AD5542 bipolar operation
Output Voltage Settling Time 1 μs To 1/2 LSB of FS, CL = 10 pF
Slew Rate 17 V/μs C
L
= 10 pF, measured from 0% to 63%
Digital-to-Analog Glitch Impulse 1.1 nV-sec 1 LSB change around the major carry
Digital Feedthrough 0.2 nV-sec All 1s loaded to DAC, VREF = 2.5 V
DAC Output Impedance
6.25
kΩ
Tolerance typically 20%
Output Noise Spectral Density 11.8 nV/√Hz DAC code = 0x8400, frequency = 1 kHz
Output Noise 0.134 µV p-p 0.1 Hz to 10 Hz
Power Supply Rejection Ratio ±1.0 LSB ΔV
DD
± 10%
DAC REFERENCE INPUT
Reference Input Range 2.0 VDD V
Reference Input Resistance
2
9 kΩ Unipolar operation
7.5 kΩ AD5542, bipolar operation
LOGIC INPUTS
Input Current ±1 μA
Input Low Voltage, V
INL
0.8 V
Input High Voltage, V
INH
2.4 V
Input Capacitance
3
10 pF
Hysteresis Voltage3 0.15 V
REFERENCE 3
Reference −3 dB Bandwidth 2.2 MHz All 1s loaded
Reference Feedthrough 1 mV p-p All 0s loaded, VREF = 1 V p-p at 100 kHz
Signal-to-Noise Ratio 92 dB
Reference Input Capacitance 26 pF Code 0x0000
26
pF
Code 0xFFFF
AD5541/AD5542 Data Sheet
Rev. F | Page 4 of 20
Parameter
1
Min Typ Max Unit Test Conditions
POWER REQUIREMENTS Digital inputs at rails
V
DD
2.7 5.5 V
I
DD
125 150 μA
Power Dissipation 0.625 0.825 mW
1 Temperature ranges are as follows: A, B, C versions: −40°C to +85°C; J, L versions: 0°C to 70°C.
2 Reference input resistance is code-dependent, minimum at 0x8555.
3 Guaranteed by design, not subject to production test.
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V ±10%, VREF = 2.5 V, VINH = 3 V and 90% of VDD, VINL = 0 V and 10% of VDD, AGND = DGND = 0 V; −40°C < TA <
+85°C, unless otherwise noted.
Table 3.
Parameter
1, 2
Limit
Unit Description
fSCLK
25
MHz max
SCLK cycle frequency
t
1
40 ns min SCLK cycle time
t
2
20 ns min SCLK high time
t
3
20 ns min SCLK low time
t
4
10 ns min CS low to SCLK high setup
t5 15 ns min CS high to SCLK high setup
t6 30 ns min SCLK high to CS low hold time
t7 20 ns min SCLK high to CS high hold time
t
8
15 ns min Data setup time
t
9
4 ns min Data hold time (V
INH
= 90% of V
DD
, V
INL
= 10% of V
DD
)
t
9
7.5 ns min Data hold time (V
INH
= 3V, V
INL
= 0 V)
t
10
30
ns min
LDAC
pulse width
t11 30 ns min CS high to LDAC low setup
t12 30 ns min CS high time between active periods
1 Guaranteed by design and characterization. Not production tested
2 All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.
SCLK
CS
DIN DB15
LDAC*
t6
t4
t12
t8t5
t2t3
t1
t7
t5
t11
t10
*AD5542 ONLY. CAN BE TI E D P E RM ANE NTLY LOW IF REQUIRED.
07557-003
Figure 3. Timing Diagram
Data Sheet AD5541/AD5542
Rev. F | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
V
DD
to AGND −0.3 V to +6 V
Digital Input Voltage to DGND −0.3 V to V
DD
+ 0.3 V
V
OUT
to AGND −0.3 V to V
DD
+ 0.3 V
AGND, AGNDF, AGNDS to DGND −0.3 V to +0.3 V
Input Current to Any Pin Except Supplies ±10 mA
Operating Temperature Range
Industrial (A, B, C Versions)
−40°C to +85°C
Commercial (J, L Versions) 0°C to 70°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature (T
J
max) 150°C
Package Power Dissipation (T
J
max – T
A
)/θ
JA
Thermal Impedance, θ
JA
SOIC (R-8) 149.5°C/W
SOIC (R-14) 104.5°C/W
Lead Temperature, Soldering
Peak Temperature1 260°C
ESD2 5 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1 As per JEDEC Standard 20.
2 HBM Classification.
AD5541/AD5542 Data Sheet
Rev. F | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
OUT 1
AGND
2
REF
3
CS
4
V
DD
8
DGND
7
DIN
6
SCLK
5
AD5541
TOP VIEW
(Not t o Scale)
07557-004
Figure 4. AD5541 Pin Configuration
Table 5. AD5541 Pin Function Descriptions
Pin No. Mnemonic Description
1 V
OUT
Analog Output Voltage from the DAC.
2 AGND Ground Reference Point for Analog Circuitry.
3 REF Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V
DD
.
4 CS Logic Input Signal. The chip select signal is used to frame the serial data input.
5 SCLK Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%.
6 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.
7
DGND
Digital Ground. Ground reference for digital circuitry.
8 V
DD
Analog Supply Voltage, 5 V ± 10%.
07557-005
RFB
1
V
OUT 2
AGNDF
3
AGNDS
4
V
DD
14
INV
13
DGND
12
LDAC
11
REFS
5
DIN
10
REFF
6
NC
9
CS
7
SCLK
8
NC = NO CONNECT
AD5542
TOP VIEW
(Not t o Scale)
Figure 5. AD5542 Pin Configuration
Table 6. AD5542 Pin Function Descriptions
Pin No. Mnemonic Description
1 RFB Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.
2 V
OUT
Analog Output Voltage from the DAC.
3
AGNDF
Ground Reference Point for Analog Circuitry (Force).
4 AGNDS Ground Reference Point for Analog Circuitry (Sense).
5 REFS Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V
DD
.
6 REFF Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V
DD
.
7 CS Logic Input Signal. The chip select signal is used to frame the serial data input.
8 SCLK Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%.
9 NC No Connect.
10 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.
11 LDAC LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the
input register.
12 DGND Digital Ground. Ground reference for digital circuitry.
13
INV
Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin to external op amps inverting input in
bipolar mode.
14 V
DD
Analog Supply Voltage, 5 V ± 10%.
Data Sheet AD5541/AD5542
Rev. F | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
0.50
0.25
0
–0.25
–0.50
–0.7508192 16384 24576 32768 40960 49152 57344 65536
CODE
INTEGRAL NONLINEARITY (LSB)
07557-006
V
DD
= 5V
V
REF
= 2.5V
Figure 6. Integral Nonlinearity vs. Code
0.25
0
–0.25
–0.50
–0.75
–1.00
–60 –40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
INTEGRAL NONLINEARITY (LSB)
07557-007
V
DD
= 5V
V
REF
= 2.5V
Figure 7. Integral Nonlinearity vs. Temperature
0.50
0.25
0
–0.25
–0.50
–0.752 3 4 5 6 7
SUPPLY VOLT AGE (V)
LINEARI TY E RROR (LSB)
07557-008
V
REF
= 2.5V
T
A
= 25° C
DNL
INL
Figure 8. Linearity Error vs. Supply Voltage
0.50
0.25
0
–0.25
–0.5008192 16384 24576 32768 40960 49152 57344 65536
CODE
DIFFERENTIAL NONLINEARITY (LSB)
07557-009
V
DD
= 5V
V
REF
= 2.5V
Figure 9. Differential Nonlinearity vs. Code
0.75
0.50
0.25
0
–0.25
–0.50
–60 –40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
DIFFERENTIAL NONLINEARITY (LSB)
07557-010
V
DD
= 5V
V
REF
= 2.5V
Figure 10. Differential Nonlinearity vs. Temperature
0.75
0.50
0.25
0
–0.25
–0.500 1 2 3 4 5 6
REFERENCE VOLT AGE (V)
LINEARI TY E RROR (LSB)
07557-011
V
DD
= 5V
T
A
= 25° C
DNL
INL
Figure 11. Linearity Error vs. Reference Voltage
AD5541/AD5542 Data Sheet
Rev. F | Page 8 of 20
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–40 25 85
TEMPERATURE (°C)
GAIN ERROR (LSB)
V
DD
= 5V
V
REF
= 2.5V
T
A
= 25°C
08898-012
Figure 12. Gain Error vs. Temperature
132
116
118
120
122
124
126
128
130
–40 25 85
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
V
DD
= 5V
V
REF
= 2.5V
T
A
= 25°C
08898-013
Figure 13. Supply Current vs. Temperature
200
0
20
40
60
80
100
120
140
160
180
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
DIGITAL INPUT VOLTAGE (V)
SUPPLY CURRENT (µV)
08898-014
Figure 14. Supply Current vs. Digital Input Voltage
0.15
–0.15
–0.10
–0.05
0
0.05
0.10
–40 25 85
TEMPERATURE (°C)
ZERO-CODE ERROR (LSB)
V
DD
= 5V
V
REF
= 2.5V
T
A
= 25°C
08898-015
Figure 15. Zero-Code Error vs. Temperature
08898-016
0
0.5
1.0
1.5
2.0
0123456
SUPPLY CURRENT (µA)
VOLTAGE (V)
REFERENCE VOLTAGE
V
DD
= 5V
SUPPLY VOLTAGE
V
REF
= 2.5V
T
A
= 25°C
Figure 16. Supply Current vs. Reference Voltage or Supply Voltage
200
150
100
50
0
0 70,00060,00050,00040,00030,00020,00010,000
CODE (Decimal)
REFERENCE CURRENT (µA)
V
DD
= 5V
V
REF
= 2.5V
T
A
= 25°C
08898-017
Figure 17. Reference Current vs. Code
Data Sheet AD5541/AD5542
Rev. F | Page 9 of 20
2µs/DIV
VREF = 2. 5V
VDD = 5V
TA = 25° C
DIN ( 5V /DIV )
VOUT (50mV/DI V )
100
10
08898-018
Figure 18. Digital Feedthrough
VOLTAGE (V)
1.236
1.234
1.232
1.230
1.228
1.226
1.224
–0.5 00.5 1.0 1.5 2.0
5
0
–5
–10
–15
–20
–25
–30
TIME (µs)
V
OUT
CS
07557-032
Figure 19. Digital-to-Analog Glitch Impulse
2µs/DIV V
REF
= 2.5V
V
DD
= 5V
T
A
= 25° C
200pF
10pF
50pF
100pF
100
10
CS (5V/DIV)
V
OUT
(0.5V /DI V )
08898-020
Figure 20. Large Signal Settling Time
07557-021
• • • •• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
• • • •• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
0.5µs/DIV
VREF = 2. 5V
VDD = 5V
TA = 25° C
100
90
10
0%
VOUT (1V/DIV)
VOUT (50mV/DI V )
GAI N = –216
1LSB = 8.2mV
Figure 21. Small Signal Settling Time
AD5541/AD5542 Data Sheet
Rev. F | Page 10 of 20
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or INL is a measure of the
maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function. A typical
INL vs. code plot can be seen in Figure 6.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures mono-
tonicity. Figure 9 illustrates a typical DNL vs. code plot.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range.
It is the deviation in slope of the DAC transfer characteristic
from ideal.
Gain Error Temperature Coefficient
Gain error temperature coefficient is a measure of the change
in gain error with changes in temperature. It is expressed in
ppm/°C.
Zero Code Error
Zero code error is a measure of the output error when zero code
is loaded to the DAC register.
Zero Code Temperature Coefficient
This is a measure of the change in zero code error with a change
in temperature. It is expressed in mV/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by
1 LSB at the major carry transition. A plot of the digital-to-
analog glitch impulse is shown in Figure 19.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but it is measured when the DAC output is not updated.
CS is held high while the CLK and DIN signals are toggled. It
is specified in nV-sec and is measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice
versa. A typical plot of digital feedthrough is shown in
Figure 18.
Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the power supply voltage. Power-supply rejection ratio is
quoted in terms of percent change in output per percent change
in VDD for full-scale output of the DAC. VDD is varied by ±10%.
Reference Feedthrough
Reference feedthrough is a measure of the feedthrough from the
VREF input to the DAC output when the DAC is loaded with all
0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough
is expressed in mV p-p.
Data Sheet AD5541/AD5542
Rev. F | Page 11 of 20
THEORY OF OPERATION
The AD5541/AD5542 are single, 16-bit, serial input, voltage
output DACs. They operate from a single supply ranging from
2.7 V to 5.5 V and consume typically 125 µA with a supply of
5 V. Data is written to these devices in a 16-bit word format,
via a 3- or 4-wire serial interface. To ensure a known power-up
state, these parts are designed with a power-on reset function.
In unipolar mode, the output is reset to 0 V; in bipolar mode,
the AD5542 output is set to −VREF. Kelvin sense connections for
the reference and analog ground are included on the AD5542.
DIGITAL-TO-ANALOG SECTION
The DAC architecture consists of two matched DAC sections.
A simplified circuit diagram is shown in Figure 22. The DAC
architecture of the AD5541/AD5542 is segmented. The four
MSBs of the 16-bit data-word are decoded to drive 15 switches,
E1 to E15. Each switch connects one of 15 matched resistors to
either AGND or VREF. The remaining 12 bits of the data-word
drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder
network.
2R . . . . .
S1 . . . . .
2R
S11
2R
E1
2R . . . . .
E2 . . . . .
2R 2R
S0
2R
E15
R R
V
REF
V
OUT
12-BI T R-2R L ADDE R FOUR MS Bs DE CODED
INTO 15 EQUAL SEGMENTS
07557-022
Figure 22. DAC Architecture
With this type of DAC configuration, the output impedance
is independent of code, while the input impedance seen by
the reference is heavily code dependent. The output voltage is
dependent on the reference voltage, as shown in the following
equation:
N
REF
OUT
DV
V2
×
=
where:
D is the decimal data-word loaded to the DAC register.
N is the resolution of the DAC.
For a reference of 2.5 V, the equation simplifies to the following:
536,65
5.2 D
V
OUT
×
=
This gives a VOUT of 1.25 V with midscale loaded and 2.5 V with
full-scale loaded to the DAC.
The LSB size is VREF/65,536.
SERIAL INTERFACE
The AD5541/AD5542 are controlled by a versatile 3- or 4-wire
serial interface that operates at clock rates up to 25 MHz and is
compatible with SPI, QSPI, MICROWIRE, and DSP interface
standards. The timing diagram is shown in Figure 3. Input data
is framed by the chip select input, CS. After a high-to-low
transition on CS, data is shifted synchronously and latched into
the input register on the rising edge of the serial clock, SCLK.
Data is loaded MSB first in 16-bit words. After 16 data bits have
been loaded into the serial input register, a low-to-high transition
on CS transfers the contents of the shift register to the DAC. Data
can be loaded to the part only while CS is low.
The AD5542 has an LDAC function that allows the DAC latch
to be updated asynchronously by bringing LDAC low after CS
goes high. LDAC should be maintained high while data is written
to the shift register. Alternatively, LDAC can be tied perma-
nently low to update the DAC synchronously. With LDAC tied
permanently low, the rising edge of CS loads the data to the DAC.
UNIPOLAR OUTPUT OPERATION
These DACs are capable of driving unbuffered loads of 60 kΩ.
Unbuffered operation results in low supply current, typically
300 μA, and a low offset error. The AD5541 provides a unipolar
output swing ranging from 0 V to VREF. The AD5542 can be
configured to output both unipolar and bipolar voltages. Figure 23
shows a typical unipolar output voltage circuit. The code table
for this mode of operation is shown in Table 7.
07557-023
OUT
REFS*REF(REFF*)
DGND AGND
V
DD
DIN
SCLK
LDAC*
CS
AD5541/AD5542
AD820/
OP196
+
0.1µF0.1µF
10µF
UNIPOLAR
OUTPUT
EXTERNAL
OPAMP
2.5V
5V
SERIAL
INTERFACE
*AD5542 ONLY.
Figure 23. Unipolar Output
Table 7. Unipolar Code Table
DAC Latch Contents
MSB LSB Analog Output
1111 1111 1111 1111 V
REF
× (65,535/65,536)
1000 0000 0000 0000 V
REF
× (32,768/65,536) = ½ V
REF
0000 0000 0000 0001 V
REF
× (1/65,536)
0000 0000 0000 0000 0 V
AD5541/AD5542 Data Sheet
Rev. F | Page 12 of 20
Assuming a perfect reference, the unipolar worst-case output
voltage can be calculated from the following equation:
VOUT-UNI
( )
INLVVV
D
ZSE
GE
REF
+++×=
16
2
where:
VOUT−UNI is unipolar mode worst-case output.
D is code loaded to DAC.
VREF is reference voltage applied to the part.
VGE is gain error in volts.
VZSE is zero scale error in volts.
INL is integral nonlinearity in volts.
BIPOLAR OUTPUT OPERATION
With the aid of an external op amp, the AD5542 can be confi-
gured to provide a bipolar voltage output. A typical circuit of
such operation is shown in Figure 24. The matched bipolar
offset resistors, RFB and RINV, are connected to an external op
amp to achieve this bipolar output swing, typically RFB = RINV =
28 kΩ. Table 8 shows the transfer function for this output
operating mode. Also provided on the AD5542 are a set of
Kelvin connections to the analog ground inputs.
07557-024
OUT
REFSREFF
INV
R
FB
R
INV
DGND AGNDF
V
DD
DIN
SCLK
LDAC
CS
AD5541/AD5542
AGNDS
+
0.1µF0.1µF
10µF
UNIPOLAR
OUTPUT
EXTERNAL
OP AMP
+2.5V
+5V
+5V
–5V
SERIAL
INTERFACE
RFB
Figure 24. Bipolar Output (AD5542 Only)
Table 8. Bipolar Code Table
DAC Latch Contents
MSB LSB Analog Output
1111 1111 1111 1111 +V
REF
× (32,767/32,768)
1000 0000 0000 0001 +V
REF
× (1/32,768)
1000 0000 0000 0000 0 V
0111 1111 1111 1111 −V
REF
× (1/32,768)
0000 0000 0000 0000 −V
REF
× (32,768/32,768) = −V
REF
Assuming a perfect reference, the worst-case bipolar output
voltage can be calculated from the following equation:
VOUT-BIP
( )
( ) ( )
[ ]
( )
A
RD
RDVRDVV REF
OS
UNIOUT
++
+−++
=−
21
12
where:
VOUT-BIP is the bipolar mode worst-case output.
VOUT−UNI is the unipolar mode worst-case output.
VOS is the external op amp input offset voltage.
RD is the RFB and RINV resistor matching error.
A is the op amp open-loop gain.
OUTPUT AMPLIFIER SELECTION
For bipolar mode, a precision amplifier should be used and
supplied from a dual power supply. This provides the ±VREF
output. In a single-supply application, selection of a suitable op
amp may be more difficult as the output swing of the amplifier
does not usually include the negative rail, in this case, AGND.
This can result in some degradation of the specified performance
unless the application does not use codes near zero.
The selected op amp needs to have a very low-offset voltage (the
DAC LSB is 38 μV with a 2.5 V reference) to eliminate the need
for output offset trims. Input bias current should also be very
low because the bias current, multiplied by the DAC output
impedance (approximately 6 kΩ), adds to the zero code error.
Rail-to-rail input and output performance is required. For fast
settling, the slew rate of the op amp should not impede the
settling time of the DAC. Output impedance of the DAC is
constant and code-independent, but to minimize gain errors,
the input impedance of the output amplifier should be as high
as possible. The amplifier should also have a 3 dB bandwidth of
1 MHz or greater. The amplifier adds another time constant to
the system, hence increasing the settling time of the output. A
higher 3 dB amplifier bandwidth results in a shorter effective
settling time of the combined DAC and amplifier.
FORCE SENSE AMPLIFIER SELECTION
Use single-supply, low-noise amplifiers. A low-output impedance
at high frequencies is preferred because the amplifiers need to
be able to handle dynamic currents of up to ±20 mA.
REFERENCE AND GROUND
Because the input impedance is code-dependent, the reference
pin should be driven from a low impedance source. The AD5541/
AD5542 operate with a voltage reference ranging from 2 V to
VDD. References below 2 V result in reduced accuracy. The full-
scale output voltage of the DAC is determined by the reference.
Table 7 and Table 8 outline the analog output voltage or partic-
ular digital codes. For optimum performance, Kelvin sense
connections are provided on the AD5542.
If the application does not require separate force and sense
lines, tie the lines close to the package to minimize voltage
drops between the package leads and the internal die.
Data Sheet AD5541/AD5542
Rev. F | Page 13 of 20
POWER-ON RESET
The AD5541/AD5542 have a power-on reset function to ensure
that the output is at a known state on power-up. On power-up,
the DAC register contains all 0s until the data is loaded from
the serial register. However, the serial register is not cleared on
power-up, so its contents are undefined. When loading data
initially to the DAC, 16 bits or more should be loaded to prevent
erroneous data appearing on the output. If more than 16 bits are
loaded, the last 16 are kept, and if less than 16 bits are loaded,
bits remain from the previous word. If the AD5541/AD5542
need to be interfaced with data shorter than 16 bits, the data
should be padded with 0s at the LSBs.
POWER SUPPLY AND REFERENCE BYPASSING
For accurate high-resolution performance, it is recommended
that the reference and supply pins be bypassed with a 10 μF
tantalum capacitor in parallel with a 0.1 μF ceramic capacitor.
AD5541/AD5542 Data Sheet
Rev. F | Page 14 of 20
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5541/AD5542 is via a
serial bus that uses standard protocol that is compatible with
DSP processors and microcontrollers. The communications
channel requires a 3- or 4-wire interface consisting of a clock
signal, a data signal and a synchronization signal. The
AD5541/AD5542 require a 16-bit data-word with data valid on
the rising edge of SCLK. The DAC update can be done
automatically when all the data is clocked in or it can be done
under control of the LDAC (AD5542 only).
AD5541/AD5542 TO ADSP-21XX INTERFACE
Figure 25 shows a serial interface between the AD5541/AD5542
and the ADSP-21xx. The ADSP-21xx should be set to operate in
the SPORT transmit alternate framing mode. The ADSP-21xx are
programmed through the SPORT control register and should be
configured as follows: internal clock operation, active low
framing, 16-bit word length. Transmission is initiated by
writing a word to the Tx register after the SPORT has been
enabled. As the data is clocked out on each rising edge of the
serial clock, an inverter is required between the DSP and the
DAC, because the AD5541/AD5542 clock data in on the falling
edge of the SCLK.
LDAC**
CS
DIN
SCLK
FO
TFS
DT
SCLK
AD5541/
AD5542*
ADSP-21xx
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5542 ONLY.
07557-025
Figure 25. AD5541/AD5542 to ADSP-21xx Interface
AD5541/AD5542 TO 68HC11/68L11 INTERFACE
Figure 26 shows a serial interface between the AD5541/AD5542
and the 68HC11/68L11 microcontroller. SCK of the 68HC11/
68L11 drives the SCLK of the DAC, and the MOSI output drives
the serial data line serial DIN. The CS signal is driven from one
of the port lines. The 68HC11/68L11 is configured for master
mode: MSTR = 1, CPOL = 0, and CPHA = 0. Data appearing
on the MOSI output is valid on the rising edge of SCK.
LDAC**
CS
DIN
SCLK
PC6
PC7
MOSI
SCK
AD5541/
AD5542*
68HC11/
68L11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5542 ONLY.
07557-026
Figure 26. AD5541/AD5542 to 68HC11/68L11 Interface
AD5541/AD5542 TO MICROWIRE INTERFACE
Figure 27 shows an interface between the AD5541/AD5542
and any MICROWIRE-compatible device. Serial data is shifted
out on the falling edge of the serial clock and into the AD5541/
AD5542 on the rising edge of the serial clock. No glue logic is
required because the DAC clocks data into the input shift
register on the rising edge.
DIN
SCLK
SO
SCLK
AD5541/
AD5542*
MICROWIRE*
*ADDITIONAL PINS OMITTED FOR CLARITY.
07557-027
CSCS
Figure 27. AD5541/AD5542 to MICROWIRE Interface
AD5541/AD5542 TO 80C51/80L51 INTERFACE
A serial interface between the AD5541/AD5542 and the 80C51/
80L51 microcontroller is shown in Figure 28. TxD of the micro-
controller drives the SCLK of the AD5541/AD5542, and RxD
drives the serial data line of the DAC. P3.3 is a bit programmable
pin on the serial port that is used to drive CS.
The 80C51/80L51 provide the LSB first, whereas the AD5541/
AD5542 expects the MSB of the 16-bit word first. Care should
be taken to ensure the transmit routine takes this into account.
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is valid on the falling edge of TxD, so the clock
must be inverted as the DAC clocks data into the input shift
register on the rising edge of the serial clock. The 80C51/80L51
transmit data in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. As the DAC requires a 16-bit
word, P3.3 must be left low after the first eight bits are transferred,
and brought high after the second byte is transferred. LDAC on
the AD5542 can also be controlled by the 80C51/ 80L51 serial
port output by using another bit programmable pin, P3.4.
LDAC**
CS
DIN
SCLK
P3.4
P3.3
RxD
TxD
AD5541/
AD5542*
80C51/
80L51*
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5542 ONLY.
07557-028
Figure 28. AD5541/AD5542 to 80C51/80L51 Interface
Data Sheet AD5541/AD5542
Rev. F | Page 15 of 20
APPLICATIONS INFORMATION
OPTOCOUPLER INTERFACE
The digital inputs of the AD5541/AD5542 are Schmitt-triggered so
that they can accept slow transitions on the digital input lines.
This makes these parts ideal for industrial applications where it
may be necessary to isolate the DAC from the controller via
optocouplers. Figure 29 illustrates such an interface.
10kΩ
10µF 0.1µF
VDD
VOUT
VDD
SCLK
POWER
10kΩ
VDD
CS CS
DIN GND
SCLK
10kΩ
VDD
DIN
5V
REGULATOR
AD5541/AD5542
07557-029
Figure 29. AD5541/AD5542 in an Optocoupler Interface
DECODING MULTIPLE AD5541/AD5542s
The CS pin of the AD5541/AD5542 can be used to select one of
a number of DACs. All devices receive the same serial clock and
serial data, but only one device receives the CS signal at any one
time. The DAC addressed is determined by the decoder. There is
some digital feedthrough from the digital input lines. Using a
burst clock minimizes the effects of digital feedthrough on the
analog signal channels. Figure 30 shows a typical circuit.
AD5541/AD5542
CS
DIN
SCLK
VOUT
AD5541/AD5542
CS
DIN
SCLK
VOUT
AD5541/AD5542
CS
DIN
SCLK
VOUT
AD5541/AD5542
CS
DIN
SCLK
VOUT
V
DD
DGND
EN
CODED
ADDRESS
SCLK
DIN
ENABLE
DECODER
07557-030
Figure 30. Addressing Multiple AD5541/AD5542s
AD5541/AD5542 Data Sheet
Rev. F | Page 16 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 31. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONSARE I N M IL LI M E TERS ; INCH DI M E NS IO NS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REF E RE NCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JE DE C S TANDARDS MS-012-AB
060606-A
14 8
7
1
6.20 ( 0.2441)
5.80 ( 0.2283)
4.00 ( 0.1575)
3.80 ( 0.1496)
8.75 ( 0.3445)
8.55 ( 0.3366)
1.27 ( 0.0500)
BSC
SEATING
PLANE
0.25 ( 0.0098)
0.10 ( 0.0039)
0.51 ( 0.0201)
0.31 ( 0.0122)
1.75 ( 0.0689)
1.35 ( 0.0531)
0.50 ( 0.0197)
0.25 ( 0.0098)
1.27 ( 0.0500)
0.40 ( 0.0157)
0.25 ( 0.0098)
0.17 ( 0.0067)
COPLANARITY
0.10
8°
0°
45°
Figure 32. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
Data Sheet AD5541/AD5542
Rev. F | Page 17 of 20
ORDERING GUIDE
Model1
INL
DNL
Temperature Range
Package Description
Package Option
AD5541CR ±1 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8
AD5541CRZ ±1 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8
AD5541CRZ-REEL7 ±1 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8
AD5541LR ±1 LSB ±1 LSB 0°C to 70°C 8-Lead SOIC_N R-8
AD5541LR-REEL7 ±1 LSB ±1 LSB 0°C to 70°C 8-Lead SOIC_N R-8
AD5541LRZ ±1 LSB ±1 LSB 0°C to 70°C 8-Lead SOIC_N R-8
AD5541LRZ-REEL7 ±1 LSB ±1 LSB 0°C to 70°C 8-Lead SOIC_N R-8
AD5541BR ±2 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8
AD5541BRZ ±2 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8
AD5541BRZ-REEL ±2 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8
AD5541JR ±2 LSB ±1.5 LSB 0°C to 70°C 8-Lead SOIC_N R-8
AD5541JR-REEL7 ±2 LSB ±1.5 LSB 0°C to 70°C 8-Lead SOIC_N R-8
AD5541JRZ
±2 LSB
±1.5 LSB
0°C to 70°C
8-Lead SOIC_N
R-8
AD5541JRZ-REEL7 ±2 LSB ±1.5 LSB 0°C to 70°C 8-Lead SOIC_N R-8
AD5541AR ±4 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8
AD5541AR-REEL7 ±4 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8
AD5541ARZ ±4 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8
AD5541ARZ-REEL7 ±4 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8
AD5542CR ±1 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14
AD5542CR-REEL7 ±1 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14
AD5542CRZ ±1 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14
AD5542CRZ-REEL7 ±1 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14
AD5542LR ±1 LSB ±1 LSB 0°C to 70°C 14-Lead SOIC_N R-14
AD5542LRZ ±1 LSB ±1 LSB 0°C to 70°C 14-Lead SOIC_N R-14
AD5542BR ±2 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14
AD5542BRZ ±2 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14
AD5542BRZ-REEL7
±2 LSB
±1 LSB
−40°C to +85°C
14-Lead SOIC_N
R-14
AD5542JR ±2 LSB ±1.5 LSB 0°C to 70°C 14-Lead SOIC_N R-14
AD5542JR-REEL7 ±2 LSB ±1.5 LSB 0°C to 70°C 14-Lead SOIC_N R-14
AD5542JRZ ±2 LSB ±1.5 LSB 0°C to 70°C 14-Lead SOIC_N R-14
AD5542JRZ-REEL7 ±2 LSB ±1.5 LSB 0°C to 70°C 14-Lead SOIC_N R-14
AD5542AR ±4 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14
AD5542AR-REEL7 ±4 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14
AD5542ARZ ±4 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14
AD5542ARZ-REEL7 ±4 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14
EVAL-AD5541/42EBZ Evaluation Board
1 Z = RoHS Compliant Part.
AD5541/AD5542 Data Sheet
Rev. F | Page 18 of 20
NOTES
Data Sheet AD5541/AD5542
Rev. F | Page 19 of 20
NOTES
AD5541/AD5542 Data Sheet
Rev. F | Page 20 of 20
NOTES
©1999–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07557-0-3/12(F)
