5962-9669005HUA - Micross Components, Inc.

FLASH

AS29F010

Micross Components reserves the right to change products or speciﬁ cations without notice.

AS29F010

Rev. 2.4 01/10

128K x 8 FLASH

UNIFORM SECTOR 5.0V FLASH MEMO-

AVAILABLE AS MILITAR Y

SPECIFICATIONS

• MIL-STD-883

• SMD 5962-96690

FEATURES

• Single 5.0V ±10% power supply operation

• Low power consumption:

3 12 mA typical active read current

3 30 mA typical program/erase current

3 <1 μA typical standby current

• Flexible sector architecture

3 Eight 16Kbyte sectors

3 Any combination of sectors can be erased

3 Full chip erase

• Sector protection

3 Hardware-based feature that disables/reenables program

and erase operations in any combination of sectors

3 Sector protection/unprotection can be implemented

using standard PROM programming equipment

• Embedded Algorithms

3 Embedded Erase algorithm automatically pre-programs

and erases the chip or any combination of designated

sectors

3 Embedded Program algorithm automatically programs

and veriﬁ es data at speciﬁ ed address

• Erase Suspend/Resume

3 Supports reading data from a sector not being erased

• Minimum 1,000,000 Program/Erase Cycles per sector

guaranteed

• Compatible with JEDEC standards

3 Pinout and software compatible with single-power-

supply FLASH

3 Superior inadvertent write protection

• Data\ Polling and Toggle Bits

3 Provides a software method of detecting program or

erase cycle completion

OPTIONS MARKING

• Timing

50ns* -50

60ns -60

70ns -70

90ns -90

120ns -120

150ns -150

• Package

Ceramic DIP (600 mil) CW

Flatpack F

Lead Formed Flatpack DCG

Small Outline J-Lead SOJ

• Temperature

Industrial Temperature (-40°C to +85°C) IT

Military Temperature (-55°C to +125°C) XT

883C Processing (-55°C to +125°C) 883C

QML Processing (-55°C to +125°C) Q

NOTES: *50ns (-50) option available with IT and XT options only.

For more products and information

please visit our web site at

www.micross.com

PIN ASSIGNMENT

(Top View)

32-PIN Ceramic DIP (CW)

32-pin Flatpack (F)

32-pin Lead Formed Flatpack (DCG)

A16

A15

A12

DQ0

DQ1

DQ2

VSS

VCC

WE\

A14

A13

A11

OE\

A10

CE\

DQ7

DQ6

DQ5

DQ4

DQ3

FLASH

AS29F010

Micross Components reserves the right to change products or speciﬁ cations without notice.

AS29F010

Rev. 2.4 01/10

GENERAL DESCRIPTION

The AS29F010 is a 1Mbit, 5.0 Volt-only FLASH memory

organized as 131,072 bytes. The AS29F010 is offered in a 32-

pin CDIP package. The byte-wide data appears on DQ0-DQ7.

The device is designed to be programmed in-system with the

standard system 5.0 Volt VCC supply. A 12.0 volt VPP is not

required for program or erase operations. The device can also

be programmed or erased in standard EPROM programmers.

This device is manufactured using 0.32 μm process

technology. It is available with access times of 50, 60, 70,

90, 120, and 150ns, allowing high-speed microprocessors to

operate without wait states. To eliminate bus contention the

device has separate chip enable (CE\), write enable (WE\), and

output enable (OE\) controls.

The device requires only a single 5.0 volt power supply

for both read and write functions. Internally generated and

regulated voltages are provided for the program and erase

operations.

The device is entirely command set compatible with the

JEDEC single-power-supply FLASH standard. Commands are

written to the command register using standard microprocessor

write timings. Register contents serve as input to an internal

state machine that controls the erase and programming circuitry.

Write cycles also internally latch addresses and data needed for

the programming and erase operations. Reading data out of

the device is similar to reading from other FLASH or EPROM

devices.

Device programming occurs by executing the program

command sequence. This invokes the Embedded Program

algorithm -- an internal algorithm that automatically times the

program pulse widths and veriﬁ es proper cell margin.

Device erasure occurs by executing the erase command

sequence. This invokes the Embedded Erase algorithm -- an

internal algorithm that automatically preprograms the array

(if it is not already programmed) before executing the erase

operation. During erase, the device automatically times the

erase pulse widths and veriﬁ es proper cell margin.

The host system can detect whether a program or erase

operation is complete by reading the DQ7 (Data\Polling) and

DQ6 (toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data or accept

another command.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data contents

of other sectors. The device is erased when shipped from the

factory.

The hardware data protection measures include a low

VCC detector that automatically inhibits write operations dur-

ing power transitions. The hardware sector protection feature

disables both program and erase operations in any combination

of the sectors of memory, and is implemented using standard

EPROM programmers.

The system can place the device into the standby mode.

Power consumption is greatly reduced in this mode. The

device electrically erases all bits within a sector simultaneously

via Fowler-Nordheim tunneling. The bytes are programmed

one byte at a time using the EPROM programming mechanism

of hot electron injection.

PIN CONFIGURATION

PIN DESCRIPTION

A0 - A16 17 Addresses

DQ0 - DQ7 8 Data Inputs/Outputs

CE\ Chip Enable

OE\ Output Enable

WE\ Write Enable

VCC +5 Volt Single Power Supply

VSS Device Ground

NC No Connect

LOGIC SYMBOL

FLASH

AS29F010

Micross Components reserves the right to change products or speciﬁ cations without notice.

AS29F010

Rev. 2.4 01/10

FUNCTIONAL BLOCK DIAGRAM

FLASH

AS29F010

Micross Components reserves the right to change products or speciﬁ cations without notice.

AS29F010

Rev. 2.4 01/10

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the inter-

nal command register. The command register itself does not

occupy any addressable memory location. The register is

composed of latches that store the commands, along with the

address and data information needed to execute the command.

The contents of the register serve as inputs to the internal state

machine. The state machine outputs dictate the function of

the device. The appropriate device bus operations table lists

the inputs and control levels required, and the resulting output.

The following subsections describe each of these operations in

further detail.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive

the CE\ and OE\ pins to VIL. CE\ is the power control and

selects the device. OE\ is the output control and gates array

data to the output pins. WE\ should remain at VIH.

The internal state machine is set for reading array data upon

device power-up, or after a hardware reset. This ensures that

no spurious alteration of the memory content occurs during

the power transition. No command is necessary in this mode

to obtain array data. Standard microprocessor read cycles that

assert valid addresses on the device address inputs produce

valid data on the device data outputs. The device remains en-

abled for read access until the command register contents are

altered.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing speciﬁ cations and

to the Read Operations Timings diagram for the timing wave-

forms. ICC1 in the DC Characteristics table represents the

active current speciﬁ cation for reading array data.

TABLE 1: DEVICE BUS OPERATIONS

OPERATION CE\ OE\ WE\ Addresses

DQ0 - DQ7

Read L L H A

OUT

Write L H L A

Standby V

± 0.5V X X X High-Z

Output Disable L H H X High-Z

Hardware Reset X X X X High-Z

NOTES:

1. Addresses are A16:A0.

2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Protection/Unprotection” section.

Writing Commands/Command Sequences

To write a command or command sequence (which includes

programming data to the device and erasing sectors of memory),

the system must drive WE\ and CE\ to VIL, and OE\ to VIH.

An erase operation can erase one sector, multiple sectors,

or the entire device. The Sector Address Tables indicate the

address space that each sector occupies. A “sector address” con-

sists of the address bits required to uniquely select a sector.

See the “Command Deﬁ nitions” section for details on erasing

a sector or the entire chip.

After the system writes the autoselect command sequence,

the device enters the autoselect mode. The system can then read

autoselect codes from the internal register (which is separate

from the memory array) on DQ7 - DQ0. Standard read cycle

timings apply in this mode. Refer to the “Autoselect Mode”

and “Autoselect Command Sequence” sections for more infor-

mation.

CC2 in the DC Characteristics table represents the active

current speciﬁ cation for the write mode. The “AC Character-

istics” section contains timing speciﬁ cation tables and timing

diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status bits

on DQ7 - DQ0. Standard read cycle timings and ICC read

speciﬁ cations apply. Refer to “Write Operation Status” for

more information, and to each AC Characteristics section in

the appropriate data sheet for timing diagrams.

FLASH

AS29F010

Micross Components reserves the right to change products or speciﬁ cations without notice.

AS29F010

Rev. 2.4 01/10

Standby Mode

When the system is not reading or writing to the device, it

can place the device in the standby mode. In this mode, current

consumption is greatly reduced, and the outputs are placed in

the high impedance state, independent of the OE\ input.

The device enters the CMOS standby mode when the CE\

pin is held at VCC ± 0.5V. (Note that this is a more restricted

voltage range than VIH.) The device enters the TTL standby

more when CE\ is held at VIH. The device requires the standard

access time (tCE) before it is ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the operation is

completed.

CC3 in the DC Characteristics table represents the standby

current speciﬁ cation.

Output Disable Mode

When the OE\ input is at VIH, output from the device is

disabled. The output pins are placed in the high impedance

state.

Autoselect Mode

The autoselect mode provides manufacturer and device

identification, and sector protection verification, through

identiﬁ er codes output on DQ7 - DQ0. This mode is primarily

intended for programming equipment to automatically match a

device to be programmed with its corresponding programming

algorithm. However, the autoselect codes can also be accessed

in-system through the command register.

When using programming equipment, the autoselect mode

requires VID on address pin A9. Address pins A6, A1, and

A0 must be as shown in the Autoselect Codes (High Voltage

Method) table. In addition, when verifying sector protection,

the sector address must appear on the appropriate highest

order address bits. Refer to the corresponding Sector Address

SECTOR A16 A15 A14 ADDRESS RANGE

SA0 0 0 0 00000h - 03FFFh

SA1 0 0 1 04000h - 07FFFh

SA2 0 1 0 08000h - 0BFFFh

SA3 0 1 1 0C000h - 0FFFFh

SA4 1 0 0 10000h - 13FFFh

SA5 1 0 1 14000h - 17FFFh

SA6 1 1 0 18000h - 1BFFFh

SA7 1 1 1 1C000h - 1FFFFh

TABLE 2: SECTOR ADDRESSES TABLE

NOTE: All sectors are 16 Kbytes in size.

Tables. The Command Deﬁ nitions table shows the remaining

address bits that are don’t care. When all necessary bits have

been set as required, the programming equipment may then

read the corresponding identiﬁ er code on DQ7 - DQ0

To access the autoselect codes in-system, the host system

can issue the autoselect command via the command register, as

shown in the Command Deﬁ nitions table. This method does

not require VID. See “Command Deﬁ nitions” for details on

using the autoselect mode.

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The hardware

sector unprotection feature re-enables both program and erase

operations in previously protected sectors.

Sector protection/unprotection must be implemented us-

ing programming equipment. The procedure requires a high

voltage (VID) on address pin A9 and the control pins. The

device is shipped with all sectors unprotected. It is possible

to determine whether a sector is protected or unprotected. See

“Autoselect Mode” for details.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection against

inadvertent writes (refer to the Command Deﬁ nitions table).

In addition, the following hardware data protection measures

prevent accidental erasure or programming, which might

otherwise be caused by spurious system level signals during

VCC power-up and power-down transitions, or from system

noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept

any write cycles. This protects data during VCC power-up and

FLASH

AS29F010

Micross Components reserves the right to change products or speciﬁ cations without notice.

AS29F010

Rev. 2.4 01/10

power-down. The command register and all internal program/

erase circuits are disabled, and the device resets. Subsequent

writes are ignored until VCC is greater than VLKO. The system

must provide the proper signals to the control pins to prevent

unintentional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5ns (typical) on OE\, CE\, or WE\

do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE\ =

VIL, CE\ = VIH or WE\ = VIH. To initiate a write cycle, CE\

and WE\ must be a logical zero while OE\ is a logical one.

Power -Up W rite Inhibit

If WE\ = CE\ = VIL and OE\ = VIH during power up, the

device does not accept commands on the rising edge of WE\.

The internal state machine is automatically reset to reading

array data on power-up.

COMMAND DEFINITIONS

Writing speciﬁ c address and data commands or sequences

into the command register initiates device operations. The

Command Deﬁ nitions table deﬁ nes the valid register com-

mand sequences. Writing incorrect address and data values

or writing them in the impr oper sequence resets the device

to reading array data.

All addresses are latched on the falling edge of WE\ or

CE\, whichever happens ﬁ rst. Refer to the appropriate timing

diagrams in the “AC Characteristics” section.

TABLE 3: Autoselect Codes (High Voltage Method)

DESCRIPTION CE\ OE\ WE\ A16 to

A14

A13 to

A10 A9

A1 A0 DQ7 to DQ0

Manufacturer ID L L H X X VID XLXLL 01h

Device ID L L H X X VID XLXLH 20h

01h

(protected)

00h

(unprotected)

LXHLSA X VID X

Sector Protection

Verification LLH

NOTE: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t Care

Reading Array Data

The device is automatically set to reading array data after

device power-up. No commands are required to retrieve data.

The device is also ready to read array data after completing an

Embedded Program or Embedded Erase algorithm.

The system must issue the reset command to re-enable the

device for reading array data if DQ5 goes high, or while in the

autoselect mode. See the “Reset Command” section, next.

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information. The

Read Operations table provides the read parameters, and the

Read Operation Timings diagram shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to

reading array data. Address bits are don’t care for this com-

mand.

The reset command may be written between the sequence

cycles in an erase command sequence before erasing begins.

This resets the device to reading array data. Once erasure

begins, however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the sequence

cycles in a program command sequence before programming

begins. This resets the device to reading array data. Once

programming begins, however, the device ignores reset com-

mands until the operation is complete.

The reset command may be written between the sequence

cycles in an autoselect command sequence. Once in the au-

toselect mode, the reset command must be written to return to

reading array data.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to reading array

data.

FLASH

AS29F010

Micross Components reserves the right to change products or speciﬁ cations without notice.

AS29F010

Rev. 2.4 01/10

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes, and

determine whether or not a sector is protected. The Command

Deﬁ nitions table shows the address and data requirements. This

method is an alternative to that shown in the Autoselect Codes

(High Voltage Method) table, which is intended for PROM

programmers and requires VID on address bit A9.

The auto select command sequence is initiated by writing

two unlock cycles, followed by the autoselect command. The

device then enters the autoselect mode, and the system may read

at any address any number of times, without initiating another

command sequence.

A read cycle at address XX00h or retrieves the manu-

facturer code. A read cycle at address XX01h returns the device

code. A read cycle containing a sector address (SA) and the

address 02h in returns 01h if that sector is protected, or 00h if

it is unprotected. Refer to the Sector Address tables for valid

sector addresses.

The system must write the reset command to exit the au-

toselect mode and return to reading array data.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two unlock

write cycles, followed by the program set-up command. The

program address and data are written next, which in turn initiate

the Embedded Program algorithm. The system is not required

to provide further controls or timings. The device au-

tomatically provides internally generated program pulses and

verify the programmed cell margin. The Command Deﬁ nitions

take shows the address and data requirements for the byte pro-

gram command sequence.

When the Embedded Program algorithm is complete, the

device then returns to reading array data and addresses are no

longer latched. The system can determine the status of the

program operation by using DQ7 or DQ6. See “Write Opera-

tion Status” for information on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored.

Programming is allowed in any sequence and across sec-

tor boundaries. A bit cannot be programmed fr om a “0” back

to a “1”. Attempting to do so may halt the operation and set

DQ5 to “1”, or cause the Data\ Polling algorithm to indicate

the operation was successful. However, a succeeding read

will show that the data is still “0”. Only erase operations can

convert a “0” to a “1”.

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional unlock write

cycles are then followed by the chip erase command, which

in turn invokes the Embedded Erase algorithm. The device

does not require the system to preprogram prior to erase. The

Embedded Erase algorithm automatically preprograms and

veriﬁ es the entire memory for an all zero data pattern prior

to electrical erase. The system is not required to provide any

controls or timings during these operations. The Command

Deﬁ nitions table shows the address and data requirements for

the chip erase command sequence.

Any commands written to the chip during the Embedded

Erase algorithm are ignored.

The system can determine the status of the erase op-

eration by using DQ7 or DQ6. See “Write Operation Status”

for information on these status bits. When the Embedded Erase

algorithm is complete, the device returns to reading array data

and addresses are no longer latched.

Figure 2 illustrates the algorithm for the erase op-

eration. See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and the Chip /Sector Erase

NOTE: See the appropriate Command Deﬁ nitions table for program com-

mand sequence.

FIGURE 1: PROGRAM OPERATION

FLASH

AS29F010

Micross Components reserves the right to change products or speciﬁ cations without notice.

AS29F010

Rev. 2.4 01/10

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional unlock write

cycles are then followed by the addresss of the sector to be

erased, and the sector erase command. The Command Deﬁ -

nitions table shows the address and data requirements for the

sector erase command sequence.

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algorithm

automatically programs and veriﬁ es the sector for an all zero

data pattern prior to electrical erase. The system is not required

to provide any controls or timings during these operations.

After the command sequence is written, a sector erase

time-out of 50μs begins. During the time-out period, additional

sector addresses and sector erase commands may be written.

Loading the sector erase buffer may be done in any sequence,

and the number of sectors may be from one sector to all sec-

tors. The time between these additional cycles must be less

than 50μs, otherwise the last address and command might not

be accepted, and erasure may begin. It is recommended that

processor interrupts be disabled during this time to ensure all

commands are accepted. The interrupts can be re-enabled after

the last Sector Erase command is written. If the time between

additional sector erase commands can be assumed to be less

than 50μs, the system need not monitor DQ3. Any command

during the time-out period resets the device to reading array

data. The system must rewrite the command sequence and any

additional sector addresses and commands.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector Erase Timer”

section.) The time-out begins from the rising edge of the ﬁ nal

WE\ pulse in the command sequence.

Once the sector erase operation has begun, all other com-

mands are ignored.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are no lon-

ger latched. The system can determine the status of the erase

operation by using DQ7 or DQ6. Refer to “Write Operation

Status” for information on these status bits.

Figure 2 illustrates the algorithm for the erase operation.

Refer to the Erase/Program Operations tables in the “AC

Characteristics” section for parameters, and to the Sector Erase

Operations Timing diagram for timing waveforms.

Erase Suspend/Erase Resume Commands

The Erase Suspect command allows the system to inter-

rupt a sector erase operation and then read data from, or program

data to, any sector not selected for erasure. This command

is valid only during the sector erase operation, including

the 50μs time-out period during the sector erase command

NOTE:

1) See the appropriate Command Deﬁ nitions table for program command

sequence.

2) See “DQ3: Sector Erase Timer” for more information.

FIGURE 2: ERASE OPERATION

sequence. The Erase Suspend command is ignored if written

during the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspect command during the Sector

Erase time-out immediately terminates the time-out period

and suspends the erase operation. Addresses are “don’t cares”

when writing the Erase Suspect command.

When the Erase Suspect command is written during a sec-

tor erase operation, the device requires a maximum of 20μs to

suspend the erase operation. However, when the Erase Suspect

command is written during the sector erase time-out, the device

immediately terminates the time-out period and suspends the

erase operation.

After the erase operation has been suspected, the system

can read array data from any sector not selected for erasure.

(The device “erase suspends” all sectors selected for erasure.)

Normal read and write timings and command deﬁ nitions ap-

ply. Reading at any address within erase-suspended sectors

produces status data on DQ7-DQ0. The system can use DQ7 to

determine if a sector is actively erasing or is erase-suspended.

See “Write Operation Status” for information on these status

bits.

After an erase-suspended program operation is com-

plete, the system can once again read array data within

FLASH

AS29F010

Micross Components reserves the right to change products or speciﬁ cations without notice.

AS29F010

Rev. 2.4 01/10

non-suspended sectors. The system can determine the status of

the program operation using the DQ7 or DQ6 status bits, just

as in the standard program operation. See “Write Operation

Status” for more information.

The system may also write the autoselect command se-

quence when the device is in the Erase Suspend mode. The

device allows reading autoselect codes even at addresses within

erasing sectors, since the codes are not stored in the memory

array. When the device exits the autoselect mode, the device

reverts to the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence” for

more information.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend mode

and continue the sector erase operation. Further writes of the

Resume command are ignored. Another Erase Suspend com-

mand can be written after the device has resumed erasing.

TABLE 4: Command Deﬁ nitions

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

1RA RD

1 XXXX F0

3 555 AA 2AA 55 555 F0

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 1

Device ID 4 555 AA 2AA 55 555 90 X01 20

4 555 AA 2AA 55 555 A0 PA PD

6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30

1 XXX B0

1 XXX 30

55 555 90 (SA)

X02

4 555 AA 2AA

Erase Resume10

Reset6

Sector Protect Verify8

Pro

ram

Chip Erase

Sector Erase

Erase Suspend9

Reset5

Autoselect7

Cycles

Bus Cycles2,3

First Second Third Fourth Fifth Sixth

Command Sequence1

LEGEND:

X = Don’t Care

RA = Address of the memory location to be read

RD = Data read from location RA during read operation

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE\ or CE\ pulse, whichever happens later

PD = Data to be programmed at location PA. Data latches on the rising edge of WE\ or CE\ pulse, whichever happens ﬁ rst

SA = Address of the sector to be veriﬁ ed (in autoselect mode) or erased. Address bits A16-A14 uniquely select any sector.

NOTES:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all command bus cycles are write operations.

4. No unlock or command cycles required when reading array data.

5. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing

status data).

6. The device accepts the three-cycle reset command sequence for backward compatibility.

7. The fourth cycle of the autoselect command sequence is a read operation.

8. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.

9. The system may read in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only

during a sector erase operation.

10. The Erase Resume command is valid only during the Erase Suspend mode.

FLASH

AS29F010

Micross Components reserves the right to change products or speciﬁ cations without notice.

AS29F010

Rev. 2.4 01/10

WRITE OPERATION STATUS

The device provides several bits to determine the status

of a write operation: DQ3, DQ5, DQ6, and DQ7. Table 5 and

the following subsections describe the functions of these bits.

DQ7 and DQ6 each offer a method for determining whether a

program or erase operation is complete or in progress. These

three bits are discussed ﬁ rst.

DQ7: Data\ Polling

The Data\ Polling bit, DQ7, indicates to the host system

whether an Embedded Algorithm is in progress or completed.

Data\ Polling is valid after the rising edge of the ﬁ nal WE\ pulse

in the program or erase command sequence.

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum programmed to DQ7.

When the Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system must pro-

vide the program address to read valid status information

on DQ7. If a program address falls within a protected sec-

tor, Data\ Polling on DQ7 is active for approximately

2μs, then the device returns to reading array data.

During the Embedded Erase algorithm, Data\ Polling

produces a “0” on DQ7. When the Embedded Erase algorithm

is complete, Data\ Polling produces a “1” on DQ7. This is

analogous to the complement/true datum output described for

the Embedded Program algorithm: the erase function changes

all the bits in a sector to “1”; prior to this, the device outputs

the “complement,” or “0”. The system must provide an ad-

dress within any of the sectors selected for erasure to read valid

status information on DQ7.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data\ Polling on DQ7

is active for approximately 100μs, then the device returns to

reading array data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected sectors, and

ignores the selected sectors that are protected.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at DQ7-DQ0

on the following read cycles. This is because DQ7 may change

asynchronously with DQ0-DQ6 while Output Enable (OE\) is

asserted low. The Data\ Polling Timings (During Embedded

Algorithms) ﬁ gure in the “AC Characteristics” section il-

lustrates this.

Table 5 shows the outputs for Data\ Polling on DQ7.

Figure 3 shows the Data\ Polling algorithm.

DQ6: Toggle Bit I

Toggle bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete. Toggle

Bit I may be read at any address, and is valid after the rising

NOTE:

1) VA = Valid address for programming. During a sector erase operation, a

valid address is an address within any sector selected for erasure. During chip

erase, a valid address is any non-protected sector address.

2) DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change

simultaneously with DQ5.

FIGURE 3: DATA\ POLLING ALGORITHM

edge of the ﬁ nal WE\ pulse in the command sequence (prior

to the program or erase operation), and during the sector erase

time-out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause DQ6 to

toggle. (The system may use either OE\ or CE\ to control

the read cycles.) When the operation is complete, DQ6 stops

toggling.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, DQ6 toggles for

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AS29F010

Rev. 2.4 01/10

approximately 100μs, then returns to reading array data. If

not all selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores the

selected sectors that are protected.

If a program address falls within a protected sector, DQ6

toggles for approximately 2μs after the program command

sequence is written, then returns to reading array data.

The Write Operation Status table shows the outputs for

Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit

algorithm, and to the Toggle Bit Timings ﬁ gure in the “AC

Characteristics” section for the timing diagram.

Reading Toggle Bit DQ6

Refer to Figure 4 for the following discussion. Whenever

the system initially begins reading toggle bit status, it must

read DQ7-DQ0 at least twice in a row to determine whether a

toggle bit is toggling. Typically, a system would note and store

the value of the toggle bit after the ﬁ rst read. After the second

read, the system would compare the new value of the toggle

bit with the ﬁ rst. If the toggle bit is not toggling, the device

has completed the program or erase operation. The system can

read array data on DQ7-DQ0 on the following read cycle.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the system also

should note whether the value of DQ5 is high (see the section on

DQ5). If it is, the system should then determine again whether

the toggle bit is toggling, since the toggle bit may have stopped

toggling just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the program

or erase operation. If it is still toggling, the device did not

complete the operation successfully, and the system must write

the reset command to return to reading array data.

The remaining scenario is that the system initially

determines that the toggle bit it toggling and DQ5 has not gone

high. The system may continue to monitor the toggle bit and

DQ5 through successive read cycles, determining the status

as described in the previous paragraph. Alternatively, it may

choose to perform other system tasks. In this case, the system

must start at the beginning of the algorithm when it returns to

determine the status of the operation (top of Figure 4).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a speciﬁ ed internal pulse count limit. Under these

conditions DQ5 produces a “1.” This is a failure condition

that indicates the program or erase cycle was not successfully

completed.

The DQ5 failure condition may appear if the system tries

to program a “1” to a location that is previously programmed

to “0.” Only an erase operation can change a “0” back to a “1.”

Under this condition, the device halts the operation, and when

the operation has exceeded the timing limits, DQ5 produces a

“1.”

Under both these conditions, the system must issue the

reset command to return the device to reading array data.

DQ3: Sector Erase Timer

NOTE:

1) Read toggle bit twice to determine whether or not it is toggling. See text.

2) Recheck toggle bit because it may stop toggling as DQ5 changes to “1”.

See text.

FIGURE 4: TOGGLE BIT ALGORITHM

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Rev. 2.4 01/10

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an erase

operation has begun. (The sector erase timer does not apply to

the chip erase command.) If additional sectors are selected for

erasure, the entire time-out also applies after each additional

sector erase command. When the time-out is complete, DQ3

switches from “0” to “1.” The system may ignore DQ3 if the

system can guarantee that the time between additional sector

erase commands will always be less than 50μs. See also the

“Sector Erase Command Sequence” section.

After the sector erase command sequence is written, the

system should read the status on DQ7 (Data\ Polling) or DQ6

(Toggle Bit I) to ensure the device has accepted the command

sequence, and then read DQ3. If DQ3 is “1”, the internally

controlled erase cycle has begun; all further commands are

ignored until the erase operation is complete. If DQ3 is “0”,

the device will accept additional sector erase commands. To

ensure the command has been accepted, the system software

should check the status of DQ3 prior to and following each

subsequent sector erase command. If DQ3 is high on the

second status check, the last command might not have been

accepted. Table 5 shows the outputs for DQ3.

TABLE 5: WRITE OPERATION STATUS

NOTES:

1. DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5: Exceeding Timing

Limits” for more information.

DQ71DQ6 DQ52DQ3

Embedded Program Algorithm DQ7\ Toggle 0 N/A

Embedded Erase Algorithm 0 Toggle 0 1

Reading within Erase Suspended Sector 1 No toggle 0 N/A

Reading within Non-Erase Suspended Sector Data Data Data Data

Standard

Mode

Erase

Suspend

Mode

OPERATION

*Stresses greater than those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above

those indicated in the operation section of this speciﬁ cation is not implied.

Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

ABSOLUTE MAXIMUM RATINGS*

Ambient Temperature with Power Applied...-55°C to +125°C

Voltage with Respect to Ground

1...................................................-2.0V to +7.0V

A92...................................................-2.0V to +13.0V

All other pins1....................................-2.0V to +7.0V

Output Short Circuit Current3.......................................200mA

VCC Supply Voltage.....................................+4.50V to +5.50V

Storage Temperature......................................-65°C to +125°C

NOTES:

1. Minimum DC voltage on input or I/O pin is -0.5V. During voltage transitions, input

may overshoot VSS to -2.0V for periods of up to 20ns. See Figure 5. Maximum DC

voltage on input and I/O pins is VCC + 0.5V. During voltage transitions, input and I/O

pins may overshoot VCC + 2.0V for periods up to 20ns. See Figure 6.

2. Minimum DC voltage on A9 pin is -0.5V. During voltage transitions, A9 pins may

overshoot VSS to -2.0V for periods of up to 20ns. See Figure 5. Maximum DC input

voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns.

3. No more than one output shorted at a time. Duration of the short circuit should not be

greater than one second.

FIGURE 5: Maximum Negative

Overshoot Waveform

FIGURE 6: Maximum Positive

Overshoot Waveform

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DC CHARACTERISTICS: TTL/NMOS Compatible

PARAMETER DESCRIPTION SYM MIN TYP MAX UNIT

Input Load Current V

= V

to V

, V

= V

Max I

±5.0 μA

A9 Input Load Current V

= V

Max, A9 = 12.5V I

LIT

100 μA

Output Leakage Current V

OUT

= V

to V

, V

= V

Max I

±5.0 μA

Active Read Current

1,2

CE\ = V

, OE\ = V

CC1

12 35 mA

Active Write Current

2,3,4

CE\ = V

, OE\ = V

CC2

30 50 mA

Standby Current CE\ and OE\ = V

CC3

0.4 5.0 mA

Input Low Voltage V

-0.5 0.8 V

Input High Voltage V

2.0 V

+ 0.5 V

Voltage for Autoselect and Sector

Protect V

= 5.0V V

10.5 12.5 V

Output Low Voltage I

= 12 mA, V

= V

Min V

0.45 V

Output High Voltage I

= -2.5 mA, V

= V

Min V

2.4 V

Low V

Lock-out Voltage V

LKO

3.2 V

NOTES:

1. The ICC current listed is typically less than 2mA/MHz, with OE\ at VIH.

2. Maximum ICC speciﬁ cations are tested with VCC = VCC Max

3. ICC active while Embedded Program or Embedded Erase Algorithm is in progress.

4. Not 100% tested.

DC CHARACTERISTICS: CMOS Compatible

PARAMETER DESCRIPTION SYM MIN TYP MAX UNIT

Input Load Current V

= V

to V

, V

= V

Max I

±5.0 μA

A9 Input Load Current V

= V

Max, A9 = 12.5V I

LIT

50 μA

Output Leakage Current V

OUT

= V

to V

, V

= V

Max I

±5.0 μA

Active Current

1,2

CE\ = V

, OE\ = V

CC1

35 mA

Active Current

2,3,4

CE\ = V

, OE\ = V

CC2

50 mA

Standby Current CE\ = V

± 0.5V, OE\ = V

CC3

1.6 mA

Input Low Voltage V

-0.5 0.8 V

Input High Voltage V

0.7 x V

+ 0.3 V

Voltage for Autoselect and

Sector Protect V

= 5.25V V

10.5 12.5 V

Output Low Voltage I

= 12 mA, V

= V

Min V

0.45 V

= -2.5 mA, V

= V

Min V

OH1

0.85 V

= -100 μA, V

= V

Min V

OH2

- 0.4

Low V

Lock-out Voltage V

LKO

3.2 V

Output High Voltage

FLASH

AS29F010

Micross Components reserves the right to change products or speciﬁ cations without notice.

AS29F010

Rev. 2.4 01/10

TABLE 6: TEST CONDITIONS,

Test Speciﬁ cations

CONDITIONS ALL SPEEDS UNIT

Output Load

Output Load Capacitance, CL

(including jig capacitance) 50 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0/3 V

Input timing measurement

reference levels 1.5 V

Output timing measurement

reference levels 1.5 V

1 TTL Gate

AC CHARACTERISTICS: Read-Only Operations

FIGURE 7: TEST CONDITIONS,

Test Setup

JEDEC Std -50 -60 -70 90 -120 -150

Read Cycle Time1tAVAV tRC MIN50607090120150ns

Address to Output Delay tAVQV tACC

CE\ = VIL

OE\ = VIL

MAX 50 60 70 90 120 150 ns

Chip Enable to Output Delay tELQV tCE OE\ = VIL MAX 50 60 70 90 120 150 ns

Output Enable to Output Delay tGLQV tOE MAX 25 30 35 40 50 55 ns

Chip Enable to Output High Z1tEHQZ tDF MAX 15 20 20 25 30 35 ns

Output Enable to Output High Z1tGHQZ tDF MAX 15 20 20 25 30 35 ns

Read MIN ns

Toggle and

Data Polling MIN ns

Output Hold Time From Addresses

CE\ or OE\, Whichever Occurs

First

tAXQX tOH MIN ns

PARAMETER TEST SETUP

Output Enable Hold Time1tOEH

SYMBOL

UNITS

SPEED OPTIONS

NOTES:

1. Not 100% tested.

2. See Figure 7 and Table 6 for test speciﬁ cations.

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Micross Components reserves the right to change products or speciﬁ cations without notice.

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Rev. 2.4 01/10

FIGURE 8: AC CHARACTERISTICS, Read Operations Timings

AC CHARACTERISTICS: Erase and Program Operations

NOTES:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

JEDEC Std -50 -60 -70 90 -120 -150

Write Cycle Time

MIN t

AVAV

50 60 70 90 120 150 ns

Address Setup Time MIN t

AVWL

Address Hold Time MIN t

WLAX

40 45 45 45 50 50 ns

Data Setup Time MIN t

DVWH

25 30 30 45 50 50 ns

Data Hold Time MIN t

WHDX

Output Enable Setup Time MIN t

OES

Read Recover Time Before Write

(OE\ High to WE\ Low) MIN t

GHWL

CE\ Setup Time MIN t

ELWL

CE\ Hold Time MIN t

WHEH

Write Pulse Width MIN t

WLWH

25 30 35 45 50 50 ns

Write Pulse Width High MIN t

WHWL

WPH

Byte Programming Operation

MIN t

WHWH1

μs

Chip/Sector Erase Operation

MAX t

WHWH2

sec

Set Up Time

MIN t

VCS

μs

SYMBOL

PARAMETER UNITS

SPEED OPTIONS

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Rev. 2.4 01/10

FIGURE 9: AC CHARACTERISTICS, Program Operation Timings

NOTES: PA = program address, PD = program data, DOUT is the true data at the program address.

FIGURE 10: AC CHARACTERISTICS, Chip/Sector Erase

Operation Timings

NOTES: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status).

FLASH

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Rev. 2.4 01/10

FIGURE 11: Data\ Polling Timings (During Embedded Algorithms)

NOTES: VA = Valid address. Illustration shows ﬁ rst status cycle after command sequence, last status read cycle, and array data read cycle.

FIGURE 12: AC CHARACTERISTICS, Toggle Bit Timings (During

Embedded Algorithms)

NOTES: VA = Valid address, not required for DQ6. Illustration shows ﬁ rst two status cycle after command sequence, last status read cycle, and array data

read cycle.

FLASH

AS29F010

Micross Components reserves the right to change products or speciﬁ cations without notice.

AS29F010

Rev. 2.4 01/10

AC CHARACTERISTICS: Erase and Program Operations

JEDEC Std -50 -60 -70 90 -120 -150

Write Cycle Time

MIN t

AVAV

50 60 70 90 120 150 ns

Address Setup Time MIN t

AVEL

Address Hold Time MIN t

ELAX

40 45 45 45 50 50 ns

Data Setup Time MIN t

DVEH

25 30 30 45 50 50 ns

Data Hold Time MIN t

EHDX

Output Enable Setup Time

MIN t

OES

Read Recover Time Before Write MIN t

GHEL

WE\ Setup Time MIN t

WLEL

WE\ Hold Time MIN t

EHWH

CE\ Pulse Width MIN t

ELEH

25 30 35 45 50 50 ns

CE\ Pulse Width High MIN t

EHEL

CPH

Byte Programming Operation

MIN t

WHWH1

μs

Chip/Sector Erase Operation

MAX t

WHWH2

sec

SYMBOL

PARAMETER UNITS

SPEED OPTIONS

NOTES:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

FIGURE 13: AC CHARACTERISTICS, Alternate CE\ Controlled

Write Operation Timings

NOTES:

1. PA = program address, PD = program data, SA = sector address, DQ7\ = complement of data input, DOUT = array data.

2. Figure indicates the last two bus cycles of the command sequence.

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Micross Components reserves the right to change products or speciﬁ cations without notice.

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Rev. 2.4 01/10

ERASE AND PROGRAMMING PERFORMANCE

TYP

MAX

UNIT

Chip/Sector Erase Time 1.0 15 sec Excludes 00h programming prior to erasure

Byte Programming Time 7 300 μs

Chip Programming Time

0.9 6.25 sec

PARAMETER

LIMITS

COMMENTS

Excludes system-level overhead

NOTES:

1. Typical program and erase times assume the following conditions: 25°C, 5.0V VCC, 1 million cycles. Additionally, programming typicals

assume checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 4.5V, 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster

than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set DQ5 = 1.

See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4 for further

information on command deﬁ nitions.

6. The device has a minimum guaranteed erase cycle endurance of 1 million cycles.

LATCHUP CHARACTERISTIC

PARAMETER MIN MAX

Input voltage with respect to V

on I/O pins -1.0V V

+ 1.0V

Current -100mA +100mA

NOTES: Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time.

PIN CAPACITANCE

PARAMETER CONDITIONS SYMBOL MAX UNIT

Input Capacitance VIN = 0 CIN 15 pF

Output Capacitance VOUT = 0 COUT 15 pF

Control Pin Capacitance VPP = 0 CIN2 15 pF

NOTES:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz

DATA RETENTION

PARAMETER CONDITIONS MIN UNIT

150°C 10 Years

125°C 20 Years

Minimum Pattern Data Retention Time

FLASH

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Micross Components reserves the right to change products or speciﬁ cations without notice.

AS29F010

Rev. 2.4 01/10

MECHANICAL DEFINITIONS*

Micross Case (Package Designator CW)

SMD 5962-96690, Case Outline Y

*All measurements are in inches.

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AS29F010

Rev. 2.4 01/10

MECHANICAL DEFINITIONS*

Micross Case (Package Designator F)

SMD 5962-96690, Case Outline T

*All measurements are in inches.

MIN MAX

A --- 0.125

b 0.015 0.019

C 0.004 0.007

D 0.810 0.830

D1 0.745 0.755

E 0.405 0.415

E1 0.305 0.315

L 0.380 0.420

Q 0.022 0.028

SYMBOL

SMD SPECIFICATIONS

0.050 TYP

FLASH

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AS29F010

Rev. 2.4 01/10

MECHANICAL DEFINITIONS*

Micross Case (Package Designator DCG)

SMD 5962-96690, Case Outline U

*All measurements are in inches.

MIN MAX

A --- 0.132

A1 0.095 0.125

A2 0.003 0.007

b 0.015 0.019

C 0.004 0.007

D 0.810 0.830

E 0.405 0.415

E1 0.525 0.535

E2 0.305 0.315

Q 0.022 0.028

R0.007 TYP

0.050 TYP

0.436 TYP

0.060 TYP

SYMBOL

SMD SPECIFICATIONS

0.750 TYP

0.030 TYP

FLASH

AS29F010

Micross Components reserves the right to change products or speciﬁ cations without notice.

AS29F010

Rev. 2.4 01/10

MECHANICAL DEFINITIONS*

Micross Case (Package Designator SOJ)

SMD 5962-96690, Case Outline X

*All measurements are in inches.

FLASH

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AS29F010

Rev. 2.4 01/10

*AVAILABLE PROCESSES

XT = Military Temperature Range -55oC to +125oC

IT = Industrial Temperature Range -40°C to +85°C

883C = 883C Processing -55°C to +125°C

Q = QML Processing -55°C to +125°C

**NOTE: 50ns (-50) option available with IT and XT options only.

ORDERING INFORMATION

EXAMPLE: AS29F010CW-90/883C

EXAMPLE: AS29F010F-120/XT

EXAMPLE: AS29F010DCG-70/Q

EXAMPLE: AS29F010SOJ-55/XT

Device Number Package Type Speed ns Process

AS29F010 CW -50** /*

AS29F010 CW -60 /*

AS29F010 CW -70 /*

AS29F010 CW -90 /*

AS29F010 CW -120 /*

AS29F010 CW -150 /*

AS29F010 F -50** /*

AS29F010 F -60 /*

AS29F010 F -70 /*

AS29F010 F -90 /*

AS29F010 F -120 /*

AS29F010 F -150 /*

AS29F010 DCG -50** /*

AS29F010 DCG -60 /*

AS29F010 DCG -70 /*

AS29F010 DCG -90 /*

AS29F010 DCG -120 /*

AS29F010 DCG -150 /*

AS29F010 SOJ -50** /*

AS29F010 SOJ -60 /*

AS29F010 SOJ -70 /*

AS29F010 SOJ -90 /*

AS29F010 SOJ -120 /*

AS29F010 SOJ -150 /*

FLASH

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Micross Components reserves the right to change products or speciﬁ cations without notice.

AS29F010

Rev. 2.4 01/10

MICROSS TO DSCC PART NUMBER

CROSS REFERENCE*

Micross Package Designator CW

Micross Part # SMD Part #

AS29F010CW-60/Q 5962-9669005HYA

AS29F010CW-70/Q 5962-9669004HYA

AS29F010CW-90/Q 5962-9669003HYA

AS29F010CW-120/Q 5962-9669002HYA

AS29F010CW-150/Q 5962-9669001HYA

Micross Package Designator F

Micross Part # SMD Part #

AS29F010F-60/Q 5962-9669005HTA

AS29F010F-70/Q 5962-9669004HTA

AS29F010F-90/Q 5962-9669003HTA

AS29F010F-120/Q 5962-9669002HTA

AS29F010F-150/Q 5962-9669001HTA

Micross Package Designator DCG

Micross Part # SMD Part #

AS29F010DCG-60/Q 5962-9669005HUA

AS29F010DCG-70/Q 5962-9669004HUA

AS29F010DCG-90/Q 5962-9669003HUA

AS29F010DCG-120/Q 5962-9669002HUA

AS29F010DCG-150/Q 5962-9669001HUA

* Micross part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.

FLASH

AS29F010

Micross Components reserves the right to change products or speciﬁ cations without notice.

AS29F010

Rev. 2.4 01/10

DOCUMENT TITLE

128K x 8 FLASH UNIFORM SECTOR 5.0V FLASH MEMORY

REVISION HISTORY

Rev # History Release Date Status

2.3 Changed MAX value from 60 to 15 December 2008 Release

corrections on page 15 &18

2.4 Updated Micross Information January 2010 Release