1. General description
The LPC11U3x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for
8/16-bit microcontroller applications, offering performance, low power, simple instruction
set and memory addressing together with reduced code size compared to existing 8/16 -bit
architectures.
The LPC11U3x operate at CPU frequencies of up to 50 MHz.
Equipped with a highly flexible and configurable full-speed USB 2.0 device controller, the
LPC11U3x brings unparalleled design flexibility and seamless integration to today’s
demanding connectivity solutions.
The peripheral complement of the LPC11U3x includes up to 128 kB of flash memory, up
to 12 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I2C-bus
interface, one RS-485/EIA-485 USART with support for synchronous mode and smart
card interface, two SSP interfaces, four general purpose counter/timers, a 10-bit ADC,
and up to 54 general purpose I/O pins.
The I/O Handler is a software library-supported hardware engine that can be used to add
performance, connectivity and flexibility to system designs. It is available on the
LPC11U37HFBD64/401. The I/O Handler can emulate serial interfaces such as UART,
I2C, and I2S with no or very low additional CPU load and can off-load the CPU by
performing processing-intensive functions like DMA transfers in hardware. Software
libraries for multiple I/O Handler applications are available on http://www.LPCware.com.
For additional documentation related to the LPC11U3x parts, see Section 15
References.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Non-Maskable Interrupt (NMI) inpu t se lectable from several input sources.
System tick timer.
Memory:
Up to 128 kB on-chip flash program memory with sector (4 kB) and page erase
(256 byte) access.
4 kB on-chip EEPROM data memory; byte erasable and byte programmable;
on-chip API support.
Up to 12 kB SRAM data memory.
LPC11U3x
32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash; up
to 12 kB SRAM and 4 kB EEPROM; USB device; USART
Rev. 2.2 — 11 March 2014 Product data sheet
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 2 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
16 kB boot ROM.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
ROM-based USB drivers. Flash updates via USB supported.
ROM-based 32-bit integer division routines.
Debug options:
Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan
Description Language).
Serial Wire Debug.
Digital peripherals:
Up to 54 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors, repeater mode, and open-drain mode.
Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
Two GPIO group ed inte rr up t modu le s en ab le an inte rr up t ba se d on a
programmable pattern of input states of a group of GPIO pins.
High-current source output driver (20 mA) on one pin.
High-current sink driver (20 mA) on true open-drain pins.
Four general purpose counter/timers with a total of up to 8 capture inputs and 13
match outpu ts.
Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal
low-power WatchDog Oscillator (WDO).
Analog peripherals:
10-bit ADC with input multiplexing among eight pins.
Serial interfaces:
USB 2.0 full-speed device co nt ro ller.
USART with fractional baud rate generation, internal FIFO, a full modem control
handshake interface, and support for RS-485/9-bit mode and synchronous mode.
USART supports an asynchronous smart card interface (ISO 7816-3).
Two SSP controllers with FIFO and multi-protocol capabilities.
I2C-bus interface suppor tin g the full I2C-bu s specifica tion and Fast-mode Plus with
a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
I/O Handler for hardware emulation of serial interfaces and DMA; supported through
software libraries. (LPC11U37HFBD64/401 only.)
Clock generation :
Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).
12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as
a system clock.
Internal low-power, low-frequency W atchDog Oscillator (WDO) with programmable
frequency outp ut .
PLL allows CPU operation up to the maximum CPU rate with the system oscillator
or the IRC as clock sources.
A second, dedicated PLL is provided for USB.
Clock output function with divider that can reflect the crystal oscillator, the main
clock, the IRC, or the watchdog oscillator.
Power control:
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 3 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, Power-down, and Deep power-down modes.
Power profiles residing in boot ROM provide optimized performance an d minimized
power consumption for any given application through one simple function call.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
Processor wake-up fro m Deep-sle ep and Power -down modes via reset, selectable
GPIO pins, watchdog interrupt, or USB port activity.
Processor wake-up from Deep power-down mode using one special function pin.
Power-On Reset (POR).
Brownout detect with up to four separate thresholds for interrupt and forced reset.
Unique device serial number for identification.
Single 3.3 V power supply (1.8 V to 3.6 V).
Temperature range 40 C to +85 C.
Available as LQFP64, LQFP48, TFBGA48, and HVQFN33 packages.
3. Applications
4. Ordering information
Consumer peripherals Handheld scanners
Medical USB audio devices
Industrial control
Table 1. Ordering information
Type number Package
Name Description Version
LPC11U34F HN33/311 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 7 7 0.85 mm n/a
LPC11U34FBD48/311 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U34F HN33/421 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 7 7 0.85 mm n/a
LPC11U34FBD48/421 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U35F HN33/401 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 7 7 0.85 mm n/a
LPC11U35FBD48/401 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U35FBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2
LPC11U3 5FHI33/501 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 5 5 0.85 mm n/a
LPC11U35F ET48/501 TFBGA48 plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 4.5
0.7 mm SOT1155-2
LPC11U36FBD48/401 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U36FBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 4 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
4.1 Ordering options
[1] For general-purpose use.
[2] For I/O Handler use only.
LPC11U37FBD48/401 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U37HFBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2
LPC11U37FBD64/501 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2
Table 1. Ordering information …continued
Type number Package
Name Description Version
Table 2. Ordering options
Type number
Flash in kB
EEPROM in kB
SRAM0 in kB
USB SRAM in kB
SRAM1 in kB
Total
SRAM in kB[1]
I/O Handler
USART
I2C-bus FM+
SSP
USB device
ADC channels
GPIO pins
LPC11U34FHN33/311 40 4 8 - - 8 no 1 1 2 1 8 26
LPC11U34FBD48/311 40 4 8 - - 8 no 1 1 2 1 8 40
LPC11U34FHN33/421 48 4 8 2 - 10 no 1 1 2 1 8 26
LPC11U34FBD48/421 48 4 8 2 - 10 no 1 1 2 1 8 40
LPC11U35FHN33/401 64 4 8 2 - 10 no 1 1 2 1 8 26
LPC11U35FBD48/401 64 4 8 2 - 10 no 1 1 2 1 8 40
LPC11U35FBD64/401 64 4 8 2 - 10 no 1 1 2 1 8 54
LPC11U35FHI33/501 64 4 8 2 2[1] 12 no 1 1 2 1 8 26
LPC11U35FET48/501 64 4 8 2 2[1] 12 no 1 1 2 1 8 40
LPC11U36FBD48/401 96 4 8 2 - 10 no 1 1 2 1 8 40
LPC11U36FBD64/401 96 4 8 2 - 10 no 1 1 2 1 8 54
LPC11U37FBD48/401 128 4 8 2 - 10 no 1 1 2 1 8 40
LPC11U37HFBD64/401 128 4 8 2 2[2] 10 yes 1 1 2 1 8 54
LPC11U37FBD64/501 128 4 8 2 2[1] 12 no 1 1 2 1 8 54
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 5 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
5. Block diagram
(1) Not available on HVQFN33 packages.
(2) CT16B0_CAP1, CT16B1_CAP1 available on LQFP64 packages only; CT32B0_CAP1 available on TFBGA48, LQFP48, and
LQFP64 packages only; CT32B1_CAP1 available in TFBGA48/LQFP64 packages only.
(3) LPC11U37HFBD64/401 only.
Fig 1. Block diagram
SRAM
8/10/12 kB
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
FLASH
40/48/64/96/128 kB
HIGH-SPEED
GPIO
AHB TO APB
BRIDGE
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
RESET
SWD, JTAG
LPC11U3x
slave
slave
master
slave slave
ROM
16 kB
slave
AHB-LITE BUS
GPIO ports 0/1
I/O
HANDLER(3)
IOH_[20:0]
CLKOUT
IRC, WDO
SYSTEM OSCILLATOR
POR
PLL0 USB PLL
BOD
10-bit ADC
USART/
SMARTCARD INTERFACE AD[7:0]
RXD
TXD
CTS, RTS, DTR
SCLK
GPIO INTERRUPTS
32-bit COUNTER/TIMER 0
CT32B0_MAT[3:0]
CT32B0_CAP[1:0](2)
32-bit COUNTER/TIMER 1
CT32B1_MAT[3:0]
CT32B1_CAP[1:0](2)
DCD, DSR(1), RI(1)
16-bit COUNTER/TIMER 1
WINDOWED WATCHDOG
TIMER
GPIO GROUP0 INTERRUPTS
CT16B1_MAT[1:0]
16-bit COUNTER/TIMER 0
CT16B0_MAT[2:0]
CT16B0_CAP[1:0](2)
CT16B1_CAP[1:0](2)
GPIO pins
GPIO pins
GPIO GROUP1 INTERRUPTS
GPIO pins
system bus
SSP0 SCK0, SSEL0,
MISO0, MOSI0
SSP1 SCK1, SSEL1,
MISO1, MOSI1
I2C-BUS
IOCON
SYSTEM CONTROL
PMU
SCL, SDA
XTALIN XTALOUT
USB DEVICE
CONTROLLER
USB_DP
USB_DM
USB_VBUS
USB_FTOGGLE,
USB_CONNECT
002aag345
master
slave
EEPROM
4 kB
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 6 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
6. Pinning information
6.1 Pinning
For parts LPC11U34FHN33/311, LPC11U34FHN33/421, LPC11U35FHN33/401, LPC11U35FHI33/501
Fig 2. Pin configuration (HVQFN33)
002aag809
Transparent top view
PIO0_8/MISO0/CT16B0_MAT0
PIO0_20/CT16B1_CAP0
PIO0_2/SSEL0/CT16B0_CAP0
PIO0_9/MOSI0/CT16B0_MAT1
VDD SWCLK/PIO0_10/SCK0/CT16B0_MAT2
XTALOUT PIO0_22/AD6/CT16B1_MAT1/MISO1
XTALIN TDI/PIO0_11/AD0/CT32B0_MAT3
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE TMS/PIO0_12/AD1/CT32B1_CAP0
RESET/PIO0_0 TDO/PIO0_13/AD2/CT32B1_MAT0
PIO1_19/DTR/SSEL1 TRST/PIO0_14/AD3/CT32B1_MAT1
PIO0_3/USB_VBUS
PIO0_4/SCL
PIO0_5/SDA
PIO0_21/CT16B1_MAT0/MOSI1
USB_DM
USB_DP
PIO0_6/USB_CONNECT/SCK0
PIO0_7/CTS
PIO0_19/TXD/CT32B0_MAT1
PIO0_18/RXD/CT32B0_MAT0
PIO0_17/RTS/CT32B0_CAP0/SCLK
VDD
PIO1_15/DCD/CT16B0_MAT2/SCK1
PIO0_23/AD7
PIO0_16/AD5/CT32B1_MAT3/WAKEUP
SWDIO/PIO0_15/AD4/CT32B1_MAT2
817
718
619
520
421
322
223
124
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
terminal 1
index area
33 VSS
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 7 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Fig 3. Pin configuration (TF BGA4 8)
002aag810
LPC11U35FET48/501
Transparent top view
H
G
F
D
B
E
C
A
24681357
ball A1
index area
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 8 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Fig 4. Pin configuration (LQFP48)
LPC11U34FBD48/311
LPC11U34FBD48/421
LPC11U35FBD48/401
LPC11U36FBD48/401
LPC11U37FBD48/401
PIO1_25/CT32B0_MAT1 PIO1_13/DTR/CT16B0_MAT0/TXD
PIO1_19/DTR/SSEL1 TRST/PIO0_14/AD3/CT32B1_MAT1
RESET/PIO0_0 TDO/PIO0_13/AD2/CT32B1_MAT0
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE TMS/PIO0_12/AD1/CT32B1_CAP0
V
SS
TDI/PIO0_11/AD0/CT32B0_MAT3
XTALIN PIO1_29/SCK0/CT32B0_CAP1
XTALOUT PIO0_22/AD6/CT16B1_MAT1/MISO1
V
DD
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO0_20/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1
PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0
PIO1_26/CT32B0_MAT2/RXD PIO1_21/DCD/MISO1
PIO1_27/CT32B0_MAT3/TXD PIO1_31
PIO1_20/DSR/SCK1 PIO1_16/RI/CT16B0_CAP0
PIO0_3/USB_VBUS PIO0_19/TXD/CT32B0_MAT1
PIO0_4/SCL PIO0_18/RXD/CT32B0_MAT0
PIO0_5/SDA PIO0_17/RTS/CT32B0_CAP0/SCLK
PIO0_21/CT16B1_MAT0/MOSI1 V
DD
PIO1_23/CT16B1_MAT1/SSEL1 PIO1_15/DCD/CT16B0_MAT2/SCK1
USB_DM PIO0_23/AD7
USB_DP V
SS
PIO1_24/CT32B0_MAT0 PIO0_16/AD5/CT32B1_MAT3/WAKEUP
PIO0_6/USB_CONNECT/SCK0 SWDIO/PIO0_15/AD4/CT32B1_MAT2
PIO0_7/CTS
PIO1_28/CT32B0_CAP0/SCLK
PIO1_22/RI/MOSI1
PIO1_14/DSR/CT16B0_MAT1/RXD
002aag811
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
48
47
46
45
44
43
42
41
40
39
38
37
24
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 9 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
See Table 3 for the full pin name.
Fig 5. Pin configuration (LQFP64)
LPC11U35FBD64/401
LPC11U36FBD64/401
LPC11U37HFBD64/401
LPC11U37FBD64/501
PIO1_0 VDD
PIO1_25 PIO1_13
PIO1_19 TRST/PIO0_14
RESET/PIO0_0 TDO/PIO0_13
PIO0_1 TMS/PIO0_12
PIO1_7 PIO1_11
VSS TDI/PIO0_11
XTALIN PIO1_29
XTALOUT PIO0_22
VDD PIO1_8
PIO0_20 SWCLK/PIO0_10
PIO1_10 PIO0_9
PIO0_2 PIO0_8
PIO1_26 PIO1_21
PIO1_27 PIO1_2
PIO1_4 VDD
PIO1_1 PIO1_6
PIO1_20 PIO1_16
PIO0_3 PIO0_19
PIO0_4 PIO0_18
PIO0_5 PIO0_17
PIO0_21 PIO1_12
PIO1_17 VDD
PIO1_23 PIO1_15
USB_DM PIO0_23
USB_DP PIO1_9
PIO1_24 VSS
PIO1_18 PIO0_16
PIO0_6 SWDIO/PIO0_15
PIO0_7 PIO1_22
PIO1_28 PIO1_3
PIO1_5 PIO1_14
002aag812
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 10 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
6.2 Pin description
Table 3 shows all pins and their assigne d dig ital or analog fu nc tion s in or de r of the GPI O
port number. The default function after reset is listed first. All port pins have internal
pull-up resistors enabled after reset except for the true open-drain pins PIO0_4 and
PIO0_5.
Every port pin has a corresponding IOCON register for programming the digital or analog
function, the pull-up/pull-down configuration, the repeater, and the open-drain modes.
The USART, counter/timer, and SSP functions are available on more than one port pin.
Table 3. Pin description
Symbol
Pin HVQFN33
Pin TFBGA48
Pin LQFP48
Pin LQFP64
Reset
state
[1]
Type Description
RESET/PIO0_0 2 C1 3 4 [2] I; PU I RESETExternal reset input with 20 ns glitch filter.
A LOW-going pulse as short as 50 ns on this pin
resets the device, causing I/O ports and peripherals to
take on their default states and processor execution
to begin at address 0. This pin also serves as the
debug select input. LOW level selects the JTAG
boundary scan. HIGH level selects the ARM SWD
debug mode.
In deep power-down mode, this pin must be pulled
HIGH externally. The RESET pin can be left
unconnected or be used as a GPIO pin if an external
RESET function is not needed and Deep power-down
mode is not used.
- I/O PIO0_0 — General purpose digital input/output pin.
PIO0_1/CLKOUT/
CT32B0_MAT2/
USB_FTOGGLE
3C245[3] I; PU I/O PIO0_1 — General purpose digital input/output pin. A
LOW level on this pin during reset starts the ISP
command handler or the USB device enumeration.
-OCLKOUT — Clockout pin.
-OCT32B0_MAT2 — Match output 2 for 32-bit timer 0.
-OUSB_FTOGGLE — USB 1 ms Start-of-Frame signal.
PIO0_2/SSEL0/
CT16B0_CAP0/IOH_0 8F11013
[3] I; PU I/O PIO0_2 — General purpose digital input/output pin.
- I/O SSEL0 — Slave select for SSP0.
-ICT1 6B0_CAP0 — Capture input 0 for 16-bit timer 0.
- I/O IOH_0 — I/O Handler input/output 0.
LPC11U37HFB D64/401 only.
PIO0_3/USB_VBUS/
IOH_1 9H21419
[3] I; PU I/O PIO0_3 — General purpose digital input/output pin. A
LOW level on this pin during reset starts the ISP
command handler. A HIGH level duri ng reset starts
the USB device enumeration.
-IUSB_VBUSMonitors the presence of USB bus
power.
- I/O IOH_1 — I/O Handler input/output 1.
LPC11U37HFB D64/401 only.
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 11 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
PIO0_4/SCL/IOH_2 10 G3 15 20 [4] I; IA I/O PIO0_4 — General purpose digital input/output pin
(open-drain).
- I/O SCL — I2C-bus clock input/output (open-drain).
High-current sink only if I2C Fast-mode Plus is
selected in the I/O configuration register .
- I/O IOH_2 — I/O Handler input/output 2.
LPC11U37HFB D64/401 only.
PIO0_5/SDA/IOH_3 11 H3 16 21 [4] I; IA I/O PIO0_5 — General purpose digital input/output pin
(open-drain).
- I/O SDA — I2C-bus data input/output (open-drain).
High-current sink only if I2C Fast-mode Plus is
selected in the I/O configuration register .
- I/O IOH_3 — I/O Handler input/output 3.
LPC11U37HFB D64/401 only.
PIO0_6/USB_CONNECT/
SCK0/IOH_4 15 H6 22 29 [3] I; PU I/O PIO0_6 — General purpose di gital input/o utput pin.
-OUSB_CONNECTSignal used to switch an external
1.5 k resistor under software control. Used with the
SoftConnect USB feature.
- I/O SCK0 — Serial clock for SSP0.
- I/O IOH_4 — I/O Handler input/output 4.
LPC11U37HFB D64/401 only.
PIO0_7/CTS/IOH_5 16 G7 23 30 [5] I; PU I/O PIO0_7 — General purpose digital input/output pin
(high-current output driver).
-ICTSClear To Send in put for USART.
- I/O IOH_5 — I/O Handler input/output 5.
(LPC11U37HFB D64/401 only. )
PIO0_8/MISO0/
CT16B0_MAT0/R/IOH_6 17 F8 27 36 [3] I; PU I/O PIO0_8 — General purpose digital input/output pin.
- I/O MISO0Master In Slave Out for SSP0.
-OCT16B0_MAT0 — Match output 0 for 16-bit timer 0.
- - Reserved.
- I/O IOH_6 — I/O Handler input/output 6.
(LPC11U37HFB D64/401 only. )
PIO0_9/MOSI0/
CT16B0_MAT1/R/IOH_7 18 F7 28 37 [3] I; PU I/O PIO0_9 — General purpose digital input/output pin.
- I/O MOSI0Master Out Slave In for SSP0.
-OCT16B0_MAT1 — Match output 1 for 16-bit timer 0.
- - Reserved.
- I/O IOH_7 — I/O Handler input/output 7.
(LPC11U37HFB D64/401 only. )
Table 3. Pin description
Symbol
Pin HVQFN33
Pin TFBGA48
Pin LQFP48
Pin LQFP64
Reset
state
[1]
Type Description
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 12 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
SWCLK/PIO0_10/SCK0/
CT16B0_MAT2 19 E7 29 38 [3] I; PU I SWCLK — Serial wire clock and test clock TCK for
JTAG interface.
- I/O PIO0_10 — General purpose digital input/output pin.
-OSCK0 — Serial clock for SSP0.
-OCT16B0_MAT2 — Match output 2 for 16-bit timer 0.
TDI/PIO0_11/AD0/
CT32B0_MAT3 21 D8 32 42 [6] I; PU I TDITest Data In for JTAG interface.
- I/O PIO0_11 — General purpose digital input/output pin.
-IAD0 — A/D converter, input 0.
-OCT32B0_MAT3 — Match output 3 for 32-bit timer 0.
TMS/PIO0_12/AD1/
CT32B1_CAP0 22 C7 33 44 [6] I; PU I TMS — Test Mode Select for JTAG interface.
- I/O PIO_12 — General purpose digital input/output pin.
-IAD1 — A/D converter, input 1.
-ICT3 2B1_CAP0 — Capture input 0 for 32-bit timer 1.
TDO/PIO0_13/AD2/
CT32B1_MAT0 23 C8 34 45 [6] I; PU O TDO — Test Dat a Out for JTAG interface.
- I/O PIO0_13 — General purpose digital input/output pin.
-IAD2 — A/D converter, input 2.
-OCT32B1_MAT0 — Match output 0 for 32-bit timer 1.
TRST/PIO0_14/AD3/
CT32B1_MAT1 24 B7 35 46 [6] I; PU I TRSTTest Reset for JTAG interface.
- I/O PIO0_14 — General purpose digital input/output pin.
-IAD3 — A/D converter, input 3.
-OCT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO0_15/AD4/
CT32B1_MAT2 25 B6 39 52 [6] I; PU I/O SWDIO — Serial wire debug input/output.
- I/O PIO0_15 — General purpose digital input/output pin.
-IAD4 — A/D converter, input 4.
-OCT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO0_16/AD5/
CT32B1_MAT3/IOH_8/
WAKEUP
26 A6 40 53 [6] I; PU I/O PIO0_16 — General purpose digital input/output pin.
-IAD5 — A/D converter, input 5.
-OCT32B1_MAT3 — Match output 3 for 32-bit timer 1.
- I/O IOH_8 — I/O Handler input/output 8.
(LPC11U37HFB D64/401 only. )
-IWAKEUP — Deep power-down mode wake-up pin
with 20 ns glitch filter. Pull this pin HIGH externally
before entering Deep power-down mode, then pull
LOW to exit Deep power-down mode. A LOW-going
pulse as short as 50 ns wakes up the part.
Table 3. Pin description
Symbol
Pin HVQFN33
Pin TFBGA48
Pin LQFP48
Pin LQFP64
Reset
state
[1]
Type Description
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 13 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
PIO0_17/RTS/
CT32B0_CAP0/SCLK 30 A3 45 60 [3] I; PU I/O PIO0_17 — General purpose digital input/output pin.
-ORTSRequest To Send output for USART.
-ICT3 2B0_CAP0 — Capture input 0 for 32-bit timer 0.
- I/O SCLK — Serial clock input/output for USART in
synchronous mode.
PIO0_18/RXD/
CT32B0_MAT0 31 B3 46 61 [3] I; PU I/O PIO0_18 — General purpose digital input/output pin.
-IRXDReceiver input for USART. Used in UART ISP
mode.
-OCT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO0_19/TXD/
CT32B0_MAT1 32 B2 47 62 [3] I; PU I/O PIO0_19 — General purpose digital input/output pin.
-OTXD — T ransmitter output for USART. Used in UART
ISP mode.
-OCT32B0_MAT1 — Match output 1 for 32-bit timer 0.
PIO0_20/CT16B1_CAP0 7 F2 9 11 [3] I; PU I/O PIO0_20 — General purpose digital input/output pin.
-ICT1 6B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO0_21/CT16B1_MAT0/
MOSI1 12 G4 17 22 [3] I; PU I/O PIO0_21 — General purpose digital input/output pin.
-OCT16B1_MAT0 — Match output 0 for 16-bit timer 1.
- I/O MOSI1Master Out Slave In for SSP1.
PIO0_22/AD6/
CT16B1_MAT1/MISO1 20 E8 30 40 [6] I; PU I/O PIO0_22 — General purpose digital input/output pin.
-IAD6 — A/D converter, input 6.
-OCT16B1_MAT1 — Match output 1 for 16-bit timer 1.
- I/O MISO1Master In Slave Out for SSP1.
PIO0_23/AD7/IOH_9 27 A5 42 56 [6] I; PU I/O PIO0_23 — General purpose digital input/output pin.
-IAD7 — A/D converter, input 7.
- I/O IOH_9 — I/O Handler input/output 9.
(LPC11U37HFB D64/401 only. )
PIO1_0/CT32B1_MAT0/
IOH_10 ---1
[3] I; PU I/O PIO1_0General purpose digital input/output pin.
-OCT32B1_MAT0 — Match output 0 for 32-bit timer 1.
- I/O IOH_10 — I/O Handler input/output 10.
(LPC11U37HFB D64/401 only.)
PIO1_1/CT32B1_MAT1/
IOH_11 ---17
[3] I; PU I/O PIO1_1General purpose digital input/output pin.
-OCT32B1_MAT1 — Match output 1 for 32-bit timer 1.
- I/O IOH_11 — I/O Handler input/output 11.
(LPC11U37HFB D64/401 only. )
PIO1_2/CT32B1_MAT2/
IOH_12 ---34
[3] I; PU I/O PIO1_2General purpose digital input/output pin.
-OCT32B1_MAT2 — Match output 2 for 32-bit timer 1.
- I/O IOH_12 — I/O Handler input/output 12.
(LPC11U37HFB D64/401 only.)
Table 3. Pin description
Symbol
Pin HVQFN33
Pin TFBGA48
Pin LQFP48
Pin LQFP64
Reset
state
[1]
Type Description
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 14 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
PIO1_3/CT32B1_MAT3/
IOH_13 ---50
[3] I; PU I/O PIO1_3General purpose digital input/output pin.
-OCT32B1_MAT3 — Match output 3 for 32-bit timer 1.
- I/O IOH_13 — I/O Handler input/output 13.
(LPC11U37HFB D64/401 only.)
PIO1_4/CT32B1_CAP0/
IOH_14 ---16
[3] I; PU I/O PIO1_4General purpose digital input/output pin.
-ICT3 2B1_CAP0 — Capture input 0 for 32-bit timer 1.
- I/O IOH_14 — I/O Handler input/output 14.
(LPC11U37HFB D64/401 only.)
PIO1_5/CT32B1_CAP1
/IOH_15 -H8-32
[3] I; PU I/O PIO1_5General purpose digital input/output pin.
-ICT3 2B1_CAP1 — Capture input 1 for 32-bit timer 1.
- I/O IOH_15 — I/O Handler input/output 15.
(LPC11U37HFB D64/401 only.)
PIO1_6/IOH_16 - - - 64 [3] I; PU I/O PIO1_6 — General purpose digital input/output pin.
- I/O IOH_16 — I/O Handler input/output 16.
(LPC11U37HFB D64/401 only.)
PIO1_7/IOH_17 - - - 6 [3] I; PU I/O PIO1_7General purpose di gital input/o utput pin.
- I/O IOH_17 — I/O Handler input/output 17.
(LPC11U37HFB D64/401 only.)
PIO1_8/IOH_18 - - - 39 [3] I; PU I/O PIO1_8 — General purpose digital input/output pin.
- I/O IOH_18 — I/O Handler input/output 18.
(LPC11U37HFB D64/401 only.)
PIO1_9 - - - 55 [3] I; PU I/O PIO1_9 — General purpose digital input/output pin.
PIO1_10 - - - 12 [3] I; PU I/O PIO1_10 — General purpose digital input/output pin.
PIO1_11 - - - 43 [3] I; PU I/O PIO1_11 — General purpose digital input/output pin.
PIO1_12 - - - 59 [3] I; PU I/O PIO1_12 — General purpose digital input/output pin.
PIO1_13/DTR/
CT16B0_MAT0/TXD -B83647
[3] I; PU I/O PIO1_13 — General purpose digital input/output pin.
-ODTRData Te rminal Ready output for USART.
-OCT16B0_MAT0 — Match output 0 for 16-bit timer 0.
-OTXD — Tra nsmitter output for USART.
PIO1_14/DSR/
CT16B0_MAT1/RXD -A83749
[3] I; PU I/O PIO1_14 — General purpose digital input/output pin.
-IDSRData Set Ready input for USART.
-OCT16B0_MAT1 — Match output 1 for 16-bit timer 0.
-IRXDReceiver input for USART.
PIO1_15/DCD/
CT16B0_MAT2/SCK1 28 A4 43 57 [3] I; PU I/O PIO1_15 — General purpose digital input/output pin.
IDCDData Carrier Detect input for USART.
-OCT16B0_MAT2 — Match output 2 for 16-bit timer 0.
- I/O SCK1 — Serial clock for SSP1.
Table 3. Pin description
Symbol
Pin HVQFN33
Pin TFBGA48
Pin LQFP48
Pin LQFP64
Reset
state
[1]
Type Description
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 15 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
PIO1_16/RI/
CT16B0_CAP0 -A24863
[3] I; PU I/O PIO1_16 — General purpose digital input/output pin.
-IRIRing Indicator input for USART.
-ICT1 6B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO1_17/CT16B0_CAP1/
RXD ---23
[3] I; PU I/O PIO1_17 — General purpose digital input/output pin.
-ICT1 6B0_CAP1 — Capture input 1 for 16-bit timer 0.
-IRXDReceiver input for USART.
PIO1_18/CT16B1_CAP1/
TXD ---28
[3] I; PU I/O PIO1_18 — General purpose digital input/output pin.
-ICT1 6B1_CAP1 — Capture input 1 for 16-bit timer 1.
-OTXD — Tra nsmitter output for USART.
PIO1_19/DTR/SSEL1 1 B1 2 3 [3] I; PU I/O PIO1_19 — General purpose digital input/output pin.
-ODTRData Te rminal Ready output for USART.
- I/O SSEL1 — Slave select for SSP1.
PIO1_20/DSR/SCK1 - H1 13 18 [3] I; PU I/O PIO1_20 — General purpose digital input/output pin.
-IDSRData Set Ready input for USART.
- I/O SCK1 — Serial clock for SSP1.
PIO1_21/DCD/MISO1 - G8 26 35 [3] I; PU I/O PIO1_21 — General purpose digital input/output pin.
-IDCDData Carrier Detect input for USART.
- I/O MISO1Master In Slave Out for SSP1.
PIO1_22/RI/MOSI1 - A7 38 51 [3] I; PU I/O PIO1_22 — General purpose digital input/output pin.
-IRIRing Indicator input for USART.
- I/O MOSI1Master Out Slave In for SSP1.
PIO1_23/CT16B1_MAT1/
SSEL1 -H41824
[3] I; PU I/O PIO1_23 — General purpose digital input/output pin.
-OCT16B1_MAT1 — Match output 1 for 16-bit timer 1.
- I/O SSEL1 — Slave select for SSP1.
PIO1_24/CT32B0_MAT0 - G6 21 27 [3] I; PU I/O PIO1_24 — General purpose digital input/output pin.
-OCT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_25/CT32B0_MAT1 - A1 1 2 [3] I; PU I/O PIO1_25 — General purpose digital input/output pin.
-OCT32B0_MAT1 — Match output 1 for 32-bit timer 0.
PIO1_26/CT32B0_MAT2/
RXD/IOH_19 -G21114
[3] I; PU I/O PIO1_26 — General purpose digital input/output pin.
-OCT32B0_MAT2 — Match output 2 for 32-bit timer 0.
-IRXDReceiver input for USART.
- I/O IOH_19 — I/O Handler input/output 19.
(LPC11U37HFB D64/401 only.)
PIO1_27/CT32B0_MAT3/
TXD/IOH_20 -G11215
[3] I; PU I/O PIO1_27 — General purpose digital input/output pin.
-OCT32B0_MAT3 — Match output 3 for 32-bit timer 0.
-OTXD — Tra nsmitter output for USART.
- I/O IOH_20 — I/O Handler input/output 20.
(LPC11U37HFB D64/401 only.)
Table 3. Pin description
Symbol
Pin HVQFN33
Pin TFBGA48
Pin LQFP48
Pin LQFP64
Reset
state
[1]
Type Description
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 16 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;
F = floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption.
[2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 32 for the
reset pad configuration.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 31).
[4] I2C-bus pin compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus. The pin requires an
external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines.
Open-drain configuration applies to all functions on this pin.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 31);
includes high-current output driver.
[6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 31); includes digital
input glitch filter.
[7] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode
only). This pad is not 5 V tolerant.
[8] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptib ility to noise). Leave XTALOUT floating.
PIO1_28/CT32B0_CAP0/
SCLK -H72431
[3] I; PU I/O PIO1_28 — General purpose digital input/output pin.
-ICT3 2B0_CAP0 — Capture input 0 for 32-bit timer 0.
- I/O SCLK — Serial clock input/output for USART in
synchronous mode.
PIO1_29/SCK0/
CT32B0_CAP1 -D73141
[3] I; PU I/O PIO1_29 — General purpose digital input/output pin.
- I/O SCK0 — Serial clock for SSP0.
-ICT3 2B0_CAP1 — Capture input 1 for 32-bit timer 0.
PIO1_31 - - 25 - [3] I; PU I/O PIO1_31 — General purpose digital input/output pin.
USB_DM 13 G5 19 25 [7] F-USB_DMUSB bidirectional D line.
USB_DP 14 H5 20 26 [7] F-USB_DPUSB bidirectional D+ line.
XTALIN 4 D1 6 8 [8] - - Input to the oscillator circuit and internal clock
generator circuits. Input voltage must not exceed
1.8 V.
XTALOUT 5 E1 7 9 [8] - - Output from the oscillator amplifier.
VDD 6;
29 B4;
E2 8;
44 10;
33;
48;
58
- - Supply voltage to the internal regulator, the external
rail, and the ADC. Also used as the ADC reference
voltage.
VSS 33 B5;
D2 5;
41 7;
54 - - Ground.
Table 3. Pin description
Symbol
Pin HVQFN33
Pin TFBGA48
Pin LQFP48
Pin LQFP64
Reset
state
[1]
Type Description
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 17 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
7. Functional description
7.1 On-chip flash programming memory
The LPC11U3x contain up to 128 kB on-chip flash program memory. The flash can be
programmed using In-System Programming (ISP) or In-Application Programming (IAP)
via the on-chip boot loader software.
The flash memor y is divide d int o 4 kB sect ors with each sector consisting of 16 pages.
Individual pages can be erased using the IAP erase page command.
7.2 EEPROM
The LPC11U3x contain 4 kB of on-chip byte-erasable and byte-programmable EEPROM
data memor y . The EEPROM can be pr ogrammed using In-Application Programming (I AP)
via the on-chip boot loader software.
7.3 SRAM
The LPC11U3x contain a total of 8 kB, 10 kB, or 12 kB on-chip static RAM memory.
On the LPC11U37HFBD64/401, the 2 kB SRAM1 region at location 0x2000 0000 to
0x2000 07FFF is used for the I/O Handler software library. Do not use this memory
location for data or other user code.
7.4 On-chip ROM
The on-chip ROM contains the boot loader and the following Applicatio n Prog ra m min g
Interfaces (APIs):
In-System Programming (ISP) and In-Application Programming (IAP) support for flash
including IAP erase page command.
IAP support for EEPROM
USB API
Power profiles for configuring power consumption and PLL settings
32-bit integer division routines
7.5 Memory map
The LPC11U3x incorporates several distinct memory regions, shown in the following
figures. Figure 6 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB (Advance d High-performance Bus) peripheral area is 2 MB in size and is divided
to allow for up to 128 peripherals. The APB (Advanced Peripheral Bus) peripheral area is
512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either
type is allocated 16 kB of space. This ad d ressing scheme allows simplifying the address
decoding for each peripheral.
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 18 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
7.6 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0. The tight
coupling to the CPU allows for low interrupt latency and ef ficient processing of late ar riving
interrupts.
7.6.1 Features
Controls system exceptions and peripheral interrupts.
In the LPC11U3x, the NVIC supports 24 vectored interrupts.
Fig 6. LPC11U3x memory map
APB peripherals
0x4000 4000
0x4000 8000
0x4000 C000
0x4001 0000
0x4001 8000
0x4002 0000
0x4002 8000
0x4003 8000
0x4003 C000
0x4004 0000
0x4004 4000
0x4004 8000
0x4004 C000
0x4004 C000
0x4005 8000
0x4005 C000
0x4006 0000
0x4006 4000
0x4008 0000
0x4002 4000
0x4001 C000
0x4001 4000
0x4000 0000
WWDT
32-bit counter/timer 0
32-bit counter/timer 1
ADC
USART/SMART CARD
PMU
I
2
C-bus
20 - 21 reserved
10 - 13 reserved
reserved
reserved
25 - 31 reserved
0
1
2
3
4
5
6
7
8
9
16
15
14
17
18
reserved
reserved
0x0000 0000
0 GB
0.5 GB
4 GB
1 GB
0x1000 0000
0x1FFF 0000
0x1FFF 4000
0x2000 0000
0x5000 0000
0x5000 4000
0xFFFF FFFF
reserved
reserved
reserved
2 kB USB RAM (LPC11U34/421
LPC11U35/401/501
LPC11U36/401/501
LPC11U37/401/501,
LPC11U37H/401)
reserved
0x4000 0000
0x4008 0000
0x4008 4000
APB peripherals
USB
GPIO
0x2000 4000
0x2000 4800
0x1000 2000
8 kB SRAM0 (LPC11U3x)
LPC11U3x
0x0000 A000
40 kB on-chip flash (LPC11U34/311)
0x0000 C000
48 kB on-chip flash (LPC11U34/421)
0x0001 0000
64 kB on-chip flash (LPC11U35)
0x0001 8000
96 kB on-chip flash (LPC11U36)
0x0002 0000
128 kB on-chip flash (LPC11U37/7H)
16 kB boot ROM
0x0000 0000
0x0000 00C0
active interrupt vectors
002aag813
reserved
reserved
SSP0
SSP1
16-bit counter/timer 1
16-bit counter/timer 0
IOCON
system control
19 GPIO interrupts
22
23 GPIO GROUP0 INT
24 GPIO GROUP1 INT
flash/EEPROM controller
0xE000 0000
0xE010 0000
private peripheral bus
2 kB SRAM1 (LPC11U35/501
LPC11U37/501)
I/O Handler code area
for LPC11U37HFBD64/401
0x2000 0800
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 19 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Four programmable interrupt priority levels, with hardware priority level masking.
Software interrupt generation.
7.6.2 Interrupt sources
Each peripheral de vice has one interrupt line conn ected to the NVIC but can have seve ral
interrupt flags. Individual interrupt flags can also represent more than one interrupt
source.
7.7 IOCON block
The IOCON block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Connect peripherals to the appropriate pins before activating the peripheral and before
enabling any related interrupt. Activity of any enabled peripheral function that is not
mapped to a related pin is treated as undefined.
7.7.1 Features
Programmable pull-up, pull-down, or repeater mode.
All GPIO pins (except PIO0_4 and PIO0_5) are pulle d up to 3.3 V (VDD = 3.3 V) if their
pull-up resistor is enabled.
Programmable pseudo open-drain mode.
Programmable 10 ns glitch filter on pins PIO0_22, PIO0_23, and PIO0_11 to
PIO0_16. The glitch filter is turned on by default.
Programmable hysteresis.
Programmable input inverter.
7.8 General-Purpose Input/Output GPIO
The GPIO registe rs con tro l de vice pin fu nct ion s tha t ar e no t co nn ec te d to a sp ecific
peripheral function. Pins can be dynamically configured as inputs or outputs. Multiple
outputs can be set or cleared in one write operation.
LPC11U3x use accelerated GPIO functions:
GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing
can be achieved .
Entire port value can be written in one instruction.
Any GPIO pin providing a digital function can be programmed to generate an interrupt on
a level, a rising or falling edge, or both.
The GPIO block consists of three parts:
1. The GPIO ports.
2. The GPIO pin interrupt block to control eight GPIO pins selected as pin interrupts.
3. Two GPIO group interrupt blocks to control two combined interrupts from all GPIO
pins.
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Product data sheet Rev. 2.2 — 11 March 2014 20 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
7.8.1 Features
GPIO pins can be configured as input or output by software.
All GPIO pins default to inputs with interrupt disabled at reset.
Pin registers allow pins to be sensed and set individually.
Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or
level-sensitive GPIO interrupt request.
Any pin or pins in each port can trigger a port interrupt.
7.9 USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports
hot-plugging and dynamic configuration of the devices. The host controller initiates all
transactions.
The LPC11U3x USB interface consists of a full-speed device controller with on-chip PHY
(PHYsical layer) for device functions.
Remark: Configure the LPC11U3x in default power mode with the power profiles before
using the USB (see Section 7.18.5.1). Do not use the USB with the part in performance,
efficiency, or low-power mode.
7.9.1 Full-speed USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, and endpoint buffer memory. The
serial interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via
status registers. If enabled, an interrupt is generated.
7.9.1.1 Features
Dedicated USB PLL available.
Fully compliant with USB 2.0 specification (full speed).
Supports 10 physical (5 logical) endpoints including one control endpoint.
Single and double buffering supported.
Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.
Supports wake-up from Deep-sleep mode and Power-down mode on USB activity
and remote wake-up.
Supports SoftConnect.
7.10 I/O Handler (LPC11U37HFBD64/401 only)
The I/O Handler is a software library-supported hardware engine for emulating serial
interfaces and off-loading the CPU for processing-intensive functions. The I/O Handler
can emulate, among others, DMA and serial interfaces such as UART, I2C, or I2S with no
or very low additional CPU load. The software libraries are available with supporting
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Product data sheet Rev. 2.2 — 11 March 2014 21 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
application notes from NXP (see http://www.LPCware.com.) LPCXpres so , Keil, and IAR
IDEs are supported. I/O Handler library code must be executed fro m the memory area
0x2000 0000 to 0x2000 07FF. This memory is not available for other use.
For application examples, see Section 11.8 “I/O Handler software library applications.
Each I/O Handler libra ry us es a sp ecif ic sub se t of I/O Han dle r pin s and in som e case s
other pins and peripherals such as the counter/timers.
7.11 USART
The LPC11U3x contains one USART.
The USART includes full modem control, support for synchronous mode, and a smart
card interface. The RS-485/9-bit mode allows both software address detection and
automatic address detection using 9-bit mode.
The USART uses a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.11.1 Features
Maximum USART data bit rate of 3.125 Mbit/s.
16 byte receive and tran sm it FI FO s.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
Support for RS-4 85 /9 -b it mo d e.
Support for modem control.
Support for synchronous mode.
Includes smart card interface.
7.12 SSP serial I/O controller
The SSP controllers operate on a SSP, 4-wire SSI, or Microwire bus. The controller can
interact with multiple masters and slaves on the bus. Only a sing le mas ter an d a sing le
slave can communicate on the bus during a given data transfer. The SSP supports full
duplex transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave
and from the slave to the master. In practice, often only one of these data flows carries
meaningful data.
7.12.1 Features
Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
Compatible with Motorola SPI (Serial Peripheral Interface), 4-wire Texas Instruments
SSI (Serial Synchronous Interface), and National Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
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NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
7.13 I2C-bus serial I/O controller
The LPC11U3x contain one I2C-bus controller.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a r eceiver-o nly device ( e.g., an LCD driver) or a tra nsmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can oper ate in eithe r master or sl ave mo de, dependin g on wheth er the chip has
to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, and
more than one bus master connected to the interface ca n be con tro lle d the bu s.
7.13.1 Features
The I2C-interface is an I2C-bus compliant interface with open-drain pins. The I2C-bus
interface supports Fast-mode Plus with bit rates up to 1 Mbit/s.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mech anism to suspend and
resume serial transfer.
The I2C-bus can be used for test and diagnostic purpose s.
The I2C-bus controller support s multiple ad dress recognition and a bus monitor mode.
7.14 10-bit ADC
The LPC1 1U3x contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
7.14.1 Features
10-bit successive approximation ADC.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 V to VDD.
10-bit conver sio n time 2.44 s (up to 400 kSamples/s).
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or timer match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
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Product data sheet Rev. 2.2 — 11 March 2014 23 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
7.15 General purpose external event counter/timers
The LPC11U3x includes two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to tr ap the timer value
when an input signal transitions, optionally generating an interrupt.
7.15.1 Features
A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
Counter or timer op er a tion .
Up to two capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event can also generate an interrupt.
Four match registers per timer tha t allow :
Continuous operation with optional interrupt generation on match.
Stop timer on match with optional interrupt generation.
Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
Set LOW on match.
Set HIGH on match.
Toggle on match.
Do nothing on match.
The timer and prescaler can be configured to be cleared on a designated capture
event. This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
7.16 System tick timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exc ep tion at a fixed time interval (typically 10 ms).
7.17 Windowed WatchDog Timer (WWDT)
The purpose of the WWDT is to prevent an unre sponsive system state. If software fails to
update the watchdog within a programmable time window, the watchdog resets the
microcontroller
7.17.1 Features
Internally resets chip if not periodically reloaded during the programmable time-out
period.
Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
Optional warning interrupt can be g enerated at a programmable time before watchdog
time-out.
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Product data sheet Rev. 2.2 — 11 March 2014 24 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Software enables the WWDT, but a hardware reset or a watchdog reset/interrupt is
required to disable the WWDT.
Incorrect feed sequence causes reset or interrupt, if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in
multiples of Tcy(WDCLK) 4.
The W atchdog Clock (WDCLK) source can be selected from the IRC or the dedica ted
watchdog oscillator (WDO). The clock source selection provides a wide range of
potential timing choices of watchdog operation under different power conditions.
7.18 Clocking and power control
7.18.1 Integrated oscillators
The LPC11U3x include three independent oscillators: the system oscillator, the Internal
RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more
than one purpose as required in a particular application.
Following reset, the LPC11U3x operates from the internal RC oscillator until software
switches to a different clock source. The IRC allows the system to operate without any
external crystal and the bootloader code to operate at a known frequency.
See Figure 7 for an overview of the LPC11U3x clock generation.
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Product data sheet Rev. 2.2 — 11 March 2014 25 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
7.18.1.1 Internal RC oscillator
The IRC can be used as the clock source for the WDT, and/or as the clock that drives the
system PLL and then the CPU. The nominal IRC frequency is 12 MHz.
Upon power-up, any chip reset, or wa ke-up fr om Deep power-down mode, the LPC11U3x
use the IRC as the clock source. Software can later switch to one of the other available
clock sources.
Fig 7. LPC11U3x clock ing generation block diagram
system oscillator
watchdog oscillator
IRC oscillator
USB PLL
USBPLLCLKSEL
(USB clock select)
SYSTEM CLOCK
DIVIDER
SYSAHBCLKCTRLn
(AHB clock enable)
CPU, system control,
PMU
memories,
peripheral clocks
SSP0 PERIPHERAL
CLOCK DIVIDER SSP0
SSP1 PERIPHERAL
CLOCK DIVIDER SSP1
USART PERIPHERAL
CLOCK DIVIDER UART
WDT
WDCLKSEL
(WDT clock select)
USB 48 MHz CLOCK
DIVIDER USB
USBUEN
(USB clock update enable)
watchdog oscillator
IRC oscillator
system oscillator CLKOUT PIN CLOCK
DIVIDER CLKOUT pin
CLKOUTUEN
(CLKOUT update enable)
002aaf892
system clock
SYSTEM PLL
IRC oscillator
system oscillator
watchdog oscillator
MAINCLKSEL
(main clock select)
SYSPLLCLKSEL
(system PLL clock select)
main clock
IRC oscillator
n
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NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
7.18.1.2 System oscillator
The system oscillator can be used as the clock source for the CPU, with or without using
the PLL. On the LPC11U3x, use the system oscillator to provide the clock source to USB.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
7.18.1.3 Watchdog oscillator
The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable betwee n 9.4 kHz and 2.3 MHz. The frequency spread over p rocessing and
temperature is 40 % (see also Table 13).
7.18.2 System PLL and USB PLL
The LPC11U3x contain a system PLL and a dedicated PLL for generating the 48 MHz
USB clock. The system and USB PLLs are identical.
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz. To support this frequency range, an additional divider keeps the
CCO within its frequency range while the PLL is providing the desired output frequency.
The output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. The
PLL output frequency must be lower than 100 MHz. Since the minimum output divider
value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off
and bypassed following a chip reset. Software can enable the PLL later. The program
must configure and activate the PLL, wait for the PLL to lock, and then connect to th e PLL
as a clock source. The PLL settling time is 100 s.
7.18.3 Clock output
The LPC11U3x feature a clock output function that routes the IRC oscillator, the system
oscillator, the watchdog oscillator, or the main clock to an output pin.
7.18.4 Wake-up process
The LPC11U3x begin operation by using the 12 MHz IRC oscillator as the clock source at
power-up and when awakened from Deep power-down mode . This mechanism allows
chip operation to resume quickly. If the application uses the main oscillator or the PLL,
software must enable these components and wait for them to stabilize. Only then can the
system use the PLL and main oscillator as a clock source.
7.18.5 Power control
The LPC11U 3 x sup p or t var iou s po we r con tr ol features. There ar e fo ur spe cial m od es of
processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode. The CPU clock rate can also be controlled as needed by
changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider
value. This power control mechanism allows a trade-of f of power versus processing speed
based on application require ments. In addition, a register is provide d for shutting down the
clocks to individual on-chip peripherals. This register allows fine-tuning of power
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32-bit ARM Cortex-M0 microcontroller
consumption by eliminating all dynamic power use in any pe ripherals that are not required
for the application. Selecte d peri pherals have their own clock divider which provides even
better power control.
7.18.5.1 Power profiles
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC11U3x for one of the following power modes:
Default mode corresponding to power configuration after reset.
CPU performance mode corresponding to optimized processing capability.
Efficie ncy mode corresponding to optimi zed balance of current consumption and CPU
performance.
Low-current mode corresponding to lowest power consumption.
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
Remark: When using the USB, configure the LPC11U3x in Default mode.
7.18.5.2 Sleep mode
When Sleep mode is entered, the clock to the core is stoppe d. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and can generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, by memory systems and related controllers, and by
internal buses.
7.18.5.3 Deep-sleep mode
In Deep-sleep mode, the LPC11U3x is in Sleep-mode and all peripheral clocks and all
clock sources are off except for the IRC. The IRC output is disabled unless the IRC is
selected as input to the watchdog timer. In addition all analog blocks are shut down and
the flash is in stan d-by mode. In Deep-sleep m ode, the application can keep the watchdog
oscillator and the BOD circuit running for self-timed wake-up and BOD protection.
The LPC11U3x can wake up from Deep-sleep mode via reset, selected GPIO pins, a
watchdog timer interrupt, or an interrupt generating USB port activity.
Deep-sleep mode saves power and allows for short wake-up times.
7.18.5.4 Power-down mode
In Power-down mode, the LPC11U3x is in Sleep-mode and all peripheral clocks and all
clock sources are off ex cept for watchdog oscillator if selected. In addition all analog
blocks and the flash are shut down. In Power-down mode, the application can keep the
BOD circuit running for BOD protection.
The LPC11U3x can wake up from Power-down mode via reset, selected GPIO pins, a
watchdog timer interrupt, or an interrupt generating USB port activity.
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32-bit ARM Cortex-M0 microcontroller
Power-down mode reduces power consumption compared to Deep-sleep mode at the
expense of longer wake-up times.
7.18.5.5 Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP
pin. The LPC11U3x can wake up from Deep power-down mode via the WAKEUP pin.
The LPC11U3x can be prevented from entering Deep power-down mode by setting a lock
bit in the PMU b lock. Locking out Deep powe r-down mode enables the application to keep
the watchdog timer or the BOD running at all times.
When entering Deep power-down mode, an external pull-up resistor is required on the
W AKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in
Deep power-down mode.
7.18.6 System control
7.18.6.1 Reset
Reset has four sources on the LPC11U3x: the RESET pin, the Watchdog reset, power-o n
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip re set by a ny source, on ce the ope ratin g voltage attains
a usable level, starts the IRC and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
In Deep power-down mode, an external pull-up resistor is required on the RESET pin.
7.18.6.2 Brownout detection
The LPC11U3x includes up to four levels for monitoring the voltage on the VDD pin. If this
voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the
NVIC. This signal can be enabled fo r interrupt in the In terrupt Enable Registe r in the NVIC
to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a
dedicated statu s register. Four threshold levels can be selected to cause a forced reset of
the chip.
7.18.6.3 Code security (Code Read Protection - CRP)
CRP provides different levels of security in the system so that access to the on-chip flash
and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be
restricted. Programming a specific pattern into a dedicated flash location invokes CRP.
IAP commands are not affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details, see the LPC11Uxx user manual.
There are three levels of Code Read Protection:
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32-bit ARM Cortex-M0 microcontroller
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is requ ired and flash field u pdates are needed b ut all sectors cannot
be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected, fully disables any acce ss to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin as well. If necessary, the application must provide a flash update
mechanism using IAP calls or using a call to the reinvoke ISP command to enable
flash update via the USART.
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details, see the LPC11Uxx user manual.
7.18.6.4 APB interface
The APB peripherals are located on one APB bus.
7.18.6.5 AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the ROM.
7.18.6.6 External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
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NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
7.19 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are
supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is
configured to support up to four breakpoints and two watch points.
The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the
LPC11U3x is in reset.
To perform boundary scan testing, follow these steps:
1. Erase any user code residing in flash.
2. Power up the part with the RESET pin pulled HIGH externally.
3. Wait for at least 250 s.
4. Pull the RESET pin LOW externally.
5. Perform boundary scan operations.
6. Once the boundary scan opera tions are completed, assert the TRST pin to enable the
SWD debug mode, and release the RESET pin (pull HIGH).
Remark: The JTAG interface cannot be used for debug purposes.
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NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
8. Limiting values
[1] The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not
guaranteed. The conditions for functional operation are specified in Table 5.
[2] Maximum/minimum voltage above the maximum operating voltage (see Table 5) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3] See Table 6 for maximum operating voltage.
[4] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down.
[5] Including voltage on outputs in 3-state mode.
[6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined
based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.
[7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter Conditions Min Max Unit
VDD supply voltage (core and
external rail) [2] 0.5 +4.6 V
VIinput voltage 5 V tolerant digital I/O pins;
VDD 1.8 V [5][2] 0.5 +5.5 V
VDD = 0 V 0.5 +3.6 V
5 V tolerant open-drain pins
PIO0_4 and PIO0_5 [2][4] 0.5 +5.5
VIA analog input voltage pin configured as analog input [2]
[3] 0.5 4.6 V
IDD supply current per supply pin - 100 mA
ISS ground current per ground pin - 100 mA
Ilatch I/O latch-up current (0.5VDD) < VI < (1.5VDD);
Tj < 125 C-100mA
Tstg storage temperature non-operating [6] 65 +150 C
Tj(max) maximum junction
temperature -150C
Ptot(pack) total power dissipation (per
package) based on package heat
transfer, not device power
consumption
-1.5W
VESD electrostatic discharge
voltage human body model; all pins [7] -+6500V
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Product data sheet Rev. 2.2 — 11 March 2014 32 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
9. Static characteristics
Table 5. Static characteristics
Tamb =
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
VDD supply voltage (core
and external rail) [2] 1.8 3.3 3.6 V
IDD supply current Active mode; VDD =3.3V;
Tamb =25C; code
while(1){}
executed from flash;
system clock = 12 MHz [3][4][5]
[6][7][8] -2-mA
system clock = 50 MHz [4][5][6]
[7][8][9] -7-mA
Sleep mode;
VDD = 3.3 V; Tamb =25C;
system clock = 12 MHz
[3][4][5]
[6][7][8] -1-mA
Deep-sleep mode ; VDD = 3.3 V;
Tamb =25C[4][7] -300-A
Power-down mode; VDD =3.3V;
Tamb =25C-2-A
Deep power-down mode;
VDD =3.3V; T
amb =25C[10] -220-nA
Standard port pins, RESET
IIL LOW-level input current VI= 0 V; on-chip pull-up resistor
disabled - 0.5 10 nA
IIH HIGH-level input
current VI=V
DD; on-chip pull-down resisto r
disabled - 0.5 10 nA
IOZ OFF-state output
current VO=0V; V
O=V
DD; on-chip
pull-up/down resistors disabled - 0.5 10 nA
VIinput voltage pin configured to provide a digital
function; VDD 1.8 V [11]
[12] 0- 5.0V
VDD = 0 V 0 - 3.6 V
VOoutput voltage output active 0 - VDD V
VIH HIGH-level input
voltage 0.7VDD --V
VIL LOW-level input voltage - - 0.3VDD V
Vhys hysteresis voltage - 0.4 - V
VOH HIGH-level output
voltage 2.0 V VDD 3.6 V; IOH =4 mA VDD 0.4--V
1.8 V VDD < 2.0 V; IOH =3 mA VDD 0.4--V
VOL LOW-level output
voltage 2.0 V VDD 3.6 V; IOL =4 mA --0.4V
1.8 V VDD < 2.0 V; IOL =3 mA --0.4V
IOH HIGH-level output
current VOH =V
DD 0.4 V;
2.0 V VDD 3.6 V
4--mA
1.8 V VDD < 2.0 V 3--mA
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32-bit ARM Cortex-M0 microcontroller
IOL LOW-level output
current VOL =0.4V
2.0 V VDD 3.6 V 4--mA
1.8 V VDD < 2.0 V 3 - - mA
IOHS HIGH-level short-circuit
output current VOH =0V [13] --45 mA
IOLS LOW-level short-circuit
output current VOL =V
DD [13] --50mA
Ipd pull-down current VI=5V 10 50 150 A
Ipu pull-up current VI=0V;
2.0 V VDD 3.6 V
15 50 85 A
1.8 V VDD < 2.0 V 10 50 85 A
VDD <V
I<5V 0 0 0 A
High-drive output pin (PIO0_7)
IIL LOW-level input current VI= 0 V; on-chip pull-up resistor
disabled - 0.5 10 nA
IIH HIGH-level input
current VI=V
DD; on-chip pull-down resisto r
disabled - 0.5 10 nA
IOZ OFF-state output
current VO=0V; V
O=V
DD; on-chip
pull-up/down resistors disabled - 0.5 10 nA
VIinput voltage pin configured to provide a digital
function; VDD 1.8 V [11]
[12] 0- 5.0V
VDD = 0 V 0 - 3.6 V
VOoutput voltage output active 0 - VDD V
VIH HIGH-level input
voltage 0.7VDD --V
VIL LOW-level input voltage - - 0.3VDD V
Vhys hysteresis voltage 0.4 - - V
VOH HIGH-level output
voltage 2.5 V VDD 3.6 V; IOH =20 mA VDD 0.4--V
1.8 V VDD < 2.5 V; IOH =12 mA VDD 0.4--V
VOL LOW-level output
voltage 2.0 V VDD 3.6 V; IOL =4 mA --0.4V
1.8 V VDD < 2.0 V; IOL =3 mA --0.4V
IOH HIGH-level output
current VOH =V
DD 0.4 V;
2.5 V VDD 3.6 V 20--mA
1.8 V VDD < 2.5 V 12 - - mA
IOL LOW-level output
current VOL =0.4V
2.0 V VDD 3.6 V 4--mA
1.8 V VDD < 2.0 V 3 - - mA
IOLS LOW-level short-circuit
output current VOL =V
DD [13] --50mA
Ipd pull-down current VI=5V 10 50 150 A
Table 5. Static characteristics …continued
Tamb =
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
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32-bit ARM Cortex-M0 microcontroller
Ipu pull-up current VI=0V
2.0 V VDD 3.6 V
15 50 85 A
1.8 V VDD < 2.0 V 10 50 85 A
VDD <V
I<5V 0 0 0 A
I2C-bus pins (PIO0_4 and PIO0_5)
VIH HIGH-level input
voltage 0.7VDD --V
VIL LOW-level input voltage - - 0.3VDD V
Vhys hysteresis voltage - 0.05VDD -V
IOL LOW-level output
current VOL = 0.4 V; I2C-bus pins configured
as standard mode pins
2.0 V VDD 3.6 V
3.5--mA
1.8 V VDD < 2.0 V 3 - -
IOL LOW-level output
current VOL = 0.4 V; I2C-bus pins configured
as Fast-mode Plus pins
2.0 V VDD 3.6 V
20--mA
1.8 V VDD < 2.0 V 16 - -
ILI input leakage current VI=V
DD [14] - 24A
VI=5V - 10 22 A
Oscillator pins
Vi(xtal) crystal input voltage 0.5 1.8 1.95 V
Vo(xtal) crystal output voltage 0.5 1.8 1.95 V
USB pins
IOZ OFF-state output
current 0V<V
I<3.3V [2] --10 A
VBUS bus supply voltage [2] --5.25V
VDI differential input
sensitivity voltage (D+) (D)[2] 0.2--V
VCM differential common
mode voltage range includes VDI range [2] 0.8 - 2.5 V
Vth(rs)se single-ended receiver
switching threshold
voltage
[2] 0.8 - 2.0 V
VOL LOW-level output
voltage for low-/full-speed;
RL of 1.5 k to 3.6 V [2] --0.18V
VOH HIGH-level output
voltage driven; for low-/full-speed;
RL of 15 k to GND [2] 2.8 - 3.5 V
Ctrans transceiver capacitance pin to GND [2] --20pF
ZDRV driver output
impedance for driver
which is not high-speed
capable
with 33 series resistor; steady state
drive [15][2] 36 - 44.1
Table 5. Static characteristics …continued
Tamb =
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
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NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] For USB operation 3.0 V VDD 3.6 V. Guaranteed by design.
[3] IRC enabled; system oscillator disabled; system PLL disabled.
[4] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[5] BOD disabled.
[6] All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to USART, SSP0/1 disabled in the SYSCON block.
[7] USB_DP and USB_DM pulled LOW externally.
[8] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.
[9] IRC disabled; system oscillator enabled; system PLL enabled.
[10] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode.
[11] Including voltage on outputs in 3-state mode.
[12] 3-state outputs go into 3-state mode in Deep power-down mode.
[13] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[14] To VSS.
[15] Includes external resistors of 33 1 % on USB_DP and USB_DM.
Pin capacitance
Cio input/output
capacitance pins configured for analog function - - 7.1 pF
I2C-bus pins (PIO0_4 and PIO0_5) - - 2.5 pF
pins configured as GPIO - - 2.8 pF
Table 5. Static characteristics …continued
Tamb =
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
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Product data sheet Rev. 2.2 — 11 March 2014 36 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
[1] The ADC is monotonic, there are no missing codes.
[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 8.
[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 8.
[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 8.
[5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 8.
[6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 8.
[7] Tamb = 25 C; maximum sampling frequency fs = 400 kSamples/s and analog input capacitance Cia = 1 pF.
[8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs Cia).
Table 6. ADC static characteristics
Tamb =
40
C to +85
C unless otherwise specified; ADC frequen cy 4.5 MHz, VDD = 2.5 V to 3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
VIA analog input vol tage 0 - VDD V
Cia analog input capacitance - - 1 pF
EDdifferential linearity error [1][2] --1LSB
EL(adj) integral non-linearity [3] --1.5 LSB
EOoffset error [4] --3.5 LSB
EGgain error [5] --0.6%
ETabsolute er ror [6] --4LSB
Rvsi voltage source interface
resistance --40k
Riinput resistance [7][8] --2.5M
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Product data sheet Rev. 2.2 — 11 March 2014 37 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 8. ADC characteristics
002aaf426
1023
1022
1021
1020
1019
(2)
(1)
10241018 1019 1020 1021 1022 1023
7123456
7
6
5
4
3
2
1
0
1018
(5)
(4)
(3)
1 LSB
(ideal)
code
out
VDD VSS
1024
offset
error
EO
gain
error
EG
offset error
EO
VIA (LSBideal)
1 LSB =
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Product data sheet Rev. 2.2 — 11 March 2014 38 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
9.1 BOD static characteristics
[1] Interrupt levels are selected by writing the level value to the BOD control register BODCT RL, see the
LPC11Uxx user manual.
9.2 Power consumption
Power measurement s in Active, Sleep , and Deep-sleep mod es were performed under the
following conditions (see the LPC11Uxx user manu al):
Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
Configure GPIO pins as outputs using the GPIOnDIR registers.
Write 0 to all GPIOnDATA registers to drive the outputs LOW.
Table 7. BOD static characteristics[1]
Tamb =25
C.
Symbol Parameter Conditions Min Typ Max Unit
Vth threshold voltage interrupt level 1
assertion - 2.22 - V
de-assertion - 2.35 - V
interrupt level 2
assertion - 2.52 - V
de-assertion - 2.66 - V
interrupt level 3
assertion - 2.80 - V
de-assertion - 2.90 - V
reset level 0
assertion - 1.46 - V
de-assertion - 1.63 - V
reset level 1
assertion - 2.06 - V
de-assertion - 2.15 - V
reset level 2
assertion - 2.35 - V
de-assertion - 2.43 - V
reset level 3
assertion - 2.63 - V
de-assertion - 2.71 - V
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Product data sheet Rev. 2.2 — 11 March 2014 39 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Conditions: Tamb = 25 C; Active mode entered executing code
while(1){}
from flash;
internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the
SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode; USB_DP and
USB_DM pulled LOW externally.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 9. Typical supply current versus regulator supply voltage VDD in active mode
Conditions: VDD = 3.3 V; Active mode entered executing code
while(1){}
from flash; internal
pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL
register; all peripheral clocks disabled; low-current mode; USB_DP and USB_DM pulled LOW
externally.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 10. Typical supply current ver sus temperature in Active mod e
VDD (V)
1.8 3.63.02.4
002aag749
3
6
9
IDD
(mA)
0
12 MHz(1)
24 MHz(2)
36 MHz(2)
48 MHz(2)
temperature (°C)
-40 853510 60-15
002aag750
3
6
9
IDD
(mA)
0
12 MHz(1)
24 MHz(2)
36 MHz(2)
48 MHz(2)
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Product data sheet Rev. 2.2 — 11 March 2014 40 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Conditions: VDD = 3.3 V; Sleep mode entered fr om flash; internal pull-up resistors disabled; BOD
disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled;
low-current mode; USB_DP and USB_DM pulled LOW externally.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 11. Typical supply current versus temperature in Sleep mode
Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG
register; USB_DP and USB_DM pulled LOW externally.
Fig 12. Typical supply current versus temperature in Deep-sleep mode
002aag751
temperature (°C)
-40 853510 60-15
1
3
2
4
IDD
(mA)
0
12 MHz(1)
36 MHz(2)
48 MHz(2)
24 MHz(2)
002aag745
temperature (°C)
-40 853510 60-15
355
375
365
385
IDD
(μA)
345
VDD = 3.6 V
VDD = 3.3 V
VDD = 2.0 V
VDD = 1.8 V
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Product data sheet Rev. 2.2 — 11 March 2014 41 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
9.3 Peripheral power consumption
The supply current p er peripheral is measured as the differ ence in supply current between
the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG
and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both
registers and no code is executed. Mea sured on a typical sample at Tamb =25 C. Unless
noted otherwise, the system oscillator and PLL are running in both measurements.
The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz.
Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG
register; USB_DP and USB_DM pulled LOW externally.
Fig 13. Typical supply current versus temperature in Power-down mode
Fig 14. Typical supply current versus temperature in Deep power-down mode
002aag746
temperature (°C)
-40 853510 60-15
5
15
10
20
IDD
(μA)
0
VDD = 3.6 V, 3.3 V
VDD = 2.0 V
VDD = 1.8 V
002aag747
temperature (°C)
-40 853510 60-15
0.2
0.6
0.4
0.8
IDD
(μA)
0
VDD = 3.6 V
VDD = 3.3 V
VDD = 2.0 V
VDD = 1.8 V
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Product data sheet Rev. 2.2 — 11 March 2014 42 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Tabl e 8. Power consumptio n for individual analog and digital blocks
Peripheral
Typical supply current in
mA Notes
n/a 12 MHz 48 MHz
IRC 0.27 - - System oscillator running; PLL off; independent
of main clock frequency.
System oscillator
at 12 MHz 0.22 - - IRC running; PLL off; independent of main clock
frequency.
Watchdog
oscillator at
500 kHz/2
0.004 - - System oscillator running ; PLL off; independent
of main clock frequency.
BOD 0.051 - - Independent of main clock frequency.
Main PLL - 0.21 - -
ADC - 0.08 0.29 -
CLKOUT - 0.12 0.47 Main clock divided by 4 in the CLKOUTDIV
register.
CT16B0 - 0.02 0.06 -
CT16B1 - 0.02 0.06 -
CT32B0 - 0.02 0.07 -
CT32B1 - 0.02 0.06 -
GPIO - 0.23 0.88 GPIO pins configured as outputs and set to
LOW. Direction and pin state are maintained if
the GPIO is disabled in the SYSAHBCLKCFG
register.
IOCONFIG - 0.03 0.10 -
I2C - 0.04 0.13 -
ROM - 0.04 0.15 -
SPI0 - 0.12 0.45 -
SPI1 - 0.12 0.45 -
UART - 0.22 0.82 -
WWDT - 0.02 0.06 Main clock selected as clock source for the
WDT.
USB --1.2 -
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Product data sheet Rev. 2.2 — 11 March 2014 43 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
9.4 Electrical pin characteristics
Conditions: VDD = 3.3 V; on pin PIO0_7.
Fig 15. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level
output current IOH.
Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5.
Fig 16. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus
LOW-level output voltage VOL
IOH (mA)
0 60402010 5030
002aae990
2.8
2.4
3.2
3.6
VOH
(V)
2
T = 85 °C
25 °C
40 °C
VOL (V)
0 0.60.40.2
002aaf019
20
40
60
IOL
(mA)
0
T = 85 °C
25 °C
40 °C
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NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Conditions: VDD = 3.3 V; standard port pins and PIO0_7.
Fig 17. Typical LOW-level output current IOL versus LOW-level output voltage VOL
Conditions: VDD = 3.3 V; standard port pins.
Fig 18. Typical HIGH-level output voltage VOH versus HIGH-level output source curren t
IOH
VOL (V)
0 0.60.40.2
002aae991
5
10
15
IOL
(mA)
0
T = 85 °C
25 °C
40 °C
IOH (mA)
0 24168
002aae992
2.8
2.4
3.2
3.6
VOH
(V)
2
T = 85 °C
25 °C
40 °C
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Product data sheet Rev. 2.2 — 11 March 2014 45 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Conditions: VDD = 3.3 V; standard port pins.
Fig 19. Ty pical pu ll-up current Ipu versus input voltage VI
Conditions: VDD = 3.3 V; standard port pins.
Fig 20. Ty pical pu ll-down current Ipd versus input volt age VI
VI (V)
0 54231
002aae988
30
50
10
10
Ipu
(μA)
70
T = 85 °C
25 °C
40 °C
VI (V)
0 54231
002aae989
40
20
60
80
Ipd
(μA)
0
T = 85 °C
25 °C
40 °C
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Product data sheet Rev. 2.2 — 11 March 2014 46 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
10. Dynamic characteristics
10.1 Flash memory
[1] Number of program/erase cycles.
[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash
in blocks of 256 bytes.
10.2 External clock
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
Table 9. Flash ch aracteristics
Tamb =
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Nendu endurance [1] 10000 100000 - cycles
tret retention time powered 10 - - years
unpowered 20 - - years
ter erase time sector or multi ple
consecut ive sectors 95 100 105 ms
tprog programming time [2] 0.95 1 1.05 ms
Table 10. EEPROM characteristics
Tamb =
40
Cto+85
C; VDD = 2.7 V to 3.6 V. Based on JEDEC NVM qualification. Failure rate <
10 ppm for parts as specified below.
Symbol Parameter Conditions Min Typ Max Unit
Nendu endurance 100000 1000000 - cycles
tret retention time powered 100 200 - years
unpowered 150 300 - years
tprog programming
time 64 bytes - 2.9 - ms
Table 11. Dynamic characteristic: external clock
Tamb =
40
C to +85
C; VDD over specified ranges.[1]
Symbol Parameter Conditions Min Typ[2] Max Unit
fosc oscillator frequency 1 - 25 MHz
Tcy(clk) clock cycle time 40 - 1000 ns
tCHCX clock HIGH time Tcy(clk) 0.4 - - ns
tCLCX clock LOW time Tcy(clk) 0.4 - - ns
tCLCH clock rise time - - 5 ns
tCHCL clock fall time - - 5 ns
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NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
10.3 Internal oscillators
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.
Fig 21. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
tCHCL tCLCX tCHCX
Tcy(clk)
tCLCH
002aaa907
Table 12. Dynamic characteristics: IRC
Tamb =
40
C to +85
C; 2.7 V
VDD
3.6 V[1].
Symbol Parameter Conditions Min Typ[2] Max Unit
fosc(RC) internal RC oscillator
frequency - 11.88 12 12.12 MHz
Conditions: Frequency values are typical values. 12 MHz 1 % accuracy is guaranteed for
2.7 V VDD 3.6 V and Tamb =40 C to +85 C. Variations between parts may cause the IRC to
fall outside the 12 MHz 1 % accuracy specification for voltages below 2.7 V.
Fig 22. Internal RC oscillator frequ ency versus temperature
Table 13. Dynamic characteristics: Watchdog oscillator
Symbol Parameter Conditions Min Typ[1] Max Unit
fosc(int) internal oscillator
frequency DIVSEL = 0x1F, FREQSEL = 0x1
in the WDTOSCCTRL register; [2][3] -9.4-kHz
DIVSEL = 0x00, FREQSEL = 0xF
in the WDTOSCCTRL register [2][3] - 2300 - kHz
002aaf403
11.95
12.05
12.15
f
(MHz)
11.85
temperature (°C)
40 853510 6015
VDD = 3.6 V
3.3 V
3.0 V
2.7 V
2.4 V
2.0 V
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NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
[2] The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %.
[3] See the LPC11Uxx user manual.
10.4 I/O pins
[1] Applies to standard port pins and RESET pin.
10.5 I2C-bus
[1] See the I2C-bus specification UM10204 for details.
[2] Parameters are valid over operating temperature range unless otherwise specified.
[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[5] Cb = total capacitance of one bus line in pF.
[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
Table 14. Dynamic characteristics: I/O pins[1]
Tamb =
40
C to +85
C; 3.0 V
VDD
3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
trrise time pin configured as output 3.0 - 5.0 ns
tffall time pin configured as output 2.5 - 5.0 ns
Table 15. Dynamic characteristic: I 2C-bus pins[1]
Tamb =
40
C to +85
C.[2]
Symbol Parameter Conditions Min Max Unit
fSCL SCL clock
frequency Standard-mode 0 100 kHz
Fast-mode 0 400 kHz
Fast-mode Plus 0 1 MHz
tffall time [4][5][6][7] of both SDA and SCL
signals
Standard-mode
-300ns
Fast-mode 20 + 0.1 Cb300 ns
Fast-mode Plus - 120 ns
tLOW LOW period of the
SCL clock Standard-mode 4.7 - s
Fast-mode 1.3 - s
Fast-mode Plus 0.5 - s
tHIGH HIGH period of the
SCL clock Standard-mode 4.0 - s
Fast-mode 0.6 - s
Fast-mode Plus 0.26 - s
tHD;DAT data hold time [3][4][8] Standard-mode 0 - s
Fast-mode 0 - s
Fast-mode Plus 0 - s
tSU;DAT data set-up time
[9][10] Standard-mode 250 - ns
Fast-mode 100 - ns
Fast-mode Plus 50 - ns
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NXP Semiconductors LPC11U3x
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[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or
tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
Fig 23. I2C-bus pins clock timing
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Product data sheet Rev. 2.2 — 11 March 2014 50 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
10.6 SSP interface
[1] Tcy(clk) = (SSPCLKDIV (1 + SCR) CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
[2] Tamb = 40 C to 85 C.
[3] Tcy(clk) = 12 Tcy(PCLK).
[4] Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V.
Table 16. Dynamic characteristics of SPI pins in SPI mode
Symbol Parameter Conditions Min Typ Max Unit
SPI master (in SPI mode)
Tcy(clk) clock cycle time full-duplex mode [1] 50 - - ns
when only transmitting [1] 40 ns
tDS data set-up time in SPI mode
2.4 V VDD 3.6 V
[2] 15 - - ns
2.0 V VDD < 2.4 V [2] 20 ns
1.8 V VDD < 2.0 V [2] 24 - - ns
tDH data hold time in SPI mode [2] 0-- ns
tv(Q) data output valid time in SPI mode [2] --10 ns
th(Q) data output hold time in SPI mode [2] 0-- ns
SPI slave (in SPI mode)
Tcy(PCLK) PCLK cycle time 20 - - ns
tDS data set-up time in SPI mode [3][4] 0-- ns
tDH data hold time in SPI mode [3][4] 3 Tcy(PCLK) + 4 - - ns
tv(Q) data output valid time in SPI mode [3][4] --3 Tcy(PCLK) + 11 ns
th(Q) data output hold time in SPI mode [3][4] --2 Tcy(PCLK) + 5 ns
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Product data sheet Rev. 2.2 — 11 March 2014 51 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Fig 24. SSP master timing in SPI mode
SCK (CPOL = 0)
MOSI
MISO
Tcy(clk)
tDS tDH
tv(Q)
DATA VALID DATA VALID
th(Q)
SCK (CPOL = 1)
DATA VALID DATA VALID
MOSI
MISO
tDS tDH
DATA VALID DATA VALID
th(Q)
DATA VALID DATA VALID
tv(Q)
CPHA = 1
CPHA = 0
002aae829
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Product data sheet Rev. 2.2 — 11 March 2014 52 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Fig 25. SSP slave timing in SPI mode
SCK (CPOL = 0)
MOSI
MISO
Tcy(clk)
tDS tDH
tv(Q)
DATA VALID DATA VALID
th(Q)
SCK (CPOL = 1)
DATA VALID DATA VALID
MOSI
MISO
tDS tDH
tv(Q)
DATA VALID DATA VALID
th(Q)
DATA VALID DATA VALID
CPHA = 1
CPHA = 0
002aae830
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Product data sheet Rev. 2.2 — 11 March 2014 53 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
10.7 USB interface
[1] Characterized but not implemented as production test. Guaranteed by design.
Table 17 . Dynamic characteristics: USB pins (full-speed)
CL = 50 pF; Rpu = 1.5 k
on D+ to VDD; 3.0 V
VDD
3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
trrise time 10 % to 90 % 8.5 - 13.8 ns
tffall time 10 % to 90 % 7.7 - 13.7 ns
tFRFM differential rise and fall time
matching tr/t
f--109%
VCRS output signal crossover voltage 1.3 - 2.0 V
tFEOPT source SE0 interval of EOP see Figure 26 160 - 175 ns
tFDEOP source jitter for differential transition
to SE0 transition see Figure 26 2-+5ns
tJR1 receiver jitter to next transition 18.5 - +18.5 ns
tJR2 receiver jitter for paired transitions 10 % to 90 % 9-+9ns
tEOPR EOP width at receiver must accept as
EOP; see
Figure 26
[1] 82 --ns
Fig 26. Differentia l da ta-to-EOP transition skew and EOP width
aaa-009330
T
PERIOD
differential
data lines
crossover point
source EOP width: t
FEOPT
receiver EOP width: t
EOPR
crossover point
extended
differential data to
SE0/EOP skew
n T
PERIOD
+ t
FDEOP
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Product data sheet Rev. 2.2 — 11 March 2014 54 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
11. Application information
11.1 Suggested USB interface solutions
The USB device can be connected to the USB as self-powered device (see Figure 27) or
bus-powered device (see Figure 28).
On the LPC11U3x, the PIO0_3/USB_VBUS pin is 5 V tolerant only when VDD is applied
and at operating voltage level. Therefore, if the USB_VBUS function is connected to the
USB connector and the device is self-powered, the USB_VBUS pin must be protected for
situations when VDD = 0 V.
If VDD is always greater than 0 V while VBUS = 5 V, the USB_VBUS pin can be connected
directly to the VBUS pin on the USB connector.
For systems where VDD can be 0 V and VBUS is directly applied to the VBUS pin,
precautions must be taken to reduce the voltage to below 3.6 V, which is the maximum
allowable voltage on the USB_VBUS pin in this case.
One method is to use a volt age divider to connect th e USB_VBUS pin to the VBUS on the
USB connector. The voltage divider ratio should be such that the USB_VBUS pin will be
greater than 0.7VDD to indicate a logic HIGH while below the 3.6 V allow ab le ma xim u m
voltage.
For the following operating conditions
VBUSmax = 5.25 V
VDD = 3.6 V,
the voltage divider shou ld pr ov ide a reduction of 3.6 V/5.2 5 V or ~0.68 6 V.
Fig 27. USB interface on a self-powered device where USB_VBUS = 5 V
LPC1xxx
USB-B
connector
USB_DP
USB_CONNECT
soft-connect switch
USB_DM
USB_VBUS
V
SS
V
DD
R1
1.5 kΩ
RS = 33 Ω
aaa-010178
RS = 33 Ω
R2
R3
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Product data sheet Rev. 2.2 — 11 March 2014 55 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
For a bus-powered device, the VBUS signal does not need to be connected to the
USB_VBUS pin (see Figure 28). The USB_CONNECT function can additionally be
connected as sho wn in Figure 27 to prevent the USB from timing out when there is a
significant delay between power-up and handling USB traffic.
Remark: When a bus-powered circuit as shown in Figure 28 is used, configure the
PIO0_3/USB_VBUS pin for GPIO (PIO0_3) in the IOCON block to ensure that the
USB_CONNECT signal can still be controlled by software. For details on the soft-connect
feature, see the LPC11U3x user manual (Ref. 1).
Remark: When a self-powered circuit is used without connecting VBUS, configure the
PIO0_3/USB_VBUS pin for GPIO (PIO0_3) and pr ovide software that can detect the host
presence through some other mechanism before enabling USB_CONNECT and the
soft-connect feature. Enabling the soft-connect without host presence will lead to USB
compliance failure.
Fig 28. USB interface o n a bu s-powered device
LPC1xxx
V
DD
R1
1.5 kΩ
aaa-010179
USB-B
connector
USB_DP
USB_DM
V
SS
RS = 33 Ω
RS = 33 Ω
REGULATOR
VBUS
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Product data sheet Rev. 2.2 — 11 March 2014 56 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
11.2 XTAL input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommende d that the inpu t be coupled throug h a cap acitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuate s the input volt age by a facto r Ci/(Ci + Cg). In slave
mode, a minimum of 200 mV (RMS) is needed.
In slave mode, couple the input clock signal with a capacitor of 100 pF (Figure 29), with an
amplitude between 200 mV (RMS) and 1000 mV (RMS). This signal corresponds to a
square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin
in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 30 and in
Table 18 and Table 19. Since the feedback resistance is integrated on chip, only a crystal
and the capacitances CX1 and CX2 need to be connected externally in case of
fundamental mode oscillation (L, CL and RS represent the fundamental frequency).
Capacit ance CP in Figure 30 represents the p arallel package ca pacitance and must not be
larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal
manufacturer.
Fig 29. Slave mode operation of the on-chip oscillator
Fig 30. Oscillator modes and mo dels: oscillation mode of operation and external crystal
model used for CX1/CX2 evaluation
LPC1xxx
XTALIN
Ci
100 pF Cg
002aae788
002aaf424
LPC1xxx
XTALIN XTALOUT
CX2
CX1
XTAL
=CLCP
RS
L
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Product data sheet Rev. 2.2 — 11 March 2014 57 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
11.3 XTAL Printed-Circuit Board (PCB) layout guidelines
Follow these guidelines for PCB layout:
Connect the crystal on the PCB as close as possible to the oscillator input and output
pins of the chip.
Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal
use have a common ground plane.
Connect the external components to the ground plain.
To keep parasitics and the noise coupled in via the PCB as small as possible, keep
loops as small as possible.
Choose smaller values of Cx1 and Cx2 if parasit ics of the PCB layout increase.
Table 18. Recommended values for CX1/CX2 in oscillation mode (c rystal and external
components paramete rs) low frequency mode
Fundamental oscillation
frequency FOSC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1, CX2
1 MHz to 5 MHz 10 pF < 300 18 pF, 18 pF
20 pF < 300 39 pF, 39 pF
30 pF < 300 57 pF, 57 pF
5 MHz to 10 MHz 10 pF < 300 18 pF, 18 pF
20 pF < 200 39 pF, 39 pF
30 pF < 100 57 pF, 57 pF
10 MHz to 15 MHz 10 pF < 160 18 pF, 18 pF
20 pF < 60 39 pF, 39 pF
15 MHz to 20 MHz 10 pF < 80 18 pF, 18 pF
Table 19. Recommended values for CX1/CX2 in oscillation mode (c rystal and external
components parameters) high frequency mode
Fundamental oscillation
frequency FOSC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1, CX2
15 MHz to 20 MHz 10 pF < 180 18 pF, 18 pF
20 pF < 100 39 pF, 39 pF
20 MHz to 25 MHz 10 pF < 160 18 pF, 18 pF
20 pF < 80 39 pF, 39 pF
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Product data sheet Rev. 2.2 — 11 March 2014 58 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
11.4 Standard I/O pad configuration
Figure 31 shows the possible pin modes for standard I/O pins with analog input function:
Digital output driver
Digital input: Pull-up enabled/disabled
Digital input: Pull-down enabled/disabled
Digital input: Repeater mode enabled/disabled
Analog input
Fig 31. Standard I/O pad configuration
PIN
V
DD
V
DD
ESD
V
SS
ESD
strong
pull-up
strong
pull-down
V
DD
weak
pull-up
weak
pull-down
open-drain enable
output enable
repeater mode
enable
pull-up enable
pull-down enable
select data
inverter
data output
data input
select glitch
filter
analog input
select analog input
002aaf695
pin configured
as digital output
driver
pin configured
as digital input
pin configured
as analog input
10 ns RC
GLITCH FILTER
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Product data sheet Rev. 2.2 — 11 March 2014 59 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
11.5 Reset pa d configuration
11.6 ADC effective input impedance
A simplified diagram of the ADC input channels can be used to determine the effective
input impedance seen from an external voltage source. See Figure 33.
The effective input impedance, Rin, seen by the external voltage source, VEXT, is the
parallel impedance of ((1/fs x Cia) + Rmux + Rsw) and (1/fs x Cio), and can be calculate d
using Equation 1 with
fs = sampling frequency
Cia = ADC analog input capacitance
Rmux = analog mux resistance
Rsw = switch resistance
Cio = pin capacitance
(1)
Fig 32. Reset pad configuration
VSS
reset
002aaf274
VDD
VDD
VDD
Rpu ESD
ESD
20 ns RC
GLITCH FILTER PIN
Fig 33. ADC input channel
Cia
Rs
V
SS
VEXT
002aah615
ADC
COMPARATOR
ADC Block
Rin
Cio
Rmux Rsw
Source
<2 kΩ<1.3 kΩ
Rin 1
fsCia
------------------Rmux Rsw
++


1
fsCio
------------------



=
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Product data sheet Rev. 2.2 — 11 March 2014 60 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Under nominal operating condition VDD = 3.3 V and with the maximum sampling
frequency fs = 400 kHz, the parameters assume the following values:
Cia = 1 pF (max)
Rmux = 2 k (max)
Rsw = 1.3 k (max)
Cio = 7.1 pF (max)
The effective input impedance with these parameters is Rin = 308 k.
11.7 ADC usage notes
The following guidelines show how to increase the performance of the ADC in a noisy
environment beyond the ADC specifications listed in Table 6:
The ADC input trace must be short and as close as possible to the LPC11U3x chip.
Shield The ADC input traces from fast switching digital signals and noisy power
supply lines.
The ADC and the digit al core share the same p ower supply . Therefore, filter the power
supply line adequately.
To improve the ADC performance in a noisy environment, put the device in Sleep
mode during the ADC conversion.
11.8 I/O Handler software library applications
The following sections provide application examples for the I/O Handler software library.
All library examples mak e us e of th e I/O Han dle r ha rd wa re to ext en d the fu nc tio na lity of
the part through software library calls. The libraries are available on
http://www.LPCware.com.
11.8.1 I/O Handler I2S
The I/O Handler software library provides functions to emulate an I2S master transmit
interface using the I/O Handler hardware block.
The emulated I2S interface loops o ver a 1 kB buf fer, transmitting the datawords according
to the I2S protocol. Interru pts are generated every time when the first 512 bytes have been
transmitted and when the last 512 bytes have been transmitted. This a llows the ARM core
to load the free portion of the buffer with new data, thereby enabling streaming audio.
Two channels with 16-bit p er chann el are supported . Th e code size of the sof tware libra ry
is 1 kB and code must be executed from the SRAM1 memory area reserved for the I/O
Handler code.
11.8.2 I/O Handler UART
The I/O Handler UART library emulates one additional full-duplex UART. The emulated
UART can be config ur ed for 7 or 8 d ata bits, no parity, and 1 or 2 stop bits. The baud rate
is configurable up to 115200 baud. The RXD signal is available on three I/O Handler pins
(IOH_6, IOH_16, IOH_20), while TXD and CTS are available on all 21 I/O Handler pins.
The code size of the software libr ary is about 1.2 kB and code must be executed fro m the
SRAM1 memory area reserved for the I/O Handler code.
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Product data sheet Rev. 2.2 — 11 March 2014 61 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
11.8.3 I/O Handler I2C
The I/O Handler I2C library allows to have an additional I2C-bus master. I2C read, I2C write
and combined I2C r ead/write are su pported. Dat a is automatically r ead from and written to
user-defined buffers.
The I/O Handler I2C library combined with the on-chip I2C module allows to have two
distinct I2C buses, allowing to sep arate low-speed fr om high - spe e d device s or brid gin g
two I2C buses.
11.8.4 I/O Handler DMA
The I/O Handler DMA library offers DMA-like functionality. Four types of transfer are
supported: memory to memory, memory to peripheral, peripheral to memory and
peripheral to peripheral. Supported peripherals are USART, SSP0/1, ADC and GPIO.
DMA transfers can be triggered by the source/target peripheral, software, counter/timer
module CT16B1, or I/O Handler pin PIO1_6/IOH_16.
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 62 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
12. Package outline
Fig 34. Packag e outline HVQFN33 (5 x 5 x 0.85 mm)
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
MO-220
hvqfn33f_po
11-10-11
11-10-17
Unit(1)
mm
max
nom
min
0.85
0.05
0.00
0.2
5.1
4.9
3.75
3.45
5.1
4.9
3.75
3.45
0.5 3.5
A1
Dimensions (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
bc
0.30
0.18
D(1)
A(1) DhE(1) Ehee
1e2L
3.5
vw
0.1 0.1
y
0.05
0.5
0.3
y1
0.05
0 2.5 5 mm
scale
1/2 e
AC B
v
Cw
terminal 1
index area
A
A1
c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
916
32 25
24
17
8
1
X
D
E
C
BA
e2
terminal 1
index area
1/2 e
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 63 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Fig 35. Packag e outline HVQFN33 (7 x 7 x 0.85 mm)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
- - -
hvqfn33_po
09-03-17
09-03-23
Unit
mm max
nom
min
1.00
0.85
0.80
0.05
0.02
0.00 0.2 7.1
7.0
6.9
4.85
4.70
4.55
7.1
7.0
6.9 0.65 4.55 0.75
0.60
0.45 0.1
A(1)
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7 x 7 x 0.85 mm
A1b
0.35
0.28
0.23
cD
(1) DhE(1) Eh
4.85
4.70
4.55
ee
1e2
4.55
Lv
0.1
w
0.05
y
0.08
y1
0 2.5 5 mm
scale
terminal 1
index area
BA
D
E
C
y
C
y1
X
detail X
A1
A
c
b
e2
e1
e
e
AC B
vCw
terminal 1
index area Dh
Eh
L9 16
32
33
25
17
24
8
1
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Product data sheet Rev. 2.2 — 11 March 2014 64 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Fig 36. Package outline TFBGA48 (SOT1155-2)
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT1155-2 - - -
sot1155-2_po
13-06-17
13-06-19
Unit
mm
max
nom
min
1.10
0.95
0.85
0.30
0.25
0.20
0.35
0.30
0.25
4.6
4.5
4.4
4.6
4.5
4.4
0.5 3.5 0.15 0.08
A
Dimensions
TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 x 4.5 x 0.7 mm SOT1155-2
A1A2
0.80
0.70
0.65
bDEee
1
3.5
e2vw
0.05
yy
1
0.1
0 5 mm
scale
ball A1
index area
BA
D
E
A
B
C
D
E
F
H
G
24681357
b
e2
e1
e
e1/2 e
1/2 e
ball A1
index area
solder mask open area
not for solder ball
C
y
C
y1
X
detail X
AA2
A1
AC B
Ø v
CØ w
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Product data sheet Rev. 2.2 — 11 March 2014 65 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Fig 37. Package outline LQFP48 (SOT313-2)
UNIT A
max. A1A2A3bpcE
(1) eH
ELL
pZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.6 0.20
0.05 1.45
1.35 0.25 0.27
0.17 0.18
0.12 7.1
6.9 0.5 9.15
8.85 0.95
0.55 7
0
o
o
0.12 0.10.21
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT313-2 MS-026136E05 00-01-19
03-02-25
D(1) (1)(1)
7.1
6.9
HD
9.15
8.85
E
Z
0.95
0.55
D
bp
e
E
B
12
D
H
bp
E
H
vMB
D
ZD
A
ZE
e
vMA
1
48
37
36 25
24
13
θ
A1
A
Lp
detail X
L
(A )
3
A2
X
y
c
wM
wM
0 2.5 5 mm
scale
pin 1 index
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 66 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Fig 38. Package outline LQFP64 (SOT314-2)
UNIT A
max. A1A2A3bpcE
(1) eH
ELL
pZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.6 0.20
0.05 1.45
1.35 0.25 0.27
0.17 0.18
0.12 10.1
9.9 0.5 12.15
11.85 1.45
1.05 7
0
o
o
0.12 0.11 0.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT314-2 MS-026136E10 00-01-19
03-02-25
D(1) (1)(1)
10.1
9.9
HD
12.15
11.85
E
Z
1.45
1.05
D
bp
e
θ
EA1
A
Lp
detail X
L
(A )
3
B
16
c
D
H
bp
E
HA2
vMB
D
ZD
A
ZE
e
vMA
X
1
64
49
48 33
32
17
y
pin 1 index
wM
wM
0 2.5 5 mm
scale
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 67 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
13. Soldering
Fig 39. Reflow so ldering for the HVQFN33 (5x5) package
Footprint information for reflow soldering of HVQFN33 package
occupied area
solder paste
solder land
Dimensions in mm
P
0.5
002aag766
Issue date 11-11-15
11-11-20
Ax Ay Bx C D
5.95 5.95 4.25 0.85
By
4.25 0.27
Gx
5.25
Gy
5.25
Hy
6.2
Hx
6.2
SLx SLy nSPx nSPy
3.75 3.75 3 3
0.30
0.60
detail X
C
SLy
D
SLx
Bx
Ay
P
nSPy
nSPx
see detail X
Gx
Hx
GyHy By
Ax
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 68 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Fig 40. Reflow so ldering for the HVQFN33 (7x7) package
Footprint information for reflow soldering of HVQFN33 package
001aao134
occupied area
solder land
solder resist
solder land plus solder paste
solder paste deposit
Dimensions in mm
Remark:
Stencil thickness: 0.125 mm
e = 0.65
evia = 4.25
OwDtot = 5.10 OA
PID = 7.25 PA+OA
OID = 8.20 OA
0.20 SR
chamfer (4×)
0.45 DM
evia = 1.05
W = 0.30 CU
evia = 4.25
evia = 2.40
LbE = 5.80 CU
LbD = 5.80 CU
PIE = 7.25 PA+OA
LaE = 7.95 CU
LaD = 7.95 CU
OIE = 8.20 OA
OwEtot = 5.10 OA
EHS = 4.85 CU
DHS = 4.85 CU
4.55 SR
4.55 SR
B-side
(A-side fully covered)
number of vias: 20
Solder resist
covered via
0.30 PH
0.60 SR cover
0.60 CU
SEhtot = 2.70 SP
SDhtot = 2.70 SP
GapE = 0.70 SP
SPE = 1.00 SP
0.45 DM
SPD = 1.00 SP
GapD = 0.70 SP
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 69 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Fig 41. Reflow soldering for the TFBGA48 package
DIMENSIONS in mm
PSLSPSRHxHy
Hx
Hy
SOT1155-2
solder land plus solder paste
occupied area
Footprint information for reflow soldering of TFBGA48 package
solder land
solder paste deposit
solder resist
P
P
SL
SP
SR
detail X
see detail X
0.50 0.225 0.275 0.325 4.75 4.75 sot1155-2_fr
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Product data sheet Rev. 2.2 — 11 March 2014 70 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Fig 42. Reflow so ldering for the LQFP48 package
SOT313-2
DIMENSIONS in mm
occupied area
Footprint information for reflow soldering of LQFP48 package
Ax
Bx
Gx
Gy
Hy
Hx
AyBy
P1
D2 (8×)D1
(0.125)
Ax Ay Bx By D1 D2 Gx Gy Hx Hy
10.350
P2
0.560 10.350 7.350 7.350
P1
0.500 0.280
C
1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr
solder land
C
Generic footprint pattern
Refer to the package outline drawing for actual layout
P2
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Product data sheet Rev. 2.2 — 11 March 2014 71 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Fig 43. Reflow so ldering for the LQFP64 package
SOT314-2
DIMENSIONS in mm
occupied area
Footprint information for reflow soldering of LQFP64 package
Ax
Bx
Gx
Gy
Hy
Hx
AyBy
P1P2
D2 (8×) D1
(0.125)
Ax Ay Bx By D1 D2 Gx Gy Hx Hy
13.300 13.300 10.300 10.300
P1
0.500
P2
0.560 0.280
C
1.500 0.400 10.500 10.500 13.550 13.550 sot314-2_fr
solder land
C
Generic footprint pattern
Refer to the package outline drawing for actual layout
LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2.2 — 11 March 2014 72 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
14. Abbreviations
15. References
[1] LPC11U3x User manual UM10462:
http://www.nxp.com/documents/user_manual/UM10462.pdf
[2] LPC11U3x Errata sheet:
http://www.nxp.com/documents/errata_sheet/ES_LPC11U3X.pdf
Table 20. Abbreviations
Acronym Description
A/D Analog-to-Digital
ADC Analog-to-Digital Converter
AHB Advanced High-performance Bus
APB Advanced Peripheral Bus
BOD BrownOut Detection
GPIO General Purpose Input/Output
JTAG Joint Test Action Group
PLL Phase-Locked Loop
RC Resistor-Capacitor
SPI Serial Peripheral Interface
SSI Serial Synchronous Interface
SSP Synchronous Serial Port
TAP Test Access Port
USART Universal Synchronous Asynchronous Receiver /Transmitter
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Product data sheet Rev. 2.2 — 11 March 2014 73 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
16. Revision history
Table 21. Revision history
Document ID Release date Data sheet status Change notice Supersedes
LPC11U3X v.2.2 20140311 Product data sheet - LPC11U3X v.2.1
Modifications: Use of USB_CONNECT signal explained in Section 11.1 “Suggested USB interfa c e
solutions.
Open-drain I2C-bus an d RESET pin descriptions clarified. See Table 3.
LPC11U3X v.2.1 20131230 Product data sheet - LPC11U3X v.2
Modifications: Add reserved function to pins PIO0_8/MISO0/CT16B0_MAT0/R/IOH_6 and
PIO0_9/MOSI0/CT16B0_MAT1/R/IOH_7.
LPC11U3X v.2 20131125 Product data sheet - LPC11U3X v.1.1
Modifications: Part LPC11U37HFBD64/401 with I/O handler added.
Additional I/O Handler pin functions added in Table 3.
Typical range of watchdog oscillator frequency changed to 9.4 kHz to
2.3 MHz.See Table 13.
Section 11.8 “I/O Handler software library app lications” added.
Updated Section 11.1 “Sugg ested USB interface solutions” for clarity.
Condition VDD = 0 V added to Parameter VI in Table 5 for clarity.
LPC11U3X v.1.1 20130924 Product data sheet - LPC11U3X v.1
Modifications: Removed the footnote “The peak current is limited to 25 times the
corresponding maximum current.” in Table 4.
Table 3: Added “5 V tolerant pad” to RESET/PIO0_0 table note.
Table 7: Removed BOD interrupt level 0.
Programmable glitch filter is enabled by default. See Section 7.7.1.
Added Section 11.6 “ADC effective input impedance”.
Table 5 “Static characteristics” added Pin capacitance section.
Updated Section 11.1 “Suggested USB interface solutions”.
Table 4 “Limiting values”:
Updated VDD min and max.
Updated VI conditions.
Table 10 “EEPROM characteristics”:
Removed fclk and ter; the user does not have control over these
parameters.
Changed the tprog from 1.1 ms to 2.9 ms; the EEPROM IAP always
does an erase and program, thus the total program time is ter + tprog.
Changed title of Figure 29 from “USB interface on a self-powered
device” to “USB interface with soft-connect”.
Section 10.7 “USB interface” added. Parameter tEOPR1 and tEOPR2
renamed to tEOPR.
LPC11U3X v.1 20120420 Product data sheet - -
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Product data sheet Rev. 2.2 — 11 March 2014 74 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
17. Legal information
17.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental ,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
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contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Producti on This document contain s the product specification.
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Product data sheet Rev. 2.2 — 11 March 2014 75 of 77
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qualif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specif ications.
17.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
I2C-bus — logo is a trademark of NXP Semi conductors N.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Product data sheet Rev. 2.2 — 11 March 2014 76 of 77
continued >>
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
19. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3
4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 4
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10
7 Functional description . . . . . . . . . . . . . . . . . . 17
7.1 On-chip flash programming memory . . . . . . . 17
7.2 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.3 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.4 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.5 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.6 Nested Vectored Interrupt Controller
(NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.6.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 19
7.7 IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.8 General-Purpose Input/Output GPIO . . . . . . . 19
7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.9 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 20
7.9.1 Full-sp eed USB device controller . . . . . . . . . . 20
7.9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.10 I/O Handler
(LPC11U37HFBD6 4/401 only) . . . . . . . . . . . . 20
7.11 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.12 SSP serial I/O controller. . . . . . . . . . . . . . . . . 21
7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.13 I2C-bus serial I/O controller . . . . . . . . . . . . . . 22
7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.14 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.15 General purpose external event
counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 23
7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.16 System tick timer . . . . . . . . . . . . . . . . . . . . . . 23
7.17 Windowed WatchDog Timer
(WWDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.18 Clocking and power control . . . . . . . . . . . . . . 24
7.18.1 Integrated oscillators . . . . . . . . . . . . . . . . . . . 24
7.18.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 25
7.18.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 26
7.18.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 26
7.18.2 System PLL and USB PLL. . . . . . . . . . . . . . . 26
7.18.3 Clock output. . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.18.4 Wake-up process. . . . . . . . . . . . . . . . . . . . . . 26
7.18.5 Power control. . . . . . . . . . . . . . . . . . . . . . . . . 26
7.18.5.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 27
7.18.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.18.5.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 27
7.18.5.4 Power-down mode. . . . . . . . . . . . . . . . . . . . . 27
7.18.5.5 Deep power-down mode . . . . . . . . . . . . . . . . 28
7.18.6 System control. . . . . . . . . . . . . . . . . . . . . . . . 28
7.18.6.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.18.6.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 28
7.18.6.3 Code security
(Code Read Protection - CRP) . . . . . . . . . . . 28
7.18.6.4 APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 29
7.18.6.5 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.18.6.6 External interrupt inputs. . . . . . . . . . . . . . . . . 29
7.19 Emulation and debugging . . . . . . . . . . . . . . . 30
8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31
9 Static characteristics . . . . . . . . . . . . . . . . . . . 32
9.1 BOD static characteristics . . . . . . . . . . . . . . . 38
9.2 Power consumption . . . . . . . . . . . . . . . . . . . 38
9.3 Peripheral power consumption . . . . . . . . . . . 41
9.4 Electrical pin characteristics. . . . . . . . . . . . . . 43
10 Dynamic characteristics. . . . . . . . . . . . . . . . . 46
10.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 46
10.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 46
10.3 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 47
10.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.5 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.6 SSP interface. . . . . . . . . . . . . . . . . . . . . . . . . 50
10.7 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 53
11 Application information . . . . . . . . . . . . . . . . . 54
11.1 Suggested USB interface solutions . . . . . . . . 54
11.2 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11.3 XTAL Printed-Circuit Board
(PCB) layout guidelines . . . . . . . . . . . . . . . . . 57
11.4 Standard I/O pad configuration . . . . . . . . . . . 58
11.5 Reset pad configuration. . . . . . . . . . . . . . . . . 59
11.6 ADC effective input impedance . . . . . . . . . . . 59
11.7 ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 60
11.8 I/O Handler software library applications . . . . 60
11.8 .1 I/O Handler I2S. . . . . . . . . . . . . . . . . . . . . . . . 60
11.8.2 I/O Handler UART . . . . . . . . . . . . . . . . . . . . . 60
11.8 .3 I/O Handler I2C. . . . . . . . . . . . . . . . . . . . . . . . 61
11.8.4 I/O Handler DMA . . . . . . . . . . . . . . . . . . . . . . 61
NXP Semiconductors LPC11U3x
32-bit ARM Cortex-M0 microcontroller
© NXP Semiconductors N.V. 2014. All right s reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 March 2014
Document identifier: LPC11U3X
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 62
13 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 72
15 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 73
17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 74
17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 74
17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 74
17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 75
18 Contact information. . . . . . . . . . . . . . . . . . . . . 75
19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76