SST39VF1601C-70-4I-B3KE-T - Microchip Technology

Data Sheet

S71380-04-000 05/10

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

16 Mbit (x16) Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FEATURES:

• Organized as 1M x16: SST39VF1601C/1602C

• Single Voltage Read and Write Operations

– 2.7-3.6V

• Superior Reliability

– Endurance: 100,000 Cycles (Typical)

– Greater than 100 years Data Retention

• Low Power Consumption (typical values at 5 MHz)

– Active Current: 9 mA (typical)

– Standby Current: 3 µA (typical)

– Auto Low Power Mode: 3 µA (typical)

• Hardware Block-Protection/WP# Input Pin

– Top Block-Protection (top 8 KWord)

– Bottom Block-Protection (bottom 8 KWord)

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Block-Erase Capability

– Flexible block architecture; one 8-, two 4-, one

16-, and thirty one 32-KWord blocks

• Chip-Erase Capability

• Erase-Suspend/Erase-Resume Capabilities

• Hardware Reset Pin (RST#)

• Latched Address and Data

• Security-ID Feature

– SST: 128 bits; User: 128 words

• Fast Read Access Time:

– 70 ns

• Fast Erase and Word-Program:

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 40 ms (typical)

– Word-Program Time: 7 µs (typical)

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bits

– Data# Polling

– Ready/Busy# Pin

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 48-lead TSOP (12mm x 20mm)

– 48-ball TFBGA (6mm x 8mm)

– 48-ball WFBGA (4mm x 6mm)

• All devices are RoHS compliant

PRODUCT DESCRIPTION

The SST39VF1601C and SST39VF1602C devices are

1M x16 CMOS Multi-Purpose Flash Plus (MPF+) manu-

factured with SST proprietary, high performance CMOS

SuperFlash technology. The split-gate cell design and

thick-oxide tunneling injector attain better reliability and

manufacturability compared with alternate approaches.

The SST39VF160xC writes (Program or Erase) with a

2.7-3.6V power supply. These devices conform to JEDEC

standard pinouts for x16 memories.

Featuring high performance Word-Program, the

SST39VF1601C/1602C devices provide a typical Word-

Program time of 7 µsec. These devices use Toggle Bit,

Data# Polling, or the RY/BY# pin to indicate the completion

of Program operation. To protect against inadvertent write,

they have on-chip hardware and Software Data Protection

schemes. Designed, manufactured, and tested for a wide

spectrum of applications, these devices are offered with a

guaranteed typical endurance of 100,000 cycles. Data

retention is rated at greater than 100 years.

The SST39VF1601C/1602C devices are suited for applica-

tions that require convenient and economical updating of

program, configuration, or data memory. For all system

applications, they significantly improve performance and

reliability, while lowering power consumption. They inher-

ently use less energy during Erase and Program than alter-

native flash technologies. The total energy consumed is a

function of the applied voltage, current, and time of applica-

tion. Since for any given voltage range, the SuperFlash

technology uses less current to program and has a shorter

erase time, the total energy consumed during any Erase or

Program operation is less than alternative flash technolo-

gies. These devices also improve flexibility while lowering

the cost for program, data, and configuration storage appli-

cations.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose

Erase and Program times increase with accumulated

Erase/Program cycles.

To meet high density, surface mount requirements, the

SST39VF1601C/1602C are offered in 48-lead TSOP, 48-

ball TFBGA, and 48-ball WFBGA packages. See Figures

2, 3, and 4 for pin assignments.

SST39VF160x / 320x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) MPF+ memories

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asserting WE# low while keeping CE#

low. The address bus is latched on the falling edge of WE#

or CE#, whichever occurs last. The data bus is latched on

the rising edge of WE# or CE#, whichever occurs first.

The SST39VF1601C/1602C also have the Auto Low

Power mode which puts the device in a near standby mode

after data has been accessed with a valid Read operation.

This reduces the IDD active read current from typically 9 mA

to typically 3 µA. The Auto Low Power mode reduces the

typical IDD active read current to the range of 2 mA/MHz of

Read cycle time. The device exits the Auto Low Power

mode with any address transition or control signal transition

used to initiate another Read cycle, with no access time

penalty. Note that the device does not enter Auto-Low

Power mode after power-up with CE# held steadily low,

until the first address transition or CE# is driven high.

Read

The Read operation of the SST39VF1601C/1602C is

controlled by CE# and OE#, both have to be low for the

system to obtain data from the outputs. CE# is used for

device selection. When CE# is high, the chip is dese-

lected and only standby power is consumed. OE# is the

output control and is used to gate data from the output

pins. The data bus is in high impedance state when

either CE# or OE# is high. Refer to the Read cycle timing

diagram for further details (Figure 6).

Word-Program Operation

The SST39VF1601C/1602C are programmed on a word-

by-word basis. Before programming, the sector where the

word exists must be fully erased. The Program operation is

accomplished in three steps. The first step is the three-byte

load sequence for Software Data Protection. The second

step is to load word address and word data. During the

Word-Program operation, the addresses are latched on the

falling edge of either CE# or WE#, whichever occurs last.

The data is latched on the rising edge of either CE# or

WE#, whichever occurs first. The third step is the internal

Program operation which is initiated after the rising edge of

the fourth WE# or CE#, whichever occurs first. The Pro-

gram operation, once initiated, will be completed within 10

µs. See Figures 7 and 8 for WE# and CE# controlled Pro-

gram operation timing diagrams and Figure 22 for flow-

charts. During the Program operation, the only valid reads

are Data# Polling and Toggle Bit. During the internal Pro-

gram operation, the host is free to perform additional tasks.

Any commands issued during the internal Program opera-

tion are ignored. During the command sequence, WP#

should be statically held high or low.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST39VF1601C/1602C offer both Sec-

tor-Erase and Block-Erase mode.

The sector architecture is based on a uniform sector size of

2 KWord. The Block-Erase mode is based on non-uniform

block sizes—thirty-one 32 KWord, one 16 KWord, two 4

KWord, and one 8 KWord blocks. See Figure 5 for top and

bottom boot device block addresses. The Sector-Erase

operation is initiated by executing a six-byte command

sequence with Sector-Erase command (50H) and sector

address (SA) in the last bus cycle. The Block-Erase opera-

tion is initiated by executing a six-byte command sequence

with Block-Erase command (30H) and block address (BA)

in the last bus cycle. The sector or block address is latched

on the falling edge of the sixth WE# pulse, while the com-

mand (30H or 50H) is latched on the rising edge of the

sixth WE# pulse. The internal Erase operation begins after

the sixth WE# pulse. The End-of-Erase operation can be

determined using either Data# Polling or Toggle Bit meth-

ods. See Figures 12 and 13 for timing waveforms and Fig-

ure 26 for the flowchart. Any commands issued during the

Sector- or Block-Erase operation are ignored. When WP#

is low, any attempt to Sector- (Block-) Erase the protected

block will be ignored. During the command sequence,

WP# should be statically held high or low.

Erase-Suspend/Erase-Resume Commands

The Erase-Suspend operation temporarily suspends a

Sector- or Block-Erase operation thus allowing data to be

read from any memory location, or program data into any

sector/block that is not suspended for an Erase operation.

The operation is executed by issuing one byte command

sequence with Erase-Suspend command (B0H). The

device automatically enters read mode typically within 20

µs after the Erase-Suspend command had been issued.

Valid data can be read from any sector or block that is not

suspended from an Erase operation. Reading at address

location within erase-suspended sectors/blocks will output

DQ2 toggling and DQ6 at ‘1’. While in Erase-Suspend

mode, a Word-Program operation is allowed except for the

sector or block selected for Erase-Suspend.

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

To resume Sector-Erase or Block-Erase operation which has

been suspended the system must issue Erase Resume

command. The operation is executed by issuing one byte

command sequence with Erase Resume command (30H)

at any address in the last Byte sequence.

Chip-Erase Operation

The SST39VF1601C/1602C provide a Chip-Erase opera-

tion, which allows the user to erase the entire memory

array to the ‘1’ state. This is useful when the entire device

must be quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command

(10H) at address 555H in the last byte sequence. The

Erase operation begins with the rising edge of the sixth

WE# or CE#, whichever occurs first. During the Erase

operation, the only valid read is Toggle Bit or Data# Polling.

See Table 7 for the command sequence, Figure 11 for tim-

ing diagram, and Figure 26 for the flowchart. Any com-

mands issued during the Chip-Erase operation are

ignored. When WP# is low, any attempt to Chip-Erase will

be ignored. During the command sequence, WP# should

be statically held high or low.

Write Operation Status Detection

The SST39VF1601C/1602C provide two software means

to detect the completion of a Write (Program or Erase)

cycle, in order to optimize the system write cycle time. The

software detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write detection

mode is enabled after the rising edge of WE#, which ini-

tiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asyn-

chronous with the system; therefore, either a Data# Poll-

ing or Toggle Bit read may be simultaneous with the

completion of the write cycle. If this occurs, the system

may possibly get an erroneous result, i.e., valid data may

appear to conflict with either DQ7 or DQ6. In order to pre-

vent spurious rejection, if an erroneous result occurs, the

software routine should include a loop to read the

accessed location an additional two (2) times. If both

reads are valid, then the device has completed the Write

cycle, otherwise the rejection is valid.

Ready/Busy# (RY/BY#)

The devices include a Ready/Busy# (RY/BY#) output sig-

nal. RY/BY# is an open drain output pin that indicates

whether an Erase or Program operation is in progress.

Since RY/BY# is an open drain output, it allows several

devices to be tied in parallel to VDD via an external pull-up

resistor. After the rising edge of the final WE# pulse in the

command sequence, the RY/BY# status is valid.

When RY/BY# is actively pulled low, it indicates that an

Erase or Program operation is in progress. When RY/BY#

is high (Ready), the devices may be read or left in standby

mode.

Data# Polling (DQ7)

When the SST39VF1601C/1602C are in the internal Pro-

gram operation, any attempt to read DQ7 will produce the

complement of the true data. Once the Program operation

is completed, DQ7 will produce true data. Note that even

though DQ7 may have valid data immediately following the

completion of an internal Write operation, the remaining

data outputs may still be invalid: valid data on the entire

data bus will appear in subsequent successive Read

cycles after an interval of 1 µs. During internal Erase oper-

ation, any attempt to read DQ7 will produce a ‘0’. Once the

internal Erase operation is completed, DQ7 will produce a

‘1’. The Data# Polling is valid after the rising edge of fourth

WE# (or CE#) pulse for Program operation. For Sector-,

Block- or Chip-Erase, the Data# Polling is valid after the

rising edge of sixth WE# (or CE#) pulse. See Figure 9 for

Data# Polling timing diagram and Figure 23 for a flowchart.

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating ‘1’s

and ‘0’s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the DQ6 bit will

stop toggling. The device is then ready for the next opera-

tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6)

is valid after the rising edge of sixth WE# (or CE#) pulse.

DQ6 will be set to ‘1’ if a Read operation is attempted on an

Erase-Suspended Sector/Block. If Program operation is ini-

tiated in a sector/block not selected in Erase-Suspend

mode, DQ6 will toggle.

An additional Toggle Bit is available on DQ2, which can be

used in conjunction with DQ6 to check whether a particular

sector is being actively erased or erase-suspended. Table 1

shows detailed status bits information. The Toggle Bit

(DQ2) is valid after the rising edge of the last WE# (or CE#)

pulse of Write operation. See Figure 10 for Toggle Bit tim-

ing diagram and Figure 23 for a flowchart.

Note: DQ7 and DQ2 require a valid address when reading

status information.

Data Protection

The SST39VF1601C/1602C provide both hardware and

software features to protect nonvolatile data from inadvertent

writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5

ns will not initiate a write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the Write operation. This prevents inadvert-

ent writes during power-up or power-down.

Hardware Block Protection

The SST39VF1602C supports top hardware block protec-

tion, which protects the top 8 KWord block of the device.

The SST39VF1601C supports bottom hardware block pro-

tection, which protects the bottom 8KWord block of the

device. The Boot Block address ranges are described in

Table 2. Program and Erase operations are prevented on

the 8 KWord when WP# is low. If WP# is left floating, it is

internally held high via a pull-up resistor, and the Boot

Block is unprotected, enabling Program and Erase opera-

tions on that block.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the

device to read array data. When the RST# pin is held low

for at least TRP, any in-progress operation will terminate and

return to Read mode. When no internal Program/Erase

operation is in progress, a minimum period of TRHR is

required after RST# is driven high before a valid Read can

take place (see Figure 18).

The Erase or Program operation that has been interrupted

needs to be re-initiated after the device resumes normal

operation mode to ensure data integrity.

Software Data Protection (SDP)

The SST39VF1601C/1602C provide the JEDEC approved

Software Data Protection scheme for all data alteration

operations, i.e., Program and Erase. Any Program opera-

tion requires the inclusion of the three-byte sequence. The

three-byte load sequence is used to initiate the Program

operation, providing optimal protection from inadvertent

Write operations, e.g., during the system power-up or

power-down. Any Erase operation requires the inclusion of

six-byte sequence. These devices are shipped with the

Software Data Protection permanently enabled. See Table

7 for the specific software command codes. During SDP

command sequence, invalid commands will abort the

TABLE 1: Write Operation Status

Status DQ7DQ6DQ2RY/BY#

Normal

Operation

Standard

Program

DQ7# Toggle No

To g g l e

Standard

Erase

0 Toggle Toggle 0

Erase-

Suspend

Mode

Read from

Erase-

Suspended

Sector/

Block

11Toggle1

Read from

Non-Erase-

Suspended

Sector/Block

Data Data Data 1

Program DQ7# Toggle N/A 0

T1.0 1380

TABLE 2: Boot Block Address Ranges

Product Address Range

Bottom Boot Block

SST39VF1601C 00000H - 01FFFH

Top Boot Block

SST39VF1602C FE000H - FFFFFH

T2.0 1380

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

device to read mode within TRC. The contents of DQ15-DQ8

can be VIL or VIH, but no other value, during any SDP com-

mand sequence.

Common Flash Memory Interface (CFI)

The SST39VF1601C/1602C also contain the CFI informa-

tion to describe the characteristics of the device. In order

to enter the CFI Query mode, the system writes a three-

byte sequence, same as product ID entry command with

98H (CFI Query command) to address 555H in the last

byte sequence. Additionally, the system can use the one-

byte sequence with 55H on the Address and 89H on the

Data Bus to enter the CFI Query mode. Once the device

enters the CFI Query mode, the system can read CFI data

at the addresses given in Tables 8 through 10. The system

must write the CFI Exit command to return to Read mode

from the CFI Query mode.

Product Identification

The Product Identification mode identifies the devices as

the SST39VF1601C, SST39VF1602C, and manufacturer

as SST. This mode may be accessed software opera-

tions. Users may use the Software Product Identification

operation to identify the part (i.e., using the device ID)

when using multiple manufacturers in the same socket.

For details, see Table 7 for software operation, Figure 14

for the Software ID Entry and Read timing diagram and

Figure 24 for the Software ID Entry command sequence

flowchart.

Product Identification Mode Exit/

CFI Mode Exit

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. Exit is accom-

plished by issuing the Software ID Exit command

sequence, which returns the device to the Read mode.

This command may also be used to reset the device to the

Read mode after any inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. Please note that the Software ID Exit/

CFI Exit command is ignored during an internal Program or

Erase operation. See Table 7 for software command

codes, Figure 16 for timing waveform, and Figure 25 for

flowcharts.

Security ID

The SST39VF1601C/1602C devices offer a 136 Word

Security ID space. The Secure ID space is divided into two

segments—one factory programmed segment and one

user programmed segment. The first segment is pro-

grammed and locked at SST with a random 128-bit num-

ber. The user segment, with a 128 word space, is left un-

programmed for the customer to program as desired.

To program the user segment of the Security ID, the user

must use the Security ID Word-Program command. To

detect end-of-write for the SEC ID, read the toggle bits. Do

not use Data# Polling. Once this is complete, the Sec ID

should be locked using the User Sec ID Program Lock-Out.

This disables any future corruption of this space. Note that

regardless of whether or not the Sec ID is locked, neither

Sec ID segment can be erased.

The Secure ID space can be queried by executing a three-

byte command sequence with Enter Sec ID command

(88H) at address 555H in the last byte sequence. To exit

this mode, the Exit Sec ID command should be executed.

Refer to Table 7 for more details.

TABLE 3: Product Identification

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST39VF1601C 0001H 234FH

SST39VF1602C 0001H 234EH

T3.2 1380

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 1: Functional Block Diagram

FIGURE 2: Pin Assignments for 48-Lead TSOP

Y-Decoder

I/O Buffers and Data Latches

1380 B1.0

Address Buffer & Latches

X-Decoder

DQ15 - DQ0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

WP#

RESET#

RY/BY#

A16

VSS

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VDD

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

1380 48-tsop P01.0

Standard Pinout

Top View

Die Up

A15

A14

A13

A12

A11

A10

A19

WE#

RST#

WP#

RY/BY#

A18

A17

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 3: Pin Assignments for 48-Ball TFBGA

FIGURE 4: Pin Assignments for 48-Ball WFBGA

A13

WE#

RY/BY#

A12

RST#

WP#

A17

A14

A10

A18

A15

A11

A19

A16

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

1380 48-tfbga B3K P02.0

SST39VF1601C/1602C

TOP VIEW (balls facing down)

A B C D E F G H

CE#

VSS

DQ8

OE#

DQ0

A18

DQ10

DQ9

DQ1

A17

WP#

A19

DQ2

DQ3

VDD

WE#

DQ12

RST#

RY/BY#

DQ13

A10

DQ4

DQ5

DQ14

A11

A13

A12

DQ11

DQ6

DQ15

A14

A15

A16

DQ7

VSS

TOP VIEW (balls facing down)

A B C D E F G H J K L

1380 48-wfbga MAQ P03.0

SST39WF160xC

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

TABLE 4: Pin Description

Symbol Pin Name Functions

AMS1-A0Address Inputs To provide memory addresses.

During Sector-Erase AMS-A11 address lines will select the sector.

During Block-Erase AMS-A15 address lines will select the block.

DQ15-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded.

RST# Reset To reset and return the device to Read mode.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide power supply voltage: 2.7-3.6V

VSS Ground

NC No Connection Unconnected pins.

RY/BY# Ready/Busy# To output the status of a Program or Erase operation

RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required

to allow RY/BY# to transition high indicating the device is ready to read.

T4.2 1380

1. AMS = Most significant address

AMS = A19

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

TABLE 5: Top / Bottom Boot Block Address

Top Boot Block Address SST39VF1602C Bottom Boot Block Address SST39VF1601C

# Size (KWord) Address Range # Size (KWord) Address Range

34 8 FE000H-FFFFFH 34 32 F8000H-FFFFFH

33 4 FD000H-FDFFFH 33 32 F0000H-F7FFFH

32 4 FC000H-FCFFFH 32 32 E8000H-EFFFFH

31 16 F8000H-FBFFFH 31 32 E0000H-E7FFFH

30 32 F0000H-F7FFFH 30 32 D8000H-DFFFFH

29 32 E8000H-EFFFFH 29 32 D0000H-D7FFFH

28 32 E0000H-E7FFFH 28 32 C8000H-CFFFFH

27 32 D8000H-DFFFFH 27 32 C0000H-C7FFFH

26 32 D0000H-D7FFFH 26 32 B8000H-BFFFFH

25 32 C8000H-CFFFFH 25 32 B0000H-B7FFFH

24 32 C0000H-C7FFFH 24 32 A8000H-AFFFFH

23 32 B8000H-BFFFFH 23 32 A0000H-A7FFFH

22 32 B0000H-B7FFFH 22 32 98000H-9FFFFH

21 32 A8000H-AFFFFH 21 32 90000H-97FFFH

20 32 A0000H-A7FFFH 20 32 88000H-8FFFFH

19 32 98000H-9FFFFH 19 32 80000H-87FFFH

18 32 90000H-97FFFH 18 32 78000H-7FFFFH

17 32 88000H-8FFFFH 17 32 70000H-77FFFH

16 32 80000H-87FFFH 16 32 68000H-6FFFFH

15 32 78000H-7FFFFH 15 32 60000H-67FFFH

14 32 70000H-77FFFH 14 32 58000H-5FFFFH

13 32 68000H-6FFFFH 13 32 50000H-57FFFH

12 32 60000H-67FFFH 12 32 48000H-4FFFFH

11 32 58000H-5FFFFH 11 32 40000H-47FFFH

10 32 50000H-57FFFH 10 32 38000H-3FFFFH

9 32 48000H-4FFFFH 9 32 30000H-37FFFH

8 32 40000H-47FFFH 8 32 28000H-2FFFFH

7 32 38000H-3FFFFH 7 32 20000H-27FFFH

6 32 30000H-37FFFH 6 32 18000H-1FFFFH

5 32 28000H-2FFFFH 5 32 10000H-17FFFH

4 32 20000H-27FFFH 4 32 08000H-0FFFFH

3 32 18000H-1FFFFH 3 16 04000H-07FFFH

2 32 10000H-17FFFH 2 4 03000H-03FFFH

1 32 08000H-0FFFFH 1 4 02000H-02FFFH

0 32 00000H-07FFFH 0 8 00000H-01FFFH

T5.1380

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

TABLE 6: Operation Modes Selection

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1Sector or block address, XXH for Chip-Erase

Standby VIH X X High Z X

Write Inhibit X VIL X High Z/ DOUT X

XXV

IH High Z/ DOUT X

Product Identification

Software Mode VIL VIL VIH See Table 7

T6.0 1380

1. X can be VIL or VIH, but no other value.

TABLE 7: Software Command Sequence

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1

1. Address format A10-A0 (Hex). Addresses A11-A19 can be VIL or VIH, but no other value, for Command sequence.

Data2

2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence

Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2

Word-Program 555H AAH 2AAH 55H 555H A0H WA3

3. WA = Program Word address

Data

Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SAX4

4. SAX for Sector-Erase; uses AMS-A11 address lines

BAX, for Block-Erase; uses AMS-A15 address lines

AMS = Most significant address; AMS = A19

50H

Block-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAX430H

Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Erase-Suspend XXXH B0H

Erase-Resume XXXH 30H

Query Sec ID5

5. With AMS-A4 = 0; Sec ID is read with A3-A0,

SST ID is read with A3 = 0 (Address range = 000000H to 000007H),

User ID is read with A3 = 1 (Address range = 000008H to 000087H).

Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.

555H AAH 2AAH 55H 555H 88H

User Security ID

Word-Program

555H AAH 2AAH 55H 555H A5H WA6

6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H-000087H.

Data

User Security ID

Program Lock-Out

555H AAH 2AAH 55H 555H 85H XXH60000H

Software ID Entry7,8

7. The device does not remain in Software Product ID Mode if powered down.

8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,

SST39VF1601C Device ID = 234FH, is read with A0 = 1, SST39VF1602C Device ID = 234EH, is read with A0 = 1,

AMS = Most significant address; AMS = A19

555H AAH 2AAH 55H 555H 90H

CFI Query Entry 555H AAH 2AAH 55H 555H 98H

CFI Query Entry 55H 98H

Software ID Exit9,10

/CFI Exit/Sec ID Exit

9. Both Software ID Exit operations are equivalent

10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID

mode again (the programmed ‘0’ bits cannot be reversed to ‘1’). Valid Word-Addresses for Sec ID are from 000000H-000007H and

000008H-000087H.

555H AAH 2AAH 55H 555H F0H

Software ID Exit9,10

/CFI Exit/Sec ID Exit

XXH F0H

T7.6 1380

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

TABLE 8: CFI Query Identification String1

Address Data Data

10H 0051H Query Unique ASCII string “QRY”

11H 0052H

12H 0059H

13H 0002H Primary OEM command set

14H 0000H

15H 0000H Address for Primary Extended Table

16H 0000H

17H 0000H Alternate OEM command set (00H = none exists)

18H 0000H

19H 0000H Address for Alternate OEM extended Table (00H = none exits)

1AH 0000H

T8.1 1380

1. Refer to CFI publication 100 for more details.

TABLE 9: System Interface Information

Address Data Data

1BH 0027H VDD Min (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1CH 0036H VDD Max (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH 0000H VPP min. (00H = no VPP pin)

1EH 0000H VPP max. (00H = no VPP pin)

1FH 0003H Typical time out for Word-Program 2N µs (23 = 8 µs)

20H 0000H Typical time out for min. size buffer program 2N µs (00H = not supported)

21H 0004H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)

22H 0005H Typical time out for Chip-Erase 2N ms (25 = 32 ms)

23H 0001H Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs)

24H 0000H Maximum time out for buffer program 2N times typical

25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)

26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)

T9.3 1380

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

TABLE 10: Device Geometry Information

Address Data Data

27H 0015H Device size = 2N Bytes (15H = 21; 221 = 2 MByte)

28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface

29H 0000H

2AH 0000H Maximum number of byte in multi-byte write = 2N (00H = not supported)

2BH 0000H

2CH 0005H Number of Erase Sector/Block sizes supported by device

2DH 0000H Erase Block Region 1 Information (Refer to the CFI specification or CFI publication 100)

2EH 0000H

2FH 0040H

30H 0000H

31H 0001H Erase Block Region 2 Information

32H 0000H

33H 0020H

34H 0000H

35H 0000H Erase Block Region 3 Information

36H 0000H

37H 0080H

38H 0000H

39H 001EH Erase Block Region 4 Information

3AH 0000H

3BH 0000H

3CH 0001H

T10.0 1380

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

ELECTRICAL SPECIFICATIONS

Power Up Specifications

All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100 ms (0V to 3V

in less than 300 ms). If the VDD ramp rate is slower than 1V per 100 ms, a hardware reset is required. The recom-

mended VDD power-up to RESET# high time should be greater than 100 µs to ensure a proper reset.

FIGURE 5: Power-Up Diagram

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

Operating Range

Range Ambient Temp VDD

Commercial

Industrial

0°C to +70°C

-40°C to +85°C

2.7-3.6V

AC Conditions of Test

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF

See Figures 20 and 21

1380 F24.0

VDD

RESET#

CE#

TPU-READ > 100 µs

VDD min

VIH

TRHR > 50ns

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

TABLE 11: DC Operating Characteristics VDD = 2.7-3.6V1

1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C

(room temperature), and VDD = 3V. Not 100% tested.

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT2, at f=5 MHz,

VDD=VDD Max

2. See Figure 20

3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Ty p ic a l V DD is 3V.

18 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

Program and Erase 35 mA CE#=WE#=VIL, OE#=VIH

ISB Standby VDD Current 20 µA CE#=VIHC, VDD=VDD Max

IALP Auto Low Power 20 µA CE#=VILC, VDD=VDD Max

All inputs=VSS or VDD, WE#=VIHC

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILIW Input Leakage Current

on WP# pin and RST#

10 µA WP#=GND to VDD or RST#=GND to VDD

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

VIH Input High Voltage 0.7VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

T11.8 1380

TABLE 12: Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T12.0 1380

TABLE 13: Capacitance (TA = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T13.0 1380

TABLE 14: Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1,2

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher

minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T14.2 1380

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

AC CHARACTERISTICS

TABLE 15: Read Cycle Timing Parameters VDD = 2.7-3.6V

Symbol Parameter Min Max Units

TRC Read Cycle Time 70 ns

TCE Chip Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 35 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1CE# High to High-Z Output 20 ns

TOHZ1OE# High to High-Z Output 20 ns

TOH1Output Hold from Address Change 0 ns

TRP1RST# Pulse Width 500 ns

TRHR1RST# High before Read 50 ns

TRY1,2

2. This parameter applies to Sector-Erase, Block-Erase and Program operations.

This parameter does not apply to Chip-Erase operations.

RST# Pin Low to Read Mode 20 µs

T15.3 1380

TABLE 16: Program/Erase Cycle Timing Parameters

Symbol Parameter Min Max Units

TBP Word-Program Time 10 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 50 ms

TBY1,2

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

RY/BY# Delay Time 90 ns

TBR1Bus Recovery Time 0µs

T16.1 1380

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 6: Read Cycle Timing Diagram

FIGURE 7: WE# Controlled Program Cycle Timing Diagram

1380 F03.0

ADDRESS AMS-0

DQ15-0

WE#

OE#

CE#

TCE

TRC TAA

TOE

TOLZ

VIH

HIGH-Z

TCLZ TOH

TCHZ

HIGH-Z

DATA VALIDDATA VALID

TOHZ

Note: AMS = Most significant address

MS = A19

1380 F25.0

ADDRESSES

DQ15-0

CE#

555 2AA 555 ADDR

XXAA XX55 XXA0 DATA

WORD

(ADDR/DATA)

OE#

WE#

RY/BY#

VALID

TDH

TWPH

TAS

TCH

TCS

TAH

TWP

TDS

TBY TBR

TBP

Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 8: CE# Controlled Program Cycle Timing Diagram

FIGURE 9: Data# Polling Timing Diagram

1380 F26.0

ADDRESSES

DQ15-0

CE#

555 2AA 555 ADDR

XXAA XX55 XXA0 DATA

WORD

(ADDR/DATA)

OE#

WE#

RY/BY#

VALID

TDH

TCPH

TAS

TCH

TCS

TAH

TCP

TDS

TBY TBR

TBP

Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

1380 F27.0

ADDRESS A19-0

DQ7DATA

WE#

OE#

CE#

RY/BY#

DATA# DATA# DATA

TOES

TOEH

TBY

TCE

TOE

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 10: Toggle Bits Timing Diagram

FIGURE 11: WE# Controlled Chip-Erase Timing Diagram

1380 F07.0

ADDRESS AMS-0

DQ6 and DQ2

WE#

OE#

CE#

TOE

TOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note: A

= Most significant address

= A

1380 F31.0

ADDRESSES

DQ15-0

WE#

555 2AA 2AA555 555

XX55 XX10

XX55XXAA XX80 XXAA

555

OE#

CE#

RY/BY#

VALID

SIX-BYTE CODE FOR CHIP-ERASE

TOEH

TSCE

TBY TBR

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchange-

able as long as minimum timings are met. (See Table 16).

WP# must be held in proper logic state (VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 12: WE# Controlled Block-Erase Timing Diagram

1380 F32.0

ADDRESSES

DQ15-0

WE#

555 2AA 2AA555 555

XX55 XX30

XX55XXAA XX80 XXAA

BAX

OE#

CE#

RY/BY#

VALID

SIX-BYTE CODE FOR BLOCK-ERASE

TWP

TBE

TBY TBR

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchange-

able as long as minimum timings are met. (See Table 16).

BAX = Block Address

WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 13: WE# Controlled Sector-Erase Timing Diagram

1380 F28.0

ADDRESSES

DQ15-0

WE#

555 2AA 2AA555 555

XX55 XX50

XX55XXAA XX80 XXAA

SAX

OE#

CE#

RY/BY#

VALID

SIX-BYTE CODE FOR SECTOR-ERASE

TWP

TSE

TBY TBR

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchange-

able as long as minimum timings are met. (See Table 16).

SAX = Block Address

WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 14: Software ID Entry and Read

FIGURE 15: CFI Query Entry and Read

1380 F11.0

ADDRESS

TIDA

DQ15-0

WE#

SW0 SW1 SW2

555 2AA 555 0000 0001

OE#

CE#

Three-Byte Sequence for Software ID Entry

TWP

TWPH TAA

00BF Device IDXX55XXAA XX90

Note: Device ID = 234BH for 39VF1601C and 234AH for 39VF1602C

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

X can be VIL or VIH, but no other value

1380 F12.0

ADDRESS

TIDA

DQ15-0

WE#

SW0 SW1 SW2

555 2AA 555

OE#

CE#

Three-Byte Sequence for CFI Query Entry

TWP

TWPH TAA

XX55XXAA XX98

Note: WP# must be held in proper logic state (V

or V

) 1 µs prior to and 1 µs after the command sequence

X can be V

or V

, but no other value

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 16: Software ID Exit/CFI Exit

FIGURE 17: Sec ID Entry

1380 F13.0

ADDRESS

DQ15-0

TIDA

TWP

TWHP

WE#

SW0 SW1 SW2

555 2AA 555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

XXAA XX55 XXF0

Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

X can be VIL or VIH, but no other value

1380 F20.0

ADDRESS AMS-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2

555 2AA 555

OE#

CE#

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

TWP

TWPH TAA

XX55XXAA XX88

Note: AMS = Most significant address

MS = A19

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

X can be VIL or VIH, but no other value.

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 18: RST# Timing Diagram (When no internal operation is in progress)

FIGURE 19: RST# Timing Diagram (During Program or Erase operation)

FIGURE 20: AC Input/Output Reference Waveforms

1380 F29.0

RY/BY#

RST#

CE#/OE#

TRP

TRHR

1380 F30.0

RY/BY#

CE#

OE#

TRP

TRY

TBR

RST#

1380F14.0

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (0.9 VDD) for a logic ‘1’ and VILT (0.1 VDD) for a logic ‘0’. Measurement reference points

for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Te s t

VOT - VOUTPUT Tes t

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 21: A Test Load Example

1380 F15.0

TO TESTER

TO DUT

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 22: Word-Program Algorithm

1380 F16.0

Start

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XXA0H

Address: 555H

Load Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

X can be VIL or VIH, but no other value

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 23: Wait Options

1380 F17.1

Wait TBP,

TSCE, TSE

or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match?

Read same

word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read word

Is DQ7 =

true data?

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

Ye s

RY/BY#

RY/BY# = 1?

Read RY/BY#

Program/Erase

Initiated

Program/Erase

Completed

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 24: Software ID/CFI Entry Command Flowcharts

1380 F21.0

Load data: XXAAH

Address: 555H

Software Product ID Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX90H

Address: 555H

Wait TIDA

Read Software ID

Load data: XXAAH

Address: 555H

CFI Query Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX98H

Address: 55H

Wait TIDA

Read CFI data

Load data: XXAAH

Address: 555H

Sec ID Query Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX88H

Address: 555H

Wait TIDA

Read Sec ID

X can be VIL or VIH, but no other value

Load data: XX98H

Address: 55H

Wait TIDA

Read CFI data

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 25: Software ID/CFI Exit Command Flowcharts

1380 F18.0

Load data: XXAAH

Address: 555H

Software ID Exit/CFI Exit/Sec ID Exit

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XXF0H

Address: 555H

Load data: XXF0H

Address: XXH

Return to normal

operation

Wait TIDA

Return to normal

operation

X can be VIL or VIH, but no other value

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 26: Erase Command Sequence

1380 F19.0

Load data: XXAAH

Address: 555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX10H

Address: 555H

Load data: XXAAH

Address: 555H

Wait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX50H

Address: SAX

Load data: XXAAH

Address: 555H

Wait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX30H

Address: BAX

Load data: XXAAH

Address: 555H

Wait TBE

Block erased

to FFFFH

X can be VIL or VIH, but no other value

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

PRODUCT ORDERING INFORMATION

Valid Combinations for SST39VF1601C

SST39VF1601C-70-4C-EKE SST39VF1601C-70-4C-B3KE SST39VF1601C-70-4C-MAQE

SST39VF1601C-70-4I-EKE SST39VF1601C-70-4I-B3KE SST39VF1601C-70-4I-MAQE

Valid Combinations for SST39VF1602C

SST39VF1602C-70-4C-EKE SST39VF1602C-70-4C-B3KE SST39VF1602C-70-4C-MAQE

SST39VF1602C-70-4I-EKE SST39VF1602C-70-4I-B3KE SST39VF1602C-70-4I-MAQE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Environmental Attribute

E1 = non-Pb

Package Modifier

K = 48 balls or leads

Q = 48 balls (66 possible positions)

Package Type

E = TSOP (type1, die up, 12mm x 20mm)

B3 = TFBGA (6mm x 8mm, 0.8mm pitch)

MA = WFBGA (4mm x 6mm, 0.5mm pitch)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

Hardware Block Protection

1 = Bottom Boot-Block

2 = Top Boot-Block

Device Density

160 = 16 Mbit

Voltage

V = 2.7-3.6V

Product Series

39 = Multi-Purpose Flash

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

SST 39 VF 1602 C - 70 - 4C - EK E

XX XX XXXXX-XX -XX-XXX X

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

PACKAGING DIAGRAMS

FIGURE 27: 48-lead Thin Small Outline Package (TSOP) 12mm x 20mm

SST Package Code: EK

1.05

0.95

0.70

0.50

18.50

18.30

20.20

19.80

0.70

0.50

12.20

11.80

0.27

0.17

0.15

0.05

48-tsop-EK-8

Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

0°- 5°

DETAIL

Pin # 1 Identifier

0.50

BSC

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

FIGURE 28: 48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm

SST Package Code: B3K

FIGURE 29: 48-ball Very, Very Thin-profile, Fine-pitch Ball Grid Array (WFBGA) 6mm x 8mm

SST Package Code: MAQ

A1 CORNER

H G F E D C B A

A B C D E F G H

BOTTOM VIEWTOP VIEW

SIDE VIEW

SEATING PLANE

0.35 ± 0.05

1.10 ± 0.10

0.12

6.00 ± 0.20

0.45 ± 0.05

(48X)

A1 CORNER

8.00 ± 0.20

0.80

4.00

0.80

5.60

48-tfbga-B3K-6x8-450mic-4

Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

1mm

L K J H G F E D C B A

ABCDEFGHJKL

0.50

BOTTOM VIEW

4.00

± 0.08

0.32 ± 0.05

(48X)

6.00

± 0.08

2.50

5.00

A1 CORNER

TOP VIEW

48-wfbga-MAQ-4x6-32mic-2.0

Note:

1. Complies with JEDEC Publication 95, MO-207, Variant CB-4 except nominal ball size is larger

and bottom side A1 indicator is triangle at corner.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.08 mm

4. Ball opening size is 0.29 mm (± 0.05 mm)

1mm

DETAIL SIDE VIEW

SEATING PLANE

0.20 ± 0.06

0.73 max.

0.636 nom.

0.08

A1 INDICATOR

Data Sheet

16 Mbit Multi-Purpose Flash Plus

SST39VF1601C / SST39VF1602C

TABLE 17: Revision History

Number Description Date

00 •Initial release Apr 2008

01 •Corrected typo in Hardware Block Protection on page 4.

•Corrected typo in table title, Table 5 page 8

Sep 2008

02 •Changed 1V per 100 µs to 1V per 100 ms in Power Up Specifications on page 12 Jan 2009

03 •Changed from Preliminary Specification to Data Sheet

•Clarified RY/BY# pin timing by updating Features, Figures 7, 8, 9, 11, 12, 13, 18,

19, and 23, and Tables 1 and 16.

Aug 2009

04 •Added information for MAQE package

•Updated SST address information on page 33.

May 2010

Silicon Storage Technology, Inc.