ADC1175-50CIMTX/NOPB - NATIONAL SEMICONDUCTOR

ADC1175-50

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ADC1175-50 8-Bit, 50 MSPS, 125 mW A/D Converter

Check for Samples: ADC1175-50

1FEATURES DESCRIPTION

The ADC1175-50 is a low power, 50 MSPS analog-

• Internal Track-and-Hold Function to-digital converter that digitizes signals to 8 bits while

• Single +5V Operation consuming just 125 mW (typ). The ADC1175-50 uses

• Internal Reference Bias Resistors a unique architecture that achieves 6.8 Effective Bits

at 25 MHz input and 50 MHz clock frequency. Output

• Industry Standard Pinout formatting is straight binary coding.

• Power-Down Mode (<5 mW) The excellent DC and AC characteristics of this

device, together with its low power consumption and

APPLICATIONS +5V single supply operation, make it ideally suited for

• Digital Still Cameras many video and imaging applications, including use in

• CCD Imaging portable equipment. Furthermore, the ADC1175-50 is

resistant to latch-up and the outputs are short-circuit

• Electro-Optics proof. The top and bottom of the ADC1175-50's

• Video Digitization reference ladder is available for connections,

• Multimedia enabling a wide range of input possibilities. The low

input capacitance (7 pF, typical) makes this device

easier to drive than conventional flash converters and

KEY SPECIFICATIONS the power down mode reduces power consumption to

• Resolution 8 Bits less than 5 mW.

• Maximum Sampling Frequency 50 MSPS (min) The ADC1175-50 is offered in 24-pin TSSOP and 24-

• THD 54 dB (typ) pin WQFN packages and is designed to operate over

• DNL 0.7 LSB (typ) the extended commercial temperature range of

−20°C to +75°C.

• ENOB @ fIN = 25 MHz 6.8 Bits (typ)

• Ensured No Missing Codes

• Power Consumption (Excluding

Reference Current) 125 mW (typ)

190 mW (max)

CONNECTION DIAGRAMS

Figure 1. 24-Pin TSSOP - Top View Figure 2. 24-Pin WQFN - Bottom View

See PW Package See NHW0024B Package

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADC1175-50

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BLOCK DIAGRAM

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DVDD

DVSS

ADC1175-50

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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS(1)

Pin Symbol Equivalent Circuit Description

No.

19 VIN Analog signal input. Conversion range is VRT to VRB.

(17)

16 Reference Top Bias with internal pull up resistor. Short this

VRTS

(14) pin to VRT to self-bias the reference ladder.

Analog input that is the high (top) side of the reference

17 ladder of the ADC. Voltages on VRT and VRB inputs define

VRT

(15) the VIN conversion range. Bypass well. See REFERENCE

INPUTS for more information.

Analog input that is the low (bottom) side of the reference

ladder of the ADC. Nominal range is 0.0V to 4.0V, with

23 VRB optimized value of 0.6V. Voltage on VRT and VRB inputs

(21) define the VIN conversion range. Bypass well. See

REFERENCE INPUTS for more information.

Reference Bottom Bias with internal pull down resistor. Short

22 VRBS to VRB to self-bias the reference ladder. Bypass well (unless

(20) grounded). See REFERENCE INPUTS for more information.

CMOS/TTL compatible Digital input that, when high, puts the

1 ADC1175-50 into a power-down mode where total power

(23) consumption is typically less than 5 mW. With this pin low,

the device is in the normal operating mode.

(1) (WQFN pins in parentheses)

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DVDD

DVSS

DVDD

DVSS

ADC1175-50

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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS(1) (continued)

Pin Symbol Equivalent Circuit Description

No.

12 CMOS/TTL compatible digital clock input. VIN is sampled on

CLK

(10) the falling edge of CLK input.

Conversion data digital Output pins. D0 is the LSB, D7 is the

3 thru 10 MSB. Valid data is output just after the rising edge of the

D0–D7

(1 thru 8) CLK input. These pins are in a high impedance mode when

the PD pin is low.

Positive digital supply pin. Connect to a quiet voltage source

of +5V. AVDD and DVDD should have a common source and

11, 13, 14 DVDD be separately bypassed with a 10 µF capacitor and a 0.1 µF

(9, 11, 12) ceramic chip capacitor. See POWER SUPPLY

CONSIDERATIONS for more information.

2, 24 The ground return for the digital supply. AVSS and DVSS

DVSS

(22, 24) should be connected together close to the ADC1175-50.

Positive analog supply pin. Connect to a quiet voltage source

of +5V. AVDD and DVDD should have a common source and

15, 18 AVDD be separately bypassed with a 10 µF capacitor and a 0.1 µF

(13, 16) ceramic chip capacitor. See POWER SUPPLY

CONSIDERATIONS for more information.

The ground return for the analog supply. AVSS and DVSS

20, 21 AVSS should be connected together close to the ADC1175-50

(18, 19) package.

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS(1)(2)(3)

Supply Voltage (AVDD, DVDD) 6.5V

Voltage on Any Input or Output Pin −0.3V to +6.5V

Reference Voltage (VRT, VRB) AVSS to VDD

CLK, PD Voltage Range −0.5 to (AVDD +0.5V)

Digital Output Voltage (VOH, VOL) VSS to VDD

Input Current at Any Pin(4) ±25 mA

Package Input Current(4) ±50 mA

Power Dissipation at TA= 25°C See (5)

ESD Susceptibility(6) Human Body Model 2000V

Machine Model 250V

Soldering Temperature Infrared (10 sec.) 235°C

Storage Temperature −65°C to +150°C

Short Circuit Duration (Single High Output to Ground) 1 Second

(1) All voltages are measured with respect to GND = AVSS = DVSS = 0V, unless otherwise specified.

(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(4) When the input voltage at any pin exceeds the power supplies (that is, less than AVSS or DVSS, or greater than AVDD or DVDD), the

current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can

safely exceed the power supplies with an input current of 25 mA to two.

(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

TJmax, the junction-to-ambient thermal resistance (θJA) and the ambient temperature (TA), and can be calculated using the formula PD

max = (TJmax – TA)/θJA. The values for maximum power dissipation listed above will be reached only when the ADC1175-50 is

operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply

polarity is reversed). Obviously, such conditions should always be avoided.

(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩresistor. Machine model is 220 pF discharged through 0Ω.

OPERATING RATINGS(1)(2)

Operating Temperature Range −20°C ≤TA≤+75°C

Supply Voltage (AVDD, DVDD) +4.75V to +5.25V

AVDD −DVDD <0.5V

Ground Difference |DVSS – AVSS| 0V to 100 mV

Pin 11 to Pin 13 Voltage <0.5V

Upper Reference Voltage (VRT) 1.0V to VDD

Lower Reference Voltage (VRB) 0V to 4.0V

VRT - VRB 1V to 2.8V

VIN Voltage Range VRB to VRT

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = AVSS = DVSS = 0V, unless otherwise specified.

PACKAGE THERMAL RESISTANCE

Package θJA

TSSOP 92°C / W

WQFN 40°C / W

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CONVERTER ELECTRICAL CHARACTERISTICS

The following specifications apply for AVDD = DVDD = +5.0 VDC, PD = 0V, VRT = +2.6V, VRB = 0.6V, CL= 20 pF, fCLK = 50 MHz

at 50% duty cycle. Boldface limits apply for TA= TMIN to TMAX; all other limits TA= 25°C (1)(2).Units

Symbol Parameter Conditions Typical(3) Limits(3) (Limits)

DC ACCURACY

INL Integral Non Linearity Error VIN = 0.6V to 2.6V ±0.8 ±1.95 LSB (max)

+0.7 +1.75 LSB (max)

DNL Differential Non-Linearity VIN = 0.6V to 2.6V −0.7 −1.0 LSB (min)

Resolution for No Missing 8Bits

Codes

EOT Top Offset Voltage −12 mV

EOB Bottom Offset Voltage +10 mV

VIDEO ACCURACY

DP Differential Phase Error fIN = 4.43 MHz Modulated Ramp 0.5 deg

DG Differential Gain Error fIN = 4.43 MHz Modulated Ramp 1.0 %

ANALOG INPUT AND REFERENCE CHARACTERISTIC

VRB V (min)

VIN Input Range 2.0 VRT V (max)

(CLK LOW) 4 pF

VIN = 1.5V

CIN VIN Input Capacitance +0.7 Vrms (CLK HIGH) 7 pF

RIN RIN Input Resistance >1 MΩ

BW Full Power Bandwidth 120 MHz

RRT Top Reference Resistor 320 Ω

200 Ω(min)

RREF Reference Ladder Resistance VRT to VRB 270 350 Ω(max)

RRB Bottom Reference Resistor 80 Ω

5.4 mA (min)

VRT = VRTS, VRB = VRBS 710.8 mA (max)

IREF Reference Ladder Current 6.1 mA (min)

VRT = VRTS, VRB = AVSS 812.3 mA (max)

Reference Top Self Bias VRT Connected to VRTS, V (min)

VRT 2.6

Voltage VRB Connected to VRBS V (max)

Reference Bottom Self Bias VRT Connected to VRTS,0.55 V (min)

VRB 0.6

Voltage VRB Connected to VRBS 0.70 V (max)

(1) The analog inputs are protected as shown below. Input voltage magnitudes up to 6.5V or 500 mV below GND will not damage this

device. However, errors in the A/D conversion can occur if the input goes above VDD or below GND by more than 50 mV. As an

example, if AVDD is 4.75 VDC, the full-scale input voltage must be ≤4.80 VDC to ensure accurate conversions.

spacer

(2) To ensure accuracy, it is required that AVDD and DVDD be well bypassed. Each VDD pin must be decoupled with separate bypass

capacitors.

(3) Typical figures are at TJ= 25°C, and represent most likely parametric norms. Test limits are ensured to TI's AOQL (Average Outgoing

Quality Level).

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CONVERTER ELECTRICAL CHARACTERISTICS (continued)

The following specifications apply for AVDD = DVDD = +5.0 VDC, PD = 0V, VRT = +2.6V, VRB = 0.6V, CL= 20 pF, fCLK = 50 MHz

at 50% duty cycle. Boldface limits apply for TA= TMIN to TMAX; all other limits TA= 25°C (1)(2).Units

Symbol Parameter Conditions Typical(3) Limits(3) (Limits)

VRT Connected to VRTS,1.89 (V (min)

VRB Connected to VRBS 2.20 V (max)

VRTS – VRBS Self Bias Voltage Delta VRT Connected to VRTS,2.3 V

VRB Connected to AVSS 1.0 V (min)

VRT – VRB Reference Voltage Differential 2 2.8 V (max)

CONVERTER DYNAMIC CHARACTERISTICS

fIN = 4.4 MHz, fCLK = 40 MHz 7.2 6.7 Bits (min)

fIN = 19.9 MHz, fCLK = 40 MHz 7.0 6.4 Bits (min)

ENOB Effective Number of Bits fIN = 1.3 MHz, fCLK = 50 MHz 7.3 Bits

fIN = 4.4 MHz, fCLK = 50 MHz 7.2 Bits

fIN = 24.9 MHz, fCLK = 50 MHz 6.8 6.1 Bits (min)

fIN = 4.4 MHz, fCLK = 40 MHz 45 42 dB (min)

fIN = 19.9 MHz, fCLK = 40 MHz 44 40 dB (min)

SINAD Signal-to-Noise & Distortion fIN = 1.3 MHz, fCLK = 50 MHz 46 dB

fIN = 4.4 MHz, fCLK = 50 MHz 45 dB

fIN = 24.9 MHz, fCLK = 50 MHz 43 38.4 dB (min)

fIN = 4.4 MHz, fCLK = 40 MHz 46 42.5 dB (min)

fIN = 19.9 MHz, fCLK = 40 MHz 44 41 dB (min)

SNR Signal-to-Noise Ratio fIN = 1.3 MHz, fCLK = 50 MHz 48 dB

fIN = 4.4 MHz, fCLK = 50 MHz 45 dB

fIN = 24.9 MHz, fCLK = 50 MHz 44 40 dB (min)

fIN = 1.3 MHz 57 dB

SFDR Spurious Free Dynamic Range fIN = 4.4 MHz 56 dB

fIN = 24.9 MHz 51 dB

fIN = 1.3 MHz −55 dB

THD Total Harmonic Distortion fIN = 4.4 MHz −54 dB

fIN = 24.9 MHz −51 dB

POWER SUPPLY CHARACTERISTICS

IADD Analog Supply Current DVDD = AVDD = 5.25V 13 mA

IDDD Digital Supply Current DVDD = AVDD = 5.25V 11 mA

DVDD = AVDD = 5.25V, fCLK = 50 MHz 25 36 mA (max)

IADD + IDDD Total Operating Current DVDD = AVDD = 5.25V, CLK Inactive (low) 14 mA

Power Consumption PD pin low 125 190 mW (max)

Power Consumption PD pin high <5 mW mW

CLK, PD DIGITAL INPUT CHARACTERISTICS

VIH Logical High Input Voltage 2.0 V (min)

VIL Logical Low Input Voltage 0.8 V (max)

IIH Logical High Input Current VIH = DVDD = AVDD = +5.25V ±5 µA (max)

IIL Logical Low Input Current VIL = 0V, DVDD = AVDD = +5.25V ±5 µA (max)

CIN Digital Input Capacitance 4 pF

DIGITAL OUTPUT CHARACTERISTICS

IOH Output Current, Logic HIGH DVDD = 4.75V, VOH = 4.0V −1.1 mA (min)

IOL Output Current, Logic LOW DVDD = 4.75V, VOL = 0.4V 1.8 mA (min)

DVDD = 5.25V, PD = DVDD,

IOZH, IOZL TRI-STATE Output Current ±20 µA

VOL = DVDD, or VOL = 0V

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CONVERTER ELECTRICAL CHARACTERISTICS (continued)

The following specifications apply for AVDD = DVDD = +5.0 VDC, PD = 0V, VRT = +2.6V, VRB = 0.6V, CL= 20 pF, fCLK = 50 MHz

at 50% duty cycle. Boldface limits apply for TA= TMIN to TMAX; all other limits TA= 25°C (1)(2).Units

Symbol Parameter Conditions Typical(3) Limits(3) (Limits)

AC ELECTRICAL CHARACTERISTICS

fC1 Maximum Conversion Rate 55 50 MHz (min)

fC2 Minimum Conversion Rate 1 MHz

5ns (min)

tOD Output Delay CLK high to data valid 14 20 ns (max)

Pipeline Delay (Latency) 2.5 Clock Cycles

tDS Sampling (Aperture) Delay CLK low to acquisition of data 3 ns

tAJ Aperture Jitter 10 ps rms

tOH Output Hold Time CLK high to data invalid 10 ns

tEN PD Low to Data Valid Loaded as in Figure 16 140 ns

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TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = DVDD = 5V, fCLK = 50 MHz, unless otherwise stated.

INL Plot DNL Plot

Figure 3. Figure 4.

INL vs. Temperature DNL vs. Temperature

Figure 5. Figure 6.

SNR vs. Temp & fIN THD vs. Temp & fIN

Figure 7. Figure 8.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

AVDD = DVDD = 5V, fCLK = 50 MHz, unless otherwise stated.

SINAD & ENOB vs. Temp & fIN SINAD & ENOB vs. Clock Duty Cycle

Figure 9. Figure 10.

SFDR vs. Temp & fIN tOD vs. Temperature

Figure 11. Figure 12.

Power Supply Current vs. fCLK Spectral Response

Figure 13. Figure 14.

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SPECIFICATION DEFINITIONS

ANALOG INPUT BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input. The test is performed with fIN equal to 100 kHz

plus integer multiples of fCLK. The input frequency at which the output is −3 dB relative to the low frequency input

signal is the full power bandwidth.

APERTURE JITTER is the time uncertainty of the sampling point (tDS), or the range of variation in the sampling

delay.

BOTTOM OFFSET is the difference between the input voltage that just causes the output code to transition to

the first code and the negative reference voltage. Bottom Offset is defined as EOB = VZT −VRB, where VZT is the

first code transition input voltage. Note that this is different from the normal Zero Scale Error.

DIFFERENTIAL GAIN ERROR is the percentage difference between the output amplitudes of a high frequency

reconstructed sine wave at two different d.c. levels.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB. DNL is measured at the rated clock frequency with a ramp input.

DIFFERENTIAL PHASE ERROR is the difference in the output phase of a reconstructed small signal sine wave

at two different d.c. levels.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion Ratio, or SINAD. ENOB is defined as (SINAD −1.76) / 6.02 and says that the converter is

equivalent to a perfect ADC of this (ENOB) number of bits.

INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual codes from a line drawn from

zero scale (1/2 LSB below the first code transition) through positive full scale (1/2 LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code value.

The end point test method is used. INL is measured at rated clock frequency with a ramp input.

OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the

output pins.

OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock.

PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data

is presented to the output stage. Data for any given sample is available the Pipeline Delay plus the Output Delay

after that sample is taken. New data is available at every clock cycle, but the data lags the conversion by the

pipeline delay.

SAMPLING (APERTURE) DELAY, or tDS, is the time required after the falling edge of the clock for the sampling

switch to open (in other words, for the Sample/Hold circuit to go from the “sample” mode into the “hold” mode).

The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode tDS after the

clock goes low.

SIGNAL TO NOISE RATIO (SNR) is the ratio of the rms value of the input signal to the rms value of the other

spectral components below one-half the sampling frequency, not including harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio of the rms value of the input signal to

the rms value of all of the other spectral components below half the clock frequency, including harmonics but

excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the

input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum

that is not present at the input.

TOP OFFSET is the difference between the positive reference voltage and the input voltage that just causes the

output code to transition to full scale and is defined as EOT = VFT −VRT. Where VFT is the full scale transition

input voltage. Note that this is different from the normal Full Scale Error.

TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first six harmonic components to the

rms value of the input signal.

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Timing Diagram

Figure 15. ADC1175-50 Timing Diagram

Figure 16. tEN, tDIS Test Circuit

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FUNCTIONAL DESCRIPTION

The ADC1175-50 maintains superior dynamic performance with input frequencies up to 1/2 the clock frequency,

achieving 6.8 effective bits with a 50 MHz sampling rate and 25 MHz input frequency.

The analog signal at VIN that is within the voltage range set by VRT and VRB are digitized to eight bits at up to 55

MSPS. Input voltages below VRB will cause the output word to consist of all zeroes. Input voltages above VRT will

cause the output word to consist of all ones. While the ADC1175-50 is specified for top and bottom reference

voltages (VRT and VRB) or 2.6V and 0.6V, respectively, and will give best performance at these values, VRT has a

range of 1.0V to the analog supply voltage, AVDD, while VRB has a range of 0V to 4.0V. VRT should always be at

least 1.0V more positive than VRB. With VRT voltages above 2.8V, it is necessary to reduce the clock frequency to

maintain SINAD performance. VRT should always be between 1.0V and 2.8V more positive than VRB.

If VRT and VRTS are connected together and VRB and VRBS are connected together, the nominal values of VRT and

VRB are 2.6V and 0.6V, respectively. If VRT and VRTS are connected together and VRB is grounded, the nominal

value of VRT is 2.3V.

Data is acquired at the falling edge of the clock and the digital equivalent of that data is available at the digital

outputs 2.5 clock cycles plus tOD later. The ADC1175-50 will convert as long as the clock signal is present at the

CLK pin. The PD pin, when high, puts the device into the Power Down mode. When the PD pin is low, the device

is in the normal operating mode.

The Power Down pin (PD), when high, puts the ADC1175-50 into a power down mode where power consumption

is typically less than 5 mW. When the part is powered down, the digital output pins are in a high impedance TRI-

STATE. It takes about 140 ns for the part to become active upon coming out of the power down mode.

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20 2 24

AVSS DVSS

D7 10

D6 9

D5 8

D0 3

D1 4

D2 5

D3 6

D4 7

AVDD

-6

237,

150,

237,

57.6,

21 12

CLK

AVSS

VRTS

VRT

VRB

VRBS

62 pF

Analog

Input

10 PF

0.1 PF

10 PF

131815 1114

0.1 PF

10 PF

DVDD

AVDD

Choke

+5V

ADC1175-50

LMH6702

150,

ADC1175-50

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APPLICATIONS INFORMATION

(All Schematic pin numbers refer to the TSSOP.)

THE ANALOG INPUT

The analog input of the ADC1175-50 is a switch followed by an integrator. That is, a switched capacitor input,

appearing as 4 pF when the clock is low, and 7 pF when the clock is high. Switched capacitor inputs produce

voltage spikes at the input pin at the ADC sample rate. There should be no attempt to eliminate these spikes, but

they should settle out during the sample period (the clock high time). An RC at the ADC analog input pin, as

shown in Figure 17, will help. For Nyquist applications, the capacitor should be about 10 times ADC track mode

input capacitance and the pole frequency of this RC should be about the ADC sample rate. The LMH6702, and

the LMH6609 have been found to be excellent amplifiers for driving the ADC1175-50. Do not drive the input

beyond the supply rails. Figure 17 shows an example of an input circuit using the LMH6702.

Driving the analog input with input signals up to 2.8 VP-P will result in normal behavior where signals above VRT

will result in a code of FFh and input voltages below VRB will result in an output code of zero. Input signals above

2.8 VP-P may result in odd behavior where the output code is not FFh when the input exceeds VRT.

Choose an op-amp that can drive a dynamic capacitance.

Figure 17. Driving the ADC1175-50

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REFERENCE INPUTS

The reference inputs VRT (Reference Top) and VRB (Reference Bottom) are the top and bottom of the reference

ladder. Input signals between these two voltages will be digitized to 8 bits. External voltages applied to the

reference input pins should be within the range specified in the Operating Ratings section (1.0V to AVDD for VRT

and 0V to (AVDD −1.0V) for VRB). Any device used to drive the reference pins should be able to source sufficient

current into the VRT pin and sink sufficient current from the VRB pin.

The reference ladder can be self-biased by connecting VRT to VRTS and connecting the VRB to VRBS to provide top

and bottom reference voltages of approximately 2.6V and 0.6V, respectively, with VCC = 5.0V. This connection is

shown in Figure 17. If VRT and VRTS are tied together, but VRB is tied to analog ground, a top reference voltage of

approximately 2.3V is generated. The top and bottom of the ladder should be bypassed with 10 µF tantalum

capacitors located close to the reference pins.

The reference self-bias circuit of Figure 17 is very simple and performance is adequate for many applications.

Better linearity performance can generally be achieved by driving the reference pins with a low impedance

source.

By forcing a little current into or out of the top and bottom of the ladder, as shown in Figure 18, the top and

bottom reference voltages can be trimmed and performance improved over the self-bias method of Figure 17.

The resistive divider at the amplifier inputs can be replaced with potentiometers, if desired. The LMC662 amplifier

shown was chosen for its low offset voltage and low cost. Note that a negative power supply is needed for these

amplifiers if the lower one is required to go slightly negative to force the required reference voltage.

If reference voltages are desired that are more than a few tens of millivolts from the self-bias values, the circuit of

Figure 19 will allow forcing the reference voltages to whatever levels are desired. This circuit provides the best

performance because of the low source impedance of the transistors. Note that the VRTS and VRBS pins are left

floating.

To minimize noise effects and ensure accurate conversions, the total reference voltage range (VRT −VRB) should

be a minimum of 1.0V and a maximum of about 2.8V.

The ADC1175-50 is designed to operate with top and bottom references of 2.6V and 0.6V, respectively.

However, it will function with reduced performance with a top reference voltage as high as AVDD and a bottom

reference voltage as low as ground.

If reference voltages are desired that are more than a few tens of millivolts from the self-bias values, the circuit of

Figure 19 will allow forcing the reference voltages to whatever levels are desired. This circuit provides the best

performance because of the low source impedance of the transistors. Note that the VRTS and VRBS pins are left

floating.

VRT can be anywhere between VRB + 1.0V and the analog supply voltage, and VRB can be anywhere between

ground and 1.0V below VRT. To minimize noise effects and ensure accurate conversions, the total reference

voltage range (VRT - VRB) should be a minimum of 1.0V and a maximum of about 2.8V. If VRB is not required to

be below about +700mV, the -5V points in Figure 19 can be returned to ground and the negative supply

eliminated.

Product Folder Links: ADC1175-50

ADC1175-50

SNAS027G –JANUARY 2000–REVISED APRIL 2013

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Self bias is still used, but the reference voltages are trimmed by providing a small trim current with the operational

amplifiers.

Figure 18. Better Defining the ADC Reference Voltage.

Requires driving with a low impedance source, provided by the transistors. Note that pins 16 and 22 are not

connected.

Figure 19. Driving the Reference to Force Desired Values

Product Folder Links: ADC1175-50

ADC1175-50

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SNAS027G –JANUARY 2000–REVISED APRIL 2013

OUTPUT DATA TIMING

The Output Delay (tOD) of the ADC1175-50 can be very close to one half clock cycle. Because of this, the output

data transition occurs very near the falling edge of the ADC clock. To avoid clocking errors, you should use the

rising edge of the ADC clock to latch the output data of the ADC1175-50 and not use the falling edge.

POWER SUPPLY CONSIDERATIONS

Many A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately

bypassed. A 10 µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 centimeters)

of the A/D power pins, with a 0.1 µF ceramic chip capacitor placed as close as possible to the converter's power

supply pins. Leadless chip capacitors are preferred because they have low lead inductance.

While a single voltage source should be used for the analog and digital supplies of the ADC1175-50, these

supply pins should be isolated from each other to prevent any digital noise from being coupled to the analog

power pins. We recommended a wide band choke, such as the JW Miller FB20010-3B, be used between the

analog and digital supply lines, with a ceramic capacitor close to the analog supply pin. If a resistor is used in

place of the choke, a maximum of 10Ωshould be used.

The converter digital supply should not be the supply that is used for other digital circuitry on the board. It should

be the same supply used for the A/D analog supply.

As with all high speed converters, the ADC1175-50 should be assumed to have little a.c. power supply rejection,

especially when self biasing is used by connecting VRT and VRTS together.

No pin should ever have a voltage on it that is in excess of the supply voltage or below ground, not even on a

transient basis. This can be a problem upon application of power to a circuit. Be sure that the supplies to circuits

driving the CLK, PD, analog input and reference pins do not come up any faster than does the voltage at the

ADC1175-50 power pins.

Pins 11 and 13 are both labeled DVDD. Pin 11 is the supply point for the digital core of the ADC, where pin 13 is

used only to provide power to the ADC output drivers. As such, pin 11 may be connected to a voltage source

that is less than the +5V used for AVDD and DVDD to ease interfacing to low voltage devices. Pin 11 should never

exceed the pin 13 potential by more than 0.5V.

THE ADC1175-50 CLOCK

Although the ADC1175-50 is tested and its performance is ensured with a 50 MHz clock, it typically will function

with clock frequencies from 1 MHz to 55 MHz.

The clock should be one of low jitter and close to 50% duty cycle.

LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals is essential to ensure accurate conversion. Separate analog

and digital ground planes that are connected beneath the ADC1175-50 may be used, but best EMI practices

require a single ground plane. However, it is important to keep analog signal lines away from digital signal lines

and away from power supply currents. This latter requirement requires the careful separation and placement of

power planes. The use of power traces rather than one or more power planes is not recommended as higher

frequencies are not well filtered with lumped capacitances. To filter higher frequency noise components it is

necessary to have sufficient capacitance between the power and ground planes.

If separate analog and digital ground planes are used, the analog and digital grounds may be in the same layer,

but should be separated from each other. If separate analog and digital ground layers are used, they should

never overlap each other.

Capacitive coupling between a typically noisy digital ground plane and the sensitive analog circuitry can lead to

poor performance that may seem impossible to isolate and remedy. The solution is to keep the analog circuitry

well separated from the digital circuitry.

Product Folder Links: ADC1175-50

ADC1175-50

SNAS027G –JANUARY 2000–REVISED APRIL 2013

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Digital circuits create substantial supply and ground current transients. The logic noise thus generated could

have significant impact upon system noise performance. The best logic family to use in systems with A/D

converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the

74LS and the 74HC(T) families. The worst noise generators are logic families that draw the largest supply current

transients during clock or signal edges, like the 74F family. In general, slower logic families will produce less high

frequency noise than do high speed logic families.

Since digital switching transients are composed largely of high frequency components, total ground plane copper

weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area

is more important than is total ground plane volume.

An effective way to control ground noise is by using a single, solid ground plane and splitting the power plane

into analog and digital areas and to have power and ground planes in adjacent board layers. There should be no

traces within either the power or the ground layers of the board. The analog and digital power planes should

reside in the same board layer so that they can not overlap each other. The analog and digital power planes

define the analog and digital areas of the board.

Mount digital components and run digital lines only in the digital areas of the board. Mount the analog

components and run analog lines only in the analog areas of the board. Be sure to treat all digital lines greater

that one inch for each nanosecond of rise time as transmission lines. That is, they should be of constant,

controlled impedance, be properly terminated at the source end and run from one point to another single point.

The back of the WQFN package has a large metal area inside the area bounded by the pins. This metal area is

connected to the die substrate (ground). This pad may be left floating if desired. If it is connected to anything, it

should be to ground near the connection between analog and digital ground planes. Soldering this metal pad to

ground will help keep the die cooler and could yield improved performance because of the lower impedance

between die and board grounds. However, a poor layout could compromise performance.

Generally, analog and digital lines should cross each other at 90° to avoid getting digital noise into the analog

path. In high frequency systems, however, avoid crossing analog and digital lines altogether. Clock lines should

be isolated from ALL other lines, analog AND digital. Even the generally accepted 90° crossing should be

avoided as even a little coupling can cause problems at high frequencies. Best performance at high frequencies

and at high resolution is obtained with a straight signal path.

Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit

in which they are used. Inductors should not be placed side by side with each other, not even with just a small

part of their bodies beside each other.

The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.

Any external component (e.g., a filter capacitor) connected between the converter's input and ground should be

connected to a very clean point in the ground plane.

DYNAMIC PERFORMANCE

The ADC1175-50 is a.c. tested and its dynamic performance is ensured. To meet the published specifications,

the clock source driving the CLK input must be free of jitter. For best a.c. performance, isolating the ADC clock

from any digital circuitry should be done with adequate buffers, as with a clock tree. See Figure 20.

Figure 20. Isolating the ADC Clock from Digital Circuitry

Product Folder Links: ADC1175-50

ADC1175-50

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SNAS027G –JANUARY 2000–REVISED APRIL 2013

It is good practice to keep the ADC clock line as short as possible and to keep it well away from any other

signals. Other signals can introduce jitter into the clock signal.

COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should

not go more than 50 mV below the ground pins or 50 mV above the supply pins. Exceeding these limits on even

a transient basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits to exhibit

undershoot that goes more than a volt below ground due to improper termination. A resistor of about 50Ωto

100Ωin series with the offending digital input, located close to the signal source, will usually eliminate the

problem.

Care should be taken not to overdrive the inputs of the ADC1175-50. Such practice may lead to conversion

inaccuracies and even to device damage.

Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers have to

charge for each conversion, the more instantaneous digital current is required from DVDD and DGND. These

large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the

digital data outputs (with a 74AC541, for example) may be necessary if the data bus to be driven is heavily

loaded. Dynamic performance can also be improved by adding 47Ωseries resistors at each digital output,

reducing the energy coupled back into the converter output pins.

Using an inadequate amplifier to drive the analog input. As explained in Applications Information, the ADC

input is a switched capacitor one and there are voltage spikes present there. This type if input is more difficult to

drive than is a fixed capacitance, and should be considered when choosing a driving device. The LMH6702 and

the LMH6609 have been found to be an excellent device for driving the ADC1175-50. Also remember to use the

RC between the driving source and the ADC input, as explained in THE ANALOG INPUT.

Driving the VRT pin or the VRB pin with devices that can not source or sink the current required by the

ladder. As mentioned in REFERENCE INPUTS, care should be taken to see that any driving devices can source

sufficient current into the VRT pin and sink sufficient current from the VRB pin. If these pins are not driven with

devices than can handle the required current, these reference pins will not be stable, resulting in a reduction of

dynamic performance.

Using a clock source with excessive jitter, using excessively long clock signal trace, or having other

signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive

output noise and a reduction in SNR performance. Simple gates with RC timing is generally inadequate as a

clock source.

Input test signal contains harmonic distortion that interferes with the measurement of dynamic signal to

noise ratio. Harmonic and other interfering signals can be removed by inserting a filter at the signal input.

Suitable filters are shown in Figure 21 and Figure 22. The circuit of Figure 21 has a cutoff of about 5.5 MHz and

is suitable for input frequencies of 1 MHz to 5 MHz. The circuit of Figure 22 has a cutoff of about 11 MHz and is

suitable for input frequencies of 5 MHz to 10 MHz. These filters should be driven by a generator of 75Ωsource

impedance and terminated with a 75Ωresistor.

Not considering the effect on a driven CMOS digital circuit(s) when the ADC1175-50 is in the power down

mode. Because the ADC1175-50 output goes into a high impedance state when in the power down mode, any

CMOS device connected to these outputs will have their inputs floating when the ADC is in power down. Should

the inputs of the circuit being driven by the ADC digital outputs float to a level near 2.5V, a CMOS device could

exhibit relative large supply currents as the input stage toggles rapidly. The solution is to use pull-down resistors

at the ADC outputs. The value of these resistors is not critical, as long as they do not cause excessive currents

in the outputs of the ADC1175-50. Low pull-down resistor values could result in degraded SNR and SINAD

performance of the ADC1175-50. Values between 5 kΩand 10 kΩshould work well.

Product Folder Links: ADC1175-50

ADC1175-50

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www.ti.com

Use with maximum input frequencies of 1 MHz to 5 MHz.

Figure 21. A 5.5 MHz Low Pass filter to eliminate harmonics at the signal input

Use with maximum input frequencies of 5 MHz to 10 MHz.

Figure 22. An 11 MHz Low Pass filter to eliminate harmonics at the signal input

Product Folder Links: ADC1175-50

ADC1175-50

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SNAS027G –JANUARY 2000–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision F (April 2013) to Revision G Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 20

Product Folder Links: ADC1175-50

PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ADC1175-50CIMTX/NOPB ACTIVE TSSOP PW 24 2500 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -20 to 75 ADC1175-50

CIMT

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADC1175-50CIMTX/NOP

BTSSOP PW 24 2500 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADC1175-50CIMTX/NOPB TSSOP PW 24 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

22X 0.65

7.15

24X 0.30

0.19

TYP

6.6

6.2

1.2 MAX

0.15

0.05

0.25

GAGE PLANE

-80

BNOTE 4

4.5

4.3

NOTE 3

7.9

7.7

0.75

0.50

(0.15) TYP

TSSOP - 1.2 mm max heightPW0024A

SMALL OUTLINE PACKAGE

4220208/A 02/2017

12 13

0.1 C A B

PIN 1 INDEX AREA

SEE DETAIL A

0.1 C

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

SEATING

PLANE

A 20

DETAIL A

TYPICAL

SCALE 2.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAX

ALL AROUND 0.05 MIN

ALL AROUND

24X (1.5)

24X (0.45)

22X (0.65)

(5.8)

(R0.05) TYP

TSSOP - 1.2 mm max heightPW0024A

SMALL OUTLINE PACKAGE

4220208/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SYMM

12 13

15.000

METAL

SOLDER MASK

OPENING METAL UNDER

SOLDER MASK SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

24X (1.5)

24X (0.45)

22X (0.65)

(5.8)

(R0.05) TYP

TSSOP - 1.2 mm max heightPW0024A

SMALL OUTLINE PACKAGE

4220208/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

SYMM

12 13

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