HDV24 ADP II SRAM eo 3.3 Volt x16 Asynchronous Dual-Port Static RAM Memory Configuration Device 4K x 16 HDV24 Key Features: * * * * * * * * * Industry leading Dual-Port Static RAM (up to 15ns) Simultaneous memory access through two ports LVTTL compatible; 3.3V power supply Easily expands bus width to 32 bits or more using the MASTER/SLAVE select function Supports Busy, Interrupt and Semaphore arbitration schemes Available packages: 100 - pin Thin Quad Flat Pack (TQFP) and 84 - pin Plastic Lead Chip Carrier (PLCC) (0C to 70C) Commercial operating temperature available for access time of 15ns and above (-40C to 85C) Industrial operating temperature available for access time of 25ns Pin-to-pin compatible with conventional dual-port devices including IDT (70V24) and Cypress (CY7C024AV) Product Description: The HDV24 Dual-Port Static RAM offers industry leading 0.25um process technology and 4K x 16 memory configuration. The device supports two memory ports with independent control, address, and I/O pins that enable simultaneous, asynchronous access to any location in memory. System designer has full flexibility of implementing deeper and wider memory using the depth and width expansion features. The HDV24 is a stand alone 64K-bit Dual-Port SRAM or as a MASTER/SLAVE combination Dual Port SRAM. The MASTER/SLAVE approach in 32 or more bit application offers bus width expansion without additional discrete logic. These devices have low power consumption, hence minimizing system power requirements. They are ideal for applications such as data communication, telecommunication, multiprocessing, test equipment, network switching, etc. 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 1 of 18 HDV24 ADP II SRAM Block Diagram of Dual Port Static RAM 4K x 16 R/ W L R/ W R UB L UB R L BL LB R C ER CE L OER OE L I/O 8-15 L I/O Control I/O0-7 I/O8-15 R I/O Control I/O0-7 R L BUSY L A 11L A0 L BUSYR Address Decoder CEL OEL SRAM Address Decoder Arbitration Interrupt Semaphore Logic CE R R/ WL A11 R A 0R OE R R/ WR SEM L SEM INT L INT R M/ S __________ R __________ Note: MASTER mode: BUSY is output. SLAVE mode: BUSY is input Figure 1. Device Architecture 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 2 of 18 HDV24 A10L 81 80 A7L A6L A11L 82 A9L A8L NC 89 UBL LBL OEL 90 SEML CEL I/O0L 91 VCC R/WL I/O1L I/O2L GND 97 I/O3L I/O6L 98 I/O5L I/O4L I/O7L I/O8L I/O9L ADP II SRAM Index 100 99 96 95 94 93 92 88 87 86 84 85 83 79 78 77 76 NC NC 1 75 NC 2 74 NC NC 3 73 NC NC 4 72 NC I/O10L 5 71 A5L I/O11L 6 70 A4L I/O12L 7 69 A3L I/O13L 8 68 A2L GND 9 67 A1L I/O14L 10 66 A0L I/O15L 11 65 INTL VCC 12 64 BUSYL GND 13 63 GND I/O0R 14 62 M/S I/O1R 15 61 BUSYR I/O2R 16 60 INTR VCC 17 59 A0R I/O3R 18 58 A1R I/O4R 19 57 A2R I/O5R I/O6R 20 56 21 55 A3R A4R NC 22 54 NC NC 23 53 NC NC 24 52 NC NC 25 51 NC 77 76 75 82 81 80 79 78 49 50 A5R A7R A8L 83 47 A6R A8R 84 A9L 1 A9R 2 A10L 3 A11R 4 46 A10R 5 45 NC A11L 6 44 NC 7 43 LBR OER 8 42 41 UBL LBL I/O15R 9 40 CER GND 10 39 UBR I/O14R 11 38 SEML CEL I/O13R Index 37 SEMR 36 VCC R/WL 35 GND 34 OEL 33 R/WR 32 I/O3L I/O2L GND I/O1L I/O0L 31 I/O12R I/O9R 30 I/O11R I/O8R 29 I/O6L I/O5L I/O4L 28 I/O10R 27 I/O7L 26 I/O7R TQFP-100 (Drw No: PF-04A; Order Code: PF) Top View 48 I/O8L I/O9L I/O10L 12 74 A7L 13 73 14 72 A6L A5L I/O11L I/O12L I/O13L 15 71 16 70 17 69 GND I/O14L I/O15L 18 68 19 67 VCC GND 21 I/O0R I/O1R I/O2R 23 63 24 62 25 61 VCC I/O3R I/O4R 26 60 27 59 28 58 I/O5R I/O6R I/O7R 29 57 30 56 31 55 I/O8R 32 20 66 PLCC-84 (Drw No: J-03A; Order Code: J) Top View 22 65 64 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A6R A9R A8R A7R 38 NC A11R A10R 37 SEMR CER UBR LBR 36 OER R/WR GND I/O10R I/O11R I/O12R I/O13R 35 I/O14R GND I/O15R 34 I/O9R 54 33 A4L A3L A2L Figure 2. Device Pin-Out 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 3 of 18 HDV24 ADP II SRAM Left Port Right Port ______ Name ______ C EL Symbol Rating Com & Ind Unit VTERM Terminal Voltage with respect to GND -0.5 to + 4.6 V TBIAS Temperature Under Bias -55 to +125 C C C ER Chip Enable R/WL R/WR Read / Write Enable OEL OER Output Enable A0L-11L A0R-11R Address I/O0L - 15L I/O0R - 15R Data Inputs / Outputs TSTG Storage Temperature -65 to +150 SEML SEMR Semaphore Enable 50 UB R Upper Byte Select IOUT DC Output Current UB L LBR Lower Byte Select INTR Interrupt Flag BUSYR Busy Flag Absolute Max Ratings are for reference only. Permanent damage to the device may occur if extended period of operation is outside this range. Standard operation should fall within the Recommended Operating Conditions. M/ S Master or Slave Select Table 2. Absolute Maximum Ratings Vcc Power GND Ground ____ ____ _____ _____ ________ ________ ______ ______ _____ _____ LBL ______ ______ INTL __________ BUSYL __________ ___ mA NOTES: Table 1. Pin Descriptions Symbol Parameter Commercial Temperature Industrial Temperature Min. Typ. Max. Min. Typ. Max. 3.0 3.3 3.6 3.0 3.3 3.6 V 0 0 0 0 0 0 V V Unit Recommended Operating Conditions VCC Supply Voltage Com'l/Ind'l GND Supply Voltage VIH VIL TA Input High Voltage Com'l/Ind'l 2.0 - - 2.0 - - Input Low Voltage Com'l/Ind'l - - 0.8 - - 0.8 V 0 - 70 -40 - 85 Input Leakage Current (any input) - - 10 - - 10 A Output Leakage Current - - 10 - - 10 A Output Logic "1" Voltage, IOH=-4mA 2.4 - - 2.4 - - V Output Logic "0" Voltage, IOL = 4mA - - 0.4 - - 0.4 V Operating Temperature C DC Electrical Characteristics ILI(1) ILO VOH VOL Capacitance at 1.0MHz Ambient Temperature (25C) Symbol Parameter (2) Input Capacitance CIN Output Capacitance COUT(2) Conditions(3) VIN= 3dV VOUT= 3dV Max. 9 11 Unit pF pF NOTES: 1. At Vcc < 2.0V, input leakage is undefined. 2. This parameter is determined by device characterization but is not production tested. 3. 3dV represents the interpolated capacitance when input and output signals switch from 0V to 3V or from 3V to 0V. 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 4 of 18 HDV24 ADP II SRAM Power Consumption Symbol ICC ISB1 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) ISB2 Standby Current (One Port - TTL Level Inputs) ISB3 Full Standby Current (Both Ports - All CMOS Level Inputs) ISB4 Standby Current (One Port - All CMOS Level Inputs) Conditions _____ Temp HDV24L15 HDV24L25 HDV24L35 Typ. Max. Typ. Max. Typ. Max. Outputs CE = VIL,________ Disabled, SEM = VIH, f=fMAX (1) C 140 185 125 165 115 155 I - - 125 180 - - _____ C 20 30 13 25 11 20 I - - 13 40 - - C 80 110 72 95 65 90 I - - 72 110 - - C 0.2 2.5 0.2 2.5 0.2 2.5 I - - 0.2 5 - - C 80 105 70 90 60 85 I - - 70 105 - - _____ CE L = CE R = VIH, ________ ________ SEMR = SEML = VIH, f=fMAX (1) _____ Unit mA mA _____ CEA = VIL and CEB = VIH Active Port Outputs (1) MAX Disabled, f=f _____ Both Ports CEL and _____ CER > Vcc - 0.2V, VIN > Vcc - 0.2V or V IN < 0.2V, f = 0 (2), ________ ________ SEMR = SEML > Vcc - 0.2V _____ _____ CEA < 0.2V and CEB ________ - 0.2V, SEMR > Vcc ________ = SEML > Vcc - 0.2V, Active Port Outputs Disabled, f=fMAX (1) mA mA mA NOTES: 1. At f = fMAX, address and I/O's are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions" of input levels of GND to 3V. 2. f = 0: no control and address bits change. 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 5 of 18 HDV24 ADP II SRAM Commercial & Industrial HDV24-15 Symbol Parameter HDV24-25 HDV24-35 Min. Max. Min. Max. Min. Max. Unit 15 - 25 - 35 - ns Read Cycle tRC Read Cycle Time tAA Address Access Time - 15 - 25 - 35 ns tACE Chip Enable Access Time - 15 - 25 - 35 ns tABE Byte Enable Access Time - 15 - 25 - 35 ns tAOE Output Enable Access Time - 10 - 13 - 20 ns tOH Output Hold from Address Change 3 - 3 - 3 - ns tLZ Output Low-Z Time 3 - 3 - 3 - ns tHZ Output High-Z Time - 10 - 12 - 15 ns tPU Chip Enable to Power Up Time 0 - 0 - 0 - ns tPD Chip Disable to Power Down Time - 15 - 25 - 35 ns tSOP Semaphore Flag Update Pulse 10 - 10 - 12 - ns tSAA Semaphore Address Access Time - 15 - 25 - 35 ns Write Cycle tWC Write Cycle Time 15 - 25 - 35 - ns tEW Chip Enable to End-of-Write 12 - 20 - 30 - ns tAW Address Valid to End-of-Write 12 - 20 - 30 - ns tAS Address Set-up Time 0 - 0 - 0 - ns tWP Write Pulse Width 12 - 20 - 25 - ns tWR Write Recovery Time 0 - 0 - 0 - ns tDW Data Valid to End-of-Write 10 - 15 - 15 - ns tHZ Output High-Z Time - 10 - 15 - 15 ns tDH Data Hold Time 0 - 0 - 0 - ns tWZ Write Enable to Output in High-Z - 10 - 15 - 15 ns tOW Output Active from End-of-Write 0 - 0 - 0 - ns tSWRD ________ SEM Flag Write to Read Time 5 - 5 - 5 - ns tSPS SEM Flag Contention Window ________ 5 - 5 - 5 - ns NOTES: 1. 2. 3. 4. Test conditions defined in Figs. 3 & 4 are used. This parameter is guaranteed, but not tested. ______ __________ ______ __________ To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. Table 3. AC Electrical Characteristics 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 6 of 18 HDV24 ADP II SRAM Commercial & Industrial HDV24-15 Symbol Parameter HDV24-25 HDV24-35 Min Max. Min. Max. Min. Max. Unit Interrupt Timing tAS Address Set-up Time 0 - 0 - 0 - ns tWR Write Recover Time 0 - 0 - 0 - ns tINS Interrupt Set Time - 15 - 20 - 25 ns tINR Interrupt Reset Time - 15 - 20 - 25 ns - 15 - 20 - 20 ns - 15 - 20 - 20 ns - 15 - 20 - 20 ns ___________ ___ BUSY Timing (M/S = VIH) __________ tBAA BUSY Access Time form Address Match __________ tBDA BUSY Disable Time from Address Not Matched tBAC BUSY Access Time from Chip Enable Low tBDC BUSY Access Time from Chip Enable High - 15 - 17 - 20 ns tAPS Arbitration Priority Set-up Time 5 - 5 - 5 - ns tBDD __________ BUSY Disable to Valid Data - 18 - 30 - 35 ns tWH Write Hold after BUSY 12 - 17 - 25 - ns 0 - 0 - 0 - ns 12 - 17 - 25 - ns __________ __________ __________ ___________ ___ BUSY Timing (M/S = VIL) __________ tWB BUSY Input to Write tWH Write Hold after BUSY __________ Port-to-Port Delay Timing tWDD Write Pulse to Data Delay - 30 - 50 - 60 ns tDDD Write Data Valid to Read Data Delay - 25 - 35 - 45 ns NOTES: 1. 2. 3. 4. 5. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY". To ensure that the earlier of the two ports wins. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tDDD - tDW (actual). To ensure that the write cycle is inhibited on port "B" during contention with port "A". To ensure that a write cycle is completed on port "B" after contention on port "A". Table 3. AC Electrical Characteristics (Continued) 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 7 of 18 HDV24 ADP II SRAM 3.3V 3.3V 590 Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Refer to Figure 3 & 4 D.U.T. BUSY INT 435 590 D.U.T. 30pF 5pF* 435 Figure 4. Output Test Load for tLZ, tHZ, tWZ, tOW *Includes jig and scope capacitances. Figure 3. AC Output Load NOTES: 1. Include jig and scope capacitances Table 4. AC Test Condition Inputs(1) ______ ____ CE H R/W X X X L ______ OE X Outputs ______ _____ _________ Mode SEM H I/O8-15 I/O0-7 High-Z High-Z Deselected: Power-Down H H High-Z High-Z Both Bytes Deselected H H Data In High-Z Write to Upper Byte Only High-Z Data In Write to Lower Byte Only Data In Data In Write to Both Bytes Data Out High-Z Read Upper Byte Only H High-Z Data Out Read Lower Byte Only L H Data Out Data Out Read Both Bytes X X High-Z High-Z Outputs Disabled UB X LB X X H L X L L L X H L H L L X L L H L H L L H H L H L H L L H L L X X H X NOTES: 1. A0L-11L A0R-11R. Table 5. Truth Table - Non-Contention Read/Write Control Inputs(1) ______ ____ Outputs ______ ______ OE L UB X _____ LB X _________ SEM L I/O8-15 I/O0-7 Mode CE H R/W H Data Out Data Out Read Data in Semaphore Flag X H L H H L Data Out Data Out Read Data in Semaphore Flag H X X X L Data In Data In Write I/O0 into Semaphore Flag X X H H L Data In Data In Write I/O0 into Semaphore Flag L X X L X L - - Not Allowed L X X X L L - - Not Allowed NOTES: 1. There are 8 semaphore flags written to I/O0 and read from all I/Os (I/00-15). These 8 semaphore flags are addressed A0-2. Table 6. Truth Table - Semaphore Read/Write Control 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 8 of 18 HDV24 ADP II SRAM Left Port Right Port ______ UB / _____ LB X ______ ____ ______ R/W CE ______ OE A11-0 _______ UB / INT ______ ______ OE A11-0 INT _______ Mode X X X X L(2) Set Right INT Flag ____ R/W _____ CE L L X FFF X LB X X X X X X X X X L L FFF H(2) Reset Right INT Flag X X X X X L(2) X L L X FFE X Set Left INT Flag X X L L FFE H(2) X X X X X X Reset Left INT Flag NOTES: _______ _______ _______ _______ __________ 1. Assuming BUSY = VIH. __________ 2. If BUSY = VIL, then no change. _______ 3. I N T must be initialized at power-up. Table 7. Truth Table - Interrupt Flag Inputs ______ CE L X ______ Outputs A11-0 __________ (1) BUSY L H __________ BUSY R(1) H Function CE R X No Match H X Match H H Normal X H Match H H Normal L L Match (2) (2) Write Inhibit(3) NOTES: __________ Normal __________ __________ 1. When part is configured as master, BUSYL and BUSYR are both outputs. When configured as slave, both are inputs and internally inhibits writes. BUSY outputs are pushpull, not open drain. 2. If inputs to opposite port were stable prior to address and enable inputs of this port, then "L." If inputs to the opposite port became stable after the address the enable inputs of __________ __________ __________ __________ port, then "H." If tAPS is not met, then either BUSYL or BUSYR = LOW. BUSYL and BUSYR cannot be LOW simultaneously __________ 3. Writes to one port are internally ignored when its BUSY outputs are LOW regardless of actual logic level on the pin. __________ Table 8. Truth Table - Address BUSY Arbitration Functions Left D0-15 Right D0-15 Status No Action 1 1 Semaphore free Left port writes "0" to semaphore 0 1 Left port has semaphore token Right port writes "0" to semaphore 0 1 No change. Right port has no write access to semaphore Left port writes "1" to semaphore 1 0 Right port obtains semaphore token Left port writes "0" to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes "1" to semaphore 0 1 Left port obtains semaphore token Left port writes "1" to semaphore 1 1 Semaphore free Right port writes "0" to semaphore 1 0 Right port has semaphore token Right port writes "1" to semaphore 1 1 Semaphore free Left port writes "0" to semaphore 0 1 Left port has semaphore token Left port writes "1" to semaphore 1 1 Semaphore free NOTES: 1. Table shows sequence of events for one of the eight semaphores. 2. There are eight semaphore flags (A0-2) written via I/O0 and read from I/O0-15. _____ ________ 3. CE = VIH, SEM = VIL to access semaphores. 4. Refer to Table 6. Table 9. Truth Table - Semaphore Procurement Sequence Example 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 9 of 18 HDV24 ADP II SRAM Timing Diagrams tRC ADDR t AA t ACE (4) CE t AOE(4) OE t ABE(4) UB, LB R/W t OH t LZ (1) Data Out Valid Data(4) t HZ (2) BUSYOut t BDD (3,4) NOTES: ______ ______ 1. tLZ timing is based on which signal is asserted last, C E ______ or OE .______ 2. tHZ timing is based on which signal is de-asserted first, C E or OE . _________ 3. tBDD is needed only where the opposite port is completing a write operation to the same address. BUSY has no effect on valid output data. 4. Valid data starts from the last of tAOE, tACE, tAA or tBDD. Diagram 1. Read Cycles 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 10 of 18 HDV24 ADP II SRAM tWC ADDR tHZ (7) OE tAW CE UB, LB tAS (6) tWR (3) tWP (2) R/W tWZ Data Out tOW (4) (4) tDH tDW Data In ____ Diagram 2. Write Cycle No. 1, R/W Controlled Timing tWC ADDR tAW CE, SEM tAS(6) tEW(2) tRW(3) UB, LB R/W tDW tDH Data In _____ Diagram 3. Write Cycle No. 2, CE Controlled Timing NOTES: ____ ______ 1. R/W or C E must be ______ HIGH during all ____ address transitions. 2. A write occurs when C E = VIL and R/W = ____ VIL for memory write cycle. ______ 3. tWR timing is from the earlier of C E or R/W going HIGH to the end of write cycle. 4. The ______ I/O pins are in the output state and input signals must not be applied during DATA out period. ____ 5. For C E =VIL transition simultaneously with or after the R/W = VIL transition, the outputs remain in the high-impedance state. ______ ____ 6. tAS timing is based on latter of C E or R/W . 7. tHZ transition is measured 0mV from steady state with the Output Test Load. _____ ____ 8. For OE =VIL during R/W write cycle, the write pulse width is the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required _____ ____ tDW. If OE = VIH during an R/W controlled writing cycle, the write pulse is specified as tWP. 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 11 of 18 HDV24 ADP II SRAM t SAA A0-A2 Valid Address t AW SEM t OH Valid Address t WR t ACE t EW t SOP t DW Data In Valid I/O0 t AS t WP Data Out Valid (2) t DH R/W t SWRD t AOE OE Write Cycle NOTES: _____ ______ Read Cycle ______ 1. CE = VIH or UB and L B = VIH for the duration of the above timing (both write and read cycle). 2. "DATA OUT VALID" represents all I/O's (I/O0-15) equal to the semaphore value Diagram 4. Semaphore Read after Write Timing, Either Side A 0 A -A 2 A S ID E A M a tc h R /W A SEM A tSPS A 0 B -A 2 B S ID E B M a tc h R /W B SEM B NOTES: _____ _____ 1. DOR = DOL = VIL, CEL = CER =VIH. 2. Timing for both ports is the same. Port B is________ opposite of port A. ____ ____ ________ 3. This parameter is measured from R/W A or SEMA =VIH to R/WB or SEMB= VIH. 4. The semaphore will be sent to either side if tSPS is not met. It cannot be guaranteed which side receives semaphore. Diagram 5. Semaphore Write Contention 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 12 of 18 HDV24 ADP II SRAM tWC AD D R A M atch tWP R /W A tDW D ata In A tDH Valid t A P S (1 ) M atch ADD R B t BAA t BDA BUSY B t BDD t W DD Valid D ata OutB t D DD ( 3 ) NOTES: ___ 1. _____ tAPS is_____ ignored for SLAVE part (M/S = VIL) 2. CE L =CER = VIH. _____ 3. OE = VIL for the reading port. ___________ ___ 4. For SLAVE mode (M/S = VIL), BUSY is an input. 5. Timing for both ports is the same. Port B is opposite of port A. ___________ __ Diagram 6. Write with Port-to-Port Read and BUSY (M/S = VIH) t WP R/WA t W B (3 ) t W H (1 ) BUSY B R/WB NOTES: ___________ (2) ___________ 1. ___________ SLAVE (BUSY input) and MASTER (BUSY output) must meet tWH. ____ ___________ 2. BUSY is sent to port B blocking R/W B till BUSYB=VIH. 3. tWB is for SLAVE mode. ___________ __ Diagram 7. Write with BUSY (M/S = VIL) 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 13 of 18 HDV24 ADP II SRAM AD D R A and AD D R B Addre sse s M atch CE A tAPS CE B t BAC t BDC BUSY B ___________ _____ __ Diagram 8. BUSY Arbitration Controlled by CE Timing (M/S = VIH) ADDR A Addre sse s N t AP S ( 1 ) ADDR B M atching Addre sse s N t BAA t BD A BUSY B NOTES: ___________ 1. If tAPS is not satisfied, the BUSY signal will be asserted randomly on one side or the other. ___________ __ Diagram 9. BUSY Arbitration Controlled by Address Match Timing (M/S = VIH) 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 14 of 18 HDV24 ADP II SRAM tWC AD D R A Inte rrupt Se t Addre ss (2 ) t A S (3 ) CE A R /W A t W R (4 ) t IN S (3 ) IN T B t RC AD D R Inte rrupt Cle ar Addre ss B (2) t A S (3 ) CE B OE B t IN R ( 3 ) IN T B NOTES: 1. 2. 3. 4. Port A and B can be either left or right port. If Port A is left port, Port B is right port. If Port A is right port, Port B is left port. Refer to Table 7. ______ ____ Timing depends on which enable signal (C E or R/W ) is asserted last. ______ ____ Timing depends on which enable signal (C E or R/W ) is de-asserted last. Diagram 10. Interrupt Timing 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 15 of 18 HDV24 ADP II SRAM Functional Description HDV24 supports two memory ports with independent control, address, and I/O pins that enable simultaneous, asynchronous access to any location in memory. Interrupts A special memory location is associated with each port when the interrupt function is used. These special memory locations are best considered as mailboxes between the two ports and the corresponding interrupt signals as _______ the flags of the mailboxes. When the right port writes a data word to the special location FFE (HEX), the left port interrupt flag (INT L) becomes _____ ____ _______ active or LOW (a data write is defined as CE R = R/W R = VIL). The left port can clear INT (HIGH) through either read or write L _____ _____ ____ access of the same memory location FFE (a data access is defined as CEL = OEL = VIL, and the value of R/W is _______ irrelevant in the case). Similarly, when the left port writes to the memory location FFF (HEX), the _______ right port interrupt flag (INT R) becomes asserted (LOW). The right port must access the memory location FFF in order to clear INT R (HIGH). The exact value of the data word at address FFE or FFF is user defined, and is irrelevant as far as the interrupt logic is concerned. If the user chooses not to use the interrupt function, the two special memory locations (FFE and FFF) are treated as part of the regular dual-port memory, and the interrupt flags can simply be ignored. Busy Logic When both ports attempt to access the same memory location at the same time, data corruption can potentially occur. In ___ the single-device or MASTER configuration (i.e. when the M/ S pin is tied HIGH), the on-chip Busy Logic arbitrates simultaneous accesses to the same memory location, and __________ determines the "winner" between the two ports. If Busy Logic considers the right port lost in the arbitration, then the right port B U S Y pin is set active (LOW) to signal the system that this memory location is "busy" being accessed by the other__________ port. Furthermore, the Busy Logic prevents the right port from writing to the same memory location for as long as the right port B U S Y signal stays active (LOW). Once the left port finishes access to this memory __________ location, the dual-port SRAM signals the system by setting the right port B U S Y pin back to inactive (HIGH), so that the system can resume its normal access from the right port. Note that only the write operation from the losing port is inhibited; the read operation is nondestructive and can thus continue regardless of the arbitration result. __________ The B U S Y pins are output pins in the single-device or MASTER mode, but become input pins instead when the ___ device is configured in SLAVE mode (this is accomplished by tying M/ S pin LOW). In SLAVE mode the on-chip arbitration __________ logic is disabled, and the device relies on the input __________ B U S Y signals for the results of arbitration when simultaneous access to the same memory location occurs. Specifically, when a B U S Y pin is set to HIGH, normal operation can be performed from this port, ___________ but when a B U S Y pin is set to LOW, write operations will be inhibited from this port. If width expansion with multiple HBA HDV24 devices is used, it is recommended that only one of them be configured in MASTER mode, and the rest of them in __________ __________ SLAVE mode. The B U S Y (output) signal from the master device should be connected to the respective B U S Y (input) pins of the slave devices. This means that only one device (the master) is performing the Busy Logic arbitration, and all the other devices (the slaves) will follow this arbitration accordingly. This can prevent the conflicts caused by the potential inconsistent arbitration results from different dual-port SRAM devices. Note that if the user does not wish the write operation to be inhibited by the Busy __________ Logic, the user can disable this feature by configuring the device in SLAVE mode and tying the B U S Y input pins to HIGH. The Busy arbitration logic is triggered whenever the two ports simultaneously attempt to access the same memory location, where____ data accesses are determined by the timings and values of the Address and Chip Enable signals only, not by the value of the R/ W signal. This means that both read and write operations can trigger the Busy Logic, even though only the write operation is inhibited from the losing port. Note that in a master/slave configuration, an additional timing constraint concerning ____ the R/ W signal needs to be met in order to prevent data corruption in the slave device: the write operation in the slave device __________ __________ cannot start before the B U S Y signal - which originates from the output B U S Y pin - is received by the slave device to ensure ____ write inhibition. In other words, the R/ W signal needs to stay high from the__________ time the Busy Logic on the master device is triggered (through the changing of the Address and Chip Enable signals) till the B U S Y signal is received by the slave device. Semaphores A semaphore can be considered as a special one-bit dual-port memory cell that can be "owned" by (or granted to) only one port at any given time. Typically a semaphore is used as an arbiter for the exclusive ownership (or access privilege) of any shared resource in a system. A semaphore ownership can be requested by writing a zero "0" to the semaphore; a semaphore ownership can be relinquished by writing a one "1" to the semaphore; and a semaphore ownership can be tested by reading from 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 16 of 18 HDV24 ADP II SRAM the semaphore - a readout of zero "0" means that the semaphore is owned by this port, while a readout of one "1" means that either the semaphore is owned by the other port, or there is no owner at all. A token-passing system can be used to conceptualize the semaphore mechanism: requesting for the semaphore ownership is equivalent to requesting for the token, and relinquishing the semaphore ownership is equivalent to releasing the token. HBA HDV24 device provides eight addressable semaphores in addition to the regular 4K x 16 dual-port memory space. A typical sequence of accessing a semaphore is as follows: first a port attempts to request for the token by writing a zero "0" to the semaphore. The result of the request is then tested by reading from the semaphore: if the readout is zero "0", then the token request has succeeded; but if the readout is one "1", then the token request has failed. The requester should then try to repeatedly read from the semaphore until the readout becomes zero "0", upon which time the requester becomes the new possessor of the token, and can be granted exclusive access privilege to the shared resource the semaphore represents. In the case when both ports request for the token at the same time, the semaphore logic ensures that only one port is granted the token. In other words, at most one of the two semaphore readout ports can assume the value of zero "0". When the token is not owned by any port, the semaphore will appear to contain the value one "1" to both ports. Note that a failed token request becomes an outstanding token request, and will remain valid until either the other port releases the token (which means the requester now becomes the new possessor of the token), or when the outstanding request is withdrawn by writing a one "1" to the semaphore before the other port releases the token. ________ Semaphore accesses are distinguished from the regular memory access through the use of the semaphore select (S E M ) ________ signal: S E M should remain HIGH when the regular dual-port memory is being accessed, but should be tied LOW when _____ ____ semaphores are being accessed. Other control signals such as C E , and R/ W behave identically in both cases. Address pins A0 to A2 are used to address the eight semaphore flags (the values of the other address pins are irrelevant to semaphores). Only data pin D0 is used when writing to a semaphore. However, when reading from a semaphore, the one-bit semaphore value will be duplicated on all data pins (D0-D15). Note that the semaphore logic is not automatically initialized during power up. The system has to handle the initialization of the semaphores during power up by writing ones from both sides to all semaphores to ensure their availabilities for future use. As discussed previously, semaphores are typically used to resolve contentions of shared resources in a system. These shared resources can be a common data bus, a bi-directional shared buffer, or even a segment of the dual-port SRAM on an HBA HDV24 device. Before any component in the system attempts to gain exclusive access to a shared resource, the semaphore can be used to ensure that no resource contention or data corruption will occur. One advantage in using hardware-supported semaphores is performance improvement by eliminating the processor wait states. HBA HDV24 semaphores also provide system designers with higher flexibility because the resource sharing can be managed much more easily. With proper system software support, semaphores can even replace the Busy arbitration logic in certain cases, albeit with a coarser data granularity. 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. PRELIMINARY Page 17 of 18 HDV24 ADP II SRAM Order Information: HBA Device Family Device Type Power Speed (ns)* Package** Temperature Range XX HD XXX V24 (4K x 16) X Low XX 15 XX PF X Blank - Commercial (0C to 70C) 25 J I - Industrial (-40 to 85C) 35 *Speed - Slower speeds available upon request. **Package - 100 pin Plastic Thin Quad Flat Pack (TQFP), 84 pin Plastic Lead Chip Carrier (PLCC) Temperature - Industrial only offered in 25ns Example: HDV24L15PF (4K x 16, 15ns, Commercial temp) USA 2107 North First Street, Suite 415 San Jose, CA 95131, USA Tel: 408.453.8885 Fax: 408.453.8886 www.hba.com Taiwan No. 81, Suite 8F-9, Shui-Lee Rd. Hsinchu, Taiwan, R.O.C. Tel: 886.3.516.9118 Fax: 886.3.516.9181 www.hba.com Europe CDE Technology B.V. Nijverheidslaan 28 1382 L J Weesp, The Netherlands Tel: 31.294.280.914 Fax: 31.294.280.919 www.hba.com 3HD166A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to change without notice. 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