HDV24L35J - AMIC Technology, Corp.

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eo

3.3 Volt x16 Asynchronous Dual-Port Static RAM

Memory Configuration Device

4K x 16 HDV24

Key Features:

• Industry leading Dual-Port Static RAM (up to 15ns)

• Simultaneous memory access through two ports

• LVTTL compatible; 3.3V power supply

• Easily expands bus width to 32 bits or more using the MASTER/SLAVE select function

• Supports Busy, Interrupt and Semaphore arbitration schemes

• Available packages: 100 – pin Thin Quad Flat Pack (TQFP) and 84 – pin Plastic Lead Chip Carrier (PLCC)

• (0°C to 70°C) Commercial operating temperature available for access time of 15ns and above

• (-40°C to 85°C) Industrial operating temperature available for access time of 25ns

• Pin-to-pin compatible with conventional dual-port devices including IDT (70V24) and Cypress (CY7C024AV)

Product Description:

The HDV24 Dual-Port Static RAM offers industry leading 0.25um process technology and 4K x 16 memory configuration. The

device supports two memory ports with independent control, address, and I/O pins that enable simultaneous, asynchronous access

to any location in memory. System designer has full flexibility of implementing deeper and wider memory using the depth and

width expansion features.

The HDV24 is a stand alone 64K-bit Dual-Port SRAM or as a MASTER/SLAVE combination Dual Port SRAM. The

MASTER/SLAVE approach in 32 or more bit application offers bus width expansion without additional discrete logic.

These devices have low power consumption, hence minimizing system power requirements. They are ideal for applications such

as data communication, telecommunication, multiprocessing, test equipment, network switching, etc.

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SRAM

Arbitration

Interrupt

Semaphore

Logic

Bl ock Di agram of Dual Port Stati c RAM

4K x 16

I/O

Control

Address

Decoder

I/O

Control

Address

Decoder

BUSY

SEM

INT

WR/

UB

OE

LB

WR/

OE

CE

SM/

I/O

8-15

I/O

0-7

A11

A0

BUSY

SEM

INT

WR/

UB

OE

LB

CE

I/O

8-15

I/O

0-7

A11

A0

WR/

OE

CE

L

R

L

R

Note: MASTER mode: BUSY

__________

is output. SLAVE mode: BUSY

__________

is input

Figure 1. Device Architecture

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I/O6L

I/O4L

I/O2L

I/O3L

GND

I/O15R

OER

R/WR

GND

CER

I/O13R

I/O9R

I/O10R

I/O11R

I/O12R

UBR

SEMR

I/O14R

I/O8R

I/O7R

NC

A5L

A4L

A3L

A2L

A1L

A0L

INTL

BUSYL

GND

M/S

BUSYR

INTR

NC

I/O10L

I/O11L

I/O12L

I/O13L

GND

I/O14L

I/O15L

VCC

GND

I/O1R

I/O2R

NC

I/O0R

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85

Index

TQFP-100

(Drw No: PF-04A; Order Code: PF)

Top View

I/O9L

I/O8L

I/O7L

I/O5L

I/O1L

I/O0L

OEL

VCC

R/WL

SEML

CEL

NC

VCC

I/O3R

I/O4R

I/O5R

I/O6R

NC

17

18

19

20

21

22

23

24

25

42 43 44 45 46 47 48 49 50

LBR

NC

A11R

A10R

A9R

A7R

A6R

A8R

A5R

59

58

57

56

55

54

53

52

51

A0R

A1R

A2R

A3R

A4R

NC

UBL

LBL

NC

A11L

A10L

A9L

A8L

A7L

A6L

84 83 82 81 80 79 78 77 76

I/O4L

I/O2L

I/O1L

GND

I/O0L

OER

R/WR

GND

SEMR

CER

LBR

GND

I/O11R

I/O12R

I/O13R

I/O14R

NC

UBR

I/O15R

I/O10R

I/O9R

A6L

A5L

A4L

A3L

A2L

A1L

A0L

INTL

BUSYL

GND

M/S

BUSYR

INTR

A0R

A1R

I/O9L

I/O10L

I/O11L

I/O12L

I/O13L

GND

I/O14L

I/O15L

VCC

GND

I/O0R

I/O1R

VCC

I/O3R

I/O8L

I/O2R

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

11109876543218483828180

Index

PLCC-84

(Drw No: J-03A; Order Code: J)

Top View

I/O7L

I/O6L

I/O5L

I/O3L

OEL

VCC

R/WL

SEML

CEL

UBL

LBL

A7L

I/O4R

I/O5R

I/O6R

I/O7R

I/O8R

28

29

30

31

32

49 50 51 52 53

A11R

A10R

A9R

A8R

A7R

58

57

56

55

54

A2R

A3R

A4R

A5R

A6R

NC

A11L

A10L

A9L

A8L

79 78 77 76 75

Figure 2. Device Pin-Out

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Table 1. Pin Descriptions

Left Port Right Port Name

CE

______

L CE

______

R Chip Enable

R/W

____

L R/W

____

R Read / Write Enable

OE

_____

L OE

_____

R Output Enable

A0L-11L A

0R-11R Address

I/O0L – 15L I/O0R – 15R Data Inputs / Outputs

SEM

________

L SEM

________

R Semaphore Enable

UB

______

L UB

______

R Upper Byte Select

LB

_____

L LB

_____

R Lower Byte Select

INT

______

L INT

______

R Interrupt Flag

BUSY

__________

L BUSY

__________

R Busy Flag

M/S

___

Master or Slave Select

Vcc Power

GND Ground

NOTES:

Absolute Max Ratings are for reference only. Permanent damage to the device may occur if extended

period of operation is outside this range. Standard operation should fall within the Recommended

Operating Conditions.

Table 2. Absolute Maximum Ratings

Symbol Rating Com & Ind Unit

VTERM Terminal Voltage with

respect to GND -0.5 to + 4.6 V

TBIAS Temperature Under Bias -55 to +125 °C

TSTG Storage Temperature -65 to +150 °C

IOUT DC Output Current 50 mA

Commercial Temperature Industrial Temperature

Symbol Parameter Min. Typ. Max. Min. Typ. Max.

Unit

Recommended Operating Conditions

VCC Supply Voltage Com’l/Ind’l 3.0 3.3 3.6 3.0 3.3 3.6 V

GND Supply Voltage 0 0 0 0 0 0 V

VIH Input High Voltage Com’l/Ind’l 2.0 - - 2.0 - - V

VIL Input Low Voltage Com’l/Ind’l - - 0.8 - - 0.8 V

TA Operating Temperature 0 - 70 -40 - 85 °C

DC Electrical Characteristics

ILI(1) Input Leakage Current (any input) - - 10 - - 10 µA

ILO Output Leakage Current - - 10 - - 10 µA

VOH Output Logic “1” Voltage, IOH=-4mA 2.4 - - 2.4 - - V

VOL Output Logic “0” Voltage, IOL = 4mA - - 0.4 - - 0.4 V

Capacitance at 1.0MHz Ambient Temperature (25°C)

Symbol Parameter Conditions(3) Max. Unit

CIN(2) Input Capacitance VIN= 3dV 9 pF

COUT(2) Output Capacitance VOUT= 3dV 11 pF

NOTES:

1. At Vcc < 2.0V, input leakage is undefined.

2. This parameter is determined by device characterization but is not production tested.

3. 3dV represents the interpolated capacitance when input and output signals switch from 0V to 3V or from 3V to 0V.

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Power Consumption

HDV24L15 HDV24L25 HDV24L35

Symbol Parameter Conditions Temp

Typ. Max. Typ. Max. Typ. Max.

Unit

C 140 185 125 165 115 155

ICC

Dynamic

Operating

Current (Both

Ports Active)

CE

_____

= VIL, Outputs

Disabled, SEM

________

= VIH,

f=fMAX (1) I - - 125 180 - -

mA

C 20 30 13 25 11 20

ISB1

Standby Current

(Both Ports –

TTL Level

Inputs)

CE

_____

L = CE

_____

R = VIH,

SEM

________

R = SEM

________

L = VIH,

f=fMAX (1) I - - 13 40 - -

mA

C 80 110 72 95 65 90

ISB2

Standby Current

(One Port – TTL

Level Inputs)

CE

_____

A = VIL and CE

_____

B =

VIH

Active Port Outputs

Disabled, f=fMAX (1)

I - - 72 110 - -

mA

C 0.2 2.5 0.2 2.5 0.2 2.5

ISB3

Full Standby

Current (Both

Ports – All

CMOS Level

Inputs)

Both Ports CE

_____

L and

CE

_____

R > Vcc – 0.2V,

VIN > Vcc – 0.2V or

VIN < 0.2V, f = 0 (2),

SEM

________

R = SEM

________

L > Vcc

– 0.2V

I - - 0.2 5 - -

mA

C 80 105 70 90 60 85

ISB4

Standby Current

(One Port – All

CMOS Level

Inputs)

CE

_____

A < 0.2V and CE

_____

B

> Vcc – 0.2V, SEM

________

R

= SEM

________

L > Vcc –

0.2V, Active Port

Outputs Disabled,

f=fMAX (1)

I - - 70 105 - -

mA

NOTES:

1. At f = fMAX, address and I/O’s are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.

2. f = 0: no control and address bits change.

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Commercial & Industrial

HDV24-15 HDV24-25 HDV24-35

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

Read Cycle

tRC Read Cycle Time 15 - 25 - 35 - ns

tAA Address Access Time - 15 - 25 - 35 ns

tACE Chip Enable Access Time - 15 - 25 - 35 ns

tABE Byte Enable Access Time - 15 - 25 - 35 ns

tAOE Output Enable Access Time - 10 - 13 - 20 ns

tOH Output Hold from Address Change 3 - 3 - 3 - ns

tLZ Output Low-Z Time 3 - 3 - 3 - ns

tHZ Output High-Z Time - 10 - 12 - 15 ns

tPU Chip Enable to Power Up Time 0 - 0 - 0 - ns

tPD Chip Disable to Power Down Time - 15 - 25 - 35 ns

tSOP Semaphore Flag Update Pulse 10 - 10 - 12 - ns

tSAA Semaphore Address Access Time - 15 - 25 - 35 ns

Write Cycle

tWC Write Cycle Time 15 - 25 - 35 - ns

tEW Chip Enable to End-of-Write 12 - 20 - 30 - ns

tAW Address Valid to End-of-Write 12 - 20 - 30 - ns

tAS Address Set-up Time 0 - 0 - 0 - ns

tWP Write Pulse Width 12 - 20 - 25 - ns

tWR Write Recovery Time 0 - 0 - 0 - ns

tDW Data Valid to End-of-Write 10 - 15 - 15 - ns

tHZ Output High-Z Time - 10 - 15 - 15 ns

tDH Data Hold Time 0 - 0 - 0 - ns

tWZ Write Enable to Output in High-Z - 10 - 15 - 15 ns

tOW Output Active from End-of-Write 0 - 0 - 0 - ns

tSWRD SEM

________

Flag Write to Read Time 5 - 5 - 5 - ns

tSPS SEM

________

Flag Contention Window 5 - 5 - 5 - ns

NOTES:

1. Test conditions defined in Figs. 3 & 4 are used.

2. This parameter is guaranteed, but not tested.

3. To access RAM, CE

______

= VIL, SEM

__________

= VIH. To access semaphore, CE

______

= VIH, SEM

__________

= VIL.

4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will

vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW.

Table 3. AC Electrical Characteristics

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Commercial & Industrial

HDV24-15 HDV24-25 HDV24-35

Symbol Parameter Min Max. Min. Max. Min. Max. Unit

Interrupt Timing

tAS Address Set-up Time 0 - 0 - 0 - ns

tWR Write Recover Time 0 - 0 - 0 - ns

tINS Interrupt Set Time - 15 - 20 - 25 ns

tINR Interrupt Reset Time - 15 - 20 - 25 ns

BUSY

___________

Timing (M/S

___

= VIH)

tBAA BUSY

__________

Access Time form Address Match - 15 - 20 - 20 ns

tBDA BUSY

__________

Disable Time from Address Not

Matched - 15 - 20 - 20 ns

tBAC BUSY

__________

Access Time from Chip Enable

Low - 15 - 20 - 20 ns

tBDC BUSY

__________

Access Time from Chip Enable

High - 15 - 17 - 20 ns

tAPS Arbitration Priority Set-up Time 5 - 5 - 5 - ns

tBDD BUSY

__________

Disable to Valid Data - 18 - 30 - 35 ns

tWH Write Hold after BUSY

__________

12 - 17 - 25 - ns

BUSY

___________

Timing (M/S

___

= VIL)

tWB BUSY

__________

Input to Write 0 - 0 - 0 - ns

tWH Write Hold after BUSY

__________

12 - 17 - 25 - ns

Port-to-Port Delay Timing

tWDD Write Pulse to Data Delay - 30 - 50 - 60 ns

tDDD Write Data Valid to Read Data Delay - 25 - 35 - 45 ns

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY”.

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port “B” during contention with port “A”.

5. To ensure that a write cycle is completed on port “B” after contention on port “A”.

Table 3. AC Electrical Characteristics (Continued)

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Input Pulse Levels GND to 3.0V

Input Rise/Fall Times 3ns

Input Timing Reference Levels 1.5V

Output Reference Levels 1.5V

Output Load Refer to Figure 3 & 4

Figure 4. Output Test Load

for tLZ, tHZ, tWZ, tOW

*Includes jig and scope capacitances.

Figure 3. AC Output Load

D.U.T.

435Ω30pF

590 Ω

3.3V

D.U.T.

435Ω5pF*

590Ω

3.3V

BUSY

INT

NOTES:

1. Include jig and scope capacitances

Table 4. AC Test Condition

Inputs(1) Outputs

CE

______

R/W

____

OE

______

UB

______

LB

_____

SEM

_________

I/O8-15 I/O0-7

Mode

H X X X X H High-Z High-Z Deselected: Power-Down

X X X H H H High-Z High-Z Both Bytes Deselected

L L X L H H Data In High-Z Write to Upper Byte Only

L L X H L H High-Z Data In Write to Lower Byte Only

L L X L L H Data In Data In Write to Both Bytes

L H L L H H Data Out High-Z Read Upper Byte Only

L H L H L H High-Z Data Out Read Lower Byte Only

L H L L L H Data Out Data Out Read Both Bytes

X X H X X X High-Z High-Z Outputs Disabled

NOTES:

1. A0L-11L ≠ A0R-11R.

Table 5. Truth Table – Non-Contention Read/Write Control

Inputs(1) Outputs

CE

______

R/W

____

OE

______

UB

______

LB

_____

SEM

_________

I/O8-15 I/O0-7

Mode

H H L X X L Data Out Data Out Read Data in Semaphore Flag

X H L H H L Data Out Data Out Read Data in Semaphore Flag

H ↑ X X X L Data In Data In Write I/O0 into Semaphore Flag

X ↑ X H H L Data In Data In Write I/O0 into Semaphore Flag

L X X L X L - - Not Allowed

L X X X L L - - Not Allowed

NOTES:

1. There are 8 semaphore flags written to I/O0 and read from all I/Os (I/00-15). These 8 semaphore flags are addressed A0-2.

Table 6. Truth Table – Semaphore Read/Write Control

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Left Port Right Port

UB

______

/

LB

_____

R/W

____

CE

______

OE

______

A11-0 INT

_______

UB

______

/

LB

_____

R/W

____

CE

______

OE

______

A11-0 INT

_______

Mode

X L L X FFF X X X X X X L(2) Set Right INT

_______

Flag

X X X X X X X X L L FFF H(2) Reset Right INT

_______

Flag

X X X X X L(2) X L L X FFE X Set Left INT

_______

Flag

X X L L FFE H(2) X X X X X X Reset Left INT

_______

Flag

NOTES:

1. Assuming BUSY

__________

= VIH.

2. If BUSY

__________

= VIL, then no change.

3. IN T

_______

must be initialized at power-up.

Table 7. Truth Table – Interrupt Flag

Inputs Outputs

CE

______

L CE

______

R A11-0 BUSY

__________

L(1) BUSY

__________

R(1)

Function

X X No Match H H Normal

H X Match H H Normal

X H Match H H Normal

L L Match (2) (2) Write Inhibit(3)

NOTES:

1. When part is configured as master, BUSY

__________

L and BUSY

__________

R are both outputs. When configured as slave, both are inputs and internally inhibits writes. BUSY

__________

outputs are push-

pull, not open drain.

2. If inputs to opposite port were stable prior to address and enable inputs of this port, then “L.” If inputs to the opposite port became stable after the address the enable inputs of

port, then “H.” If tAPS is not met, then either BUSY

__________

L or BUSY

__________

R = LOW. BUSY

__________

L and BUSY

__________

R cannot be LOW simultaneously

3. Writes to one port are internally ignored when its BUSY

__________

outputs are LOW regardless of actual logic level on the pin.

Table 8. Truth Table – Address BUSY

__________

Arbitration

Functions Left D0-15 Right D0-15 Status

No Action 1 1 Semaphore free

Left port writes “0” to semaphore 0 1 Left port has semaphore token

Right port writes “0” to semaphore 0 1 No change. Right port has no write access to semaphore

Left port writes “1” to semaphore 1 0 Right port obtains semaphore token

Left port writes “0” to semaphore 1 0 No change. Left port has no write access to semaphore

Right port writes “1” to semaphore 0 1 Left port obtains semaphore token

Left port writes “1” to semaphore 1 1 Semaphore free

Right port writes “0” to semaphore 1 0 Right port has semaphore token

Right port writes “1” to semaphore 1 1 Semaphore free

Left port writes “0” to semaphore 0 1 Left port has semaphore token

Left port writes “1” to semaphore 1 1 Semaphore free

NOTES:

1. Table shows sequence of events for one of the eight semaphores.

2. There are eight semaphore flags (A0-2) written via I/O0 and read from I/O0-15.

3. CE

_____

= VIH, SEM

________

= VIL to access semaphores.

4. Refer to Table 6.

Table 9. Truth Table – Semaphore Procurement Sequence Example

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Timing Diagrams

ADDR

tRC

tACE (4)

CE

tAA

Valid Data(4)

R/W

Data Out

BUSYOut

tLZ (1)

tBDD (3,4)

tHZ (2)

tOH

OE

tAOE(4)

UB, LB

tABE(4)

NOTES:

1. tLZ timing is based on which signal is asserted last, C E

______

or OE

______

.

2. tHZ timing is based on which signal is de-asserted first, C E

______

or OE

______

.

3. tBDD is needed only where the opposite port is completing a write operation to the same address. BUSY

_________

has no effect on valid output data.

4. Valid data starts from the last of tAOE, tACE, tAA or tBDD.

Diagram 1. Read Cycles

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ADDR

OE

tWC

tHZ (7)

R/W

Data Out

Data In

(4)

tAS (6) tWP (2) tWR (3)

tWZ tOW

tDW tDH

tAW

CE

UB, LB

Diagram 2. Write Cycle No. 1, R/W

____

Controlled Timing

ADDR

tWC

R/W

Data In

tDW tDH

tEW(2)

tAS(6)

tRW(3)

CE, SEM

tAW

UB, LB

Diagram 3. Write Cycle No. 2, CE

_____

Controlled Timing

NOTES:

1. R/W

____

or C E

______

must be HIGH during all address transitions.

2. A write occurs when C E

______

= VIL and R/W

____

= VIL for memory write cycle.

3. tWR timing is from the earlier of C E

______

or R/W

____

going HIGH to the end of write cycle.

4. The I/O pins are in the output state and input signals must not be applied during DATA out period.

5. For C E

______

=VIL transition simultaneously with or after the R/W

____

= VIL transition, the outputs remain in the high-impedance state.

6. tAS timing is based on latter of C E

______

or R/W

____

.

7. tHZ transition is measured 0mV from steady state with the Output Test Load.

8. For OE

_____

=VIL during R/W

____

write cycle, the write pulse width is the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required

tDW. If OE

_____

= VIH during an R/W

____

controlled writing cycle, the write pulse is specified as tWP.

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A0-A2

SEM

I/O0

R/W

OE

Valid Address Valid Address

tSAA

tACEtWRtAW

tEW

tSOP

tOH

Data Out Valid (2)

Data In Valid

tDW

tDHtWPtAS

tSWRD tAOE

Write Cycle Read Cycle

NOTES:

1. CE

_____

= VIH or UB

______

and L B

______

= VIH for the duration of the above timing (both write and read cycle).

2. “DATA OUT VALID” represents all I/O’s (I/O0-15) equal to the semaphore value

Diagram 4. Semaphore Read after Write Timing, Either Side

SIDE B

A0A-A 2A

R/WA

SEMA

A0B-A2B

R/WB

SEMB

Match

tSPS

SIDE A

NOTES:

1. DOR = DOL = VIL, CE

_____

L = CE

_____

R =VIH.

2. Timing for both ports is the same. Port B is opposite of port A.

3. This parameter is measured from R/W

____

A or SEM

________

A =VIH to R/W

____

B or SEM

________

B= VIH.

4. The semaphore will be sent to either side if tSPS is not met. It cannot be guaranteed which side receives semaphore.

Diagram 5. Semaphore Write Contention

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Match

Valid

BUSYB

R/WA

Data InA

ADDR B

Data OutBValid

ADDRA

tWP

tWC

tDW tDH

tBAA tBDA

tWDD

tBDD

tAPS(1 )

tDDD(3)

Match

NOTES:

1. tAPS is ignored for SLAVE part (M/S

___

= VIL)

2. CE

_____

L =CE

_____

R = VIH.

3. OE

_____

= VIL for the reading port.

4. For SLAVE mode (M/S

___

= VIL), BUSY

___________

is an input.

5. Timing for both ports is the same. Port B is opposite of port A.

Diagram 6. Write with Port-to-Port Read and BUSY

___________

(M/S

__

= VIH)

R/WA

BUSYB

R/WB

tWP

(2)

tWB

(3)

tWH

(1)

NOTES:

1. SLAVE (BUSY

___________

input) and MASTER (BUSY

___________

output) must meet tWH.

2. BUSY

___________

is sent to port B blocking R/W

____

B till BUSY

___________

B=VIH.

3. tWB is for SLAVE mode.

Diagram 7. Write with BUSY

___________

(M/S

__

= VIL)

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ADDRA

and

ADDRB

Addresses Match

CE A

CE B

BUSYB

tAPS

tBAC tBDC

Diagram 8. BUSY

___________

Arbitration Controlled by CE

_____

Timing (M/S

__

= VIH)

ADDRA

BUSYB

ADDRB

Addresses N

M atching Addre ss e s N

tBDAtBAA

tAPS (1)

NOTES:

1. If tAPS is not satisfied, the BUSY

___________

signal will be asserted randomly on one side or the other.

Diagram 9. BUSY

___________

Arbitration Controlled by Address Match Timing (M/S

__

= VIH)

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ADDR A

CE A

R/W A

INT B

Interrupt Set Addre ss (2)

tWC

tWR

(4 )

tAS (3 )

tINS (3 )

Inte rrupt Cle ar Addre ss (2)

ADDR B

CE B

OE B

INT B

tRC

tAS (3)

tINR (3 )

NOTES:

1. Port A and B can be either left or right port. If Port A is left port, Port B is right port. If Port A is right port, Port B is left port.

2. Refer to Table 7.

3. Timing depends on which enable signal (C E

______

or R/W

____

) is asserted last.

4. Timing depends on which enable signal (C E

______

or R/W

____

) is de-asserted last.

Diagram 10. Interrupt Timing

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Functional Description

HDV24 supports two memory ports with independent control, address, and I/O pins that enable simultaneous, asynchronous

access to any location in memory.

Interrupts

A special memory location is associated with each port when the interrupt function is used. These special memory

locations are best considered as mailboxes between the two ports and the corresponding interrupt signals as the flags of the

mailboxes. When the right port writes a data word to the special location FFE (HEX), the left port interrupt flag (INT

_______

L) becomes

active or LOW (a data write is defined as CE

_____

R = R/W

____

R = VIL). The left port can clear IN T

_______

L (HIGH) through either read or write

access of the same memory location FFE (a data access is defined as CE

_____

L = OE

_____

L = VIL, and the value of R/W

____

is irrelevant in the

case). Similarly, when the left port writes to the memory location FFF (HEX), the right port interrupt flag (INT

_______

R) becomes

asserted (LOW). The right port must access the memory location FFF in order to clear INT

_______

R (HIGH). The exact value of the data

word at address FFE or FFF is user defined, and is irrelevant as far as the interrupt logic is concerned. If the user chooses not to

use the interrupt function, the two special memory locations (FFE and FFF) are treated as part of the regular dual-port memory,

and the interrupt flags can simply be ignored.

Busy Logic

When both ports attempt to access the same memory location at the same time, data corruption can potentially occur. In

the single-device or MASTER configuration (i.e. when the M/ S

___

pin is tied HIGH), the on-chip Busy Logic arbitrates

simultaneous accesses to the same memory location, and determines the “winner” between the two ports. If Busy Logic considers

the right port lost in the arbitration, then the right port B U SY

__________

pin is set active (LOW) to signal the system that this memory

location is “busy” being accessed by the other port. Furthermore, the Busy Logic prevents the right port from writing to the same

memory location for as long as the right port BUSY

__________

signal stays active (LOW). Once the left port finishes access to this memory

location, the dual-port SRAM signals the system by setting the right port B U S Y

__________

pin back to inactive (HIGH), so that the system

can resume its normal access from the right port. Note that only the write operation from the losing port is inhibited; the read

operation is nondestructive and can thus continue regardless of the arbitration result.

The BUSY

__________

pins are output pins in the single-device or MASTER mode, but become input pins instead when the

device is configured in SLAVE mode (this is accomplished by tying M/ S

___

pin LOW). In SLAVE mode the on-chip arbitration

logic is disabled, and the device relies on the input BUSY

__________

signals for the results of arbitration when simultaneous access to the

same memory location occurs. Specifically, when a B U SY

__________

pin is set to HIGH, normal operation can be performed from this port,

but when a B U S Y

___________

pin is set to LOW, write operations will be inhibited from this port. If width expansion with multiple HBA

HDV24 devices is used, it is recommended that only one of them be configured in MASTER mode, and the rest of them in

SLAVE mode. The BUSY

__________

(output) signal from the master device should be connected to the respective BUSY

__________

(input) pins of

the slave devices. This means that only one device (the master) is performing the Busy Logic arbitration, and all the other devices

(the slaves) will follow this arbitration accordingly. This can prevent the conflicts caused by the potential inconsistent arbitration

results from different dual-port SRAM devices. Note that if the user does not wish the write operation to be inhibited by the Busy

Logic, the user can disable this feature by configuring the device in SLAVE mode and tying the B U S Y

__________

input pins to HIGH.

The Busy arbitration logic is triggered whenever the two ports simultaneously attempt to access the same memory

location, where data accesses are determined by the timings and values of the Address and Chip Enable signals only, not by the

value of the R/ W

____

signal. This means that both read and write operations can trigger the Busy Logic, even though only the write

operation is inhibited from the losing port. Note that in a master/slave configuration, an additional timing constraint concerning

the R/ W

____

signal needs to be met in order to prevent data corruption in the slave device: the write operation in the slave device

cannot start before the BUSY

__________

signal – which originates from the output BU S Y

__________

pin – is received by the slave device to ensure

write inhibition. In other words, the R/ W

____

signal needs to stay high from the time the Busy Logic on the master device is

triggered (through the changing of the Address and Chip Enable signals) till the B U S Y

__________

signal is received by the slave device.

Semaphores

A semaphore can be considered as a special one-bit dual-port memory cell that can be “owned” by (or granted to) only

one port at any given time. Typically a semaphore is used as an arbiter for the exclusive ownership (or access privilege) of any

shared resource in a system. A semaphore ownership can be requested by writing a zero “0” to the semaphore; a semaphore

ownership can be relinquished by writing a one “1” to the semaphore; and a semaphore ownership can be tested by reading from

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the semaphore – a readout of zero “0” means that the semaphore is owned by this port, while a readout of one “1” means that

either the semaphore is owned by the other port, or there is no owner at all. A token-passing system can be used to conceptualize

the semaphore mechanism: requesting for the semaphore ownership is equivalent to requesting for the token, and relinquishing

the semaphore ownership is equivalent to releasing the token. HBA HDV24 device provides eight addressable semaphores in

addition to the regular 4K x 16 dual-port memory space.

A typical sequence of accessing a semaphore is as follows: first a port attempts to request for the token by writing a

zero “0” to the semaphore. The result of the request is then tested by reading from the semaphore: if the readout is zero “0”, then

the token request has succeeded; but if the readout is one “1”, then the token request has failed. The requester should then try to

repeatedly read from the semaphore until the readout becomes zero “0”, upon which time the requester becomes the new

possessor of the token, and can be granted exclusive access privilege to the shared resource the semaphore represents. In the case

when both ports request for the token at the same time, the semaphore logic ensures that only one port is granted the token. In

other words, at most one of the two semaphore readout ports can assume the value of zero “0”. When the token is not owned by

any port, the semaphore will appear to contain the value one “1” to both ports. Note that a failed token request becomes an

outstanding token request, and will remain valid until either the other port releases the token (which means the requester now

becomes the new possessor of the token), or when the outstanding request is withdrawn by writing a one “1” to the semaphore

before the other port releases the token.

Semaphore accesses are distinguished from the regular memory access through the use of the semaphore select (S E M

________

)

signal: S E M

________

should remain HIGH when the regular dual-port memory is being accessed, but should be tied LOW when

semaphores are being accessed. Other control signals such as C E

_____

, and R/ W

____

behave identically in both cases. Address pins A0 to

A2 are used to address the eight semaphore flags (the values of the other address pins are irrelevant to semaphores). Only data

pin D0 is used when writing to a semaphore. However, when reading from a semaphore, the one-bit semaphore value will be

duplicated on all data pins (D0-D15). Note that the semaphore logic is not automatically initialized during power up. The system

has to handle the initialization of the semaphores during power up by writing ones from both sides to all semaphores to ensure

their availabilities for future use.

As discussed previously, semaphores are typically used to resolve contentions of shared resources in a system. These

shared resources can be a common data bus, a bi-directional shared buffer, or even a segment of the dual-port SRAM on an HBA

HDV24 device. Before any component in the system attempts to gain exclusive access to a shared resource, the semaphore can be

used to ensure that no resource contention or data corruption will occur. One advantage in using hardware-supported semaphores

is performance improvement by eliminating the processor wait states. HBA HDV24 semaphores also provide system designers

with higher flexibility because the resource sharing can be managed much more easily. With proper system software support,

semaphores can even replace the Busy arbitration logic in certain cases, albeit with a coarser data granularity.

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Order Information:

*

Speed – Slower speeds available upon request.

**Package – 100 pin Plastic Thin Quad Flat Pack (TQFP), 84 pin Plastic Lead Chip Carrier (PLCC)

†Temperature – Industrial only offered in 25ns

Example:

HDV24L15PF (4K x 16, 15ns, Commercial temp)

USA Taiwan Europe

2107 North First

Street, Suite 415

San Jose, CA 95131,

USA

Tel: 408.453.8885

Fax: 408.453.8886

www.hba.com

No. 81, Suite 8F-9,

Shui-Lee Rd.

Hsinchu, Taiwan,

R.O.C.

Tel: 886.3.516.9118

Fax: 886.3.516.9181

www.hba.com

CDE Technology B.V.

Nijverheidslaan 28

1382 L J Weesp, The

Netherlands

Tel: 31.294.280.914

Fax: 31.294.280.919

www.hba.com

HBA

Device Family

Device Type

Power

Speed (ns)*

Package**

Temperature Range

XX XXX X XX XX X

HD V24 (4K x 16) Low 15 PF Blank – Commercial (0°C to 70°C)

25 J I – Industrial (-40° to 85°C) †

35