© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications are subject to
change without notice.
HD
24
PRELIM
NARY
DP II
SRAM
3HD166A
Page 16 of 18
Functional Description
HDV24 supports two memory ports with independent control, address, and I/O pins that enable simultaneous, asynchronous
access to any location in memory.
Interrupts
A special memory location is associated with each port when the interrupt function is used. These special memory
locations are best considered as mailboxes between the two ports and the corresponding interrupt signals as the flags of the
mailboxes. When the right port writes a data word to the special location FFE (HEX), the left port interrupt flag (INT
_______
L) becomes
active or LOW (a data write is defined as CE
_____
R = R/W
____
R = VIL). The left port can clear IN T
_______
L (HIGH) through either read or write
access of the same memory location FFE (a data access is defined as CE
_____
L = OE
_____
L = VIL, and the value of R/W
____
is irrelevant in the
case). Similarly, when the left port writes to the memory location FFF (HEX), the right port interrupt flag (INT
_______
R) becomes
asserted (LOW). The right port must access the memory location FFF in order to clear INT
_______
R (HIGH). The exact value of the data
word at address FFE or FFF is user defined, and is irrelevant as far as the interrupt logic is concerned. If the user chooses not to
use the interrupt function, the two special memory locations (FFE and FFF) are treated as part of the regular dual-port memory,
and the interrupt flags can simply be ignored.
Busy Logic
When both ports attempt to access the same memory location at the same time, data corruption can potentially occur. In
the single-device or MASTER configuration (i.e. when the M/ S
___
pin is tied HIGH), the on-chip Busy Logic arbitrates
simultaneous accesses to the same memory location, and determines the “winner” between the two ports. If Busy Logic considers
the right port lost in the arbitration, then the right port B U SY
__________
pin is set active (LOW) to signal the system that this memory
location is “busy” being accessed by the other port. Furthermore, the Busy Logic prevents the right port from writing to the same
memory location for as long as the right port BUSY
__________
signal stays active (LOW). Once the left port finishes access to this memory
location, the dual-port SRAM signals the system by setting the right port B U S Y
__________
pin back to inactive (HIGH), so that the system
can resume its normal access from the right port. Note that only the write operation from the losing port is inhibited; the read
operation is nondestructive and can thus continue regardless of the arbitration result.
The BUSY
__________
pins are output pins in the single-device or MASTER mode, but become input pins instead when the
device is configured in SLAVE mode (this is accomplished by tying M/ S
___
pin LOW). In SLAVE mode the on-chip arbitration
logic is disabled, and the device relies on the input BUSY
__________
signals for the results of arbitration when simultaneous access to the
same memory location occurs. Specifically, when a B U SY
__________
pin is set to HIGH, normal operation can be performed from this port,
but when a B U S Y
___________
pin is set to LOW, write operations will be inhibited from this port. If width expansion with multiple HBA
HDV24 devices is used, it is recommended that only one of them be configured in MASTER mode, and the rest of them in
SLAVE mode. The BUSY
__________
(output) signal from the master device should be connected to the respective BUSY
__________
(input) pins of
the slave devices. This means that only one device (the master) is performing the Busy Logic arbitration, and all the other devices
(the slaves) will follow this arbitration accordingly. This can prevent the conflicts caused by the potential inconsistent arbitration
results from different dual-port SRAM devices. Note that if the user does not wish the write operation to be inhibited by the Busy
Logic, the user can disable this feature by configuring the device in SLAVE mode and tying the B U S Y
__________
input pins to HIGH.
The Busy arbitration logic is triggered whenever the two ports simultaneously attempt to access the same memory
location, where data accesses are determined by the timings and values of the Address and Chip Enable signals only, not by the
value of the R/ W
____
signal. This means that both read and write operations can trigger the Busy Logic, even though only the write
operation is inhibited from the losing port. Note that in a master/slave configuration, an additional timing constraint concerning
the R/ W
____
signal needs to be met in order to prevent data corruption in the slave device: the write operation in the slave device
cannot start before the BUSY
__________
signal – which originates from the output BU S Y
__________
pin – is received by the slave device to ensure
write inhibition. In other words, the R/ W
____
signal needs to stay high from the time the Busy Logic on the master device is
triggered (through the changing of the Address and Chip Enable signals) till the B U S Y
__________
signal is received by the slave device.
Semaphores
A semaphore can be considered as a special one-bit dual-port memory cell that can be “owned” by (or granted to) only
one port at any given time. Typically a semaphore is used as an arbiter for the exclusive ownership (or access privilege) of any
shared resource in a system. A semaphore ownership can be requested by writing a zero “0” to the semaphore; a semaphore
ownership can be relinquished by writing a one “1” to the semaphore; and a semaphore ownership can be tested by reading from