Vishay Siliconix
DG401/403/405
Document Number: 70049
S-61921–Rev. G, 16-Oct-06
www.vishay.com
1
Low-Power, High-Speed CMOS Analog Switches
FEATURES
• 44 V Supply Max Rating
• ± 15 V Analog Signal Range
• On-Resistance - rDS(on): 30 Ω
• Low Leakage - ID(on): 40 pA
• Fast Switching - tON: 75 ns
• Ultra Low Power
Requirements - PD: 0.35 µW
• TTL, CMOS Compatible
• Single Supply Capability
BENEFITS
• Wide Dynamic Range
• Break-Before-Make Switching Action
• Simple Interfacing
APPLICATIONS
• Audio and Video Switching
• Sample-and-Hold Circuits
• Battery Operation
• Test Equipment
• Communications Systems
• PBX, PABX
DESCRIPTION
The DG401/403/405 monolithic analog switches were
designed to provide precision, high performance switching of
analog signals. Combining low power (0.35 µW, typ) with
high speed (tON: 75 ns, typ), the DG401 series is ideally
suited for portable and battery powered industrial and mili-
tary applications.
Built on the Vishay Siliconix proprietary high-voltage silicon-
gate process to achieve high voltage rating and superior
switch on/off performance, break-before-make is guaran-
teed for the SPDT configurations. An epitaxial layer prevents
latchup.
Each switch conducts equally well in both directions when
on, and blocks up to 30 V peak-to-peak when off. On-resis-
tance is very flat over the full ± 15 V analog range, rivaling
JFET performance without the inherent dynamic range limi-
tations.
The three devices in this series are differentiated by the type
of switch action as shown in the functional block diagrams.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Two SPST Switches per Package
Logic "0" ≤ 0.8 V
Logic "1" ≥ 2.4 V
DG401
NC GND
NC VL
NC V+
NC IN2
D2S2
D1S1
NC
Dual-In-Line and SOIC
IN1
NC V–
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
NC
NC
V–
S2
NC
IN2
GND
NC
NC
D2
NC
NC
NC
S1
VL
IN1
NC
NC
V+
D1
Key
Top View
LCC
910111213
4
5
6
7
8
1231920
14
15
16
17
18
DG401
TRUTH TABLE
Logic Switch
0 OFF
1ON
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2
Document Number: 70049
S-61921–Rev. G, 16-Oct-06
Vishay Siliconix
DG401/403/405
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Two SPDT Switches per Package
Logic "0" ≤ 0.8 V
Logic "1" ≥ 2.4 V
Two DPST Switches per Package
Logic "0" ≤ 0.8 V
Logic "1" ≥ 2.4 V
DG403
D1S1
NC
Dual-In-Line and SOIC
IN1
D3V–
S3GND
S4VL
D4V+
NC IN2
D2S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
D3
NC
V–
S2
S3
IN2
GND
NC
NC
D2
NC
NC
S4
S1
VL
IN1
D4
NC
V+
D1
Key
Top View
LCC
910111213
4
5
6
7
8
1231920
14
15
16
17
18
DG403
TRUTH TABLE
Logic SW1, SW2SW3, SW4
0 OFF ON
1ONOFF
DG405
D1S1
NC
Dual-In-Line and SOIC
IN1
D3V–
S3GND
S4VL
D4V+
NC IN2
D2S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
D3
NC
V–
S2
S3
IN2
GND
NC
NC
D2
NC
NC
S4
S1
VL
IN1
D4
NC
V+
D1
Key
Top View
LCC
910111213
4
5
6
7
8
1231920
14
15
16
17
18
DG405
TRUTH TABLE
Logic Switch
0 OFF
1ON
Document Number: 70049
S-61921–Rev. G, 16-Oct-06
www.vishay.com
3
Vishay Siliconix
DG401/403/405
Notes:
a. Signals on SX, DX, or INX exceeding V+ or V– will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC Board.
c. Derate 6 mW/°C above 75 °C.
d. Derate 7.6 mW/°C above 75 °C.
ORDERING INFORMATION
Temp Range Package Part Number
DG401
- 40 to 85 °C 16-Pin Plastic DIP DG401DJ
DG401DJ-E3
DG403
- 40 to 85 °C
16-Pin Plastic DIP DG403DJ
DG403DJ-E3
16-Pin Narrow SOIC
DG403DY
DG403DY-E3
DG403DY-T1
DG403DY-T1-E3
DG405
- 40 to 85 °C
16-Pin Plastic DIP DG405DJ
DG405DJ-E3
16-Pin Narrow SOIC
DG405DY
DG405DY-E3
DG405DY-T1
DG405DY-T1-E3
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol Limit Unit
V+ to V- 44
V
GND to V- 25
VL(GND - 0.3 V) to (V+) + 0.3 V
Digital Inputsa, VS, VD
(V-) - 2 V to (V+) + 2 V
or
30 mA, whichever occurs first
Current (Any Terminal) Continuous 30 mA
Current, S or D (Pulsed 1 ms, 10 % duty) 100
Storage Temperature (DJ, DY Suffix) - 65 to 125 °C
Power Dissipation (Package)b 16-Pin Plastic DIPc450
mW
16-Pin SOICd600
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Document Number: 70049
S-61921–Rev. G, 16-Oct-06
Vishay Siliconix
DG401/403/405
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONSa
Parameter
Symbol
Test Conditions
Unless Specified
V+ = 15 V, V– = - 15 V
VL = 5 V, VIN = 2.4 V, 0.8 VfTempb Typc
D Suffix
- 40 to 85 °C
Unit Mind Maxd
Analog Switch
Analog Signal RangeeVANALOG Full - 15 15 V
Drain-Source
On-Resistance rDS(on)
IS = - 10 mA, VD = ± 10 V
V+ = 13.5 V, V- = - 13.5 V
Room
Full 30 45
55 Ω
Δ Drain-Source
On-Resistance ΔrDS(on)
IS = - 10 mA, VD = ± 5 V, 0 V
V+ = 16.5 V, V- = - 16.5 V
Room
Full 33
5
Switch Off Leakage Current
IS(off) V+ = 16.5 V, V- = - 16.5 V
VD = ± 15.5 V, VS = ± 15.5 V
Room
Hot - 0.01 - 0.5
- 5
0.5
5
nA
ID(off) Room
Hot - 0.01 - 0.5
- 5
0.5
5
Channel On Leakage Current ID(on)
V+ = 16.5 V, V- = - 16.5 V
VS = VD = ± 15.5 V
Room
Hot - 0.04 - 1
- 10
1
10
Digital Control
Input Current VIN Low IIL
VIN under test = 0.8 V
All Other = 2.4 V Full 0.005 - 1 1
µA
Input Current VIN High IIH
VIN under test = 2.4 V
All Other = 0.8 V Full 0.005 - 1 1
Dynamic Characteristics
Tur n - O n T i m e tON RL = 300 Ω, CL = 35 pF
See Figure 2
Room 75 150
ns
Tur n - O f f T i m e tOFF Room 30 100
Break-Before-Make
Time Delay (DG403) tDRL = 300 Ω, CL = 35 pF Room 35 5
Charge Injection Q CL = 10 nF
Vgen = 0 V, Rgen = 0 ΩRoom 60 pC
Off Isolation Reject Ratio OIRR RL = 100 Ω, CL = 5 pF
f = 1 MHz
Room 72 dB
Channel-to-Channel Crosstalk XTA L K Room 90
Source Off Capacitance CS(off)
f = 1 MHz, VS = 0 V
Room 12
pFDrain Off Capacitance CD(off) Room 12
Channel On Capacitance CD, CS(on) Room 39
Power Supplies
Positive Supply Current I+
V+ = 16.5 V, V- = - 16.5 V
VIN = 0 or 5 V
Room
Full
0.01 1
5
µA
Negative Supply Current I- Room
Full
- 0.01 - 1
- 5
Logic Supply Current ILRoom
Full
0.01 1
5
Ground Current IGND Room
Full
- 0.01 - 1
- 5
Document Number: 70049
S-61921–Rev. G, 16-Oct-06
www.vishay.com
5
Vishay Siliconix
DG401/403/405
TYPICAL CHARACTERISTICS 25 °C, unless noted
Input Switching Threshold vs. Logic Supply Voltage
rDS(on) vs. VD and Temperature
rDS(on) vs. VD and Power Supply Voltage (V– = 0 V)
(V)
T
V
VL – Logic Supply (V)
0
1
2
3
4
5
6
7
0 2 4 6 8 1012141618
SW1,
2
SW3, 4
V+ = 15 V
V- = -15 V
VD – Drain V oltage (V)
rDS(on) – Drain-Source On-Resistance ( )Ω
0
5
10
15
20
25
30
35
40
45
50
-15.0 -10.0 -5.0 0.0 5.0 10.0 15.0
V+ = 15 V, V- = -15 V
VL = 5 V
85 °C
25 °C
0 °C
- 40 °C
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25
VD – Drain Voltage (V)
TA = 25 °C
7.5 V
10 V
12 V
15 V
20 V
22 V
rDS(on) – Drain-Source On-Resistance (Ω)
Input Switching Threshold vs. Supply Voltages
rDS(on) vs. VD and Power Supply Voltage
Charge Injection vs. Analog Voltage
(V)
TH
V
0
0.5
1
1.5
2
2.5
3
3.5
5101520253035
VL = 7 V
VL = 5 V
(V+)
- 25 - 15 26- 5 5 15
V
D
– Drain V oltage (V)
TA = 25 °C
±6 V
±10 V
±12 V
± 15 V
±20 V
±22 V
10
30
20
40
50
60
rDS(on) – Drain-Source On-Resistance (Ω)
Q (pC)
VS
– Source V oltage (V )
- 30
- 20
- 10
0
10
20
30
40
50
- 15 - 10 - 5 0 5 10 15
100 pF
CL = 10 nF
1 nF
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Document Number: 70049
S-61921–Rev. G, 16-Oct-06
Vishay Siliconix
DG401/403/405
TYPICAL CHARACTERISTICS 25 °C, unless noted
*Refer to Figure 2 for test conditions.
Leakage Current vs. Temperature
Supply Current vs. Temperature
Switching Time vs. Power Supply Voltage*
Temperature (°C)
I D (off)
1p
10p
100p
1000p
- 40 - 20 0 20 40 60 80
Is (off)
Id (off)
Id (on)
V+ = 15 V
V- = -15 V
VL = 5 V
VD = ± 14 V
I+, I-, IL (A)
TA – Temperature (°C)
1 pA
10 pA
100 pA
1 nA
100 nA
- 40 - 20 0 20 40 60 80 100
I+
I-
IL
V+ = 15 V
V- = - 15 V
VL = 5 V
V+, V– Positive and Negative Supplies (V)
t
ON (ns) , t
OFF
0
20
40
60
80
100
120
140
160
180
0 ± 5 ± 10 ± 15 ± 20 ± 25
VS = 5 V
VS = 5 V
VS = - 5 V
tON
tOFF
VS = - 5 V
Leakage Current vs. Analog Voltage
Switching Time vs. Temperature*
Switching Time vs. Positive Supply Voltage*
(pA) I , I
SD
V
D
or V
S
– Drain or Source V oltage (V)
- 100
- 80
- 60
- 40
- 20
0
20
40
- 15.0 - 10.0 - 5.0 0.0 5.0 10.0 15.0
Is (off)
Id (off)
Id (on)
tON (ns) , t
OFF
TA – Temperature (°C)
0
20
40
60
80
100
120
- 40 - 20 0 20 40 60 80 100
V+ = 15 V
V- = - 15 V
VL = 5 V tON
tOFF
VS = -10 V
VS = 10 V
VS = - 10 V
VS = 10 V
tON (ns) , t OFF
V+ – Positive Supply (V)
0
30
60
90
120
150
180
210
240
270
300
0 5 10 15 20 25
VS = 5 V
tON
tOFF
0 V
0 V
- 5 V
- 5 V
- 15 V
- 15 V
Document Number: 70049
S-61921–Rev. G, 16-Oct-06
www.vishay.com
7
Vishay Siliconix
DG401/403/405
TYPICAL CHARACTERISTICS 25 °C, unless noted
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
Supply Current vs. Switching Frequency
Frequency (Hz)
Supply Current (A)
100 mA
10 mA
1 mA
100 μA
10 μA
1 μA
100 nA
10 nA
10 100 1K 10K 100K 1M 10M
Figure 1.
Level
Shift/
Drive
VIN
VL
S
V+
GND
V–
D
V–
V+
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Document Number: 70049
S-61921–Rev. G, 16-Oct-06
Vishay Siliconix
DG401/403/405
TEST CIRCUITS
VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trail-
ing edge of the output waveform.
Figure 2. Switching Time
0 V
Logic
Input
Switch
Input*
Switch
Output
0 V
Switch
Input*
VS
tf < 20 ns
tf
< 20 ns
90 %
-V S
tOFF
tON
VO
90 %
VO
*V
S = 10 V for tON, VS = - 10 V for tOFF
Note: Logic input waveform is inverted for switches that
have the opposite logic sense control
CL (includes fixture and stray capacitance)
V+
IN
RL
RL + rDS(on)
VO = VS
S D
- 15 V
VO
GND
± 10 V
VL
CL
35 pF
V-
RL
1 kΩ
+ 15 V+ 5 V 50 %
Figure 3. Break-Before-Make
0 V
Logic
Input
Switch
Switch
Output
3 V
50 %
0 V
Output
0 V
90 %
VO2
VO1
90 %
VS1
VS2
tDtD
VO2
CL (includes fixture and stray capacitance)
V+
RL1
S2
CL1
V-
S1
VL
VS2
IN
D2
VS1
R
L2
L2
D1VO1
CL2
- 15 V
GND
+ 5 V + 15 V
Figure 4. Charge Injection
Off OnOn
IN
ΔVO
VO
Q = ΔVO x CL
CL
10 nF
D
Rg
VO
V+
S
V-
3 V
IN
VL
Vg
- 15 V
GND
+ 15 V+ 5 V
Document Number: 70049
S-61921–Rev. G, 16-Oct-06
www.vishay.com
9
Vishay Siliconix
DG401/403/405
TEST CIRCUITS
Figure 5. Off Isolation
Figure 6. Insertion Loss
RL
100 Ω
D
0 V, 2.4 V
V+
Rg = 50 Ω
- 15 V
GND V- C
VS
Off Isolation = 20 log VS
VO
IN
VLVO
+ 5 V
C
+ 15 V
S
C
C = RF bypass
RL
100 Ω
S
VSVO
0 V, 2.4 V IN
VL
D
Rg = 50 Ω
+ 5 V
- 15 V
GND V- C
C
+ 15 V
V+
C
C = RF bypass
Figure 7. Crosstalk
Figure 8. Capacitances
Rg = 50 Ω
IN
0.8 V
VLV+
V-
XTALK Isolation = 20 log VS
VO
GND
S2
VS
VO
S1
RL
D
C = RF bypass
50 Ω
+ 15 V
- 15 V
C
C+ 5 V C
D
f = 1 MHz
IN
S
VLV+
- 15 V
GND V- C
0 V, 2.4 V
Meter
HP4192A
Impedance
Analyzer
or Equivalent
+ 5 V
C
+ 15 V
C
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Document Number: 70049
S-61921–Rev. G, 16-Oct-06
Vishay Siliconix
DG401/403/405
APPLICATIONS
Dual Slope Integrators:
The DG403 is well suited to configure a selectable slope inte-
grator. One control signal selects the timing capacitor C1 or
C2. Another one selects ein or discharges the capacitor in
preparation for the next integration cycle.
Band-Pass Switched Capacitor Filter:
Single-pole double-throw switches are a common element
for switched capacitor networks and filters. The fast switch-
ing times and low leakage of the DG403 allow for higher
clock rates and consequently higher filter operating frequen-
cies.
Figure 9. Stereo Source Selector
DG403
Right
Right
Left
Left
Channel
Select
Source 1
Source 2
TTL
Left
Right
- 15 V
+ 15 V+ 5 V
GND V-
V+
S1
IN2
S3
S2
S4
D1
D3
D2
D4
VL
IN1
Figure 10. Dual Slope Integrator
DG403
Integrate/
Reset
Slope
Select
TTL
+
-
- 15 V
+ 15 V+ 5 V
GND V-
V+
S1
IN2
S3
S2
S4
D1
D3
D2
D4
VL
IN1
C1
C2
eout
ein
Figure 11. Band-Pass Switched Capacitor Filter
- 15 V
+ 15 V+ 5 V
GND V-
V+
Clock
+
-
VL
eout
ein
DG403
S1
IN2
S3
S2
S4
D1
D3
D2
D4
IN1
Document Number: 70049
S-61921–Rev. G, 16-Oct-06
www.vishay.com
11
Vishay Siliconix
DG401/403/405
APPLICATIONS
Peak Detector:
A3 acting as a comparator provides the logic drive for oper-
ating SW1. The output of A2 is fed back to A3 and compared
to the analog input ein. If ein > eout the output of A3 is high
keeping SW1 closed. This allows C1 to charge up to the ana-
log input voltage. When ein goes below eout A3 goes nega-
tive, turning SW1 off. The system will therefore store the most
positive analog input experienced.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech-
nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see http://www.vishay.com/ppg?70049.
Figure 12. Positive Peak Detector
A2
+
–eout
+
–
A3
+
–
A1
ein
Reset
SW1
SW2
DG401
R1
C1
Legal Disclaimer Notice
Vishay
Document Number: 91000 www.vishay.com
Revision: 08-Apr-05 1
Notice
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc.,
or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's
terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express
or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness
for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications.
Customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Vishay for any damages resulting from such improper use or sale.
