January 2007
HYS64D32301[G/H]U–5–B
HYS[64/72]D64xxx[G/H]U–[5/6]–B
HYS[64/72]D128xxx[G/H]U–[5/6]–B
184-Pin Unbuffered Double-Data-Rate Memory Modules
UDIMM
DDR SDRAM
Internet Data Sheet
Rev. 1.22
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Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
qag_techdoc_rev400 / 3.2 QAG / 2006-07-21 2
03292006-CXBY-V2JX
HYS64D32301[G/H]U–5–B, HYS[64/72]D64xxx[G/H]U–[5/6]–B, HYS[64/72]D128xxx[G/H]U–[5/6]–B
Revision History: 2007-01, Rev. 1.22
Page Subjects (major changes since last revision)
All Adapted internet edition
23 tDQSS min from 0.75ns to 0.72ns
tRFC min from 70ns to 65ns
Previous Revision: 2006-09, Rev. 1.21
All Qimonda update
Previous Revision: 1.2
4Added new product type
16 Added raw card C Diagram
18 Updated IDD values
20 Added SPD Code for new product type
Previous Revision: Rev. 1.1
Internet Data Sheet
Rev. 1.22, 2007-01 3
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
1Overview
This chapter contains features and the description.
1.1 Features
• 184-Pin Unbuffered Double-Data-Rate Memory Modules
(ECC and non-parity) for PC and Workstation main
memory applications
• One rank 32M ×64, 64M x 64, 64M ×72 and two ranks
128M ×64, 128M ×72 organization
• standard Double Data Rate Synchronous DRAMs Single
+2.5V (± 0.2V) power supply
• Built with 512-Mbit in P-TSOPII-66 package
• Programmable CAS Latency, Burst Length, and Wrap
Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_2 compatible
• Serial Presence Detect with E2PROM
• JEDEC standard MO-206 form factor:
133.35 mm ×31.75 mm ×4.00 mm max.
• Standard reference layout
• Gold plated contacts
• DDR400 speed grade supported
• Lead-free
TABLE 1
Performance for –5 and –6
1.2 Description
The Qimonda
HYS64D32301[G/H]U–5–B, HYS[64/72]D64xxx[G/H]U–
[5/6]–B and HYS[64/72]D128xxx[G/H]U–[5/6]–B
are industry standard
184-Pin Unbuffered Double-Data-Rate Memory Modules
(UDIMM)
organized as 32M × 64M (256 MB), 64M ×64 (512 MB),
128M ×64 (1 GB) for non-parity and 64M ×72 (512 MB),
128M ×72 (1 GB) for ECC main memory applications. The
memory array is designed with 512Mbit Double Data Rate
Synchronous DRAMs. A variety of decoupling capacitors are
mounted on the printed circuit board. The DIMMs feature
serial presence detect (SPD) based on a serial E2PROM
device using the 2-pin I2C protocol. The first 128 bytes are
programmed with configuration data and the second
128 bytes are available to the customer.
Part Number Speed Code –5 –6 Unit
Speed Grade Component DDR400B DDR333B —
Module PC3200 - 3033 PC2700 - 2533 —
Max. Clock Frequency @CL3 fCK3 200 166 MHz
@CL2.5 fCK2.5 166 166 MHz
@CL2 fCK2 133 133 MHz
Internet Data Sheet
Rev. 1.22, 2007-01 4
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 2
Ordering Information
Note: All part numbers end with a place code designating the silicon-die revision. Reference information available on request.
Example: HYS72D64300HU-6-B, indicating rev. B dies are used for SDRAM components. The Compliance Code is
printed on the module labels describing the speed sort (for example “PC2700”), the latencies and SPD code definition
(for example “20330” means CAS latency of 2.0 clocks, RCD (Row-Column-Delay) latency of 3 clocks, Row Precharge
latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.
Type Compliance Code Description SDRAM Technology
PC3200 (CL=3.0)
HYS64D64300GU–5–B PC3200U–30330–A0 one rank 512 MB DIMM 512 Mbit (×8)
HYS72D64300GU–5–B PC3200U–30330–A0 one rank 512 MB ECC-DIMM 512 Mbit (×8)
HYS64D128320GU–5–B PC3200U–30330–B0 two ranks 1 GB DIMM 512 Mbit (×8)
HYS72D128320GU–5–B PC3200U–30330–B0 two ranks 1 GB ECC-DIMM 512 Mbit (×8)
PC2700 (CL=2.5)
HYS64D64300GU–6–B PC2700U–25330–A0 one rank 512 MB DIMM 512 Mbit (×8)
HYS72D64300GU–6–B PC2700U–25330–A0 one rank 512 MB ECC-DIMM 512 Mbit (×8)
HYS64D128320GU–6–B PC2700U–25330–B0 two ranks 1 GB DIMM 512 Mbit (×8)
HYS72D128320GU–6–B PC2700U–25330–B0 two ranks 1 GB ECC-DIMM 512 Mbit (×8)
PC3200 (CL=3.0)
HYS64D32301HU–5–B PC3200U–30330–C0 one rank 256 MB DIMM 512 Mbit (×16)
HYS64D64300HU–5–B PC3200U–30330–A0 one rank 512 MB DIMM 512 Mbit (×8)
HYS72D64300HU–5–B PC3200U–30330–A0 one rank 512 MB ECC-DIMM 512 Mbit (×8)
HYS64D128320HU–5–B PC3200U–30330–B0 two ranks 1 GB DIMM 512 Mbit (×8)
HYS72D128320HU–5–B PC3200U–30330–B0 two ranks 1 GB ECC-DIMM 512 Mbit (×8)
PC2700 (CL=2.5)
HYS64D64300HU–6–B PC2700U–25330–A0 one rank 512 MB DIMM 512 Mbit (×8)
HYS72D64300HU–6–B PC2700U–25330–A0 one rank 512 MB ECC-DIMM 512 Mbit (×8)
HYS64D128320HU–6–B PC2700U–25330–B0 two ranks 1 GB DIMM 512 Mbit (×8)
HYS72D128320HU–6–B PC2700U–25330–B0 two ranks 1 GB ECC-DIMM 512 Mbit (×8)
Internet Data Sheet
Rev. 1.22, 2007-01 5
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
2 Pin Configuration
The pin configuration of the Unbuffered DDR SDRAM DIMM
is listed by function in Table 3 (184 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 4
and Table 5 respectively. The pin numbering is depicted in
Figure 1.
TABLE 3
Pin Configuration of UDIMM
Pin# Name Pin
Type
Buffer
Type
Function
Clock Signals
137 CK0 I SSTL Clock Signals 2:0
NC NC –
16 CK1 I SSTL
76 CK2 I SSTL
138 CK0 I SSTL Complement Clock Signals 2:0
NC NC –
17 CK1 I SSTL
75 CK2 I SSTL
21 CKE0 I SSTL Clock Enable Rank 0
111 CKE1 I SSTL Clock Enable Rank 1
Note: 2-rank module
NC NC – Note: 1-rank module
Control Signals
157 S0 I SSTL Chip Select Rank 0
158 S1 I SSTL Chip Select Rank 1
Note: 2-rank module
NC NC – Note: 1-rank module
154 RAS I SSTL Row Address Strobe
65 CAS I SSTL Column Address Strobe
63 WE I SSTL Write Enable
Internet Data Sheet
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03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Address Signals
59 BA0 I SSTL Bank Address Bus 2:0
52 BA1 I SSTL
48 A0 I SSTL Address Bus 11:0
43 A1 I SSTL
41 A2 I SSTL
130 A3 I SSTL
37 A4 I SSTL
32 A5 I SSTL
125 A6 I SSTL
29 A7 I SSTL
122 A8 I SSTL Address Bus 11:0
27 A9 I SSTL
141 A10 I SSTL
AP I SSTL
118 A11 I SSTL
115 A12 I SSTL Address Signal 12
Note: Module based on 256 Mbit or larger dies
NC NC – Note: 128 Mbit based module
167 A13 I SSTL Address Signal 13
Note: 1 Gbit based module
NC NC – Note: Module based on 512 Mbit or smaller dies
Pin# Name Pin
Type
Buffer
Type
Function
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03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Data Signals
2 DQ0 I/O SSTL Data Bus 63:0
4 DQ1 I/O SSTL
6 DQ2 I/O SSTL
8 DQ3 I/O SSTL
94 DQ4 I/O SSTL
95 DQ5 I/O SSTL
98 DQ6 I/O SSTL
99 DQ7 I/O SSTL
12 DQ8 I/O SSTL
13 DQ9 I/O SSTL
19 DQ10 I/O SSTL
20 DQ11 I/O SSTL
105 DQ12 I/O SSTL
106 DQ13 I/O SSTL
109 DQ14 I/O SSTL
110 DQ15 I/O SSTL
23 DQ16 I/O SSTL
24 DQ17 I/O SSTL
28 DQ18 I/O SSTL
31 DQ19 I/O SSTL
114 DQ20 I/O SSTL
117 DQ21 I/O SSTL
121 DQ22 I/O SSTL
123 DQ23 I/O SSTL
33 DQ24 I/O SSTL
35 DQ25 I/O SSTL
39 DQ26 I/O SSTL
40 DQ27 I/O SSTL
126 DQ28 I/O SSTL
127 DQ29 I/O SSTL
131 DQ30 I/O SSTL
133 DQ31 I/O SSTL
53 DQ32 I/O SSTL
55 DQ33 I/O SSTL
57 DQ34 I/O SSTL
60 DQ35 I/O SSTL
146 DQ36 I/O SSTL
147 DQ37 I/O SSTL
150 DQ38 I/O SSTL
Pin# Name Pin
Type
Buffer
Type
Function
Internet Data Sheet
Rev. 1.22, 2007-01 8
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
151 DQ39 I/O SSTL Data Bus 63:0
61 DQ40 I/O SSTL
64 DQ41 I/O SSTL
68 DQ42 I/O SSTL
69 DQ43 I/O SSTL
153 DQ44 I/O SSTL
155 DQ45 I/O SSTL
161 DQ46 I/O SSTL
162 DQ47 I/O SSTL
72 DQ48 I/O SSTL
73 DQ49 I/O SSTL
79 DQ50 I/O SSTL
80 DQ51 I/O SSTL
165 DQ52 I/O SSTL
166 DQ53 I/O SSTL
170 DQ54 I/O SSTL
171 DQ55 I/O SSTL
83 DQ56 I/O SSTL
84 DQ57 I/O SSTL
87 DQ58 I/O SSTL
88 DQ59 I/O SSTL
174 DQ60 I/O SSTL
175 DQ61 I/O SSTL
178 DQ62 I/O SSTL
179 DQ63 I/O SSTL
44 CB0 I/O SSTL Check Bit 0
Note: ECC type module
NC NC – Note: Non-ECC module
45 CB1 I/O SSTL Check Bit 1
Note: ECC type module
NC NC – Note: Non-ECC module
49 CB2 I/O SSTL Check Bit 2
Note: ECC type module
NC NC – Note: Non-ECC module
51 CB3 I/O SSTL Check Bit 3
Note: ECC type module
NC NC – Note: Non-ECC module
134 CB4 I/O SSTL Check Bit 4
Note: ECC type module
NC NC – Note: Non-ECC module
Pin# Name Pin
Type
Buffer
Type
Function
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03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
135 CB5 I/O SSTL Check Bit 5
Note: ECC type module
NC NC – Note: Non-ECC module
142 CB6 I/O SSTL Check Bit 6
Note: ECC type module
NC NC – Note: Non-ECC module
144 CB7 I/O SSTL Check Bit 7
Note: ECC type module
NC NC – Note: Non-ECC module
5 DQS0 I/O SSTL Data Strobe Bus 7:0
14 DQS1 I/O SSTL
25 DQS2 I/O SSTL
36 DQS3 I/O SSTL
56 DQS4 I/O SSTL
67 DQS5 I/O SSTL
78 DQS6 I/O SSTL
86 DQS7 I/O SSTL
47 DQS8 I/O SSTL Data Strobe 8
Note: ECC type module
NC NC – Note: Non-ECC module
97 DM0 I SSTL Data Mask Bus 7:0
107 DM1 I SSTL
119 DM2 I SSTL
129 DM3 I SSTL
149 DM4 I SSTL
159 DM5 I SSTL
169 DM6 I SSTL
177 DM7 I SSTL
140 DM8 I SSTL Data Mask 8
Note: ECC type module
NC NC – Note: Non-ECC module
EEPROM
92 SCL I CMOS Serial Bus Clock
91 SDA I/O OD Serial Bus Data
181 SA0 I CMOS Slave Address Select Bus 2:0
182 SA1 I CMOS
183 SA2 I CMOS
Power Supplies
1VREF AI – I/O Reference Voltage
184 VDDSPD PWR – EEPROM Power Supply
Pin# Name Pin
Type
Buffer
Type
Function
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03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
15,
22,
30,
54,
62,
77,
96,
104,
112,
128,
136,
143,
156,
164,
172,
180
VDDQ PWR – I/O Driver Power Supply
7,
38,
46,
70,
85,
108,
120,
148,
168
VDD PWRzp – Power Supply
3,
11,
18,
26,
34,
42,
50,
58,
66,
74,
81,
89,
93,
100,
116,
124,
132,
139,
145,
152,
160,
176
VSS GND – Ground Plane
Pin# Name Pin
Type
Buffer
Type
Function
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03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Other Pins
82 VDDID OOD VDD Identification
9,
10,
71,
90,
101,
102,
103,
113,
163,
173
NC NC – Not connected
Pin# Name Pin
Type
Buffer
Type
Function
Internet Data Sheet
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03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 4
Abbreviations for Pin Type
TABLE 5
Abbreviations for Buffer Type
TABLE 6
Address Format
Abbreviation Description
I Standard input-only pin. Digital levels.
O Output. Digital levels.
I/O I/O is a bidirectional input/output signal.
AI Input. Analog levels.
PWR Power
GND Ground
NC Not Connected
Abbreviation Description
SSTL Serial Stub Terminated Logic (SSTL2)
LV-CMOS Low Voltage CMOS
CMOS CMOS Levels
OD Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Density Organization Memory
Ranks
SDRAMs # of
SDRAMs
# of row/bank/
columns bits
Refresh Period Interval
256 MB 32M ×64 1 32M ×16 4 13/2/9 8K 64 ms 7.8 ms
512 MB 64M ×64 1 64M ×88 13/2/11 8K 64ms7.8ms
512 MB 64M ×72 1 64M ×88 13/2/11 8K 64ms7.8ms
1 GB 128M ×64 2 64M ×8 16 13/2/12 8K 64 ms 7.8 ms
1 GB 128M ×72 2 64M ×8 18 13/2/12 8K 64 ms 7.8 ms
Internet Data Sheet
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03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
FIGURE 1
Pin Configuration 184-Pin, UDIMM
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Internet Data Sheet
Rev. 1.22, 2007-01 14
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
3 Electrical Characteristics
This chapter lists the electrical characteristics.
3.1 Operating Conditions
This chapter describes the operating conditions.
TABLE 7
Absolute Maximum Ratings
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This is a stress
rating only, and functional operation should be restricted to recommended operation conditions. Exposure
to absolute maximum rating conditions for extended periods of time may affect device reliability and
exceeding only one of the values may cause irreversible damage to the integrated circuit.
Parameter Symbol Values Unit Note/ Test
Condition
min. typ. max.
Voltage on I/O pins relative to VSS VIN, VOUT –0.5 — VDDQ + 0.5 V —
Voltage on inputs relative to VSS VIN –1 — +3.6 V —
Voltage on VDD supply relative to VSS VDD –1 — +3.6 V —
Voltage on VDDQ supply relative to VSS VDDQ –1 — +3.6 V —
Operating temperature (ambient) TA0—+70 °C—
Storage temperature (plastic) TSTG –55 — +150 °C—
Power dissipation (per SDRAM component) PD — 1 — W —
Short circuit output current IOUT —50— mA—
Internet Data Sheet
Rev. 1.22, 2007-01 15
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 8
Electrical Characteristics and DC Operating Conditions
Parameter Symbol Values Unit Note1) / Test Condition
1) 0 °C ≤ TA ≤ 70 °C
Min. Typ. Max.
Device Supply Voltage VDD 2.3 2.5 2.7 V fCK ≤166 MHz
Device Supply Voltage VDD 2.5 2.6 2.7 V fCK >166MHz
2)
2) DDR400 conditions apply for all clock frequencies above 166 MHz
Output Supply Voltage VDDQ 2.3 2.5 2.7 V fCK ≤166 MHz 3)
3) Under all conditions, VDDQ must be less than or equal to VDD.
Output Supply Voltage VDDQ 2.5 2.6 2.7 V fCK >166MHz
2)3)
EEPROM supply voltage VDDSPD 2.3 2.5 3.6 V —
Supply Voltage, I/O Supply
Voltage
VSS,
VSSQ
0—0V—
Input Reference Voltage VREF 0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ V4)
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
I/O Termination Voltage
(System)
VTT VREF – 0.04 — VREF + 0.04 V 5)
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF.
Input High (Logic1) Voltage VIH(DC) VREF + 0.15 — VDDQ + 0.3 V 8)
Input Low (Logic0) Voltage VIL(DC) –0.3 —VREF – 0.15 V 8)
Input Voltage Level, CK and
CK Inputs
VIN(DC) –0.3 —VDDQ + 0.3 V 8)
Input Differential Voltage, CK
and CK Inputs
VID(DC) 0.36 — VDDQ + 0.6 V 8)6)
6) VID is the magnitude of the difference between the input level on CK and the input level on CK.
VI-Matching Pull-up Current
to Pull-down Current
VIRatio 0.71 — 1.4 — 7)
7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature
and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
Input Leakage Current II–2 — 2 µAAny input 0V ≤VIN ≤VDD; All
other pins not under test = 0 V
8)9)
8) Inputs are not recognized as valid until VREF stabilizes.
9) Values are shown per component
Output Leakage Current IOZ –5 — 5 µA DQs are disabled; 0 V ≤ VOUT ≤
VDDQ 8)
Output High Current, Normal
Strength Driver
IOH — — –16.2 mA VOUT = 1.95 V 8)
Output Low Current, Normal
Strength Driver
IOL 16.2 — — mA VOUT = 0.35 V 8)
Internet Data Sheet
Rev. 1.22, 2007-01 16
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 9
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter Symbol –5 –6 Unit Note1) / Test
Condition
DDR400B DDR333
Min. Max. Min. Max.
DQ output access time from CK/CK tAC –0.5 +0.5 –0.7 +0.7 ns 2)3)4)5)
DQS output access time from CK/CK tDQSCK –0.6 +0.6 –0.6 +0.6 ns 2)3)4)5)
CK high-level width tCH 0.45 0.55 0.45 0.55 tCK
2)3)4)5)
CK low-level width tCL 0.45 0.55 0.45 0.55 tCK
2)3)4)5)
Clock Half Period tHP Min. (tCL, tCH)Min. (tCL, tCH)ns 2)3)4)5)
Clock cycle time tCK 5 8 — — ns CL = 3.0 2)3)4)5)
6 12 7.5 12 ns CL = 2.5 2)3)4)5)
7.5 12 7.5 12 ns CL = 2.0 2)3)4)5)
DQ and DM input hold time tDH 0.4 — 0.45 — ns 2)3)4)5)
DQ and DM input setup time tDS 0.4 — 0.45 — ns 2)3)4)5)
Control and Addr. input pulse width (each
input)
tIPW 2.2 — 2.2 — ns 2)3)4)5)6)
DQ and DM input pulse width (each input) tDIPW 1.75 — 1.75 — ns 2)3)4)5)6)
Data-out high-impedance time from CK/CK tHZ –0.7 +0.7 –0.7 +0.7 ns 2)3)4)5)7)
Data-out low-impedance time from CK/CK tLZ –0.7 +0.7 –0.7 +0.7 ns 2)3)4)5)7)
Write command to 1st DQS latching
transition
tDQSS 0.75 1.25 0.75 1.25 tCK
2)3)4)5)
DQS-DQ skew (DQS and associated DQ
signals)
tDQSQ — +0.40 — +0.45 ns TSOPII 2)3)4)5)
Data hold skew factor tQHS — +0.50 — +0.55 ns TSOPII 2)3)4)5)
DQ/DQS output hold time tQH tHP –tQHS tHP –tQHS ns 2)3)4)5)
DQS input low (high) pulse width (write
cycle)
tDQSL,H 0.35 — 0.35 — tCK
2)3)4)5)
DQS falling edge to CK setup time (write
cycle)
tDSS 0.2 — 0.2 — tCK
2)3)4)5)
DQS falling edge hold time from CK (write
cycle)
tDSH 0.2 — 0.2 — tCK
2)3)4)5)
Mode register set command cycle time tMRD 2— 2— tCK
2)3)4)5)
Write preamble setup time tWPRES 0— 0— ns
2)3)4)5)8)
Write postamble tWPST 0.40 0.60 0.40 0.60 tCK
2)3)4)5)9)
Write preamble tWPRE 0.25 — 0.25 — tCK
2)3)4)5)
Address and control input setup time tIS 0.6 — 0.75 — ns Fast slew rate
3)4)5)6)10)
0.7 — 0.8 — ns Slow slew rate
3)4)5)6)10)
Internet Data Sheet
Rev. 1.22, 2007-01 17
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Address and control input hold time tIH 0.6 — 0.75 — ns Fast slew rate
3)4)5)6)10)
0.7 — 0.8 — ns Slow slew rate
3)4)5)6)10)
Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK
2)3)4)5)
Read postamble tRPST 0.40 0.60 0.40 0.60 tCK
2)3)4)5)
Active to Precharge command tRAS 40 70E+3 42 70E+3 ns 2)3)4)5)
Active to Active/Auto-refresh command
period
tRC 55 — 60 — ns 2)3)4)5)
Auto-refresh to Active/Auto-refresh
command period
tRFC 70 — 72 — ns 2)3)4)5)
Active to Read or Write delay tRCD 15 — 18 — ns 2)3)4)5)
Precharge command period tRP 15 — 18 — ns 2)3)4)5)
Active to Autoprecharge delay tRAP tRCD – tRASmin ns 2)3)4)5)
Active bank A to Active bank B command tRRD 10 — 12 — ns 2)3)4)5)
Write recovery time tWR 15 — 15 — ns 2)3)4)5)
Auto precharge write recovery + precharge
time
tDAL —— —— tCK
2)3)4)5)11)
Internal write to read command delay tWTR 2— 1— tCK
2)3)4)5)
Exit self-refresh to non-read command tXSNR 75 — 75 — ns 2)3)4)5)
Exit self-refresh to read command tXSRD 200 — 200 — tCK
2)3)4)5)
Average Periodic Refresh Interval tREFI —7.8 —7.8 µs2)3)4)5)12)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ±0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns, slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac).
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Parameter Symbol –5 –6 Unit Note1) / Test
Condition
DDR400B DDR333
Min. Max. Min. Max.
Internet Data Sheet
Rev. 1.22, 2007-01 18
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
3.2 Current Conditions and Specification
This chapter describes the Conditions and Specification.
TABLE 10
IDD Specification for HYS[64/72]D[32/64/128]3xxHU–5–B
Product Type
HYS64D32301HU–5–B
HYS64D64300HU–5–B
HYS64D64300GU–5–B
HYS72D64300HU–5–B
HYS72D64300GU–5–B
HYS64D128320HU–5–B
HYS64D128320GU–5–B
HYS72D128320HU–5–B
Unit Note 1)2)
1) DRAM component currents only
2) Test condition for maximum values: VDD =2.7V, TA=10°C
Organization 256 MB 512 MB 512 MB 1 GB 1 GB
×64 ×64 ×64 ×64 ×72
1Rank 1Rank 1Rank 2Ranks 2Ranks
–5 –5 –5 –5 –5
Symbol Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max.
IDD0 400 480 640 800 720 900 950 1180 1070 1330 mA 3)
3) The module IDDx values are calculated from the component IDDx data sheet values as: m×IDDx [component] + n×IDD3N [component] with
m and n number of components of rank 1 and 2; n=0 for 1 rank modules
IDD1 460 560 720 880 810 990 1030 1260 1160 1420 mA 3)4)
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
IDD2P 10 20 10 30 20 40 30 64 31 70 mA 5)
5) The module IDDx values are calculated from the component IDDx data sheet values as: (m + n) × IDDx [component]
IDD2F 120 140 240 290 270 320 480 580 540 650 mA 5)
IDD2Q 80 100 150 210 170 230 300 420 340 470 mA 5)
IDD3P 50 60 100 130 110 140 190 260 220 290 mA 5)
IDD3N 170 200 310 380 350 420 620 750 700 850 mA 5)
IDD4R 480 580 680 800 770 900 990 1180 1120 1320 mA 3)4)
IDD4W 500 600 720 840 810 950 1030 1220 1160 1370 mA 3)
IDD5 820 980 1640 1960 1850 2210 1950 2340 2200 2630 mA 3)
IDD6 11 20.8 22 42 30 50 45 80 50 90 mA 3)
IDD7 1140 1360 2080 2480 2340 2790 2390 2860 2690 3210 mA 3)4)
Internet Data Sheet
Rev. 1.22, 2007-01 19
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 11
IDD Specification for HYS[64/72]D[64/128]3xxHU–6–B
Product Type
HYS64D64300HU–6–B
HYS64D64300GU–6–B
HYS72D64300HU–6–B
HYS72D64300GU–6–B
HYS64D128320HU–6–B
HYS64D128320GU–6–B
HYS72D128320HU–6–B
Unit Note 1)2)
1) DRAM component currents only
2) Test condition for maximum values: VDD =2.7V, TA=10°C
Organization 512 MB 512 MB 1 GB 1 GB
×64 ×72 ×64 ×72
1 Rank 1 Rank 2 Ranks 2 Ranks
–6 –6 –6 –6
Symbol Typ. Max. Typ. Max. Typ. Max. Typ. Max.
IDD0 600 720 680 810 880 1050 990 1180 mA 3)
3) The module IDDx values are calculated from the component IDDx data sheet values as: m×IDDx [component] + n×IDD3N [component] with
m and n number of components of rank 1 and 2; n=0 for 1 rank modules
IDD1 680 800 770 900 960 1130 1080 1270 mA 3)4)
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
IDD2P 10 30 10 40 30 64 290 70 mA 5)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx [component]
IDD2F 200 240 230 270 400 480 450 540 mA 5)
IDD2Q 140 190 150 220 270 380 310 430 mA 5)
IDD3P 90 120 100 140 180 240 200 270 mA 5)
IDD3N 280 330 320 370 560 660 630 740 mA 5)
IDD4R 620 720 690 810 900 1050 1010 1180 mA 3)4)
IDD4W 650 760 730 860 930 1090 1040 1220 mA 3)
IDD5 1480 1760 1670 1980 1760 2090 1980 2350 mA 3)
IDD6 22 42 24 47 43 80 49 94 mA 3)
IDD7 1870 2230 2110 2510 2150 2560 2420 2880 mA 3)4)
Internet Data Sheet
Rev. 1.22, 2007-01 20
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
4 SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•Table 12 “HYS[64/72]D[64/128]3x0GU-5-B” on Page 20
•Table 13 “HYS[64/72]D[64/128]3x0GU-6-B” on Page 24
•Table 14 “HYS[64/72]D[32/64/128]3xxHU-5-B” on Page 28
•Table 15 “HYS[64/72]D[64/128]3x0HU-6-B” on Page 32
TABLE 12
HYS[64/72]D[64/128]3x0GU-5-B
Product Type
HYS64D64300GU–5–B
HYS72D64300GU–5–B
HYS64D128320GU–5–B
HYS72D128320GU–5–B
Organization 512MB 512MB 1 GByte 1 GByte
×64 ×72 ×64 ×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code PC3200U–
30330
PC3200U–
30330
PC3200U–
30330
PC3200U–
30330
JEDEC SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80 80 80
1 Total number of Bytes in E2PROM 08 08 08 08
2 Memory Type (DDR = 07h) 07 07 07 07
3 Number of Row Addresses 0D 0D 0D 0D
4 Number of Column Addresses 0B 0B 0B 0B
5 Number of DIMM Ranks 01 01 02 02
6 Data Width (LSB) 40 48 40 48
7 Data Width (MSB) 00 00 00 00
8 Interface Voltage Levels 04 04 04 04
9 tCK @ CLmax (Byte 18) [ns] 50 50 50 50
10 tAC SDRAM @ CLmax (Byte 18) [ns] 50 50 50 50
11 Error Correction Support 00 02 00 02
Internet Data Sheet
Rev. 1.22, 2007-01 21
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
12 Refresh Rate 82 82 82 82
13 Primary SDRAM Width 08 08 08 08
14 Error Checking SDRAM Width 00 08 00 08
15 tCCD [cycles] 01 01 01 01
16 Burst Length Supported 0E 0E 0E 0E
17 Number of Banks on SDRAM Device 04 04 04 04
18 CAS Latency 1C 1C 1C 1C
19 CS Latency 01 01 01 01
20 Write Latency 02 02 02 02
21 DIMM Attributes 20 20 20 20
22 Component Attributes C1 C1 C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 60 60 60
24 tAC SDRAM @ CLmax -0.5 [ns] 50 50 50 50
25 tCK@ CLmax -1 (Byte 18) [ns] 75 75 75 75
26 tAC SDRAM @ CLmax -1 [ns] 50 50 50 50
27 tRPmin [ns] 3C 3C 3C 3C
28 tRRDmin [ns] 28 28 28 28
29 tRCDmin [ns] 3C 3C 3C 3C
30 tRASmin [ns] 28 28 28 28
31 Module Density per Rank 80 80 80 80
32 tAS, tCS [ns] 60 60 60 60
33 tAH, tCH [ns] 60 60 60 60
34 tDS [ns] 40 40 40 40
35 tDH [ns] 40 40 40 40
36 - 40 Not used 00 00 00 00
41 tRCmin [ns] 37 37 37 37
Product Type
HYS64D64300GU–5–B
HYS72D64300GU–5–B
HYS64D128320GU–5–B
HYS72D128320GU–5–B
Organization 512MB 512MB 1 GByte 1 GByte
×64 ×72 ×64 ×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code PC3200U–
30330
PC3200U–
30330
PC3200U–
30330
PC3200U–
30330
JEDEC SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX HEX
Internet Data Sheet
Rev. 1.22, 2007-01 22
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
42 tRFCmin [ns] 41 41 41 41
43 tCKmax [ns] 28 28 28 28
44 tDQSQmax [ns] 28 28 28 28
45 tQHSmax [ns] 50 50 50 50
46 Not used 00 00 00 00
47 DIMM PCB Height 00 00 00 00
48 - 61 Not used 00 00 00 00
62 SPD Revision 00 00 00 00
63 Checksum of Byte 0-62 3E 50 3F 51
64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 7F
65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 7F
66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 7F
67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 7F
68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 7F
69 Manufacturer’s JEDEC ID Code (6) 51 51 51 51
70 Manufacturer’s JEDEC ID Code (7) 00 00 00 00
71 Manufacturer’s JEDEC ID Code (8) 00 00 00 00
72 Module Manufacturer Location xx xx xx xx
73 Part Number, Char 1 36 37 36 37
74 Part Number, Char 2 34 32 34 32
75 Part Number, Char 3 44 44 44 44
76 Part Number, Char 4 36 36 31 31
77 Part Number, Char 5 34 34 32 32
78 Part Number, Char 6 33 33 38 38
79 Part Number, Char 7 30 30 33 33
80 Part Number, Char 8 30 30 32 32
Product Type
HYS64D64300GU–5–B
HYS72D64300GU–5–B
HYS64D128320GU–5–B
HYS72D128320GU–5–B
Organization 512MB 512MB 1 GByte 1 GByte
×64 ×72 ×64 ×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code PC3200U–
30330
PC3200U–
30330
PC3200U–
30330
PC3200U–
30330
JEDEC SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX HEX
Internet Data Sheet
Rev. 1.22, 2007-01 23
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
81 Part Number, Char 9 47 47 30 30
82 Part Number, Char 10 55 55 47 47
83 Part Number, Char 11 35 35 55 55
84 Part Number, Char 12 42 42 35 35
85 Part Number, Char 13 20 20 42 42
86 Part Number, Char 14 20 20 20 20
87 Part Number, Char 15 20 20 20 20
88 Part Number, Char 16 20 20 20 20
89 Part Number, Char 17 20 20 20 20
90 Part Number, Char 18 20 20 20 20
91 Module Revision Code 1x 1x 1x 1x
92 Test Program Revision Code xx xx xx xx
93 Module Manufacturing Date Year xx xx xx xx
94 Module Manufacturing Date Week xx xx xx xx
95 - 98 Module Serial Number xx xx xx xx
99 - 127 Not used 00 00 00 00
Product Type
HYS64D64300GU–5–B
HYS72D64300GU–5–B
HYS64D128320GU–5–B
HYS72D128320GU–5–B
Organization 512MB 512MB 1 GByte 1 GByte
×64 ×72 ×64 ×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code PC3200U–
30330
PC3200U–
30330
PC3200U–
30330
PC3200U–
30330
JEDEC SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX HEX
Internet Data Sheet
Rev. 1.22, 2007-01 24
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 13
HYS[64/72]D[64/128]3x0GU-6-B
Product Type
HYS64D64300GU–6–B
HYS72D64300GU–6–B
HYS64D128320GU–6–B
HYS72D128320GU–6–B
Organization 512MB 512MB 1 GByte 1 GByte
×64 ×72 ×64 ×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
JEDEC SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80 80 80
1 Total number of Bytes in E2PROM 08 08 08 08
2 Memory Type (DDR = 07h) 07 07 07 07
3 Number of Row Addresses 0D 0D 0D 0D
4 Number of Column Addresses 0B 0B 0B 0B
5 Number of DIMM Ranks 01 01 02 02
6 Data Width (LSB) 40 48 40 48
7 Data Width (MSB) 00 00 00 00
8 Interface Voltage Levels 04 04 04 04
9 tCK @ CLmax (Byte 18) [ns] 60 60 60 60
10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70
11 Error Correction Support 00 02 00 02
12 Refresh Rate 82 82 82 82
13 Primary SDRAM Width 08 08 08 08
14 Error Checking SDRAM Width 00 08 00 08
15 tCCD [cycles] 01 01 01 01
16 Burst Length Supported 0E 0E 0E 0E
17 Number of Banks on SDRAM Device 04 04 04 04
18 CAS Latency 0C 0C 0C 0C
19 CS Latency 01 01 01 01
20 Write Latency 02 02 02 02
21 DIMM Attributes 20 20 20 20
22 Component Attributes C1 C1 C1 C1
Internet Data Sheet
Rev. 1.22, 2007-01 25
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75 75 75
24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 70 70
25 tCK @ CLmax-1 (Byte 18) [ns] 00 00 00 00
26 tAC SDRAM @ CLmax -1 [ns] 00 00 00 00
27 tRPmin [ns] 48 48 48 48
28 tRRDmin [ns] 30 30 30 30
29 tRCDmin [ns] 48 48 48 48
30 tRASmin [ns] 2A 2A 2A 2A
31 Module Density per Rank 80 80 80 80
32 tAS, tCS [ns] 75 75 75 75
33 tAH, tCH [ns] 75 75 75 75
34 tDS [ns] 45 45 45 45
35 tDH [ns] 45 45 45 45
36 - 40 Not used 00 00 00 00
41 tRCmin [ns] 3C 3C 3C 3C
42 tRFCmin [ns] 48 48 48 48
43 tCKmax [ns] 30 30 30 30
44 tDQSQmax [ns] 2D 2D 2D 2D
45 tQHSmax [ns] 55 55 55 55
46 Not used 00 00 00 00
47 DIMM PCB Height 00 00 00 00
48 - 61 Not used 00 00 00 00
62 SPD Revision 00 00 00 00
63 Checksum of Byte 0-62 42 54 43 55
64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 7F
65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 7F
Product Type
HYS64D64300GU–6–B
HYS72D64300GU–6–B
HYS64D128320GU–6–B
HYS72D128320GU–6–B
Organization 512MB 512MB 1 GByte 1 GByte
×64 ×72 ×64 ×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
JEDEC SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX HEX
Internet Data Sheet
Rev. 1.22, 2007-01 26
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 7F
67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 7F
68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 7F
69 Manufacturer’s JEDEC ID Code (6) 51 51 51 51
70 Manufacturer’s JEDEC ID Code (7) 00 00 00 00
71 Manufacturer’s JEDEC ID Code (8) 00 00 00 00
72 Module Manufacturer Location xx xx xx xx
73 Part Number, Char 1 36 37 36 37
74 Part Number, Char 2 34 32 34 32
75 Part Number, Char 3 44 44 44 44
76 Part Number, Char 4 36 36 31 31
77 Part Number, Char 5 34 34 32 32
78 Part Number, Char 6 33 33 38 38
79 Part Number, Char 7 30 30 33 33
80 Part Number, Char 8 30 30 32 32
81 Part Number, Char 9 47 47 30 30
82 Part Number, Char 10 55 55 47 47
83 Part Number, Char 11 36 36 55 55
84 Part Number, Char 12 42 42 36 36
85 Part Number, Char 13 20 20 42 42
86 Part Number, Char 14 20 20 20 20
87 Part Number, Char 15 20 20 20 20
88 Part Number, Char 16 20 20 20 20
89 Part Number, Char 17 20 20 20 20
90 Part Number, Char 18 20 20 20 20
91 Module Revision Code 1x 1x 1x 1x
Product Type
HYS64D64300GU–6–B
HYS72D64300GU–6–B
HYS64D128320GU–6–B
HYS72D128320GU–6–B
Organization 512MB 512MB 1 GByte 1 GByte
×64 ×72 ×64 ×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
JEDEC SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX HEX
Internet Data Sheet
Rev. 1.22, 2007-01 27
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
92 Test Program Revision Code xx xx xx xx
93 Module Manufacturing Date Year xx xx xx xx
94 Module Manufacturing Date Week xx xx xx xx
95 - 98 Module Serial Number xx xx xx xx
99 - 127 Not used 00 00 00 00
Product Type
HYS64D64300GU–6–B
HYS72D64300GU–6–B
HYS64D128320GU–6–B
HYS72D128320GU–6–B
Organization 512MB 512MB 1 GByte 1 GByte
×64 ×72 ×64 ×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
JEDEC SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX HEX
Internet Data Sheet
Rev. 1.22, 2007-01 28
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 14
HYS[64/72]D[32/64/128]3xxHU-5-B
Product Type
HYS64D32301HU–5–B
HYS64D64300HU–5–B
HYS72D64300HU–5–B
HYS64D128320HU–5–B
HYS72D128320HU–5–B
Organization 256MB 512MB 512MB 1 GByte 1 GByte
×64 ×64 ×72 ×64 ×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code PC3200U
–30331
PC3200U
–30330
PC3200U
–30330
PC3200U
–30330
PC3200U
–30330
JEDEC SPD Revision Rev. 1.0 Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80 80 80 80
1 Total number of Bytes in E2PROM 08 08 08 08 08
2 Memory Type (DDR = 07h) 07 07 07 07 07
3 Number of Row Addresses 0D0D0D0D0D
4 Number of Column Addresses 0A0B0B0B0B
5 Number of DIMM Ranks 0101010202
6 Data Width (LSB) 4040484048
7 Data Width (MSB) 00 00 00 00 00
8 Interface Voltage Levels 04 04 04 04 04
9 tCK @ CLmax (Byte 18) [ns] 50 50 50 50 50
10 tAC SDRAM @ CLmax (Byte 18) [ns] 50 50 50 50 50
11 Error Correction Support 00 00 02 00 02
12 Refresh Rate 82 82 82 82 82
13 Primary SDRAM Width 1008080808
14 Error Checking SDRAM Width 00 00 08 00 08
15 tCCD [cycles] 01 01 01 01 01
16 Burst Length Supported 0E 0E 0E 0E 0E
17 Number of Banks on SDRAM Device 04 04 04 04 04
18 CAS Latency 1C1C1C1C1C
19 CS Latency 01 01 01 01 01
20 Write Latency 0202020202
21 DIMM Attributes 20 20 20 20 20
22 Component Attributes C1 C1 C1 C1 C1
Internet Data Sheet
Rev. 1.22, 2007-01 29
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 60 60 60 60
24 tAC SDRAM @ CLmax -0.5 [ns] 50 50 50 50 50
25 tCK @ CLmax -1 (Byte 18) [ns] 75 75 75 75 75
26 tAC SDRAM @ CLmax -1 [ns] 50 50 50 50 50
27 tRPmin [ns] 3C 3C 3C 3C 3C
28 tRRDmin [ns] 28 28 28 28 28
29 tRCDmin [ns] 3C 3C 3C 3C 3C
30 tRASmin [ns] 28 28 28 28 28
31 Module Density per Rank 40 80 80 80 80
32 tAS, tCS [ns] 60 60 60 60 60
33 tAH, tCH [ns] 60 60 60 60 60
34 tDS [ns] 40 40 40 40 40
35 tDH [ns] 40 40 40 40 40
36 - 40 Not used 00 00 00 00 00
41 tRCmin [ns] 37 37 37 37 37
42 tRFCmin [ns] 41 41 41 41 41
43 tCKmax [ns] 28 28 28 28 28
44 tDQSQmax [ns] 28 28 28 28 28
45 tQHSmax [ns] 50 50 50 50 50
46 Not used 00 00 00 00 00
47 DIMM PCB Height 01 00 00 00 00
48 - 61 Not used 00 00 00 00 00
62 SPD Revision 10 00 00 00 00
63 Checksum of Byte 0-62 16 3E 50 3F 51
64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 7F 7F
Product Type
HYS64D32301HU–5–B
HYS64D64300HU–5–B
HYS72D64300HU–5–B
HYS64D128320HU–5–B
HYS72D128320HU–5–B
Organization 256MB 512MB 512MB 1 GByte 1 GByte
×64 ×64 ×72 ×64 ×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code PC3200U
–30331
PC3200U
–30330
PC3200U
–30330
PC3200U
–30330
PC3200U
–30330
JEDEC SPD Revision Rev. 1.0 Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX HEX HEX
Internet Data Sheet
Rev. 1.22, 2007-01 30
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 7F 7F
66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 7F 7F
67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 7F 7F
68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 7F 7F
69 Manufacturer’s JEDEC ID Code (6) 51 51 51 51 51
70 Manufacturer’s JEDEC ID Code (7) 00 00 00 00 00
71 Manufacturer’s JEDEC ID Code (8) 00 00 00 00 00
72 Module Manufacturer Location xx xx xx xx xx
73 Part Number, Char 1 3636373637
74 Part Number, Char 2 3434323432
75 Part Number, Char 3 4444444444
76 Part Number, Char 4 3336363131
77 Part Number, Char 5 3234343232
78 Part Number, Char 6 3333333838
79 Part Number, Char 7 3030303333
80 Part Number, Char 8 3130303232
81 Part Number, Char 9 4848483030
82 Part Number, Char 10 55 55 55 48 48
83 Part Number, Char 11 35 35 35 55 55
84 Part Number, Char 12 42 42 42 35 35
85 Part Number, Char 13 20 20 20 42 42
86 Part Number, Char 14 20 20 20 20 20
87 Part Number, Char 15 20 20 20 20 20
88 Part Number, Char 16 20 20 20 20 20
89 Part Number, Char 17 20 20 20 20 20
Product Type
HYS64D32301HU–5–B
HYS64D64300HU–5–B
HYS72D64300HU–5–B
HYS64D128320HU–5–B
HYS72D128320HU–5–B
Organization 256MB 512MB 512MB 1 GByte 1 GByte
×64 ×64 ×72 ×64 ×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code PC3200U
–30331
PC3200U
–30330
PC3200U
–30330
PC3200U
–30330
PC3200U
–30330
JEDEC SPD Revision Rev. 1.0 Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX HEX HEX
Internet Data Sheet
Rev. 1.22, 2007-01 31
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
90 Part Number, Char 18 20 20 20 20 20
91 Module Revision Code 1x 1x 1x 1x 1x
92 Test Program Revision Code xx xx xx xx xx
93 Module Manufacturing Date Year xx xx xx xx xx
94 Module Manufacturing Date Week xx xx xx xx xx
95 - 98 Module Serial Number xx xx xx xx xx
99 - 127 Not used 00 00 00 00 00
Product Type
HYS64D32301HU–5–B
HYS64D64300HU–5–B
HYS72D64300HU–5–B
HYS64D128320HU–5–B
HYS72D128320HU–5–B
Organization 256MB 512MB 512MB 1 GByte 1 GByte
×64 ×64 ×72 ×64 ×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code PC3200U
–30331
PC3200U
–30330
PC3200U
–30330
PC3200U
–30330
PC3200U
–30330
JEDEC SPD Revision Rev. 1.0 Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX HEX HEX
Internet Data Sheet
Rev. 1.22, 2007-01 32
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
TABLE 15
HYS[64/72]D[64/128]3x0HU-6-B
Product Type
HYS64D64300HU–6–B
HYS72D64300HU–6–B
HYS64D128320HU–6–B
HYS72D128320HU–6–B
Organization 512MB 512MB 1 GByte 1 GByte
×64 ×72 ×64 ×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
JEDEC SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80 80 80
1 Total number of Bytes in E2PROM 08 08 08 08
2 Memory Type (DDR = 07h) 07 07 07 07
3 Number of Row Addresses 0D 0D 0D 0D
4 Number of Column Addresses 0B 0B 0B 0B
5 Number of DIMM Ranks 01 01 02 02
6 Data Width (LSB) 40 48 40 48
7 Data Width (MSB) 00 00 00 00
8 Interface Voltage Levels 04 04 04 04
9 tCK @ CLmax (Byte 18) [ns] 60 60 60 60
10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70
11 Error Correction Support 00 02 00 02
12 Refresh Rate 82 82 82 82
13 Primary SDRAM Width 08 08 08 08
14 Error Checking SDRAM Width 00 08 00 08
15 tCCD [cycles] 01 01 01 01
16 Burst Length Supported 0E 0E 0E 0E
17 Number of Banks on SDRAM Device 04 04 04 04
18 CAS Latency 0C 0C 0C 0C
19 CS Latency 01 01 01 01
20 Write Latency 02 02 02 02
21 DIMM Attributes 20 20 20 20
22 Component Attributes C1 C1 C1 C1
Internet Data Sheet
Rev. 1.22, 2007-01 33
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75 75 75
24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 70 70
25 tCK @ CLmax -1 (Byte 18) [ns] 00 00 00 00
26 tAC SDRAM @ CLmax -1 [ns] 00 00 00 00
27 tRPmin [ns] 48 48 48 48
28 tRRDmin [ns] 30 30 30 30
29 tRCDmin [ns] 48 48 48 48
30 tRASmin [ns] 2A 2A 2A 2A
31 Module Density per Rank 80 80 80 80
32 tAS, tCS [ns] 75 75 75 75
33 tAH, tCH [ns] 75 75 75 75
34 tDS [ns] 45 45 45 45
35 tDH [ns] 45 45 45 45
36 - 40 Not used 00 00 00 00
41 tRCmin [ns] 3C 3C 3C 3C
42 tRFCmin [ns] 48 48 48 48
43 tCKmax [ns] 30 30 30 30
44 tDQSQmax [ns] 2D 2D 2D 2D
45 tQHSmax [ns] 55 55 55 55
46 Not used 00 00 00 00
47 DIMM PCB Height 00 00 00 00
48 - 61 Not used 00 00 00 00
62 SPD Revision 00 00 00 00
63 Checksum of Byte 0-62 42 54 43 55
64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 7F
65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 7F
Product Type
HYS64D64300HU–6–B
HYS72D64300HU–6–B
HYS64D128320HU–6–B
HYS72D128320HU–6–B
Organization 512MB 512MB 1 GByte 1 GByte
×64 ×72 ×64 ×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
JEDEC SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX HEX
Internet Data Sheet
Rev. 1.22, 2007-01 34
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 7F
67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 7F
68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 7F
69 Manufacturer’s JEDEC ID Code (6) 51 51 51 51
70 Manufacturer’s JEDEC ID Code (7) 00 00 00 00
71 Manufacturer’s JEDEC ID Code (8) 00 00 00 00
72 Module Manufacturer Location xx xx xx xx
73 Part Number, Char 1 36 37 36 37
74 Part Number, Char 2 34 32 34 32
75 Part Number, Char 3 44 44 44 44
76 Part Number, Char 4 36 36 31 31
77 Part Number, Char 5 34 34 32 32
78 Part Number, Char 6 33 33 38 38
79 Part Number, Char 7 30 30 33 33
80 Part Number, Char 8 30 30 32 32
81 Part Number, Char 9 48 48 30 30
82 Part Number, Char 10 55 55 48 48
83 Part Number, Char 11 36 36 55 55
84 Part Number, Char 12 42 42 36 36
85 Part Number, Char 13 20 20 42 42
86 Part Number, Char 14 20 20 20 20
87 Part Number, Char 15 20 20 20 20
88 Part Number, Char 16 20 20 20 20
89 Part Number, Char 17 20 20 20 20
90 Part Number, Char 18 20 20 20 20
91 Module Revision Code 1x 1x 1x 1x
Product Type
HYS64D64300HU–6–B
HYS72D64300HU–6–B
HYS64D128320HU–6–B
HYS72D128320HU–6–B
Organization 512MB 512MB 1 GByte 1 GByte
×64 ×72 ×64 ×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
JEDEC SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX HEX
Internet Data Sheet
Rev. 1.22, 2007-01 35
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
92 Test Program Revision Code xx xx xx xx
93 Module Manufacturing Date Year xx xx xx xx
94 Module Manufacturing Date Week xx xx xx xx
95 - 98 Module Serial Number xx xx xx xx
99 - 127 Not used 00 00 00 00
Product Type
HYS64D64300HU–6–B
HYS72D64300HU–6–B
HYS64D128320HU–6–B
HYS72D128320HU–6–B
Organization 512MB 512MB 1 GByte 1 GByte
×64 ×72 ×64 ×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
PC2700U–
25330
JEDEC SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX HEX
Internet Data Sheet
Rev. 1.22, 2007-01 36
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
5 Package Outlines
This chapter contains the package outlines of the products.
FIGURE 2
Raw Card C DDR UDIMM HYS64D32301HU–5–B (1 Rank Module)
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Internet Data Sheet
Rev. 1.22, 2007-01 37
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
FIGURE 3
Raw Card A DDR UDIMM HYS64D64300HU–[5/6/7]–B (1 Rank Module)
92
1
1.27 1±0.05 0.1 BA C
Detail of contacts
0.2
3 MIN.
2.5 ±0.2
3.8
93
±0.13
±0.1
1.8 A
0.1 CB
17.8
10
184
92
1.27 ±0.1
C
0.4
B
31.75 ±0.13
2.7 MAX.
6.62
±0.1
1
2.36
64.77
95 x
CBA
ø0.1
6.35
120.651.27 =
2.175
49.53
92
±0.1
40.1 ABC
128.95
133.35 B
0.15 A C
A
Burr max. 0.4 allowed
Internet Data Sheet
Rev. 1.22, 2007-01 38
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
FIGURE 4
Raw Card A DDR UDIMM HYS72D64300HU–[5/6/7F]–B (1 Rank Module)
192
±0.13
1
±0.05
1.27 0.1 BA C
Detail of contacts
0.2
3 MIN.
3.8
93
2.5 ±0.2
1.8
±0.1
CA
0.1 B
17.8
184
10
4±0.1 0.1 ACB
128.95
A
133.35
2.7 MAX.
0.15 BA C
6.35
±0.1
2.36
1
64.77
ø0.1 C
A B
1.27x95 120.65=
2.175
6.62
49.53
92 B
±0.13
31.75
1.27
C
±0.1
0.4
1)
Burr max. 0.4 allowed
1) On ECC modules only
Internet Data Sheet
Rev. 1.22, 2007-01 39
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
FIGURE 5
Raw Card B DDR UDIMM HYS64D128320HU–[5/6/7]–B (2 Ranks Module)
4CB
0.1 A
±0.1
2.36
1
±0.1
C
64.77
ø0.1 A B
95
133.35
128.95
1.27x=
2.175
6.62
120.65
A
6.35 1.27
0.15
4 MAX.
49.53
92
0.4
31.75
B
±0.13
C
B
±0.1
A C
0.1
Detail of contacts
0.2
1.27
3.8
±0.13
3 MIN.
93
±0.2
2.5
1
±0.05
0.1 ACB
1.8
±0.1
BA C 184
10
17.8
Burr max. 0.4 allowed
Internet Data Sheet
Rev. 1.22, 2007-01 40
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
FIGURE 6
Raw Card B DDR UDIMM HYS72D128320HU–[5/6/7]–B (2 Rank Module)
11 9292
±0.1
1.27
C
4 MAX.
0.4
A
0.1 B C
A
133.35
128.95
A
0.15 B C
±0.1
4
B
±0.13
31.75
A
64.77
2.36 ±0.1 ø0.1
6.35
95 x 1.27 = 120.65
6.62
CB
2.175
49.53
±0.05
1
1.27
0.2
Detail of contacts
0.1 ABC
2.5 ±0.2
17.8
10
18493
±0.13
3.8
3 MIN.
±0.1
1.8 BA
0.1 C
1)
Burr max. 0.4 allowed
1) On ECC modules only
Internet Data Sheet
Rev. 1.22, 2007-01 41
03292006-CXBY-V2JX
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table of Contents
Edition 2007-01
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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Internet Data Sheet