ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER General Description Features The ICS85311 is a low skew, high perfor- mance 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL HiPerClockSTM Fanout Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels.The ICS85311 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the ICS85311 ideal for those clock distribution applications demanding well defined performance and repeatability. * * * Two differential 2.5V/3.3V LVPECL / ECL outputs * * Maximum output frequency: 1GHz * * * * * Output skew: 15ps (maximum) * ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.465V * * 0C to 70C ambient operating temperature ICS Block Diagram CLK Pulldown nCLK Pullup One CLK, nCLK input pair CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input Part-to-part skew: 100ps (maximum) Propagation delay: 1.4ns (maximum) Additive phase jitter, RMS: 0.14ps (typical), 3.3V LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment Q0 nQ0 Q0 nQ0 Q1 nQ1 Q1 nQ1 1 2 3 4 8 7 6 5 VCC CLK nCLK VEE ICS85311 8-Lead SOIC 3.90mm x 4.903mm x 1.37mm package body M Package Top View IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER 1 ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 2 Q0, nQ0 Output Differential output pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5 VEE Power Negative supply pin. 6 nCLK Input Pullup 7 CLK Input Pulldown 8 VCC Power Inverting differential clock input. Non-inverting differential clock input. Positive supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER Test Conditions 2 Minimum Typical Maximum Units ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Storage Temperature, TSTG -65C to 150C Package Thermal Impedance, JA 112C/W (0 lfpm) DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VCC = 3.3V5% or 2.5V5%, VEE = 0V, TA = 0C to 70C Symbol Parameter Test Conditions VCC Positive Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 2.375 2.5 2.625 V 25 mA Maximum Units Table 3B. Differential DC Characteristics, VCC = 3.3V5% or 2.5V5%, VEE = 0V, TA = 0C to 70C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Cureent VPP Peak-to-Peak Input Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical nCLK VCC = VIN = 3.465V or 2.625V 5 A CLK VCC = VIN = 3.465V or 2.625V 150 A nCLK VCC = 3.465V or 2.625V, VIN = 0V -150 A CLK VCC = 3.465V or 2.625V, VIN = 0V -5 A 0.15 1.3 V VEE + 0.5 VCC - 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER 3 ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Table 3C. LVPECL DC Characteristics, VCC = 3.3V5% or 2.5V5%, VEE = 0V, TA = 0C to 70C Symbol Parameter VOH Output High Current; NOTE 1 VOL Output Low Current; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCC - 1.4 VCC - 0.9 V VCC - 2.0 VCC - 1.7 V 0.65 1.0 V NOTE1: Outputs terminated with 50 to VCC - 2V. AC Electrical Characteristics Table 4A. AC Characteristics, VCC = 3.3V5%, VEE = 0V, TA = 0C to 70C Symbol Parameter Test Conditions Minimum 0.9 Typical Maximum Units 1 GHz 1.4 ns fMAX Maximum Output Frequency tPD Propagation Delay; NOTE 1 1GHz tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 156.25MHz, Integration Range (12kHz - 20MHz) tsk(o) Output Skew; NOTE 2, 4 15 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 100 ps tR / tF Output Rise/Fall Time 300 700 ps odc Output Duty Cycle 48 52 % 20% to 80% @ 50MHz 0.14 ps NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters are measured 500MHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. Table 4B. AC Characteristics, VCC = 2.5V5%, VEE = 0V, TA = 0C to 70C Symbol Parameter Test Conditions Minimum fMAX Maximum Output Frequency tPD Propagation Delay; NOTE 1 1GHz 0.9 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 156.25MHz, Integration Range (12kHz - 20MHz) tsk(o) Output Skew; NOTE 2, 4 15 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 100 ps tR / tF Output Rise/Fall Time 300 700 ps odc Output Duty Cycle 48 52 % 20% to 80% @ 50MHz Typical Maximum Units 1 GHz 1.4 ns 0.135 ps See Table 5A for NOTES. IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER 4 ICS85311AM REV. D OCTOBER 22, 2008