16-Bit, 15 MSPS, Module Data Acquisition Solution ADAQ23875 Preliminary Technical Data FEATURES GENERAL DESCRIPTION The ADAQ23875 is a precision, high speed, Module(R) data acquisition solution that reduces the development cycle of a precision measurement systems by transferring the design burden of component selection, optimization, and layout from designer to the device. Using System-in-Package (SIP) technology, the ADAQ23875 reduces end system component count by combining multiple common signal processing and conditioning blocks in a single device, including a low noise, fully differential ADC driver, a stable reference buffer, and a high speed, 16-bit, 15 MSPS successive approximation register (SAR) ADC. The ADAQ23875 also incorporates the critical passive components with superior matching and drift characteristics using Analog Devices, Inc., iPassive(R) technology to minimize temperature dependent error sources and to offer optimized performance. The fast settling of the ADC driver stage and no latency of the SAR ADC provide a unique solution for high channel count multiplexed signal chain architectures and control loop applications. The small footprint, 9 mm x 9 mm BGA package enables smaller form factor instruments without sacrificing any performance. The system integration solves many design challenges while the device still provides the flexibility of a configurable ADC driver feedback loop to allow gain or attenuation adjustments as well as fully differential or single-ended to differential input. A single 5 V supply operation is possible while achieving optimum performance from the device. The ADAQ23875 features a serial LVDS digital interface with one-lane or two-lane output modes, allowing the user to optimize the interface data rate for each application. The specified operation of the Module is from -40C to +85C. Integrated fully differential ADC driver with signal scaling Wide input common range High common-mode rejection Single-ended to differential conversion 2.048 V input range with 4.096 V REFBUF Critical passive components 0.005% precision matched resistor array for FDA 9 mm x 9 mm, 0.8 mm pitch, 100-ball BGA package 2.5x footprint reduction versus discrete solution Low power, dynamic power scaling, power-down mode 143 mW typical at 15 MSPS Throughput: 15 MSPS, no pipeline delay INL: 0.4 LSB typical, 1 LSB maximum SINAD: 89 dB typical at 1 kHz THD: -119 dB at 1 kHz, -100 dB at 500 kHz Gain error: 0.005% typical Gain error drift: 1 ppm/C typical On-board reference buffer with VCM generation Serial LVDS interface Wide operating temperature range: -40C to +85C APPLICATIONS ATE Data acquisition Hardware in the Loop (HiL) Power analyzers Non-destructive test (acoustic emissions) Mass spectrometry Travelling-wave fault location Medical imaging and instruments FUNCTIONAL BLOCK DIAGRAM VS+ +4V EXAMPLE 2 +1.024V +4V -1.024V REFIN VCMO REFBUF VDD EXAMPLE 3 15k 2.048V REFERENCE IN+ IN- +4V 0.5 2 10F 2.2F 0.1F 0V 0V +1.024V -1V -1.024V +1.024V 0V -1.024V IN+ IN- IN- IN+ 550 1.3pF VCMO 550 1.3pF 0.1F 1.1k 24.9 82pF 16-BIT, 15MSPS ADC FDA 24.9 1.1k 82pF 0.1F IN+ IN- -1V ADAQ23875 -1V PDB_AMP VS- MODE GND PDB_ADC VIO CNV+, CNV- DA+/DA-, DB+/DB-, DCO+, DCO- CLK+, CLK- SERIAL LVOS INTERFACE 25390-001 EXAMPLE 1 Figure 1. ADAQ23875 Configured for Gain = 2, 2.048 V Differential Input Range Rev. PrH Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADAQ23875 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 12 Applications ...................................................................................... 1 Circuit Information ................................................................... 12 Functional Block Diagram .............................................................. 1 Transfer Function ...................................................................... 12 Specifications .................................................................................... 3 Applications Information ............................................................. 13 Timing Specifications .................................................................. 5 Typical Application Diagram ................................................... 13 Absolute Maximum Ratings ........................................................... 7 Voltage Reference Input............................................................ 14 Thermal Resistance ...................................................................... 7 Common-Mode Output ............................................................ 14 Electrostatic Discharge (ESD) Ratings ...................................... 7 Power Supply .............................................................................. 14 ESD Caution.................................................................................. 7 Digital Interface .............................................................................. 15 Pin Configuration and Function Descriptions ............................ 8 Board Layout............................................................................... 17 Typical Performance Characteristics ........................................... 10 Outline Dimensions ....................................................................... 18 Terminology .................................................................................... 11 Rev. PrH | Page 2 of 18 Preliminary Technical Data ADAQ23875 SPECIFICATIONS VDD = 5 V 5%, VS+ = 5 V 5%, VS- = -1 V 5%, VS- = 0 V 1 (95% of VIN), VIO = 2.375 V to 2.625 V, REFBUF = 4.096 V, 15 MSPS, gain =2, all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter RESOLUTION ANALOG Input Impedance, ZIN Input Capacitance Differential Input Voltage Range, VIN3 THROUGHPUT Complete Cycle Conversion Time Acquisition Phase 4 Throughput Rate 5 Transient Response 6 DC ACCURACY No Missing Codes Integral Linearity Error Test Conditions/Comments VIN = 4.096 V p-p Single-ended to differential configuration Differential configuration IN1+, IN1- Gain = 2, VIN = 4.096 V p-p Signal-to-Noise + Distortion (SINAD) Total Harmonic Distortion Spurious-Free Dynamic Range -3 dB Input Bandwidth, RC Filter Aperture Delay 9 Aperture Jitter9 -2.048 Max +2.048 58 tCYC - 39 0 Full-scale step Single ended and differential configuration 63 15 52 16 -1 -1 Transition Noise Gain Error Power Supply Rejection Ratio (PSRR) Positive Negative 1/f Noise 7 Input Current Noise AC ACCURACY 8 Dynamic Range Total RMS Noise Signal-to-Noise Ratio Typ 550 1100 TBD 66.6 54 Differential Linearity Error Gain Error Drift Offset Error Offset Error Drift Common Mode Rejection Ratio (CMRR), Input Referred Min 18 -0.045 Bits LSB 0.2 +1 LSB 0.73 0.005 +0.045 LSBRMS %FS TBD 106 Rev. PrH | Page 3 of 18 TBD 87.5 87.3 ns ns ns MSPS ns +1 1 Bandwidth = 0.1 Hz to 10 Hz f = 100 kHz Single ended and differential configuration fIN = 1 kHz, -60 dB input All Gains fIN = 1 kHz fIN = 100 kHz fIN = 500 kHz fIN = 1 MHz fIN = 1 kHz fIN = 100 kHz fIN = 500 kHz fIN = 1 MHz fIN = 1 kHz fIN = 100 kHz fIN = 500 kHz fIN = 1 MHz fIN = 1 kHz pF V 0.4 -1.5 VICM/VOSDIFF Unit 2 Bits TBD +1.5 TBD ppm/C mV ppm/C dB 106 106 TBD 1 dB dB V p-p pA/Hz 90 91.6 89.3 88.5 88 87.5 89 88 87.5 87 -119 -111 -100 -80 114 136 0 0.25 dB VRMS dB dB dB dB dB dB dB dB dB dB dB dB dB MHz ns psRMS ADAQ23875 Parameter REFERENCE REFIN, Internal Reference Output Voltage Temperature Coefficient Output Impedance Line Regulation Input Voltage Range REFBUF, Reference Buffer Output Voltage Input Voltage Range Load Current VCMO Common-Mode Output Output Impedance DIGITAL INPUTS Logic Levels Input Low Voltage, VIL Input High Voltage, VIH Digital Input Current Input Pin Capacitance CNV+/CNV- and CLK+/CLK- (LVDS Clock Input) Differential Input Voltage, VID Common Mode Input Voltage, VICM DCO+/DCO-, DA+/DA-, DB+/DB- (LVDS Outputs) VOD, Differential Output Voltage VOS, Common Mode Output Voltage POWER-DOWN MODE ADC Driver (PDB_AMP)/ ADC (PDB_ADC) Low High Turn-On Time POWER REQUIREMENTS VDD VS+ VS- VIO Total Standby Current 11, 12 ADAQ23875 Current Draw VDD VS+/VS- VIO ADAQ23875 Power Dissipation VDD VS+/VS- VIO Total Preliminary Technical Data Test Conditions/Comments Min Typ Max Unit 2 IOUT = 0 A 2.028 2.048 2.068 V 20 2.028 4.056 5 15 0.3 2.048 4.096 ppm/C k mV/V V V VDD = 4.75 V to 5.25 V REFIN overdriven REFIN = 2.048 V 2.068 4.136 REFBUF overdriven 10 REFBUF = 4.096 V (REFBUF overdriven) REFBUF = 4.096 V (REFBUF overdriven) 4.056 4.096 1.6 0.5 4.136 1.8 V mA mA REFBUF = 4.096 V, IOUT = 0 A -1 mA < IOUT < +1 mA 2.028 2.048 15 2.028 V 0.6 V V A pF VIO = 2.5 V VIO = 2.5 V VIN = 0 V to 2.5 V 1.7 -10 +10 3 100 differential load 100 differential load 175 0.8 350 1.25 650 1.7 mV V 247 1.125 350 1.25 454 1.375 mV V <1 >1.7 TBD TBD V V s 5 5 0 2.5 45 0.1 5.25 VS- + 10 +0.1 2.625 52 0.4 V V V V mA A 3.8 4 40 4.1 5.5 42 mA mA mA 19 24 100 143 21.53 33 110.25 164.78 mW mW mW mW Power-down mode Enabled, normal operation Specified performance 4.75 3 VS+ - 10 2.375 Static, all devices enabled Static, all devices disabled VDD = 5 V, VS+ = 5 V, VS- = 0 V Gain = 2 One-Lane mode 13 Rev. PrH | Page 4 of 18 Preliminary Technical Data Parameter TEMPERATURE RANGE Specified Performance ADAQ23875 Test Conditions/Comments Min TMIN to TMAX -40 Typ Max Unit 2 +85 C For gain = 2, limit the differential input range, VIN, to 95% to allow enough footroom for the ADC driver with VS- = 0 V to achieve the above specified performance. The LSB unit means least significant bit. The weight of the LSB, referred to input, changes depending on the input voltage range. The differential input ranges, VIN should be within allowed input common-mode range as per Figure 3 to Figure 7and is dependent on the VS+/VS- supply rails used. 4 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADAQ23875 running at a throughput rate of 15 MSPS. 5 A throughput rate of 15 MSPS can only be achieved with a minimum SCK rate of TBD MHz. 6 Transient response is the time required for the ADAQ23875 to acquire a full-scale input step to within 1 LSB accuracy. Guaranteed by design, not subject to test. 7 See the 1/f noise plot in Figure TBD. 8 All ac specifications expressed in decibels are referenced to the full-scale input range (FSR) and are tested with an input signal at 1 dB below full scale, unless otherwise specified. 9 Guaranteed by design, not subject to test. 10 When REFBUF is overdriven, the internal reference buffer must be turned off by setting REFIN = 0 V. Refer to the Voltage Reference Input section. 11 With all digital inputs forced to VIO or GND as required. 12 During the acquisition phase. 12 In two-lane mode, the VIO power dissipation is about 10 mW higher than one-lane mode. 1 2 3 TIMING SPECIFICATIONS VDD = 5 V 5%, VS+ = 5 V 5%, VS- = -1 V 5%, VS- = 0 V1 (95% of VIN), VIO = 2.375 V to 2.625 V, REFBUF = 4.096 V, 15 MSPS, gain = 0.37, 0.73, 0.87, 1.38, 2.25, all specifications TMIN to TMAX, unless otherwise noted. Table 2. Digital Interface Timing Parameter Sampling Frequency Conversion Time--CNV Rising Edge to Data Available Acquisition Phase Time Between Conversions CNV High Time CNV Low Time CNV to First CLK from the Same Conversion CNV to First CLK from the Previous Conversion CLK TO DCO Delay SCK Low Time SCK High Time CLK to DA/DB Delay DCO to DA/DB skew Sampling Delay Time Sampling Delay Jitter Symbol fSMPL tCONV tACQ tCYC tCNVH tCNVL tFIRSTCLK tLASTCLK tCLKDCO tSCKL tSCKH tCLKD tSKEW tAP tJITTER Min 0.02 54 Typ 58 tCYC -39 66.6 5 8 65 0.7 1.25 1.25 0.7 -200 Max 15 63 Unit MSPS ns ns ns ns ns ns ns ns ns ns ns ns ns ns 50,000 1.3 1.3 0 0 0.25 49 2.3 2.3 200 Timing Diagram SAMPLE N tAP SAMPLE N + 1 ANALOG INPUT tACQ INPUT ACQUISITION tCNVH CNV - INPUT ACQUISITION tCYC CNV+ tFIRSTCLK tCONV CLK+ tLASTCLK 1 2 3 4 5 6 7 8 CLK- DCO+ DCO- DA+ D5 D4 D3 D2 D1 D0 LOGIC 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LOGIC 0 D15 D14 D13 D12 D11 D10 D9 D8 OUTPUT DATA FROM SAMPLE N - 1 OUTPUT DATA FROM SAMPLE N Figure 2. One-Lane Output Mode Rev. PrH | Page 5 of 18 OUTPUT DATA FROM SAMPLE N + 1 D7 D6 D5 25390-002 D6 DA- ADAQ23875 Preliminary Technical Data SAMPLE N tAP SAMPLE N + 1 ANALOG INPUT tACQ INPUT ACQUISITION INPUT ACQUISITION tCYC CLV+ tCNVH CLV- tFIRSTCLK tLASTCLK tCONV CLK+ 1 2 3 4 CLK- DCO+ DCO- DA+ D13 D11 D9 D7 D5 D3 D1 LOGIC 0 D15 D13 D11 D9 D7 D5 D3 D1 LOGIC 0 D15 D7 D5 D3 D1 D12 D10 D8 D6 D4 D2 D0 LOGIC 0 D14 D12 D10 D8 D6 D4 D2 D0 LOGIC 0 D14 D6 D4 D2 D0 DA- OUTPUT DATA FROM SAMPLE N - 1 OUTPUT DATA FROM SAMPLE N + 1 OUTPUT DATA FROM SAMPLE N Figure 3. Two-Lane Output Mode CLK- tCLKH tCLKL CLK+ tCLKDCO tCLKDCO tCLKD tCLKD DCO- DCO+ DA- DA+ DB- 25390-004 DB- DB+ Figure 4. Data Output Timing Rev. PrH | Page 6 of 18 25390-003 DB+ Preliminary Technical Data ADAQ23875 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Analog Inputs IN1+, IN1- to GND Supply Voltage VDD to GND VIO to GND VS+ to VS- VS+ to GND VS- to GND REFBUF to GND REFIN to GND Digital Inputs to GND Storage Temperature Range Junction Temperature Lead Temperature Soldering 1 Rating -12 V to +12 V or 10 mA1 6V 2.8 V 11 V -0.3 V to +11 V -11 V to +0.3 V -0.3 V to VDD + 0.3 V -0.3 V to +2.8 V -0.3 V to VIO + 0.3 V -65C to +150C 150C 260C reflow as per JEDEC J-STD-020 Whichever occurs first. Current condition tested over a 10 ms time interval. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Table 4. Thermal Resistance Package Type1 BC-100-7 JA2 48.4 JC3 35.1 Unit C/W Test Condition 1: thermal impedance simulated values are based on use of 2S2P JEDEC PCB. 2 JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. 3 JC is the junction to case thermal resistance. 1 ELECTROSTATIC DISCHARGE (ESD) RATINGS The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDDEC JS-001. Field induced charged device model (FICDM) per ANSI/ESDA/JEDEC JS-002. Table 5. ADAQ23875, 100-Ball CSP_BGA ESD Model HBM FICDM ESD CAUTION Rev. PrH | Page 7 of 18 Withstand Threshold (V) 1250 750 ADAQ23875 Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A1 BALL CORNER 1 2 3 4 5 6 7 8 9 10 A B C D E F G H 25390-005 J K Figure 5. 100-Ball CSP BGA Top View Table 6. 100-Ball CSP BGA Pin Configuration A B C D E F G H J K 1 GND PDB_AMP GND GND GND NC GND VS+ VS- GND 2 IN1- IN1- MODE GND GND NC GND GND GND GND 3 IN1+ IN1+ GND GND GND GND GND GND REFBUF REFIN 4 GND GND VS+ GND VS+ GND GND GND REFBUF GND 5 GND GND VS- GND GND GND GND GND GND PDB_ADC 6 GND GND GND VCMO GND GND GND GND GND VDD 7 GND GND GND GND GND GND GND GND GND TESTPAT 8 VIO TWOLANES GND GND GND GND GND GND GND DB- 9 GND GND GND GND GND GND GND GND GND DB+ 10 CNV+ CNV- GND CLK+ CLK- GND DCO+ DCO- DA+ DA- Table 7. Pin Function Descriptions Pin No. A1, A4, A5, A6, A7, A9, B4, B5, B6, B7, B9, C1, C3, C6, C7, C8, C9, C10, D1, D2, D3, D4, D5, D7, D8, D9, E1, E2, E3, E5, E6, E7, E8, E9, F3, F4, F5, F6, F7, F8, F9, F10, G1, G2, G3, G4, G5, G6, G7, G8, G9, H2, H3, H4, H5, H6, H7, H8, H9, J2,J5, J6, J7, J8, J9, K1, K2, K4 A2, B2 A3, B3 A8 Mnemonic GND Type 1 P Description Power Supply Ground. IN1- IN1+ VIO AI AI P A10 CNV+ DI B1 PDB_AMP DI B8 TWOLANES DI B10 CNV- DI Negative Input of Fully Differential ADC Driver Connected to 550 Resistor. Positive Input of Fully Differential ADC Driver Connected to 550 Resistor. 2.5 V Analog and Output Power Supply. The range of VIO is 2.375 V to 2.625 V. Bypass this pin to GND with an at least 2.2 F (0402, X5R) ceramic capacitor. Conversion Start LVDS Input. A rising edge on CNV+ puts the internal sample and hold in hold mode and starts a conversion cycle. CNV+ can be also driven with 2.5 V CMOS signal if CNV- is connected to GND. Active Low. Connect this pin to GND to power down the fully differential ADC driver. Otherwise, connect this pin to VS+. Digital Input that Enables Two-Lane Output Mode. When TWOLANES is connected high (two-lane output mode), the ADAQ23875 outputs two bits at a time on DA-/DA+ and DB-/DB+. When TWOLANES is low (one-lane output mode), the ADAQ23875 outputs one bit at a time on DA-/DA+, and DB-/DB+ are disabled. Logic levels are determined by VIO. Conversion Start LVDS Input. A rising edge on CNV+ puts the internal sample and hold into the hold mode and starts a conversion cycle. CNV+ can be also driven with 2.5 V CMOS signal if CNV- is connected to GND. Rev. PrH | Page 8 of 18 Preliminary Technical Data ADAQ23875 Pin No. C2 Mnemonic MODE Type 1 DI C4, E4, H1 VS+ P C5, J1 VS- P D6 D10 VCMO CLK+ AO DI E10 CLK- DI F1, F2 G10 NC DCO+ DO H10 DCO- DO J3, J4 REFBUF AO J10 DA+ DO K3 REFIN P K5 PDB_ADC DI K6 VDD P K7 TESTPAT DI K8 DB- DO K9 DB+ DO K10 DA- DO 1 Description Power Mode for Fully Differential Amplifier. Connect this pin to VS+ for full performance. Connect this pin to GND for power-down mode. Differential Amplifier and Reference Buffer Positive Supply. Bypass this pin to GND with an at least 2.2 F (0402, X5R) ceramic capacitor. Differential Amplifier Negative Supply. Bypass this pin to GND with an at least 2.2 F (0402, X5R) ceramic capacitor. Differential Amplifier Output Common-Mode Voltage. Nominally REFBUF/2. LVDS Clock Input. This is an externally applied clock that serially shifts out the conversion result. LVDS Clock Input. This is an externally applied clock that serially shifts out the conversion result. Do Not Connect. LVDS Data Clock Output. This is an echoed version of CLK+/CLK- that can be used to latch the data outputs. LVDS Data Clock Output. This is an echoed version of CLK+/CLK- that can be used to latch the data outputs. Reference Buffer Output Voltage. As a required component of SAR architecture, a 10 F ceramic bypass capacitor is already laid out within the ADAQ23875 between REFBUF and GND. Therefore, adding a second, smaller capacitor in parallel with the 10 F capacitor may degrade performance and is not recommended. Serial LVDS Data Output. In one-lane output mode, DB-/DB+ are not used and their LVDS driver is disabled to reduce power consumption. Internal Reference Output/Reference Buffer Input. The output voltage of the internal reference, nominally 2.048 V, is output on this pin. An external reference can be applied to REFIN if a more accurate reference is required. If the internal reference buffer is not used, connect REFIN to GND to power down the buffer and connect an external buffered reference to REFBUF. Digital Input that Enables the Power-Down Mode. When PDB_ADC is low, an internal ADC core enters power-down mode, and all circuitry (including the LVDS interface) is shutdown. When PDB_ADC is high, the part operates normally. Logic levels are determined by VIO. 5 V Analog Power Supply. The range of VDD is 4.75 V to 5.25 V. Short the two pins together and bypass them to GND with at least 2.2 F (0402, X5R) ceramic capacitors. Digital Input that Forces the LVDS Data Outputs to be a Test Pattern. When TESTPAT is high, the digital outputs are test pattern. When TESTPAT is low, the digital outputs are the ADAQ23875 conversion result. Logic levels are determined by VIO. Serial LVDS Data Output. In one-lane output mode, DA-/DA+ are not used and their LVDS driver is disabled to reduce power consumption. Serial LVDS Data Outputs. In one-lane output mode, DA-/DA+ are not used and their LVDS driver is disabled to reduce power consumption. Serial LVDS Data Outputs. In one-lane output mode, DB-/DB+ are not used and their LVDS driver is disabled to reduce power consumption. AI is analog input, AO is analog output, P is power, DI is digital input, NC is no connection, and DO is digital output. Rev. PrH | Page 9 of 18 ADAQ23875 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS 0.8 0.6 0.6 INTEGRAL NONLINEARITY (LSB) 0.8 0.4 0.2 0 -0.2 -0.4 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 2048 12048 22048 32048 42048 52048 62048 CODE -0.8 2048 12048 22048 32048 42048 Figure 6. DNL vs. Code, fS = 15 MSPS 0 ADD DYNAMIC RANGE = 90dB -20 -40 -40 NOISE FIGURE (dB) -20 -100 -120 -140 -80 -100 -120 -140 -160 -200 -200 10k 100k 1M 7.5M FREQUENCY (Hz) 25390-007 -160 1k SNR = 88.74dB SINAD = 88.72dB THD = -112dB SFDR = 112.63dB 100 1k 10k 100k 1M Figure 10. FFT, fIN = 1 kHz, 13.8 MSPS, -0.5 dBFS, REFBUF = 4.096 V Figure 7. FFT, fS = 15 MSPS, IN1+/IN1- Shorted to GND 9 6 +3.7V, +5V -3.7V, +5V 3 TBD Vs+ = 5V, Vs- = 0V Vs+ = 5V, Vs- = -5V 0 -6 -9 -4.5 -3.7V, -2.2V +3.7V, -2.2V -3.7V, -5V -3.0 +3.7V, -5V -1.5 0 1.5 ADC DRIVER OUTPUT VOLTAGE (V) 3.0 4.5 25390-008 -3 6.9M FREQUENCY (Hz) Figure 8. Input Common-Mode Voltage vs. ADC Driver Output Voltage, Gain = 2, 1.024 V Differential Input Rev. PrH | Page 10 of 18 Figure 11. 25390-010 -80 100 INPUT COMMON-MODE VOLTAGE (V) 62048 Figure 9. INL vs. Code, fS = 15 MSPS 0 AMPLITUDE (dB OF FULL SCALE) 52048 CODES 25390-009 -0.6 25390-006 DIFFERENTIAL NONLINEARITY (LSB) VDD = 5 V 5%, VS+ = 5 V 5%, VS- = -1 V 5%, VS- = 0 V1 (95% of VIN), VIO = 2.375 V to 2.625 V, REFBUF = 4.096 V, 15 MSPS, gain = 2, all specifications TMIN to TMAX, unless otherwise noted. Preliminary Technical Data ADAQ23875 TERMINOLOGY Integral Nonlinearity (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 11/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line Differential Nonlinearity (DNL) In an ideal Module, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal midscale voltage, 0 V, and the actual voltage producing the midscale output code, 0 LSB. Gain Error The first transition (from 100 ... 00 to 100 ... 01) occurs at a level 1/2 LSB above nominal negative full scale. The last transition (from 011 ... 10 to 011 ... 11) occurs for an analog voltage 11/2 LSB below the nominal full scale. The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. The value for dynamic range is expressed in decibels. It is measured with a signal at -60 dBFS so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the Module to acquire a full-scale input step to 1 LSB accuracy. Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the Module output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the input common-mode voltage of frequency, f. CMRR (dB) = 10log(PModule_IN/PModule _OUT) Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: ENOB is expressed in bits. where: PModule_IN is the common-mode power at the frequency, f, applied to the inputs. PModule _OUT is the power at the frequency, f, in the Module output. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the Module output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the Module VDD supply of frequency, f. ENOB = (SINADdB - 1.76)/6.02 PSRR (dB) = 10 log(PVDD_IN/ PModule _OUT) where: PVDD_IN is the power at the frequency, f, at the VDD pin. PModule _OUT is the power at the frequency, f, in the Module output. Rev. PrH | Page 11 of 18 ADAQ23875 Preliminary Technical Data THEORY OF OPERATION REFIN VS+ 0.1F 15k 2.048V REFERENCE REFBUF VDD VCMO 0.1F 0.5 2 10F 1.0F 0.1F IN- IN+ 550 1.3pF VCMO 550 1.3pF 0.1F 1.1k 24.9 82pF 24.9 1.1k CNV+, CNV- DA+/DA-, DB+/DB-, DCO+, DCO- CLK+, CLK- 16-BIT, 15MSPS ADC HS FDA 82pF 0.1F GND MODE SERIAL LVOS INTERFACE 25390-012 ADAQ23875 PDB_AMP VS- VIO PDB_ADC Figure 12. ADAQ23875 Module Simplified Block Diagram TRANSFER FUNCTION The ADAQ23875 Module digitizes the full-scale voltage of 2x REFBUF into 216 levels, resulting in an LSB size of 125 V with REFBUF = 4.096 V. The output data is in twos complement format. The ideal transfer function is shown in Figure 13. The ideal offset binary transfer function can be obtained from the twos complement transfer function by inverting the most significant bit (MSB) of each output code. 011...111 011...110 011...101 100...010 100...001 100...000 -FSR -FSR + 1 LSB +FSR - 1 LSB +FSR - 1.5 LSB -FSR + 0.5 LSB ANALOG INPUT 25390-013 The ADAQ23875 is a precision, high speed Module data acquisition solution that reduces the development cycle of a precision measurement systems by transferring the design burden of component selection, optimization, and layout from designer to the device. The ADAQ23875 reduces end system component count by combining multiple common signal processing and conditioning blocks in a single device including a low noise, fully differential ADC driver, a stable reference buffer, and a high speed, 16-bit, 15 MSPS successive approximation register (SAR) ADC. It also incorporates the Analog Devices proprietary iPASSIVESTM technology components necessary for optimum performance. The superior matching and drift characteristics of the resistors minimizes temperature dependent error sources. The ADAQ23875 includes a precision internal 2.048 V reference as well as an internal reference buffer. The ADAQ23875 also has a high speed serial LVDS interface that can output one or two bits at a time. The fast 15 MSPS throughput with no pipeline latency makes the ADAQ23875 ideally suited for a wide variety of high speed applications. The ADAQ23875 dissipates only 185 mW at 15 MSPS and has a power-down mode to reduce the power consumption to TBD W during inactive periods. ADC CODE (TWOS COMPLEMENT) CIRCUIT INFORMATION Figure 13. ADAQ23875 Transfer Function (FSR Is Full-Scale Range) Table 8. Output Codes and Ideal Input Voltages Description FSR - 1 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FSR + 1 LSB -FSR Rev. PrH | Page 12 of 18 Inputs Voltages (32,767 x VREF)/(32,768 x gain) VREF/(32,768 x gain) Digital Output Code (Twos Complement, Hex.) 0x7FFF 0x0001 0V -VREF/(32,768 x gain) 0x0000 0xFFFF -(32,767 x VREF)/(32,768 x gain) -VREF x gain 0x8001 0x8000 Preliminary Technical Data ADAQ23875 APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAM typical application example of a single-ended signal applied to one of the ADAQ23875 inputs for a given gain with a fixed common-mode voltage of 0 V. Figure 14 shows the typical application examples of differential signals applied to each of the ADAQ23875 inputs for a given gain with varying common-mode voltage. Figure 15 shows the VS+ EXAMPLE 1 +1.024V +4V -1.024V VCMO REFIN REFBUF VDD EXAMPLE 3 0.5 15k 2.048V REFERENCE IN+ IN- +4V 2 10F 0.1F 0.1F 0V +1.024V 0V -1.024V IN+ IN- IN- IN+ 550 VCMO 550 16-BIT, 15MSPS ADC HS FDA 24.9 1.1k 1.3pF 82pF 24.9 82pF 0.1F IN+ IN- -1V ADAQ23875 -1V PDB_AMP VS- GND MODE VIO CNV+, CNV- DA+/DA-, DB+/DB-, DCO+, DCO- CLK+, CLK- SERIAL LVOS INTERFACE 25390-014 +1.024V -1V -1.024V 0V 0.1F 1.1k 1.3pF PDB_ADC Figure 14. ADAQ23875 Differential Input Configuration with Gain = 2, 2.048 V Input Range VS+ REFIN 15k 2.048V REFERENCE REFBUF VDD 0.5 2 10F 0.1F 0.1F IN+ +1.024V IN- 550 1.3pF 0V 550 1.3pF 0.1F 1.1k VCMO IN+ -1.024V VCMO 24.9 82pF 16-BIT, 15MSPS ADC HS FDA 24.9 1.1k 82pF 0.1F ADAQ23875 PDB_AMP VS- MODE GND PDB_ADC Figure 15. ADAQ23875 Single-Ended Input Configuration with Gain = 2, 2.048 V Input Range Rev. PrH | Page 13 of 18 VIO CNV+, CNV- DA+/DA-, DB+/DB-, DCO+, DCO- CLK+, CLK- SERIAL LVOS INTERFACE 25390-015 +4V EXAMPLE 2 ADAQ23875 Preliminary Technical Data VOLTAGE REFERENCE INPUT COMMON-MODE OUTPUT The ADAQ23875 Module has an internal low noise, low drift (20 ppm/C), band gap reference connected to REFIN. An internal reference buffer gains the REFIN voltage by 2x to 4.096 V at the REFBUF pin. The voltage difference between REFBUF and GND determines the full-scale input range of the ADAQ23875. The reference and reference buffer can also be externally driven if desired. Also housed in the ADAQ23875 is a 10 F decoupling capacitor between REFBUF and GND that is ideally laid out within the device. This decoupling capacitor is a required component of the SAR architecture. Adding a second, smaller capacitor in parallel with the 10 F capacitor may degrade performance and is not recommended. The VCMO pin is an output that provides one half the voltage present on the REFBUF pin. This voltage is used to set the common mode of a differential amplifier driving the analog inputs. If VCMO is not used, it can be left floating, but the parasitic capacitance on the pin must be under 10 pF. Internal Reference with Internal Reference Buffer To use the internal reference and internal reference buffer, bypass REFIN pin to GND with a 0.1F ceramic capacitor. POWER SUPPLY The ADAQ23875 uses four power supplies: an internal ADC core supply (VDD), a digital input/output interface supply (VIO), a fully differential ADC driver positive supply (VS+), and a negative supply (VS-). Figure 18 shows the typical total power consumption including individual consumption for each of the VS+, VDD, and VIO supplies. It is recommended to bypass each of the supply pins (VDD, VIO, VS+, and VS-) with a 2.2 F (0402, X5R) ceramic decoupling capacitor connected to GND. See the Board Layout section. 180 If more accuracy and/or lower drift is desired, REFIN can be directly overdriven by an external 2.048 V reference as shown in Figure 16. Analog Devices offers a portfolio of high performance references designed to meet the needs of many applications. With its small size, low power, and high accuracy, the LTC6655-2.048 is well suited for use with the ADAQ23875 when overdriving the internal reference. The LTC6655-2.048 offers 0.025% (maximum) initial accuracy and 2 ppm/C (maximum) temperature coefficient for high precision applications. 160 POWER CONSUMPTION (mW) External Reference with Internal Reference Buffer 0.1F REFIN 25390-016 REFIN ADAQ23875 REFBUF REFBUF 25390-017 0.1F 2.5 5.0 7.5 10.0 12.5 15.0 Figure 18. IN1+, IN1- Connected to GND, VS+ = 5 V, VS- = -1 V, REFBUF = 4.096 V The internal reference buffer can also be overdriven with an external 4.096 V reference at REFBUF as shown in Figure 17. To do so, REFIN must be grounded to disable the reference buffer. The external reference must have a fast transient response and be able to drive the 0.5 mA to 1.6 mA load at the REFBUF pin. The LTC6655-4.096 is recommended when overdriving REFBUF. VOUT_F VOUT_S SHDN GND 40 FSAMPLE (MSPS) External Reference Buffer LTC6655-4.096 VS+ VDD VIO TOTAL POWER 60 0 Figure 16. Using the LTC6655-2.048 as an External Reference VIN 80 0 VOUT_S GND ADAQ23875 5V 100 Figure 17. Overdriving REFBUF Using the LTC6655-4.096 25390-018 SHDN VOUT_F 120 20 LTC6655-2.048 VIN 5V 140 Power Supply Sequencing The ADAQ23875 does not have any specific power supply sequencing requirements. The internal ADC core of ADAQ23875 has a power-on-reset (POR) circuit that resets the ADAQ23875 at initial power-up or whenever VDD drops well below the minimum values. After the supply voltage re-enters the nominal supply voltage range, the POR reinitializes the ADAQ23875. Power-Down Mode The power-down mode of fully differential ADC driver is asserted by applying a low logic level (GND) to the PDB_AMP pin to minimize the quiescent current consumed when the ADAQ23875 is not being used. When the PDB_AMP pin is connected to GND, the fully differential ADC driver output is high impedance. When PDB_ADC is low logic level, an internal ADC core enters power-down mode, and all circuitry (including the LVDS interface) is shut down. When PDB_AMP and PDB_ADC are connected to a high logic level, the ADAQ23875 operates normally. The logic levels for both the PDB_AMP and PDB_ADC pins are determined by VS+ and VIO, respectively. Rev. PrH | Page 14 of 18 Preliminary Technical Data ADAQ23875 DIGITAL INTERFACE The ADAQ23875 conversion is controlled by the CNV+ and CNV- inputs, which can be driven directly with an LVDS signal. Alternatively, the CNV+ pin can be driven with a 0 V to 2.5 V CMOS signal when CNV- is connected to GND. A rising edge on CNV+ samples the analog inputs and initiates a conversion. The pulse width of CNV+ should meet the tCNVH and tCNVL specifications in the timing table. ADAQ23875 FPGA CLK+ CLK- 100 DCO+ 100 DCO- DA+ After the ADAQ23875 is powered on, or exits power-down mode, conversion data is invalid for the first two conversion cycles. The subsequent conversion results are accurate as long as the time between conversions meets the tCYC specification. If the analog input signal has not completely settled when it is sampled, the ADAQ23875 noise performance is affected by jitter on the rising edge of CNV+. In this case, drive the rising edge of CNV+ with a clean, low jitter signal. Note that the ADAQ23875 is less sensitive to jitter on the falling edge of CNV+. In applications that are insensitive to jitter, CNV can be driven directly from an FPGA. 100 DA- 100 25390-019 DB+ OPTIONAL DB- Figure 19. Digital Output Interface to an FPGA One-Lane Output Mode A conversion is started by the rising edge of CNV+. When the conversion is complete, the most significant data bit is output on DA. Data is then ready to be shifted out by applying a burst of eight clock pulses to the CLK input. The data on DA is updated by every edge of CLK. An echoed version of CLK is output on DCO. The edges of DA and DCO are aligned, so DCO can be used to latch DA in the FPGA. The timing of a single conversion is shown in Figure 20 and Figure 21. Data must be clocked out after the current conversion is complete, and before the next conversion finishes. The valid time window for clocking out data is shown in Figure 22. Note that it is allowed to be still clocking out data when the next conversion begins. The ADAQ23875 has an internal clock that is trimmed to achieve a maximum conversion time of 63 ns. With a typical acquisition time of 27.7 ns, throughput performance of 15 MSPS is achieved. The ADAQ23875 has a serial LVDS digital interface that is easy to connect to an FPGA. Three LVDS pairs are required: CLK, DCO, and DA. A fourth LVDS pair, DB, is optional (see Figure 19). Route the LVDS signals on the PC board as 100 differential transmission lines and terminated at the receiver with 100 resistors. The optional LVDS output, DB, is enabled, and data is output two bits at a time on DA and DB. Enabling the DB output increases the supply current from VIO by about 3.6 mA. In two-lane mode, four clock pulses are required for CLK (see Figure 23). Two-Lane Output Mode At high sample rates, the required LVDS interface data rate can reach >400 Mbps. Most FPGAs can support this rate, but if a lower data rate is desired, the two-lane output mode can be used. When the TWOLANES input pin is connected high (VIO), the ADAQ23875 outputs two bits at a time on DA-/DA+ and DB-/DB+, as shown in Figure 23. CNV 1 2 3 4 5 6 7 8 CLK tCONV DA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 MSB Figure 20. Timing Diagram for a Single Conversion in One-Lane Mode Rev. PrH | Page 15 of 18 D1 D0 LSB 25390-020 DCO ADAQ23875 Preliminary Technical Data SAMPLE N tAP SAMPLE N + 1 ANALOG INPUT tACQ INPUT ACQUISITION tCYC tCNVH CNV - INPUT ACQUISITION CNV+ tFIRSTCLK tCONV CLK+ tLASTCLK 1 2 3 4 5 6 7 8 CLK- DCO+ DCO- DA+ D6 D5 D4 D3 D2 D1 LOGIC 0 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LOGIC 0 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 OUTPUT DATA FROM SAMPLE N - 1 OUTPUT DATA FROM SAMPLE N 25390-021 DA- OUTPUT DATA FROM SAMPLE N + 1 Figure 21. Timing Diagram for Multiple Conversions in One-Lane Output Mode CONVERSION N CONVERSION N + 1 CNV tFIRSTCLK tLASTCLK 1 2 3 4 5 6 7 8 25390-022 CLK TIME WINDOW FOR CLOCKING OUT CONVERSION N Figure 22. Valid Time Window for Clocking Out Data SAMPLE N tAP SAMPLE N + 1 ANALOG INPUT tACQ INPUT ACQUISITION INPUT ACQUISITION tCYC CLV+ tCNVH CLV- tFIRSTCLK tLASTCLK tCONV CLK+ 1 3 2 4 CLK- DCO+ DCO - DA+ D13 D11 D9 D7 D5 D3 D1 LOGIC 0 D15 D13 D11 D9 D7 D5 D3 D1 LOGIC 0 D15 D7 D5 D3 D1 D12 D10 D8 D6 D4 D2 D0 LOGIC 0 D14 D12 D10 D8 D6 D4 D2 D0 LOGIC 0 D14 D6 D4 D2 D0 DA- DB- OUTPUT DATA FROM SAMPLE N - 1 OUTPUT DATA FROM SAMPLE N Figure 23. Two-Lane Output Mode Rev. PrH | Page 16 of 18 OUTPUT DATA FROM SAMPLE N + 1 25390-023 DB+ Preliminary Technical Data ADAQ23875 Output Test Patterns The test pattern is enabled when the TESTPAT pin is brought high (VIO) to allow in-circuit testing of the digital interface of the ADAQ23875 and forces its LVDS data outputs to be a test pattern. The ADAQ23875 digital data outputs known values as a test pattern as follows: * * One-lane mode: 1010 0000 0111 1111 Two-lane mode: 1100 1100 0011 1111 When the TESTPAT pin connected low (GND), the ADAQ23875 digital data outputs the conversion results. BOARD LAYOUT The printed circuit board (PCB) layout is critical for preserving signal integrity and achieving the expected performance from the ADAQ23875. A multilayer board with an internal, clean ground plane in the first layer beneath the ADAQ23875 is recommended. Care must be taken with the placement of individual components and routing of various signals on the board. It is especially recommended to route input and output signals symmetrically. Solder the ground pins of the ADAQ23875 directly to the ground plane of the PCB using multiple vias. Remove the ground and power planes beneath the input and output pins of ADAQ23875 to avoid undesired parasitic capacitance. The sensitive analog and digital sections must be separated on PCB while keeping the power supply circuitry away from the analog signal path. Fast switching signals, such as CNV or CLK, and digital outputs DA, DB should not run near or cross over analog signal paths to prevent noise coupling to the ADAQ23875. Good quality ceramic bypass capacitors of at least 2.2 F (0402, X5R) must be placed between each of supply pins VDD, VIO, VS+, and VS- of the ADAQ23875 and GND to minimize EMI susceptibility and reduce the effect of glitches on the power supply lines. All the other required bypass capacitors are laid out within the ADAQ23875, saving extra board space and cost. Mechanical Stress Shift The mechanical stress of mounting a device to a board may cause subtle changes to the SNR and internal voltage reference. The best soldering method is to use IR reflow or convection soldering with a controlled temperature profile. Hand soldering with a heat gun or a soldering iron is not recommended Rev. PrH | Page 17 of 18 ADAQ23875 Preliminary Technical Data OUTLINE DIMENSIONS 100-Ball Chip Scale Package Ball Grid Array (BC-100-7) Dimensions shown in millimeters A1 BALL INDICATOR AREA 9.10 9.00 SQ 8.90 A1 BALL CORNER 10 9 8 7 6 5 4 3 2 1 A B C D 7.20 REF SQ E F G 0.80 BSC H J K TOP VIEW 2.368 2.268 2.168 DETAIL A SIDE VIEW 0.90 BSC 0.40 0.35 0.30 SEATING PLANE BOTTOM VIEW DETAIL A 1.65 REF 0.50 O 0.45 COPLANARITY 0.08 07-17-2019-A 0.40 Figure 24. 100-Ball, 9 mm x 9 mm Chip Scale Package Ball Grid Array [CSP_BGA] (c)2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR25390-10/20(PrA) Rev. PrH | Page 18 of 18