FUJITSU SEMICONDUCTOR DATA SHEET DS04-28215-2E ASSP For Video Applications CMOS 8-bit 140 MSPS A/D Converter MB40C318 DESCRIPTION MB40C318 is a high-speed A/D converter using a fast CMOS technology. FEATURES * * * * Resolution Linearity error Maximum conversion rate Power supply voltage : : : : * Clock input voltage range : * * * * * * : : : : : Digital input voltage range Digital output voltage range Analog input voltage range Analog input capacitance Power dissipation Additional features * Package : 8 bit 0.40% (standard) 140 MSPS (minimum) 3.3 V/5 V (standard: PECL clock input) 3.3 V (standard: PECL other than clock input) PECL level (140 MHz max differential input CLKEP, CLKEN) CMOS level (70 MHz max two-phase input CLKA, CLKB) CMOS level CMOS level compatible 0 to 3.0 V (2 Vp-p) 22 pF (standard) 300 mW (standard) Reference voltage generator circuit: VREFT = 3.0 V, VREFB = 1.0 V High impedance output, power down function 1:2 demultiplex output enable (RESET action enable) 1/2 deviding clock output Cross sampling at 70 MHz (two-phase CLK) enable (CLKA, CLKB) LQFP48 (7 mm x 7 mm, lead pitch 0.5 mm) PACKAGE 48-pin plastic LQFP (FPT-48P-M05) MB40C318 VR3 VREFT VRT AVDD AVSS DVDD CLKOA DVSS DA0 (LSB) DAI DA2 DA3 48 47 46 45 44 43 42 41 40 39 38 37 PIN ASSIGNMENT VR2 1 36 DA4 VR1 2 35 DA5 AVDD 3 34 DA6 AVSS 4 33 DA7 (MSB) VREFB 5 32 CLKEN VRB 6 31 CLKA AVSS 7 30 CLKB (TOP VIEW) 2 22 23 24 DB3 DB2 DB1 DB4 25 21 12 DB5 AVSS 20 DB0 (LSB) DB6 26 19 11 (MSB) DB7 CE 18 DVDDI DVSS 27 17 10 CLKOB CKSEL 16 RESET DVDD 28 15 9 DSEL AVDD 14 CLKEP OE 29 13 8 AVDD VINA MB40C318 PIN DESCRIPTION Pin No. Symbol Description 3, 9, 13, 45 AVDD Analog power supply (+3.3 V) 16, 43 DVDD Digital power supply (+3.3 V) 27 DVDDI Digital power supply for CLKEP/CLKEN (+5.0 V or +3.3 V) 4, 7, 12, 44 AVSS Analog power supply ground pin (0 V) 18, 41 DVSS Digital power supply ground pin (0 V) 33 to 40 DA7 to DA0 Digital output pin (Port A) DA7: MSB, DA0: LSB 19 to 26 DB7 to DB0 Digital output pin (Port B) DB7: MSB, DB0: LSB 11 CE Power down at CE input "H" (internal pull-up resistor) 14 OE Digital output (Both Port A, B) and clock output (CLKOA, CLKOB) are high impedance at OE input "H". 10 CKSEL 15 DSEL 28 RESET Dividing circuit reset input pin (See TIMING CHART 2, 3) 29 CLKEP Differential clock (positive-phase) input pin (max 140 MHz) 32 CLKEN Differential clock (negative-phase) input pin (max 140 MHz) 31 CLKA Two-phase clock (A ch) input pin (max 70 MHz) 30 CLKB Two-phase clock (B ch) input pin (max 70 MHz) 42 CLKOA Clock output pin (See TIMING CHART 1 to 4) 17 CLKOB Clock output pin (See TIMING CHART 1 to 4) 8 VINA Analog input pin Input range is VRT to VRB (0 V to 3.0 V: 2 Vp-p) 2 1 48 VR1 VR2 VR3 Reference 1/4 voltage output pin (Add 0.1 F for AVSS) Reference 1/2 voltage output pin (Add 0.1 F for AVSS) Reference 3/4 voltage output pin (Add 0.1 F for AVSS) 46 VRT Reference voltage input pin on top side 47 VREFT 6 VRB 5 VREFB Mode of operation setting input pin (Refer to MODE SETTING) PECL level CMOS level Reference voltage output pin By connecting to VRT, 0.9 x AVDD (.=. 3 V) is generated. Reference voltage input pin on bottom side Reference voltage output pin By connecting to VRB, 0.3 x AVDD (.=. 1 V) is generated. The values in parentheses are standard. PRECAUTIONS ON USE * Be sure to ground the pins of AVDD, DVDD, DVDDI, VRT, VRB, VR1, VR2, and VR3 via high-frequency capacitor. Place the high-frequency capacitor as close as possible to the pin. * To avoid generation of undesired current owing to indetermination of internal logic, set CE to "H" at powering on and input more than five clock pulses just after operation (CE: "H" "L"). 3 MB40C318 BLOCK DIAGRAM CKSEL DSEL VINA CLKOA DVDDI AVDD DVDD VREFT AVDD Mode setting VRT Timing circuit CLKA CLKEP CLKEN CLK select VR3 VR2 VR1 B ch CLKB A output buffer DA0 to DA7 B output buffer DB0 to DB7 Output selector FF A ch FF Timing circuit VRB AVDD AVSS RESET 4 CE CLKOB AVSS DVSS OE VREFB MB40C318 ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Input/output voltage Storage temperature Symbol Rating Unit Min. Max. AVDD, DVDD -0.3 +4.0 V DVDDI -0.3 +7.0 V VINA, VRT, VRB, VREFT, VREFB, VR1, VR2, VR3, CE, CKSEL -0.3 AVDD+0.3*1 V DA0 to DA7, DB0 to DB7, CLKOA, CLKOB, CLKA, CLKB, DSEL, OE, RESET -0.3 DVDD+0.3*1 V CLKEP, CLKEN -0.3 DVDDI+0.3*2 V TSTG -55 +125 C *1: Do not exceed +4.0 V. *2: Do not exceed +7.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 5 MB40C318 RECOMMENDED OPERATING CONDITIONS Parameter Power supply voltage Symbol Value Unit Min. Typ. Max. AVDD, DVDD 3.00 3.30 3.60 V DVDDI (5 V) 4.75 5.00 5.25 V DVDDI (3 V) 3.00 3.30 3.60 V Analog input voltage VINA VRB -- VRT V Analog reference voltage: T VRT -- -- 3.00 V Analog reference voltage: B VRB 0.00 -- -- V VRT - VRB 1.90 2.00 2.10 V CKSEL, CE AVDD - 0.5 -- -- V OE, DSEL, RESET, CLKA, CLKB DVDD - 0.5 -- -- V DVDDI - 1.1 -- DVDDI - 0.6 V DVDDI - 0.5 -- DVDDI V CKSEL, CE -- -- 0.5 V OE, DSEL, RESET, CLKA, CLKB -- -- 0.5 V DVDDI - 2.0 -- DVDDI - 1.45 V 2.3 -- DVDDI - 0.5 V 0.4 0.8 -- V 0.4 0.6 -- V IID -20 -- 5 A Differential clock frequency fCLKEP, fCLKEN 0.1 -- 140 MHz Two-phase clock frequency fCLKA, fCLKB 0.1 -- 70 MHz Minimum clock pulse width (differential) tWS+, tWS- 3.0 3.5 -- ns Minimum clock pulse width (two-phase) tWD+, tWD- 6.0 7.0 -- ns tr, tf -- 2.0 -- ns RESET signal setup time ts 1.5 -- -- ns RESET signal hold time th 1.5 -- -- ns Operating temperature range Ta -20 -- 70 C Analog reference voltage range Digital "H" level input voltage CLKEP, CLKEN (DVDDI = 5 V) VIHD CLKEP, CLKEN (DVDDI = 3.3 V) Digital "L" level input voltage CLKEP, CLKEN (DVDDI = 5 V) VILD CLKEP, CLKEN (DVDDI = 3.3 V) Digital input voltage range CLKEP, CLKEN (DVDDI = 5 V) CLKEP, CLKEN (DVDDI = 3.3 V) Digital input current Clock pulse rising/falling time VIHD - VILD WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 6 MB40C318 ELECTRICAL CHARACTERISTICS * DC Characteristics in Analog Section (AVDD = DVDD = 3.00 V to 3.60 V, DVDDI = 4.75 V to 5.25 V, Ta = -20C to +70C) Parameter Symbol Value Min. Typ. Max. Unit Resolution -- -- 8 -- bit Linearity error LE -- 0.40 0.6 % Differential linearity error DLE -- 0.20 0.36 % Analog input capacity CINA -- 22 -- pF Reference voltage: T VREFT 0.88 x AVDD 0.91 x AVDD 0.94 x AVDD V Reference voltage: B VREFB 0.27 x AVDD 0.3 x AVDD 0.33 x AVDD V IRB -15 -10 -- mA AIDD -- 60.0 100 mA DIDD -- 30.0 45 mA DIDDI -- 1 3 mA ISB -- 1 -- mA Reference current Analog supply current Digital supply current Standby current * DC Characteristics in Digital Section (AVDD = DVDD = 3.00 V to 3.60 V, DVDDI = 4.75 V to 5.25 V, Ta = -20C to +70C) Parameter Symbol Value Min. Typ. Max. Unit Digital "H" level output voltage VOHD DVDD - 0.4 -- DVDD V Digital "L" level output voltage VOLD -- -- 0.4 V Digital "H" level output current IOHD -400 -- -- A Digital "L" level output current IOLD -- -- 1.6 mA 7 MB40C318 * Switching Characteristics (AVDD = DVDD = 3.00 V to 3.60 V, DVDDI = 4.75 V to 5.25 V, Ta = -20C to +70C) Parameter Maximum conversion rate Typ. Max. 140 -- -- MSPS -- 3.5 -- ns -- 2.0 -- ns tpdS 4 8 11.5 ns tpdSO tWS+ + 4 tWS+ + 8 tWS+ + 11 ns tpdM1 4 7 11.5 ns tpdM1O T+4 T+7 T + 11 ns tpdM2 4 7 11.5 ns tpdM2O T+4 T+7 T + 11 ns tpdD 3 6 10.5 ns tpdDO tWD+ + 2 tWD+ + 6 tWD+ + 10 ns tAD Timing chart 4 Timing chart 1 Timing chart 2 Digital output delay time Timing chart 3 Timing chart 4 Unit Min. fS Timing chart 1 to 3 Aperture time Value Symbol DIGITAL OUTPUT BUFFER LOAD CIRCUIT To the measurement point Measurement point CL = 18 pF DVSS Note: CL includes a stray capacitance of a probe and a fixture. MODE SETTING 8 CKCEL DCEL Mode Timing Chart H H Differential CLK input-straight output mode Timing chart 1 H L Differential CLK input-demultiplex output (in-phase) mode Timing chart 2 L H Differential CLK input-demultiplex output (two-phase) mode Timing chart 3 L L Two-phase CLK input mode (CLKA, CLKB) Timing chart 4 MB40C318 TIMING CHART 1 Differential CLK input-straight output mode * * * * * * * CLKEP = CLKEN = 140 MHz (max) CLKA = CLKB = "L" (DVSS) CKSEL = "H" (AVDD) DSEL = "H" (DVDD) RESET = "H" (DVDD) CE = "L" (AVSS) OE = "L" (DVSS) tr N-1 VINA input VOHD DB0 to DB7 VOLD N+1 N N+2 N+3 N+4 tAD N-7 N-6 N+5 N+6 tpdS (max) tpdS (typ) tpdS (min) N-5 N-4 N-3 N-2 N-1 N+7 N DVDD - 0.4 V N+1 0.4 V ALL "L" fix tpdSO (max) tpdSO (typ) tpdSO (min) VOHD CLKOA VOLD VOHD CLKOB VOLD tWS- DVDDI - 1.1 V DVDDI - 1.45 V CLK input VILD VOHD DA0 to DA7 VOLD tWS+ tf Differential VIHD DVDD - 0.4 V 0.4 V ALL "L" fix * Differential CLK input -- Solid line: CLKEP, Dotted line: CLKEN * VINA input -- Sampling at CLKEP rising (CLKEN falling) * DA0 to DA7 -- Output (after 5 CLK + tpdS from Sampling) at CLKEP rising (CLKEN falling) 9 MB40C318 TIMING CHART 2 Differential CLK input-demultiplex output (in-phase) mode * * * * * * CLKEP = CLKEN = 140 MHz (max) CLKA = CLKB = "L" (DVSS) CKSEL = "H" (AVDD) DSEL = "L" (DVSS) CE = "L" (AVSS) OE = "L" (DVSS) tf tr tWS+ tWS- T DVDDI - 1.1 V VIHD Differential CLK input VILD N-3 N-2 DVDDI - 1.45 V N-1 N N+1 VINA input N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 tAD tpdM1(max) N-9 N-9 VOHD or N - 10 or N - 8 DA0 to DA7 VOLD N - 10 tpdM1(typ) N - 10 N-7 or N - 8 N-8 N-5 or N - 6 N-3 or N - 4 N-6 or N - 7 N-4 or N - 5 N-8 VOHD or N - 11 or N - 9 or N - 9 or N - 7 DB0 to DB7 VOLD VOHD CLKOA VOLD ALL "L" fix th * * * * 10 N+3 N+2 DVDD - 0.4 V 0.4 V VOHD CLKOB VOLD VIHD RESET input VILD tpdM1(min) N+1 N-1 DVDD - 0.4 V or N - 2 0.4V tpdM1(max) tpdM1(typ) tpdM1(min) N N-2 DVDD - 0.4 V or N - 3 0.4V tpdM1O(max) tpdM1O(typ) tpdM1O(min) tS th tS 1.5 V Differential CLK input -- Solid line: CLKEP, Dotted line: CLKEN VINA input -- Sampling at CLKEP rising (CLKEN falling) DA0 to DA7 -- Output (after 5 CLK + tpdM1 from Sampling) at CLKEP rising (CLKEN falling) DB0 to DB7 -- Output (after 6 CLK + tpdM1 from Sampling) at CLKEP rising (CLKEN falling) N + 10 MB40C318 TIMING CHART 3 Differential CLK input-demultiplex output (two-phase) mode * * * * * * CLKEP = CLKEN = 140 MHz (max) CLKA = CLKB = "L" (DVSS) CKSEL = "L" (AVSS) DSEL = "H" (DVDD) CE = "L" (AVSS) OE = "L" (DVSS) tr Differential CLK input VIHD tf DVDDI - 1.1 V VILD DVDDI - 1.45 V N-3 N-2 N-1 VINA input N-9 N+3 N+4 N+5 N - 10 N-7 or N - 8 N-5 or N - 6 N-3 or N - 4 N-8 N-8 VOHD CLKOA VOLD N+6 tpdM2(max) tpdM2(typ) tpdM2(min) N-9 VOHD or N - 9 or N - 9 or N - 7 DB0 to DB7 VOLD N-6 or N - 7 N-4 or N - 5 N-1 or N - 2 tpdM2(max) tpdM2(typ) tpdM2(min) N-2 or N - 3 N+7 N+8 N+9 N+1 DVDD - 0.4 V 0.4 V N + 10 N+3 N DVDD - 0.4 V 0.4 V tpdM2O(max) tpdM2O(typ) tpdM2O(min) N+2 DVDD - 0.4 V 0.4 V tpdM2O(max) tpdM2O(typ) tpdM2O(min) VOHD CLKOB VOLD DVDD - 0.4 V 0.4 V th * * * * N+2 tAD VOHD or N - 10 or N - 8 DA0 to DA7 VOLD VOHD RESET input VOLD N+1 N tWS+ tWS- T tS th tS 1.5 V Differential CLK input -- Solid line: CLKEP, Dotted line: CLKEN VINA input -- Sampling at CLKEP rising (CLKEN falling) DA0 to DA7 -- Output (after 5 CLK + tpdM2 from Sampling) at CLKEP rising (CLKEN falling) DB0 to DB7 -- Output (after 5 CLK + tpdM2 from Sampling) at CLKEP rising (CLKEN falling) 11 MB40C318 TIMING CHART 4 Two-phase CLK input mode (CLKA, CLKB) * * * * * * * * DVDDI = DVDD CLKEP = "L" (DVSS), CLKEN = "H" (DVDD) or CLKEP = "H" (DVDD), CLKEN = "L" (DVSS) CLKA = CLKB = 70 MHz (max) CKSEL = "L" (AVSS) DSEL = "L (DVSS) RESET = "H" (DVDD) or RESET = "L" (DVSS) CE = "L" (AVSS) OE = "L" (DVSS) tWD- tWD+ tr tf VIHD CLKA input VILD DVDD - 0.5 V 0.5 V tWD+ tWD- tr tf VIHD CLKB input VILD DVDD - 0.5 V 0.5 V N(Ach) VINA input VOHD DA0 to DA7 VOLD VOHD DB0 to DB7 VOLD 1.5 V tAD N + 1(Bch) N + 2(Ach) N + 3(Bch) N + 4(Ach) N + 5(Bch) N + 6(Ach) N + 7(Bch) tAD N-6 tpdD(max) tpdD(typ) tpdD(min) N-4 N-5 N-2 N-3 N DVDD - 0.4 V 0.4 V tpdD(max) tpdD(typ) tpdD(min) N-1 tpdDO(max) tpdDO(typ) tpdDO(min) VOHD CLKOA VOLD VOHD CLKOB VOLD * VINA input -- Sampling (A ch) at CLKA falling Sampling (B ch) at CLKB falling * DA0 to DA7 -- Output (after 2.5 CLK + tpdD from Sampling) at CLKA rising * DB0 to DB7 -- Output (after 2.5 CLK + tpdD from Sampling) at CLKB rising 12 1.5 V N+1 DVDD - 0.4 V 0.4 V DVDD - 0.4 V 0.4 V tpdDO(max) tpdDO(typ) tpdDO(min) DVDD - 0.4 V 0.4 V MB40C318 DA3 DA2 DA1 VRT CLKOA DA0(LSB) TYPICAL CONNECTION EXAMPLE + DA4 2 VR1 DA5 35 DA5 3 AVDD DA6 34 DA6 4 AVSS (MSB)DA7 33 5 VREFB CLKEN 32 6 VRB (TOP VIEW) 7 AVSS VINA CKSEL DA7(MSB) CLKEN CLKA 31 CLKA CLKB 30 CLKB 8 VINA CLKEP 29 CLKEP 9 AVDD RESET 28 RESET 10 CKSEL DVDDI 27 11 CE 23 DB3 22 DB4 21 DB5 DB1 25 20 DB6 19 DB7(MSB) 18 DVSS 17 CLKOB 14 OE 13 AVDD 12 AVSS 16 DVDD (LSB)DB0 26 15 DSEL CE DA3 37 DA2 38 DA1 39 (LSB)DA0 40 DVSS 41 DA4 36 DB0(LSB) DB1 24 DB2 + 1 VR2 CLKOA 42 DVDD 43 AVSS 44 AVDD 45 VR3 48 VRB VRT 46 +3.3 V VREFT 47 +3.3 V DB2 DB3 DB4 DB5 DB6 (MSB)DB7 CLKOB DSEL 0.1 F OE +3.3 V or +5 V + To avoid voltage fluctuation at operation of reference voltage generator circuit (VREFT, VREFB) VREFT: 150 F, VREFB: 330 F 13 MB40C318 ORDERING INFORMATION Part number MB40C318PFV 14 Package 48-pin Plastic LQFP (FPT-48P-M05) Remark MB40C318 PACKAGE DIMENSION 48-pin Plastic LQFP (FPT-48P-M05) Note) Pins width and pins thickness include plating thickness. 9.000.20(.354.008)SQ 7.000.10(.276.004)SQ 36 25 37 24 0.08(.003) INDEX Details of "A" part +0.20 1.50 -0.10 48 13 +.008 (Mounting height) .059 -.004 "A" LEAD No. 1 0.500.08 (.020.003) 12 +0.08 0.18 -0.03 +.003 .007 -.001 0.08(.003) M 0.1450.055 (.006.002) 0~8 0.500.20 (.020.008) 0.45/0.75 (.018/.030) C 1998 FUJITSU LIMITED F48013S-3C-6 0.100.10 (.004.004) (Stand off) 0.25(.010) Dimensions in mm (inches). 15 MB40C318 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0001 FUJITSU LIMITED Printed in Japan