KM68257CJ-15 - Samsung Electronics

KM68257C CMOS SRAM

PRELIMINARY

Rev 4.0

- 1 - February 1998

Document Title

32Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out.

Operated at Commercial Temperature Range.

Revision History

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Rev No.

Rev. 0.0

Rev. 1.0

Rev. 2.0

Rev. 3.0

Rev. 4.0

Remark

Preliminary

Final

History

Initial release with Preliminary.

Release to final Data Sheet.

1. Delete Preliminary

Update A.C parameters

2.1. Updated A.C parameters

2.2. Add VOH1=3.95V with the test condition as Vcc=5V±5% at 25°C

3.1. Add 28-TSOP1 Package.

3.2. Add L-version.

3.3. Add Data Rentention Characteristics.

4.1. Delete DIP Package.

4.2. Delete L-version.

4.3. Delete Data Retention Characteristics and Wavetorm.

Items Previous spec.

(12/15/20ns part) Updated spec.

(12/15/20ns part)

tOE - / 8/10ns - / 7 /9 ns

tCW - /12/ - ns - /11/ - ns

tHZ 8/10/10ns 6/7/8ns

tOHZ - / 8 / - ns - / 7 / - ns

tDW - / 9 / - ns - / 8 / - ns

Draft Data

Apr. 1st, 1994

May 14th,1994

Oct. 4th, 1994

Feb. 22th, 1996

Feb. 25th, 1998

KM68257C CMOS SRAM

PRELIMINARY

Rev 4.0

- 2 - February 1998

PIN FUNCTION

Pin Name Pin Function

A0 - A14 Address Inputs

WE Write Enable

CS Chip Select

OE Output Enable

I/O1 ~ I/O8Data Inputs/Outputs

VCC Power(+5.0V)

VSS Ground

32K x 8 Bit High-Speed CMOS Static RAM

The KM68257C is a 262,144-bit high-speed Static Random

Access Memory organized as 32,768 words by 8 bits. The

KM68257C uses 8 common input and output lines and has an

output enable pin which operates faster than address access

time at read cycle. The device is fabricated using SAMSUNG′s

advanced CMOS process and designed for high-speed circuit

technology. It is particularly well suited for use in high-density

high-speed system applications. The KM68257C is packaged in

a 300mil 28-pin plastic SOJ or TSOP1 forward.

GENERAL DESCRIPTIONFEATURES

• Fast Access Time 12, 15, 20ns(Max.)

• Low Power Dissipation

Standby (TTL) : 40mA(Max.)

(CMOS) : 2mA(Max.)

Operating KM68257C - 12 : 165mA(Max.)

KM68257C - 15 : 150mA(Max.)

KM68257C - 20 : 140mA(Max.)

• Single 5.0V±10% Power Supply

• TTL Compatible Inputs and Outputs

• I/O Compatible with 3.3V Device

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• Standard Pin Configuration

KM68257CJ : 28-SOJ-300

KM68257CTG : 28-TSOP1-0813. 4F

Clk Gen.

I/O1~I/O8

PIN CONFIGURATION(Top View)

FUNCTIONAL BLOCK DIAGRAM

A12

A13

A14

Row Select

Data

Cont.

A0A1A2A9A10 A11

CLK

Gen.

Pre-Charge-Circuit

Memory Array

512 Rows

64x8 Columns SOJ

TSOP1

A11

A13

Vcc

A14

A12

A10

I/O8

I/O7

I/O6

I/O5

I/O4

Vss

I/O3

I/O2

I/O1

A14

A12

I/O1

I/O2

I/O3

Vss

Vcc

A13

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

Column Select

I/O Circuit

KM68257C CMOS SRAM

PRELIMINARY

Rev 4.0

- 3 - February 1998

ABSOLUTE MAXIMUM RATINGS*

* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter Symbol Rating Unit

Voltage on Any Pin Relative to VSS VIN, VOUT -0.5 to 7.0 V

Voltage on VCC Supply Relative to VSS VCC -0.5 to 7.0 V

Power Dissipation PD1.0 W

Storage Temperature TSTG -65 to 150 °C

Operating Temperature TA0 to 70 °C

RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)

* VIL(Min) = -2.0(Pulse Width≤10ns) for I≤20mA

** VIH(Max) = VCC+2.0V(Pulse Width≤10ns) for I≤20mA

Parameter Symbol Min Typ Max Unit

Supply Voltage VCC 4.5 5.0 5.5 V

Ground VSS 000V

Input High Voltage VIH 2.2 -VCC+0.5** V

Input Low Voltage VIL -0.5* -0.8 V

DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C,VCC=5.0V±10% unless otherwise specified)

* VCC=5.0V, Temp.=25°C

Parameter Symbol Test Conditions Min Max Unit

Input Leakage Current ILI VIN = VSS to VCC -2 2µA

Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL

VOUT = VSS to VCC -2 2µA

Operating Current ICC Min. Cycle, 100% Duty

CS=VIL, VIN = VIH or VIL,

IOUT=0mA

12ns -165 mA

15ns -150

20ns -140

Standby Current ISB Min. Cycle, CS=VIH -40 mA

ISB1 f=0MHz, CS≥VCC-0.2V,

VIN≥VCC-0.2V or VIN≤0.2V -2mA

Output Low Voltage Level VOL IOL=8mA -0.4 V

Output High Voltage Level VOH IOH=-4mA 2.4 -V

VOH1* IOH1=0.1mA -3.95 V

CAPACITANCE*(TA=25°C, f=1.0MHz)

* NOTE : Capacitance is sampled and not 100% tested.

Item Symbol Test Conditions MIN Max Unit

Input/Output Capacitance CI/O VI/O=0V -8pF

Input Capacitance CIN VIN=0V -7pF

KM68257C CMOS SRAM

PRELIMINARY

Rev 4.0

- 4 - February 1998

TEST CONDITIONS

Parameter Value

Input Pulse Levels 0V to 3V

Input Rise and Fall Times 3ns

Input and Output timing Reference Levels 1.5V

Output Loads See below

AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)

Output Loads(A) Output Loads(B)

DOUT

5pF*

480Ω

255Ω

for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ

+5.0V

READ CYCLE

Parameter Symbol KM68257C-12 KM68257C-15 KM68257C-20 Unit

Min Max Min Max Min Max

Read Cycle Time tRC 12 -15 -20 -ns

Address Access Time tAA -12 -15 -20 ns

Chip Select to Output tCO -12 -15 -20 ns

Output Enable to Valid Output tOE -6-7-9ns

Chip Enable to Low-Z Output tLZ 3-3-3-ns

Output Enable to Low-Z Output tOLZ 0-0-0-ns

Chip Disable to High-Z Output tHZ 0 6 0 7 0 10 ns

Output Disable to High-Z Output tOHZ 0 6 0 7 0 10 ns

Output Hold from Address Change tOH 3-3-3-ns

Chip Selection to Power Up Time tPU 0-0-0-ns

Chip Selection to Power DownTime tPD -12 -15 -20 ns

DOUT

30pF*

480Ω

255Ω

+5V

* Including Scope and Jig Capacitance

KM68257C CMOS SRAM

PRELIMINARY

Rev 4.0

- 5 - February 1998

WRITE CYCLE

Parameter Symbol KM68257C-12 KM68257C-15 KM68257C-20 Unit

Min Max Min Max Min Max

Write Cycle Time tWC 12 -15 -20 -ns

Chip Select to End of Write tCW 9-11 -13 -ns

Address Setup Time tAS 0-0-0-ns

Address Valid to End of Write tAW 9-12 -13 -ns

Write Pulse Width(OE High) tWP 9-12 -13 -ns

Write Pulse Width(OE Low) tWP1 12 -15 -20 -ns

Write Recovery Time tWR 0-0-0-ns

Write to Output High-Z tWHZ 060808ns

Data to Write Time Overlap tDW 7-8-10 -ns

Data Hold from Write Time tDH 0-0-0-ns

End Write to Output Low-Z tOW 0-0-0-ns

Address

Data Out Previous Valid Data Valid Data

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)

tAA

tRC

tOH

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Address

Data out

tAA

tOLZ

tLZ(4,5) tOH

tOHZ

tRC

tOE

tCO

tPU tPD

Valid Data

tHZ(3,4,5)

50%

VCC

Current

ICC

ISB

KM68257C CMOS SRAM

PRELIMINARY

Rev 4.0

- 6 - February 1998

TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)

Address

tWP(2)

tDW tDH

Valid Data

Data in

Data out

tWC

tWR(5)

tAW

tCW(3)

High-Z(8)

High-Z

tOHZ(6)

tAS(4)

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL

levels.

4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to

device.

5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS=VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)

Address

tWP1(2)

tDW tDH

tOW

tWHZ(6)

Valid Data

Data in

Data out

tWC

tAS(4)

tWR(5)

tAW tCW(3)

(10) (9)

High-Z(8)

High-Z

KM68257C CMOS SRAM

PRELIMINARY

Rev 4.0

- 7 - February 1998

TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)

Address

tAW

tDW tDH

Valid Data

Data in

Data out High-Z High-Z(8)

tCW(3)

tWP(2)tAS(4)

tWC

tWR(5)

High-Z

tLZ tWHZ(6)

NOTES(WRITE CYCLE)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;

A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end

of write.

3. tCW is measured from the later of CS going low to end of write.

4. tAS is measured from the address valid to the beginning of write.

5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be

applied.

FUNCTIONAL DESCRIPTION

* NOTE : X means Don′t Care.

CS WE OE Mode I/O Pin Supply Current

HXX* Not Select High-Z ISB, ISB1

LH H Output Disable High-Z ICC

LHLRead DOUT ICC

L L XWrite DIN ICC

KM68257C CMOS SRAM

PRELIMINARY

Rev 4.0

- 8 - February 1998

PACKAGE DIMENSIONS

Units:millimeters/Inches

28-SOJ-300

#28

18.41 ±0.12

0.725 ±0.005

7.62

0.300

+0.10

MAX

18.82

0.741

0.20 -0.05

+0.004

0.008

-0.002

6.86 ±0.25

0.270 ±0.010

MAX

0.148

3.76

MIN

0.69

0.027

1.30

( )

0.051

1.30

( )

0.051

#14

#15

0.95

( )

0.0375

+0.10

0.43 -0.05

+0.004

0.017 -0.002

+0.10

0.71 -0.05

+0.004

0.028 -0.002

1.27

0.050

0.004

0.10 MAX

8.51 ±0.12

0.335 ±0.005

28-TSOP1-0813.4F

1.00 ±0.10

0.039 ±0.004

MAX

8.40

0.331

0.004 MAX

0.10 MAX

0.50

( )

0.020

11.80 ±0.10

0.465 ±0.004

0.45 ~0.75

0.018 ~0.030

+0.10

0.15 -0.05

+0.004

0.006 -0.002

0~8°

0.425

( )

0.017

MIN

0.05

0.002

MAX

1.20

0.047

8.00

0.315

TYP

0.25

0.010

#28#1

13.40 ±0.20

0.528 ±0.008

#15#14

+0.10

0.20 -0.05

+0.004

0.008 -0.002

0.55

0.0217

Units:millimeters/Inches