DATASHEET ICS660 DIGITAL VIDEO CLOCK SOURCE Description Features The ICS660 provides clock generation and conversion for clock rates commonly needed in digital video equipment, including rates for MPEG, NTSC, PAL, and HDTV. The ICS660 uses the latest PLL technology to provide excellent phase noise and long term jitter performance for superior synchronization and S/N ratio. * * * * * * * * For audio sampling clocks generated from 27 MHz, use the ICS661. Please contact IDT if you have a requirement for an input and output frequency not included here - we can rapidly modify this product to meet special requirements. Packaged in 16-pin TSSOP Pb-free packaging, RoHS compliant Clock or crystal input Low phase noise Low jitter Exact (0 ppm) multiplication ratios Power-down control Reference clock output available Block Diagram VDD (P2) VDD (P3) VDDO X2 VDDR REF Crystal Oscillator X1/REFIN SELIN S3:0 PLL Clock Synthesis CLK 4 GND (P6) GND (P13) IDTTM / ICSTM DIGITAL VIDEO CLOCK SOURCE 1 GND (P5) ICS660 REV G 051310 ICS660 DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER Pin Assignment Output Clock Selection Table S3 S2 S1 S0 Input Frequency (MHz) Output Frequency (MHz) X1/REFIN 1 16 X2 VDD 2 15 REF 0 0 0 0 13.5 74.25 VDD 3 14 VDDR 0 0 0 1 13.5 74.175824 S0 4 13 GND 0 0 1 0 27 74.25 0 0 1 1 27 74.175824 GND 5 12 SELIN 0 1 0 0 Pass thru Input Freq GND 6 11 VDDO 0 1 0 1 74.25 74.175824 S3 7 10 S1 0 1 1 0 74.175824 74.25 0 1 1 1 S2 8 9 1 0 0 0 16.9344 27 1 0 0 1 125 106.25 1 0 1 0 14.3181818 27 1 0 1 1 106.25 125 1 1 0 0 27.027 27 1 1 0 1 27 27.027 CLK 16-pin 4.40 mil body, 0.65 mm pitch TSSOP 1 1 1 0 27 14.3181818 1 1 1 1 27 17.734472051 1 Pin Descriptions Pin Number Pin Name Pin Type 1 X1/REFIN Input 2 VDD Power Power supply for crystal oscillator. 3 VDD Power Power supply for PLL. Power down - 0.16 ppm compared to PAL specification Pin Description Connect this pin to a crystal or clock input 4 S0 Input Output frequency selection. Determines output frequency per table above. On chip pull-up. 5 GND Power Ground for output stage. 6 GND Power Ground for PLL. 7 S3 Input Output frequency selection. Determines output frequency per table above. On chip pull-up. Output frequency selection. Determines output frequency per table above. On chip pull-up. 8 S2 Input 9 CLK Output Clock output. 10 S1 Input Output frequency selection. Determines output frequency per table above. On chip pull-up. 11 VDDO Power Power supply for output stage. 12 SEL Input Low for clock input, high for crystal. On chip pull-up. 13 GND Power Connect to ground. 14 VDDR Power Power supply for reference output. Ground to turn off REF. 15 REF Output Reference clock output. 16 X2 Input Connect this pin to a crystal. Leave open if using a clock input. IDTTM / ICSTM DIGITAL VIDEO CLOCK SOURCE 2 ICS660 REV G 051310 ICS660 DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER Application Information Series Termination Resistor capacitance of the board to match the nominally required crystal load capacitance. To reduce possible noise pickup, use very short PCB traces (and no vias) been the crystal and device. Clock output traces should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20. The value of the load capacitors can be roughly determined by the formula C = 2(CL - 6) where C is the load capacitor connected to X1 and X2, and CL is the specified value of the load capacitance for the crystal. A typical crystal CL is 18 pF, so C = 2(18 - 6) = 24 pF. Because these capacitors adjust the stray capacitance of the PCB, check the output frequency using your final layout to see if the value of C should be changed. Decoupling Capacitors As with any high-performance mixed-signal IC, the ICS660 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01F must be connected between each VDD and the PCB ground plane. To further guard against interfering system supply noise, the ICS660 should use one common connection to the PCB power plane as shown in the diagram on the next page. The ferrite bead and bulk capacitor help reduce lower frequency noise in the supply that can lead to output clock phase modulation. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. Recommended Power Supply Connection for Optimal Device Performance V D D P in C onnection to 3.3V P ow er P lane Ferrite Bead B ulk D ecoupling C apacitor (such as 1 F Tantalum ) 0.01 V D D P in 2) The external crystal should be mounted next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. V D D P in 3) To minimize EMI, and obtain the best signal integrity, the 33 series termination resistor should be placed close to the clock output. F D ecoupling C apacitors 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS660. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. All power supply pins must be connected to the same voltage, except VDDR and VDDO, which may be connected to a lower voltage in order to change the output level. If the reference output is not used, ground VDDR. Crystal Load Capacitors If a crystal is used, the device crystal connections should include pads for capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray IDTTM / ICSTM DIGITAL VIDEO CLOCK SOURCE 3 ICS660 REV G 051310 ICS660 DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS660. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 5.5 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85 C Storage Temperature -65 to +150 C Junction Temperature 125 C Soldering Temperature 260 C Recommended Operation Conditions Parameter Min. Typ. Max. Units Ambient Operating Temperature -40 +85 C Power Supply Voltage (measured in respect to GND) +3.0 +3.6 V DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85 C Parameter Operating Voltage Supply Current Standby Supply Current Symbol Conditions Min. Typ. Max. Units VDD 3.0 3.6 V VDDO 2.5 VDD V VDDR 2.5 VDD V IDD No Load IDDPD 25 mA 75 A Input High Voltage VIH Input Low Voltage VIL Output High Voltage VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -20 mA 2.4 V Output Low Voltage VOL IOL = 20 mA Short Circuit Current IOS Each output Nominal Output Impedance CIN Internal Pull-up Resistor RPU V 0.8 ZOUT Input Capacitance IDTTM / ICSTM DIGITAL VIDEO CLOCK SOURCE 2 input pins 4 0.4 V V 65 mA 20 7 pF 120 k ICS660 REV G 051310 ICS660 DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85 C Parameter Symbol Conditions Min. Typ. Crystal Frequency Max. Units 28 MHz Output Clock Rise Time tOR 20% to 80%, 15 pF load 1.5 ns Output Clock Fall Time tOF 80% to 20%, 15 pF load 1.5 ns Output Duty Cycle tOD at VDD/2, 15 pF load 60 % Power up time tPU inputs out of PD state to clocks stable 10 ms Power down time tPD inputs in PD state to clocks off 1 s 40 49 to 51 Jitter, short term Reference clock off 100 ps p-p Jitter, short term Reference clock on 125 ps p-p Jitter, long term Reference clock off; 10 us delay 300 ps p-p Jitter, long term Reference clock on; 10 us delay 300 ps p-p Single sideband phase noise Reference clock off; 10 kHz offset -110 dBc Single sideband phase noise Reference clock on; 10 kHz offset -110 dBc 0 ppm Actual mean frequency error versus target Note 1 Note 1: Selection 1111 is 0.16 ppm lower than the PAL specified frequency Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case IDTTM / ICSTM DIGITAL VIDEO CLOCK SOURCE Symbol Conditions Min. Typ. Max. Units JA Still air 78 C/W JA 1 m/s air flow 70 C/W JA 3 m/s air flow 68 C/W 37 C/W JC 5 ICS660 REV G 051310 ICS660 DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 Millimeters 16 Symbol E1 A A1 A2 b C D E E1 e L aaa E IN D EX AR EA 1 2 D A 2 Min Inches Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10 Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004 A A 1 c -C e b S E A TIN G P LA N E L aaa C Ordering Information Part / Order Number Marking Shipping packaging Package Temperature 660GILF 660GILF Tubes 16-pin TSSOP -40 to +85 C 660GILFT 660GILF Tape and Reel 16-pin TSSOP -40 to +85 C "LF" denotes Pb-free package, RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDTTM / ICSTM DIGITAL VIDEO CLOCK SOURCE 6 ICS660 REV G 051310 ICS660 DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA