W982516CH-75 - Winbond Electronics Corporation America

W982516CH

4M ×× 4 BANKS ×× 16 BIT SDRAM

Publication Release Date: Mar 2003

- 1 - Revision A1

GENERAL DESCRIPTION

W982516CH is a high-speed synchronous dynamic random access memory (SDRAM), organized as

4M words × 4 banks × 16 bits. Using pipelined architecture and 0.13 µm process technology,

W982516CH delivers a data bandwidth of up to 143M words per second (-7). To fully comply with the

personal computer industrial standard, W982516CH is sorted into two speed grades: -7 and -75. The -

7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is compliant to the PC133/CL3

specification, for handheld device application, we also provide a low power option, the 75L grade, with

Self Refresh Current under 1mA., and an industrial temperature option, the grade of 75I, which is

guranteed to support -40°C – 85°C.

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be

accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE

command. Column addresses are automatically generated by the SDRAM internal counter in burst

operation. Random column read is also possible by providing its address at each clock cycle. The

multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle,

interleave or sequential burst to maximize its performance. W982516CH is ideal for main memory in

high performance applications.

FEATURES

• 3.3V ± 0.3V Power Supply

• Up to 143 MHz Clock Frequency

• 4,194,304 Words × 4 Banks × 16 Bits Organization

• Self Refresh Mode: Standard and Low Power

• CAS Latency: 2 and 3

• Burst Length: 1, 2, 4, 8, and Full Page

• Burst Read, Single Writes Mode

• Byte Data Controlled by LDQM, UDQM

• Power-down Mode

• Auto-precharge and Controlled Precharge

• 8K Refresh Cycles/64 mS

• Interface: LVTTL

• Packaged in TSOP II 54-pin, 400 mil - 0.80

AVAILABLE PART NUMBER

Part Number Speed Grade Self Refresh Current (Max) Operating Temperature

W982516CH- 7 PC133/CL2 3mA 0°C - 70°C

W982516CH-75 PC133/CL3 3mA 0°C - 70°C

W982516CH75L PC133/CL3 1mA 0°C - 70°C

W982516CH75I PC133/CL3 1mA -40°C - 85°C

W982516CH

- 2 -

PIN CONFIGURATION

VSS

DQ15

VSSQ

DQ14

DQ13

VCCQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VCCQ

DQ8

VSS

UDQM

CLK

CKE

A12

A11

VSS

VCC

DQ0

VCCQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VCCQ

DQ5

DQ6

VSSQ

DQ7

VCC

LDQM

BS0

BS1

A10/AP

VCC

RAS

CAS

W982516CH

Publication Release Date: Mar 2003

- 3 - Revision A1

PIN DESCRIPTION

PIN NO. PIN NAME

FUNCTION DESCRIPTION

23−26, 22,

29−36 A0−A12 Address Multiplexed pins for row and column address.

Row address: A0−A12. Column address: A0−A8.

20, 21 BS0, BS1 Bank Select Select bank to activate during row address latch time, or

bank to read/write during address latch time.

2, 4, 5, 7, 8, 10,

11, 13, 42, 44,

45, 47, 48, 50,

51, 53 DQ0−DQ16

Data

Input/Output Multiplexed pins for data output and input.

19 CS Chip Select Disable or enable the command decoder. When

command decoder is disabled, new command is

ignored and previous operation continues.

18 RAS Row Address

Strobe

Command input. When sampled at the rising edge of

the clock, RAS , CAS and

define the operation

to be executed.

17 CAS Column

Address

Strobe Referred to RAS

Write Enable Referred to RAS

15, 39 LDQM,

UDQM Input/Output

Mask

The output buffer is placed at Hi-Z(with latency of 2)

when DQM is sampled high in read cycle. In write

cycle, sampling DQM high will block the write operation

with zero latency.

38 CLK Clock Inputs System clock used to sample inputs on the rising edge

of clock.

37 CKE Clock Enable

CKE controls the clock activation and deactivation.

When CKE is low, Power Down mode

, Suspend mode,

or Self Refresh mode is entered.

1, 14, 27 VCC Power (+3.3V)

Power for input buffers and logic circuit inside DRAM.

28, 41, 54 VSS Ground Ground for input buffers and logic circuit inside DRAM.

3, 9, 43, 49 VCCQ Power (+3.3V)

for I/O Buffer Separated power from VCC, to improve DQ noise

immunity.

6, 12, 46, 52 VSSQ Ground

for I/O Buffer Separated ground from VSS, to improve DQ noise

immunity.

40 NC No Connection

No connection

W982516CH

- 4 -

BLOCK DIAGRAM

DQ0

DQ15

LDQM

UDQM

CLK

CKE

RAS

CAS

A10

A11

A12

BS0

BS1

CLOCK

BUFFER

COMMAND

DECODER

ADDRESS

BUFFER

REFRESH

COUNTER COLUMN

COUNTER

CONTROL

SIGNAL

GENERATOR

MODE

COLUMN DECODER

SENSE AMPLIFIER

CELL ARRAY

BANK #2

COLUMN DECODER

SENSE AMPLIFIER

CELL ARRAY

BANK #0

COLUMN DECODER

SENSE AMPLIFIER

CELL ARRAY

BANK #3

DATA CONTROL

CIRCUIT DQ

BUFFER

COLUMN DECODER

SENSE AMPLIFIER

CELL ARRAY

BANK #1

Note: The cell array configuration is 8192 * 512 * 16.

ROW DECODER ROW DECODER

ROW DECODERROW DECODER

W982516CH

Publication Release Date: Mar 2003

- 5 - Revision A1

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATING UNIT NOTES

Input, Output Voltage VIN, VOUT -0.3 − VCC + 0.3 V 1

Supply Voltage VCC, VCCQ -0.3 − 4.6 V 1

Operating Temperature(-7/-75/75L) TOPR 0 − 70 °C 1

Operating Temperature(75I) TOPR -40 − 85 °C 1

Storage Temperature TSTG -55 − 150 °C 1

Soldering Temperature (10s) TSOLDER 260 °C 1

Power Dissipation PD 1 W 1

Short Circuit Output Current IOUT 50 mA 1

Note 1: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

RECOMMENDED DC OPERATING CONDITIONS

(Ta = 0 to 70°C for -7/-75/75L, Ta=-40 to 85°C for 75I)

PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES

Supply Voltage VCC 3.0 3.3 3.6 V 2

Supply Voltage (for I/O Buffer) VCCQ 3.0 3.3 3.6 V 2

Input High Voltage VIH 2.0 - VCC +0.3 V 2

Input Low Voltage VIL -0.3 - 0.8 V 2

Note 2: VIH(max) = VCC/ VCCQ+1.2V for pulse width < 5 nS

VIL(min) = VSS/ VSSQ-1.2V for pulse width < 5 nS

CAPACITANCE

(VCC = 3.3V, f = 1 MHz, TA = 25°C)

PARAMETER SYMBOL MIN. MAX. UNIT

Input Capacitance

(A0 to A12, BS0, BS1, CS, RAS , CAS,

, LDQM,

UDQM, CKE)

CI - 3.8 pf

Input Capacitance (CLK) CCLK - 3.5 pf

Input/Output Capacitance CIO - 6.5 pf

Note: These parameters are periodically sampled and not 100% tested.

W982516CH

- 6 -

AC CHARACTERISTICS AND OPERATING CONDITION

(Vcc = 3.3V ± 0.3V, Ta = 0 to 70°C for -7/-75/75L, Ta=-40 to 85°C for 75I ; Notes: 5, 6, 7, 8)

PARAMETER SYM. -7

(PC133, CL2) -75/75L/75I

(PC133, CL3) UNIT

MIN. MAX. MIN. MAX.

Ref/Active to Ref/Active Command Period tRC 56 65 nS

Active to precharge Command Period tRAS 40 100000 45 100000 nS

Active to Read/Write Command Delay Time tRCD 15 20 nS

Read/Write(a) to Read/Write(b) Command

Period tCCD 1 1 tCK

Precharge to Active Command Period tRP 15 20 nS

Active(a) to Active(b) Command Period tRRD 15 15 nS

Write Recovery Time CL* = 2 tWR 2 2 tCK

CL* = 3 2 2 tCK

CLK Cycle Time CL* = 2 tCK 7.5 1000 10 1000 nS

CL* = 3 7 1000 7.5 1000 nS

CLK High Level Width tCH 2.5 2.5 nS

CLK Low Level Width tCL 2.5 2.5 nS

Access Time from CLK CL* = 2 tAC 5.4 6 nS

CL* = 3 5.4 5.4 nS

Output Data Hold Time tOH 3 3 nS

Output Data High Impedance Time tHZ 3 7 3 7.5 nS

Output Data Low Impedance Time tLZ 0 0 nS

Power Down Mode Entry Time tSB 0 7 0 7.5 nS

Transition Time of CLK

(Rise and Fall) tT 0.5 10 0.5 10 nS

Data-in Set-up Time tDS 1.5 1.5 nS

Data-in Hold Time tDH 0.8 0.8 nS

Address Set-up Time tAS 1.5 1.5 nS

Address Hold Time tAH 0.8 0.8 nS

CKE Set-up Time tCKS 1.5 1.5 nS

CKE Hold Time tCKH 0.8 0.8 nS

Command Set-up Time tCMS 1.5 1.5 nS

Command Hold Time tCMS 0.8 0.8 nS

Refresh Time tREF 64 64 mS

Mode register Set Cycle Time tRSC 14 15 nS

*CL = CAS Latency

W982516CH

Publication Release Date: Mar 2003

- 7 - Revision A1

DC CHARACTERISTICS

(VCC = 3.3V ± 0.3V, Ta = 0 to 70°C for -7/-75/75L, Ta=-40 to 85°C for 75I)

PARAMETER SYM

. -7

(PC133, CL2) -75/75L/75I

(PC133, CL3) UNIT NOTES

MIN. MAX. MIN. MAX.

Operating Current

tCK = min., tRC = min.

Active precharge command

cycling without burst

operation

1 Bank Operation ICC1 80 75 3

Standby Current

tCK = min, CS = VIH

CKE = VIH ICC2 40 35 3

VIH/L = VIH (min.)/VIL (max.)

Bank: Inactive state CKE = VIL (Power

down mode) ICC2P 1 1 3

Standby Current

CLK = VIL, CS = VIH

CKE = VIH ICC2S 10 10

VIH/L = VIH (min.)/VIL (max.)

BANK: Inactive state CKE = VIL (Power

down mode) ICC2PS 1 1 mA

No Operating Current

tCK = min., CS = VIH (min.)

CKE = VIH ICC3 60 55

BANK: Active state

(4 banks) CKE = VIL (Power

down mode) ICC3P 10 10

Burst Operating Current

tCK = min.

Read/ Write command cycling

ICC4 100 95 3, 4

Auto Refresh Current

tCK = min.

Auto refresh command cycling

ICC5 170 160 3

Standard(-7/-75) 3 3

Self Refresh Current

Self Refresh Mode

CKE = 0.2V Low Power(75L/75I) ICC6L - 1

PARAMETER SYMBOL MIN. MAX. UNIT NOTES

Input Leakage Current

(0V ≤ VIN ≤ VCC, all other pins not under test = 0V)

II(L) -5 5 µA

Output Leakage Current

(Output disable, 0V ≤ VOUT ≤ VCCQ)

IO(L) -5 5 µA

LVTTL Output ″H″ Level Voltage

(IOUT = -2 mA )

VOH 2.4 - V

LVTTL Output ″L″ Level Voltage

(IOUT = 2 mA )

VOL - 0.4 V

W982516CH

- 8 -

Notes:

1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the

devices.

2. All voltages are referenced to VSS

3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the

minimum values of tCK and tRC.

4. These parameters depend on the output loading conditions. Specified values are obtained with

output open.

5. Power up sequence is further described in the "Functional Description" section.

6. AC Testing Conditions

Output Reference Level 1.4V/1.4V

Output Load See diagram below

Input Signal Levels 2.4V/0.4V

Transition Time (Rise and Fall) of Input Signal 2 nS

Input Reference Level 1.4V

50 ohms

1.4 V

AC TEST LOAD

Z = 50 ohmsoutput 50pF

7. Transition times are measured between VIH and VIL.

8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to

output level.

W982516CH

Publication Release Date: Mar 2003

- 9 - Revision A1

OPERATION MODE

Fully synchronous operations are performed to latch the commands at the positive edges of CLK.

Table 1 shows the truth table for the operation commands.

Table 1 Truth Table (Note (1) , (2))

COMMAND DEVICE

STATE

CKEN-1 CKEN DQM BS0, 1 A10 A0−−A9

A11, A12 CS RAS CAS WE

Bank Active Idle H x x v v v L L H H

Bank Precharge Any H x x v L x L L H L

Precharge All Any H x x x H x L L H L

Write Active (3) H x x v L v L H L L

Write with Autoprecharge Active (3) H x x v H v L H L L

Read Active (3) H x x v L v L H L H

Read with Autoprecharge Active (3) H x x v H v L H L H

Mode Register Set Idle H x x v v v L L L L

No-operation Any H x x x x x L H H H

Burst Stop Active (4) H x x x x x L H H L

Device Deselect Any H x x x x x H x x x

Auto-refresh Idle H H x x x x L L L H

Self-refresh Entry Idle H L x x x x L L L H

Self-refresh Exit Idle

(S.R.) L

Clock Suspend Mode

Entry Active H L x x x x x x x x

Power Down Mode Entry Idle

Active (5) H

Clock Suspend Mode Exit Active L H x x x x x x x x

Power Down Mode Exit

Any

(Power

down)

Data Write/Output Enable Active H x L x x x x x x x

Data Write/Output Disable Active H x H x x x x x x x

Notes:

(1) v = valid x = Don't care L = Low Level H = High Level

(2) CKEn signal is input level when commands are provided.

CKEn-1 signal is the input level one clock cycle before the command is issued.

(3) These are state of bank designated by BS0, BS1 signals.

(4) Device state is full page burst operation.

(5) Power Down Mode can not be entered in the burst cycle.

When this command asserts in the burst cycle, device state is clock suspend mode.

W982516CH

- 10 -

FUNCTIONAL DESCRIPTION

Power Up and Initialization

The default power up state of the mode register is unspecified. The following power up and

initialization sequence need to be followed to guarantee the device being preconditioned to each user

specific needs.

During power up, all Vcc and VccQ pins must be ramp up simultaneously to the specified voltage

when the input signals are held in the "NOP" state. The power up voltage must not exceed Vcc +0.3V

on any of the input pins or Vcc supplies. After power up, an initial pause of 200 µS is required followed

by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus

during power up, it is required that the DQM and CKE pins be held high during the initial pause period.

Once all banks have been precharged, the Mode Register Set Command must be issued to initialize

the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after

programming the Mode Register to ensure proper subsequent operation.

Programming Mode Register

After initial power up, the Mode Register Set Command must be issued for proper device operation.

All banks must be in a precharged state and CKE must be high at least one cycle before the Mode

signals of RAS, CAS, CS and WE at the positive edge of the clock. The address input data during this

cycle defines the parameters to be set as shown in the Mode Register Operation table. A new

command may be issued following the mode register set command once a delay equal to tRSC has

elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.

Bank Activate Command

The Bank Activate command must be applied before any Read or Write operation can be executed.

The operation is similar to

RAS

activate in EDO DRAM. The delay from when the Bank Activate

command is applied to when the first read or write operation can begin must not be less than the RAS

to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank

Activate command can be issued to the same bank. The minimum time interval between successive

Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).

The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice

versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is

specified as tRAS (max).

Read and Write Access Modes

After a bank has been activated , a read or write cycle can be followed. This is accomplished by

setting RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage

level defines whether the access cycle is a read operation (WE high), or a write operation (WE low).

The address inputs determine the starting column address.

Reading or writing to a different row within an activated bank requires the bank be precharged and a

new Bank Activate command be issued. When more than one bank is activated, interleaved bank

Read or Write operations are possible. By using the programmed burst length and alternating the

access and precharge operations between multiple banks, seamless data access operation among

many different pages can be realized. Read or Write Commands can also be issued to the same bank

or between active banks on every clock cycle.

W982516CH

Publication Release Date: Mar 2003

- 11 - Revision A1

Burst Read Command

The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS

and WE high at the rising edge of the clock. The address inputs determine the starting column

address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst

length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page

explain the address sequence of interleave mode and sequential mode.

Burst Write Command

The Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding

RAS high at the rising edge of the clock. The address inputs determine the starting column address.

Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the

Write Command is issued. The remaining data inputs must be supplied on each subsequent rising

clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be

ignored.

Read Interrupted by a Read

A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,

the remaining addresses are overridden by the new read address with the full burst length. The data

from the first Read Command continues to appear on the outputs until the CAS latency from the

interrupting Read Command the is satisfied.

Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output

drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will

issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the

DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM

masking is no longer needed.

Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When the

previous burst is interrupted, the remaining addresses are overridden by the new address and data

will be written into the device until the programmed burst length is satisfied.

Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read

Command is activated. The DQs must be in the high impedance state at least one cycle before the

new read data appears on the outputs to avoid data contention. When the Read Command is

activated, any residual data from the burst write cycle will be ignored.

Burst Stop Command

A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open

for future Read or Write Commands to the same page of the active bank, if the burst length is full page.

Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop

Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock.

The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst

read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write

operation, then any residual data from the burst write cycle will be ignored.

W982516CH

- 12 -

Addressing Sequence of Sequential Mode

A column access is performed by increasing the address from the column address which is input to

the device. The disturb address is varied by the Burst Length as shown in Table 2.

Table 2 Address Sequence of Sequential Mode

DATA ACCESS ADDRESS BURST LENGTH

Data 0 n BL = 2 (disturb address is A0)

Data 1 n + 1 No address carry from A0 to A1

Data 2 n + 2 BL = 4 (disturb addresses are A0 and A1)

Data 3 n + 3 No address carry from A1 to A2

Data 4 n + 4

Data 5 n + 5 BL = 8 (disturb addresses are A0, A1 and A2)

Data 6 n + 6 No address carry from A2 to A3

Data 7 n + 7

Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting the address bit

in the sequence shown in Table 3.

Table 3 Address Sequence of Interleave Mode

DATA ACCESS ADDRESS BUST LENGTH

Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2

Data 1 A8 A7 A6 A5 A4 A3 A2 A1

Data 2 A8 A7 A6 A5 A4 A3 A2

A0 BL = 4

Data 3 A8 A7 A6 A5 A4 A3 A2

Data 4 A8 A7 A6 A5 A4 A3

A1 A0 BL = 8

Data 5 A8 A7 A6 A5 A4 A3

Data 6 A8 A7 A6 A5 A4 A3

Data 7 A8 A7 A6 A5 A4 A3

W982516CH

Publication Release Date: Mar 2003

- 13 - Revision A1

Auto-precharge Command

If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is

entered. During auto-precharge, a Read Command will execute as normal with the exception that the

active bank will begin to precharge automatically before all burst read cycles have been completed.

Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled

burst cycle. The number of clocks is determined by CAS latency.

A Read or Write Command with auto-precharge can not be interrupted before the entire burst

operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during

a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot

be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-pecharge command is

illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write

with Auto-pecharge function is initiated. The SDRAM automatically enters the precharge operation two

clock delay from the last burst write cycle. This delay is referred to as Write tWR. The bank undergoing

auto-precharge can not be reactivated until tWR and tRP are satisfied. This is referred to as tDAL, Data-in

to Active delay (tDAL = tWR + tRP). When using the Auto-precharge Command, the interval between the

Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS (min).

Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The

Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising edge of

the clock. The Precharge Command can be used to precharge each bank separately or all banks

simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to be

precharged when the command is issued. After the Precharge Command is issued, the precharged

bank must be reactivated before a new read or write access can be executed. The delay between the

Precharge Command and the Activate Command must be greater than or equal to the Precharge time

(tRP).

Self Refresh Command

The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at

the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once

the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the

SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled.

The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self

Refresh operation after CKE is returned high. A minimum delay time is required when the device exits

Self Refresh Operation and before the next command can be issued. This delay is equal to the tAC

cycle time plus the Self Refresh exit time.

If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly

distributed), a burst of 8,192 AUTO REFRESH cycles should be completed just prior to entering and

just after exiting the self refresh mode.

Power Down Mode

The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are

gated off to reduce the power. The Power Down mode does not perform any refresh operations,

therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the

device.

W982516CH

- 14 -

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation

Command is required on the next rising clock edge, depending on tCK. The input buffers need to be

enabled with CKE held high for a period equal to tCKS (min) + tCK (min).

No Operation Command

The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to

prevent the SDRAM from registering any unwanted commands between operations. A No Operation

Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the

clock. A No Operation Command will not terminate a previous operation that is still executing, such as

a burst read or write cycle.

Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect

Command occurs when CS is brought high, the RAS, CAS, and WE signals become don't cares.

Clock Suspend Mode

During normal access mode, CKE must be held high enabling the clock. When CKE is registered low

while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode

deactivates the internal clock and suspends any clocked operation that was currently being executed.

There is a one clock delay between the registration of CKE low and the time at which the SDRAM

operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are

issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay

from when CKE returns high to when Clock Suspend mode is exited.

W982516CH

Publication Release Date: Mar 2003

- 15 - Revision A1

TIMING WAVEFORMS

Command Input Timing

CLK

A0-A12

BS0, 1

VIH

VIL

tCMH tCMS

tCHtCL

tTtT

tCKS tCKH

tCKH

tCKS

tCKS tCKH

Command Input Timing

RAS

CAS

CKE

tCMS tCMH

tAS tAH

tCK

W982516CH

- 16 -

Timing Waveforms, continued

Read Timing

Read CAS Latency

tAC

tLZ

tAC

tOH

tHZ

tOH

Burst Length

Read Command

CLK

RAS

CAS

A0 - A12

BS0, 1

DQ Valid

Data-Out Valid

Data-Out

W982516CH

Publication Release Date: Mar 2003

- 17 - Revision A1

Timing Waveforms, continued

Control Timing of Input/Output Data

tCMH tCMS tCMH tCMS

tDS tDH tDS tDH tDS tDH tDS tDH

Valid

Data-Out Valid

Data-Out

Valid

Data-in Valid

Data-in

tCKH tCKS tCKH tCKS

tDS tDH tDS tDH tDHtDS tDS tDH

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

tCMH tCMS tCMH tCMS

tOHtAC tOH tAC tOHtHZ

OPEN

tLZtAC tOH tAC

tCKH tCKS tCKH tCKS

tOHtAC tOH tAC tOHtAC tOH tAC

Valid

Data-Out Valid

Data-Out

Valid

Data-Out

CLK

DQM

DQ0 -15

(Word Mask)

(Clock Mask)

CLK

CKE

DQ0 -15

CLK

Input Data

Output Data

(Output Enable)

(Clock Mask)

DQM

DQ0 -15

CKE

CLK

DQ0 -15

W982516CH

- 18 -

Timing Waveforms, continued

Mode Register Set Cycle

Burst Length

Addressing Mode

CAS Latency

(Test Mode)

A8 Reserved

A0A7

A0A9 A0Write Mode

A10

A12

A0A11

A0BS0

"0"

A0A3 A0Addressing Mode

A00A0Sequential

A01A0Interleave

A0A9 Single Write Mode

A00A0Burst read and Burst write

A01A0Burst read and single write

A0A2 A1 A0

A00 0 0

A00 0 1

A00 1 0

A00 1 1

A01 0 0

1 0 1

A01 1 0

A01 1 1

A0Burst Length

A0Sequential A0Interleave

1A01

A02A02

A04A04

A08A08

A0Reserved A0

Reserved

A0Full Page

A0CAS Latency

A0Reserved

A03

Reserved

A0A6 A5 A4

A00 0 0

A00 1 0

A00 1 1

A01 0 0

A00 0 1

RSC

CMS

CMH

CMS

CMH

CMS

CMH

CMS

CMH

CLK

RAS

CAS

A0-A12

BS0,1 Register

set data

command

Reserved

"0"

A0BS1 "0"

W982516CH

Publication Release Date: Mar 2003

- 19 - Revision A1

OPERATING TIMING EXAMPLE

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)

0123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

(CLK = 100 MHz)

CLK

CKE

DQM

A0-A9,

A11,12

A10

BS1

CAS

RAS

BS0

tRC tRC

tRAS tRP tRAS tRP

tRPtRAS tRAS

tRCD tRCD tRCD tRCD

tAC tAC tAC tAC

tRRD tRRD tRRD tRRD

Active Read

Active

Read

Precharge

RAa RBb RAc RBd RAe

RAa CAw RBb CBx RAc CAy RBd CBz RAe

aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3

Bank #0

Idle

Bank #1

Bank #2

Bank #3

W982516CH

- 20 -

Operating Timing Example, continued

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)

0123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

(CLK = 100 MHz)

CLK

CKE

DQM

A0-A9,

A11,12

A10

BS1

CAS

RAS

BS0

tRC tRC

tRC

tRAS tRP tRAS tRP

tRAS tRP tRAS

tRCD tRCD tRCD tRCD

tAC tAC tAC tAC

tRRD tRRD tRRD tRRD

Active Read

Active

Read

tRC

RAa RBb RAc RBd RAe

DQ aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0

* AP is the internal precharge start timing

Bank #0

Idle

Bank #1

Bank #2

Bank #3

AP*

AP* AP*

RAa CAw RBb CBx RAc CAy RBd RAe

CBz

W982516CH

Publication Release Date: Mar 2003

- 21 - Revision A1

Operating Timing Example, continued

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)

0123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

tRC tRC

tRC

tRAS tRP tRAS

tRP tRAS tRP

tRCD tRCD tRCD

tRRD tRRD

RAa

RAa CAx

RBb

RBb CBy

RAc

RAc CAz

ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 CZ0

(CLK = 100 MHz)

CLK

CKE

DQM

A0-A9,

A11,12

A10

BS0

CAS

RAS

BS1

Active Read

Precharge Active Read

Precharge Active

tAC tAC

Read

Precharge

tAC

Bank #0

Idle

Bank #1

Bank #2

Bank #3

W982516CH

- 22 -

Operating Timing Example, continued

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge)

0123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

tRC

tRAS tRP tRAS

tRAS tRP

tRCD tRCD tRCD

tRRD tRRD

ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 CZ0

RAa

CAx

RBb

RBb CBy

(CLK = 100 MHz)

RAc

RAc CAz

* AP is the internal precharge start timing

Active Read

Active

Active Read

tCAC tCAC

tCAC

CLK

CKE

DQM

A0-A9,

A11,12

A10

BS1

CAS

RAS

Bank #0

Idle

Bank #1

Bank #2

Bank #3

Read

AP*

BS0

W982516CH

Publication Release Date: Mar 2003

- 23 - Revision A1

Operating Timing Example, continued

Interleaved Bank Write (Burst Length = 8)

0123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

tRC

tRAS tRP

tRCD tRCD tRCD

tRRD tRRD

RAa

RAa CAx

RBb

RBb CBy

RAc

RAc CAz

ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2

(CLK = 100 MHz)

Write

Precharge

Active

Active Write

Precharge

Active Write

CLK

CKE

DQM

A0-A9,

A11,12

A10

BS0

CAS

RAS

BS1

Idle

Bank #0

Bank #1

Bank #2

Bank #3

tRAS

W982516CH

- 24 -

Operating Timing Example, continued

Interleaved Bank Write (Burst Length = 8, Autoprecharge)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

tRC

tRAS tRP tRAS

tRAS tRP

tRCD

RCD tRCD

tRRD tRRD

RAa

RAa CAx

RBb

RBb CBy

RAb

RAc

ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2

CAz

(CLK = 100 MHz)

* AP is the internal precharge start timing

CLK

CKE

DQM

A0-A9,

A11,12

A10

BS0

CAS

RAS

BS1

Active Write Write

Active

Bank #0

Idle

Bank #1

Bank #2

Bank #3

AP*

Active Write AP*

W982516CH

Publication Release Date: Mar 2003

- 25 - Revision A1

Operating Timing Example, continued

Page Mode Read (Burst Length = 4, CAS Latency = 3)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CCD

RAS

RCD

RRD

RAa

RAa CAI

RBb

RBb CBx CAy CAm CBz

a0 a1 a2 a3 bx0 bx1 Ay0 Ay1 Ay2 am0 am1 am2 bz0 bz1 bz2 bz3

(CLK = 100 MHz)

* AP is the internal precharge start timing

CLK

CKE

DQM

A0-A9,

A11,12

A10

BS0

CAS

RAS

BS1

Active Read

Read Read

Read

Precharge

Bank #0

Idle

Bank #1

Bank #2

Bank #3

AP*

W982516CH

- 26 -

Operating Timing Example, continued

Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)

0123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

RAS tRP

tRCD

tWR

RAa

RAa CAy

ax0 ax2 ax3 ax5 ay1 ay2 ay4

Q Q Q Q Q Q D DD

(CLK = 100 MHz)

CLK

CKE

DQM

A0-A9,

A11,12

A10

BS0

CAS

RAS

BS1

Active Read Write Precharge

tAC

Bank #0

Idle

Bank #1

Bank #2

Bank #3

W982516CH

Publication Release Date: Mar 2003

- 27 - Revision A1

Operating Timing Example, continued

Auto Precharge Read (Burst Length = 4, CAS Latency = 3)

0 1 2 4 5 7 8 10 11 13 14 16 17 19 20 22 23

(CLK = 100 MHz)

CLK

CKE

DQM

A0-A9,

A11,12

A10

BS1

CAS

RAS

BS0

tRC tRC

tRAS tRP tRAS tRP

tRCD RCD

tAC

Active Read AP* Active Read AP*

RAa

RAa CAw RAb CAx

aw0 aw1 aw2 aw3

* AP is the internal precharge start timing

Bank #0

Idle

Bank #1

Bank #2

Bank #3

tAC

bx0 bx1 bx2 bx3

W982516CH

- 28 -

Operating Timing Example, continued

Auto Precharge Write (Burst Length = 4)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

(CLK = 100 MHz)

CLK

CKE

DQM

A0-A9,

A11,12

A10

BS1

CAS

RAS

BS0

RAS

RAa

RCD

RAb RAc

RAa CAw RAb CAx RAc

aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3

Active

Active Write AP* Active Write AP*

* AP is the internal precharge start timing

Bank #0

Idle

Bank #1

Bank #2

Bank #3

W982516CH

Publication Release Date: Mar 2003

- 29 - Revision A1

Operating Timing Example, continued

Auto Refresh Cycle

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

(CLK = 100 MHz)

All Banks

Prechage Auto

Refresh Auto Refresh (Arbitrary Cycle)

tRCtRP tRC

CLK

CKE

DQM

A0-A9,

A11,12

A10

CAS

RAS

BS0,1

W982516CH

- 30 -

Operating Timing Example, continued

Self Refresh Cycle

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

(CLK = 100 MHz)

CLK

CKE

DQM

A0-A9,

A11,12

A10

BS0,1

CAS

RAS

CKS

All Banks

Precharge Self Refresh

Entry Arbitrary Cycle

Self Refresh Cycle

No Operation Cycle

W982516CH

Publication Release Date: Mar 2003

- 31 - Revision A1

Operating Timing Example, continued

Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

RAS

CAS

BS0

BS1

A10

A0-A9,

A11,12

DQM

CKE

(CLK = 100 MHz)

RCD

RBa

RBa CBv CBw CBx CBy CBz

av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3

Q Q Q Q D DD Q Q Q Q

Read Read

Single WriteActive

Bank #0

Idle

Bank #1

Bank #2

Bank #3

W982516CH

- 32 -

Operating Timing Example, continued

PowerDown Mode

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

(CLK = 100 MHz)

RAa CAa RAa CAx

RAa RAa

ax0 ax1 ax2 ax3

tSB

tCKS tCKS tCKS

tSB

tCKS

Active Standby

Power Down mode Precharge Standby

Power Down mode

Active NOP Precharge NOPActive

Note: The PowerDown Mode is entered by asserting CKE "low".

All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode.

When CKE goes high, command input must be No operation at next CLK rising edge.

CLK

CKE

DQM

A0-A9

A11,12

A10

CAS

RAS

Read

W982516CH

Publication Release Date: Mar 2003

- 33 - Revision A1

Operating Timing Example, continued

Autoprecharge Timing (Read Cycle)

Read AP

0 1110987654321

Read AP Act

Q1 Q2

AP ActRead

Act

(1) CAS

Latency=2

Read

Act

When the Auto precharge command is asserted, the period from Bank Activate command to

the start of internal precgarging must be at least t RAS(min).

represents the Read with Auto precharge command.

represents the start of internal precharging.

represents the Bank Activate command.

Note )

tRP

( a ) burst length = 1

Command

( b ) burst length = 2

Command

( c ) burst length = 4

Command

( d ) burst length = 8

Command

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

tRP

( a ) burst length = 1

Command

( b ) burst length = 2

Command

( c ) burst length = 4

Command

( d ) burst length = 8

Command

Read AP Act

Q1 Q2 Q3

Read AP Act

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

(2) CAS

Latency=3

tRP

W982516CH

- 34 -

Operating Timing Example, continued

Autoprecharge Timing (Write Cycle)

Act

0 1 32

(1) CAS Latency = 2

(a) burst length = 1

4 5 76 8 9 1110

Write

ActAP

Command

(b) burst length = 2

Write

ActAP

Command

tRP

Write

ActAP

Command

tRP

(d) burst length = 8

Write

ActAP

Command

tRP

D2 D3

D2 D3 D4 D5 D6 D7

(2) CAS Latency = 3

(a) burst length = 1

Write

ActAP

Command

(b) burst length = 2

Write

ActAP

Command

tRP

Write

ActAP

Command

tRP

(d) burst length = 8

Write

Command

tRP

D2 D3

D2 D3 D4 D5 D6 D7

tWR

Act

W982516CH

Publication Release Date: Mar 2003

- 35 - Revision A1

Operating Timing Example, continued

Timing Chart of Read to Write Cycle

Note: The Output data must be masked by DQM to avoid I/O conflict

1110987654321

(1) CAS Latency=2

In the case of Burst Length = 4

Read

Write

( b ) Command

DQM

D0 D1 D2 D3

( a ) Command

(2) CAS Latency=3

Read Write

D0 D1 D2 D3

( a ) Command

DQM

( b ) Command

DQM

D0 D1 D2 D3

Timing Chart of Write to Read Cycle

ReadWrite

01110987654321

Read

Q1 Q2 Q3

Read

Write

Q0 Q1 Q2 Q3

Write

Q0 Q1 Q2 Q3

D0 D1

( a ) Command

DQM

( b ) Command

DQM

( a ) Command

( b ) Command

DQM

In the case of Burst Length=4

(1) CAS Latency=2

(2) CAS Latency=3

D0 D1

Q0 Q1 Q2 Q3D0

W982516CH

- 36 -

Timing Chart of Burst Stop Cycle (Burst Stop Command)

Read BST

0 1110987654321

DQ Q0 Q1 Q2 Q3

BST

( a ) CAS latency =2

Command

( b )CAS latency = 3

(1) Read cycle

(2) Write cycle

Command

Read

Command

Q0 Q1 Q2 Q3 Q4

Write BST

Note: represents the Burst stop commandBST

Timing Chart of Burst Stop Cycle (Precharge Command)

W982516CH

Publication Release Date: Mar 2003

- 37 - Revision A1

0 1 111098765432

(1) Read cycle

(a) CAS latency =2

Command

Q0 Q1 Q2 Q3 Q4

PRCGRead

(b) CAS latency =3

Command

Q0 Q1 Q2 Q3 Q4

PRCGRead

(2) Write cycle

(a) CAS latency =2

Command

Q0 Q1 Q2 Q3 Q4

PRCG

Write

(b) CAS latency =3

Command

Q0 Q1 Q2 Q3 Q4

Write

DQM

PRCG

tWR

W982516CH

- 38 -

Operating Timing Example, continued

CKE/DQM Input Timing (Write Cycle)

5432

CKE MASK

( 1 )

D1 D6D5D3D2

CLK cycle No.

External

Internal

CKE

DQM

5432

( 2 )

D1 D6D5D3D2

CLK cycle No.

External

Internal

CKE

DQM

543

( 3 )

D1 D6

D5D4D3D2

CLK cycle No.

External

CKE

DQM

DQM MASK

DQM MASK CKE MASK

CKE MASK

Internal

CLK

W982516CH

Publication Release Date: Mar 2003

- 39 - Revision A1

Operating Timing Example, continued

CKE/DQM Input Timing (Read Cycle)

5432

( 1 )

CLK cycle No.

External

Internal

CKE

DQM

DQ Open Open

5432

CLK cycle No.

External

Internal

CKE

DQM

DQ Open

( 2 )

765432

CLK cycle No.

External

Internal

CKE

DQM

( 3 )

CLK

W982516CH

- 40 -

Operating Timing Example, continued

Self Refresh/Power Down Mode Exit Timing

Asynchronous Control

Input Buffer turn on time ( Power down mode exit time ) is specified by tCKS(min) + tCK(min)

Command

NOP

CLK

CKE

Command

A ) tCK < tCKS(min)+tCK(min)

Input Buffer Enable

Command

CLK

CKE

Command

B) tCK

>= tCKS(min) + tCK

(min)

Input Buffer Enable

Note )

Command

NOP

All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode

and Self Refresh mode

Represents the No-Operation command

Represents one command

tCK

CKS

(min)+t

(min)

CKS

(min)+t

(min)

W982516CH

Publication Release Date: Mar 2003

- 41 - Revision A1

PACKAGE DIMENSION

54L TSOP (II)-400 mil

SEATING PLANE

1 27

54 28

ZD 0.71 0.028

0.002

0.009

MAX.MIN. NOM.

0.24 1.00

0.05

0.40

1.20

0.15

SYM.

DIMENSION

(MM)

MAX.MIN. NOM.

e0.80 0.0315

0.016

L0.40 0.50 0.60 0.020 0.024

0.396

E10.06 10.16 10.26 0.400 0.404

0.871

D22.2222.12 22.62 0.875 0.905

0.039 0.016

0.047

0.006

DIMENSION

(INCH)

0.10 0.004

0.32

L1 0.80 0.032

c0.15 0.006

0.012

0.45511.7611.56 11.96 0.463 0.471

Y0.10 0.004

Controlling Dimension: Millimeters

W982516CH

- 42 -

Headquarters

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5796096

http://www.winbond.com.tw/

Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-27190505

FAX: 886-2-27197502

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

No. 378 Kwun Tong Rd;

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

Winbond Electronics North America Corp.

Winbond Memory Lab.

Winbond Microelectronics Corp.

Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.

TEL: 408-9436666

FAX: 408-5441798

Note: All data and specifications are subject to change withou t notice.

Headquarters

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5796096

http://www.winbond.com.tw/

Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-27190505

FAX: 886-2-27197502

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

No. 378 Kwun Tong Rd;

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

Winbond Electronics North America Corp.

Winbond Memory Lab.

Winbond Microelectronics Corp.

Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.

TEL: 408-9436666

FAX: 408-5441798

Note: All data and specifications are subject to change withou t notice.