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Table Of Contents
Page 2: Inputs.SCH
Page 5: Displays.SCH
Page 6: Datainfo.SCH
Page 1: Cover.SCH
Note: Unless otherwise stated the resistors are a 0805 package and 5% Tol.
Note: Unless otherwise stated the capacitors are a 0805 package and 10% Tol.
Page 8: Debug.SCH
Page 7: Ethernet.SCH
Page 3: MACH.SCH
NOTE: An asterisk (*) in front of a resistor or capacitor value
indicates a non populated component.
Page 4: Ports.SCH
TEST INTERFACE PORT
Schematics
7,3
REV 1.1
Sheet 2: Removed 1K pull down on AEN.
Added a Schottky Barrier Rectifier
to power supply circuit.
Sheet 3: Added TRESET net to MACH.
Changed resistor values of R10 and R11.
Sheet 5: Changed resistor R66 form 10K to 0 ohm.
Sheet 6: Changed resistors R84 - R91 from 10K to 1K.
Sheet 7: Ground AVSS1 on U26.
Sheet 8: Changed SW_IRQ# nodename to MAIN_IRQ.
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Added 1k pull up resistor to IOCHRDY signal.
REV 1.2
Sheet 3: Replace 74HC4072 OR gate with 74HC21 AND gate.
shared interrupt signals.
Removed pull down resistor R15 - R18 from
Added a pull up resistor to the PARINT signal.
Sheet 4: Added a pull up resistor to the PEMD signal.
while making the existing pull down resistor
an optional populate resistor.
Sheet 8: Routed IOCHRDY and TIPFLHCS# nets to debug header
© Copyright 1998 Advanced Micro Devices, Inc. All Rights Reserved
REV 1.3
Sheet 3: Removed resistor R17.
Replaced AND gates with OR gates.
Made the spare MACH I/O pin 61 accessible for use.
Cover.SCH
1.3
Test Interface Port (TIP)
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5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
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Friday, May 07, 1999
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