A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
Table Of Contents
Page 2: Inputs.SCH
Page 5: Displays.SCH
Page 6: Datainfo.SCH
Page 1: Cover.SCH
Note: Unless otherwise stated the resistors are a 0805 package and 5% Tol.
Note: Unless otherwise stated the capacitors are a 0805 package and 10% Tol.
Page 8: Debug.SCH
Page 7: Ethernet.SCH
Page 3: MACH.SCH
NOTE: An asterisk (*) in front of a resistor or capacitor value
indicates a non populated component.
Page 4: Ports.SCH
TEST INTERFACE PORT
Schematics
7,3
REV 1.1
Sheet 2: Removed 1K pull down on AEN.
Added a Schottky Barrier Rectifier
to power supply circuit.
Sheet 3: Added TRESET net to MACH.
Changed resistor values of R10 and R11.
Sheet 5: Changed resistor R66 form 10K to 0 ohm.
Sheet 6: Changed resistors R84 - R91 from 10K to 1K.
Sheet 7: Ground AVSS1 on U26.
Sheet 8: Changed SW_IRQ# nodename to MAIN_IRQ.
Advanced Micro Devices, Inc. ("AMD") reserves the right to discontinue its products,
or make changes in its products, at any time without notice.
The information in this publication is believed to be accurate at the time of publication,
but AMD makes no representations or warranties with respect to the accuracy or completeness
of the contents of this publication or the information contained herein, and reserves the
right to make changes at any time, without notice. AMD disclaims responsibility for any
consequences resulting from the use of the information included in this publication.
This publication neither states nor implies any representations or warranties of any kind,
including but not limited to, any implied warranty of merchantability or fitness for a
particular purpose. AMD’s products are not designed, intended, authorized or warranted for
use as components in systems intended for surgical implant into the body, or in other applications
intended to support or sustain life, or in any other application in which the failure of AMD’s
product could create a situation where personal injury, death, or severe property or environmental
damage may occur. AMD assumes no liability whatsoever for claims associated with the sale or use
(including the use of engineering samples) of AMD products except as provided in AMD’s
Terms and Conditions of Sale for such product.
Added 1k pull up resistor to IOCHRDY signal.
REV 1.2
Sheet 3: Replace 74HC4072 OR gate with 74HC21 AND gate.
shared interrupt signals.
Removed pull down resistor R15 - R18 from
Added a pull up resistor to the PARINT signal.
Sheet 4: Added a pull up resistor to the PEMD signal.
while making the existing pull down resistor
an optional populate resistor.
Sheet 8: Routed IOCHRDY and TIPFLHCS# nets to debug header
© Copyright 1998 Advanced Micro Devices, Inc. All Rights Reserved
REV 1.3
Sheet 3: Removed resistor R17.
Replaced AND gates with OR gates.
Made the spare MACH I/O pin 61 accessible for use.
Cover.SCH
1.3
Test Interface Port (TIP)
(C) Advanced Micro Devices, Inc. (800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
1
8
Friday, May 07, 1999
Title
Size Document Number Rev
Date: Sheet of
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
** NOTE **
31
BAT54
2/NC
Target boards should
use a pull down resistor
on pin 35 or a pull up
resistor on pin 37, for
auto detect of the TIP
being active
12
3
Barrel Connector
Top View
A 5V external power supply is
required to provide VCC to the
TIP board. But a host board
must be properly connected
to the TIP before the external
supply is allowed to power the
board.
NOTE:
24
13
Alcoswitch FSM4J
104068-6
12
59
Top View
60
Power Supply Circuit
Inputs.SCH
1.3
Test Interface Port (TIP)
(C) Advanced Micro Devices, Inc. (800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
2
8
Monday, April 26, 1999
Title
Size Document Number Rev
Date: Sheet of
U3INPOS
EVCC
DB2G#
A6
DB2DIR#
A5
D3
A8
A11
D1
D0
A10
D5
D7
A13
RD#
A7
A12
A4
D4
D2
A15
A14
D6
A9
A16
A0
A17
A3
A1
A19
A2
A18
SW_INTRP#
TRESET
FLASHWR#
EXTFLHCS#
TIPSEL
FLASHRD#
FLASHCS#
TIPSEL#
TRD# TRD#
MAIN_IRQ
HRESET#
TWR# TWR#
TS2TS2
TAEN TAEN
TD[7:0]
TD2
TD4
TD3
TD0
TD0
TD7
TD4
TD6
TD[7:0]
TD5
TD2
TD3
TD7
TD6
TD1
TD1
TD5
TA4
TA5
TA11
TA14
TA0
TA17
TA11
TA19
TA4
TA15
TA6
TA9
TA3
TA[19:0]
TA0
TA18
TA7
TA1
TA12
TA6
TA9
TA7
TA2
TA19
TA13
TA5
TA10
TA18
TA14
TA17
TA8
TA16
TA10
TA2
TA1
TA15
TA12
TA16
TA8
TA3
TA13
HRESET#
HVCC
HVCC
WR#
S2
AEN
SEL186
FET2
U3JMP
COMPAROUT
FET1
ALTOUT
HVCCRVCC
VCC5
VCC5
VCC5VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
R2 10K
U1
TI 74ACT16244DGGR
1
48 7
18
25
24 31
42
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
21
4
10
15
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
28
34
39
45
1OE#
2OE# VCC
VCC
3OE#
4OE# VCC
VCC
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
GND
GND
GND
GND
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
GND
GND
GND
GND
R3 10K
R1 10K
C5
0.1uF
C1
0.1uF
C7
0.1uF
C4
0.1uF
C2
0.1uF
C6
0.1uF
C3
0.1uF
C8
0.1uF
+
C10
10uF
C CASE, 16V
R9
10K
JP1
1
2
3
R8 1K
R10
3.3M
R11
1.2M
R13
10K
P2
KYCON KLD-0202-BC
DC POWER CONN
1
2
3
CENTER
SHUNT
SLEEVE
C11
0.1uF
SW2
FSM4J
1 3
R14
10K
D1
1 3
U2
TI 74ACT16245DGGR
47 2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
44
43
41
40
38
37
36
35
33
32
30
29
27
26
46
31
42
7
18
48
25
1
24
28
34
39
45
21
4
10
15
1A1 1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
1A2
VCC
VCC
VCC
VCC
1G#
2G#
1DIR
2DIR
GND
GND
GND
GND
GND
GND
GND
GND
R4 10K
R5 1K
P1
AMP 104068-6
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
60
58
1
3
5
7
9
GND
13
15
17
19
21
GND
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
VCC
VCC
2
4
6
8
10
GND
14
16
18
20
22
GND
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
60
58
SW1
FSM4J
13
U5
MOSFET (N-CHAN)
Temic Si9925DY
675
2
4
1
3
8
D2 D1D2
G1
G2
S1
S2
D1
R7 1K
U4
LINEAR LTC1155
MOSFET DRIVER
651 28 73
4
Vs IN2DS1 G1DS2 G2GND
IN1
R12
*0
U3
LINEAR LTC1540CMS8
COMPARATOR
4
3 5
2 6
1 8
7IN-
IN+ HYST
V- REF
GND OUT
V+
+
C9 10uF
C CASE, 16V
D2
21
A[19:0]
RD#
WR#
D[7:0]
TRESET
FLASHWR#
TIPFLHCS#
FLASHRD#
SERINT0
ENETIRQ
PARINT
SERINT1
IOCHRDY
AEN
TD[7:0]
HRESET#
MAIN_IRQ
DB2G#
DB2DIR#
S2
SW_INTRP#
SEL186
ALTOUT
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
4932 50
79
31
100
52
81
80
99
51
MACH-4
82
1
29
30
78
53
2
123456
74HC21
7
8
9
1011121314
REV 1.3
REV 1.3
WARNING: The peripheral interrupt signals on the TIP ar e u nt er mi nat ed .
As a result, software must ensure that each peripheral’ s interru pt is
enabled so that the interrupt input to the OR gat e driving th e M AI N_ IR Q
signal is not floatng. Alternatively, the t arget board may ut ilize p ul l-d own
resistors on the peripheral interrupt signals.
MACH.SCH
1.3
Test Interface Port (TIP)
(C) Advanced Micro Devices, Inc. (800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
38
Friday, May 07, 1999
Title
Size Document Number Rev
Date: Sheet of
D4
A12
A8
D7
D6
A10
A0
D3
A19
A3
D5
A9
A5
IOSPARE3D0
D7
D1
A15
A6
IOSPARE2
D0
A13
IOSPARE1
D1
A17
A7
A1
D6
D4
A14
A4
D3
D5
D2
A18
A11
A2
D2
SW_IRQ
A16
TMS
TDI
LOW
TDO
TCK
TRST
ENABLE
IOSPARE4
TP_IRQ
VCC5VCC5
VCC5
VCC5
VCC5
VCC5
C67
0.1uF
SP2
SP3
C15
0.1uF
C12
0.1uF
C13
0.1uF
C14
0.1uF
P3
3M 2510-6002UB
2
34
56
78
910
1
R19 1K
U7
VANTIS MACH4-128/64-12YC
56
58
59
60
61
62
69
70
71
72
73
75
82
84
85
86
87
88
93
94
95
96
97
99
6
8
9
10
11
12
19
20
21
22
23
25
32
34
35
36
37
38
43
44
45
46
47
49
13
18
26
54
63
68
76
4
3
28
53
78
1
2
16
17
29
30
40
41
51
52
66
67
79
80
90
91
5
7
24 27
31
33
48
50
55
57
74
77
81
83
98 100
14
15
39
42
64
65
89
92
I/O41
I/O43
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O54
I/O57
I/O59
I/O60
I/O61
I/O62
I/O63
I/O0
I/O1
I/O2
I/O3
I/O4
I/O6
I/O9
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
I/O18
I/O19
I/O20
I/O22
I/O25
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
I/O33
I/O34
I/O35
I/O36
I/O38
I0/CLK0
I1/CLK1
I/O23
I2
I3/CLK2
I4/CLK3
I/O55
I5
TDI
TCK
ENABLE
TDO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O8
I/O10
I/O21 TMS
I/O24
I/O26
I/O37
I/O39
I/O40
I/O42
I/O53
TRST
I/O56
I/O58
I/O5 I/O7
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
R117 10K
R118 1K
SP4
SP1
U6A
2
3
4
5
1
714
U6B
9
10
11
12
13
714
HEXCS0#
LEDCLK
SERCS1#
HEXCS1#
DIPSWOE#
SERCS0#
HDRLTCLK
LCDEN
LCDR/W
PARCS#
HDRBFOE#
LCDRS
HEXCS3#
LEDOE#
HEXCS2#
HDRLTOE#
A[19:0]
D[7:0]
DB2DIR#
DB2G#
RD#
WR#
AEN
S2
SW_INTRP#
TIPFLHCS#
FLASHRD#
FLASHWR#
SEL186
SELBIT
D[7:0]
TRESET
MAIN_IRQ
PARINT
ENETIRQ
SERINT1
SERINT0
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
2
4
1
5
6
9
8
7
3
Serial Connector
3
6
23
Connector
4
21
Component
19
17
Parallel
15
13
11
9
7
24
2
5
22
side view
20
18
25
16
14
12
10
1
8
1
EC2500ETT-8.00M
34
2
16
12 7
ASF42
With these resistors populated
the serial port is in DCE configuration.
NOTE: This is the default configuration
of the TIP board.
With these resistors populated
the serial port is in DCE configuration.
NOTE: This is the default configuration
of the TIP board.
1
26
7
38
49
To configure as DTE serial port, the
DCE resistors must be removed then
the below resistor must me populated.
DCE SERIAL CONFIGURATION
DTE SERIAL CONFIGURATION
NOTE:
ALCO
17
14 8
MC74ACT04
Ports.SCH
1.3
Test Interface Port (TIP)
(C) Advanced Micro Devices, Inc. (800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
4
8
Monday, April 26, 1999
Title
Size Document Number Rev
Date: Sheet of
PARSLCT
SER_CTS0#
PARPE
PARPD5
PARPD4
PARPD3
PARSLIN#
PARBUSY
PARPD2
PARNIT#
SER_SOUT0
PARACK#
PARPD6
PARPD1
SER_SIN0
SER_RTS0#
PARERR#
PARPD0
PARPD7
PARAFD#
PARSTB#
D0
RESET#
PEMD
ENIRQ
CLK8MHZ
SER_SOUT1
SER_RTS1#
SER_CTS1#
SER_SIN1
SER1VM
SER_DTR1#
SER_DSR1#
SER_DTR0#
D1
D6
D4
D5
D7
D2
D3
SER_A2
A1
A0
A2
A1A2
A3
SER_A2
SER_A1
SER_A0
SER_A1
SER_A0
SW3LOW
SW3HIGH
SER1C1P
SER1C1M
SER1VP
SER1C2P
SER1C2M
SER_DCD1#
DTR1#_C
SOUT1_C
CTS1#_CCTS1#_T SIN1_C
RTS1#_C
RI1#
SOUT1_T
SER_RI1#
SER0C1P
SER0VM
SER0C1M
SER0C2M
SER0VP
SER0C2P
SER_DSR0#
SER_DCD0#
SER_RI0#
SIN0_T
DSR0#_T
SOUT0_T
CTS0#_T
RTS0#_T
DTR1#_T
DCD1#_T
SIN1_T
RTS1#_T
DSR1#_T
DTR0#_C
SOUT0_C
CTS0#_C
SIN0_C
RTS0#_C
DSR0#_C
CTS0#_C
SIN0_C
DTR0#_C
RTS0#_C
SOUT0_C
DSR0#_C
CTS1#_C
SIN1_C
DTR1#_C
DSR1#_C
RTS1#_C
SOUT1_C
DSR1#_T
DCD1#_T
SIN1_T
RTS1#_T
SOUT1_T
CTS1#_T
DTR1#_T
DSR0#_T
DCD0#_T
SIN0_T
RTS0#_T
SOUT0_T
CTS0#_T
DTR0#_T
DCD0#_C
DTR0#_T
DCD0#_T
DCD1#_C
DCD1#_C
DCD0#_C
RMRESET0RI0#
DSR1#_C
RMRESET1
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5 P4
AMP 747846-2
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
C22
0.1uF
R21
0
R18
0
C25
0.1uF
Y1
ECLIPTEK EC2500-8.3300M
1
2 3
4
OE
GND OUT
VCC
C18
0.1uF
C19
0.1uF C20
0.1uF
U11A
1 2
147
R33
*0
C23
0.1uF
R23 10K
R22
10K
U9
TI TL16C552FN
53
52
51
50
49
48
47
46
68
66
67
65
29
31
41
24
26
28
25
30
8
5
62
12
10
13
11
6
14
15
16
17
18
19
20
21
1
43
38
55
56
63
57
58
35
34
33
36
37
4
39
60
61
42
3
2
59
44
45
9
22
32
64
40 7
27
54
23
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
ACK#
BUSY
PE
SLCT
DCD0#
DSR0#
SIN0
RTS0#
SOUT0
CTS0#
DTR0#
RI0#
DCD1#
DSR1#
SIN1
RTS1#
SOUT1
CTS1#
DTR1#
RI1#
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
PEMD
ENIRQ
CS2#
STB#
AFD#
ERR#
INIT#
SLIN#
A0
A1
A2
IOW#
IOR#
CLK
RESET#
INT1
RXRDY1#
TXRDY1#
CS1#
TRI
INT2
BDO
INT0
RXRDY0#
TXRDY0#
CS0#
VDD
VDD GND
GND
GND
VDD
C21
0.1uF
C24
0.1uF
P5
AMP 747844-5
5
9
4
8
3
7
2
6
1
R27 0
R26 0
R28 0
R29 0
R30 0
R31 0
R24 0
C28
0.1uF
C27
0.1uF R43
*0
C29
0.1uF
C26
0.1uF
U10
Sipex SP211CA
2
3
45
6
7
8 9
10 11
12 13
14
15
16
17
19
20
21
22 23
24
25
26 27
1
28
18
T1OUT
T2OUT
R2INR2OUT
T2IN
T1IN
R1OUT R1IN
GND VCC
C1+ V+
C1-
C2+
C2-
V-
R5OUT
T3IN
T4IN
R4OUT R4IN
EN#
SD
R3OUT R3IN
T3OUT
T4OUT
R5IN
R37 0
R36 0
R38 0
R39 0
R40 0
R41 0
R34 0
R51 *0
R57 *0
R54 *0
R52 *0
R55 *0
R53 *0
R56 *0
R44 *0
R50 *0
R47 *0
R45 *0
R48 *0
R46 *0
R49 *0
R35 0
R25 0
U12
Sipex SP211CA
2
3
45
6
7
8 9
10 11
12 13
14
15
16
17
19
20
21
22 23
24
25
26 27
1
28
18
T1OUT
T2OUT
R2INR2OUT
T2IN
T1IN
R1OUT R1IN
GND VCC
C1+ V+
C1-
C2+
C2-
V-
R5OUT
T3IN
T4IN
R4OUT R4IN
EN#
SD
R3OUT R3IN
T3OUT
T4OUT
R5IN
P6
AMP 747844-5
5
9
4
8
3
7
2
6
1
SW3
ASF42
2
4
6
10
12111
5
39
8
7
C1
1
2
2
11 C4
C2
21
C3
2
R32 0
R42 0
R20
*0
D[7:0]
SERCS1#
PARCS#
SERCS0#
WR#
RD#
A[19:0]
TRESET
SERINT0
SERINT1
PARINT
HRESET#
SELBIT
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
15
1
Top View
2
16
MDLS-20265
GND
GND
U18
U17
U19 U20 U16U15 U14U13
1
2
3
4
5
78
10
12
13
14
TOP VIEW
TIL311
SPARES
F L A S H
L C D
Displays.SCH
1.3
Test Interface Port (TIP)
(C) Advanced Micro Devices, Inc. (800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
5
8
Monday, April 26, 1999
Title
Size Document Number Rev
Date: Sheet of
LDC2H LDC2L
LDC0L
LDC0H
HEXCS2#
HEXCS0#
LDC3H
HEXCS1#
HEXCS3#
LDC3L
LDC1L
LDC1H
A17
A6
A14
A16
A2
A8
A10
A13
A1
A5
A9
A15
A18
A7
A11
A4
A3
A12
A0
VCCSW20
U21VO
VCCSW20
D2
D3
D6
D6
D5
D1
D6
D5
D4
D7
D3
D0
D2
D5
D2
D1
D6
D6
D4
D0
D1D1
D2
D0
D0
D[7:0]
D4
D7
D7
D3
D6
D4
D5
D7
D4
D2
D5
D5
D4
D1
D1
D7
D3
D0
D0
D7
D3
D3
D2
VCC5VCC5 VCC5VCC5
VCC5 VCC5 VCC5VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5
R59
330 R61
330
R65
330
R58
330
R63
330
U17
TI TIL311
14
7
3
2
13
12
1
5
8
4
10
6
9
11
VCC
GND
DA
DB
DC
DD
LED
STRB
BLNK
LDC
RDC
NC
NC
NC
U21
VL ELELCTRICS MDLS-20265K-LV-G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
VDD
VO
RS
R/W
E
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
*SP2
*SPARE_20
2
4
6
811
13
15
17
1 19
18
16
14
12
9
7
5
3
20
10
A2
A4
A6
A8 Y9
Y7
Y5
Y3
A1 Y1
Y2
Y4
Y6
Y8
A9
A7
A5
A3
VCC
GND
*SP1
*SPARE_14
2
4
6
11
131
14
12
7
5
310
09
08
A2
A4
A6
Y4
Y6A1
VCC
Y5
GND
A5
A3 Y3
Y2
Y1
JP2
HEADER, 1
1
JP3
HEADER, 1
1
C39
0.1uF
U22
AMD AM29F002T
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
22
24
31
1
13
14
15
17
18
19
20
21
32
16
30
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
CE
OE
WE
A18
D0
D1
D2
D3
D4
D5
D6
D7
VCC
GND
A17
C34
0.1uF C35
0.1uF
C36
0.1uF C37
0.1uF
C32
0.1uF C33
0.1uF
C30
0.1uF C31
0.1uF
U18
TI TIL311
14
7
3
2
13
12
1
5
8
4
10
6
9
11
VCC
GND
DA
DB
DC
DD
LED
STRB
BLNK
LDC
RDC
NC
NC
NC
U14
TI TIL311
14
7
3
2
13
12
1
5
8
4
10
6
9
11
VCC
GND
DA
DB
DC
DD
LED
STRB
BLNK
LDC
RDC
NC
NC
NC
U13
TI TIL311
14
7
3
2
13
12
1
5
8
4
10
6
9
11
VCC
GND
DA
DB
DC
DD
LED
STRB
BLNK
LDC
RDC
NC
NC
NC
U15
TI TIL311
14
7
3
2
13
12
1
5
8
4
10
6
9
11
VCC
GND
DA
DB
DC
DD
LED
STRB
BLNK
LDC
RDC
NC
NC
NC
U19
TI TIL311
14
7
3
2
13
12
1
5
8
4
10
6
9
11
VCC
GND
DA
DB
DC
DD
LED
STRB
BLNK
LDC
RDC
NC
NC
NC
U16
TI TIL311
14
7
3
2
13
12
1
5
8
4
10
6
9
11
VCC
GND
DA
DB
DC
DD
LED
STRB
BLNK
LDC
RDC
NC
NC
NC
C38
0.1uF
20K POTENTIOMETER
R67
13
2
R62
330
U20
TI TIL311
14
7
3
2
13
12
1
5
8
4
10
6
9
11
VCC
GND
DA
DB
DC
DD
LED
STRB
BLNK
LDC
RDC
NC
NC
NC
R66
0
R60
330
R64
330
HEXCS0# HEXCS1#
LCDEN
LCDRS
LCDR/W
HEXCS2# HEXCS3#
FLASHRD#
D[7:0]
A[19:0]
TIPFLHCS#
FLASHWR#
D[7:0]
D[7:0]
ALTOUT
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
SSL-LX15YGC-RP
19
20
Top View
1
2
2 X 10
HEADER
YEL
SSL-LX15YGC-RP
3
GRN
1
CATH
2
0|
116
SW OPS of AMP 3-435650-9
0|
DataInfo.SCH
1.3
Test Interface Port (TIP)
(C) Advanced Micro Devices, Inc. (800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
6
8
Monday, April 26, 1999
Title
Size Document Number Rev
Date: Sheet of
INPDSW1
OUTHDR3
OUTHDR1
OUTHDR2
OUTHDR6
OUTHDR7
OUTHDR5
OUTHDR4
OUTHDR0
CRLN3
LED6
LED2
CRLN2
CRLN5
LED1
LED2
LED5
LED3
CRLN6
LED5
LED4
CRLN8
LED0
LED4
LED3
CRLN7
LED1
CRLN4
LED7
LED7
CRLN1
LED0
LED6
LED6
LED7
LED1
LED0
LED3
LED5
LED2
LED4
OUTHDR3
OUTHDR6
OUTHDR2
OUTHDR4
OUTHDR1
OUTHDR5
OUTHDR7
OUTHDR0
D4
D6
D1
D3
D5
D2
D7
D0
D6
D7
D5
D0
D4
D3
D1
D2
LED[7:0]
D1
D0
D2
D0
D4
D5
D7
D4
D5
D1D6
D1
D4
D2 D2
D3 D3
D0
D7
D1
D3D4
D6
D5
D7
D6
D3
D7
D6
D0
D5D2
INPHDR7
INPHDR6
INPHDR5
INPHDR4
INPHDR2
INPHDR1
INPHDR0
OUTHDR1
OUTHDR6
OUTHDR2
OUTHDR3
OUTHDR4
OUTHDR5
OUTHDR7
OUTHDR0
OUTHDR[7:0]
OUTHDR[7:0]
INPHDR3
INPDSW2
INPDSW4
INPDSW3
INPDSW5
INPDSW6
INPDSW7
INPDSW0
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5 VCC5
VCC5
R68 220
R70 220
R80 220
R83 220
R81 220
R69 220
R82 220
R71 220
R76 10K
R78 10K
R79 10K
R73 10K
R72 10K
R75 10K
R77 10K
R74 10K
C48
0.1uF
C50
0.1uF
C49
0.1uF
C51
0.1uF
C42
0.1uF
C40
0.1uF
C43
0.1uF
C41
0.1uF
C46
0.1uF
C44
0.1uF
C47
0.1uF
C45
0.1uF
U24
TI 74ACT16244DGGR
1
48 7
18
25
24 31
42
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
21
4
10
15
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
28
34
39
45
1OE#
2OE# VCC
VCC
3OE#
4OE# VCC
VCC
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
GND
GND
GND
GND
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
GND
GND
GND
GND
U23
TI 74ACT16244DGGR
1
48
7
18 25
24
31
42
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
21
4
10
15
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
28
34
39
45
1OE#
2OE#
VCC
VCC 3OE#
4OE#
VCC
VCC
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
GND
GND
GND
GND
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
GND
GND
GND
GND
CR1
2 3
CR2
2 3
P7
AMP 103308-5
2
34
56
78
910
11 12
13 14
15 16
17 18
19 20
1
SW4
AMP 3-435640-9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
U25
TI 74ACT16373DW
48
25
4
10
15
21
28
34
39
45
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
7
18
31
42
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1
24
1LE
2LE
GND
GND
GND
GND
GND
GND
GND
GND
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
VCC
VCC
VCC
VCC
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
10E#
2OE#
R84 1K
R85 1K
R86 1K
R87 1K
R88 1K
R89 1K
R90 1K
R91 1K
CR3
2 3
CR4
2 3
CR5
2 3
CR6
2 3
CR7
2 3
CR8
2 3
D[7:0]
HDRBFOE#
LEDCLK
HDRLTCLK
DIPSWOE#
HDRLTOE#
LEDOE#
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
The main outer pin-out is for
the AM79C961A (TQFP 144)
configured in the BUS SLAVE
mode. The pin names in "[]"
are for the the device
configured in the BUS MASTER
mode.
55659-1
ECCM63-50-20.000MTR
Mounting Hole Layout
47
Front View
618325
SSL-LX15YGC-RP
SSL-LX15YGC-RP
2
1
3
YEL
CATH
GRN
Top View
28
7
From component side
Top View
1
NOTE:
For anolog decoupling, the boxed in area should be
routed as shown, and the capacitors should be con-
nected to the prescribed pins, not vias.
Ethernet.SCH
1.3
Test Interface Port (TIP)
(C) Advanced Micro Devices, Inc. (800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
78
Monday, April 26, 1999
Title
Size Document Number Rev
Date: Sheet of
RESLED0
RESLED1
RESLED2
RESLED3
TDPOS
TDNEG
RDPOS
RDNEG
CINCIP
PRDB[7:0]
AUDX1AUDX2
PRDB1
PRAB2
A10
TXDNEG
ENETLED3
PRAB5
PRAB8
PRAB0
A5
IRQ4
CI
PRDB7
SMAM#
PRAB3
PRAB14
PRAB12
SHBE#
IRQ11
PRDB7
D7
D1
PRAB12
PRAB11
TXNEG
PRAB1
PRAB4
PRAB2
PRDB2
SHFBUSY
CINEG
PRDB2
REF#
A14
A13
A6
A1
A0
IRQ5
DI
PRDB4 PRDB1
D5
PRAB9
PRAB1
A9
SRCS#
ENETLED1
ENETLED0
PRAB10
PRDB3
D0
A11
RXPOS
SRAMOE#
A7
TXDPOS
PRAB13
PRAB8
D6
PRAB13
A2
IRQ10
PRDB0
MEMR#
RXNEG
D3
D2
PRAB7
BPAM#
A3
PRDB3
PRDB5
PRDB0
PRDB6
PRDB4
D4
PRAB10
SMA#
A12
A8
A4
IRQ9
DIPOS
PRAB7
PRDB5
IRQ15
SLEEP#
MEMW#
PRAB9
DINDIP
PRAB14
SRWE#
PRAB11
PRAB6
PRAB0
IRQ3
EECS
A15 TXPOS
ENETLED2
PRDB6
AVSS2
PRAB6
PRAB[14:0]
PRAB5
PRAB4
PRAB3
FILTAVDD
GND
AVSS2
IOCHRDY
VCC5
VCC5
VCC5
VCC5
VCC5
VCC5VCC5
VCC5 VCC5
VCC5
R111
330
R114
330
R109
330
R110
330
C53
33pf
X1
C52
33pf
C62
0.1uF
R112 40.2 R113 40.2
R11540.2
R98
0
R96
*0
R94
*0
R92
*0
R95
*0
R97
*0
R93
*0
R100
10K
CR9 13
R11640.2
R101
10K
U28
NATIONAL SEMI NM93C56N
3
4
1
2 8
7
5
6
DI
DO
CS
SK VCC
NC
GND
NC
R108
0
C63 0.1uF
R103
1K
R104
1K
R102
1K
R106
1K
R105
1K
C65
0.1uF
C64
0.1uF
R107
1K
P8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
CR10 13
CR11 13
CR12 13
C54
0.1uF
C60
0.1uF
C56
0.1uF
C55
0.1uF
C57
0.1uF
U29
TOSHIBA TC55257DFTI-70V
17
26
24
22
19
15
13
11
4
28
9
8
16
14
12
10
3
2
5
18
20
23
25
6
1
27 7
21
A0
I/O8
I/O6
I/O4
I/O2
A2
A4
A6
A8
A10
A12
A14
A1
A3
A5
A7
A9
A11
A13
I/O1
I/O3
I/O5
I/O7
R/W
OE#
CE# VCC
VSS
U27 Pulse E2003
3
1
4
2
14
16
8
6
9
11
5
12
15
TDX-
TDX+
TXP-
TXP+
RXD-
RXD+
TD+
TD-
RD+
RD-
5
12
15
L1
C59
0.1uF
C58
0.1uF
C61
22uF
C CASE, 16
R99
4.7
U26
AMD AM79C961AVC
104
106
58
49
71
65
47
119
136
124
123
121
120
117
116
115
114
112
111
100
102
99
101
96
97
2
7
15
24
32
43
52
64
80
90
95
122
130
105
110
66
60
61
62
69
57
55
54
4
5
6
8
9
10
11
12
13
14
16
17
18
44
45
46
3
70
48
59
19
67
68
51
50
63
75
53
21
22
23
25
26
27
28
29
30
31
33
34
39
40
41
42
76
78
81
83
86
88
91
93
77
79
82
84
87
89
92
94
20
38
56
74
85
125
142
98
103
113
118
1
35
36
37
72
73
107
108
109
143
144
131
129
128
127
126
139
140
138
141
135
137
132
133
134
XTAL1
XTAL2
IOCS16#
IOCHRDY
[NC] PCMCIA_MODE
[DRQ3] SROE#
[SA19] SRWE#
DXCVR/EAR#
BPCS#
LED0
LED1
LED2
LED3
CI+
CI-
DI+
DI-
DO+
DO-
TXD-
TXD+
TXPD-
TXPD+
RXD-
RXD+
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
AVSS2
AVSS1
SMAM# [DACK3#]
IRQ3
IRQ4
IRQ5
IRQ9
IRQ10
IRQ11
[FLashWE#] IRQ12
SA0 [DRQ7]
SA1 [DRQ6]
SA2 [DRQ5]
SA3 [DACK7#]
SA4 [DACK6#]
SA5 [DACK5#]
SA6 [LA17]
SA7 [LA18]
SA8 [LA19]
SA9 [LA20]
SA10 [LA21]
SA11 [SA22]
SA12 [SA23]
SA13 [SA16]
SA14 [SA17]
SA15 [SA18]
SMA# [MASTER#]
RESET
AEN
BPAM#
SBHE#
IOR#
IOW#
MEMR#
MEMW#
REF#
SLEEP#
IRQ15
PRAB0 [SA0]
PRAB1 [SA1]
PRAB2 [SA2]
PRAB3 [SA3]
PRAB4 [SA4]
PRAB5 [SA5]
PRAB6 [SA6]
PRAB7 [SA7]
PRAB8 [SA8]
PRAB9 [SA9]
PRAB10 [SA10]
PRAB11 [SA11]
PRAB12 [SA12]
PRAB13 [SA13]
PRAB14 [SA14]
PRAB15 [SA15]
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
AVDD
AVDD3
AVDD
AVDD2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PRDB3
PRDB4
PRDB5
PRDB6
PRDB7
TDO
TMS
TDI
TCK
SHFBUSY
EECS
PRDB2/EEDO
PRDB1/EEDI
PRDBO/EESK
C66
0.1uF
R119
1K
A[19:0]
D[7:0]
IOCHRDY
WR#
AEN
TRESET
RD#
ENETIRQ
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
HP Conn.
12
19 20
Top View
SN74ACT04PW
SPARES
Debug.SCH
1.3
Test Interface Port (TIP)
(C) Advanced Micro Devices, Inc. (800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
8
8
Monday, April 26, 1999
Title
Size Document Number Rev
Date: Sheet of
A2
A15
A13
A11
A9
A7
A5
A3
A1
A12
A6
A8
A14
A10
A4
A18
A16 A17
A19
A0
SPRD SPRE SPRF
SPRCSPRB
AEN
TD0
WR#
RD#
TD5
TD2
TD7
TD4
S2
TD1
TD3
TD6
VCC5 VCC5
VCC5
VCC5
VCC5
P10
HEADER, 2 X 10
AMP 103308-5
2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
1CLK2
CLK1 D15
D14 D13
D12 D11
D10 D9
D8 D7
D6 D5
D4 D3
D2 D1
D0 GND
+5V
P9
HEADER, 2 X 10
AMP 103308-5
2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
1CLK2
CLK1 D15
D14 D13
D12 D11
D10 D9
D8 D7
D6 D5
D4 D3
D2 D1
D0 GND
+5V
U11D
9 8
147
U11F
1312
147
U11C
56
147
U11B
3 4
147
U11E
11 10
147
S1
1 2
S3
1 2 S5
1 2
S2
1 2
S4
1 2
P11
HEADER, 2 X 10
AMP 103308-5
2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
1CLK2
CLK1 D15
D14 D13
D12 D11
D10 D9
D8 D7
D6 D5
D4 D3
D2 D1
D0 GND
+5V
A[19:0]
TD[7:0]
RD#
WR#
AEN
S2
SERINT0
SERINT1
SERCS0#
SERCS1#
PARCS#
MAIN_IRQ
HRESET#
FLASHRD#
PARINT
ENETIRQ
FLASHWR#
IOCHRDY
TIPFLHCS#