Altera Corporation 901
AN 76: Understanding FLEX 8000 Timing
t
ZX3
Output buffer enable delay with the slow slew rate logic
option turned on and V
CCIO
= 5.0 V or 3.3 V. The delay
required for the output signal to appear at the output pin
after the tri-state buffer’s enable control is enabled.
Interconnect Timing Parameters
The following list defines the interconnect timing parameters for the
FLEX 8000 device family.
t
DIN_D
Dedicated input data delay. The time required for a signal
(used as a data input) to reach a logic element (LE) from a
dedicated input pin. The
t
DIN_D
delay is a function of
fan-out and the distance between the source pin and
destination LEs. The value shown in the
FLEX 8000
Programmable Logic Device Family Data Sheet
is the longest
delay possible for a pin with a fan-out of four LEs. However,
the value generated by the MAX+PLUS II Timing Analyzer
is more accurate because it includes considerations of the
fan-out and the relative locations of the source pin and
destination LEs of the design.
t
DIN_C
Dedicated input control delay. The delay of a signal coming
from a dedicated input pin that is used as an LE register
control. These signals include the clock, clear, and preset
inputs to the LE register.
t
DIN_IO
Dedicated input I/O control delay. The delay of a signal
from a dedicated input pin that is used as an IOE register
control. These signals include the clock and clear inputs to
the IOE register and the output enable control of the IOE’s
tri-state buffer.
t
COL
FastTrack Interconnect column delay. The delay incurred by
a signal that requires routing through a column channel in
the FastTrack Interconnect.
t
ROW
FastTrack Interconnect row delay. The delay incurred by a
signal that requires routing through a row channel in the
FastTrack Interconnect. The
t
ROW
delay is a function of
fan-out and the distance between the source and destination
LEs. The value shown in the
FLEX 8000 Programmable Logic
Device Family Data Sheet
is the longest delay possible for an
LE with a fan-out of four LEs. However, the value generated
by the MAX+PLUS II Timing Analyzer is more accurate
because it includes considerations of the fan-out and the
relative locations of the source and destination LEs of the
design.