MICROPROCESSOR WITH CLOCK AND OPTIONAL RAM The MC6802 is a monolithic 8-bit microprocessor registers and accumulators of the present MC68~ oscillator and dtiver on the same chip, In addition, bytes of on-board RAM located at hex addresses first 32 bytes of RAM, in a low power at hex addresses mode by utilizing $~0 VCC that contains all the plus an internal clock the MC8802 has 128 $0000 to $O07F. The to $001 F, maybe standby; thus, retained facilitating memory retention during a power-down situation. The MC6802 is completely software compatible with' the MC68W as well as the entire M68~ family of parts. Hence, the MC6802 is expandable to ~K words, The M C~02NS is identical to the M C6802 without standby RAM feature. The MC~08 is identical to the MC6802 without on-board RAM. 0 On-Chip Clock Circuit PIN ASSIGNMENT -n Vss -- -- 1 g 40 RESET HALT 2 3g EXTAL MR 3 38 XTAL FQ [ 4 37 E VMA[ 5 36 ] RE*' NMI[ 6 35 J VCC BA[ ? w JR/~ 8 33 ] DO Vcc[ m+'~ .>..+,. t:. *\i?,}, * ~,,s.\t:.-{~\,.,. `::;/,. .;+ Parallel 1/0 Cso - VMA VMA Clock 2 k Bytes ROM 10 1/0 Lines 3 Unes Timer DO-D7 DO-D7 A2 [ 11 30 ~ D3 29 ] D4 R`w M C6802 ml MPU ~A DO-D7 EXTAL ~ A4 [ 13 28 ] D5 A5 [ 14 27 ] D6 -- { o CP2 CP1 AO-A1 O, Csl AO-A15 31 ] D2 A3 [ 12 g Control 32 ]Dl Al [ 10 RE - E RIF HA.LT -~ -- AO ~ 9 AO-A15 XTAL - This block diagram shows a tvpical cost effective microcomputer. The M PU is the center of the microcomputer system and is shown in a minimum svstem interfacing with a ROM combination chip, It is not intended that this system be limited to this function but that it be expandable with other parts in the M6800 Microcomputer family. A6 [ 15 26 ] D7 A7 [ 16 25 ]A15 A8 [ 77 24 1 A14 A9 [ 18 23 ]A13 A1O [ 19 22 ]A12 All[ 21 IVss 20 Standby' pifl 35 mUSt be tied to 5 v on the 6802NS *Pin 36 must be tied to around for the 6808 MOTOROLA INC., 19S1 Ds-9al&R2 OPERATING TEMPERATURE RANGE Device Speed Symbol Value Unit TA Oto +70 -40to +85 `c TA Oto +70 -40to +85 TA Oto +70 _@to +85 MC6802P, L MC6802CP,CL (1.0 MHz) (1.0 MHz) MC68A02P, L MC68A02CP,CL (1.5 MHz) (1.5 MHz) MC68B02P,L MC68802CP,CL (2.0 MHz) (2.0 MHz) MC6802NSP, L (1.0 MHz) TA MC6808P, L MC68A08P, L MC68808P,L (1.0 MHz) (1.5 MHz) (2.0 MHz) TA DC ELECTRICAL CHARACTERISTICS (Vcc= sy.@ol Looic. EXTAL I `:a+tJi>* - -- max) uutput Hlgn voltage (i LOad= - 205pA, VCC= rein] (lLoad= - 145pA, VCC= rein) (lLoad=- 100 PA, VCC=min) wi'P%:$t ,,*,, = n"f ,, r Min I v<<+ 2.0 , v:; +4.0 I Typ I : Max Unit Vcc Vcc v Vs S-0,3 - VSS+O.8 v - 1.0 2.5 VA - V I - - - -- VSS+2.4 VSS+2.4 VSS+2.4 vOH vOL D,. I "$ I Logic, EXTAL, w~ ~,$~[L ,.. ..':' Ii" L&Mc I .....+ ,!$~,**,.:. ,~'QO-D7 AO-A~5>@l~j VMA, E ..,,.,!-' ,+~ ,, ., ,>,<3,, \\,,`J)y>>, BA ,,,,,. *.:$?~..`.~ Output Low Voltage .(l Load= 1.6 mA, VCC= rein} Internal Power Dissipation (Meas!jred at T A Oc ,,,\ tg ~ ,:,,\I ~ $,*:.~$?,. 5.o Vdc + 5%, VSS =0, TA=O to 700C, unl*+&~,~?wise noted) I--,p",,+u; "h , \/-l.--,t, , ,,~, v"l Lagc 5.25 V, Vcc= o to + 7q~'':i:~>,"w ,\ .,., $;. l;,< :$,{,.>:,..$,.,,, o t$,;~z{px ..,,. ~,~. , . ,.l\:..\' `~s.~ .,> .+'~e::$ ,\,:>., , *+.:.t.~\\, *\?{v .:!!;.::,"~~: . .\ ,Y. .+.?. "t ~cl Characteristic Input Low Voltage ,., -,,, lnpu~ LeaKage Lurrent (Vi" =Uto `c "?. ,;$$>,g, - .-- v VSS+O.4 0.600 ,T w 1,0 t:il . In power-down mode, maximu~~*$~issipation .,4* is less than 42 mW. #Capacitances are periodically s&p'l@ rather than 100% tested, ~..~,:,,<,t~! .,,+ ~~~.'. e!.$,~ ~. \,>h \\/::, >,, .\,::; .e,.,$> CONTROL TIM ING,$$@gc=<&o V +5%, VSS =0, TA= TL to TH, unless otherwise noted) , ,!.:,$,., ~~ .:,:,, ,,)i ~;r' r.:\, . :\.* ,.,,:~' ., .. .>~i., \'\,l,.,,7J ,.,`J)!*. ~..il.~ ~~,i,t%> .t~~ Characteristics Symbol Frequenc$~?@eration Cryst~ Fr~kncy cillator Frequencv MC6B02NS, MC6B08 Min Max MC6BA02 McmBo2 f. 0.1 1.0 0.1 1.5 I 0.1 2.0 MHz fXTAL 1.0 4.0 1.0 I 6.0 I 1.0 8.0 I MHz 4xfo 0.4 4.0 0.4 6.0 0.4 8.0 MHz tr~ 100 - 100 - 100 - ms tpcs 200 - 140 - 110 - ns tPCr, _ 100 -- RE, RESET, ~~) Processor Control Rise and Fall Time (Does Not Applv to RESET) tPcf MOTOROLA Semiconductor @ 3 Products - 100 I Inc. I 100 I ns I FIGURE 3 - BUS TIMING TEST LOAD 4,75 v ? C=130 pF for DO-D7, E =90 PF for AO-A15, R/~, and VMA =30 pF for BA R= I1.7 kQ for DO-D7, E = 16.5 kQ for AO-A15, RI=, and VMA =24 k~ for BA `estpointti~~~~ FIGURE 4 - TYPICAL DATA BUS OUTPUT DELAY versus CAPACITIVE LOADING 600 [ - I I I lo H=-205@max@2.4V 10 L=l.6mAmax@0.4V 500 -VCC=5,0V - TA = 25C ~ . u z F > ~ 400 300 / / : ` ` 200 / ` / I 100 CL includes stray capacitance , 600 o 0 100 200 400 300 500 a we B 35 32 BVtes ---------- 96 Bytes L---- ~_ --__ _ J Program mm Counter Stack Pointer ~ L Index Register * ~ "7 Instruction [ Accumulator Register B Co;:jon Register II VCC= VCC = Pin VSS= Pins Vss Data Pin 8 35 for MC6802NS 1, 21 = Pin 36 for ALU Buffer [ MCW08 26 27 $#t!#$ 28 29 30 31 D7 D6 D5 D3 D2 MOTOROLA D4 32 D1 33 DO Semiconductor @ .5 Products Inc. VCC StandbV Not Available on MC6808 ... . . .. . . .. . ,:. : ,, :,. : :., . ..... .... .. :,,,.y..,, >-. .;,;,.-.-.;.:: :. ,.,-~. ,. :,. , ,,, : ;-.,-'~,;, .,., ., ... .. ,.7: ..... . ,. ,, .-: ,.,, . .. ., !,-. ,,- ,,:, ,'- `: MPU REGISTERS ,. , A general block diagram of the M C6802is shown in Figure , 6. As shown, the number and configuration of the registers are the same as for the MC68~. The 128x 8-bit "RAM* has Juco I IU, L I Iavc -",,-. ..!. --,,.- ui I-uuaI `,. u , PROGRAM COUNTER The program c,ounter is a two"byte (16-bit) register that' points to the current program address. STACK POINTER The stack pointer is a two byte register that contains the address of the next available location in an external pushdown/pop-up stack. This stack is normally a random access If programs are not executed from on-board RAM,' TAVI applies. plies. For normal data storage in the on-board RAM,, this extended when using A and B parts (M C68A02, MC68A08, read/w;te memory that may have any location (address) that is convenient. -In those applications that require storage of information in the stack when power is lost, the stack The MPU contains two 8-bit accumul~lb~~l~at The condition code r~~x;<$hdicates the results of an Arithmetic Logic Unit~w#~on: Negative (N), Zero [Z), Overflow (V), Carr&~rn%t 7 (C), and Half Carry from bit 3 (H). These bits ofj:&&&,Qndition Code Register are used as testable condj$$&h~~r the conditional branch instructions. Bit 4 is the ~~t~;[.y~{ mask bit (1). The unused bits of the Condition Cod$J~eg&ter (b6 and b7) are ones. Fig&@ 8 mows the order of saving the microprocessor stat~$''~~~{hin the stack. ,wt. ~ + ,@ i>. ~t*,. Ji If. pro~ra~%"ko be stored and executed from on-board RAM, TAV2 apdela~wsot applv. Programs cannot be executed MC68B02, and MC68B&}. ,:.,$> ,1:::. . >+:,, !ji `.yl:> <./(. t,~.," -F, ,,,~$ft FIGURE7 - PROG;A@W#~DEL ,~ltt..,3. ~,> *,}`q$+s+ ~F,>:$3~ .tJ3,Ny::+*b `..~:~ ~ 7 , *:**y`*Y # ,~> On-board `ccum"'atorA m `ccumu'a'OrB ~ n .!.?.,,,,, .\.~,:::{&F ~,+:is>. 15 .?l. ,}$' *?:\\ `~.~~ ,h.:~, ~i>. `s~~~r' .\)$,., s{} . <. . ?*'- ,@ ~ ,, `$$ .,+\l. , .,.,, `*)*:.> \!~\.A\.....t. ,3*,%,,, > (4+;. *) `*:&%;i ~$:~:i{:',) ,> Ix Index Register I 0 Pc Program Counter 0. SP Stack 7. Pointer o Condition Codes Register Carry (From eit 7) Overflow ZirO Negative Interrupt Half MOTOROLA ,@".. ,',.,, ., from on-board Carry (From Bit 3) Semiconductor Products Inc. 6 RAM RAM can be used for data storage with all parts. OF THE MICROPROCESSINGUNIT m ~,yst<~k.b$ ,. e>< . .."$a.? are used to 0 " FIGURE 8 - SAVING THE STATUS OF THE MICROPROCESSOR IN THE STACK I I I m-9 m-8 SP = Stack CC= Condition Codes ACCB = Accumulator B ACCA = Accumulator A (Almcalled the Processor = Index Register, Higher Order 8 its I X L = Index Register, Lower Order 8 Bits IXH B Pointer PCH = Program Counter, Higher ord~~ 8 ~it~ PCL = Program Counter, Lower Order Status Byte) m-2 8 Bits m -1 m m+l m+z I .,.,~, ., Proper operation and timing signals of the MPU requires that certain control be provided to accomplish specific func- .tt {}'~~ri bus available will be at a high state, valid memory ad~~ \dress will be at a low state. The address bus will dis~lav ,, the :J5:,.:\i..~* tions and that other signal lines be monitored to determine "Rs+~'J' address of the next instruction. `,~: the state of the processor. These control and timing signals,t~ To ensure single instruction operation, transition of the are similar to those of the MC6800 except that TSC,$$~8E, _ line must occur tpcs before the falling edge of E and @l, @2 input, and two unused pins have been eli~!n~k~d, the HALT line must go high for one clock cycle. and the following signal and timing lines have b~~,'~ded: HALT should be tied high if not used. This is good ",~A ` .f,~ "~.:.:,..: RAM Enable (RE) engineering design practice in general and necessary to en~i.',it? ,,.:?, Crystal Connections EXTAL and XTAL ~>~~i~. ,#" sure proper operation of the part. J,h> .,:.:> . *:.) $,.1s. ~ ,,,kj..,,.t .,. Memory Ready (MR) `~a **,\ * ~.~,, .-k,x, >--~' VCC Standby READ/WRITE (R/~) \.\ `,.* .>., .+.,*,. ,\,~: .>..:,,. ~i,l,.., Enable 42 Output (E) This TTL-compatible output signals the peripherals and *,=*'!. -,,;$+: The following is a summary of~he~~PU signals: memory devices whether the MPU is in a read (high) or write ..:'J*~y:?' ADDRESS Sixteen capable (low) BUS (AO-AI 5) .,~3fi+,J{;~ pins are used ~~t'~ of driving o,~e,sta$mrd lines do not have+~t&-yate .:,+ DATA ~"~ (&:~& address bus. The outputs state. The normal standby state of this signal is read (high). When the processor is halted, it will be in the read state. This output is capable of driving one standard TTL are load and 90 pF. TTL load and 90 pF. These capability. VALID MEMORY This output ~+.y, `$%ix Eight piq~%qa'hsed for the data bus. It is bidirectional, transf@~~Xta to and from the memory and peripheral dev~~4Y~:,~~also has three-state output buffers capable of drwln~i~ne standard TTL load and 130 pF. valid address signal should ADDRESS indicates (VMA) to peripheral devices that there is a on the address bus, In normal operation, this be utilized for enabling peripheral interfaces such as the PIA and AC IA. This signal is not three-state. One standard TTL load and 90 pF may be directly driven by this active ~~+~~ bus will be in the output mode when the internal ~~~ is accessed and RE will be high. This prohibits external d5ta entering the MPU. It should be noted that the internal RAM is fully decoded from $0000 to $O07F. External RAM at $0000 to $O07F must be disabled when internal RAM is ac- high signal. BUS AVAILABLE (BA) - The bus available sianal will normally be in the low state; when activated, it ~ill go to the high state indicating that the microprocessor has stopped and that the address bus is available (but not in a three-state condition). This will occur if the HALT line is in the low state cessed. HALT or the processor When this input is in the low state, all activity in the machine will be halted. This input is level sensitive. In the HALT mode, the machine will stop at the end of an instruc- tion of a WAIT instruction. At such time, all three-state output drivers will go to their off-state and other outputs to their normally inactive level. The processor is removed from the is in the WAIT state as a result of the execu- Semiconductor Products Inc. @ 7 .... .. . ,...,,. .. ;,, ,., ,.:,.,,,i, ..e,.:, ,, ~..,.. ~ `, ` ., :O :0: ,7 . ~:_ . m... .T,, ...:. . ,:., = 7 .,,==... ... . ... :,(: :"-! ., ',::..,. { ,,. ,:, : ,.: ,::,.i ~.,: ,+~, ,.: ,,,,, . .; .,.; .,. . h. ,::.,:.,`:' `:. ,., ,,.,-: -,. . . ,. ... . . ,: ,. . ,""" :. :$ ,., ., ,,, ,,. .:, .;,: -., .. . ...' -., :. .',; ,. WAIT `state by the occurrence of a `m'askable (rnask.bitl ,. ="0) ` or nonmaskable interrupt. This output is capable of. dtiving" one standard TTL" load and 30 pF. .. .. " tion of a routine to initialize'the processor from its reset con,' dition.'All"the higher order address lines will be forced high. `For the restart, the last two ($FFFE, $FFFF) locations in memory will, be. used to load the program that is addressed `": by the program counter. During the restart routine, the interrupt mask bit is set and must be reset before the MPU can be ~ interrupted by ~Q. Power-up. and reset timing and power., down sequences are shown in Figures 9 and 10, respectiv~y, ,,RESET, when brought low, must be held low at least ~*,: clock cycles, This allows adequate time to respond @~[E@%y INTERRUPT REQUEST (~Q) ; `: ,;' f `" , A low level on this input requests `that an interrupt sequence be `generated within the machine. The processor will wait until it completes the current instruction ttiat is being excuted before it recognizes the request. At that time, if the interrupt mask bit in the' condition code register is not: set; :.- to the reset. This is independent of the trc p~,~'a/~&set the machine will begin an interrupt sequence. The index register, program counter, accumulator:, and condition code register are stored away on the stack. Next the MPU "will respond to. the interrupt. request by setting the interrupt ,,,:..~$~?> "'.*,? that is required. >+, `.+&b@.. ~J low-toWhen RESET is released it must go t~:,~hk%e high threshold without bouncing, osc~J%\~~#~r otherwise causing an erroneous reset (less tha~\Jh&e" clock cycles). This may cause improper MPU op&~~tio~.&ntil the next valid .Ji~.*>%,, ,! reset. ".%~<$~$s `+;,"'':k{,tt:$t;t mask bit high so that no further interrupts may occur. At the end of the cycle, a 16-bit'vectoring address which is' located in memory locations $FFF8' and $FFF9 is loaded which causes the MPU to branch to an interrupt routine in memory.. The HALT line must be in the high "state for interrupts to -- be serviced. Interrupts will be latched internally while HALT ,,, , ::. is low. NON-MASKABLE lNTERR,@3@~@) requests that a nonA low-going edge q~~~~~wput maskable' interrupt sequ~$~ be generated within the pro- A nominal 3 k~ pull up resistor to ,VCC should be used for wire-OR and optimum control of interrupts: ~Q may be tied directly to VCC if not used. .,. cessor. As with tw]'%terrupt request signal, the processor ,*.K.,*?:C*I..:... will complete t~~~,mretit Instruction that is being executed before it rec~~~:e~the NM I sig'nal. The interrupt mask bit in the condi~~~jcb~ register has no effect on ~. ,' ,.. RESET The ,J?de%$egister, program counter, accumulators, and conti$?~~:code registers are stored away on the stack. At the This input is used to reset and start theMPU from a .tR# cycle, a 16-bit vectoting address which is located power-down condition,. ,resulting from a power' failure or ,ap :p `"< ~$+ .,,,~;~g@ory locations $FFFC and $FFFD is loaded causing the initial start-up of the processor. When _this line is' low, the *~J&~~~ to branch to an interrupt service routine in memory, MPU is inactive and the information `in theregisters will be ~ A nominal 3 k~ pullup resistor to VCC should be used for lost. If a high level is detected on the. input, this will signal may be tied the M PU to begin the restart sequence. This will start exec~<~~> `"$s, wire-OR and optimum control of interrupts. ml "*.:$*$, .,:' ~..:,$,, $;h AND RESET TIMING" ~ FIGURE `9 -l~Q\~~iyUP -, ,, 4.75 v ., ,, .,' ,,. E, ," tr~ + RESET ,., :,*$ !) Option 1 (See Note 8elow) ,' ,. .Option 2 (See Figure 10 for Power-down Condition) ~,. ,. RE ,, NOTE: If option 1 is chosen, ~ and RE pins can be tied together. ,. ,,, ,, @ MOTOHO~~ ,. ~~...,, .,. , ,', ,;, ,; ., .,. .,> Semiconductor Pioducts /nc. ,8. - directly to VCC if not used, Inputs ~Q and ~ are hardware interrupt lines that are sampled when E is high and will start the interrupt routine on a low E following the completion of an instruction. the major decision Figure 11 is a flowchart describing paths and interrupt vectors of the microprocessor, Table 1 gives the memory map for interrupt vectors, FIGURE 10 - POWER-DOWN `CC7 I TABLE 1 - MEMORY MAP FOR INTERRUPT VECTORS 6Ac ,", " Vector I lc $FFFE I L- Description I $FFFF $FFFC I $FFFD $FFFA $FFFB $FFF8 I $FFF9 I tpcft:Hiw Rests rt Non-Maskable , Interrupt Software lnterru Dt ,. Interrupt Request Fetch Instruction Execute Interrupt Routine I 4 I Execute Instruction I + NMI $FFFC $FFFD o 7 [ MO~OROLA SEQUENCE + v * ~Q $FFF8 $FFF9 * Semiconductor Products Inc. @ 9 FIGURE 14 - MEMORY READY SYNCHRONIWTION u 4xfo Oscillator EXTA XTA' M C6802 Ml The E clock will resume normal operation at the end of the k cycle during which MR assertion meets the tpcs setup time. The tpcs setup time is referenced to transitions of E were it not stretched, If tpcs setup time is not met, E will fall at the second possible transition time after MR is asserted. There is no direct means of determining when the tpcs references occur, unless the synchronizing circuit of Figure 14 is used. m MOTOROLA Semiconductor Products Inc. 11 The instruction set has 72 different instructions. Included are binary and decimal arithmetic, logical, shift, rotate, load, itional or unconditional branch, interrupt and ~lation instructions (Tables 2 through 6). The in- *-- @te addressing,' the operand is contained in the of the instruction except LDS and LDX which erand in the second' and third bytes of the in~e MPU addresses this location when it fetches Ite instruction for execution. These are two- or lstructions. ~':: ~ ~..i.i':+?;, ,.,~'*$:*\ l~,s:~t- DIRECT ADDRESSING In direct addressing, the address of the operand is Contained in the second byte of the instruction. Direct addressing allows the user to directly address the lowest 256 bytes in the !., locations-zero through 255. Enhanced execu"e achieved by storing data in these locations. In ost configurations, it should be a random-access memory, jtructions. `~' ;ING This pin supplies the@~$k fo~h- ..... ---------------system. This is a sing~~~~$%, TTL-cornpatible clock, TI clock may be con~~w$d,by,a me,,. -,, ____ -.=,, -,. , ,.equivalent to 42/~~~~QeM,C6800. This output is capable of driving one st&$SM. ~TL load anc **:a~'*:&,l ,. Thus, tier-up; 3ximum. current drain at VSB maximum ii this pin must be connected to VC ` , : In extended addressing, the address contained in the se: the instruction is used as the higher eight bits of of the operand. The third byte of the instruction e lower eight bits of the address for the operand, ~is is an absolute address in memory. These are three-byte instructions. ` DDRESSING ~ addressing, the address contained in the sef the instruction is added to the index register's lowest &ght bits in the MPU. The carry is then added to the higher order eight bits of the index register, This result is then used to address memory, The modified address is held irv address resister so there is no change to the Semiconductor Products Inc. -- IMPLIED ADDRESSING byte In the implied addressing address (i. e., stack pointer, one-byte instructions. RELATIVE mode, the instruction index register, etc.). addressing, the address contained ABA ADC ADD AND ASL ASR Add Accumulators Add with Car~ Add Logical And Arithmeti Shti Left Arithmeti Shift Right BCC Branch if Car~ Clear Branch if Carry Set Branch if Equal to Zero Branch if Greater or Equa zero Branch if Greater than zero Branch if Higher Bit Test Branch if Lessor Equal Branch if Lower or Same Branch if Less than Zero Branch if Minus Branch if Not `Equ4 to Zero Branch if Pfus Bramh Always Branch to Subroutine Bramh if Overflow Clear Branch if Overflow Set BEQ BGE BGT BHI BIT BLE BLS BLT BMI BNE BPL BRA BSR BVC BVS CBA CLC CLI of the instruction is added to the program counter's lowest eight bits plus two, The carry or borrow is then added to the high eight bits. This allows the user to address data within a range of - 125 to + 129 bytes of the present instruction. These are two-byte instructions. ADDRESSING In relative Bcs gives the These are Compare Accumulators Clear Carrv m in the second CLR CLV CMP COM CPX Clear Clear Overflow Compare Complement Compare Index Register DAA DEC DES DEX Decimal Adjust Decrement Decrement Stack Pointer Decrement index Register EOR Exclusive OR STA .,,\ ~!i$t, Increment ,,"%... STS Increment Stack Poi,ntBP~~.. STX increment Index ~'g~~ "w SUB `, ~`$.::~,:N*. ".?.,.., JMP Jump Swl Jump to suti@*\ JSR \.\\ TAB LDA TAP Load Accu~labr LDS TBA Loa~~@tack pointer TPA LDX Lq@]~ex Register LSR TST ,~~~,d Shift Right . ~ft\.,~ !,,,, ~.. TSX NEG ~,.s~x ,~~a~e Txs NO~%,&*+& Operation !$+.$) ~J....>.... WAI ~QJ~t't;?.'YInclusive OR Accumulator INC INS INX MOTOROLA Semiconductor Set Interrupt Mask Set Overflow Store Accumulator Store Stack Register Store Index Register Subtract Software Interrupt Transfer Transfer Transfer Transfer Test Transfer Transfer Accumulators Accumulators to Condition Code Reg. Accumulators Condition C&e Reg. to Accumulator Stack Pointer to Index Register Itiex Register to Stack Pointer Wait for Interrupt Products \nc. ,. .. . . .. . ..... ,: .:... -.--7:7 T_... r;-7:7 ;,, ,,. :,.; :.,,,.;.' {., :, . ,., ,, T_ . -, . .-, ----- . . . . . .,.,: TABLE 3,.. ,{, ,, . . , . . . . . ,.. .:_ ,, ... .. . .,", `...!. ,,, .,"., ..7,-.. . ..-, ,. , . . . . . . ;. . . .- ACCUMULATOR MNEMONIC Add Add Acmltrs Addw!lh Carry BOOLEAN/lRITHMETIC Bit Test Clear Compare = 8B 2 2 9B32 AB C8 2 `2 OB32 EB52 Co,npare Acmltrs Op, 5 2 . IMPLIEO = 8922 C9 84 C4 ,B5 C5,2 2 2 2 2 2 2 2 2 2 9932 0932 .9J 3. 0432 9532 0532 2 A952 E9 .5 A4 5 E4 5 A552 E5 5 6F 7 3 A+ M-A ! t t J I 3 B+ M--B t t 1 t 1 t t t J t t t t t t 1 I $ t t t t f f t 1 t j R . R . R . R' `&< B143 A+ B-A A+ M+ C-A B+ M+ C--B A.M:A B. M.. B AM EM 004M 00-. A 00- B A-M Flq3 B-M 4 2 2 B443 F443 B5q3 2 2 F543 7F, 6 3 4F21 5F21 B122 9132 C122 D1 Al' 3, 2 5 2 E152 1121 6372 ` 6072 NEGA NEGB Oecimal Adjust, A OAA Oecrement OEC 7063 4021 00 -A-A . 5021 00 -B-.6 1921 Converts Binarv$~~ti:~&O 4A21 5A21 into BCD ~grmat "'>*F ",'.+..h M - I,,,*M b .}. .t/.t,:>?<~\*.s A +>1, `+;), #?'l**B'* 6A72 7A `6 3 OECB Incremel,t Load Acmltr Or, Inclusi"e BB22 C8 Pull Data PULA PULB Rotare Left A852 EB"5 `flOLB ROR RORA RORB ASL ASLA ASLB ASR Shalt Left, Arilhme;tc Shalt Right, Arlthmet!c B6 C6 8A CA ,' 2 2 2 2 9'6 3 0632 2 2 2 9A32 0A32 2 2 A; 5 2 AA 5 EA52 2 ~., ,.{#$:$ ,' q; `~~%kiv $' ,4 334' 7963 tt~$ 4921 >..> ,*k\. Slore Aclnllr. .}*.t+,*$'$'~ ,, >+*. .~,*::&y,,& ~.s. sub,,, cl A&;l;~%@* ,!.. -q.,.. Subtr. w~\~8q\k ?:<, ,,.\:.:\:*> Subtract . STAB su~A ">''~cml$fs ,t~sw$fe%:,, <. .. ,<.~v ~~~$l:~~ro or Minus ,:$y .... !.>,,.. \ ., ,:~:.~.,:<*R* is Characters B OP . t @ @ t @ @ t t [ t I @ t t 4 { 1 4 * [ ! 4 . t i 1 1 r 1 t R R @ @ @ R R t t t t t t 1 r I . R . R . . . A+ M-A 6+ M-. B 9 ] t ,+ Nu!nber of Program Bvtes; + Arithmetic Plus: Arithmetic Minus: Boolea!l ANO; Msp Boolean Excl"si.e u Complement OR; 01 M; Note - Accumulator @ addressing mode instructions 9 . . . . . . . . . ] t @ t t t t 1 : 1 t \ t @ @ @ @ @ @ @ @ @ I t \ i 1 I I t j f * t 1 6 * t t @ 1 M R 1 @ ~ R [ 6 ] e R t @ B M AM-A . . t t i \ R . R . 1 t r t 1621 1721 B- M-B A-B. A A-M- C.A B- M-C-.8 A--B 8 .A . . . . . . 4021 5021 M-OO A-00 B-00 . . . . . . . ] 1 ] ! t \ [ i t [ [ [ I 1 1 1 t 1 ] \ ] I R R R R R t t I 1 . . R R R H 1 N z v c M A B }b M A B }. b7 "''''"J - bO "'''':'4 -- bO . . . ~~ C-b7 - ~- o 4421 A 5421 B} A.. M 3 o-~ -0 bO b7 C COOE SVMBOLS H Hal f.c~rri from b,t 3; I Interrupt mask Transfer Into; N Negative (tign bitl Blt = Zero; Zero (bvte) 00 Byte = Zero; z v c are included 10 the column for IMPLIED MOTOROLA ~, addressing Owedlow, 2's complement Carrv from bit 7 R Reset Alwavs s Se! Alwavs 1 Test and se! if true, cleared otherwise Not Affected Semiconductor Products Inc. 14 . . . . . . 1 1 c o Conlents of memorv Iocatlon pointed to be Slack Pointer: @ Boolean Inclusive OR; @ @ 9 * * . . . . CO NOITION Operalton Code (Hexadecimal); Number of MPU CVcles; 1 t 1 f R s 1 R s ~ R s r !~~. LEGENO: t I t , t --SP .SP $ j SP+l--SP, MSP-A ~+1 -. SP, Msp -8 a: 8 p ~ t .$: .? t 6 +1-B M--A M -B A `- MsP, SP -1 B-. Msp, SP-l R .+? ~., .~, \& .RS)'* * * 1021 9232 02 3 : &o-; B} b7 F043 ,. . 7463 A762 4B21 5821 5721 9742 `a$>k'$;iw:~ 6!3 ~721 $- . 9 2' 2 7863 `$*{:? 46 56 6472 t t t 1 j 1 t 1 1 7683 77 , ,i~ 3A AB lb 5921 6/72 WM ,:.B@#: .,~t,!$$~' "P{ ~M+ l-M 1 :A+I-. A ~~+~> ` # ,:?~ ,. ~"%.. F64$ :.' .,:+$ BA ~~~ s.)! i'!. F#/.>Lf,,;:+~; *&' 4+, 3641 .',.,ia>:, . 31 "4 I ,i;#> 3241 B6 *+, ~;}..\. }%. ,.:. * t?:,~ .'tt-.~~' .i$/ " *4. W72 ~{',+~ws+~~~>. -~ ~>, c ~~ ~:$;~}, %:3::>.: . `v&!. .)"!.?+ 68' 7 2 ,,, - .>$y$k"~ ~w.{.)i 1-.. *+.:t. r ~t:.,t . . ~F** ~y &, 7C63 E652 ASRA . ":$ ~~:, ASRB ,.\y .,. .%4..,$,*V ,+p ~**% b, LS~$ ,:$* ,.&bq&?i& t. log!c . 4&:@'%2 ROL ,' RoIste Right BB43 F843 2 `" ROLA Shalt flight, 9632 DB32 2.2 6C72 ORAA ORAB PSHA PSHB Push Onta ` ,' , EORA EORB INC INCA INCB LOAA. LOAB fi-A ~4B 00 -M-M DECK Exclusi"e OR 1 5321 NEG (Negate) 2, , *3 ,$$)$ )$,, "7,\ . d .<-<,,.,,, `N; ,* $:, >\:$, >~$;, *$:'*: !,. :!~~+ . . ~k,;.t>i}\+., ~.,:!:r~,,...> xi ..:,1,, M-M 43 COMB 2's . A-B 1363 COMA Complement, 5 4 3 2 1 0 H I N z v c FB' ," ~ CONO. COOEREG BB - 4 B943 F943 z OPERATION (All register labels refer tO contentsl OP-= IB21 CBA COM 1's EXTNO' Op-= AODB, CMPB Complement, .OP. INOEX AODA ABA AOCA AOCB' ANDA ANDB BITA 81TB CLR CLR,A CLRB CMPA A"d "OIRECT OP== . AND MEMORY INSTRUCTIONS ,. ADO RESSINGMOOE5" OPERATIONS . .. .. ,. ,,"IMMEO .... , t = I TABLE 4 - INDEX REGISTER AND STACK MANIPULATION IMMEO POINTER Compare OPERATIONS Index MNEMONIC ttag Index Reg DEX Oecrement Stack Pntr OES Increment Index Reg INX Increment Stack Pntr INS Index Reg Load Slack Store 8C CPX Oecrement Load OP -- LOX CE Pnlr LOS 8E Reg STX StoreStackPntr STS Indx Stack Index Reg - Stack Pntr - Indx Pntr TXS Reg TSX -- I O lEl -- OP 3 3 3 9C -- 4 II DE OP AC -- & -- CO ND. COO EREG, -- E OP -- 2 6 K TN Ifi -- Lll -- -- OP -- -- 09 4 1 34 4 1 08 4 1 31 4 1 35 4 1 30 4 -- 1 -- -- = -- 151413/21110 BOOLEAN/ARITHMETIC OPERATION H] 4 EE 6 2 FE 5 9E 4 AE 6 2 BE 5 OF 5 EF 2 FF 6 9F 5 AF 1 1 2 BF 6 -- -- -- -- IN RELATIVE INOEX EXTNO II NIZIVIC 5 OE -- INSTRUCTIONS -- -IE -- OP -- -- [G. ( 4 i 7 -- N u -- * 0 0 m e D e e 0 * BGE N@V=O I -- * e e e e BGT Z+(N@V)=O 0 * e BHI C+z=o e e e B LE Z+(N@V)=l e 0 @ B LS C+z=l a * B LT N@V=l 0 * e BMI e e e BNE N=l Z=o e * e 8VC V=o e m BVS V=l N=o 0 e * e * * m 0 e 0 e @ e 0 a 9 a BRA C=o 8CC B CS C=l \,, -\* . BEO Z=l BPL BSR JMP 7E JSR BD See Special NOP 2 0 5 2 9 -- 1 1 1 1 1 } (Figure 16) Advances See Special } Operations Prog. Cntr. Only Uperallons (Figure 16) Semiconductor Products Inc. @ 15 -- - TABLE 7 - INSTRUCTION ABA ADC ADD AND ASL ASR BCC BCS BEA BGE BGT BHI BIT BLE BLS BLT BMI BNE BPL BRA BSR BVC BVS CBA CLC CLI CLR CLV CM P COM CPX DAA DEC DES DEX EOR 2 2 234 2345e. 2345. ..67.. ..67., X* X* Xe ADDRESSING MODES AND ASSOCIATED (Times in Mechine Cycle) 2. . 4 4 ****** a***. ****e *oa*e 000 x- 00 23 INC tee O**eee EXECUTION TIMES :5*. .**.. *@*.* ee **seem *****e *****9 ***e* ma 4 4 4 4 **@ **e 4 4 4 4 4 4 4 6 10 e*9 5 2 ***O eee 2345. 2 2 2 eeee 9 *oBe e 0 0 2345 eee, *Q* 456. 567e 567. 192 2 2 ..ee baee 2 2 Oeoe .0.8 ne 00oe **O* 67. eee 4 4 9 NOTE o MOTOROLA Semiconductor Products Inc. @ 17 Register Data (Low Order Byte) - TABLE 8 - Address Mode and instructions INHERENT Cycles OPERATIONS Cycle VMA # Line SUMMARY (CONCLUDED) Address Bus R/fl Line Data Bus (Continued) WA I 1 Op Code Address Op Code 2 Op Code Address+ 1 Op Code of Naxt Instruction 3 Stack Pointer Return Address (Low Order Byte) 4 Stack Pointer - 1 Return Address (High Order Byte) 5 Stack Pointer - 2 Index Register {Low Order Byte) Index Register (High Order B~~e) .J,> ... `~~ \:. of AccumulatorJ~~~R> 6 Stack Pointer - 3 7 Stack Pointer - 4 Contents 8 Stack Pointer - 5 Contants 9 Stack Pointer - 6 of Accumula4&r&~~ "::" .,y Ji\ of Con~~,.$~~W/gister :s .Jl::*\&,\ .1 Op Code ~+,i,:t,~+,,* Contents 1 Op Code Address 2 Op Code Address+ 3 Stack Pointer 4 Stack Pointer t 1 5 Stack Pointer t 2 6 Stack Pointer t 3 ~~ntents 7 Stack Pointer + 4 ~~t~ 1 of Accumulator A from Stack Register from Stack (High Order B Index Register from Stack (Low Order BVte) 9 Next Instruction Address from Stack (High Order Byte) 10 Next Instruction Address from Stack (Low Order Bvte) Swl Op Code Irrelevant 12 I Sta~k Poster - 2 ~'a~iPointer - 3 Data (Note 1 ) Return Address (Low Order BVte) Return Address (High Order .Bvte) Index Registar (Low Order BVte) Index Register (High Order Byte) ~$~~k Pointer -- 4 Contents of Accumulator A %tack Pointer - 5 Cqntents of Accumulator B Stack Pointer - 6 Contents of Cond. Code Register Irrelevant Stack Pointer - 7 Data (Note 1) Vector Address FFFA (Hex) Address of Subroutine BVte) (High Order Vector Address FFFB (Hax) Address of Subroutine Bvte} ( Low Order Op Code Address Op Code Op Code Address + 1 Branch Offset Op Code Address + 2 Irrelevant Data (Note 1 ) Branch Address Irrelevant Data (Note Op Code Address Op Coda Op Code Address t 1 Branch Offset 1) Return Address of Main Program Irrelevant Stack Pointer Return Address (Low Order BVte) Address (High Order Byte) Data (Note 1) Stack Pointer - 1 Return Stack Pointer - 2 Irrelevant Return Irrelevant Data (Note 1 ) Address of Main Program Subroutine Address (Note 4) Irrelevant Data (Note Data (Note 1) 1) OTES: 1. If device which is addressed during this cvcle uses VMA, then the Data Bus will go to the high-impedance three-state condition. Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus. 2. Data is ignored by the MPU. 3, For TST, VMA=O and Operand data does not change. 4. MS Byte of Address Bus= MS Byte of Address of BSR instruction and LS Byte of Address Bus= LS Byte of Sub-Routine Address. ~@ MOTOROLA Semiconductor Products Inc. ORDERING INFORMATION o 11 J!uilllllllll II dLD H ,.;:;,,,"s d+' `n lli JU--~.Jjp'~:+"' `EAT'NGPLAN:JL .;~:&~'M+ ,. ,:.:,,. `::.:{:,), "s?; ..l?l,>~~Yt. ~ `*,>1:>>.,~?$ ,,$,,1:..~~~..$,,.h,?.~~' ..; W! V&A ~ : 4~ ~.;. Motorola reserves ~ -F to make changes or uae of any product MOTOROLA @ ~;~ ~: R p~: fi: : -\ D ::j(a~l `; tti 2.5ASSC 1.78 0.76 0.20 0.33 4,19 2.54 .99 15.49 - 1,52 to any products or circuit herein described to improve herein; neither NOTES: 1. LEAOS, TRUE POSITIONED WITHIN O.25mm 10.O1O)OIA (AT SEATING PLANE), AT MAX MA~L CONOITION. 2. OIMENSION "~ TO CENTER OF LEAOS WHEN FORMEO PARALLEL. O.lw Bsc O.mo 0.070 0.008 0.01s 0.100 0.165 0.590 0.610 )00 1,02 j~ 0.040 O.mo pL4yi{{AG :!;`~;~`$~ 3.94 5.08 ~ 0.36 1.52 1.02 2.s Bsc 1,65 2.16 0,20 0.36 2.92 3.43 15,24 6SC 00 159 0.51 I 1,02 c o F G H J K L M N \ "~~.M SEfiT!NG PLANE the right out of the application ,L ,, ~G~ MAX 2.020 ~f:: MlN . .*.t.. ,:. \Lt, l~.:,~* `f.*" ~i~. MIN 1,980 1:: ----------ic~-L' -q $,, ,. .', "..:.. ,.~ ~ MAX 5!.31 l% G H J K `t.'; q *.,4.$?*,.~tj!i$? ~.\* DIM MIN A 50,29 -; reliability, function 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 i 0.085 0.00B I 0.015 0.1151 0.135 0.600 BSC OQ NOTES: 1. POSITIONAL TOLERANCE OF LEADS (0), SHALL BE WITHIN 0.25 mm (0.010) AT MAXIMUM MATERIAL CONOITION, IN RELATION TO SEATING PLANE ANO EACH OTHER. 2. OIMENSION L TO CENTER OF LEAOS WHEN FORMEO PARALLEL. 3. OIMENSION B OOES NOT INCLUOE MOLO FLASH. 150 0.020 I 0.040 or design. Motorola does not assume anv Iiabilitvarising does it convey any license under its patent rights nor the rights of others. Semiconductor Producfs Inc. 3501 ED BLUESTEIN BLVD., AUSTIN, THAS 78721 A SUBSIDIARY OF MOTOROLA INC. --