128K x 16 Static RAM
CY62136CV18 MoBL2™
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05016 Rev. *C Revised August 30, 2002
Features
•High Speed
—55 ns and 70 ns availability
•Low voltage range:
—1.65V−1.95V
•Pin Compatible with CY62136BV18
•Ultra-low active power
—Typical Active Current: 0.5 mA @ f = 1 MHz
—Typical Active Current: 1.5 mA @ f = fmax (70 ns
speed)
•Low st andby power
•Easy memory expansion with CE and OE featu res
•Automatic power-down when deselected
•CMOS for optimum speed/power
Functional Description
The CY62136CV18 is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life® (MoBL™) in portable
applic ati ons suc h as ce ll ular telephon es . T he dev ic e al so ha s
an automatic power-down feature that significantly reduces
power co nsumptio n by 99% when addr esses are not togglin g.
The devi ce can als o be put in to stan dby mode whe n deselec t-
ed (CE HIGH). The input/output pins (I/O0 through I/O15) are
placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), both Byte High En-
able and Byte Low Enable are disabled (BHE, BLE HIGH), or
during a write operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appea r on I/O0 to I/O 7. If Byte High En able ( BHE) is LOW,
then data from memory will appear on I/O8 to I/O15. See the
Truth Table at the back of this data sheet for a complete de-
scription of read and write modes.
The CY62136CV18 is available in 48-ball FBGA packaging.
Logic Block Diagram
128K x 16
RAM Array I/O0–I/O7
COLUMN DECODER
A11
A12
A13
A14
A15
2048 X 1024
SENS E AMPS
DATA IN DRIVERS
OE
I/O8–I/O15
CE
WE
BLE
BHE
A16
ROW DECODER
A7
A6
A3
A0
A2
A1
A5
A4
A8
A9
A10
CY62136CV18 MoBL2™
Document #: 38-05016 Rev. *C Page 2 of 12
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tes ted .)
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Supply Voltage to Ground Potential.................−0.2V to +2.4V
DC Voltage Applied to Outputs
in High Z State[3]........................................ −0.2V to VCC + 0.2V
DC Input Voltage[3].................................... −0.2V to VCC + 0.2V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Notes:
1. NC pins are not connected to the die.
2. E3 (DNU) can be left as NC or VSS to ensure proper application.
3. VIL(min) = −2.0V for pulse durations less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Pin Configurati o n[1 , 2]
WE
Vccq
A11
A10
NC
A6
A0
A3CE
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
Vssq
A7
I/O0
BHE
NC
DNU
A2
A1
BLE
VCC
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
FBGA
A16
Top View
Operating Range
Device Range Ambient Temperature VCC
CY62136CV18 Industrial −40°C to +85°C 1.65V to 1.95V
Product Portfol io
Product
VCC Range
Speed
Power Dissipation (Industrial)
Operating (ICC)Standby (ISB2)
f = 1 MHz f = fmax Typ.[4] Max.VCC(min) VCC(typ)[4] VCC(max) Typ.[4] Max. Typ.[4] Max.
CY62136CV18 1.65V 1.80V 1.95V 55 ns 0.5 mA 2 mA 2 mA 7 mA 1 µA8 µA
70 ns 0.5 mA 2 mA 1.5 mA 6 mA
CY62136CV18 MoBL2™
Document #: 38-05016 Rev. *C Page 3 of 12
Electrical Characteristics Over the Operating Ran ge
Test Conditions
CY62136CV18-55 CY62136CV18-70
Parameter Description Min. Typ.[4] Max. Min. Typ.[4] Max. Unit
VOH Output HIGH Vo ltage IOH = −0.1 mA VCC = 1.65V 1.4 1.4 V
VOL Output LOW Voltage IOL = 0.1 mA VCC = 1.65V 0.2 0.2 V
VIH Input HIGH Voltage 1.4 VCC +
0.2V 1.4 VCC +
0.2V V
VIL Input LOW Voltage −0.2 0.4 −0.2 0.4 V
IIX Input Leakage Current GND < VI < VCC −1+1−1+1µA
IOZ Output Leakage
Current GND < VO < VCC, Output Disabled −1+1−1+1µA
ICC VCC Operating Supply
Current f = fMAX = 1/tRC VCC = 1. 95V
IOUT = 0 mA
CMOS levels
27 1.56mA
f = 1 MHz 0.5 2 0.5 2 mA
ISB1
Automatic CE
Power-Down Cur-
rent— CMOS Inputs
CE > VCC – 0.2V,
VIN > VCC– 0.2V, VIN < 0.2V
f = fMAX (Address and Data Only),
f = 0 (OE, WE, BHE, and BLE)
18 18µA
ISB2 Automatic CE
Power-Down Cur-
rent— CMOS Inputs
CE > VCC− 0.2V
VIN > VCC − 0.2V or VIN < 0.2V,
f = 0, VCC = 1.95V
Capacitance[5]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC= V CC(typ) 6pF
COUT Output Capacitance 8pF
Thermal Resistance
Description Test Conditions Symbol BGA Unit
Thermal Resistance
(Juncti on to Ambi ent )[5] Still Air , soldered on a 4.25 x 1.125 inch, 4-layer printed
circuit board ΘJA 55 °C/W
Thermal Resistance
(Juncti on to Ca se)[5] ΘJC 16 °C/W
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
CY62136CV18 MoBL2™
Document #: 38-05016 Rev. *C Page 4 of 12
Note:
6. Full devic e operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
AC Test Loads and Waveforms
VCC Typ
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
OUTPUT V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Rise Time:
1 V/ns Fall Time:
1 V/ns
Parameters 1.8V UNIT
R1 13500 Ohms
R2 10800 Ohms
RTH 6000 Ohms
VTH 0.80 Volts
Data Retenti on Characteristi cs (Over the Operating Range)
Parameter Description Conditions Min. Typ.[4] Max. Unit
VDR VCC for Data Retention 1.0 1.95 V
ICCDR Data Retention Current VCC = 1.0V
CE > VCC − 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V
0.5 5µA
tCDR[5] Chip Desel ect to Data
Retention Time 0ns
tR[6] Operation Recovery Time tRC ns
Data Retenti on Waveform
VCC(min.)
VCC(min.)
tCDR
VDR >1.0 V
DATA RETENTION MODE
tR
CE
VCC
CY62136CV18 MoBL2™
Document #: 38-05016 Rev. *C Page 5 of 12
Switching Characteristics Over the Operating Range[7]
55 ns 70 ns
Parameter Description Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time 55 70 ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 10 10 ns
tACE CE LOW to Data Valid 55 70 ns
tDOE OE LOW to Data Valid 25 35 ns
tLZOE OE LOW to Low Z[8] 5 5 ns
tHZOE OE HIGH to High Z[8, 9] 20 25 ns
tLZCE CE LOW to Low Z[8] 510 ns
tHZCE CE HIGH to High Z[8, 9] 20 25 ns
tPU CE LOW to Power-Up 0 0 ns
tPD CE HIGH to Power-Down 55 70 ns
tDBE BLE/BHE LOW to Data Valid 25 35 ns
tLZBE BLE/BHE LOW to Low Z[8] 5 5 ns
tHZBE BLE/BHE HIGH to High Z[8, 9] 20 25 ns
Write Cycle[10]
tWC Write Cycle Time 55 70 ns
tSCE CE LO W to Write End 40 60 ns
tAW Address Set-Up to Write End 40 60 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-Up to Write Start 0 0 ns
tPWE WE Pulse Wid th 40 50 ns
tBW BLE/BHE LOW to Write End 40 60 ns
tSD Data Set-Up to Write End 25 30 ns
tHD Data Hold from Write End 0 0 ns
tHZWE WE LOW to High Z[8, 9] 20 25 ns
tLZWE WE HIGH to Low Z[8] 510 ns
Notes:
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), an d out pu t l oad i n g o f th e
specified IOL/IOH and 30-pF loa d cap acit ance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, tHZBE and tHZWE trans itions are me asured when the output s enter a high impedance st ate.
10. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and a ny
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that term inates
the write
CY62136CV18 MoBL2™
Document #: 38-05016 Rev. *C Page 6 of 12
Switching Waveforms
Notes:
11. Device is continuously selected. O E, CE = VIL, BHE a nd/or BLE = VIL.
12. WE is HIGH for read cyc le.
13. Address v a lid prior to or coincident with CE, BHE, BLE, transition LOW.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
Read Cycle No. 1(Address Transition Controlled)
[11, 12]
Read Cycle No. 2 (OE Controlled)[12, 13]
50%
50%
DATA VALID
tRC
tACE
tDBE
tLZBE
tLZCE
tPU
DATA OUT HIGH IMPEDANC E IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
OE
CE
HIGH
VCC
SUPPLY
CURRENT
tHZBE
BHE/BLE tLZOE
ADDRESS
tDOE
CY62136CV18 MoBL2™
Document #: 38-05016 Rev. *C Page 7 of 12
Notes:
14. Data I/O is high impedance if OE = VIH.
15. If CE goe s HIGH simult aneously with WE HIGH, the out put r emains i n a hi gh-impedan ce st ate .
16. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
DATA I/O
ADDRESS
CE
WE
OE
tHZOE
DATAIN VALID
NOTE
Write Cy cle No. 1 (WE Controlled)[10, 14, 15]
16
BHE/BLE tBW
tSCE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 16
Write Cycle No. 2 (CE Controlled)
BHE/BLE tBW
[10, 14, 15 ]
tSA
CY62136CV18 MoBL2™
Document #: 38-05016 Rev. *C Page 8 of 12
Switching Waveforms
DATAIN VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATAI/O NOTE 16
Write Cycle No. 3 (WE Controlled, OE LOW)
tBW
BHE/BLE
DATA I/O
ADDRESS
tHD
tSD
tSA
tHA
tAW
tWC
CE
WE
DATAIN VALID
Write Cycle No. 4 (BHE/BLE Cont rolled, OE LOW)[15]
NOTE 16
tBW
BHE/BLE
tSCE
tPWE
CY62136CV18 MoBL2™
Document #: 38-05016 Rev. *C Page 9 of 12
Typical DC and AC Characteristics
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.)
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
HXXXXHigh Z Deselect/Power-Down Standby (ISB)
L X X H H High Z Output D isa bl ed Active (ICC)
L H L L L Data Out (I/OO–I/O15)Read Active (ICC)
L H L H L Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z Read Active (ICC)
L H L L H Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z Read Active (ICC)
L H H L L High Z Out put D isa bl ed Active (ICC)
L H H H L High Z Output D isa bl ed Active (ICC)
L H H L H High Z Output Disa bl ed Active (ICC)
L L X L L Data In (I/OO–I/O15)Write Active (ICC)
L L X H L Data In (I/OO–I/O7);
I/O8–I/O15 in High Z Write Active (ICC)
L L X L H Data In (I/O8–I/O15);
I/O0 –I/O7 in High Z Write Active (ICC)
3.5
3.0
1.5
1.0
0.5
1.80
0
2.0
ISB (µA)
2.4
2.0
1.2
0.8
0.4
1.65 1.80 1.95
0.0
1.6
ICC
40
35
25
20
15
1.65 1.8 1.95
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
10
30
TAA (ns)
Operating Current Standby Current vs. Supply Voltage
SUPP LY VO LTAG E (V)
SUPP LY VO LTAG E (V)
MoBL2
MoBL2
MoBL2
vs. Supply Voltage
1.95
1.65
(f=fmax, 55ns)
(f=fmax, 70ns)
(f = 1 MHz)
CY62136CV18 MoBL2™
Document #: 38-05016 Rev. *C Page 10 of 12
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
70 CY62136CV18LL-70BAI BA48A 48-Ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) Industrial
CY62136CV18LL-70BVI BV48A 48-Ball Fine Pitch BGA (6 mm x 8 mm x 1mm)
55 CY62136CV18LL-55BAI BA48A 48-Ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm)
CY62136CV18LL-55BVI BV48A 48-Ball Fine Pitch BGA (6 mm x 8 mm x 1mm)
Package Diagram
48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A
51-85096-*E
CY62136CV18 MoBL2™
Document #: 38-05016 Rev. *C Page 11 of 12
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
MoBL is a registered t radema rk and MoBL2 and More Battery Life are trade marks of Cyp ress Semi conducto r Corporation. Al l
product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagram (co nti nue d)
48-Lead VF BGA (6 x 8 x 1 mm) BV48A
51-85150-*A
CY62136CV18 MoBL2™
Document #: 38-05016 Rev. *C Page 12 of 12
Document Title: CY62136CV18 MoBL2™, 128K x 16 Static RAM
Document Numbe r: 38-050 16
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 106264 05/07/01 HRT/MGN New Data Sheet
*A 107701 06/15/01 MGN Delete data sheet. Not offering device.
*B 111522 11/06/01 GAV Reactivate spec. Final data sheet.
*C 115865 09/04/02 MGN Add BV pkg
