MICRON TECHNOLOGY INC MICRON MT5C2565 883C ort eel ar AN T-46-23 -19 MILITARY SRAM 64K x 4 SRAM WITH OUTPUT ENABLE AVAILABLE AS MILITARY SPECIFICATIONS SMD 5962-89524 JAN M38510, 293 MIL-STD-883, Class B * Radiation tolerant (consult factory) FEATURES High-speed: 20, 25, 35 and 45ns Battery backup: 2V data retention Low power standby Power down (gated inputs) High-performance, low-power, CMOS double-metal process * Single +5V (410%) power supply e Easy memory expansion with CE Allinputs and outputs are TTL compatible OPTIONS : MARKING * Timing 20ns access -20 25ns access -25 35ns access 235 45ns access -45 55ns access -55* 70ns access a -70* Packages Ceramic DIP (300 mil) Cc Ceramic LCC EC * 2V data retention, low power standby L Power down (gated inputs) P Electrical characteristics identical to those provided for the 45ns access device. GENERAL DESCRIPTION The Micron SRAM family employs high-speed, low- power CMOS designs using a four-transistor memory cell. Micron SRAMs are fabricated using double-layer metal, double-layer polysilicon technology. Micron SRAMs are manufactured and quality controlled in the USA at our modern Boise, Idaho, facility. For flexibility in high-speed memory applications, - Micron offers chip enable (CE) and output enable (OE) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE) PIN ASSIGNMENT (Top View) 28-Pin DIP 28-Pin LCC (D-15) (C-11) NC d1 28} Vec AOG2 270 A15 A143 26D A14 A204 250 A13 AIS 24B A12. A4d6 23 Att ASU7 220 A10 A6U8 210NC A719 202NC ag10 19) Daa Agd11 18) Das CE 412 17) paz OE 413 16) Dat Vss 414 15) WE ABSASRESB awa uss 17 Is $2185 and CE inputs are both LOW. . Reading is accomplished when WE remains HIGH and CE and OE go LOW. The device offers a reduced power standby mode when dis- abled. This allows system designs to achieve low standby power requirements. The L version provides an approximate 50 percent reduction in CMOS standby current (Issc2) over the stan- dard version. The P version provides an approximate 80 percent reduction in TTL standby current (Issti). This is achieved by including gated inputs on the WE, OE and address lines. The gated inputs also facilitate the design of battery-backed systems where the designer needs to protect against inadvertent battery-current drain during power-down, when inputs may be at undefined levels. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible. MTSC2565 883 REV. 702 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. (1992, Micton Semiconductor, Inc. S55E D MM 613431549 0005629 b28 MMRN WVdS LSVSMICRON TECHNOLOGY INC SSE D MM 6121549 0005630 34T BEMRN MT5C2565 883C MICRON 64K x 4 SRAM FUNCTIONAL BLOCK DIAGRAM T~46-2 3-1o > Voc GND ~ =| | | ~ Ai2 [Atl > a = A |AIO > Ato |A12 - : a 3 : As | AB e!] O o : oD} MEMORY ARRAY @ Z oh a3 | AS > > 8 |__ par : > A2 A2 > Fr CE Art| At o LSB Ao | Ao | (LSB) re SE th LL 1O (Lec) We COLUMN DECODER (LSB) POWER ttt?tttitit CS AT = AGCOASi (iC sC<C S(t CAA TRUTH TABLE MODE ve! te | WE pa POWER STANDBY x | H x HIGH-z | STANDBY READ t{o- H Q ACTIVE READ H| OL H HIGH-Z | ACTIVE WRITE Xx L L D ACTIVE oe 1-50 Micron Semiconductor, Inc. reserves the ight to change produce or epacttcanons etinowt nae.MICRON TECHNOLOGY INC Na tet = (end SSE D MM 61131549 0005631 246 @ENRN- MT5C2565 883C 64K x 4 SRAM T-46-2 3-10 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Input or DQ Relative to Vss ....-2V to +7V Voltage on Vcc Supply Relative to VS .............. *Stresses greater than those listed under Absolute Maxi- mum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the Storage Temperature .........ssscsssessesssessssseese device at these or any other conditions above those indi- \T1 Power Dissipation cated in the operational sections of this specification is not p> Short Circuit Output Current ...-sccccsssssscsssesesessuseen implied. Exposure to absolute maximum rating conditions (f) Lead Temperature (soldering 10 seconds) 0.00.0... for extended periods may affect reliability. =| Junction Temperature ..0...........ccosesscsssetsscssonseesssssaces wo ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS e (55C < Tg < 125C; Veco = 5V t 10%) = DESCRIPTION CONDITIONS SYMBOL | MIN MAX UNITS | NOTES ! Input High (Logic 1) Voltage Vin 2.2 | Vcc+1.0 V 1 Input Low (Logic 0) Voltage Vit 0.5 0.8 Vv 1,2 Input Leakage Current OV < Vin s Veo ili 5 5 pA Output Leakage Current Outputs Disabled ILo 5 5 pA , OV < VouT s Vec . Output High Voltage lou = -4.0mA Vou 2.4 Vv 1 Output Low Voitage lo. = 8.0mMA Vor 0.4 Vv 1 4 MAX DESCRIPTION CONDITIONS SYMBOL -20 | -25 | -35 | -45 | UNITS | NOTES Power Supply CE s Vit; Voc = MAX Current: Operating f = MAX = 1/'RE (MIN) Icc 130 | 120 | 110 | 100 mA 3 Outputs Open Power Supply CE = Vin; Vec = MAX Current: Standby f = MAX = 1/'RC (MIN) Isert 35 | 30 | 27 | 25 mA Outputs Open P Version Only IseT1 5 5 5 mA CE 2 Vin, All Other Inputs Ss Vit or > Vin, Voc = MAX IspT2 20 | 20 | 20 | 20 mA f=0Hz | P Version Only IsBT2 515 [5 ] 5 mA CE 2 Vec -0.2V; Voc = MAX Vit < Vss +0.2V Isac2 5 5 5 5 mA Vin 2 Vcc -0.2V; f = 0 Hz | L Version Only seca 313 | 3/3 mA CAPACITANCE DESCRIPTION CONDITIONS SYMBOL | MIN MAX UNITS NOTES Input Capacitance Ta = 25C, f= 1MHz Ci 8 pF 4 Output Capacitance Voc = 5V Co 8 pF 4 foe 1-51 Micron Semiconductor, Inc., reserves the right to change products or specifications without notice. 1992, Micron Semiconductor, inc.55E D MM 61312549 O005b3e Lie MENRN MICRON TECHNOLOGY INC glee a MT5C2565 883C 64K x 4 SRAM T-46-2 3-10 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 5) (-55C <T, s 125C; Vcc = 5V + 10%) y -20 -25 -35 -45 an DESCRIPTION = sym | MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX | UNITS | NOTES wo READ Cycle a READ cycle time RC 20 25 35 45 ns = Address access time AA 20 25 35 45 | ns Chip Enable access time tACE 20 25 35 45 ns Output hold from address change OH 3 3 3 3 ns Chip Enable to output in Low-Z 1ZCE | 5 5 5 5 ns 7 Chip disable to output in High-Z HZCE 9 10 14 16 ns | 6,7 Chip Enable to power-up time tpu 0 ) 0 0 ns Chip disable to power-down time PD 20 25 35 45 ns Output Enabie access time AOE 9 10 14 15 ns Output Enable to output in Low-Z 'LZOE i) 0 0 0 ns Output disable to output in High-Z tHZOE 8 10 14 15 ns 6 WRITE Cycle WRITE cycle time two 20 25 35 45 ns Chip Enable to end of write cw 15 18 20 25 | ns Address valid to end of write 'AW 15 18 20 25 ns Address setup time tas 0 0 0 0 ns Address hold from end of write . tAH 0 0 0 0 ns WRITE pulse width twp | 15 17 20 os) ns Data setup time Ds 10 12 15 20 ns Data hold time DH 0 0 0 0 ns Write disable to output in Low-Z 'LZWE | 3 3 3 3 eh Ms 7. Write Enable to output in High-Z tHZWE | 0 10 Q 11 0 14 0 15 | ns | 6,7 MT5C2565 8830 1-52 Micron Semiconductor, Inc., resarves the right to change products or spacifications without notice. REV. 702 1992, Micron Semiconductor, Inc.MICRON TECHNOLOGY INC S5E D MM 6333549 0005633 OSS mMRN MT5C2565 883C ieee ert ae eer T-46-2 3-10 AC TEST CONDITIONS +5V +5V 480 480 Input pulse levels ............eeesecsesesssecceeees Q Q Input rise and fall times ...........ccsscccssecssnseeccsseeseees 255 =r 30 pF 255 ; 7 SPF Input timing reference fevel ... Output reference teVel oo... sessssesscscescesececeeee 1.5V IVS LSV4 , Fig. 1 OUTPUT LOAD Fig. 2 OUTPUT LOAD Output load .eeecssseesssseeees See figures 1 and 2- EQUIVALENT EQUIVALENT NOTES 1. All voltages referenced to Vss (GND). 7. At any given temperature and voltage condition, : 2. -3V for pulse width < 20ns. 3. Icc is dependent on output loading and cycle rates. The specified value applies with the outputs unloaded, and f = HZCE is less than LZCE and HZWE is less than LZWE 8. WEis HIGH for READ cycle. 9. Device is continuously selected. Chip enable and output enable are held in their active state. RC ) 10. Address valid prior to or coincident with latest 4. This parameter is sampled. 5. Test conditions as specified with the output loading occurring chip e ble. aan " . - 11. 'RC = READ cycle time. as shown in Fig. 1 unless otherwise noted. 12. Chip enable (CB) and write enable (WE) can initiate 6. CE, E and F ed with CL = and terminate a WRITE cycle. 5 pF as in Fig. 2. Transition is measured + 500mV typical from steady state voltage, allowing for actual tester RC time constant. DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only) DESCRIPTION CONDITIONS SYMBOL | MIN MAX UNITS | NOTES Vcc for Retention Data Vor 2 _ Vv Data Retention Current CE = (Vee - 0.2V)|Voc = 2V] Iccor 500 pA Vin 2 (Vcc - 0.2V) ors0.2V Vcc = 8V 800 HA Chip Deselect to Data CDR 0 _ ns 4 Retention Time Operation Recovery Time 'R tRC ns 4,11 LOW Vcc DATA RETENTION WAVEFORM DATA RETENTION MODE Vee N45 Vpr>2 45V cor ta we WIR ct E WLLL: DON'T CARE R33) UNDEFINED Pees 2886 1 -53 Miron Semicond, in. roarves the dato change precucts specications wit nceMICRON TECHNOLOGY INC SSE D MM 6113549 0005634 T45 MENRN, MT5C2565 883C ee 64K x 4 SRAM READ CYCLE NO. 12:2 T~46-23-19 Tl tac | om ADDR _, VALID -y ~ AA a tou > = Q PREVIOUS DATA VALID DATA VALID READ CYCLE NO. 27.8 10 tre T*T f CE K i taOE tLZ0E | tHZOE eI F OE \ tACE tLZCE tHZCE pa HIGH-Z DATA VALID -_ tpy tpp [a lec | | DON'T CARE RX) UNDEFINED MT5C2565 BBSC- 1 54 Micron Semiconductor, Inc., reserves the right 10 change products or specifications without notice. REV, 7492 - 7982, Micron Semiconductor, Inc.MICRON TECHNOLOGY INC 55E D MM 6122549 0005635 42] MEMRN Rac , MT5C2565 883C tl eS 64K x 4 SRAM WRITE CYCLE NO. 1 72 T-46-23- 10 (Chip Enable Controlled) | we z ADDR } ] XK YW taw tas | tow taH & eo > _ we = we WLLL ] / tos toy D DATA VALID Q HIGH-Z WRITE CYCLE NO. 27.12 (Write Enable Controlled) two ADDR Y 4 taw | cw 'aH WY TLD j L, |. tas we We WE WLS I os pH dD DATA VALID Q HIGH-2 DON'T CARE RR] UNDEFINED NOTE: Output enable (OE) is inactive (HIGH). Micron Semiconductor, inc., reserves the right bo change products or specifications without natioa. REV. 792 , 1-55 1982, Micron Semiconductor, Inc.MICRON TECHNOLOGY INC SSE D MM 6333549 0005636 464 MMNRN MICRON MT5C2565 883C 64K x 4 SRAM 0 ELECTRICAL TEST REQUIREMENTS a es la "Ti SUBGROUPS > MIL-STD-883 TEST REQUIREMENTSV (per Method 5005, Table |) ) | inTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS 2, 8A, 10 =| (Method 5004) ~ FINAL ELECTRICAL TEST PARAMETERS 1", 2, 3, 7", 8, 9, 10, 11 I (Method 5004) > GROUP A TEST REQUIREMENTS 1, 2,3, 4", 7,8, 9, 10, 11 = (Method 5005) GROUP C AND D END-POINT ELECTRICAL PARAMETERS 1, 2,3,7,8,9, 10, 11 (Method 5005) * PDA applies to subgroups 1 and 7. ** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input or output capacitance. 1992, Micron Semiconductor, inc. MTSC2565 8836 1 56 Micron Semiconductor, Inc., reserves the right to change products of specifications without notice. REV. 7/82 -