M41T81SM6ET - STMicroelectronics

1/29September 2005

M41T81S

Serial Access Real-Time Clock with Alarms

* Contact local ST sales office for availability.

Rev 4.0

FEATURES SUMMARY

■COUNT ERS FOR TENTHS/HUNDREDTHS

OF SECONDS, SECONDS, MINUTES,

HOURS, DAY, DATE, MONTH, YEAR, AND

CENTURY

■32KHz CRYSTAL OSCILLATOR WITH

INTEGRAT ED LOAD CAPAC ITANCE

(12.5pF ) WHICH PROVIDES EXCEPTIONAL

OSCILLATOR STABILITY AND HIGH

CRYSTA L SERIES RESISTANCE

OPERATION)

■OSCILLATOR STOP DETECTION

(MONITORS CLOCK OPE RATION)

■SERIAL INTERFACE SUPPORTS I2C BUS

(400kHz PROTOCOL)

■ULTRA-L OW BA TTERY SUPP LY CURRENT

OF 0.6µA ( typ)

■2.0 TO 5 .5 V C L O C K O PER AT IN G VOLT AGE

■AUTOMATIC SWITCHOVER AND

DESELECT CIRCUITRY (FIXED

REFERENCE) WHICH PROV IDES FULL

OPERATIO N IN 3.0V APPLICATIONS)

–V

CC = 2.7 to 5.5V

2.5V ≤ VPFD ≤ 2.7V

■POWER-DOWN TIME STAMP ( H T BIT )

WHICH ALLOWS DETERMINATIO N OF

TIME EL APSED IN BATTERY BACK-U P

■BATTERY LOW F L AG

■P ROG R AMMABLE ALARM AND

INTERRUPT FUNCTIO N (valid even during

Batt ery Back-up Mode)

■ACCURATE PROGRAMMABLE

WA TCHDO G TIMER (from 62.5ms to 128s)

■SOFTWARE CLOCK CALIB RATION (TO

COMPEN SATE FO R C R YSTAL DEVIATION

DUE TO TEMPERATURE)

■OP ERAT ING TEMPER ATURE OF –40 TO

85°C

■PAC KAG E OPT IO N S IN CL U D E AN 8-L EAD

SOIC OR 18-LEAD EMBEDDED CRYSTAL

SOIC

Figure 1. Packages

SO8 (M)

8-pin SOIC

SOX18 (MY)*

18-pin (300mil) SOIC

with Embedded Crystal

M41T81S

2/29

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPT ION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Na mes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. 8-pin SOIC (M) Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 4. 18-pin, 300mil SOIC (MY) Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 6. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 7. Acknowledg eme nt Sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 8. Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 9. READ Mode S equen ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 10.Alternative READ Mode Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

Figure 11.WRITE Mode Seq uence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Power-down Timestamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

TIMEKEEPER® Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Table 2. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Calibrating th e Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

Figure 12.Crystal Accuracy Acro ss Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 13.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

Figure 14.Alarm Interru pt Reset W aveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 15.Back-up Mode Alarm Wavefo rm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3. A larm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Watchdog Time r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

Sq uare Wave Outp ut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4. S quare Wav e Output Frequen cy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Oscillator Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Oscillator Fail Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Preferred Initial Power-o n Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Table 5. Prefe rred Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3/29

M41T81S

MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0

Table 7. Operating and AC Measurement Conditi ons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 16.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1

Table 10. Crystal Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 17.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11 . Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12 . Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 18.Bus Timing Requiremen ts Sequenc e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 19.SO8 – 8-lead Plastic Small Package Out line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 14. SO8 – 8-lead Plast ic Small Outline (150 mils body width), Package Mech. Data. . . . . . 25

Figure 20.SOX18 – 18-lead Plastic Small Outli ne, 300mils, Embed ded Crystal, Outline . . . . . . . . 26

Table 15. SOX 18 – 18-lead Plast ic Small Ou tline, 300mils , Embedded Crystal, Package M ech. . 26

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 16. Orderi ng Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17. Document Revi sion History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

M41T81S

4/29

S UM MARY DESCR IPTION

The M41T81S Serial Access TIMEKEEPER®

SRAM is a low power Serial RTC with a built-in

32.768kHz oscillator (external crystal controlled).

Eight bytes of the SRAM (see Table 2., page 12)

are used for the clock/calendar function and are

configured in bina ry cod ed dec imal (BCD) form at.

An additional 12 bytes of SRAM provide status/

control of Alarm, Watchdog and Square Wave

functions. Addresse s and data are transferred se-

rially via a two line, bi-directional I2C i nte rf ace. The

built-in address register is incremented automati-

cally after each WR ITE or READ data byte.

The M41T81S has a built-in power sense circuit

which detects power failures and automatically

switches to the battery supply when a power fail-

ure occurs. The energy needed to sustain the

clock operations can be supplied by a small lithium

button supply when a power failure occurs. Func-

tions available to the user include a non-volatile,

time-of-day clock/calendar, Alarm interrupts,

Watchdog Timer and programmable Square

Wave output. The eight clock address locations

contain the century, year, month, d ate, day, hour,

minute, second and tenths/hundredths of a sec-

ond in 24 hour BCD format. Corrections for 28, 29

(leap year - valid until year 2100), 30 and 31 day

months are made automat ically.

The M 41T8 1S is supplied in either an 8-pin SOI C

or an 18-pin (MY), 300mil SOIC package which i n-

cludes an embedded 32k Hz crysta l.

The 18-pin, embed ded cryst al SOIC requires only

a user-supplied battery to provide non -volatile op-

eration.

Figure 2. Logic Diagram

Note: 1. For SO 8 package only.

Table 1. Signal Names

Note: 1. For SO 8 package only.

2. NC and NF p ins should be tied to VSS.

SCL

VCC

M41T81S

VSS

SDA

IRQ/FT/OUT/SQW

VBAT

XI(1)

XO(1)

AI09160

XI(1) Oscillator Input

XO(1) Oscillator Output

IRQ/OUT/

FT/SQW Interrupt / Output Driver / Frequency

Test / Square Wave (Open Drain)

SDA Serial Data Input/Output

SCL Serial Clock Input

VBAT Battery Supply Voltage

VCC Supply Voltage

VSS Ground

NC(2) No Connect

NF(2) No Function

5/29

M41T81S

Figure 3. 8-pin SOIC (M) Connecti ons

Note: 1. Open Drain Ou tput

Figure 4. 18-pin, 300mil SOIC (MY)

Connections

Note : 1. NC a nd NF pi ns s hou ld be tied to VSS. Pins 2 an d 3 ar e

intern all y sho rted t oget her . Pins 17 an d 16 are int erna lly

sho r te d toge th er.

2. Open Drain Output

Figu re 5. Blo ck Diagram

Note: 1. Open Drain Ou tput

2. Sq uare Wave functi on has the highest pr i ori t y on IRQ/FT/OUT/ SQW output.

1IRQ/FT/OUT/SQW(1)

SDA

VBAT SCL

VSS

XI VCC

M41T81S

AI09161 8

NF(1)

SCL

SDA

VSS

VBAT

NF(1)

VCC

M41T81S IRQ/FT/OUT/SQW(2)

NF(1)

AI09162

REAL TIME CLOCK

CALENDAR

RTC W/ALARM

& CALIBRATION

WATCHDOG

OSCILLATOR FAIL

CIRCUIT

SQUARE WAVE

FREQUENCY TEST

OUTPUT DRIVER

IRQ/FT/OUT/SQW(1)

INTERNAL

POWER

SQWE(2)

AFE

SDA

SCL

VCC

OFIE

COMPARE

I2C

INTERFACE

32KHz

OSCILLATOR

VBAT

CRYSTAL

VSO

VPFD AI09163

WRITE

PROTECT

OUT

M41T81S

6/29

OPERATION

The M41T81S clock operates as a slave device on

the serial bus . Access is obtained by implementing

a start condition f ollowed by the correc t slave ad-

dress (D0h). The 20 bytes cont ained in the device

can then be accessed sequentially in t he foll owing

order:

1. Tenths/ Hundredths of a Second Register

2. Seconds Register

3. Min utes Register

4. Century/Hours Regi ster

5. Day Register

6. D ate Register

7. Month Regist er

8. Yea r Register

9. C alibration Register

10. W atchd og Register

11 - 15. A la rm Registers

16. Flags Register

17 - 19. Reserved

20. Square Wave Regi st er

The M41T81S clock continually monitors VCC for

an out-of-toleranc e condition. S hould VCC f all be-

low VPFD, the device terminates an access in

progress and resets the device address counter.

Inputs to the device will not be recognized at this

time to prev ent erroneous data fr om bei ng wri tten

to the device from a an out-of-tolerance system.

Once VCC falls below the switchover voltage

(VSO), the device automatically switches over to

the battery and powers down i nto an ult ra-low cur-

rent mode of operation to preserve battery life. If

VBAT is less than VPFD, the device power is

switched from VCC to V BAT when V CC drops bel ow

VBAT. If VBAT is greater than VPFD, the device

power is switched from VCC to VBAT when VCC

drops below VPFD. Upon power-up, the device

switches from battery to VCC at VSO. When VCC

rises a bov e VPFD, it will recognize the i n puts.

For more information on Battery Storage Li fe refer

to Application Note AN1012.

2-Wire Bus Characteristics

The bus is intended for communication between

different ICs. It consists of two lines: a bi-direction-

al data signal (SDA) and a clock signal (SCL).

Both the SDA and SCL lines mus t be connected to

a positive supply voltage via a pull-up resist or.

The following protocol has been defined:

– Data transfer may be initiated only when the

bus is not busy.

– During data transfer, the data line must remain

stable whenever the clock line is High.

– Changes in the data line, while the clock line is

H igh, will be interpreted as control signals.

Accordingly, the following bus conditions have

been defined:

Bus not busy. Both data and clock lines remain

High.

Start data transfer . A change in th e state of the

data line, from high to Low, while the clock is High,

defines the START condi tion.

Stop data transfer. A change in the state of the

data line, from Low to High, while the clock is High,

defines the STOP condition .

Data Va lid. The state of the data line represe nts

valid data when after a start condition, the dat a line

is stable for the d uration of the high period of the

clock signal. T he data on the line may be changed

during the Low period of the clock signal. There i s

one clock pulse per bit of data.

Each data transfer is initiated with a start condi tion

and terminated with a stop condition. The number

of data bytes transferred between the start and

stop conditions is not limited. The information is

transmitted byte-wide and each rec eiver ack nowl-

edges with a nin th bit.

By definition a dev ice t hat gives o ut a m essag e is

called “transmitter,” the receiving dev ice that gets

the messa ge is called “receiver.” The device that

controls the message is called “master.” The de-

vices that are controlled by the ma ster are called

“slaves.”

Acknowledge. E ac h byte of eight bits is f ollowed

by one Acknowledge B it. This Acknowled ge Bit is

a low level put on t he bus by the receiver whereas

the master generates an extra acknowled ge relat-

ed clock pulse. A slave receiver which is ad-

dressed is obliged to generate an acknowledge

after the reception of each byte that has been

clocked out of the slave transmitter.

The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse

in such a way that the SDA line is a stable Low dur-

ing the High period of the acknowledge related

clock pulse. Of course, setup and hold times mus t

be taken int o account. A master recei ver must sig-

nal an end of data to the slave transmitter by not

generating an acknowledge on the last byte that

has been cloc ked out of the slave. In this case the

transmitter must l eave the data l ine High to enable

the mast er to generate the STOP condition.

7/29

M41T81S

Figure 6. Serial Bus Data Transfer Sequen ce

Figure 7. Acknowledgement Sequence

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION CHANGE OF

DATA ALLOWED STOP

CONDITION

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCL FROM

MASTER

START CLOCK PULSE FOR

ACKNOWLEDGEMENT

12 89

MSB LSB

M41T81S

8/29

READ Mode

In this mode the master reads t he M41T81S sl ave

after setting the slave address (see Figure

9., page 9). Following the WRITE Mode Control

Bit (R/W=0) and the Acknowledge Bit, the word

address 'An' is written to the on-chip address

pointer. Next the START condition and slave ad-

dress are repeated followed by the READ Mode

Control Bit (R/W=1). At this point the master trans-

mitter becomes the master receiver. The data byte

which was addressed will be transmitted and the

master receiver will send an Acknowledge Bit to

the slave transmitter. The address pointe r is only

incremented on reception of an Acknowledge

Clock. The M41T81S slave transmitter will now

place the data byte at address An+1 on the bus,

the master receiver reads and acknowledges the

new byte and the ad dress pointer is incremented

to “An+2.”

This cycle of reading consecutive addresses will

continue until the master receiver se nds a STOP

condition to the slave transmitter.

The system-to-user transfer of clock data will be

halted whenever the address bei ng read is a clock

address (00h to 07h). The update will resu me due

to a Stop Condition or when the pointer increments

to any non-clock address (08h-13h).

Note: This is true bot h in READ Mode and WRITE

Mode.

An alternate READ Mode may also be implement-

ed whereby the m as ter reads the M41T8 1S s lave

without first w ri ting to the (volatile) addres s poin t-

er. The first address that is read is the last one

stored in the pointer (see Figure 10. , page 9).

Figure 8. Slave Address Lo cation

AI00602

R/W

SLAVE ADDRESS

START A

0100011

MSB

LSB

9/29

M41T81S

Figure 9. READ Mode S equence

Figu re 10 . Al te rnat i ve R E A D Mod e Seque nce

AI00899

BUS ACTIVITY:

ACK

NO ACK STOP

START

SDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

START

R/W

SLAVE

ADDRESS

ACK

AI00895

BUS ACTIVITY:

ACK

NO ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

SLAVE

ADDRESS

M41T81S

10/29

WRITE Mod e

In this mode the master transmitter transmits to

the M41T81S slave receiver. Bus protocol is

shown in Figure 11., page 10. Following the

START condition and slave address, a logic '0' (R/

W=0) is placed on the bus and indicates to t he ad-

dressed device that word address “An” will follow

and is to be written to t he on-chip address pointer.

The data word to be written to the memory is

strobed in next and t he internal addres s pointer is

incremented to the next address location on the

reception of an acknowledge cl ock. The M41T81S

slave receiver will send an acknowledge clock to

the master transmitter after it has received the

slave address see F igure 8., page 8 and again af-

ter it has received the word address and each data

byte.

Data Reten tion Mode

With valid VCC applied, the M41T81S can be ac-

cessed as des cribed ab ov e with REA D or WRI TE

Cycles. Should the supply voltage decay, t he pow-

er input will be switched from the VCC pin to the

battery when V CC falls below the Battery Back-up

Switchover Voltage (VSO). At this time the clock

registers will be maintained by the attached bat-

tery supply. On power-up, when VCC returns to a

nominal val ue, write protection conti nues for tREC.

For a further, more detailed review of lifetime cal-

culations, please see Application Note AN1012.

Figure 1 1. WR I TE Mode Se qu e nce

AI00591

BUS ACTIVITY:

ACK

ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

11/29

M41T81S

C LOCK OPERATION

The 20-byte Regi ster Map (see Table 2., page 12)

is used to bot h set the clock and to re ad the date

and time from the clock, in a bi nary coded decimal

format. Tenths /H undredths of S econds, Second s,

Minutes, and Hours are contained within the first

four registers.

Note: Tenths/Hundredths of Seconds cannot be

written to any value other than “00.”

Bits D6 and D7 of Clock Register 03h (Century/

Hours Register) contain the CENTURY ENABLE

Bit (CEB) and the CENTURY Bit (CB). Setting

CEB to a '1' will cause CB to toggle, either from '0'

to '1' or fr om '1' to '0' at the turn of the century (de-

pending upon its initial state). If CEB is set to a '0,'

CB will not toggle. B its D0 through D2 of Register

04h contain the Day (day of week). Registers 05h,

06h, and 07h contain the Date (day of month),

Month and Years. The ninth clock register is the

Calibration Register (this is described in the Clock

Calibration section). Bit D7 of Register 01h con-

ta ins the STOP Bit ( ST). Settin g th is bit to a ' 1 ' wil l

cause the oscillator to stop. If the device i s expect -

ed to spend a significant amount of time on the

shelf, the oscillator may be stopped to reduce cur-

rent drain. When reset t o a '0' the oscillator restarts

within one second.

The eight Clock Registers may be read one byte at

a time, or in a sequent ial block. Provision has been

made to assure that a clock update does not occur

while any of the eight clock addresses are being

read. If a clock address is being read, an update of

the clock registers will be halted. T his will prevent

a transition of data duri ng the READ.

Power-dow n Tim estamp

When a power failure occurs, the HALT (HT) Bit

will automatical ly be set to a '1.' T his wil l prevent

the clock from updat i ng the TIMEKEEPER® regis-

ters, and will allow the user to read the exac t time

of the power-down event. Resetting the HT Bit to

a '0' will allow the clock to update the TIMEKEEP-

ER registers with the current time.

TIMEKEEPER® Registers

The M41T81S offers 20 internal registers which

contain Clock, Alarm, Watchdog, Flags, Square

Wave and Calibration data. These registers are

memory locations which contain external (user ac-

cessible) and internal copies of the data (usually

referred to as BiPORT™ TI MEKEEPER cells) . The

external copies are independent of internal func-

tions except that they are updated p eriodically by

the simultaneous transf er of the incremented inter-

nal copy. The internal divider (or clock) chain will

be reset upon the completion of a WRITE to any

clock addr ess.

The system-to-user transfer of clock data will be

halted whenever the address bei ng read is a clock

address (00h to 07h). The update will resume ei-

ther due to a Stop Condition or when the pointer

increments to any non-clock address (08h-13h).

TIMEKEEPER and Alarm Registers store data in

BCD. Calibration, Watchdog and Square Wave

Registers store data in Binary Format.

M41T81S

12/29

Table 2. TIME KEEPER ® Re g ister Map

K eys: 0 = Mus t be set to '0'

ABE = Alarm in Bat te ry Back-u p Mode Enable Bit

AF = A l arm F l ag (Read only)

AFE = Alarm Flag Enable Flag

BL = Battery Low Bit

BMB0-BMB4 = Watchdog Multiplier Bits

CB = Century B i t

CE B = C entury Enable Bit

FT = Frequency Test Bit

HT = Halt Updat e B i t

OF = Oscillator Fail Fla g

OFIE = Oscillator Fail Interrupt Enable

OUT = Output level

RB 0-RB1 = Wa tc hdog Resolution Bits

RP T 1-RPT5 = A l arm Repeat M ode Bits

RS 0-RS3 = SQ W Frequency

S = Sig n Bit

SQWE = Square Wave Enable

ST = Sto p Bit

WDF = Watchd og Flag (Read onl y)

Addr Function/Range BCD

Format

D7 D6 D5 D4 D3 D2 D1 D0

00h 0.1 Seconds 0.01 Seconds Seconds 00-99

01h ST 10 Seconds Seconds Seconds 00-59

02h 0 10 Minutes Minutes Minutes 00-59

03h CEB CB 10 Hours Hours (24 Hour Format) Century/

Hours 0-1/00-23

04h 0 0 0 0 0 Day of Week Day 01-7

05h 0 0 10 Date Date: Day of Month Date 01-31

06h 0 0 0 10M Month Month 01-12

07h 10 Years Year Year 00-99

08h OUT FT S Calibration Calibration

09h OFIE BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

0Ah AFE S QWE ABE Al 10M Alarm Mont h Al Month 01-12

0Bh RPT4 RPT5 AI 10 Date Alarm Date Al Date 01-31

0Ch RPT3 HT AI 10 Hour Alarm Hour Al Hour 00-23

0Dh RPT2 Alarm 10 Minutes Alarm Minutes Al Min 00-59

0Eh RPT1 Alarm 10 Seconds Alarm Seconds Al Sec 00-59

0Fh WD F AF 0 BL 0 OF 0 0 Flags

10h00000000Reserved

11h00000000Reserved

12h00000000Reserved

13h RS3 RS2 RS1 RS0 0 0 0 0 SQW

13/29

M41T81S

Ca libr a tin g t h e C lock

The M4 1T81S is driven by a qu artz controlled os-

cillator with a nominal frequency of 32,768Hz. The

devices are t ested not ex ceed ±35 ppm (parts per

million) oscillator frequency error at 25oC, which

equates t o about + 1.9 to –1.1 m inutes per month

(see Figure 12., page 14). When the Calibration

circuit i s properly employed, accuracy improves to

better than ±2 ppm at 25°C.

The oscillation rate of crystals changes with tem-

perature. The M41T81S design employs peri odic

counter correction. The calibration circuit adds or

subtracts counts from the o scillator divi der circuit

at the divide by 256 stage, as shown in Figure

13., page 14. The number of times pulses which

are blanked (subtracted, negative calibration) or

split (added, positive calibration) depends upon

the value loaded into the five Calibration B its found

in the Calibration Re giste r. Adding c ounts speeds

the clock up, subtracting counts slows the clock

down.

The Calibration Bits occupy the five lower order

bits (D4-D0) in the Calibration Register 08h. These

bits can be set to represent any value between 0

and 31 in binary form. Bit D5 is a Sign Bit; '1' indi-

cates positive calibration, '0' indicates negative

calibration. Calibration occurs within a 64 minute

cycle. The first 62 m inutes i n the cycle m ay, once

per minute, h ave one second either shortened by

128 or lengthened by 256 oscillator cycles. If a bi-

nary '1' is loaded into the register, only the first 2

minute s in the 64 minute cycle will be modified; if

a binary 6 is loaded, the first 12 will be affected,

and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 osc illator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step in the calibration register (see Figure

13., page 14). Assuming t hat the oscillator is run-

ning at exactly 32,768Hz, each of the 31 incre-

ments in the Calibration byte would represent

+10.7 or –5.35 seconds per month which corre-

sponds to a total range of +5.5 or –2.75 minutes

per month.

Two methods are available for ascertaining how

much cal ibration a giv en M41T81S may require.

The first involves setting the clock, lett i ng it run for

a month and comparing it to a known accurate r ef-

erence and r ecor ding dev iation over a fixed period

of time. Calibration values, including the number of

seconds lost or gained in a given period, can be

found in Application Note AN934, “TIMEKEEP-

ER® CALIBRATION.” This allows the designer to

give the end user the ability to calibrate the clock

as the environment r equi res, even i f the final prod-

uct is packaged in a non-user serviceable enclo-

sure. The designer could provide a simple utility

that accesses the Calibration byte.

The second approach is better suited to a m anu-

facturing environment, and involves the use of the

IRQ/FT/OUT/SQW pin. The pin will toggle at

512Hz, when the Stop Bit (ST, D7 of 01h) is '0,' the

Frequency Test Bit (FT, D6 of 08h) is '1,' the Alarm

Flag Enable Bit (AFE, D7 of 0Ah) is '0,' and the

Square Wave Enable Bit (SQWE, D6 of 0Ah) is '0'

and the Watchdog Register (09h = 0) is reset.

Any deviation from 512Hz indicates the degree

and direction of oscillator frequency shift at the test

temperature. For example, a reading of

512.010124Hz would indicate a +20 ppm oscillator

frequency error, requiring a –10 (XX001010) to be

loaded into the Calibration Byte for correction.

Note that setting or changing the Calibration Byte

does not affect the Frequency Test output fre-

quency.

The IRQ/FT/OUT/ SQW pin is an open drain output

which requires a pull-up resistor to VCC for proper

operation. A 500-10k resistor is recommended in

order to c ontrol the rise time. T he FT Bit i s cleared

on power-down.

M41T81S

14/29

Figure 12. Crys tal Accuracy Acro ss Tem p eratur e

Figu re 13 . Cl ock C al ib r at i on

AI07888

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

= –0.036 ppm/°C2 ± 0.006 ppm/°C2

∆F= K x (T – TO)2

TO = 25°C ± 5°C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

15/29

M41T81S

Setting Alarm Clock Registers

Address locations 0Ah-0E h cont ain the alarm se t-

tings. The alarm can be configured to go off at a

prescribed time on a specific month, date, hour,

minute, or second or repeat every year, month,

day, hour, minute, or second. It can also be pro-

grammed to go off while the M41T81S is in the

battery back-up mode to serve as a system wake-

up call.

Bits RPT5-RPT1 put the alarm in the repeat mode

of operation. Table 3., page 16 shows the possible

configurations. Codes not listed in the table default

to the once per second mode to quickly alert the

user of an incorrect al arm setting.

When the clock information matches the alarm

clock settings based on the match crit eria d efined

by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE

(Alarm Flag Enable) is also set (and SQWE is '0.'),

the alarm condition activates the IRQ/FT/OUT/

SQW pin.

Note: If the address pointer is allowed to incre-

ment to t he F l ags Register address, an al arm con-

dition will not cause the Interrupt/Flag to occur until

the address pointer is moved to a different ad-

dress. It should also be noted that if the last ad-

dress written is the “Alarm Seconds,” the address

pointer will increment to t he F lag address, c ausi ng

this situation to occur.

The IRQ/FT/OUT/SQW output is cleared by a

READ to the Flags Register as shown in Figure

14. A subsequent READ of the Flags Register is

necessary to see that the value of the Alarm Flag

has been reset to '0.'

The IRQ/FT/OUT/SQW pin can also be a ctivated

in the battery back-up mode. The IRQ/FT/OUT/

SQW will go low if an alarm occ urs and both A BE

(Alarm in Battery Back-up Mode Enable) and AFE

are set. Figure 15 illustrates the back-up mode

alarm timing.

Figure 14. Alarm Interrupt Reset Waveform

Figure 15. Back-up Mode Alarm Wave form

IRQ/FT/OUT/SQW

ACTIVE FLAG

0Fh0Eh 10h

HIGH-Z

AI04617

VCC

IRQ/FT/OUT/SQW

ABE and AFE Bits

AF Bit in Flags

HIGH-Z

VSO

VPFD

trec

AI09164b

M41T81S

16/29

Table 3. Alarm Repeat Modes

Watchdog Timer

The watchdog timer can be used to detect an out-

of-control microprocessor. The us er program s the

watchdog timer by setting the desired amount of

time-out into the Watchdog Register, address 09h.

Bits BMB4-BMB0 store a binary mul tiplier and the

two lower order bits RB1-RB0 select the resolu-

tion, where 00 = 1/16 second, 01 = 1/4 second,

10 = 1 second, and 11 = 4 seconds. The amount

of time-out is then determined to be the multiplica-

tion of the five-bit multiplier value with the resolu-

tion. (For example: writing 00001110 in the

Watchdog Register = 3*1, or 3 seconds). If the

processor does not reset t he timer within the spec-

ified period, the M41T81S sets the WDF (Watch-

dog Flag) and generates a watchdog interrupt.

The watc hdog timer can be reset by having the mi-

croprocessor perform a WRITE of the Watchdog

Should the watchdog timer time-out, a value of

00h needs to be written to the Watchdog Regi ster

in order to clear the IRQ/FT/OUT/SQW pin. This

will also disable the watchdog function until it is

again programm ed corr ectly. A RE AD of the Fl ags

The watchdog function is automatically disabled

upon power-up and the Watchdog Register is

cleared. If the watchdog function is set, the fre-

quency test function is activated, and the SQWE

Bit is '0,' the watchdog function prevails and the

frequency test function is denied.

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Setting

1 1 1 1 1 O nce per Second

1 1 1 1 0 Once per Minute

1 1 1 0 0 Once per Hour

11000 Once per Day

1 0 0 0 0 Once per Month

00000 Once per Year

17/29

M41T81S

Square Wave Output

The M41T81S offers the user a programmable

square wave function which is output on the SQW

pin. RS3-RS0 bits located in 13h establish the

square wave output f requency. These frequencies

are listed in Table 4. Once the selection of the

SQW f requency has been completed, the IRQ/FT/

OUT/SQW pin can be turned on and of f under soft-

ware control with the Square Wave Enable Bit

(SQWE) located in Register 0Ah.

Table 4. Square Wave Output Frequency

Square Wave Bits Square Wave

RS3 RS2 RS1 RS0 Frequency Units

0000None-

000132.768kHz

00108.192kHz

00114.096kHz

01002.048kHz

01011.024kHz

0110512Hz

0111256Hz

1000128Hz

100164Hz

101032Hz

101116Hz

11008Hz

11014Hz

11102Hz

11111Hz

M41T81S

18/29

Century Bit

Bits D7 and D6 of Clock Register 03h contain the

CENTURY ENABLE Bi t (CEB) and the CENTURY

Bit ( CB). Setting CEB to a '1' will cause CB to tog-

gle, either from a '0' to '1' or fr om '1' to '0' at the turn

of the century (depending upon its initial state). If

CEB is s et to a '0,' CB will not toggle.

Batt ery Lo w W arn in g

The M41T81S automatically performs battery volt-

age monit oring upon power-up and at factory-pro-

grammed time intervals of approximately 24

hours. The Battery Low (BL) Bit, Bit D4 of Flags

is found to be less than approximately 2.5V. The

BL Bit will r emain asserted unt i l completion of bat-

tery replacement and subsequent battery low

monitoring tests, either during the next power-up

sequence or the next scheduled 24-hour interval.

If a battery low is generated during a power-up se-

quence, this indicates that the battery i s below ap-

proximately 2.5 volts and may not be able to

maintain data in tegrity. Clock dat a should be con-

sidered suspect and verified as correct. A fresh

battery should be installed.

If a battery low indication is generated during the

24-hour interval check, this indicates that the bat-

tery is n ear end of life. Howe ver, dat a i s not com-

promised due to the fact that a nominal VCC is

supplied. In order to insure data integrity during

subsequent pe riods of bat tery back-up m ode, the

battery should be replaced.

The M41T81S only monitors the battery when a

nominal VCC is applied to the device. Thus ap pli-

cations which require extensive durations in the

battery back- up mode should be powered-up peri-

odically (at least once every few mont hs) in order

for this technique to be beneficial. Addit ionally , if a

battery low is indicated, data integrity should be

verified upon power-up via a checksum or other

technique.

Osc illator Fail Detec t io n

If the Oscillator Fail Bit (OF) is internally set to '1,'

this indicates that the oscillator has either stopped,

or was stopped for some period of time and can be

used to judge the validity of t he clock and date da-

ta.

In the event the OF Bit is found to be set to '1' at

any time other than the initial power-up, the S TOP

Bit (ST) should be written t o a '1,' then immediately

reset to '0.' Th is w ill r es tart the os c ill a tor .

The following co nditions can cau se the OF Bit to

be set:

– The first time power is applied (defaults to a '1'

on powe r-u p).

– The volt age present on VCC is i n su fficient to

suppor t os c illation .

– The ST Bit is set to '1.'

– External interferenc e of the crystal.

The OF Bit will remain set to '1' until written to logic

'0.' The oscillator must start and have run for at

least 4 seconds before attempt ing to reset the OF

Bi t to '0. '

Osc illator Fail I nte r r up t Enable

If the Oscillator Fail Interrupt Bit (OFIE) is set to a

'1,' the IRQ pin will also be activat ed. The IRQ out -

put is cleared by resetting the OFIE or OF Bit t o '0'

(not be reading the Flags Register).

Output Driver Pin

When the F T Bit, AFE Bit , SQ WE Bi t, and Wa tch-

dog Register are not set, the IRQ/FT/OUT/SQW

pin becomes an output driver t hat reflects t he con-

tents of D7 of the Calibration Register. In other

words, when D7 (O UT Bit) and D6 (FT Bit) of ad-

dress location 08h are a '0,' then the IRQ/FT/OUT/

SQW pi n will be dri ven low.

Note: The I RQ/ FT/OUT/SQW pin i s an open drain

which requires an external pull-up resistor.

Preferred Initial Power-on D ef au lt

Upon initial application of power to the device, the

following register bit s are set to a '0' st ate: Watch-

dog Register; AFE; ABE; SQWE; OFIE; and FT.

The following bits are set to a '1' state: ST; OUT;

OF; and HT (see Table 5., page 18).

Table 5. Preferred Default Values

Not e: 1. BMB0- BMB4 , RB0, RB1.

2. Stat e of othe r contro l b its undefined.

3. UC = Unchanged

Condition ST HT Out FT AFE SQWE ABE WATCHDOG

Initial Po wer-up(2) 1110000 0 10

Subsequent Power-up

(with battery back-up)(3) UC 1 UC 0 UC UC UC 0 UC UC

19/29

M41T81S

MAXI MUM RAT IN G

Stressing the device ab ove t he rating listed in t he

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Oper ating sections of this specification is

not impl ied. Exposure to Absol ute Max imum Ra t-

ing conditions for extended periods may affect de-

vice reliability. Refer also to the

STMicroelectronics S URE P rogram and other rel-

evant quality documents.

Table 6. Absolute Maximum Ratings

Note: 1. For SO8 package, Lead-free (Pb-free) lead f inish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C

for greater than 30 seconds).

2. For SO8 package, standard (SnPb) lead finish: Reflow at peak temperature of 240°C (total thermal budget not to exceed 180°C for

betw ee n 90 to 150 seconds).

3. The SO X18 pac k age has Lead- fr ee (P b-fr ee) l ead fin ish , b ut c an not b e exp os ed to peak r eflow tem pe ratur e in exc ess of 24 0°C

(use same reflow profile as st andard (SnPb) le ad finis h).

CAUTION: Negativ e undershoots bel ow –0.3 vol ts are no t all owed on any pin whi l e i n t he Battery Back-up Mod e

Sym Parameter Value Unit

TSTG Storage Tempe rature (VCC Off, Oscillator Off) SOIC –55 to 125 °C

VCC Supply Voltage –0.3 to 7 V

TSLD Lead Solder Temperature for 10 Seconds Lead-free lead finish (1) 260 °C

Standard (SnPb)

lead finish(2,3) 240 °C

VIO Input or Output Voltages –0.3 to Vcc+0.3 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

M41T81S

20/29

DC AND A C PARAMETE RS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Charac teristic tables are

derived from tests pe rform ed under the Measure-

ment Condition s listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 7. Operating and AC Measurem en t Conditions

Note: O ut put Hi-Z is def i ned as the poin t where dat a i s no longer driven.

Figu re 16. AC Measure m e nt I/ O Wa veform

Table 8. Capacitance

Note: 1. Eff ective c apacitance measured wi th power supply at 5V; s am p l ed only, not 100% tested.

2. At 25°C, f = 1M Hz.

3. Out puts desel ected.

Parameter M41T81S

Supply Voltage (VCC)2.7 to 5.5V

Ambient Operating Temperature (TA)–40 to 85°C

Load Capacitance (CL)100pF

Input Rise and Fall Times ≤ 50ns

Input Pulse Voltages 0.2VCC to 0.8 VCC

Input and Output Timing Ref. Voltages 0.3VCC to 0.7 VCC

AI02568

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance 7 pF

COUT(3) Output Capacitance 10 pF

tLP Low-pass filter input time constant (SDA and SCL) 50 ns

21/29

M41T81S

Table 9. DC Characteristics

Note: 1. Val i d for Ambient Operating T em perature: TA = –40 t o 85°C; VCC = 2.7 to 5.5V (e x cept wh ere noted).

2. For IRQ/FT/OUT/ SQW pin (O pen Drain)

3. STMi croelectro ni cs recommend s t he RAYOVA C BR12 25 or BR1632 (or equivalen t) as t he batte ry suppl y.

4. For rechargeabl e back-u p, VBAT (max ) m ay be cons i dered to be VCC.

Table 10. Crystal Electrical Characteristics

Note : 1. Ext erna lly supp lied if usin g th e SO8 pa ckag e. S TMi croe lec tronic s re co mmend s the KD S DT-38 : 1TA/ 1TC252 E 127, Tun ing Fork

Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quart z crystal for industrial temperature operations. KDS can be con-

tacted at kouhou@kdsj.co. j p or http:// www.kdsj.co.j p for further informati on on this cr ystal type.

2. Load capacitors are integrated within the M41T81S. Circuit board layout considerat ions for the 32.768kHz crystal of minimum trace

leng ths and isolation from RF generating sig nal s should be take n i nto acco unt.

3. For applications requiring back -up supply operat i on below 2.5V, RS (max) should be considered 40kΩ.

Sym Parameter Test Condition(1) Min Typ Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current Switch Freq = 400kHz 400 µA

ICC2 Supply Current (standby)

SCL = 0Hz

All Inputs

≥ VCC – 0.2V

≤ VSS + 0.2V

100 µA

VIL Input Low Voltage –0.3 0.3VCC V

VIH Input High Voltage 0.7VCC VCC + 0.3 V

VOL Output Low Vo ltage IOL = 3.0mA 0.4 V

Output Low Voltage (Open Drain)(2) IOL = 10mA 0.4 V

Pull-up Supply Voltage (Open Drain) IRQ/OUT/FT/SQW 5.5 V

VBAT(3) Back-up Supply Voltage 2.0 3.5(4) V

IBAT Battery Supply Current TA = 25°C, VCC = 0V

Oscillator ON, VBAT = 3V 0.6 1 µA

Sym Parameter(1,2) Min Typ Max Units

fOResonant Frequency 32.768 kHz

RSSeries Resistance 60(3) kΩ

CLLoad Capacitance 12.5 pF

M41T81S

22/29

Figure 17. Power Down /U p Mode AC Waveform s

Table 11. Power Down/U p AC Characteri stics

Note: 1. VCC fall tim e should no t e xc eed 5mV/µs.

2. Va l i d fo r Ambien t Operat in g T em perature: TA = –40 t o 85°C; VCC = 2.7 to 5.5V (e x cept wh ere noted).

Table 12. Power Down/U p Trip Points DC Characteristic s

Note: 1. All voltages referenced to VSS.

2. Va l i d fo r Ambien t Operat in g T em perature: TA = –40 t o 85°C; VCC = 2.7 to 5.5V (e x cept wh ere noted).

Symbol Parameter(1,2) Min Typ Max Unit

tPD SCL and SDA at VIH before Power Down 0nS

trec SCL and SDA at VIH after Power Up 10 µS

Sym Parameter(1,2) Min Typ Max Unit

VPFD Po wer-fail Deselect 2.5 2.6 2.7 V

Hysteresis 25 mV

VSO

Battery Back-up Switchover Voltage

(VCC < VBAT; VCC < VPFD)VBAT < VPFD VBAT V

VBAT > VPFD VPFD V

Hysteresis 40 mV

AI00596

VCC

trec

tPD

VSO

SDA

SCL DON'T CARE

23/29

M41T81S

Figure 18. Bus Timing Requirements Sequence

Table 13. AC Characteristics

Note: 1. Val i d for Ambient Operating T em perature: TA = –40 t o 85°C; VCC = 2.7 to 5.5V (e x cept wh ere noted).

2. Transmitter mu st in te rnally provide a h ol d t i m e to brid ge the undef i ned regi on (300ns m ax) of the falling edge of SCL.

Sym Parameter(1) Min Typ Max Units

fSCL SCL Clock Frequency 0 400 kHz

tLOW Clock Low Period 1.3 µs

tHIGH Clock High Period 600 ns

tRSDA and SCL Rise Time 300 ns

tFSDA and SCL Fall Time 300 ns

tHD:STA START Condition Hold Time

(after this period the first clock pulse is generated) 600 ns

tSU:STA START Condition Setup Time

(only relevant for a repeated start condition) 600 ns

tSU:DAT(2) Data Setup Time 100 ns

tHD:DAT Data Hold Time 0 µs

tSU:STO STOP Condition Setup Time 600 ns

tBUF Time the bus must be free before a new

transmission can start 1.3 µs

AI00589

SDA

PtSU:STOtSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STAtBUF

M41T81S

24/29

P ACKAGE ME CHANICA L INFORMAT ION

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These

packages have a Lead-free second level interconnect. The category of second Level Interconnect is

marked on the package and on the inner box label, in compliance with JEDEC Stand ard JES D97.

The maximum rat ings related t o sol dering conditions are al so marked on t he inne r box labe l. ECO PACK

is an ST trademark. ECOP ACK specificat ions are available at: www.st.com.

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M41T81S

Figure 19. SO8 – 8-lead Plastic Small Packag e Outline

No te : Drawing is not to scal e.

Table 14. SO8 – 8-lead Plastic Small Outline (150 mils body wi dth), Package M ech. D ata

Symb mm inches

Typ Min Max Typ Min Max

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

A2 1.10 1.65 0.043 0.065

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e1.27– –0.050– –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α0° 8° 0° 8°

N8 8

ddd 0.10 0.004

SO-A

ddd

LA1 α

h x 45˚

M41T81S

26/29

Figure 20. SOX18 – 18-lead Plastic Small Outline, 300mils , Embedded Crystal, Outline

No te : Drawing is not to scal e.

Table 15. SOX18 – 18-lead Plastic Small Outline, 300mils, Emb edd ed Crystal, Packag e Me ch.

Symbol millimeters inches

Typ Min Max Typ Min Max

A 2.44 2.69 0.096 0.106

A1 0.15 0.31 0.006 0.012

A2 2.29 2.39 0.090 0.094

B 0.41 0.51 0.016 0.020

C 0.20 0.31 0.008 0.012

D 11.61 11.56 11.66 0.457 0.455 0.459

ddd 0.10 0.004

E 7.57 7.67 0.298 0.302

e1.27– –0.050– –

H 10.16 10.52 0.400 0.414

L 0.51 0.81 0.020 0.032

α0° 8° 0° 8°

N 18 18

10 18

SO-J

A1 LA1 α

h x 45°

AA2

ddd

27/29

M41T81S

PART NUMBERING

Table 16. Ordering Information Scheme

Note: 1. The SOX18 package includes an embedded 32,768Hz crystal. Contact local ST sales office fo r availability.

For other options, or for more information on any aspec t of t his device, please contact the ST Sales Office

nearest you.

Example: M41T 81S M 6 E

Device Type

M41T

Supply Voltage and Write Protect Voltage

81S = VCC = 2.7 to 5.5V

Package

M = SO8

MY(1) = SOX18

Temperature Range

6 = –40°C to 85°C

Shipping Method

For SO8:

E = ECOPACK Package, Tubes

F = ECOPACK Package, Tape & Reel

For SOX18:

blank = ECOPACK Package, Tubes

T = ECOPACK Package, Tape & Reel

M41T81S

28/29

REVISION HISTORY

Table 17. Document Revi sion History

M41T81S, 41T81S, T81S, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Seri al, Serial, Serial, Serial, Serial, Serial, Serial, Serial,

Serial, Serial, Seri al, Serial, Serial, Serial, Serial, Serial, Seria l, Ser ial, S erial, Seria l, Seria l, Ser ial , Serial, Seria l, Serial, Serial, Serial, Serial, Serial, Serial , Serial, Serial,

Serial, Access, Access, Access, Access, Access, Access, Access, Access, A ccess, Access, Access, Access, Access, Access, Access, A ccess, Access, Access, Access,

Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Ac-

cess, Access, A ccess, Access, Access, Access, Access, Access, Access, Access, A ccess, Access, Access, Access, Access, Access, Acce ss, Access, Access, A ccess,

Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, A ccess, Access, Interface, Interface,

Inter face , Int erface , In ter fa ce, In te rface, Inte rf ace, Inter face , Int er face , In terfa ce, In ter fa ce, In te rface, Inte rf ace, Inter face , Int er face , In terfa ce, In ter fa ce, In te rface, Inte r-

face, In ter fa ce, Inte rface , In ter fa ce, I nte rf ace , In terfa ce, I nte rf ace, Int erface , In te rfa ce, Int erface , In ter fa ce, I nte r face , In terfa ce, I nte rf ace , Int erfa ce, In te rfa ce, Int erface ,

face, Interface, Interface, Interface, Interface, Interface, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,

Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,

Clock, Clock, Clock, Clock, Clock, Clock, Clo ck, Clock, Clock, Clock, Cl ock, Clock, Clock, Clock, Clock, Cl ock, Clock, Clock, Clock, Clo ck, Cl ock, Clo ck, RTC, RTC, RTC,

RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC,

RT C, RTC, RTC, RT C, RTC, RTC, P rogra mmab le, Pro gram mable , Prog ramma bl e, Prog ramma ble, Pro gramm able , Progr amma ble, Prog ramma ble, Programmable, Pro-

grammable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Progra mm a b l e , P r ogra m-

m abl e , Prog ra mm ab le, Pr og ra mma b le, Pr og ra mma bl e, Pro gr am ma ble , Pro gr am m abl e, Pro gr am mab le , Pro gra mm ab le , Pr ogr a mm ab le, Pr og ra mm able, Programmabl e,

Progra mmable, Prog rammable, Progra mmab le, Pr ogrammab le, Programm able, Progra mmable, Prog rammable, Progra mmable, Program mable, Prog ram mabl e, Pr o-

grammable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Progra mm a b l e , P r ogra m-

mable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable Alarm, Programmable Alarm, Programmable Alarm,

Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Alarm,

Alarm, Alarm, Ala rm, Alarm, Alarm, Alarm, Alarm, Alarm, A larm, Alarm, Alarm, Alarm, Alarm, A larm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,

Alarm, Al arm , Al a rm, A larm , A lar m, Alar m, Alar m , In terr upt , In terr up t, In terr up t, In te rrup t, I nte rrup t, I nte rru pt, Inte r rupt, Int er rupt, Int er rupt , In ter rupt , In ter rup t, In terr up t,

Interrupt, Interrupt, Interrup t, Interrupt, Inte rrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interru pt, Interrupt, Interrupt, Interrupt, Interrup t, Interr upt, In-

terrupt, Interrupt, Interrupt, Interr upt, Inter rupt, Interrupt, Inte rrupt, Inter rupt, Inte rrupt, Inter rupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interr upt, Inter-

rupt, Interrupt, Inter rupt, Interrupt, Interrupt, Interrup t, In te rrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interr upt, Interrupt, Interrup t, Interru pt, Interrupt, Interrupt,

Interrupt, Interrupt, Interrup t, Interrupt, Inte rrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interru pt, Interrupt, Interrupt, Interrupt, Interrup t, Interr upt, In-

terrupt, Interrupt, Interrupt, Interr upt, Inter rupt, Interrupt, Inte rrupt, Inter rupt, Inte rrupt, Inter rupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interr upt, Inter-

rupt, Interrupt, Inter rupt, Interrupt, Interrupt, Interrup t, In te rrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interr upt, Interrupt, Interrup t, Interru pt, Interrupt, Interrupt,

Interrupt, Interrupt, Interrup t, Interrupt, Inte rrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interru pt, Interrupt, Interrupt, Interrupt, Interrup t, Interr upt, In-

terrupt, Interrupt, Interrupt, Interr upt, Inter rupt, Interrupt, Inte rrupt, Inter rupt, Inte rrupt, Inter rupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interr upt, Inter-

rupt, Interrupt, Inter rupt, Interrupt, Interrupt, Interrup t, In te rrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interr upt, Interrupt, Interrup t, Interru pt, Interrupt, Interrupt,

Interr upt, Inter rupt, Interrupt, Interru pt, Interrupt, Interrupt, Inter rupt, Interrupt, Interrupt, Interrup t, Interrupt, Interrupt, Watchdog, Watchdog, Watchdog, W atch dog, Watch-

dog, Wat chd og, Wa tch do g, Wat chd og, Wa tch dog , Wat chd og, Watc hdog , Wat chd og, Watc hdog , Wat chdo g, Watc hdog , Wat chdo g, Watc hdog , Wa tc hdog, Watc hdog ,

Watchdog, Watchdo g, Watchdog, Watchd og, Watchdog, Watch dog, Wa tchdog, Wa tchdog, Wa tchdog, Watchdog, W atchdog, Watchdog, Watchdog, Watchdog, Watch-

dog, Wat chd og, Wa tch do g, Wat chd og, Wa tch dog , Wat chd og, Watc hdog , Wat chd og, Watc hdog , Wat chdo g, Watc hdog , Wat chdo g, Watc hdog , Wa tc hdog, Watc hdog ,

Watchd og , W atch do g, Bat tery , B att ery , B atte ry , Ba tte ry, Ba tte ry, Bat ter y, B att er y, Batter y, Ba tte ry, Ba tte ry, Bat ter y, B attery, B att er y, Ba tte ry, Batte ry, Bat ter y, Batter y,

Battery, Batter y, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,

Battery, Battery, Battery, Switchover, Switchover, Sw itchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switch over, Backup, Backup, Backup, B ack-

up, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backu p, Wr ite Pr ot ect, W rite

Protect, W ri te Protec t, Wri te Prot ect, W rite Protect, W r it e Pr otect, Wri te Protect, W ri te Protect, W r it e Pr otect, Wri te Protect, Write Protect, Write Protect, Write Protect,

Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Wr ite Pr otect, Write Protect, Write Protect, Write Protect, Write Protect, Write Pro-

tect, Ind ustrial, Ind ustrial , Industria l, Industr ial, Industr ial, In dustrial, I ndustr ial, Industr ial, In dustrial, I ndustr ial, Industr ial, vIn dustria l, In dustr ial , Industrial , SOIC, SOIC ,

SOIC, SOIC, SOIC , SOIC , SOIC, SOIC , SOIC, SOIC , SOIC, SOIC , SOIC , SOIC, SOIC

Date Version Revision Details

January 22, 2004 0.1 First Draft

06-Feb-04 0.2 Update BL information, characteristics, ratings, and Lead (Pb)-free information (Table

12, 6, 10, 16)

20-Feb-04 0.3 Update characteristics (Table 11, 12, 7, 16)

14-Apr-04 1.0 Product promoted; reformatted; update characteristics, including Lead-free package

information (Figure 4, 5, 12, 15; 4, 13, 16)

05-May-04 1.1 Update DC Characteristics (Table 9)

16-Jun-04 1.2 Add shipping package (Table 16)

13-Sep-04 2.0 Update Maximum ratings (Table 6)

26-Nov-04 3.0 Promote document; update characteristics and marketing status (Figure 1, 5; Table

16)

23-Sep-05 4.0 Update features; added Lead-free information (page 1; Figure 4; Table 1, 16)

29/29

M41T81S

Information fur nished is believed to b e accurate and relia ble. However, STMicroelectronics a ssumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMi croelectronics product s are not

authorized for us e as critical com ponents in lif e support devices or sys te m s without express written approval of STMi croelect ronics.

The ST l ogo is a registered tra dem ark of STMi croelectron ics.

All other names are th e prope rt y of their respectiv e owners

STM i croelectron ics group of companies

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Malaysia - Malta - Mo rocco - Singapore - Spain - Sweden - Swit zerlan d - United K i ngdom - United S tates of A m erica