OCTOBER 2001
DSC-5333/03
1
2002 Integrated Device Technology, Inc.
All rights reserved. Product specifications subject to change without notice.
Features
Full Ternary 64K x 72 bit content addressable memory
Upgradeable to 128K x 72 IPC
Power Management
Global Mask Registers
Segments individually configurable
36/72/144/288/576 multiple width lookups
100M sustained lookups per second at 72 and 144 width lookups
Burst write for high speed table updates
Multi-match
Learn new entries
Dual bus interface
Cascadable to 8 devices with no glue logic or latency penalty
Glueless interface to standard ZBT™ or
Synchronous Pipelined Burst SRAMs
Boundary Scan JTAG Interface (IEEE 1149.1compliant)
1.8V core power supply
2.5V VBIAS power supply
User selectable 2.5V or 1.8V I/O supply
IP Co-Processor
64K x 72 Entries Datasheet
Brief
75P52100
Device Description
IDT’s 75P52100 IPC is a high performance pipelined low-power,
synchronous full-ternary 64K x 72 entry device. Each entry location in
the IPC has both a Data entry and an associated Mask entry. IDT’s IPC
devices integrate content addressable memory (CAM) technology with
high-performance logic. The device can perform Lookup and Learn IPC
operations plus Read, Write, Burst Write, and Dual Write maintenance
operations.
The IDT 75P52100 IPC device has a bi-directional bus that is a
multiplexed address and data bus that can support 100 million sustained
searches per second. This device provides array segments which can
be configured to enable multiple width lookups from 36 to 576 bits wide.
The IDT 75P52100 requires a 1.8-volt VDD supply, a user selectable 1.8
or 2.5-volt VDDQ supply, and a 2.5-volt VBIAS supply. This IPC device
provides the user with flexibility and control in determining the device
power. Only the array segments that will be used for a specific IPC
operation are powered up while the unused segments are not.
The IDT 75P52100 utilizes IDT’s latest high-performance 1.8V
CMOS processing technology and is packaged in a JEDEC Standard,
thermally enhanced, low profile Ball Grid Array. The options include a
304 BGA, satisfying smaller footprint requirements and a 372 BGA
package that is compatible with IDT's 32K x 72 Entry (75P42100) and
128K x 72 Entry (75P62100) IPC devices.
Configuration Registers
and
Ram Control Circuits
CLOCK
CCLK
÷2
PHASE
SRAM CONTROL
P
R
I
O
R
I
T
Y
E
N
C
O
D
E
R
S
I
Z
E
L
O
G
I
C
D
E
C
O
D
E
Address
MMOUT
MATCHOUT
REQSTB R/W
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RESET
Command
Bus
Request
Data
Bus
Index
Bus
Counter
BURST
IPC
REQUEST
BUS
IPC
RESPONS
E
BUS
LAST IPC
LAST SRAM
ASIC FEEDBACK
Bypass
DATA
ARRAY
Comparand Registers
Instruction
Global Mask Registers
Result Register
Block Diagram
Figure 1.0 ASIC / Compatible IPC / SRAM configuration
System Configurations
IDT’s IPCs are designed to fulfill the needs of various types of
networking systems. In solutions requiring data searching such as
routers, a system configuration as shown in Figure 1.0 may be realized.
Maximum flexibility is provided by allowing one board design to be
populated today using either IDT’s 75P42100 or 75P52100 IPCs and
later upgraded to use IDT’s 75K62100 IPC. Applications note AN-279
discusses how to accommodate one board design for any of these IPCs.
In this compatible configuration, the IPC interfaces directly to an
ASIC/ FPGA for lookups and routes an Index to an associated SRAM
device, which supplies the next hop address via an SRAM Data Bus to
the ASIC. The IPC provides the required control signals to directly
hookup to ZBT™ or Synchronous Pipeline Burst SRAM. Lookup results
can also be fed directly back to the ASIC/ FPGA without the use of external
SRAM. Control of the associated handshake signals is provided by all
IPCs to adapt to either configuration.
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Optional
Network Interface
ASIC
or
FPGA
ZBT
or
Sync SRAM
To request the full IDT75P52100 datasheet, please contact your local
IDT Sales Representative or call 1-831-754-4555
IDT
75P42100
or
75P52100
or
75K62100
IP Co-Processor
2
IP Co-Processor 64K x 72 Entries Datasheet Brief 75P52100
SRAM Interface
The IPC provides all required address and control signals for a
glueless SRAM interface. The IPC provides a pipelined bypass path for
reads or writes to the external SRAM. The ASIC/FPGA handles the
pipelining of the data to and from the SRAM.
Registers
There are four basic types of registers supported:
Configuration Registers are used at initialization to define the
segmentation of the entries, timing of outputs and the SRAM interface.
Global Mask Registers are provided to support Lookup
instructions by masking individual bits during a search.
Comparand Registers assist in the Learn Instruction.
Result Registers are used to store the resulting index of a
search from a Lookup or Learn operation.
Synchronous Burst Write
The burst write feature has no limit on the number of continuous write
accesses and supports initialization of the IPC.
Width Segmentation Capability
The IPCs are capable of performing lookups for comparisons on data
structures of 72 bits, 144 bits, 288 bits and 576 bits. These devices has
can be configured to meet various system requirements.
Single Width Array
Multiple Width Arrays within a Single Device
Multi Match
The Multi-Match feature signals to the user that more than one match
has resulted. The result of the lookup, which defines the highest priority
match, is sent along with the Multi-Match signal.
Power Savings and Classification Features
See the full IDT75P52100 Datasheet for more information.
Functional Highlights
Figure 1.1
Bus Interface
The IPC utilizes a dual bus interface consisting of the IPC Request Bus
and the IPC Response Bus.
The IPC Request Bus is comprised of the Command Bus and the
Request Data Bus. The Command Bus handles the instruction to the IPC
while the Request Data Bus is the main data path to the IPC.
The 72 bit bi-directional Request Data Bus functions as a multiplexed
address and data bus, which performs the writing and reading of IPC
entries, as well as presenting lookup data to the device.
The IPC Response Bus is comprised of an independent unidirectional
Index Bus which drives the result of the lookup (or index) to either an
SRAM device or an ASIC. In addition to driving the Index, the IPC
Response Bus also drives the associated SRAM control signals (CE/OE,
and WE) for either ZBT™ or Synchronous Pipeline Burst SRAM devices.
Command Bus
The Command Bus loads the specific instructions into the IPC. These
include:
Read or Write
A Read or Write instruction operates on a specified data entry, mask
entry, or register.
SRAM No Wait Read
An SRAM No Wait Read is a Read instruction to an external SRAM
that can be pipelined within a series of operations and does not require
the user to wait for the Read to complete before loading the next instruction.
Dual Write
In addition to individual writes, the IPC has the ability to perform
simultaneous writes to a Data entry and a respective external SRAM
location.
Data and Mask Array
The IPC has Data cell entries and associated
Mask cell entries as shown in Fig. 1.1. This
combination of Data and Mask cell entries en-
ables the IPC to store 0, 1 or X, making it a full
ternary IP Co-Processor. During a lookup
operation, both arrays are used along with a
Global Mask Register to find a match to a re-
quested data word.
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Data
Mask
Lookup
A lookup can be requested in 72-bit, 144-bit, 288-bit or 576-bit widths.
A 36-bit lookup can be accomplished by using two Global Mask Registers.
Learn
The IPC implements a fully autonomous Learn Instruction, which
provides a mechanism for the user to write a lookup entry into an unused
location in the IPC and the associated data in external SRAM. This allows
the user to update an entry into the IPC which had not previously been stored.
The Learn writes the new entry, making it available for future lookups.
6.42
3
IP Co-Processor 64K x 72 Entries Datasheet Brief 75P52100
Signal Descriptions
Pin Function I/O Description
IPC Request Bus:
Re que st Strob e Input This inp ut sig nifie s a v alid inp ut re q ue st and signals the start o f an IP C o p eratio n cycle .
Command
Bus
Instruction Input These two fields of the Command bus define the instruction to be performed by the IPC and the lookup
type . The lo ok up ty pe is se le cte d only for op e ratio nal type comm and s (Lo o kup s, Le arns) and is a "d on't
care " fo r m ainte nance ty p e command s (all Read s and Write s).
Lookup Type Input
Global Mask
Register Select Input This field is within the Command bus. During Lookup or Write operations, this field defines which of the
Global Mask Register groups are b eing accessed. This field is a "don't care" for Read, SRAM No Wait
Re ad, and Le arn Op eratio ns.
Co mp arand and
Result Re gister
Select Input This is a multiplexed field within the Command Bus that specifies both the Result Register to store the
Inde x into , and the C o mp arand Re gister to use . This fie ld is samp le d e very inp u t c lo ck cycle . The first
cycle decodes the selected Comparand Register and the second decodes the selected Result Register.
Request Data Bus Input/Output
Three State The Re quest Data Bus is a multiplexe d add ress/data bus used to perform re ads (a nd writes) from (to) the
IPC, and to p re se nt se arch d ata for lo okups .
IPC Response Bus:
Ind e x Bus
Address Output
Thre e State
This b us is us ed to driv e the ad d re ss of an e xte rnal SRA M, o r fe e db ack Loo kup result informatio n
directly to the IPC's ASIC/FPGA. The Index Bus contain the encoded location at which the compare was
found, the address of the IPC which found the result and the Lookup type.
De v ic e ID
Lo ok up Ty pe
Chip Enab le / Output Enab le Output
Three State This signal is driven along with the Index Bus. It is connected to the CE i np u t p in o f a ZBT S RA M o r to the
OE p in o f a PB SRAM.
Write Enab le Output
Thre e State This signal is driven along with the Index bus. It is used to assert the WE
pin of an external SRAM. It is
active for b oth SRAM write op e ratio ns and the Le arn co mmand.
Read Acknowledge Output Thi s s ignal is se nt b ac k when the d ata is re ad from the IP C o n the Req u e s t Data B us , o r whe n th e d ata
b e ing re ad fro m the assoc iated external SRAM.
Match Acknowledge Output This is signal is sent with the Index. It will be driven low if there was no match, high if a match was found.
Valid
Lo ok up Bit Output This signal is sent with the Index. It will be driven high upon the completion of a lookup, even if the
lo o kup did no t re s ult in a hit.
Multi Match
Output Output
(Op e n Drain)
This signal is sent with the Index. It shall go active when a) multiple hits occur in one segment; or, b) one
o r more hits o ccur in two (o r mo re) se g me nts ; o r, c) o ne o r mo re hits o ccur in multip le d e vic es that are
depth cascaded.
Depth Expansion:
De vic e Ad dre ss Inp ut These three DC pins are used to define the Device Address for each of the eight possible depth
expanded IPC dev ices in an IPC system.
Match
Input Input The Match Inp ut s ig nal i s d riv en b y all up stream Match Output sig nals . This ind ic a te s to all d o wn s tre am
IPCs that a hit in a hig he r p rio rity IPC has occurre d.
Match
Output Output The M atch Outp ut s ig nal s ig nifie s that a matc h has oc curre d in the IPC. The sig nal is fe d into a Matc h
Input line o f all l ower p rio rity IPC(s).
Clock and I nitiali zation:
Clock Input Input All inputs and outputs are referenced to the positive edge of this clock.
Clo ck Phas e Enab le Input This sig nal is use d to ge ne rate an inte rnal clo ck at ½ the fre quenc y of the input clo ck.
Re se t Input This p in wil l force all outp uts to a high imp e de nce co nd itio n, as well as cle ar ing the IPC e nab le b it.
Advanc e Burst Ad dres s Input This sig nal will advanc e an inte rnal ad d ress c ounter to allo w for b urst write s when writing to the Data/Mas k
me mory in the IPC. This p rovides a m ec hanism to co nvenie ntly initialize the IPC memory.
Last IPC Input This pin defines which IPC device will drive the ASIC Feedback signals to the ASIC/FPGA.
Las t SRAM Input Thi s p in d e fine s which IPC d evice will d riv e the SRAM c o ntro l s ig nals CE/OE and WE. It als o d efaults
this device to driving the Index Bus when there is no ongoing operation preventing the bus from floating.
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