REJ09B0148-0200Z The revision list can be viewed directly by cliking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8S/2282Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series H8S/2282F H8S/2282 H8S/2281 Rev.2.00 Revision Date: Mar. 18, 2004 HD64F2282 HD6432282 HD6432281 Rev. 2.00, 03/04, page ii of xxx Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 2.00, 03/04, page iii of xxx General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 2.00, 03/04, page iv of xxx Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev. 2.00, 03/04, page v of xxx Preface This LSI is a single-chip microcomputer made up of the high-speed H8S/2000 CPU as its core, and the peripheral functions required to configure a system. This LSI is equipped with ROM, RAM, a 16-bit timer pulse unit, a watchdog timer, serial communication interfaces, a controller area network, an A/D converter, a motor control PWM timer, an LCD controller/driver (LCD), a clock pulse generator, and I/O ports as on-chip peripheral modules. This LSI is suitable for use as an embedded processor for high-level control systems. Its on-chip ROM is flash memory (F-ZTATTM*) that provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. This is particularly applicable to application devices with specifications that will most probably change. Note: * F-ZTATTM is a trademark of Renesas Technology Corp. Target Users: This manual was written for users who will be using the H8S/2282 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2282 Group to the target users. See the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of the instruction set. Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 20, List of Registers. Examples: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication interfaces, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Rev. 2.00, 03/04, page vi of xxx Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx Signal notation: An overbar is added to a low-active signal: xxxx Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. (http://www.renesas.com/eng/) H8S/2282 Group manuals: Document Title Document No. H8S/2282 Group Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083 User's manuals for development tools: Document Title Document No. H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual ADE-702-247 H8S, H8/300 Series Simulator/Debugger (for Windows) User's Manual ADE-702-085 H8S, H8/300 Series Embedded Workshop, Debugging Interface Tutorial ADE-702-231 High-Performance Embedded Workshop User's Manual ADE-702-201 Rev. 2.00, 03/04, page vii of xxx Rev. 2.00, 03/04, page viii of xxx Contents Section 1 Overview............................................................................................1 1.1 1.2 1.3 1.4 Overview........................................................................................................................... 1 Internal Block Diagram..................................................................................................... 2 Pin Arrangement ............................................................................................................... 3 Pin Functions .................................................................................................................... 4 Section 2 CPU....................................................................................................11 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Features............................................................................................................................. 11 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 12 2.1.2 Differences from H8/300 CPU ............................................................................ 13 2.1.3 Differences from H8/300H CPU.......................................................................... 13 CPU Operating Modes...................................................................................................... 14 2.2.1 Normal Mode....................................................................................................... 14 2.2.2 Advanced Mode................................................................................................... 16 Address Space................................................................................................................... 18 Register Configuration...................................................................................................... 19 2.4.1 General Registers................................................................................................. 20 2.4.2 Program Counter (PC) ......................................................................................... 21 2.4.3 Extended Control Register (EXR) ....................................................................... 21 2.4.4 Condition-Code Register (CCR).......................................................................... 22 2.4.5 Initial Values of CPU Registers ........................................................................... 23 Data Formats..................................................................................................................... 24 2.5.1 General Register Data Formats ............................................................................ 24 2.5.2 Memory Data Formats ......................................................................................... 26 Instruction Set ................................................................................................................... 27 2.6.1 Table of Instructions Classified by Function ....................................................... 28 2.6.2 Basic Instruction Formats .................................................................................... 37 Addressing Modes and Effective Address Calculation..................................................... 39 2.7.1 Register Direct--Rn ............................................................................................ 39 2.7.2 Register Indirect--@ERn .................................................................................... 39 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn).............. 39 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn ................................................................... 40 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32.................................... 40 2.7.6 Immediate--#xx:8, #xx:16, or #xx:32................................................................. 41 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC).................................... 41 2.7.8 Memory Indirect--@@aa:8 ................................................................................ 41 2.7.9 Effective Address Calculation ............................................................................. 42 Processing States............................................................................................................... 45 Rev. 2.00, 03/04, page ix of xxx 2.9 Usage Note........................................................................................................................ 46 2.9.1 Note on Bit Manipulation Instructions ................................................................ 46 Section 3 MCU Operating Modes ..................................................................... 47 3.1 3.2 3.3 3.4 Operating Mode Selection ................................................................................................ 47 Register Descriptions........................................................................................................ 47 3.2.1 Mode Control Register (MDCR) ......................................................................... 47 3.2.2 System Control Register (SYSCR)...................................................................... 48 Pin Functions in Each Operating Mode ............................................................................ 49 Address Map ..................................................................................................................... 50 Section 4 Exception Handling ........................................................................... 51 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Exception Handling Types and Priority............................................................................ 51 Exception Sources and Exception Vector Table ............................................................... 51 Reset ................................................................................................................................. 53 4.3.1 Reset Exception Handling ................................................................................... 53 4.3.2 Interrupts after Reset............................................................................................ 55 4.3.3 State of On-Chip Peripheral Modules after Reset Release .................................. 55 Traces................................................................................................................................ 56 Interrupts........................................................................................................................... 56 Trap Instruction................................................................................................................. 57 Stack Status after Exception Handling.............................................................................. 58 Usage Note........................................................................................................................ 59 Section 5 Interrupt Controller............................................................................ 61 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Features............................................................................................................................. 61 Input/Output Pins.............................................................................................................. 63 Register Descriptions........................................................................................................ 63 5.3.1 Interrupt Priority Registers A to G, J, K, M (IPRA to IPRG, IPRJ, IPRK, IPRM) ................................................................... 64 5.3.2 IRQ Enable Register (IER) .................................................................................. 65 5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 66 5.3.4 IRQ Status Register (ISR).................................................................................... 68 Interrupt Sources............................................................................................................... 69 5.4.1 External Interrupts ............................................................................................... 69 5.4.2 Internal Interrupts ................................................................................................ 70 Interrupt Exception Handling Vector Table...................................................................... 70 Interrupt Control Modes and Interrupt Operation ............................................................. 73 5.6.1 Interrupt Control Mode 0..................................................................................... 73 5.6.2 Interrupt Control Mode 2..................................................................................... 75 5.6.3 Interrupt Exception Handling Sequence .............................................................. 76 5.6.4 Interrupt Response Times .................................................................................... 78 Usage Notes ...................................................................................................................... 79 Rev. 2.00, 03/04, page x of xxx 5.7.1 5.7.2 5.7.3 5.7.4 5.7.5 Contention between Interrupt Generation and Disabling..................................... 79 Instructions that Disable Interrupts ...................................................................... 80 When Interrupts Are Disabled ............................................................................. 80 Interrupts during Execution of EEPMOV Instruction.......................................... 81 IRQ Interrupts ...................................................................................................... 81 Section 6 Bus Controller....................................................................................83 6.1 Basic Timing..................................................................................................................... 83 6.1.1 On-Chip Memory Access Timing (ROM, RAM) ................................................ 83 6.1.2 On-Chip Peripheral Module Access Timing........................................................ 84 6.1.3 On-Chip HCAN Module Access Timing............................................................. 85 6.1.4 On-Chip PWM, LCD, Ports H and J Module Access Timing ............................. 85 Section 7 I/O Ports .............................................................................................87 7.1 7.2 7.3 7.4 7.5 7.6 Port 1................................................................................................................................. 91 7.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 91 7.1.2 Port 1 Data Register (P1DR)................................................................................ 91 7.1.3 Port 1 Register (PORT1)...................................................................................... 92 7.1.4 Pin Functions ....................................................................................................... 92 Port 3................................................................................................................................. 101 7.2.1 Port 3 Data Direction Register (P3DDR)............................................................. 101 7.2.2 Port 3 Data Register (P3DR)................................................................................ 101 7.2.3 Port 3 Register (PORT3)...................................................................................... 102 7.2.4 Port 3 Open-Drain Control Register (P3ODR) .................................................... 102 7.2.5 Pin Functions ....................................................................................................... 103 Port 4................................................................................................................................. 105 7.3.1 Port 4 Register (PORT4)...................................................................................... 105 Port A................................................................................................................................ 106 7.4.1 Port A Data Direction Register (PADDR) ........................................................... 106 7.4.2 Port A Data Register (PADR).............................................................................. 106 7.4.3 Port A Register (PORTA).................................................................................... 107 7.4.4 Port A Open Drain Control Register (PAODR)................................................... 107 7.4.5 Pin Functions ....................................................................................................... 108 Port B ................................................................................................................................ 109 7.5.1 Port B Data Direction Register (PBDDR) ........................................................... 109 7.5.2 Port B Data Register (PBDR) .............................................................................. 109 7.5.3 Port B Register (PORTB) .................................................................................... 110 7.5.4 Port B Open Drain Control Register (PBODR) ................................................... 110 7.5.5 Pin Functions ....................................................................................................... 111 Port C ................................................................................................................................ 112 7.6.1 Port C Data Direction Register (PCDDR) ........................................................... 112 7.6.2 Port C Data Register (PCDR) .............................................................................. 112 7.6.3 Port C Register (PORTC) .................................................................................... 113 Rev. 2.00, 03/04, page xi of xxx 7.6.4 Port C Open Drain Control Register (PCODR) ................................................... 113 7.6.5 Pin Functions ....................................................................................................... 114 7.7 Port D................................................................................................................................ 115 7.7.1 Port D Data Direction Register (PDDDR)........................................................... 115 7.7.2 Port D Data Register (PDDR).............................................................................. 115 7.7.3 Port D Register (PORTD).................................................................................... 116 7.7.4 Pin Functions ....................................................................................................... 116 7.8 Port F ................................................................................................................................ 117 7.8.1 Port F Data Direction Register (PFDDR) ............................................................ 117 7.8.2 Port F Data Register (PFDR) ............................................................................... 118 7.8.3 Port F Register (PORTF) ..................................................................................... 118 7.8.4 Pin Functions ....................................................................................................... 119 7.9 Port H................................................................................................................................ 121 7.9.1 Port H Data Direction Register (PHDDR)........................................................... 121 7.9.2 Port H Data Register (PHDR).............................................................................. 121 7.9.3 Port H Register (PORTH).................................................................................... 122 7.9.4 Pin Functions ....................................................................................................... 122 7.10 Port J ................................................................................................................................. 125 7.10.1 Port J Data Direction Register (PJDDR).............................................................. 125 7.10.2 Port J Data Register (PJDR) ................................................................................ 125 7.10.3 Port J Register (PORTJ) ...................................................................................... 126 7.10.4 Pin Functions ....................................................................................................... 126 7.11 Pin Switch Function.......................................................................................................... 129 7.11.1 Transport Register (TRPRT) ............................................................................... 129 7.11.2 Reading of Port Registers by Switching the Pin .................................................. 129 Section 8 16-Bit Timer Pulse Unit (TPU) ......................................................... 131 8.1 8.2 8.3 8.4 Features............................................................................................................................. 131 Input/Output Pins.............................................................................................................. 135 Register Descriptions........................................................................................................ 136 8.3.1 Timer Control Register (TCR)............................................................................. 137 8.3.2 Timer Mode Register (TMDR)............................................................................ 140 8.3.3 Timer I/O Control Register (TIOR)..................................................................... 142 8.3.4 Timer Interrupt Enable Register (TIER).............................................................. 151 8.3.5 Timer Status Register (TSR)................................................................................ 153 8.3.6 Timer Counter (TCNT)........................................................................................ 155 8.3.7 Timer General Register (TGR) ............................................................................ 155 8.3.8 Timer Start Register (TSTR) ............................................................................... 156 8.3.9 Timer Synchro Register (TSYR) ......................................................................... 157 Operation .......................................................................................................................... 158 8.4.1 Basic Functions.................................................................................................... 158 8.4.2 Synchronous Operation........................................................................................ 164 8.4.3 Buffer Operation.................................................................................................. 166 Rev. 2.00, 03/04, page xii of xxx 8.5 8.6 8.7 8.8 8.4.4 PWM Modes ........................................................................................................ 169 8.4.5 Phase Counting Mode.......................................................................................... 174 Interrupts........................................................................................................................... 181 A/D Converter Activation................................................................................................. 182 Operation Timing.............................................................................................................. 183 8.7.1 Input/Output Timing ............................................................................................ 183 8.7.2 Interrupt Signal Timing........................................................................................ 187 Usage Notes ...................................................................................................................... 190 8.8.1 Module Stop Mode Setting .................................................................................. 190 8.8.2 Input Clock Restrictions ...................................................................................... 190 8.8.3 Caution on Period Setting .................................................................................... 191 8.8.4 Contention between TCNT Write and Clear Operations..................................... 191 8.8.5 Contention between TCNT Write and Increment Operations.............................. 192 8.8.6 Contention between TGR Write and Compare Match ......................................... 193 8.8.7 Contention between Buffer Register Write and Compare Match ........................ 194 8.8.8 Contention between TGR Read and Input Capture.............................................. 195 8.8.9 Contention between TGR Write and Input Capture............................................. 196 8.8.10 Contention between Buffer Register Write and Input Capture ............................ 197 8.8.11 Contention between Overflow/Underflow and Counter Clearing........................ 198 8.8.12 Contention between TCNT Write and Overflow/Underflow............................... 199 8.8.13 Multiplexing of I/O Pins ...................................................................................... 199 8.8.14 Interrupts in Module Stop Mode.......................................................................... 199 8.8.15 Interrupts in Subactive Mode/Watch Mode ......................................................... 199 Section 9 Watchdog Timer ................................................................................201 9.1 9.2 9.3 9.4 9.5 Features............................................................................................................................. 201 Register Descriptions ........................................................................................................ 203 9.2.1 Timer Counter 0 and 1 (TCNT_0 and TCNT_1) ................................................. 203 9.2.2 Timer Control/Status Register 0 and 1 (TCSR_0 and TCSR_1).......................... 203 9.2.3 Reset Control/Status Register (RSTCSR)............................................................ 207 Operation .......................................................................................................................... 208 9.3.1 Watchdog Timer Mode ........................................................................................ 208 9.3.2 Interval Timer Mode............................................................................................ 210 Interrupts........................................................................................................................... 211 Usage Notes ...................................................................................................................... 211 9.5.1 Notes on Register Access..................................................................................... 211 9.5.2 Contention between Timer Counter (TCNT) Write and Increment ..................... 212 9.5.3 Changing Value of CKS2 to CKS0...................................................................... 213 9.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 213 9.5.5 Internal Reset in Watchdog Timer Mode............................................................. 213 9.5.6 OVF Flag Clearing in Interval Timer Mode ........................................................ 213 Rev. 2.00, 03/04, page xiii of xxx Section 10 Serial Communication Interface (SCI)............................................ 215 10.1 Features............................................................................................................................. 215 10.2 Input/Output Pins.............................................................................................................. 217 10.3 Register Descriptions........................................................................................................ 217 10.3.1 Receive Shift Register (RSR) .............................................................................. 218 10.3.2 Receive Data Register (RDR).............................................................................. 218 10.3.3 Transmit Data Register (TDR)............................................................................. 218 10.3.4 Transmit Shift Register (TSR) ............................................................................. 218 10.3.5 Serial Mode Register (SMR) ............................................................................... 219 10.3.6 Serial Control Register (SCR) ............................................................................. 222 10.3.7 Serial Status Register (SSR) ................................................................................ 225 10.3.8 Smart Card Mode Register (SCMR).................................................................... 229 10.3.9 Bit Rate Register (BRR) ...................................................................................... 230 10.4 Operation in Asynchronous Mode .................................................................................... 237 10.4.1 Data Transfer Format........................................................................................... 237 10.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode............................................................................................ 239 10.4.3 Clock.................................................................................................................... 240 10.4.4 SCI Initialization (Asynchronous Mode)............................................................. 241 10.4.5 Data Transmission (Asynchronous Mode) .......................................................... 242 10.4.6 Serial Data Reception (Asynchronous Mode) ..................................................... 244 10.5 Multiprocessor Communication Function......................................................................... 248 10.5.1 Multiprocessor Serial Data Transmission ............................................................ 250 10.5.2 Multiprocessor Serial Data Reception ................................................................. 251 10.6 Operation in Clocked Synchronous Mode ........................................................................ 254 10.6.1 Clock.................................................................................................................... 254 10.6.2 SCI Initialization (Clocked Synchronous Mode)................................................. 255 10.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 256 10.6.4 Serial Data Reception (Clocked Synchronous Mode) ......................................... 258 10.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) ............................................................................. 260 10.7 Operation in Smart Card Interface .................................................................................... 262 10.7.1 Pin Connection Example ..................................................................................... 262 10.7.2 Data Format (Except for Block Transfer Mode).................................................. 263 10.7.3 Block Transfer Mode ........................................................................................... 264 10.7.4 Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode.................................................................................. 265 10.7.5 Initialization......................................................................................................... 266 10.7.6 Data Transmission (Except for Block Transfer Mode)........................................ 266 10.7.7 Serial Data Reception (Except for Block Transfer Mode)................................... 270 10.7.8 Clock Output Control........................................................................................... 271 10.8 Interrupts........................................................................................................................... 273 Rev. 2.00, 03/04, page xiv of xxx 10.8.1 Interrupts in Normal Serial Communication Interface Mode .............................. 273 10.8.2 Interrupts in Smart Card Interface Mode ............................................................. 274 10.9 Usage Notes ...................................................................................................................... 274 10.9.1 Module Stop Mode Setting .................................................................................. 274 10.9.2 Break Detection and Processing .......................................................................... 274 10.9.3 Mark State and Break Detection .......................................................................... 275 10.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)..................................................................... 275 Section 11 Controller Area Network (HCAN) ..................................................277 11.1 Features............................................................................................................................. 277 11.2 Input/Output Pins .............................................................................................................. 279 11.3 Register Descriptions ........................................................................................................ 279 11.3.1 Master Control Register (MCR) .......................................................................... 280 11.3.2 General Status Register (GSR) ............................................................................ 281 11.3.3 Bit Configuration Register (BCR) ....................................................................... 282 11.3.4 Mailbox Configuration Register (MBCR) ........................................................... 284 11.3.5 Transmit Wait Register (TXPR) .......................................................................... 285 11.3.6 Transmit Wait Cancel Register (TXCR).............................................................. 286 11.3.7 Transmit Acknowledge Register (TXACK) ........................................................ 287 11.3.8 Abort Acknowledge Register (ABACK) ............................................................. 288 11.3.9 Receive Complete Register (RXPR).................................................................... 289 11.3.10 Remote Request Register (RFPR)........................................................................ 290 11.3.11 Interrupt Register (IRR)....................................................................................... 291 11.3.12 Mailbox Interrupt Mask Register (MBIMR)........................................................ 294 11.3.13 Interrupt Mask Register (IMR) ............................................................................ 295 11.3.14 Receive Error Counter (REC).............................................................................. 296 11.3.15 Transmit Error Counter (TEC)............................................................................. 296 11.3.16 Unread Message Status Register (UMSR)........................................................... 297 11.3.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 298 11.3.18 Message Control (MC0 to MC15) ....................................................................... 300 11.3.19 Message Data (MD0 to MD15) ........................................................................... 302 11.4 Operation .......................................................................................................................... 303 11.4.1 Hardware and Software Resets ............................................................................ 303 11.4.2 Initialization after Hardware Reset ...................................................................... 303 11.4.3 Message Transmission ......................................................................................... 309 11.4.4 Message Reception .............................................................................................. 312 11.4.5 HCAN Sleep Mode.............................................................................................. 315 11.4.6 HCAN Halt Mode................................................................................................ 318 11.5 Interrupts........................................................................................................................... 319 11.6 CAN Bus Interface............................................................................................................ 320 11.7 Usage Notes ...................................................................................................................... 320 11.7.1 Module Stop Mode Setting .................................................................................. 320 Rev. 2.00, 03/04, page xv of xxx 11.7.2 Reset .................................................................................................................... 320 11.7.3 HCAN Sleep Mode.............................................................................................. 321 11.7.4 Interrupts.............................................................................................................. 321 11.7.5 Error Counters ..................................................................................................... 321 11.7.6 Register Access.................................................................................................... 321 11.7.7 HCAN Medium-Speed Mode .............................................................................. 321 11.7.8 Register Hold in Standby Modes ......................................................................... 321 11.7.9 Usage of Bit Manipulation Instructions ............................................................... 321 11.7.10 HCAN TXCR Operation ..................................................................................... 322 11.7.11 HCAN Transmit Procedure ................................................................................. 323 11.7.12 Note on Releasing the HCAN Software Reset and HCAN Sleep........................ 323 11.7.13 Note on Accessing Mailbox during the HCAN Sleep ......................................... 323 Section 12 A/D Converter ................................................................................. 325 12.1 Features............................................................................................................................. 325 12.2 Input/Output Pins.............................................................................................................. 327 12.3 Register Descriptions........................................................................................................ 328 12.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 328 12.3.2 A/D Control/Status Register (ADCSR) ............................................................... 329 12.3.3 A/D Control Register (ADCR) ............................................................................ 331 12.4 Operation .......................................................................................................................... 332 12.4.1 Single Mode......................................................................................................... 332 12.4.2 Scan Mode ........................................................................................................... 332 12.4.3 Input Sampling and A/D Conversion Time ......................................................... 333 12.4.4 External Trigger Input Timing............................................................................. 335 12.5 Interrupts........................................................................................................................... 335 12.6 A/D Conversion Precision Definitions ............................................................................. 336 12.7 Usage Notes ...................................................................................................................... 338 12.7.1 Module Stop Mode Setting .................................................................................. 338 12.7.2 Permissible Signal Source Impedance ................................................................. 338 12.7.3 Influences on Absolute Precision......................................................................... 338 12.7.4 Range of Analog Power Supply and Other Pin Settings...................................... 339 12.7.5 Notes on Board Design ........................................................................................ 339 12.7.6 Notes on Noise Countermeasures ........................................................................ 339 Section 13 Motor Control PWM Timer (PWM) ............................................... 341 13.1 Features............................................................................................................................. 341 13.2 Input/Output Pins.............................................................................................................. 344 13.3 Register Descriptions........................................................................................................ 344 13.3.1 PWM Control Register_1, 2 (PWCR_1, PWCR_2) ............................................ 345 13.3.3 PWM Polarity Register_1, 2 (PWPR_1, PWPR_2)............................................. 347 13.3.4 PWM Counter_1, 2 (PWCNT_1, PWCNT_2)..................................................... 347 13.3.5 PWM Cycle Register_1, 2 (PWCYR_1, PWCYR_2) ......................................... 348 Rev. 2.00, 03/04, page xvi of xxx 13.4 13.5 13.6 13.7 13.3.6 PWM Duty Register_1A, 1C, 1E, 1G (PWDTR_1A, PWDTR_1C, PWDTR_1E, PWDTR_1G)................................... 348 13.3.7 PWM Buffer Register_1A, 1C, 1E, 1G (PWBFR_1A, PWBFR_1C, PWBFR_1E, PWBFR_1G)..................................... 351 13.3.8 PWM Duty Register_2A to 2H (PWDTR_2A to PWDTR_2H).......................... 352 13.3.9 PWM Buffer Register_2A to 2D (PWBFR2_A to PWBFR_2D) ........................ 353 Bus Master Interface ......................................................................................................... 355 13.4.1 16-Bit Data Registers........................................................................................... 355 13.4.2 8-Bit Data Registers............................................................................................. 355 Operation .......................................................................................................................... 356 13.5.1 PWM Channel 1 Operation.................................................................................. 356 13.5.2 PWM Channel 2 Operation.................................................................................. 357 Interrupts........................................................................................................................... 358 Usage Note........................................................................................................................ 359 Section 14 LCD Controller/Driver (LCD).........................................................361 14.1 Features............................................................................................................................. 361 14.2 Input/Output Pins .............................................................................................................. 362 14.3 Register Descriptions ........................................................................................................ 363 14.3.1 LCD Port Control Register (LPCR)..................................................................... 363 14.3.2 LCD Control Register (LCR)............................................................................... 365 14.3.3 LCD Control Register 2 (LCR2).......................................................................... 366 14.4 Operation .......................................................................................................................... 367 14.4.1 Settings up to LCD Display ................................................................................. 367 14.4.2 Relationship between LCD RAM and Display.................................................... 368 14.4.3 Operation in Power-Down Modes ....................................................................... 372 14.4.4 Boosting the LCD Drive Power Supply............................................................... 373 Section 15 RAM ................................................................................................375 Section 16 Flash Memory (F-ZTAT Version) ...................................................377 16.1 16.2 16.3 16.4 16.5 Features............................................................................................................................. 377 Mode Transitions .............................................................................................................. 378 Block Configuration.......................................................................................................... 382 Input/Output Pins .............................................................................................................. 383 Register Descriptions ........................................................................................................ 383 16.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 384 16.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 385 16.5.3 Erase Block Register 1 (EBR1) ........................................................................... 385 16.5.4 RAM Emulation Register (RAMER)................................................................... 386 16.5.5 Flash Memory Power Control Register (FLPWCR) ............................................ 387 16.6 On-Board Programming Modes........................................................................................ 387 16.6.1 Boot Mode ........................................................................................................... 388 Rev. 2.00, 03/04, page xvii of xxx 16.6.2 Programming/Erasing in User Program Mode..................................................... 390 16.7 Flash Memory Emulation in RAM ................................................................................... 391 16.8 Flash Memory Programming/Erasing............................................................................... 393 16.8.1 Program/Program-Verify ..................................................................................... 393 16.8.2 Erase/Erase-Verify............................................................................................... 395 16.8.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 395 16.9 Program/Erase Protection ................................................................................................. 397 16.9.1 Hardware Protection ............................................................................................ 397 16.9.2 Software Protection ............................................................................................. 397 16.9.3 Error Protection ................................................................................................... 398 16.10 Programmer Mode ............................................................................................................ 398 16.11 Power-Down States for Flash Memory............................................................................. 399 16.12 Flash Memory and Power-Down Modes .......................................................................... 399 Section 17 Mask ROM ...................................................................................... 401 17.1 Note on Switching from F-ZTAT Version to Masked ROM Version .............................. 402 Section 18 Clock Pulse Generator..................................................................... 403 18.1 Register Descriptions........................................................................................................ 404 18.1.1 System Clock Control Register (SCKCR) ........................................................... 404 18.1.2 Low-Power Control Register (LPWRCR) ........................................................... 406 18.2 Oscillator........................................................................................................................... 407 18.2.1 Connecting a Crystal Resonator........................................................................... 407 18.2.2 External Clock Input............................................................................................ 408 18.3 PLL Circuit ....................................................................................................................... 409 18.4 Subclock Divider .............................................................................................................. 409 18.5 Medium-Speed Clock Divider .......................................................................................... 409 18.6 Bus Master Clock Selection Circuit.................................................................................. 410 18.7 Usage Notes ...................................................................................................................... 410 18.7.1 Note on Crystal Resonator................................................................................... 410 18.7.2 Note on Board Design.......................................................................................... 410 Section 19 Power-Down Modes........................................................................ 413 19.1 Register Descriptions........................................................................................................ 417 19.1.1 Standby Control Register (SBYCR) .................................................................... 417 19.1.2 Low-Power Control Register (LPWRCR) ........................................................... 419 19.1.3 Module Stop Control Registers A to D (MSTPCRA to MSTPCRD) .................. 421 19.2 Medium-Speed Mode ....................................................................................................... 423 19.3 Sleep Mode ....................................................................................................................... 424 19.3.1 Transition to Sleep Mode..................................................................................... 424 19.3.2 Clearing Sleep Mode ........................................................................................... 424 19.4 Software Standby Mode.................................................................................................... 425 19.4.1 Transition to Software Standby Mode ................................................................. 425 Rev. 2.00, 03/04, page xviii of xxx 19.5 19.6 19.7 19.8 19.9 19.10 19.11 19.12 19.4.2 Clearing Software Standby Mode ........................................................................ 425 19.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode....................................................................................... 426 19.4.4 Software Standby Mode Application Example.................................................... 427 Hardware Standby Mode .................................................................................................. 428 19.5.1 Transition to Hardware Standby Mode ................................................................ 428 19.5.2 Clearing Hardware Standby Mode....................................................................... 428 19.5.3 Hardware Standby Mode Timings ....................................................................... 429 Module Stop Mode ........................................................................................................... 430 Watch Mode...................................................................................................................... 431 19.7.1 Transition to Watch Mode ................................................................................... 431 19.7.2 Canceling Watch Mode........................................................................................ 431 Subsleep Mode.................................................................................................................. 432 19.8.1 Transition to Subsleep Mode ............................................................................... 432 19.8.2 Canceling Subsleep Mode.................................................................................... 432 Subactive Mode ................................................................................................................ 433 19.9.1 Transition to Subactive Mode.............................................................................. 433 19.9.2 Canceling Subactive Mode .................................................................................. 433 Direct Transitions.............................................................................................................. 434 19.10.1 Direct Transitions from High-Speed Mode to Subactive Mode........................... 434 19.10.2 Direct Transitions from Subactive Mode to High-Speed Mode........................... 434 Clock Output Disabling Function .................................................................................. 434 Usage Notes ...................................................................................................................... 435 19.12.1 I/O Port Status...................................................................................................... 435 19.12.2 Current Dissipation during Oscillation Stabilization Wait Period ....................... 435 19.12.3 On-Chip Peripheral Module Interrupt.................................................................. 435 19.12.4 Writing to MSTPCR ............................................................................................ 435 Section 20 List of Registers ...............................................................................437 20.1 Register Addresses (Address Order)................................................................................. 438 20.2 Register Bits...................................................................................................................... 452 20.3 Register States in Each Operating Mode .......................................................................... 467 Section 21 Electrical Characteristics .................................................................481 21.1 Absolute Maximum Ratings ............................................................................................. 481 21.2 DC Characteristics ............................................................................................................ 482 21.3 AC Characteristics ............................................................................................................ 485 21.3.1 Clock Timing ....................................................................................................... 485 21.3.2 Control Signal Timing ......................................................................................... 487 21.3.3 Timing of On-Chip Supporting Modules............................................................. 489 21.4 A/D Conversion Characteristics........................................................................................ 493 21.5 Flash Memory Characteristics .......................................................................................... 494 21.6 LCD Characteristics.......................................................................................................... 496 Rev. 2.00, 03/04, page xix of xxx Appendix A. B. C. ......................................................................................................... 497 I/O Port States in Each Pin State....................................................................................... 497 Product Lineup.................................................................................................................. 498 Package Dimensions ......................................................................................................... 498 Main Revisions and Additions in this Edition..................................................... 499 Index ......................................................................................................... 505 Rev. 2.00, 03/04, page xx of xxx Figures Section 1 Overview Figure 1.1 Internal Block Diagram ................................................................................................. 2 Figure 1.2 Pin Arrangement............................................................................................................ 3 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 15 Figure 2.2 Stack Structure in Normal Mode ................................................................................. 15 Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 16 Figure 2.4 Stack Structure in Advanced Mode ............................................................................. 17 Figure 2.5 Memory Map............................................................................................................... 18 Figure 2.6 CPU Registers ............................................................................................................. 19 Figure 2.7 Usage of General Registers ......................................................................................... 20 Figure 2.8 Stack Status ................................................................................................................. 21 Figure 2.9 General Register Data Formats (1).............................................................................. 24 Figure 2.9 General Register Data Formats (2).............................................................................. 25 Figure 2.10 Memory Data Formats............................................................................................... 26 Figure 2.11 Instruction Formats (Examples) ................................................................................ 38 Figure 2.12 Branch Address Specification in Memory Indirect Mode ......................................... 42 Figure 2.13 State Transitions ........................................................................................................ 46 Section 3 MCU Operating Modes Figure 3.1 Address Map ............................................................................................................... 50 Section 4 Exception Handling Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)................................ 54 Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled: Cannot be Used in this LSI)............ 55 Figure 4.3 Stack Status after Exception Handling ........................................................................ 58 Figure 4.4 Operation when SP Value Is Odd................................................................................ 59 Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Interrupt Controller Block Diagram of Interrupt Controller........................................................................ 62 Block Diagram of Interrupts IRQ5 to IRQ0 ................................................................ 69 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0...... 74 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2..................... 76 Interrupt Exception Handling ...................................................................................... 77 Contention between Interrupt Generation and Disabling ............................................ 80 Section 6 Figure 6.1 Figure 6.2 Figure 6.3 Bus Controller On-Chip Memory Access Cycle.................................................................................. 83 On-Chip Peripheral Module Access Cycle.................................................................. 84 On-Chip HCAN Module Access Cycle (Wait States Inserted) ................................... 85 Rev. 2.00, 03/04, page xxi of xxx Figure 6.4 On-Chip PWM, LCD, Ports H and J Module Access Cycle ....................................... 85 Section 8 16-Bit Timer Pulse Unit (TPU) Figure 8.1 Block Diagram of TPU ............................................................................................. 134 Figure 8.2 Example of Counter Operation Setting Procedure .................................................... 158 Figure 8.3 Free-Running Counter Operation .............................................................................. 159 Figure 8.4 Periodic Counter Operation....................................................................................... 160 Figure 8.5 Example of Setting Procedure for Waveform Output by Compare Match................ 160 Figure 8.6 Example of 0 Output/1 Output Operation ................................................................. 161 Figure 8.7 Example of Toggle Output Operation ....................................................................... 161 Figure 8.8 Example of Input Capture Operation Setting Procedure ........................................... 162 Figure 8.9 Example of Input Capture Operation ........................................................................ 163 Figure 8.10 Example of Synchronous Operation Setting Procedure .......................................... 164 Figure 8.11 Example of Synchronous Operation........................................................................ 165 Figure 8.12 Compare Match Buffer Operation........................................................................... 166 Figure 8.13 Input Capture Buffer Operation............................................................................... 166 Figure 8.14 Example of Buffer Operation Setting Procedure..................................................... 167 Figure 8.15 Example of Buffer Operation (1) ............................................................................ 168 Figure 8.16 Example of Buffer Operation (2) ............................................................................ 168 Figure 8.17 Example of PWM Mode Setting Procedure ............................................................ 170 Figure 8.18 Example of PWM Mode Operation (1) ................................................................... 171 Figure 8.19 Example of PWM Mode Operation (2) ................................................................... 172 Figure 8.20 Example of PWM Mode Operation (3) ................................................................... 173 Figure 8.21 Example of Phase Counting Mode Setting Procedure............................................. 174 Figure 8.22 Example of Phase Counting Mode 1 Operation ...................................................... 175 Figure 8.23 Example of Phase Counting Mode 2 Operation ...................................................... 176 Figure 8.24 Example of Phase Counting Mode 3 Operation ...................................................... 177 Figure 8.25 Example of Phase Counting Mode 4 Operation ...................................................... 178 Figure 8.26 Phase Counting Mode Application Example........................................................... 180 Figure 8.27 Count Timing in Internal Clock Operation.............................................................. 183 Figure 8.28 Count Timing in External Clock Operation ............................................................ 183 Figure 8.29 Output Compare Output Timing ............................................................................. 184 Figure 8.30 Input Capture Input Signal Timing.......................................................................... 184 Figure 8.31 Counter Clear Timing (Compare Match) ................................................................ 185 Figure 8.32 Counter Clear Timing (Input Capture) .................................................................... 185 Figure 8.33 Buffer Operation Timing (Compare Match) ........................................................... 186 Figure 8.34 Buffer Operation Timing (Input Capture) ............................................................... 186 Figure 8.35 TGI Interrupt Timing (Compare Match) ................................................................. 187 Figure 8.36 TGI Interrupt Timing (Input Capture) ..................................................................... 187 Figure 8.37 TCIV Interrupt Setting Timing................................................................................ 188 Figure 8.38 TCIU Interrupt Setting Timing................................................................................ 188 Figure 8.39 Timing for Status Flag Clearing by CPU ................................................................ 189 Figure 8.40 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode .................. 190 Rev. 2.00, 03/04, page xxii of xxx Figure 8.41 Figure 8.42 Figure 8.43 Figure 8.44 Figure 8.45 Figure 8.46 Figure 8.47 Figure 8.48 Figure 8.49 Section 9 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Contention between TCNT Write and Clear Operations......................................... 191 Contention between TCNT Write and Increment Operations ................................. 192 Contention between TGR Write and Compare Match............................................. 193 Contention between Buffer Register Write and Compare Match............................ 194 Contention between TGR Read and Input Capture ................................................. 195 Contention between TGR Write and Input Capture ................................................ 196 Contention between Buffer Register Write and Input Capture................................ 197 Contention between Overflow and Counter Clearing.............................................. 198 Contention between TCNT Write and Overflow..................................................... 199 Watchdog Timer Block Diagram of WDT_0 ........................................................................................ 202 Block Diagram of WDT_1 ........................................................................................ 202 (a) WDT_0 Operation in Watchdog Timer Mode ..................................................... 209 (b) WDT_1 Operation in Watchdog Timer Mode ..................................................... 209 Operation in Interval Timer Mode............................................................................. 210 Writing to TCNT, TCSR, and RSTCSR (example for WDT0)................................. 212 Contention between TCNT Write and Increment...................................................... 212 Section 10 Serial Communication Interface (SCI) Figure 10.1 Block Diagram of SCI............................................................................................. 216 Figure 10.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) .................................................. 237 Figure 10.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 239 Figure 10.4 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) ............................................................................................. 240 Figure 10.5 Sample SCI Initialization Flowchart ....................................................................... 241 Figure 10.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 242 Figure 10.7 Sample Serial Transmission Flowchart ................................................................... 243 Figure 10.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 244 Figure 10.9 Sample Serial Reception Data Flowchart (1) .......................................................... 246 Figure 10.9 Sample Serial Reception Data Flowchart (2) .......................................................... 247 Figure 10.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) .......................................... 249 Figure 10.11 Sample Multiprocessor Serial Transmission Flowchart ........................................ 250 Figure 10.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 251 Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 252 Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 253 Figure 10.14 Data Format in Synchronous Communication (for LSB-First) ............................. 254 Figure 10.15 Sample SCI Initialization Flowchart ..................................................................... 255 Figure 10.16 Sample SCI Transmission Operation in Clocked Synchronous Mode .................. 256 Rev. 2.00, 03/04, page xxiii of xxx Figure 10.17 Figure 10.18 Figure 10.19 Figure 10.20 Figure 10.21 Figure 10.22 Figure 10.23 Figure 10.24 Figure 10.25 Figure 10.26 Figure 10.27 Figure 10.28 Figure 10.29 Figure 10.30 Figure 10.31 Figure 10.32 Sample Serial Transmission Flowchart ................................................................. 257 Example of SCI Operation in Reception ............................................................... 258 Sample Serial Reception Flowchart ...................................................................... 259 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ...... 261 Schematic Diagram of Smart Card Interface Pin Connections.............................. 262 Normal Smart Card Interface Data Format ........................................................... 263 Direct Convention (SDIR = SINV = O/E = 0) ...................................................... 263 Inverse Convention (SDIR = SINV = O/E = 1) .................................................... 264 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Transfer Rate) ..................................................... 265 Retransfer Operation in SCI Transmit Mode ........................................................ 267 TEND Flag Generation Timing in Transmission Operation ................................. 268 Example of Transmission Processing Flow........................................................... 269 Retransfer Operation in SCI Receive Mode .......................................................... 270 Example of Reception Processing Flow................................................................ 271 Timing for Fixing Clock Output Level ................................................................. 271 Clock Halt and Restart Procedure ......................................................................... 272 Section 11 Controller Area Network (HCAN) Figure 11.1 HCAN Block Diagram ............................................................................................ 278 Figure 11.2 Message Control Register Configuration ................................................................ 300 Figure 11.3 Standard Format ...................................................................................................... 300 Figure 11.4 Extended Format ..................................................................................................... 300 Figure 11.5 Message Data Configuration ................................................................................... 302 Figure 11.6 Hardware Reset Flowchart ...................................................................................... 304 Figure 11.7 Software Reset Flowchart ....................................................................................... 305 Figure 11.8 Detailed Description of One Bit .............................................................................. 306 Figure 11.9 Transmission Flowchart .......................................................................................... 309 Figure 11.10 Transmit Message Cancellation Flowchart ........................................................... 311 Figure 11.11 Reception Flowchart ............................................................................................. 312 Figure 11.12 Unread Message Overwrite Flowchart.................................................................. 315 Figure 11.13 HCAN Sleep Mode Flowchart .............................................................................. 316 Figure 11.14 HCAN Halt Mode Flowchart ................................................................................ 318 Figure 11.15 High-Speed Interface Using PCA82C250............................................................. 320 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Figure 12.8 A/D Converter Block Diagram of A/D Converter ........................................................................... 326 A/D Conversion Timing.......................................................................................... 333 External Trigger Input Timing ................................................................................ 335 A/D Conversion Precision Definitions.................................................................... 337 A/D Conversion Precision Definitions.................................................................... 337 Example of Analog Input Circuit ............................................................................ 338 Example of Analog Input Protection Circuit........................................................... 340 Analog Input Pin Equivalent Circuit ....................................................................... 340 Rev. 2.00, 03/04, page xxiv of xxx Section 13 Figure 13.1 Figure 13.2 Figure 13.3 Motor Control PWM Timer (PWM) Block Diagram of PWM Channel 1 ........................................................................ 342 Block Diagram of PWM Channel 2 ........................................................................ 343 Cycle Register Compare Match............................................................................... 348 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Figure 14.7 LCD Controller/Driver (LCD) Block Diagram of LCD Controller/Driver .............................................................. 362 LCD RAM Map (1/4 Duty)..................................................................................... 368 LCD RAM Map (1/3 Duty)..................................................................................... 369 LCD RAM Map (Static Mode)................................................................................ 369 Output Waveforms for Each Duty Cycle (A Waveform) ........................................ 370 Output Waveforms for Each Duty Cycle (B Waveform) ........................................ 371 Connection of External Split-Resistance ................................................................. 373 Section 16 Flash Memory (F-ZTAT Version) Figure 16.1 Block Diagram of Flash Memory............................................................................ 378 Figure 16.2 Flash Memory State Transitions.............................................................................. 379 Figure 16.3 Boot Mode............................................................................................................... 380 Figure 16.4 User Program Mode ................................................................................................ 381 Figure 16.5 Flash Memory Block Configuration........................................................................ 382 Figure 16.6 Programming/Erasing Flowchart Example in User Program Mode ........................ 390 Figure 16.7 Flowchart for Flash Memory Emulation in RAM ................................................... 391 Figure 16.8 Example of RAM Overlap Operation...................................................................... 392 Figure 16.9 Program/Program-Verify Flowchart........................................................................ 394 Figure 16.10 Erase/Erase-Verify Flowchart ............................................................................... 396 Section 17 Mask ROM Figure 17.1 Block Diagram of 128-Kbyte Masked ROM (HD6432282) ................................... 401 Figure 17.2 Block Diagram of 64-Kbyte Masked ROM (HD6432281) ..................................... 401 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 Figure 18.7 Clock Pulse Generator Block Diagram of Clock Pulse Generator ............................................................... 403 Connection of Crystal Resonator (Example)........................................................... 407 Crystal Resonator Equivalent Circuit ...................................................................... 407 External Clock Input (Examples) ............................................................................ 408 External Clock Input Timing................................................................................... 409 Note on Board Design of Oscillator Circuit ............................................................ 410 External Circuitry Recommended for PLL Circuit.................................................. 411 Section 19 Figure 19.1 Figure 19.2 Figure 19.3 Figure 19.4 Figure 19.5 Power-Down Modes Mode Transition Diagram ....................................................................................... 414 Medium-Speed Mode Transition and Clearance Timing ........................................ 423 Software Standby Mode Application Example ....................................................... 427 Timing of Transition to Hardware Standby Mode .................................................. 429 Timing of Recovery from Hardware Standby Mode ............................................... 429 Rev. 2.00, 03/04, page xxv of xxx Section 21 Electrical Characteristics Figure 21.1 Output Load Circuit ................................................................................................ 485 Figure 21.2 System Clock Timing.............................................................................................. 486 Figure 21.3 Oscillation Stabilization Timing.............................................................................. 486 Figure 21.4 Reset Input Timing.................................................................................................. 487 Figure 21.5 Interrupt Input Timing............................................................................................. 488 Figure 21.6 I/O Port Input/Output Timing.................................................................................. 490 Figure 21.7 TPU Input/Output Timing ....................................................................................... 491 Figure 21.8 TPU Clock Input Timing......................................................................................... 491 Figure 21.9 SCK Clock Input Timing ........................................................................................ 491 Figure 21.10 SCI Input/Output Timing (Clock Synchronous Mode) ......................................... 492 Figure 21.11 A/D Converter External Trigger Input Timing...................................................... 492 Figure 21.12 HCAN Input/Output Timing ................................................................................. 492 Figure 21.13 Motor Control PWM Output Timing .................................................................... 492 Appendix Figure C.1 FP-100A Package Dimensions ................................................................................. 498 Rev. 2.00, 03/04, page xxvi of xxx Tables Section 2 CPU Table 2.1 Instruction Classification ........................................................................................ 27 Table 2.2 Operation Notation ................................................................................................. 28 Table 2.3 Data Transfer Instructions....................................................................................... 29 Table 2.4 Arithmetic Operations Instructions (1) ................................................................... 30 Table 2.4 Arithmetic Operations Instructions (2) ................................................................... 31 Table 2.5 Logic Operations Instructions................................................................................. 32 Table 2.6 Shift Instructions..................................................................................................... 32 Table 2.7 Bit Manipulation Instructions (1)............................................................................ 33 Table 2.7 Bit Manipulation Instructions (2)............................................................................ 34 Table 2.8 Branch Instructions ................................................................................................. 35 Table 2.9 System Control Instructions.................................................................................... 36 Table 2.10 Block Data Transfer Instructions ............................................................................ 37 Table 2.11 Addressing Modes .................................................................................................. 39 Table 2.12 Absolute Address Access Ranges ........................................................................... 40 Table 2.13 Effective Address Calculation (1)........................................................................... 43 Table 2.13 Effective Address Calculation (2)........................................................................... 44 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection ............................................................................ 47 Section 4 Exception Handling Table 4.1 Exception Types and Priority.................................................................................. 51 Table 4.2 Exception Handling Vector Table........................................................................... 52 Table 4.3 Status of CCR and EXR after Trace Exception Handling....................................... 56 Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling...................... 57 Section 5 Interrupt Controller Table 5.1 Pin Configuration.................................................................................................... 63 Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities................................. 71 Table 5.3 Interrupt Control Modes ......................................................................................... 73 Table 5.4 Interrupt Response Times ....................................................................................... 78 Table 5.5 Number of States in Interrupt Handling Routine Execution Status ........................ 79 Section 7 I/O Ports Table 7.1 Port Functions (1) ................................................................................................... 88 Table 7.1 Port Functions (2) ................................................................................................... 89 Table 7.1 Port Functions (3) ................................................................................................... 90 Table 7.2 Pins of Registers to be Read and PWM Output by Switching Pins ...................... 130 Rev. 2.00, 03/04, page xxvii of xxx Section 8 16-Bit Timer Pulse Unit (TPU) Table 8.1 TPU Functions (1) ................................................................................................ 132 Table 8.1 TPU Functions (2) ................................................................................................ 133 Table 8.2 Pin Configuration.................................................................................................. 135 Table 8.3 CCLR0 to CCLR2 (Channel 0) ............................................................................ 138 Table 8.4 CCLR0 to CCLR2 (Channels 1 and 2) ................................................................. 138 Table 8.5 TPSC0 to TPSC2 (Channel 0) .............................................................................. 139 Table 8.6 TPSC0 to TPSC2 (Channel 1) .............................................................................. 139 Table 8.7 TPSC0 to TPSC2 (Channel 2) .............................................................................. 140 Table 8.8 MD0 to MD3 ........................................................................................................ 141 Table 8.9 TIORH_0 .............................................................................................................. 143 Table 8.10 TIORL_0 .............................................................................................................. 144 Table 8.11 TIOR_1................................................................................................................. 145 Table 8.12 TIOR_2................................................................................................................. 146 Table 8.13 TIORH_0 .............................................................................................................. 147 Table 8.14 TIORL_0 .............................................................................................................. 148 Table 8.15 TIOR_1................................................................................................................. 149 Table 8.16 TIOR_2................................................................................................................. 150 Table 8.17 Register Combinations in Buffer Operation ......................................................... 166 Table 8.18 PWM Output Registers and Output Pins .............................................................. 170 Table 8.19 Phase Counting Mode Clock Input Pins ............................................................... 174 Table 8.20 Up/Down-Count Conditions in Phase Counting Mode 1...................................... 175 Table 8.21 Up/Down-Count Conditions in Phase Counting Mode 2...................................... 176 Table 8.22 Up/Down-Count Conditions in Phase Counting Mode 3...................................... 177 Table 8.23 Up/Down-Count Conditions in Phase Counting Mode 4...................................... 178 Table 8.24 TPU Interrupts ...................................................................................................... 181 Section 9 Watchdog Timer Table 9.1 WDT Interrupt Source .......................................................................................... 211 Section 10 Serial Communication Interface (SCI) Table 10.1 Pin Configuration.................................................................................................. 217 Table 10.2 The Relationships between The N Setting in BRR and Bit Rate B ...................... 230 Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ........................... 231 Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ........................... 232 Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ........................... 233 Table 10.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 234 Table 10.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 234 Table 10.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 235 Table 10.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .... 235 Table 10.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (When n = 0 and S = 372)..................................................................................... 236 Rev. 2.00, 03/04, page xxviii of xxx Table 10.9 Table 10.10 Table 10.11 Table 10.12 Table 10.13 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372)...................................................................................................... 236 Serial Transfer Formats (Asynchronous Mode).................................................... 238 SSR Status Flags and Receive Data Handling ...................................................... 245 SCI Interrupt Sources............................................................................................ 273 SCI Interrupt Sources............................................................................................ 274 Section 11 Controller Area Network (HCAN) Table 11.1 Pin Configuration.................................................................................................. 279 Table 11.2 Limits for the Settable Value ................................................................................ 306 Table 11.3 Setting Range for TSEG1 and TSEG2 in BCR..................................................... 307 Table 11.4 HCAN Interrupt Sources....................................................................................... 319 Table 11.5 Interval Limitation between TXPR and TXPR or between TXPR and TXCR ..... 323 Section 12 A/D Converter Table 12.1 Pin Configuration.................................................................................................. 327 Table 12.2 Analog Input Channels and Corresponding ADDR Registers .............................. 328 Table 12.3 A/D Conversion Time (Single Mode)................................................................... 334 Table 12.4 A/D Conversion Time (Scan Mode) ..................................................................... 334 Table 12.5 A/D Converter Interrupt Source............................................................................ 335 Table 12.6 Analog Pin Specifications..................................................................................... 340 Section 13 Motor Control PWM Timer (PWM) Table 13.1 Pin Configuration.................................................................................................. 344 Table 13.2 PWM Interrupt Sources ........................................................................................ 358 Section 14 LCD Controller/Driver (LCD) Table 14.1 Pin Configuration.................................................................................................. 362 Table 14.2 Selection of the Duty Cycle and Common Functions ........................................... 364 Table 14.3 Selection of Segment Drivers ............................................................................... 364 Table 14.4 Selection of the Operating Clock and Frame Frequency ...................................... 366 Table 14.5 Output Levels (A Waveform) ............................................................................... 372 Table 14.6 Power-Down Modes and Display Operation ........................................................ 372 Section 16 Flash Memory (F-ZTAT Version) Table 16.1 Differences between Boot Mode and User Program Mode .................................. 379 Table 16.2 Pin Configuration.................................................................................................. 383 Table 16.3 Setting On-Board Programming Modes ............................................................... 387 Table 16.4 Boot Mode Operation ........................................................................................... 389 Table 16.5 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible ........................................................................................ 389 Table 16.6 Flash Memory Operating States............................................................................ 399 Section 17 Mask ROM Table 17.1 Register Present in F-ZTAT Version but Absent in Masked ROM Version......... 402 Rev. 2.00, 03/04, page xxix of xxx Section 18 Clock Pulse Generator Table 18.1 Damping Resistance Value................................................................................... 407 Table 18.2 Crystal Resonator Characteristics ......................................................................... 407 Table 18.3 External Clock Input Conditions .......................................................................... 408 Section 19 Power-Down Modes Table 19.1 Power-Down Mode Transition Conditions ........................................................... 415 Table 19.2 LSI Internal States in Each Mode ......................................................................... 416 Table 19.3 Oscillation Stabilization Time Settings ................................................................ 426 Table 19.4 Pin State in Each Processing State..................................................................... 434 Section 21 Electrical Characteristics Table 21.1 Absolute Maximum Ratings ................................................................................. 481 Table 21.2 DC Characteristics ................................................................................................ 482 Table 21.3 Permissible Output Currents................................................................................. 484 Table 21.4 Clock Timing ........................................................................................................ 485 Table 21.5 Control Signal Timing .......................................................................................... 487 Table 21.6 Timing of On-Chip Supporting Modules.............................................................. 489 Table 21.7 A/D Conversion Characteristics ........................................................................... 493 Table 21.8 Flash Memory Characteristics .............................................................................. 494 Table 21.9 LCD Characteristics.............................................................................................. 496 Rev. 2.00, 03/04, page xxx of xxx Section 1 Overview 1.1 Overview * High-speed H8S/2000 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions * Various peripheral functions 16-bit timer-pulse unit (TPU) Watchdog timer (WDT) Asynchronous or clocked synchronous serial communication interface (SCI) Controller area network (HCAN) 10-bit A/D converter Motor control PWM timer (PWM) LCD controller/driver (LCD) Clock pulse generator * On-chip memory ROM Model ROM RAM F-ZTAT Version HD64F2282 128 kbytes 4 kbytes Mask ROM Version HD6432282 HD6432281 128 kbytes 64 kbytes 4 kbytes 4 kbytes Pin Pitch * * * * * General I/O ports I/O pins: 64 Input-only pins: 8 Supports various power-down states Compact package Package (Code) Body Size QFP-100 FP-100A 14.0 x 20.0 mm 0.65 mm Rev. 2.00, 03/04, page 1 of 508 Internal Block Diagram PWMVCC PWMVCC PWMVSS PWMVSS LPVCC VCC VCC VSS VSS VSS VCL V1 V2 V3 AVCC AVSS 1.2 Port B Peripheral data bus WDT 2 channels Port C ROM (Mask ROM, flash memory) Peripheral address bus Port F Interrupt controller PF7/ PF6/SEG24 PF5/SEG23 PF4/SEG22 PF3/ / PF2/SEG21 Bus controller H8S/2000 CPU Internal data bus NMI FWE* Internal address bus Clock pulse generator Port A PLL MD2 MD0 EXTAL XTAL PLLCAP PLLVSS TPU 3 channels SCI PWM 10-bit A/D converter Port 4 HRxD/ HTxD Port J PH7/PWM1H PH6/PWM1G PH5/PWM1F PH4/PWM1E PH3/PWM1D PH2/PWM1C PH1/PWM1B PH0/PWM1A PJ7/PWM2H PJ6/PWM2G PJ5/PWM2F PJ4/PWM2E PJ3/PWM2D PJ2/PWM2C PJ1/PWM2B PJ0/PWM2A Port H Note: The FWE pin is provided only in the flash memory version. The NC pin is provided only in the mask ROM version. Figure 1.1 Internal Block Diagram Rev. 2.00, 03/04, page 2 of 508 PD7/SEG4 PD6/SEG3 PD5/SEG2 PD4/SEG1 P35/SCK1/ P34/RxD1 P33/TxD1 P32/SCK0/ P31/RxD0 P30/TxD0 2 channels P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Port 1 HCAN 1 channel Port D LCD P17/TIOCB2/TCLKD P16/TIOCA2/ P15/TIOCB1/TCLKC P14/TIOCA1/ P13/TIOCD0/TCLKB P12/TIOCC0/TCLKA P11/TIOCB0 P10/TIOCA0 Port 3 RAM PA7/SEG28 PA6/SEG27 PA5/SEG26 PA4/SEG25 PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 PB7/SEG20 PB6/SEG19 PB5/SEG18 PB4/SEG17 PB3/SEG16 PB2/SEG15 PB1/SEG14 PB0/SEG13 PC7/SEG12 PC6/SEG11 PC5/SEG10 PC4/SEG9 PC3/SEG8 PC2/SEG7 PC1/SEG6 PC0/SEG5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P31/RxD0 P32/SCK0/ P33/TxD1 P34/RxD1 P35/SCK1/ HRxD/ HTxD P40 / AN0 P41 / AN1 P42 / AN2 P43 / AN3 P44 / AN4 P45 / AN5 P46 / AN6 P47 / AN7 AVCC AVSS V1 V2 V3 VSS VCC PD4/SEG1 PD5/SEG2 PD6/SEG3 PD7/SEG4 PC0/SEG5 PC1/SEG6 PC2/SEG7 PC3/SEG8 PC4/SEG9 PC5/SEG10 PC6/SEG11 PC7/SEG12 PB0/SEG13 PB1/SEG14 PB2/SEG15 PB3/SEG16 LPVCC VSS PB4/SEG17 PB5/SEG18 PB6/SEG19 PB7/SEG20 PF2/SEG21 PF4/SEG22 PF5/SEG23 PF6/SEG24 PA4/SEG25 PA5/SEG26 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 / NMI MD0 MD2 P17/TIOCB2/TCLKD P16/TIOCA2/ P15/TIOCB1/TCLKC P14/TIOCA1/ P13/TIOCD0/TCLKB P12/TIOCD0/TCLKA P11/TIOCB0 P10/TIOCA0 PJ7/PWM2H PJ6/PWM2G PJ5/PWM2F PJ4/PWM2E PWMVCC PWMVSS FWE VCL PLLVSS PLLCAP P30/TxD0 PF3/ PF7/ VCC XTAL EXTAL VSS 1.3 Pin Arrangement Top view (FP-100A) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 PJ3/PWM2D PJ2/PWM2C PJ1/PWM2B PJ0/PWM2A PH7/PWM1H PH6/PWM1G PH5/PWM1F PH4/PWM1E PWMVCC PWMVSS PH3/PWM1D PH2/PWM1C PH1/PWM1B PH0/PWM1A PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 PA7/SEG28 PA6/SEG27 Figure 1.2 Pin Arrangement Rev. 2.00, 03/04, page 3 of 508 1.4 Pin Functions Type Symbol Pin NO. I/O Function Power Supply VCC 2 77 Input Power supply pins. Connect all these pins to the system power supply. PWMVCC 42 52 Input Power supply pins for the ports H, J, and the motor control PWM timer. LPVCC 19 Input Power supply pins for the ports A to D and F (PF2 and PF4 to PF6). V1 V2 V3 98 99 100 Input Power supply pins for the LCD controller/driver. These pins are internally connected to the power-supply dividing resistors and in normal use are open-circuit. When power is supplied, the state is LPVCC V1 V2 V3 VSS VSS 1 20 74 Input Ground pins. Connect all these pins to the system power supply (0V). PWMVSS 41 51 Input Power supply pins for the ports H, J, and the motor control PWM timer. Connect all these pins to the system power supply (0V). VCL 71 Output External capacitance pin for internal power-down power supply. Connect this pin to VSS via a 0.1F capacitor (placed close to the pins). PLLVSS 70 Input On-chip PLL oscillator ground pin. PLLCAP 69 Output External capacitance pin for an on-chip PLL oscillator. XTAL 76 Input For connection to a crystal resonator. For examples of crystal resonator connection and external clock input, see section 18, Clock Pulse Generator. EXTAL 75 Input For connection to a crystal resonator. (An external clock can be supplied from the EXTAL pin.) For examples of crystal resonator connection and external clock input, see section 18, Clock Pulse Generator. 78 Output Supplies the system clock to external devices. MD2 MD0 65 66 Input Set the operating mode. Inputs at these pins should not be changed during operation. Clock Operating mode control Rev. 2.00, 03/04, page 4 of 508 Type Symbol Pin NO. I/O Function System control RES 73 Input Reset input pin. When this pin is low, the chip is reset. STBY 68 Input When this pin is low, a transition is made to hardware standby mode. FWE 72 Input Pin for use by flash memory. This pin is only used in the flash memory version. NMI 67 Input Nonmaskable interrupt pin. If this pin is not used, it should be fixed-high. IRQ5 IRQ4 85 IRQ3 IRQ2 82 IRQ1 IRQ0 79 86 63 61 Input These pins request a maskable interrupt. 59 60 62 64 Input These pins input an external clock. TIOCA0 TIOCB0 TIOCC0 TIOCD0 57 58 59 60 Input/Out TGRA_0 to TGRD_0 input capture input/output put compare output/PWM output pins. TIOCA1 TIOCB1 61 62 Input/Out TGRA_1 to TGRB_1 input capture input/output put compare output/PWM output pins. TIOCA2 TIOCB2 63 64 Input/Out TGRA_2 to TGRB_2 input capture input/output put compare output/PWM output pins. Interrupts 16-bit timer- TCLKA pulse unit TCLKB TCLKC TCLKD Serial communication Interface (SCI)/ smart card interface HCAN TxD1 TxD0 83 80 Output Data output pins RxD1 RxD0 84 81 Input Data input pins SCK1 SCK0 85 82 Input/Out Clock input/output pins put HTxD 87 Output CAN bus transmission pin HRxD 86 Input CAN bus reception pin Rev. 2.00, 03/04, page 5 of 508 Type Symbol Pin NO. I/O Function A/D converter AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 95 94 93 92 91 90 89 88 Input Analog input pins ADTRG 79 Input Pin for input of an external trigger to start A/D conversion AVCC 96 Input Power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply (+5V). AVSS 97 Input The ground pin for the A/D converter. Connect this pin to the system power supply (0V). Motor PWM1H control PWM PWM1G timer PWM1F PWM1E PWM1D PWM1C PWM1B PWM1A 46 45 44 43 40 39 38 37 Output PWM_1 pulse output pin PWM2H PWM2G PWM2F PWM2E PWM2D PWM2C PWM2B PWM2A 56 55 54 53 50 49 48 47 Output PWM_2 pulse output pin Rev. 2.00, 03/04, page 6 of 508 Type Symbol Pin NO. I/O Function LCD controller/ driver SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 32 31 30 29 28 27 26 25 24 23 22 21 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Output Output pins for the LCD-segment-driving signals. COM4 COM3 COM2 COM1 36 35 34 33 Output Output pins for the LCD-common-driving signals. P17 P16 P15 P14 P13 P12 P11 P10 64 63 62 61 60 59 58 57 Input/ Output Eight input/output pins P35 P34 P33 P32 P31 P30 85 84 83 82 81 80 Input/ Output Six input/output pins I/O ports Rev. 2.00, 03/04, page 7 of 508 Type Symbol Pin NO. I/O Function I/O ports P47 P46 P45 P44 P43 P42 P41 P40 95 94 93 92 91 90 89 88 Input Eight input pins PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 32 31 30 29 36 35 34 33 Input/ Output Eight input/output pins PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 24 23 22 21 18 17 16 15 Input/ Output Eight input/output pins PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 14 13 12 11 10 9 8 7 Input/ Output Eight input/output pins PD7 PD6 PD5 PD4 6 5 4 3 Input/ Output Four input/output pins PF7 PF6 PF5 PF4 PF3 PF2 78 28 27 26 79 25 Input/ Output Six input/output pins Rev. 2.00, 03/04, page 8 of 508 Type Symbol Pin NO. I/O Function I/O ports PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 46 45 44 43 40 39 38 37 Input/ Output Eight input/output pins PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 56 55 54 53 50 49 48 47 Input/ Output Eight input/output pins Rev. 2.00, 03/04, page 9 of 508 Rev. 2.00, 03/04, page 10 of 508 Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, see section 3, MCU Operating Modes. 2.1 Features * Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H CPUs object programs * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes * High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 12 states 16 / 8-bit register-register divide: 12 states 16 x 16-bit register-register multiply: 20 states 32 / 16-bit register-register divide: 20 states CPUS212A_000620020200 Rev. 2.00, 03/04, page 11 of 508 * Two CPU operating modes Normal mode* Advanced mode * Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection Note: * Normal mode is not available in this LSI. 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below. * Register configuration The MAC register is supported by the H8S/2600 CPU only. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by the H8S/2600 CPU only. * The number of execution states of the MULXU and MULXS instructions; Execution States Instruction Mnemonic H8S/2600 H8S/2000 MULXU MULXU.B Rs, Rd 3 12 MULXU.W Rs, ERd 4 20 MULXS MULXS.B Rs, Rd 4 13 MULXS.W Rs, ERd 5 21 In addition, there are differences in address space, CCR and EXR register functions, and powerdown modes, etc., depending on the model. Rev. 2.00, 03/04, page 12 of 508 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements: * More general registers and control registers Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements: * Additional control register One 8-bit and two 32-bit control registers have been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. Rev. 2.00, 03/04, page 13 of 508 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. * Address Space A maximum address space of 64 kbytes can be accessed. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. * Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table in normal mode is shown in figure 2.1. For details of the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. * Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) is pushed onto the stack in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. Note: Normal mode is not available in this LSI. Rev. 2.00, 03/04, page 14 of 508 H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Exception vector 1 Exception vector 2 Exception vector 3 Exception vector table Exception vector 4 Exception vector 5 Exception vector 6 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) EXR*1 SP (SP * 2 Reserved*1,*3 ) CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. lgnored when returning. Figure 2.2 Stack Structure in Normal Mode Rev. 2.00, 03/04, page 15 of 508 2.2.2 Advanced Mode * Address Space Linear access is provided to a 16-Mbyte maximum address space is provided. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. * Instruction Set All instructions and addressing modes can be used. * Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Exception vector 1 H'00000003 H'00000004 Reserved Exception vector 2 H'00000007 H'00000008 Reserved Exception vector table Exception vector 3 H'0000000B H'0000000C Reserved Exception vector 4 H'00000010 Reserved Exception vector 5 Figure 2.3 Exception Vector Table (Advanced Mode) Rev. 2.00, 03/04, page 16 of 508 The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits is a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. * Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. EXR*1 SP SP Reserved PC (24 bits) (SP *2 Reserved*1, *3 ) (a) Subroutine Branch CCR PC (24 bits) (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2.4 Stack Structure in Advanced Mode Rev. 2.00, 03/04, page 17 of 508 2.3 Address Space Figure 2.5 shows a memory map for the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, see section 3, MCU Operating Modes. H'0000 H'00000000 64 kbytes 16 Mbytes H'FFFF Program area H'00FFFFFF Data area H'FFFFFFFF (a) Normal Mode* (b) Advanced Mode Note: * Normal mode is not available in this LSI. Figure 2.5 Memory Map Rev. 2.00, 03/04, page 18 of 508 2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR). General Registers (Rn) and Extended Registers (En) 15 0 7 0 7 0 ER0 E0 R0H R0L ER1 E1 R1H R1L ER2 E2 R2H R2L ER3 E3 R3H R3L ER4 E4 R4H R4L ER5 E5 R5H R5L ER6 E6 R6H R6L ER7 (SP) E7 R7H R7L Control Registers (CR) 23 0 PC 7 6 5 4 3 2 1 0 - - - - I2 I1 I0 EXR T 7 6 5 4 3 2 1 0 CCR I UI H U N Z V C [Legend] SP: PC: EXR: T: I2 to I0: CCR: I: Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit UI: H: U: N: Z: V: C: User bit or interrupt mask bit Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Figure 2.6 CPU Registers Rev. 2.00, 03/04, page 19 of 508 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8bit registers. The usage of each register can be selected independently. General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack. * Address registers * 32-bit registers * 16-bit registers * 8-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) RH registers (R0H to R7H) R registers (R0 to R7) RL registers (R0L to R7L) Figure 2.7 Usage of General Registers Rev. 2.00, 03/04, page 20 of 508 Free area SP (ER7) Stack area Figure 2.8 Stack Status 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). 2.4.3 Extended Control Register (EXR) EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions. When these instructions, except for the STC instruction, are executed, all interrupts including NMI will be masked for three states after execution is completed. Bit Bit Name Initial Value R/W Description 7 T 0 R/W Trace Bit When this bit is set to 1, a trace exception is generated each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 All 1 Reserved These bits are always read as 1. 2 I2 1 R/W 1 I1 1 R/W 0 I0 1 R/W These bits designate the interrupt mask level (0 to 7). For details, see section 5, Interrupt Controller. Rev. 2.00, 03/04, page 21 of 508 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. Bit Bit Name Initial Value R/W 7 I 1 R/W Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 by hardware at the start of an exception-handling sequence. For details, see section 5, Interrupt Controller. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit cannot be used as an interrupt mask bit in this LSI. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Rev. 2.00, 03/04, page 22 of 508 Bit Bit Name Initial Value 1 V Undefined R/W R/W Description Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.5 Initial Values of CPU Registers Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev. 2.00, 03/04, page 23 of 508 2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats in general registers. Data Type Register Number Data Format 7 RnH 1-bit data 0 Don't care 7 6 5 4 3 2 1 0 7 1-bit data RnL 4-bit BCD data RnH 4-bit BCD data RnL Byte data RnH Don't care 7 4 3 Upper 0 7 6 5 4 3 2 1 0 0 Lower Don't care 7 Don't care 7 4 3 Upper 0 Don't care MSB LSB 7 Byte data RnL 0 Don't care MSB Figure 2.9 General Register Data Formats (1) Rev. 2.00, 03/04, page 24 of 508 0 Lower LSB Data Type Register Number Word data Rn Data Format 15 0 MSB Word data LSB En 15 0 MSB LSB Longword data ERn 31 16 15 MSB En 0 Rn LSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 2.00, 03/04, page 25 of 508 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches. When ER7 is used as an address register to access the stack, the operand size should be word or longword. Data Type Address Data Format 1-bit data Address L 7 Byte data Address L MSB Word data Address 2M MSB 7 0 6 5 4 3 2 Address 2N 0 LSB LSB Address 2M+1 Longword data 1 MSB Address 2N+1 Address 2N+2 Address 2N+3 Figure 2.10 Memory Data Formats Rev. 2.00, 03/04, page 26 of 508 LSB 2.6 Instruction Set The H8S/2000 CPU has 65 instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 POP* , PUSH* 1 MOVFPE* , MOVTPE* Arithmetic operations Types B/W/L 5 W/L LDM, STM 3 Size L 3 B ADD, SUB, CMP, NEG B/W/L ADDX, SUBX, DAA, DAS B INC, DEC B/W/L ADDS, SUBS L MULXU, DIVXU, MULXS, DIVXS B/W EXTU, EXTS W/L TAS* 4 19 B Logic operations AND, OR, XOR, NOT B/W/L 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8 Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR B 14 Branch Bcc*2, JMP, BSR, JSR, RTS -- 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP -- 9 Block data transfer EEPMOV -- 1 Total: 65 [Legend] B: Byte W: Word L: Longword Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in this LSI. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 2.00, 03/04, page 27 of 508 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description Rd General register (destination)* Rs General register (source)* Rn General register* ERn General register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended control register CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition - Subtraction x Multiplication / Division Logical AND Logical OR Logical XOR Move NOT (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 2.00, 03/04, page 28 of 508 Table 2.3 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. MOVTPE B Cannot be used in this LSI. POP W/L @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. PUSH W/L Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. LDM L @SP+ Rn (register list) Pops two or more general registers from the stack. STM L Rn (register list) @-SP Pushes two or more general registers onto the stack. [Legend] B: Byte W: Word L: Longword Note: * Refers to the operand size. Rev. 2.00, 03/04, page 29 of 508 Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) ADDX SUBX B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. INC DEC B/W/L Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) ADDS SUBS L Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. DAA DAS B Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. MULXU B/W Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. MULXS B/W Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. DIVXU B/W Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. [Legend] B: Byte W: Word L: Longword Note: * Refers to the operand size. Rev. 2.00, 03/04, page 30 of 508 Table 2.4 Arithmetic Operations Instructions (2) Instruction Size*1 Function DIVXS B/W Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. CMP B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. NEG B/W/L 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTU W/L Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. EXTS W/L Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. TAS*2 B @ERd - 0, 1 (<bit 7> of @ERd) Tests memory contents, and sets the most significant bit (bit 7) to 1. [Legend] B: Byte W: Word L: Longword Notes: 1. Refers to the operand size. 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 2.00, 03/04, page 31 of 508 Table 2.5 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B/W/L (Rd) (Rd) Takes the one's complement of general register contents. [Legend] B: Byte W: Word L: Longword Note: * Refers to the operand size. Table 2.6 Shift Instructions Instruction Size* Function SHAL SHAR B/W/L Rd (shift) Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shifts are possible. SHLL SHLR B/W/L Rd (shift) Rd Performs a logical shift on general register contents. 1-bit or 2-bit shifts are possible. ROTL ROTR B/W/L Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotations are possible. ROTXL ROTXR B/W/L Rd (rotate) Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotations are possible. [Legend] B: Byte W: Word L: Longword Note: * Refers to the operand size. Rev. 2.00, 03/04, page 32 of 508 Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 (<bit-No.> of <EAd>) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B (<bit-No.> of <EAd>) (<bit-No.> of <EAd>) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B (<bit-No.> of <EAd>) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C (<bit-No.> of <EAd>) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIAND B C (<bit-No.> of <EAd>) C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR B C (<bit-No.> of <EAd>) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIOR B C (<bit-No.> of <EAd>) C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. [Legend] B: Byte Note: * Refers to the operand size. Rev. 2.00, 03/04, page 33 of 508 Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C (<bit-No.> of <EAd>) C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B BLD B (<bit-No.> of <EAd>) C Transfers a specified bit in a general register or memory operand to the carry flag. BILD B (<bit-No.> of <EAd>) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST B C (<bit-No.> of <EAd>) Transfers the carry flag value to a specified bit in a general register or memory operand. BIST B C (<bit-No.> of <EAd>) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. C (<bit-No.> of <EAd>) C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. [Legend] B: Byte Note: * Refers to the operand size. Rev. 2.00, 03/04, page 34 of 508 Table 2.8 Branch Instructions Instruction Size Function Bcc Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never BHI High CZ=0 BLS Low or same CZ=1 BCC(BHS) Carry clear (high or same) C=0 BCS(BLO) Carry set (low) C=1 BNE Not equal Z=0 BEQ Equal Z=1 BVC Overflow clear V=0 BVS Overflow set V=1 BPL Plus N=0 BMI Minus N=1 BGE Greater or equal NV=0 BLT Less than NV=1 BGT Greater than Z(N V) = 0 BLE Less or equal Z(N V) = 1 JMP Branches unconditionally to a specified address. BSR Branches to a subroutine at a specified address. JSR Branches to a subroutine at a specified address. RTS Returns from a subroutine Rev. 2.00, 03/04, page 35 of 508 Table 2.9 System Control Instructions Instruction Size* Function TRAPA Starts trap-instruction exception handling. RTE Returns from an exception-handling routine. SLEEP Causes a transition to a power-down state. LDC B/W (EAs) CCR, (EAs) EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. STC B/W CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. ANDC B CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. ORC B CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. XORC B CCR #IMM CCR, EXR #IMM EXR Logically XORs the CCR or EXR contents with immediate data. NOP PC + 2 PC Only increments the program counter. [Legend] B: Byte W: Word Note: * Refers to the operand size. Rev. 2.00, 03/04, page 36 of 508 Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next; EEPMOV.W if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. 2.6.2 Basic Instruction Formats This LSI's instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.11 shows examples of instruction formats. Rev. 2.00, 03/04, page 37 of 508 * Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition Field Specifies the branching condition of Bcc instructions. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA(disp) (4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:16, etc. Figure 2.11 Instruction Formats (Examples) Rev. 2.00, 03/04, page 38 of 508 2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or the absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes No. Addressing Mode Symbol 1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn) 4 Register indirect with post-increment Register indirect with pre-decrement @ERn+ @-ERn 5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 8 Memory indirect @@aa:8 2.7.1 Register Direct--Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect--@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 2.7.3 Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. Rev. 2.00, 03/04, page 39 of 508 2.7.4 Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn Register indirect with post-increment--@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For the word or longword transfer instructions, the register value should be even. Register indirect with pre-decrement--@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For the word or longword transfer instructions, the register value should be even. 2.7.5 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 Absolute Address Access Ranges Absolute Address Data address Normal Mode* Advanced Mode 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) Note: Normal mode is not available in this LSI. Rev. 2.00, 03/04, page 40 of 508 H'000000 to H'FFFFFF 2.7.6 Immediate--#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 Program-Counter Relative--@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 2.7.8 Memory Indirect--@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, see section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) Note: Normal mode is not available in this LSI. Rev. 2.00, 03/04, page 41 of 508 Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode* (a) Advanced Mode Note: * Normal mode is not available in this LSI. Figure 2.12 Branch Address Specification in Memory Indirect Mode 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is not available in this LSI. Rev. 2.00, 03/04, page 42 of 508 Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct(Rn) rm Operand is general register contents. rn Register indirect(@ERn) 31 0 op 3 31 24 23 0 Don't care General register contents r Register indirect with displacement @(d:16,ERn) or @(d:32,ERn) 31 0 General register contents op r 31 disp 31 Register indirect with post-increment or pre-decrement *Register indirect with post-increment @ERn+ op disp 31 0 31 24 23 0 Don't care General register contents r *Register indirect with pre-decrement @-ERn 0 0 Sign extension 4 24 23 Don't care 1, 2, or 4 31 0 General register contents 31 24 23 0 Don't care op r 1, 2, or 4 Operand Size Byte Word Longword Offset 1 2 4 Rev. 2.00, 03/04, page 43 of 508 Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 op @aa:16 31 op 0 H'FFFF 24 23 16 15 0 Don't care Sign extension abs @aa:24 31 op 8 7 24 23 Don't care abs 24 23 0 Don't care abs @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 0 24 23 Don't care abs Operand is immediate data. IMM 0 23 Program-counter relative PC contents @(d:8,PC)/@(d:16,PC) op disp 23 0 Sign extension disp 31 24 23 0 Don't care 8 Memory indirect @@aa:8 * Normal mode* 8 7 31 op abs 0 abs H'000000 15 0 31 24 23 Don't care Memory contents 16 15 0 H'00 * Advanced mode 8 7 31 op abs H'000000 31 0 Memory contents Note: * Normal mode is not available in this LSI. Rev. 2.00, 03/04, page 44 of 508 0 abs 31 24 23 Don't care 0 2.8 Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state transitions. * Reset State In this state, the CPU and all on-chip peripheral modules are initialized and not operating. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, see section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow. * Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, see section 4, Exception Handling. * Program Execution State In this state, the CPU executes program instructions in sequence. * Bus-Released State The bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. * Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further details, see section 19, Power-Down Modes. Rev. 2.00, 03/04, page 45 of 508 Reset state* igh =H , igh = H Low = Exception handling state Request for exception handling End of exception handling Program execution state In reqterru ue pt st Bus-released state s Bu est u req Bus request End of bus request us fb d o uest n E eq r SLEEP instruction Program halt state Notes: From any state, a transition to hardware standby mode occurs when goes low. * From any state except hardware standby mode, a transition to the reset state goes low. A transition can also be made to the reset state occurs whenever when the watchdog timer overflows. Figure 2.13 State Transitions 2.9 Usage Note 2.9.1 Note on Bit Manipulation Instructions Bit manipulation instructions such as BSET, BCLR, BNOT, BST, and BIST read data in byte units, perform bit manipulation, and write data in byte units. Thus, care must be taken when these bit manipulation instructions are executed for a register or port including write-only bits. In addition, the BCLR instruction can be used to clear the flag of an internal I/O register. In this case, if the flag to be cleared has been set by an interrupt processing routine, the flag need not be read before executing the BCLR instruction. Rev. 2.00, 03/04, page 46 of 508 Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports only operating mode 7, that is, the advanced single-chip mode. The operating mode is determined by the setting of the mode pins (MD2 and MD0). Only mode 7 can be used in this LSI. Therefore, all mode pins must be fixed high, as shown in table 3.1. Do not change the mode pin settings during operation. Table 3.1 MCU Operating Mode Selection MCU Operating Mode MD2 7 1 3.2 External Data Bus MD0 CPU Operating Mode Description On-Chip ROM Initial Width Max. Width 1 Advanced mode Single-chip mode Enabled Register Descriptions The following registers are related to the operating mode. * Mode control register (MDCR) * System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) Bit Bit Name Initial Value R/W Descriptions 7 1 R/W Reserved Only 1 should be written to this bit. 6 to 3 All 0 Reserved These bits are always read as 0 and cannot be modified. 2 MDS2 R This bit indicates the input level at pin MD2 (the current operating mode). This bit corresponds to MD2. MDS2 is read-only bit and this cannot be written to. The MD2 input level is latched into this bit when MDCR is read. This latch is canceled by a reset. This latch is canceled by a reset. 1 1 R Reserved This bit is always read as 1 and cannot be modified. Rev. 2.00, 03/04, page 47 of 508 Bit Bit Name Initial Value R/W Descriptions 0 MDS0 R This bit indicates the input level at pin MD0 (the current operating mode). This bit corresponds to MD0. MDS0 is read-only bit and this cannot be written to. The MD0 input level is latched into this bit when MDCR is read. This latch is canceled by a reset. This latch is canceled by a reset. 3.2.2 System Control Register (SYSCR) SYSCR selects the interrupt control mode and the detected edge for NMI, and enables or disables on-chip RAM. Bit Bit Name Initial Value R/W Descriptions 7 0 R/W Reserved Only 0 should be written to this bit. 6 0 Reserved This bit is always read as 0 and cannot be modified. 5 INTM1 0 R/W 4 INTM0 0 R/W These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.6, Interrupt Control Modes and Interrupt Operation. 00: Interrupt control mode 0 01: Setting prohibited 10: Interrupt control mode 2 11: Setting prohibited 3 NMIEG 0 R/W NMI Edge Select Selects the valid edge of the NMI interrupt input. 0: An interrupt is requested at the falling edge of NMI input 1: An interrupt is requested at the rising edge of NMI input 2, 1 All 0 Reserved These bits are always read as 0 and cannot be modified. Rev. 2.00, 03/04, page 48 of 508 Bit Bit Name Initial Value R/W Descriptions 0 RAME 1 R/W RAM Enable Enables or disables on-chip RAM. This bit is initialized when the reset status is released. 0: On-chip RAM is disabled 1: On-chip RAM is enabled 3.3 Pin Functions in Each Operating Mode The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, however external addresses cannot be accessed. All I/O ports are available for use as input-output ports. Rev. 2.00, 03/04, page 49 of 508 3.4 Address Map Figure 3.1 shows the address map in each operating mode. H8S/2282 H8S/2281 ROM: 128 kbytes RAM: 4 kbytes Mode 7 Advanced single-chip mode ROM: 64 kbytes RAM: 4 kbytes Mode 7 Advanced single-chip mode H'000000 H'000000 On-chip ROM (MASK ROM*) On-chip ROM (F-ZTAT/MASK ROM*) H'00FFFF H'01FFFF H'01FFFF H'FFE000 H'FFE000 On-chip RAM On-chip RAM H'FFEFBF H'FFEFBF H'FFF800 H'FFF800 Internal I/O registers H'FFFF3F Internal I/O registers H'FFFF3F H'FFFF60 H'FFFF60 Internal I/O registers H'FFFFBF H'FFFFC0 Internal I/O registers H'FFFFBF H'FFFFC0 On-chip RAM H'FFFFFF On-chip RAM H'FFFFFF Figure 3.1 Address Map Rev. 2.00, 03/04, page 50 of 508 Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode. For details on the interrupt control mode, see section 5, Interrupt Controller. Table 4.1 Exception Types and Priority Priority Exception Type Start of Exception Handling High Reset Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low. Trace*1 Starts when execution of the current instruction or exception handling ends, if the trace (T) bit in the EXR is set to 1 Direct transition Starts when a direction transition occurs as the result of SLEEP instruction execution. Interrupt Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued*2 Trap instruction*3 Started by execution of a trap instruction (TRAPA) Low Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in program execution state. 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Since the usable modes differ depending on the product, for details on each product, see section 3, MCU Operating Modes. Rev. 2.00, 03/04, page 51 of 508 Table 4.2 Exception Handling Vector Table Vector Address*1 Exception Source Vector Number Normal Mode*2 Advanced Mode Power-on reset 0 H'0000 to H'0001 H'0000 to H'0003 2 Manual reset * 1 H'0002 to H'0003 H'0004 to H'0007 Reserved for system use 2 H'0004 to H'0005 H'0008 to H'000B 3 H'0006 to H'0007 H'000C to H'000F 4 H'0008 to H'0019 H'0010 to H'0013 Trace 5 H'000A to H'000B H'0014 to H'0017 Interrupt (direct transitions)*3 6 H'000C to H'000D H'0018 to H'001B Interrupt (NMI) 7 H'000E to H'000F H'001C to H'001F Trap instruction (#0) 8 H'0010 to H'0011 H'0020 to H'0023 (#1) 9 H'0012 to H'0013 H'0024 to H'0027 (#2) 10 H'0014 to H'0015 H'0028 to H'002B (#3) 11 H'0016 to H'0017 H'002C to H'002F 12 H'0018 to H'0019 H'0030 to H'0033 Reserved for system use 13 H'001A to H'001B H'0034 to H'0037 14 H'001C to H'001D H'0038 to H'003B 15 H'001E to H'001F H'003C to H'003F IRQ0 16 H'0020 to H'0021 H'0040 to H'0043 IRQ1 17 H'0022 to H'0023 H'0044 to H'0047 IRQ2 18 H'0024 to H'0025 H'0048 to H'004B IRQ3 19 H'0026 to H'0027 H'004C to H'004F IRQ4 20 H'0028 to H'0029 H'0050 to H'0053 IRQ5 21 H'002A to H'002B H'0054 to H'0057 Reserved for system use 22 H'002C to H'002D H'0058 to H'005B 23 H'002E to H'002F H'005C to H'005F 24 127 H'0030 to H'0031 H'00FE to H'00FF H'0060 to H'0063 H'01FC to H'01FF External interrupt 4 Internal interrupt* Notes: 1. 2. 3. 4. Lower 16 bits of the address. Not available in this LSI. For details on direct transitions, see section 19.10, Direct Transitions. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling Vector Table. Rev. 2.00, 03/04, page 52 of 508 4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip can also be reset by overflow of the watchdog timer. For details see section 9, Watchdog Timer. The interrupt control mode is 0 immediately after reset. 4.3.1 Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figure 4.1 and figure 4.2 show examples of the reset sequence. Rev. 2.00, 03/04, page 53 of 508 Vector fetch Prefetch of first Internal processing program instruction (1) (3) Internal address bus (5) Internal read signal Internal write signal Internal data bus High (2) (4) (6) (1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled) Rev. 2.00, 03/04, page 54 of 508 Internal processing Vector fetch * * Prefetch of first program instruction * RES Address bus (1) (3) (5) RD HWR, LWR D15 to D0 High (2) (4) (6) (1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Three program wait states are inserted. Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled: Cannot be Used in this LSI) 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.3.3 State of On-Chip Peripheral Modules after Reset Release After reset release, MSTPCRA to MSTPCRD* are initialized to H'3F, H'FF, H'FF, and B'11****** respectively, and all modules enter module stop mode. Consequently, on-chip peripheral module registers cannot be read or written to. Register reading and writing is enabled when the module stop mode is exited. Note: * The initial values of bits 5 to 0 in MSTPCRD are undefined. Rev. 2.00, 03/04, page 55 of 508 4.4 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by clearing the T bit in EXR to 0. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Interrupts are accepted even within the trace exception handling routine. Table 4.3 Status of CCR and EXR after Trace Exception Handling CCR Interrupt Control Mode I 0 UI EXR I2 to I0 T Trace exception handling cannot be used. 2 1 0 [Legend] 1: Set to 1 0: Cleared to 0 : Retains value prior to execution 4.5 Interrupts Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, see section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended control register (EXR) are saved to the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution begins from that address. Rev. 2.00, 03/04, page 56 of 508 4.6 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. Trap instruction exception handling is conducted as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended control register (EXR) are saved to the stack. 2. The interrupt mask bit is updated and the T bit is cleared. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 1 2 1 0 [Legend] 1: Set to 1 0: Cleared to 0 : Retains value prior to execution Rev. 2.00, 03/04, page 57 of 508 4.7 Stack Status after Exception Handling Figures 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes*2 SP EXR Reserved*1 SP CCR CCR CCR*1 CCR*1 PC (16 bits) PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 (b) Advanced Modes SP EXR Reserved*1 SP CCR PC (24 bits) Interrupt control mode 0 CCR PC (24 bits) Interrupt control mode 2 Note: 1. Ignored on return. 2. Normal modes are not available in this LSI. Figure 4.3 Stack Status after Exception Handling Rev. 2.00, 03/04, page 58 of 508 4.8 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.W @SP+, Rn) POP.L ERn (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of what happens when the SP value is odd. Address CCR SP R1L SP H'FFFEFA H'FFFEFB PC PC H'FFFEFC H'FFFEFD H'FFFEFE SP H'FFFEFF SP set to H'FFFEFF TRAPA instruction executed MOV.B R1L, @-ER7 executed Data saved above SP Contents of CCR lost [Legend] CCR: PC: R1L: SP: Condition code register Program counter General register R1L Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.4 Operation when SP Value Is Odd Rev. 2.00, 03/04, page 59 of 508 Rev. 2.00, 03/04, page 60 of 508 Section 5 Interrupt Controller 5.1 Features * Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Seven external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ5 to IRQ0. Rev. 2.00, 03/04, page 61 of 508 A block diagram of the interrupt controller is shown in figure 5.1. CPU INTM1, INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input IRQ input unit ISR ISCR IER Interrupt request Vector number Priority determination I Internal interrupt request WOVI0 to RM0 CCR I2 to I0 IPR Interrupt controller [Legend] ISCR: IER: ISR: IPR: SYSCR: IRQ sense control register IRQ enable register IRQ status register Interrupt priority register System control register Figure 5.1 Block Diagram of Interrupt Controller Rev. 2.00, 03/04, page 62 of 508 EXR 5.2 Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable external interrupt Rising or falling edge can be selected IRQ5 Input Maskable external interrupts IRQ4 Input IRQ3 Input Rising, falling, or both edges, or level sensing, can be selected IRQ2 Input IRQ1 Input IRQ0 Input 5.3 Register Descriptions The interrupt controller has the following registers. For details system control register (SYSCR), see section 3.2.2, System Control Register(SYSCR). * * * * * * * * * * * * * * * System control register (SYSCR) IRQ sense control register H (ISCRH) IRQ sense control register L (ISCRL) IRQ enable register (IER) IRQ status register (ISR) Interrupt priority register A (IPRA) Interrupt priority register B (IPRB) Interrupt priority register C (IPRC) Interrupt priority register D (IPRD) Interrupt priority register E (IPRE) Interrupt priority register F (IPRF) Interrupt priority register G (IPRG) Interrupt priority register J (IPRJ) Interrupt priority register K (IPRK) Interrupt priority register M (IPRM) Rev. 2.00, 03/04, page 63 of 508 5.3.1 Interrupt Priority Registers A to G, J, K, M (IPRA to IPRG, IPRJ, IPRK, IPRM) The IPR registers set priorities (levels 7 to 0) for interrupts other than NMI. There are ten IPR registers. The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 0 to 2 and 4 to 6 sets the priority of the corresponding interrupt. Bit Bit Name Initial Value R/W Description 7 0 Reserved These bits are always read as 0. 6 IPR6 1 R/W Sets the priority of the corresponding interrupt source. 5 IPR5 1 R/W 000: Priority level 0 (Lowest) 4 IPR4 1 R/W 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) 3 0 Reserved This bit is always read as 0. 2 IPR2 1 R/W Sets the priority of the corresponding interrupt source. 1 IPR1 1 R/W 000: Priority level 0 (Lowest) 0 IPR0 1 R/W 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) Rev. 2.00, 03/04, page 64 of 508 5.3.2 IRQ Enable Register (IER) IER controls the enabling and disabling of interrupt requests IRQ5 to IRQ0. Bit Bit Name Initial Value R/W Description 7, 6 All 0 R/W Reserved Only 0 should be written to these bits. 5 IRQ5E 0 R/W IRQ5 Enable 4 IRQ4E 0 R/W IRQ4 Enable The IRQ5 interrupt request is enabled when this bit is 1. The IRQ4 interrupt request is enabled when this bit is 1. 3 IRQ3E 0 R/W IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1. 2 IRQ2E 0 R/W IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1. 1 IRQ1E 0 R/W IRQ1 Enable The IRQ1 interrupt request is enabled when this bit is 1. 0 IRQ0E 0 R/W IRQ0 Enable The IRQ0 interrupt request is enabled when this bit is 1. Rev. 2.00, 03/04, page 65 of 508 5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ5 to IRQ0. Bit Initial Bit Name Value R/W Description 15 to 12 R/W Reserved All 0 Only 0 should be written to these bits. 11 IRQ5SCB 0 R/W IRQ5 Sense Control B 10 IRQ5SCA 0 R/W IRQ5 Sense Control A 00: Interrupt request generated at IRQ5 input level low 01: Interrupt request generated at falling edge of IRQ5 input 10: Interrupt request generated at rising edge of IRQ5 input 11: Interrupt request generated at both falling and rising edges of IRQ5 input 9 IRQ4SCB 0 R/W IRQ4 Sense Control B 8 IRQ4SCA 0 R/W IRQ4 Sense Control A 00: Interrupt request generated at IRQ4 input level low 01: Interrupt request generated at falling edge of IRQ4 input 10: Interrupt request generated at rising edge of IRQ4 input 11: Interrupt request generated at both falling and rising edges of IRQ4 input 7 IRQ3SCB 0 R/W IRQ3 Sense Control B 6 IRQ3SCA 0 R/W IRQ3 Sense Control A 00: Interrupt request generated at IRQ3 input level low 01: Interrupt request generated at falling edge of IRQ3 input 10: Interrupt request generated at rising edge of IRQ3 input 11: Interrupt request generated at both falling and rising edges of IRQ3 input Rev. 2.00, 03/04, page 66 of 508 Bit Initial Bit Name Value R/W Description 5 IRQ2SCB 0 R/W IRQ2 Sense Control B 4 IRQ2SCA 0 R/W IRQ2 Sense Control A 00: Interrupt request generated at IRQ2 input level low 01: Interrupt request generated at falling edge of IRQ2 input 10: Interrupt request generated at rising edge of IRQ2 input 11: Interrupt request generated at both falling and rising edges of IRQ2 input 3 IRQ1SCB 0 R/W IRQ1 Sense Control B 2 IRQ1SCA 0 R/W IRQ1 Sense Control A 00: Interrupt request generated at IRQ1 input level low 01: Interrupt request generated at falling edge of IRQ1 input 10: Interrupt request generated at rising edge of IRQ1 input 11: Interrupt request generated at both falling and rising edges of IRQ1 input 1 IRQ0SCB 0 R/W IRQ0 Sense Control B 0 IRQ0SCA 0 R/W IRQ0 Sense Control A 00: Interrupt request generated at IRQ0 input level low 01: Interrupt request generated at falling edge of IRQ0 input 10: Interrupt request generated at rising edge of IRQ0 input 11: Interrupt request generated at both falling and rising edges of IRQ0 input Rev. 2.00, 03/04, page 67 of 508 5.3.4 IRQ Status Register (ISR) ISR indicates the status of IRQ5 to IRQ0 interrupt requests. Bit Bit Name Initial Value R/W Description 7. 6 All 0 R/W Reserved Only 0 should be written to these bits. 5 IRQ5F 0 R/W [Setting condition] 4 IRQ4F 0 R/W 3 IRQ3F 0 R/W When the interrupt source selected by the ISCR registers occurs 2 IRQ2F 0 R/W [Clearing conditions] 1 IRQ1F 0 R/W 0 IRQ0F 0 R/W * Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag * When interrupt exception handling is executed when low-level detection is set and IRQn input is high * When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set (n = 5 to 0) Rev. 2.00, 03/04, page 68 of 508 5.4 Interrupt Sources 5.4.1 External Interrupts There are seven external interrupts: NMI and IRQ5 to IRQ0. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. IRQ5 to IRQ0 Interrupts: Interrupts IRQ5 to IRQ0 are requested by an input signal at pins IRQ5 to IRQ0 Interrupts IRQ5 to IRQ0 have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ5 to IRQ0. * Enabling or disabling of interrupt requests IRQ5 to IRQ0 can be selected with IER. * The interrupt priority level can be set with IPR. * The status of interrupt requests IRQ5 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. The detection of IRQ5 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0; and use the pin as an I/O pin for another function. A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 5.2. IRQnE IRQnSCA, IRQnSCB IRQnF Edge / level detection circuit S Q IRQn interrupt request R input Clear signal Note: n= 5 to 0 Figure 5.2 Block Diagram of Interrupts IRQ5 to IRQ0 Rev. 2.00, 03/04, page 69 of 508 5.4.2 Internal Interrupts The sources for internal interrupts from on-chip peripheral modules have the following features: * For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. * The interrupt priority level can be set by means of IPR. 5.5 Interrupt Exception Handling Vector Table Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the IPR. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. Rev. 2.00, 03/04, page 70 of 508 Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address* Interrupt Source Origin of Interrupt Source External pin NMI Reserved for system use Vector Number Advanced Mode IPR Priority 7 H'001C IRQ0 16 H'0040 IPRA6 to IPRA4 IRQ1 17 H'0044 IPRA2 to IPRA0 IRQ2 18 H'0048 IPRB6 to IPRB4 IRQ3 19 H'004C IPRB6 to IPRB4 IPRB2 to IPRB0 IRQ4 20 H'0050 IRQ5 21 H'0054 22 H'0058 23 H'005C High Watchdog timer 0 WOVI0 25 H'0064 IPRD6 to IPRD4 A/D ADI 28 H'0070 IPRE2 to IPRE0 Watchdog timer 1 WOVI1 29 H'0074 IPRE2 to IPRE0 TPU TGI0A 32 H'0080 IPRF6 to IPRF4 channel 0 TGI0B 33 H'0084 TGI0C 34 H'0088 TGI0D 35 H'008C TCI0V 36 H'0090 TPU TGI1A 40 H'00A0 channel 1 TGI1B 41 H'00A4 TCI1V 42 H'00A8 TCI1U 43 H'00AC TGI2A 44 H'00B0 TPU channel 2 TGI2B 45 H'00B4 TCI2V 46 H'00B8 TCI2U 47 H'00BC IPRF2 to IPRF0 IPRG6 to IPRG4 Low Rev. 2.00, 03/04, page 71 of 508 Vector Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority SCI ERI0 80 H'0140 IPRJ2 to IPRJ0 High channel 0 RXI0 81 H'0144 TXI0 82 H'0148 TEI0 83 H'014C SCI ERI1 84 H'0150 channel 1 RXI1 85 H'0154 TXI1 86 H'0158 PWM Reserved for system use HCAN Reserved for system use Note: * TEI1 87 H'015C CMI1 104 H'01A0 CMI2 105 H'01A4 106 H'01A8 107 H'01AC ERS0/OVR0, RM0, 108 RM1, SLE0 109 (mailbox 0 reception) H'01B0 H'01B4 H'01BC 111 IPRK6 to IPRK4 IPRM6 to IPRM4 IPRM2 to IPRM0 Low Lower 16 bits of the start address. Rev. 2.00, 03/04, page 72 of 508 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by SYSCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.3 Interrupt Control Modes Interrupt Priority Setting Control Mode Registers Interrupt Mask Bits 0 I Default Description The priorities of interrupt sources are fixed at the default settings. Interrupt sources, except for NMI, are masked by the I bit. 2 IPR I2 to I0 8 priority levels other than NMI can be set with IPR. 8-level interrupt mask control is performed by bits I2 to I0. 5.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests other than for NMI are masked by the I bit of the CCR in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1 If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2 If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. If the I bit is cleared, an interrupt request is accepted. 3 Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. 4 When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5 The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6 Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. 7 The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 2.00, 03/04, page 73 of 508 Program execution status No Interrupt generated? Yes Yes NMI No I=0 No Hold pending Yes No IRQ0 Yes No IRQ1 Yes RM0 Yes Save PC and CCR I1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 2.00, 03/04, page 74 of 508 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is applied to eight levels for interrupt requests other than NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1 If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2 When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.3 is selected. 3 Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. 4 When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5 The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6 The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. 7 The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 2.00, 03/04, page 75 of 508 Program execution status Interrupt generated? No Yes Yes NMI No Level 7 interrupt? No Yes Mask level 6 or below? Yes Level 6 interrupt? No No Yes Level 1 interrupt? Mask level 5 or below? No No Yes Yes Mask level 0? No Yes Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2 5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev. 2.00, 03/04, page 76 of 508 Figure 5.5 Interrupt Exception Handling Rev. 2.00, 03/04, page 77 of 508 (1) (2) (4) (3) Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 (1) Internal data bus Internal write signal Internal read signal Internal address bus Interrupt request signal Interrupt level determination Instruction Wait for end of instruction prefetch Interrupt acceptance (7) (8) (10) (9) Vector fetch (12) (11) (14) (13) Interrupt service routine instruction prefetch Saved PC and saved CCR Vector address Interrupt handling routine start address (Vector address contents) Interrupt handling routine start address ((13) = (10)(12)) First instruction of interrupt handling routine (6) (6) (8) (9) (11) (10) (12) (13) (14) (5) Stack Internal operation 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, has the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.4 Interrupt Response Times Normal Mode*5 Advanced Mode No. Execution Status Interrupt control mode 0 1 Interrupt priority determination*1 3 2 Number of wait states until executing 1 to 19 +2*SI 1 to 19+2*SI instruction ends*2 1 to 19+2*SI 1 to 19+2*SI 3 PC, CCR, EXR stack save 2*SK 3*SK 2*SK 3*SK 4 Vector fetch SI SI 2*SI 2*SI 5 Instruction fetch*3 2*SI 2*SI 2*SI 2*SI 2 2 2 2 11 to 31 12 to 32 12 to 32 13 to 33 6 Internal processing* 4 Total (using on-chip memory) Notes: 1. 2. 3. 4. 5. Interrupt control mode 2 Interrupt control mode 0 Interrupt control mode 2 3 3 3 Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Not available in this LSI. Rev. 2.00, 03/04, page 78 of 508 Table 5.5 Number of States in Interrupt Handling Routine Execution Status Object of Access External Device * 8 Bit Bus Symbol Instruction fetch SI Branch address read SJ Stack manipulation SK 16 Bit Bus Internal Memory 2-State Access 3-State Access 2-State Access 3-State Access 1 4 6+2m 2 3+m [Legend] m: Number of wait states in an external device access. Note: * Cannot be used in this LSI. 5.7 Usage Notes 5.7.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.6 shows an example in which the TGIEA bit in the TPU's TIER_0 register is cleared to 0. The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. Rev. 2.00, 03/04, page 79 of 508 TIER_0 write cycle by CPU TCIVexception handling Internal address bus TIER_0 address Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5.6 Contention between Interrupt Generation and Disabling 5.7.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.3 When Interrupts Are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. Rev. 2.00, 03/04, page 80 of 508 5.7.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: 5.7.5 EEPMOV.W MOV.W R4,R4 BNE L1 IRQ Interrupts When the clock is operating, IRQ inputs are accepted in synchronization with the clock input. In software standby mode, IRQ inputs are accepted asynchronously. For details on the IRQ input conditions, see section 21.3.2, Control Signal Timing. Rev. 2.00, 03/04, page 81 of 508 Rev. 2.00, 03/04, page 82 of 508 Section 6 Bus Controller The H8S/2600 CPU is driven by a system clock, denoted by the symbol . The bus controller controls a memory cycle and a bus cycle. Different methods are used to access on-chip memory and on-chip peripheral modules. The bus controller also has a bus arbitration function, and controls the operation of the internal bus master. 6.1 Basic Timing The period from one rising edge of to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, three, or four states. Different methods are used to access on-chip memory, on-chip peripheral modules, and the external address space. 6.1.1 On-Chip Memory Access Timing (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 6.1 shows the on-chip memory access cycle. Bus cycle T1 Internal address bus Read access Internal read signal Internal data bus Write access Address Read data Internal write signal Internal data bus Write data Figure 6.1 On-Chip Memory Access Cycle BSCS209A_000020020200 Rev. 2.00, 03/04, page 83 of 508 6.1.2 On-Chip Peripheral Module Access Timing The on-chip peripheral modules, except for HCAN, PWM, LCD, Ports H and J, are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. For details, see section 20, List of Registers. Figure 6.2 shows access timing for the on-chip peripheral modules. Bus cycle T1 T2 Internal address bus Read access Internal read signal Internal data bus Write access Address Read data Internal write signal Internal data bus Write data Figure 6.2 On-Chip Peripheral Module Access Cycle Rev. 2.00, 03/04, page 84 of 508 6.1.3 On-Chip HCAN Module Access Timing On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access timing is shown in figures 6.3. Bus cycle T1 T2 T3 Tw Tw T4 Internal address bus Address HCAN read signal Read access Internal data bus Read data HCAN write signal Write access Internal data bus Write data Figure 6.3 On-Chip HCAN Module Access Cycle (Wait States Inserted) 6.1.4 On-Chip PWM, LCD, Ports H and J Module Access Timing On-chip PWM, LCD, Ports H and J module access timing is performed in four states. The data bus width is 16 bits. PWM, LCD, Ports H and J module access timing is shown in figure 6.4. Bus cycle T1 T2 T3 T4 Internal address bus Address PWM, LCD, ports H Read and J read signal access Internal data bus PWM, LCD, ports H and J write signal Write access Internal data bus Read data Write data Figure 6.4 On-Chip PWM, LCD, Ports H and J Module Access Cycle Rev. 2.00, 03/04, page 85 of 508 Rev. 2.00, 03/04, page 86 of 508 Section 7 I/O Ports Table 7.1 summarizes the port functions. The pins of each port also have other functions such as input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR or DDR register. Ports 3 and A to C includes an open-drain control register (ODR) that controls the on/off state of the output buffer PMOS. All of the I/O ports can drive a single TTL load and 30 pF capacitive load. Rev. 2.00, 03/04, page 87 of 508 Table 7.1 Port Functions (1) Port Description Port 1 General I/O port also functioning as TPU_0, TPU_1,and TPU_2 I/O pins and interrupt input pins Port and Other Functions Name Input/Output and Output Type P17/TIOCB2/TCLKD P16/TIOCA2/IRQ1 P15/TIOCB1/TCLKC P14/TIOCA1/IRQ0 P13/TIOCD0/TCLKB P12/TIOCC0/TCLKA P11/TIOCB0 P10/TIOCA0 Port 3 General I/O port also functioning as SCI_0 and SCI_1 I/O pins and interrupt input pins P35/SCK1/IRQ5 P34/RxD1 Push-pull or open-drain output type selectable P33/TxD1 P32/SCK0/IRQ4 P31/RxD0 P30/TxD0 Port 4 General input port also P47/AN7 functioning as A/D P46/AN6 converter analog input pins P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Port A General I/O port also PA7/SEG28 functioning as segment PA6/SEG27 and common output pins of PA5/SEG26 LCD PA4/SEG25 PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 Rev. 2.00, 03/04, page 88 of 508 Push-pull or open-drain output type selectable Table 7.1 Port Functions (2) Port Description Port B General I/O port also functioning as segment output pins of LCD Port and Other Functions Name Input/Output and Output Type PB7/SEG20 Push-pull or open-drain output type selectable PB6/SEG19 PB5/SEG18 PB4/SEG17 PB3/SEG16 PB2/SEG15 PB1/SEG14 PB0/SEG13 Port C General I/O port also functioning as segment output pins of LCD PC7/SEG12 PC6/SEG11 Push-pull or open-drain output type selectable PC5/SEG10 PC4/SEG9 PC3/SEG8 PC2/SEG7 PC1/SEG6 PC0/SEG5 Port D General I/O port also functioning as segment output pins of LCD PD7/SEG4 PD6/SEG3 PD5/SEG2 PD4/SEG1 Port F General I/O port also functioning as interrupt input pin, A/D converter start trigger input pin, segment output pins of LCD, and a system clock output pin PF7/ PF6/SEG24 PF5/SEG23 PF4/SEG22 PF3/ADTRG/IRQ3 PF2/SEG21 Rev. 2.00, 03/04, page 89 of 508 Table 7.1 Port Functions (3) Port Description Port H General I/O port also functioning as PWM_1 output pins Port and Other Functions Name PH7/PWM1H PH6/PWM1G PH5/PWM1F PH4/PWM1E PH3/PWM1D PH2/PWM1C PH1/PWM1B PH0/PWM1A Port J General I/O port also functioning as PWM_2 output pins PJ7/PWM2H PJ6/PWM2G PJ5/PWM2F PJ4/PWM2E PJ3/PWM2D PJ2/PWM2C PJ1/PWM2B PJ0/PWM2A Rev. 2.00, 03/04, page 90 of 508 Input/Output and Output Type 7.1 Port 1 Port 1 is an 8-bit I/O port. Port 1 has the following registers. * Port 1 data direction register (P1DDR) * Port 1 data register (P1DR) * Port 1 register (PORT1) 7.1.1 Port 1 Data Direction Register (P1DDR) The individual bits of P1DDR specify input or output for the pins of port 1. Bit Bit Name Initial Value R/W Description 7 P17DDR 0 W 6 P16DDR 0 W 5 P15DDR 0 W When a pin function is specified to a general I/O port, setting this bit to 1 makes the corresponding port 1 pin an output pin, while clearing this bit to 0 makes the pin an input pin. 4 P14DDR 0 W 3 P13DDR 0 W 2 P12DDR 0 W 1 P11DDR 0 W 0 P10DDR 0 W 7.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit Bit Name Initial Value R/W Description 7 P17DR 0 R/W 6 P16DR 0 R/W Output data for a pin is stored when the pin function is specified to a general I/O port. 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W Rev. 2.00, 03/04, page 91 of 508 7.1.3 Port 1 Register (PORT1) PORT1 shows port 1 pin states. PORT1 cannot be modified. Bit Bit Name Initial Value 7 P17 Undefined* R 6 P16 Undefined* R 5 P15 Undefined* R 4 P14 Undefined* R 3 P13 Undefined* R 2 P12 Undefined* R 1 P11 Undefined* R 0 P10 Undefined* R Note: 7.1.4 * R/W Description If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read. Determined by the states of pins P17 to P10. Pin Functions Port 1 pins also function as I/O pins of TPU_0, TPU_1, and TPU_2, and interrupt input pins. The correspondence between the register specification and the pin functions is shown below. Rev. 2.00, 03/04, page 92 of 508 * P17/TIOCB2/TCLKD The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0, and bit P17DDR. TPU channel 2 settings (1) in table below 0 TIOCB2 output P17 input P17DDR Pin function (2) in table below 1 P17 output TIOCB2 input*1 TCLKD input*2 TPU channel 2 settings (2) (1) MD3 to MD0 B'0000, B'01xx (2) (2) B'0010 (1) (2) B'0011 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 CCLR1, CCLR0 Other than B'10 B'10 Output function Output compare output PWM mode 2 output IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx while IOB3 = 1. 2. TCLKD input when TPSC2 to TPSC0 = B'111 in TCR_0. TCLKD input when phase counting mode is set to channel 2. Rev. 2.00, 03/04, page 93 of 508 * P16/TIOCA2/IRQ1 The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2) and bit P16DDR. TPU channel 2 settings (1) in table below 0 TIOCA2 output P16 input P16DDR Pin function (2) in table below 1 P16 output TIOCA2 input*1 IRQ1 input TPU channel 2 settings (2) MD3 to MD0 B'0000, B'01xx IOA3 to IOA0 (1) (2) (1) B'001x B'0010 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 CCLR1, CCLR0 Output function Output compare output (1) B'0011 Other than B'xx00 Other than B'01 PWM mode PWM mode 1 output*2 2 output [Legend] x: Don't care Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx while IOA3 = 1. 2. TIOCB2 output disabled. Rev. 2.00, 03/04, page 94 of 508 (2) B'01 * P15/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, and bit P15DDR. TPU channel 1 settings (1) in table below P15DDR Pin function (2) in table below -- 0 TIOCB1 output P15 input 1 P15 output TIOCB1 input*1 TCLKC input*2 TPU channel 1 settings (2) MD3 to MD0 B'0000, B'01xx IOB3 to IOB0 (1) (2) (2) B'0010 (1) (2) B'0011 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 -- B'xx00 Other than B'xx00 CCLR1, CCLR0 -- -- -- -- Other than B'10 B'10 Output function -- Output compare output -- -- PWM mode 2 output -- [Legend] x: Don't care Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx while IOB3 to IOB0 = B'10xx. 2. TCLKC input when the bits TPSC2 to TPSC0 in either TCR_0 or TCR_2 are set to B'110. TCLKC input also when phase counting mode is set for channel 2. Rev. 2.00, 03/04, page 95 of 508 * P14/TIOCA1/IRQ0 The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1) and bit P14DDR. TPU channel 1 settings (1) in table below P14DDR Pin function (2) in table below -- 0 TIOCA1 output P14 input 1 P14 output TIOCA1 input*1 IRQ0 input TPU channel 1 settings (2) MD3 to MD0 B'0000, B'01xx IOA3 to IOA0 (1) (2) (1) B'001x B'0010 B'0011 Other than B'xx00 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR1, CCLR0 -- -- -- -- Output function -- Output compare output -- (1) (2) Other than B'01 PWM mode PWM mode 1 output*2 2 output B'01 -- [Legend] x: Don't care Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx while IOA3 to IOA0 = B'10xx. 2. TIOCB1 output disabled. Rev. 2.00, 03/04, page 96 of 508 * P13/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, and bit P13DDR. TPU channel 0 settings (1) in table below P13DDR Pin function (2) in table below -- 0 TIOCD0 output P13 input 1 P13 output TIOCD0 input*1 TCLKB input*2 TPU channel 0 settings (2) MD3 to MD0 IOD3 to IOD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 -- B'xx00 Other than B'xx00 CCLR2 to CCLR0 -- -- -- -- Other than B'110 B'110 Output function -- Output compare output -- -- PWM mode 2 output -- [Legend] x: Don't care Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 while IOD3 to IOD0 = B'10xx. 2. TCLKB input when TPSC2 to TPSC0 = B'101 in any of TCR_0 to TCR_2. TCLKB input also when phase counting mode is set for channel 1. Rev. 2.00, 03/04, page 97 of 508 * P12/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, and bit P12DDR. TPU channel 0 settings (1) in table below P12DDR Pin function (2) in table below -- 0 TIOCC0 output P12 input 1 P12 output TIOCC0 input*1 TCLKA input*2 TPU channel 0 settings (2) MD3 to MD0 IOC3 to IOC0 (1) B'0000 (2) (1) B'001x B'0010 B'0011 Other than B'xx00 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 -- -- -- -- Output function -- Output compare output -- (1) (2) Other than B'101 PWM mode PWM mode 1 output*3 2 output B'101 -- [Legend] x: Don't care Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 while IOC3 to IOC0 = B'10xx. 2. TCLKA input when TPSC2 to TPSC0 = B'100 in any of TCR_0 to TCR_2. TCLKA input also when phase counting mode is set for channel 1. 3. TIOCC0 output disabled. Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR_0. Rev. 2.00, 03/04, page 98 of 508 * P11/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0) and bit P11DDR. TPU channel 0 settings (1) in table below P11DDR Pin function (2) in table below -- 0 TIOCB0 output P11 input 1 P11 output TIOCB0 input TPU channel 0 settings (2) MD3 to MD0 IOB3 to IOB0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 -- B'xx00 Other than B'xx00 CCLR2 to CCLR0 -- -- -- -- Other than B'010 B'010 Output function -- Output compare output -- -- PWM mode 2 output -- [Legend] x: Don't care Note: TIOCB0 input when MD3 to MD0 = B'0000 while IOB3 to IOB0 = B'10xx. Rev. 2.00, 03/04, page 99 of 508 * P10/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0) and bit P10DDR. TPU channel 0 settings (1) in table below P10DDR Pin function (2) in table below -- 0 TIOCA0 output P10 input 1 P10 output TIOCA0 input* TPU channel 0 settings (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000 (2) (1) B'001x B'0010 B'0011 Other than B'xx00 B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 -- -- -- -- Output function -- Output compare output -- (1) (2) Other than B'001 PWM mode PWM mode 1 output*2 2 output [Legend] x: Don't care Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000 while IOA3 to IOA0 = B'10xx. 2. TIOCA0 output disabled. Rev. 2.00, 03/04, page 100 of 508 B'001 -- 7.2 Port 3 Port 3 is a 6-bit I/O port that also has other functions. Port 3 has the following registers. * * * * Port 3 data direction register (P3DDR) Port 3 data register (P3DR) Port 3 register (PORT3) Port 3 open-drain control register (P3ODR) 7.2.1 Port 3 Data Direction Register (P3DDR) The individual bits of P3DDR specify input or output for the pins of port 3. Bit Bit Name Initial Value R/W 7, 6 -- Undefined -- Description Reserved These bits will return undefined values if read. 5 P35DDR 0 W 4 P34DDR 0 W 3 P33DDR 0 W 2 P32DDR 0 W 1 P31DDR 0 W 0 P30DDR 0 W 7.2.2 When a pin function is specified to a general I/O port, setting this bit to 1 makes the corresponding port 1 pin an output pin, while clearing this bit to 0 makes the pin an input pin. Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit Bit Name Initial Value R/W Description 7, 6 -- Undefined -- Reserved These bits will return undefined values if read. 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W Output data for a pin is stored when the pin function is specified to a general I/O port. Rev. 2.00, 03/04, page 101 of 508 7.2.3 Port 3 Register (PORT3) PORT3 shows port 3 pin states. PORT3 cannot be modified. Bit Bit Name Initial Value R/W 7, 6 -- Undefined -- Description Reserved These bits will return undefined values if read. 5 P35 Undefined* R 4 P34 Undefined* R 3 P33 Undefined* R 2 P32 Undefined* R 1 P31 Undefined* R 0 P30 Undefined* R Note: 7.2.4 * If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read. Determined by the states of pins P35 to P30. Port 3 Open-Drain Control Register (P3ODR) P3ODR selects the output type of port 3. Bit Bit Name Initial Value R/W Description 7, 6 -- Undefined -- Reserved These bits will return undefined values if read. 5 P35ODR 0 R/W 4 P34ODR 0 R/W 3 P33ODR 0 R/W 2 P32ODR 0 R/W 1 P31ODR 0 R/W 0 P30ODR 0 R/W Rev. 2.00, 03/04, page 102 of 508 Setting this bit to 1 turns off the PMOS of the corresponding pin, and if the pin function is specified to output, makes it an open-drain output pin, while clearing this bit to 0 makes it a push-pull output pin. 7.2.5 Pin Functions Port 3 pins also function as I/O pins for SCI_0 and SCI_1, and interrupt input pins. The correspondence between the register specification and the pin functions is shown below. * P35/SCK1/IRQ5 The pin function is switched as shown below according to the combination of bit C/A in SMR and bits CKE0 and CKE1 in SCR of SCI_1, and bit P35DDR. CKE1 0 C/A CKE0 P35DDR Pin function 1 0 0 1 -- 1 -- -- 0 1 -- -- -- P35 input P35 output SCK1 output SCK1 output SCK1 input IRQ5 input * P34/RxD1 The pin function is switched as shown below according to the combination of bit RE in SCR of SCI_1 and bit P34DDR. RE P34DDR Pin function 0 1 0 1 -- P34 input P34 output RxD1 input * P33/TxD1 The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_1 and bit P33DDR. TE P33DDR Pin function 0 1 0 1 -- P33 input P33 output TxD1 output Rev. 2.00, 03/04, page 103 of 508 * P32/SCK0/IRQ4 The pin function is switched as shown below according to the combination of bit C/A in SMR and bits CKE0 and CKE1 in SCR of SCI_0, and bit P32DDR. CKE1 0 C/A 0 CKE0 P32DDR Pin function 1 0 1 -- 1 -- -- 0 1 -- -- -- P32 input P32 output SCK0 output SCK0 output SCK0 input IRQ4 input * P31/RxD0 The pin function is switched as shown below according to the combination of bit RE in SCR of SCI_0 and bit P31DDR. RE P31DDR Pin function 0 1 0 1 -- P31 input P31 output RxD0 input * P30/TxD0 The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_0 and bit P30DDR. TE P30DDR Pin function 0 1 0 1 -- P30 input P30 output TxD0 input Rev. 2.00, 03/04, page 104 of 508 7.3 Port 4 Port 4 is an 8-bit I/O port that also functions as an A/D converter analog input port. Port 4 has the following register. * Port 4 register (PORT4) 7.3.1 Port 4 Register (PORT4) PORT4 shows port 4 pin states. PORT4 cannot be modified. Bit Bit Name Initial Value 7 P47 Undefined* R 6 P46 Undefined* R 5 P45 Undefined* R 4 P44 Undefined* R 3 P43 Undefined* R 2 P42 Undefined* R 1 P41 Undefined* R 0 P40 Undefined* R Note: * R/W Description The pin states are always read when a port 4 read is performed. Determined by the states of pins P47 to P40. Rev. 2.00, 03/04, page 105 of 508 7.4 Port A Port A is an 8-bit I/O port that also has other functions. Port A has the following registers. * * * * Port A data direction register (PADDR) Port A data register (PADR) Port A register (PORTA) Port A open-drain control register (PAODR) 7.4.1 Port A Data Direction Register (PADDR) The individual bits of PADDR specify input or output for the pins of port A. Bit Bit Name Initial Value R/W Description 7 PA7DDR 0 W 6 PA6DDR 0 W 5 PA5DDR 0 W When a pin function is specified to a general I/O port, setting this bit to 1 makes the corresponding port A pin an output pin, while clearing this bit to 0 makes the pin an input pin. 4 PA4DDR 0 W 3 PA3DDR 0 W 2 PA2DDR 0 W 1 PA1DDR 0 W 0 PA0DDR 0 W 7.4.2 Port A Data Register (PADR) PADR stores output data for the port A pins. Bit Bit Name Initial Value R/W Description 7 PA7DR 0 R/W 6 PA6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general I/O port. 5 PA5DR 0 R/W 4 PA4DR 0 R/W 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W Rev. 2.00, 03/04, page 106 of 508 7.4.3 Port A Register (PORTA) PORTA shows port A pin states. PORTA cannot be modified. Bit Bit Name Initial Value 7 PA7 Undefined* R 6 PA6 Undefined* R 5 PA5 Undefined* R 4 PA4 Undefined* R 3 PA3 Undefined* R 2 PA2 Undefined* R 1 PA1 Undefined* R 0 PA0 Undefined* R Note: 7.4.4 * R/W Description If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A read is performed while PADDR bits are cleared to 0, the pin states are read. Determined by the states of pins PA7 to PA0. Port A Open Drain Control Register (PAODR) PAODR selects the output type of port A. Bit Bit Name Initial Value R/W Description 7 PA7ODR 0 R/W 6 PA6ODR 0 R/W 5 PA5ODR 0 R/W Setting this bit to 1 turns off the PMOS of the corresponding pin, and if the pin function is specified to output, makes it an open-drain output pin, while clearing this bit to 0 makes it a push-pull output pin. 4 PA4ODR 0 R/W 3 PA3ODR 0 R/W 2 PA2ODR 0 R/W 1 PA1ODR 0 R/W 0 PA0ODR 0 R/W Rev. 2.00, 03/04, page 107 of 508 7.4.5 Pin Functions Port A pins also function as segment output pins and common output pins of the LCD. The correspondence between the register specification and the pin functions is shown below. * PA7/SEG28, PA6/SEG27, PA5/SEG26, PA4/SEG25 The pin function is switched as shown below according to the combination of bits SGS3 to SGS0 in LPCR of the LCD and bit PAnDDR. SGS3 to SGS0 PAnDDR Pin function 0000 Other than 0000 0 1 -- PA7 to PA4 input PA7 to PA4 output SEG28 to SEG25 output n = 7 to 4 * PA3/COM4, PA2/COM3, PA1/COM2, PA0/COM1 The pin function is switched as shown below according to the combination of bits SGS3 to SGS0 in LPCR of the LCD and bit PAnDDR. SGS3 to SGS0 PAnDDR Pin function 0000 Other than 0000 0 1 -- PA3 to PA0 input PA3 to PA0 output COM4 to COM1 output n = 3 to 0 Rev. 2.00, 03/04, page 108 of 508 7.5 Port B Port B is an 8-bit I/O port that also has other functions. Port B has the following registers. * * * * Port B data direction register (PBDDR) Port B data register (PBDR) Port B register (PORTB) Port B open-drain control register (PBODR) 7.5.1 Port B Data Direction Register (PBDDR) The individual bits of PBDDR specify input or output for the pins of port B. Bit Bit Name Initial Value R/W Description 7 PB7DDR 0 W 6 PB6DDR 0 W 5 PB5DDR 0 W When a pin function is specified to a general I/O port, setting this bit to 1 makes the corresponding port 1 pin an output pin, while clearing this bit to 0 makes the pin an input pin. 4 PB4DDR 0 W 3 PB3DDR 0 W 2 PB2DDR 0 W 1 PB1DDR 0 W 0 PB0DDR 0 W 7.5.2 Port B Data Register (PBDR) PBDR stores output data for the port B pins. Bit Bit Name Initial Value R/W Description 7 PB7DR 0 R/W 6 PB6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general I/O port. 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 PB0DR 0 R/W Rev. 2.00, 03/04, page 109 of 508 7.5.3 Port B Register (PORTB) PORTB shows port B pin states. PORTB cannot be modified. Bit Bit Name Initial Value 7 PB7 Undefined* R 6 PB6 Undefined* R 5 PB5 Undefined* R 4 PB4 Undefined* R 3 PB3 Undefined* R 2 PB2 Undefined* R 1 PB1 Undefined* R 0 PB0 Undefined* R Note: 7.5.4 * R/W Description If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is performed while PBDDR bits are cleared to 0, the pin states are read. Determined by the states of pins PB7 to PB0. Port B Open Drain Control Register (PBODR) PBODR selects the output type of port B. Bit Bit Name Initial Value R/W Description 7 PB7ODR 0 R/W 6 PB6ODR 0 R/W 5 PB5ODR 0 R/W Setting this bit to 1 turns off the PMOS of the corresponding pin, and if the pin function is specified to output, makes it an open-drain output pin, while clearing this bit to 0 makes it a push-pull output pin. 4 PB4ODR 0 R/W 3 PB3ODR 0 R/W 2 PB2ODR 0 R/W 1 PB1ODR 0 R/W 0 PB0ODR 0 R/W Rev. 2.00, 03/04, page 110 of 508 7.5.5 Pin Functions Port B pins also function as segment output pins of the LCD. The correspondence between the register specification and the pin functions is shown below. * PB7/SEG20, PB6/SEG19, PB5/SEG18, PB4/SEG17 The pin function is switched as shown below according to the combination of bits SGS3 to SGS0 in LPCR of the LCD and bit PBnDDR. SGS3 to SGS0 PBnDDR Pin function 0000 or 0001 Other than 0000 or 0001 0 1 -- PB7 to PB4 input PB7 to PB4 output SEG20 to SEG17 output n = 7 to 4 * PB3/SEG16, PB2/SEG15, PB1/SEG14, PB0/SEG13 The pin function is switched as shown below according to the combination of bits SGS3 to SGS0 in LPCR of the LCD and bit PBnDDR. SGS3 to SGS0 PBnDDR Pin function 0000 to 0010 Other than 0000 to 0010 0 1 -- PB3 to PB0 input PB3 to PB0 output SEG16 to SEG13 output n = 3 to 0 Rev. 2.00, 03/04, page 111 of 508 7.6 Port C Port C is an 8-bit I/O port that also has other functions. Port C has the following registers. * * * * Port C data direction register (PCDDR) Port C data register (PCDR) Port C register (PORTC) Port C open-drain control register (PCODR) 7.6.1 Port C Data Direction Register (PCDDR) The individual bits of PCDDR specify input or output for the pins of port C. Bit Bit Name Initial Value R/W Description 7 PC7DDR 0 W 6 PC6DDR 0 W 5 PC5DDR 0 W When a pin function is specified to a general I/O port, setting this bit to 1 makes the corresponding port 1 pin an output pin, while clearing this bit to 0 makes the pin an input pin. 4 PC4DDR 0 W 3 PC3DDR 0 W 2 PC2DDR 0 W 1 PC1DDR 0 W 0 PC0DDR 0 W 7.6.2 Port C Data Register (PCDR) PCDR stores output data for the port C pins. Bit Bit Name Initial Value R/W Description 7 PC7DR 0 R/W 6 PC6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general I/O port. 5 PC5DR 0 R/W 4 PC4DR 0 R/W 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 PC0DR 0 R/W Rev. 2.00, 03/04, page 112 of 508 7.6.3 Port C Register (PORTC) PORTC shows port C pin states. PORTC cannot be modified. Bit Bit Name Initial Value 7 PC7 Undefined* R 6 PC6 Undefined* R 5 PC5 Undefined* R 4 PC4 Undefined* R 3 PC3 Undefined* R 2 PC2 Undefined* R 1 PC1 Undefined* R 0 PC0 Undefined* R Note: 7.6.4 * R/W Description If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin states are read. Determined by the states of pins PC7 to PC0. Port C Open Drain Control Register (PCODR) PCODR selects the output type of port C. Bit Bit Name Initial Value R/W Description 7 PC7ODR 0 R/W 6 PC6ODR 0 R/W 5 PC5ODR 0 R/W Setting this bit to 1 turns off the PMOS of the corresponding pin, and if the pin function is specified to output, makes it an open-drain output pin, while clearing this bit to 0 makes it a push-pull output pin. 4 PC4ODR 0 R/W 3 PC3ODR 0 R/W 2 PC2ODR 0 R/W 1 PC1ODR 0 R/W 0 PC0ODR 0 R/W Rev. 2.00, 03/04, page 113 of 508 7.6.5 Pin Functions Port C pins also function as segment output pins of the LCD. The correspondence between the register specification and the pin functions is shown below. * PC7/SEG12, PC6/SEG11, PC5/SEG10, PC4/SEG9 The pin function is switched as shown below according to the combination of bits SGS3 to SGS0 in LPCR of the LCD and bit PCnDDR. SGS3 to SGS0 PCnDDR Pin function 0000 to 0011 Other than 0000 to 0011 0 1 -- PC7 to PC4 input PC7 to PC4 output SEG12 to SEG9 output n = 7 to 4 * PC3/SEG8, PC2/SEG7, PC1/SEG6, PC0/SEG5 The pin function is switched as shown below according to the combination of bits SGS3 to SGS0 in LPCR of the LCD and bit PCnDDR. SGS3 to SGS0 PCnDDR Pin function 0000 to 0100 Other than 0000 to 0100 0 1 -- PC3 to PC0 input PC3 to PC0 output SEG8 to SEG5 output n = 3 to 0 Rev. 2.00, 03/04, page 114 of 508 7.7 Port D Port D is a 4-bit I/O port that also has other functions. Port D has the following registers. * Port D data direction register (PDDDR) * Port D data register (PDDR) * Port D register (PORTD) 7.7.1 Port D Data Direction Register (PDDDR) The individual bits of PDDDR specify input or output for the pins of port D. Bit Bit Name Initial Value R/W Description 7 PD7DDR 0 W 6 PD6DDR 0 W 5 PD5DDR 0 W When a pin function is specified to a general I/O port, setting this bit to 1 makes the corresponding port 1 pin an output pin, while clearing this bit to 0 makes the pin an input pin. 4 PD4DDR 0 W Undefined -- 3 to 0 -- Reserved These bits will return undefined values if read. 7.7.2 Port D Data Register (PDDR) PDDR stores output data for the port D pins. Bit Bit Name Initial Value R/W Description 7 PD7DR 0 R/W 6 PD6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general I/O port. 5 PD5DR 0 R/W 4 PD4DR 0 R/W Undefined -- 3 to 0 -- Reserved These bits will return undefined values if read. Rev. 2.00, 03/04, page 115 of 508 7.7.3 Port D Register (PORTD) PORTD shows port D pin states. PORTD cannot be modified. Bit Bit Name Initial Value 7 PD7 Undefined* R 6 PD6 Undefined* R 5 PD5 Undefined* R 4 PD4 Undefined* R 3 to 0 -- R/W Undefined Description If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed while PDDDR bits are cleared to 0, the pin states are read. -- Reserved These bits will return undefined values if read. Note: 7.7.4 * Determined by the states of pins PD7 to PD4. Pin Functions Port D pins also function as segment output pins of the LCD. The correspondence between the register specification and the pin functions is shown below. * PD7/SEG4, PD6/SEG3, PD5/SEG2, PD4/SEG1 The pin function is switched as shown below according to the combination of bits SGS3 to SGS0 in LPCR of the LCD and bit PDnDDR. SGS3 to SGS0 PDnDDR Pin function Other than 0110 0110 0 1 -- PD7 to PD4 input PD7 to PD4 output SEG4 to SEG1 output n = 7 to 4 Rev. 2.00, 03/04, page 116 of 508 7.8 Port F Port F is an 8-bit I/O port that also has other functions. Port F has the following registers. * Port F data direction register (PFDDR) * Port F data register (PFDR) * Port F register (PORTF) 7.8.1 Port F Data Direction Register (PFDDR) The individual bits of PFDDR specify input or output for the pins of port F. Bit Bit Name Initial Value R/W Description 7 PF7DDR 0 W When the pin function is specified to a general I/O port, setting this bit to 1 makes the PF7 pin the output pin, while clearing this bit to 0 makes the pin an input pin. 6 PF6DDR 0 W 5 PF5DDR 0 W 4 PF4DDR 0 W When a pin function is specified to a general I/O port, setting this bit to 1 makes the corresponding port F pin an output pin, while clearing this bit to 0 makes the pin an input pin. 3 PF3DDR 0 W 2 PF2DDR 0 W 1, 0 -- Undefined -- Reserved These bits will return undefined values if read. Rev. 2.00, 03/04, page 117 of 508 7.8.2 Port F Data Register (PFDR) PFDR stores output data for the port F pins. Bit Bit Name Initial Value R/W Description 7 -- 0 R/W Reserved Only 0 should be written to this bit. 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1, 0 -- Undefined -- Output data for a pin is stored when the pin function is specified to a general I/O port. Reserved These bits will return undefined values if read. 7.8.3 Port F Register (PORTF) PORTF shows port F pin states. PORTF cannot be modified. Bit Bit Name Initial Value R/W 7 PF7 Undefined* R 6 PF6 Undefined* R 5 PF5 Undefined* R 4 PF4 Undefined* R 3 PF3 Undefined* R 2 PF2 Undefined* R 1, 0 -- Undefined -- Description If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while PFDDR bits are cleared to 0, the pin states are read. Reserved These bits will return undefined values if read. Note: * Determined by the states of pins PF7 to PF2. Rev. 2.00, 03/04, page 118 of 508 7.8.4 Pin Functions Port F pins also function as an external interrupt input pin, an A/D converter start trigger input pin, segment output pins of the LCD, and a system clock output pin. The correspondence between the register specification and the pin functions is shown below. * PF7/ The pin function is switched as shown below according to bit PF7DDR. PF7DDR Pin function 0 1 PF7 input output * PF6/SEG24 The pin function is switched as shown below according to the combination of bits SGS3 to SGS0 in LPCR of the LCD and bit PF6DDR. SGS3 to SGS0 PF6DDR Pin function 0000 Other than 0000 0 1 -- PF6 input PF6 output SEG24 output * PF5/SEG23 The pin function is switched as shown below according to the combination of bits SGS3 to SGS0 in LPCR of the LCD and bit PF5DDR. SGS3 to SGS0 PF5DDR Pin function 0000 Other than 0000 0 1 -- PF5 input PF5 output SEG23 output * PF4/SEG22 The pin function is switched as shown below according to the combination of bits SGS3 to SGS0 in LPCR of the LCD and bit PF4DDR. SGS3 to SGS0 PF4DDR Pin function 0000 Other than 0000 0 1 -- PF4 input PF4 output SEG22 output Rev. 2.00, 03/04, page 119 of 508 * PF3/ADTRG/IRQ3 The pin function is switched as shown below according to the combination of bits TRGS1 and TRGS0 in ADCR of the A/D converter and bit PF3DDR. PF3DDR Pin function 0 1 PF3 input PF3 output ADTRG input* IRQ3 input Note: When TRGS1 = 1 and TRGS0 = 1, it becomes ADTRG input. * PF2/SEG21 The pin function is switched as shown below according to the combination of bits SGS3 to SGS0 in LPCR of the LCD and bit PF2DDR. SGS3 to SGS0 PF2DDR Pin function 0000 Other than 0000 0 1 -- PF2 input PF2 output SEG21 output Rev. 2.00, 03/04, page 120 of 508 7.9 Port H Port H is an 8-bit I/O port that also has other functions. Port H has the following registers. * Port H data direction register (PHDDR) * Port H data register (PHDR) * Port H register (PORTH) 7.9.1 Port H Data Direction Register (PHDDR) The individual bits of PHDDR specify input or output for the pins of port H. Bit Bit Name Initial Value R/W Description 7 PH7DDR 0 W 6 PH6DDR 0 W 5 PH5DDR 0 W When a pin function is specified to a general I/O port, setting this bit to 1 makes the corresponding port 1 pin an output pin, while clearing this bit to 0 makes the pin an input pin. 4 PH4DDR 0 W 3 PH3DDR 0 W 2 PH2DDR 0 W 1 PH1DDR 0 W 0 PH0DDR 0 W 7.9.2 Port H Data Register (PHDR) PHDR stores output data for the port H pins. Bit Bit Name Initial Value R/W Description 7 PH7DR 0 R/W 6 PH6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general I/O port. 5 PH5DR 0 R/W 4 PH4DR 0 R/W 3 PH3DR 0 R/W 2 PH2DR 0 R/W 1 PH1DR 0 R/W 0 PH0DR 0 R/W Rev. 2.00, 03/04, page 121 of 508 7.9.3 Port H Register (PORTH) PORTH shows port H pin states. PORTH cannot be modified. Bit Bit Name Initial Value 7 PH7 Undefined* R 6 PH6 Undefined* R 5 PH5 Undefined* R 4 PH4 Undefined* R 3 PH3 Undefined* R 2 PH2 Undefined* R 1 PH1 Undefined* R 0 PH0 Undefined* R Note: 7.9.4 * R/W Description If a port H read is performed while PHDDR bits are set to 1, the PHDR values are read. If a port H read is performed while PHDDR bits are cleared to 0, the pin states are read. Determined by the states of pins PH7 to PH0. Pin Functions Port H pins also function as the PWM_1 output pins. The correspondence between the register specification and the pin functions is shown below. * PH7/PWM1H The pin function is switched as shown below according to the combination of bit OE1H in PWOCR_1 of PWM_1 and bit PH7DDR. OE1H PH7DDR Pin function 0 1 0 1 -- PH7 input PH7 output PWM1H output * PH6/PWM1G The pin function is switched as shown below according to the combination of bit OE1G in PWOCR_1 of PWM_1 and bit PH6DDR. OE1G PH6DDR Pin function 0 1 0 1 -- PH6 input PH6 output PWM1G output Rev. 2.00, 03/04, page 122 of 508 * PH5/PWM1F The pin function is switched as shown below according to the combination of bit OE1F in PWOCR_1 of PWM_1 and bit PH5DDR. OE1F PH5DDR Pin function 0 1 0 1 -- PH5 input PH5 output PWM1F output * PH4/PWM1E The pin function is switched as shown below according to the combination of bit OE1E in PWOCR_1 of PWM_1 and bit PH4DDR. OE1E PH4DDR Pin function 0 1 0 1 -- PH4 input PH4 output PWM1E output * PH3/PWM1D The pin function is switched as shown below according to the combination of bit OE1D in PWOCR_1 of PWM_1 and bit PH3DDR. OE1D PH3DDR Pin function 0 1 0 1 -- PH3 input PH3 output PWM1D output * PH2/PWM1C The pin function is switched as shown below according to the combination of bit OE1C in PWOCR_1 of PWM_1 and bit PH2DDR. OE1C PH2DDR Pin function 0 1 0 1 -- PH2 input PH2 output PWM1C output Rev. 2.00, 03/04, page 123 of 508 * PH1/PWM1B The pin function is switched as shown below according to the combination of bit OE1B in PWOCR_1 of PWM_1 and bit PH1DDR. OE1B PH1DDR Pin function 0 1 0 1 -- PH1 input PH1 output PWM1B output * PH0/PWM1A The pin function is switched as shown below according to the combination of bit OE1A in PWOCR_1 of PWM_1 and bit PH0DDR. OE1A PH0DDR Pin function 0 1 0 1 -- PH0 input PH0 output PWM1A output Rev. 2.00, 03/04, page 124 of 508 7.10 Port J Port J is an 8-bit I/O port that also has other functions. Port J has the following registers. * Port J data direction register (PJDDR) * Port J data register (PJDR) * Port J register (PORTJ) 7.10.1 Port J Data Direction Register (PJDDR) The individual bits of PJDDR specify input or output for the pins of port J. Bit Bit Name Initial Value R/W Description 7 PJ7DDR 0 W 6 PJ6DDR 0 W 5 PJ5DDR 0 W When a pin function is specified to a general I/O port, setting this bit to 1 makes the corresponding port 1 pin an output pin, while clearing this bit to 0 makes the pin an input pin. 4 PJ4DDR 0 W 3 PJ3DDR 0 W 2 PJ2DDR 0 W 1 PJ1DDR 0 W 0 PJ0DDR 0 W 7.10.2 Port J Data Register (PJDR) PJDR stores output data for the port J pins. Bit Bit Name Initial Value R/W Description 7 PJ7DR 0 R/W 6 PJ6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general I/O port. 5 PJ5DR 0 R/W 4 PJ4DR 0 R/W 3 PJ3DR 0 R/W 2 PJ2DR 0 R/W 1 PJ1DR 0 R/W 0 PJ0DR 0 R/W Rev. 2.00, 03/04, page 125 of 508 7.10.3 Port J Register (PORTJ) PORTJ shows port J pin states. PORTJ cannot be modified. Bit Bit Name Initial Value 7 PJ7 Undefined* R 6 PJ6 Undefined* R 5 PJ5 Undefined* R 4 PJ4 Undefined* R 3 PJ3 Undefined* R 2 PJ2 Undefined* R 1 PJ1 Undefined* R 0 PJ0 Undefined* R Note: * 7.10.4 R/W Description If a port J read is performed while PJDDR bits are set to 1, the PJDR values are read. If a port J read is performed while PJDDR bits are cleared to 0, the pin states are read. Determined by the states of pins PJ7 to PJ0. Pin Functions Port J pins also function as the PWM_2 output pins. The correspondence between the register specification and the pin functions is shown below. * PJ7/PWM2H The pin function is switched as shown below according to the combination of bit OE2H in PWOCR_2 of PWM_2 and bit PJ7DDR. OE2H PJ7DDR Pin function 0 1 0 1 -- PJ7 input PJ7 output PWM2H output * PJ6/PWM2G The pin function is switched as shown below according to the combination of bit OE2G in PWOCR_2 of PWM_2 and bit PJ6DDR. OE2G PJ6DDR Pin function 0 1 0 1 -- PJ6 input PJ6 output PWM2G output Rev. 2.00, 03/04, page 126 of 508 * PJ5/PWM2F The pin function is switched as shown below according to the combination of bit OE2F in PWOCR_2 of PWM_2 and bit PJ5DDR. OE2F PJ5DDR Pin function 0 1 0 1 -- PJ5 input PJ5 output PWM2F output * PJ4/PWM2E The pin function is switched as shown below according to the combination of bit OE2E in PWOCR_2 of PWM_2 and bit PJ4DDR. OE2E PJ4DDR Pin function 0 1 0 1 -- PJ4 input PJ4 output PWM2E output * PJ3/PWM2D The pin function is switched as shown below according to the combination of bit OE2D in PWOCR_2 of PWM_2 and bit PJ3DDR. OE2D PJ3DDR Pin function 0 1 0 1 -- PJ3 input PJ3 output PWM2D output * PJ2/PWM2C The pin function is switched as shown below according to the combination of bit OE2C in PWOCR_2 of PWM_2 and bit PJ2DDR. OE2C PJ2DDR Pin function 0 1 0 1 -- PJ2 input PJ2 output PWM2C output Rev. 2.00, 03/04, page 127 of 508 * PJ1/PWM2B The pin function is switched as shown below according to the combination of bit OE2B in PWOCR_2 of PWM_2 and bit PJ1DDR. OE2B PJ1DDR Pin function 0 1 0 1 -- PJ1 input PJ1 output PWM2B output * PJ0/PWM2A The pin function is switched as shown below according to the combination of bit OE2A in PWOCR_2 of PWM_2 and bit PJ0DDR. OE2A PJ0DDR Pin function 0 1 0 1 -- PJ0 input PJ0 output PWM2A output Rev. 2.00, 03/04, page 128 of 508 7.11 Pin Switch Function The upper or lower 4 bits of port H and port J are switched according to the combination of the TRPB and TRPA bits in TRPRT. 7.11.1 Transport Register (TRPRT) TRPRT specifies the switch of pin functions in port H and port J by the combination of the TRPB and TRPA bits. Bit Bit Name Initial Value 7 to 2 -- Undefined -- R/W Description Reserved These bits will return undefined values if read. 1 TRPB 0 R/W 0 TRPA 0 R/W The pin functions in ports H and J are switched as shown below according to the combination of the TRPB and TRPA bits. 00: Initial value 01: The pin functions of PH3 to PH0 are switched to those of PJ3 to PJ0. 10: The pin functions of PH7 to PH4 are switched to those of PJ7 to PJ4. 11: The pin functions of PH7 to PH4 and PH3 to PH0 are switched to those of PJ7 to PJ4 and PJ3 to PJ0, respectively. 7.11.2 Reading of Port Registers by Switching the Pin In reading PORTH and PORTJ, the pins to be read will differ by the TRPB and TRPA bits in TRPRT. Table 7.2 lists the pins of registers to be read by switching the pins. For the status of the pins to be read in PORTH and PORTJ, see section 7.9.3, Port H Register (PORTH), and section 7.10.3, Port J Register (PORTJ). Set TRPRT before writing to data direction registers (PHDDR and PJDDR) and data registers (PHDR and PJDR). Rev. 2.00, 03/04, page 129 of 508 Table 7.2 Pins of Registers to be Read and PWM Output by Switching Pins TRPB TRPA Port H Pin No. Pin State 0 Read Data Pin No. Pin State Read Data Pin No. Pin State 44 43 40 39 38 37 Pin No. Pin State 56 55 54 53 50 49 48 47 PJ7 input/ PJ6 input/ PJ5 input/ PJ4 input/ PJ3 input/ PJ2 input/ PJ1 input/ PJ0 input/ PWM2H/ PWM2G/ PWM2F/ PWM2E/ PWM2D/ PWM2C/ PWM2B/ PWM2A/ PJDR7 PJDR6 PJDR5 PJDR4 PJDR3 PJDR2 PJDR1 PJDR0 7 6 5 4 3 2 1 0 PH7 input/ PH6 input/ PH5 input/ PH4 input/ PH3 input/ PH2 input/ PH1 input/ PH0 input/ PWM1H/ PWM1G/ PWM1F/ PWM1E/ PWM1D/ PWM1C/ PWM1B/ PWM1A/ PHDR7 PHDR6 PHDR5 PHDR4 PHDR3 PHDR2 PHDR1 PHDR0 46 45 44 43 40 39 38 37 PH7 input/ PH6 input/ PH5 input/ PH4 input/ PH3 input/ PH2 input/ PH1 input/ PH0 input/ PWM1H/ PWM1G/ PWM1F/ PWM1E/ PWM2D/ PWM2C/ PWM2B/ PWM2A/ PHDR7 PHDR6 PHDR5 PHDR4 PJDR3 PJDR2 PJDR1 PJDR0 Bit Read Data Pin No. Pin State 7 6 5 4 3 2 1 0 PJ7 input/ PJ6 input/ PJ5 input/ PJ4 input/ PJ3 input/ PJ2 input/ PJ1 input/ PJ0 input/ PWM2H/ PWM2G/ PWM2F/ PWM2E/ PWM2D/ PWM2C/ PWM2B/ PWM2A/ PJDR7 PJDR6 PJDR5 PJDR4 PJDR3 PJDR2 PJDR1 PJDR0 56 55 54 53 50 49 48 47 PJ7 input/ PJ6 input/ PJ5 input/ PJ4 input/ PJ3 input/ PJ2 input/ PJ1 input/ PJ0 input/ PWM2H/ PWM2G/ PWM2F/ PWM2E/ PWM1D/ PWM1C/ PWM1B/ PWM1A/ PJDR7 PJDR6 PJDR5 PJDR4 PHDR3 PHDR2 PHDR1 PHDR0 7 6 5 4 3 2 1 0 PH7 input/ PH6 input/ PH5 input/ PH4 input/ PJ3 input/ PJ2 input/ PJ1 input/ PJ0 input/ PWM1H/ PWM1G/ PWM1F/ PWM1E/ PWM1D/ PWM1C/ PWM1B/ PWM1A/ PHDR7 PHDR6 PHDR5 PHDR4 PHDR3 PHDR2 PHDR1 PHDR0 46 45 44 43 40 39 38 37 PH7 input/ PH6 input/ PH5 input/ PH4 input/ PH3 input/ PH2 input/ PH1 input/ PH0 input/ PWM2H/ PWM2G/ PWM2F/ PWM2E/ PWM1D/ PWM1C/ PWM1B/ PWM1A/ PJDR7 PJDR6 PJDR5 PJDR4 PHDR3 PHDR2 PHDR1 PHDR0 Bit Read Data Pin No. Pin State 7 6 5 4 3 2 1 0 PJ7 input/ PJ6 input/ PJ5 input/ PJ4 input/ PH3 input/ PH2 input/ PH1 input/ PH0 input/ PWM2H/ PWM2G/ PWM2F/ PWM2E/ PWM2D/ PWM2C/ PWM2B/ PWM2A/ PJDR7 PJDR6 PJDR5 PJDR4 PJDR3 PJDR2 PJDR1 PJDR0 56 55 54 53 50 49 48 47 PJ7 input/ PJ6 input/ PJ5 input/ PJ4 input/ PJ3 input/ PJ2 input/ PJ1 input/ PJ0 input/ PWM1H/ PWM1G/ PWM1F/ PWM1E/ PWM2D/ PWM2C/ PWM2B/ PWM2A/ PHDR7 PHDR6 PHDR5 PHDR4 PJDR3 PJDR2 PJDR1 PJDR0 0 Bit Read Data Pin No. Pin State 1 45 1 Bit 1 46 PH7 input/ PH6 input/ PH5 input/ PH4 input/ PH3 input/ PH2 input/ PH1 input/ PH0 input/ PWM1H/ PWM1G/ PWM1F/ PWM1E/ PWM1D/ PWM1C/ PWM1B/ PWM1A/ PHDR7 PHDR6 PHDR5 PHDR4 PHDR3 PHDR2 PHDR1 PHDR0 0 Bit 0 Port J 7 6 5 4 3 2 1 0 PJ7 input/ PJ6 input/ PJ5 input/ PJ4 input/ PH3 input/ PH2 input/ PH1 input/ PH0 input/ PWM1H/ PWM1G/ PWM1F/ PWM1E/ PWM1D/ PWM1C/ PWM1B/ PWM1A/ PHDR7 PHDR6 PHDR5 PHDR4 PHDR3 PHDR2 PHDR1 PHDR0 46 45 44 43 40 39 38 37 PH7 input/ PH6 input/ PH5 input/ PH4 input/ PH3 input/ PH2 input/ PH1 input/ PH0 input/ PWM2H/ PWM2G/ PWM2F/ PWM2E/ PWM2D/ PWM2C/ PWM2B/ PWM2A/ PJDR0 PJDR1 PJDR2 PJDR3 PJDR4 PJDR5 PJDR6 PJDR7 Bit Read Data Pin No. Pin State 7 6 5 4 3 2 1 0 PH7 input/ PH6 input/ PH5 input/ PH4 input/ PJ3 input/ PJ2 input/ PJ1 input/ PJ0 input/ PWM2H/ PWM2G/ PWM2F/ PWM2E/ PWM2D/ PWM2C/ PWM2B/ PWM2A/ PJDR7 PJDR6 PJDR5 PJDR4 PJDR3 PJDR2 PJDR1 PJDR0 56 55 54 53 50 49 48 47 PJ7 input/ PJ6 input/ PJ5 input/ PJ4 input/ PJ3 input/ PJ2 input/ PJ1 input/ PJ0 input/ PWM1H/ PWM1G/ PWM1F/ PWM1E/ PWM1D/ PWM1C/ PWM1B/ PWM1A/ PHDR0 PHDR1 PHDR2 PHDR3 PHDR4 PHDR5 PHDR6 PHDR7 1 Bit Read Data 7 6 5 4 3 2 1 0 PJ7 input/ PJ6 input/ PJ5 input/ PJ4 input/ PJ3 input/ PJ2 input/ PJ1 input/ PJ0 input/ PWM1H/ PWM1G/ PWM1F/ PWM1E/ PWM1D/ PWM1C/ PWM1B/ PWM1A/ PHDR7 PHDR6 PHDR5 PHDR4 PHDR3 PHDR2 PHDR1 PHDR0 Rev. 2.00, 03/04, page 130 of 508 Bit Read Data 7 6 5 4 3 2 1 0 PH7 input/ PH6 input/ PH5 input/ PH4 input/ PH3 input/ PH2 input/ PH1 input/ PH0 input/ PWM2H/ PWM2G/ PWM2F/ PWM2E/ PWM2D/ PWM2C/ PWM2B/ PWM2A/ PJDR7 PJDR6 PJDR5 PJDR4 PJDR3 PJDR2 PJDR1 PJDR0 Section 8 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) comprised of three 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 8.1 and figure 8.1, respectively. 8.1 Features * Maximum 8-pulse input/output * Selection of 8 counter input clocks for each channel * The following operations can be set for each channel. Waveform output at compare match Input capture function Counter clear operation Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture is possible Register simultaneous input/output is possible by synchronous counter operation A maximum 7-phase PWM output is possible in combination with synchronous operation * Buffer operation settable for channel 0 * Phase counting mode settable independently for each of channels 1 and 2 * Fast access via internal 16-bit bus * 13 interrupt sources * A/D converter conversion start trigger can be generated * Module stop mode can be set TIMTPU4A_000020020200 Rev. 2.00, 03/04, page 131 of 508 Table 8.1 TPU Functions (1) Item Channel 0 Channel 1 Channel 2 Count clock /1 /4 /16 /64 TCLKA TCLKB TCLKC TCLKD /1 /4 /16 /64 /256 TCLKA TCLKB /1 /4 /16 /64 /1024 TCLKA TCLKB TCLKC General registers TGRA_0 TGRB_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 General registers/ buffer registers TGRC_0 TGRD_0 I/O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Counter clear function TGR compare match or TGR compare match or TGR compare match or input capture input capture input capture Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation Rev. 2.00, 03/04, page 132 of 508 Table 8.1 TPU Functions (2) Item Channel 0 Channel 1 Channel 2 A/D converter trigger TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture Interrupt sources 5 sources 4 sources 4 sources * Compare match or input capture 0A * Compare match or input capture 1A * Compare match or input capture 2A * Compare match or input capture 0B * Compare match or input capture 1B * Compare match or input capture 2B * Compare match or input capture 0C * Overflow * Overflow * Underflow * Underflow * Compare match or input capture 0D * Overflow [Legend] : Possible --: Not possible Rev. 2.00, 03/04, page 133 of 508 TGRB TCNT A/D converter convertion start signal TGRD TGRB TGRB TGRC TCNT TGRA TCNT Interrupt request signals TGRA Module data bus TGRA TSTR Bus interface Internal data bus TSR TIER TSR TIER TSR TIER TIOR TIOR TIORH TIORL Common Control logic TMDR Channel 2 TCR TMDR Channel 1 TCR Channel 2: Channel 0 Channel 1: TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Control logic for channel 0 to 2 Channel 0: TMDR Input/output pins TCR External clock: /1 /4 /16 /64 /256 /1024 TCLKA TCLKB TCLKC TCLKD TSYR Clock input Internal clock: [Legend] TSTR: TSYR: TCR: TMDR: Timer start register Timer synchro register Timer control register Timer mode register TIOR(H, L): TIER: TSR: TGR(A, B, C, D): Timer I/O control registers (H, L) Timer interrupt enable register Timer status register TImer general registers (A, B, C, D) Figure 8.1 Block Diagram of TPU Rev. 2.00, 03/04, page 134 of 508 Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U 8.2 Table 8.2 Input/Output Pins Pin Configuration Channel Symbol I/O All TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 phase counting mode B phase input) TCLKC Input External clock C input pin (Channel 2 phase counting mode A phase input) TCLKD Input External clock D input pin (Channel 2 phase counting mode B phase input) TIOCA0 I/O TGRA_0 input capture input/output compare output/PWM output pin TIOCB0 I/O TGRB_0 input capture input/output compare output/PWM output pin TIOCC0 I/O TGRC_0 input capture input/output compare output/PWM output pin TIOCD0 I/O TGRD_0 input capture input/output compare output/PWM output pin TIOCA1 I/O TGRA_1 input capture input/output compare output/PWM output pin TIOCB1 I/O TGRB_1 input capture input/output compare output/PWM output pin TIOCA2 I/O TGRA_2 input capture input/output compare output/PWM output pin TIOCB2 I/O TGRB_2 input capture input/output compare output/PWM output pin 0 1 2 Function Rev. 2.00, 03/04, page 135 of 508 8.3 Register Descriptions The TPU has the following registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. * * * * * * * * * * * * * * * * * * * * * * * * * * * Timer control register_0 (TCR_0) Timer mode register_0 (TMDR_0) Timer I/O control register H_0 (TIORH_0) Timer I/O control register L_0 (TIORL_0) Timer interrupt enable register_0 (TIER_0) Timer status register_0 (TSR_0) Timer counter_0 (TCNT_0) Timer general register A_0 (TGRA_0) Timer general register B_0 (TGRB_0) Timer general register C_0 (TGRC_0) Timer general register D_0 (TGRD_0) Timer control register_1 (TCR_1) Timer mode register_1 (TMDR_1) Timer I/O control register _1 (TIOR_1) Timer interrupt enable register_1 (TIER_1) Timer status register_1 (TSR_1) Timer counter_1 (TCNT_1) Timer general register A_1 (TGRA_1) Timer general register B_1 (TGRB_1) Timer control register_2 (TCR_2) Timer mode register_2 (TMDR_2) Timer I/O control register_2 (TIOR_2) Timer interrupt enable register_2 (TIER_2) Timer status register_2 (TSR_2) Timer counter_2 (TCNT_2) Timer general register A_2 (TGRA_2) Timer general register B_2 (TGRB_2) Common Registers * Timer start register (TSTR) * Timer synchro register (TSYR) Rev. 2.00, 03/04, page 136 of 508 8.3.1 Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The TPU has a total of three TCR registers, one for each channel. TCR register settings should be conducted only when TCNT operation is stopped. Bit Bit Name Initial value R/W Description 7 CCLR2 0 R/W Counter Clear 0 to 2 6 CCLR1 0 R/W 5 CCLR0 0 R/W These bits select the TCNT counter clearing source. See tables 8.3 and 8.4 for details. 4 CKEG1 0 R/W Clock Edge 0 and 1 3 CKEG0 0 R/W These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). If phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is /4 or slower. This setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected. 00: Count at rising edge 01: Count at falling edge 1X: Count at both edges 2 TPSC2 0 R/W Time Prescaler 0 to 2 1 TPSC1 0 R/W 0 TPSC0 0 R/W These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 8.5 to 8.7 for details. [Legend] X: Don't care Rev. 2.00, 03/04, page 137 of 508 Table 8.3 CCLR0 to CCLR2 (Channel 0) Channel Bit 7 CCLR2 Bit 6 CCLR1 Bit 5 CCLR0 Description 0 0 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 0 TCNT clearing disabled 1 TCNT cleared by TGRC compare match/input 2 capture* 0 TCNT cleared by TGRD compare match/input capture*2 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1 1 1 0 1 Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 8.4 CCLR0 to CCLR2 (Channels 1 and 2) Channel Bit 7 Bit 6 Reserved*2 CCLR1 Bit 5 CCLR0 Description 1, 2 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1 0 1 Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified. Rev. 2.00, 03/04, page 138 of 508 Table 8.5 TPSC0 to TPSC2 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on /1 1 Internal clock: counts on /4 0 Internal clock: counts on /16 1 Internal clock: counts on /64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input 1 1 0 1 Table 8.6 TPSC0 to TPSC2 (Channel 1) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 1 0 0 0 Internal clock: counts on /1 1 Internal clock: counts on /4 1 1 0 1 0 Internal clock: counts on /16 1 Internal clock: counts on /64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 Internal clock: counts on /256 1 Setting prohibited Note: This setting is ignored when channel 1 is in phase counting mode. Rev. 2.00, 03/04, page 139 of 508 Table 8.7 TPSC0 to TPSC2 (Channel 2) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 2 0 0 0 Internal clock: counts on /1 1 Internal clock: counts on /4 0 Internal clock: counts on /16 1 Internal clock: counts on /64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 Internal clock: counts on /1024 1 1 0 1 Note: This setting is ignored when channel 2 is in phase counting mode. 8.3.2 Timer Mode Register (TMDR) The TMDR registers are used to set the operating mode of each channel. The TPU has three TMDR registers, one for each channel. TMDR register settings should be changed only when TCNT operation is stopped. Bit Bit Name Initial value R/W Description 7, 6 All 1 Reserved These bits are always read as 1 and cannot be modified. 5 BFB 0 R/W Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation Rev. 2.00, 03/04, page 140 of 508 Bit Bit Name Initial value R/W Description 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation 3 MD3 0 R/W Modes 0 to 3 2 MD2 0 R/W These bits are used to set the timer operating mode. 1 MD1 0 R/W 0 MD0 0 R/W MD3 is a reserved bit. In a write, it should always be written with 0. See table 8.8 for details. Table 8.8 MD0 to MD3 Bit 3 MD3*1 Bit 2 MD2*2 Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 1 1 0 1 1 X X 0 Phase counting mode 3 1 Phase counting mode 4 X [Legend] X: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channel 0. In this case, 0 should always be written to MD2. Rev. 2.00, 03/04, page 141 of 508 8.3.3 Timer I/O Control Register (TIOR) The TIOR registers control the TGR registers. The TPU has four TIOR registers, two for channel 0, and one each for channels 1 and 2. Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. * TIORH_0, TIOR_1, TIOR_2 Bit Bit Name Initial value R/W Description 7 IOB3 0 R/W I/O Control B0 to B3 6 IOB2 0 R/W Specify the function of TGRB. 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W I/O Control A0 to A3 2 IOA2 0 R/W Specify the function of TGRA. 1 IOA1 0 R/W 0 IOA0 0 R/W * TIORL_0 Bit Bit Name Initial value R/W Description 7 IOD3 0 R/W I/O Control D0 to D3 6 IOD2 0 R/W Specify the function of TGRD. 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W I/O Control C0 to C3 2 IOC2 0 R/W Specify the function of TGRC. 1 IOC1 0 R/W 0 IOC0 0 R/W Rev. 2.00, 03/04, page 142 of 508 Table 8.9 TIORH_0 Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_0 Function 0 0 0 0 Output compare register 1 TIOCB0 Pin Function Output disabled Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 1 Output disabled Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 [Legend] X: Note: * 1 Input capture Input capture at rising edge register Input capture at falling edge 1 X Input capture at both edges X X Capture input source is channel 1/count clock Input capture at TCNT_1 count- up/count-down* 0 0 Don't care When bits TPSC0 to TPSC2 in TCR_1 are set to B'000 and /1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. Rev. 2.00, 03/04, page 143 of 508 Table 8.10 TIORL_0 Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_0 Function 0 0 0 0 Output compare register*2 1 TIOCD0 Pin Function Output disabled Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 1 Output disabled Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture Capture input source is TIOCD0 pin register*2 Input capture at rising edge 1 Capture input source is TIOCD0 pin Input capture at falling edge 1 X Capture input source is TIOCD0 pin Input capture at both edges 1 X X Capture input source is channel 1/count clock 1 Input capture at TCNT_1 count-up/count-down* [Legend] X: Don't care Notes: 1. When bits TPSC0 to TPSC2 in TCR_1 are set to B'000 and /1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 2.00, 03/04, page 144 of 508 Table 8.11 TIOR_1 Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_1 Function 0 0 0 0 Output compare register 1 TIOCB1 Pin Function Output disabled Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 1 Output disabled Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture Capture input source is TIOCB1 pin register Input capture at rising edge 1 Capture input source is TIOCB1 pin Input capture at falling edge 1 X Capture input source is TIOCB1 pin Input capture at both edges 1 X X TGRC_0 compare match/ input capture Input capture at generation of TGRC_0 compare match/input capture [Legend] X: Don't care Rev. 2.00, 03/04, page 145 of 508 Table 8.12 TIOR_2 Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_2 Function 0 0 0 0 Output compare register 1 TIOCB2 Pin Function Output disabled Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 1 Output disabled Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 Input capture Capture input source is TIOCB2 pin register Input capture at rising edge 1 Capture input source is TIOCB2 pin Input capture at falling edge 1 X Capture input source is TIOCB2 pin Input capture at both edges [Legend] X: Don't care Rev. 2.00, 03/04, page 146 of 508 Table 8.13 TIORH_0 Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_0 Function 0 0 0 0 Output compare register 1 TIOCA0 Pin Function Output disabled Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 1 Output disabled Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture Capture input source is TIOCA0 pin register Input capture at rising edge 1 Capture input source is TIOCA0 pin Input capture at falling edge 1 X Capture input source is TIOCA0 pin Input capture at both edges 1 X X Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Rev. 2.00, 03/04, page 147 of 508 Table 8.14 TIORL_0 Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_0 Function 0 0 0 0 Output compare register* 1 TIOCC0 Pin Function Output disabled Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 1 Output disabled Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture Capture input source is TIOCC0 pin register* Input capture at rising edge 1 Capture input source is TIOCC0 pin Input capture at falling edge 1 X Capture input source is TIOCC0 pin Input capture at both edges 1 X X Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 2.00, 03/04, page 148 of 508 Table 8.15 TIOR_1 Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_1 Function 0 0 0 0 Output compare register 1 TIOCA1 Pin Function Output disabled Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 1 Output disabled Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture Capture input source is TIOCA1 pin register Input capture at rising edge 1 Capture input source is TIOCA1 pin Input capture at falling edge 1 X Capture input source is TIOCA1 pin Input capture at both edges 1 X X Capture input source is TGRA_0 compare match/input capture Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] X: Don't care Rev. 2.00, 03/04, page 149 of 508 Table 8.16 TIOR_2 Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_2 Function 0 0 0 0 Output compare register 1 TIOCA2 Pin Function Output disabled Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 1 Output disabled Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 Input capture Capture input source is TIOCA2 pin register Input capture at rising edge 1 Capture input source is TIOCA2 pin Input capture at falling edge 1 X Capture input source is TIOCA2 pin Input capture at both edges [Legend] X: Don't care Rev. 2.00, 03/04, page 150 of 508 8.3.4 Timer Interrupt Enable Register (TIER) The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has three TIER registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TTGE 0 R/W A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 1 Reserved This bit is always read as 1 and cannot be modified. 5 TCIEU 0 R/W Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channel 0. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled Rev. 2.00, 03/04, page 151 of 508 Bit Bit Name Initial value R/W Description 2 TGIEC 0 R/W TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Rev. 2.00, 03/04, page 152 of 508 8.3.5 Timer Status Register (TSR) The TSR registers indicate the status of each channel. The TPU has three TSR registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TCFD 1 R Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1 and 2. In channel 0, bit 7 is reserved. It is always read as 1 and cannot be modified. 0: TCNT counts down 1: TCNT counts up 6 1 5 TCFU 0 R/(W)* Underflow Flag Reserved This bit is always read as 1 and cannot be modified. Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. Only 0 can be written, for flag clearing. In channel 0, bit 5 is reserved. It is always read as 0 and cannot be modified. [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 4 TCFV 0 R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 Rev. 2.00, 03/04, page 153 of 508 Bit Bit Name Initial value R/W 3 TGFD 0 R/(W)* Input Capture/Output Compare Flag D Description Status flag that indicates the occurrence of TGRD input capture or compare match in channel 0. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * When TCNT = TGRD and TGRD is functioning as output compare register * When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register [Clearing condition] * 2 TGFC 0 When 0 is written to TGFD after reading TGFD = 1 R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channel 0. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * When TCNT = TGRC and TGRC is functioning as output compare register * When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register [Clearing condition] * 1 TGFB 0 When 0 is written to TGFC after reading TGFC = 1 R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] * When TCNT = TGRB and TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register [Clearing condition] * Rev. 2.00, 03/04, page 154 of 508 When 0 is written to TGFB after reading TGFB = 1 Bit Bit Name Initial value R/W 0 TGFA 0 R/(W)* Input Capture/Output Compare Flag A Description Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions] * When TCNT = TGRA and TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register [Clearing condition] * Note: 8.3.6 * When 0 is written to TGFA after reading TGFA = 1 Only 0 can be written, for flag clearing. Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The TPU has three TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 8.3.7 Timer General Register (TGR) The TGR registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. The TPU has eight TGR registers, four for channel 0 and two each for channels 1 and 2. TGRC and TGRD for channel 0 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA--TGRC and TGRB-- TGRD. Rev. 2.00, 03/04, page 155 of 508 8.3.8 Timer Start Register (TSTR) TSTR selects operation/stoppage for channels 0 to 2. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit Bit Name Initial value R/W Description 7 to 3 All 0 Reserved Only 0 should be written to these bits. 2 CST2 1 CST1 These bits select operation or stoppage for TCNT. 0 CST0 If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0 R/W Counter Start 2 to 0 0: TCNT_2 to TCNT_0 count operation is stopped 1: TCNT_2 to TCNT_0 performs count operation Rev. 2.00, 03/04, page 156 of 508 8.3.9 Timer Synchro Register (TSYR) TSYR selects independent operation or synchronous operation for the channel 0 to 2 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Bit Name Initial value R/W Description 7 to 3 All 0 R/W Reserved Only 0 should be written to these bits. 2 SYNC2 1 SYNC1 0 SYNC0 0 R/W Timer Synchro 2 to 0 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_2 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_2 to TCNT_0 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible Rev. 2.00, 03/04, page 157 of 508 8.4 Operation 8.4.1 Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation: When one of bits CST0 to CST2 is set to 1 in TSTR, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. 1. Example of count operation setting procedure Figure 8.2 shows an example of the count operation setting procedure. Operation selection Select counter clock [1] Periodic counter Select counter clearing source Free-running counter [2] [3] Select output compare register Set period [4] Start count operation [5] <Periodic counter> Start count operation <Free-running counter> [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. [5] Set the CST bit in TSTR to 1 to start the counter operation. Figure 8.2 Example of Counter Operation Setting Procedure Rev. 2.00, 03/04, page 158 of 508 2. Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 8.3 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 8.3 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 8.4 illustrates periodic counter operation. Rev. 2.00, 03/04, page 159 of 508 Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software TGF Figure 8.4 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. 1. Example of setting procedure for waveform output by compare match Figure 8.5 shows an example of the setting procedure for waveform output by compare match Output selection Select waveform output mode [1] Set output timing [2] Start count operation [3] [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin unit the first compare match occurs. [2] Set the timing for compare match generation in TGR. [3] Set the CST bit in TSTR to 1 to start the count operation. <Waveform output> Figure 8.5 Example of Setting Procedure for Waveform Output by Compare Match Rev. 2.00, 03/04, page 160 of 508 2. Examples of waveform output operation Figure 8.6 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB Time H'0000 No change No change 1 output TIOCA TIOCB No change No change 0 output Figure 8.6 Example of 0 Output/1 Output Operation Figure 8.7 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA Time H'0000 Toggle output TIOCB Toggle output TIOCA Figure 8.7 Example of Toggle Output Operation Rev. 2.00, 03/04, page 161 of 508 Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channel 0, /1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if /1 is selected. 1. Example of input capture operation setting procedure Figure 8.8 shows an example of the input capture operation setting procedure. Input selection Select input capture input Start count [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation. [1] [2] <Input capture operation> Figure 8.8 Example of Input Capture Operation Setting Procedure Rev. 2.00, 03/04, page 162 of 508 2. Example of input capture operation Figure 8.9 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 Time H'0000 TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 8.9 Example of Input Capture Operation Rev. 2.00, 03/04, page 163 of 508 8.4.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 2 can all be designated for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 8.10 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Set TCNT Synchronous clearing [2] Clearing source generation channel? No Yes <Synchronous presetting> Select counter clearing source [3] Set synchronous counter clearing [4] Start count [4] Start count [5] <Counter clearing> <Synchronous clearing> [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 8.10 Example of Synchronous Operation Setting Procedure Rev. 2.00, 03/04, page 164 of 508 Example of Synchronous Operation: Figure 8.11 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details of PWM modes, see section 8.4.4, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 Time H'0000 TIOCA0 TIOCA1 TIOCA2 Figure 8.11 Example of Synchronous Operation Rev. 2.00, 03/04, page 165 of 508 8.4.3 Buffer Operation Buffer operation, provided for channel 0, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 8.17 shows the register combinations used in buffer operation. Table 8.17 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGRA_0 TGRC_0 TGRB_0 TGRD_0 * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 8.12. Compare match signal Timer general register Buffer register Comparator TCNT Figure 8.12 Compare Match Buffer Operation * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 8.13. Input capture signal Timer general register Buffer register Figure 8.13 Input Capture Buffer Operation Rev. 2.00, 03/04, page 166 of 508 TCNT Example of Buffer Operation Setting Procedure: Figure 8.14 shows an example of the buffer operation setting procedure. Buffer operation Select TGR function [1] Set buffer operation [2] Start count [3] [1] Designate TGR as an input capture register or output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation. <Buffer operation> Figure 8.14 Example of Buffer Operation Setting Procedure Examples of Buffer Operation 1. When TGR is an output compare register Figure 8.15 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time that compare match A occurs. For details of PWM modes, see section 8.4.4, PWM Modes. Rev. 2.00, 03/04, page 167 of 508 TCNT value TGRB_0 H'0520 H'0450 H'0200 TGRA_0 Time H'0000 TGRC_0 H'0200 H'0450 H'0520 Transfer TGRA_0 H'0200 H'0450 TIOCA Figure 8.15 Example of Buffer Operation (1) 2. When TGR is an input capture register Figure 8.16 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 TGRC H'0F07 H'09FB H'0532 H'0F07 Figure 8.16 Example of Buffer Operation (2) Rev. 2.00, 03/04, page 168 of 508 8.4.4 PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 4-phase PWM output is possible. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 7-phase PWM output is possible in combination use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 8.18. Rev. 2.00, 03/04, page 169 of 508 Table 8.18 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 0 TGRA_0 TIOCA0 TIOCA0 TGRB_0 TIOCB0 TGRC_0 TIOCC0 TIOCC0 TIOCA1 TIOCA1 TGRD_0 1 TIOCD0 TGRA_1 TGRB_1 2 TIOCB1 TGRA_2 TIOCA2 TGRB_2 TIOCA2 TIOCB2 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. Example of PWM Mode Setting Procedure: Figure 8.17 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] Select counter clearing source [2] Select waveform output level [3] Set TGR [4] Set PWM mode [5] Start count [6] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other the TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 start the count operation. <PWM mode> Figure 8.17 Example of PWM Mode Setting Procedure Rev. 2.00, 03/04, page 170 of 508 Examples of PWM Mode Operation: Figure 8.18 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers are used as the duty levels. TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 8.18 Example of PWM Mode Operation (1) Rev. 2.00, 03/04, page 171 of 508 Figure 8.19 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are used as the duty levels. Counter cleared by TGRB_1 compare match TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 8.19 Example of PWM Mode Operation (2) Rev. 2.00, 03/04, page 172 of 508 Figure 8.20 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB rewritten TGRB H'0000 Time 100% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB TGRB rewritten Time H'0000 TIOCA 100% duty 0% duty Figure 8.20 Example of PWM Mode Operation (3) Rev. 2.00, 03/04, page 173 of 508 8.4.5 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 8.19 shows the correspondence between external clock pins and channels. Table 8.19 Phase Counting Mode Clock Input Pins External Clock Pins Channels A-Phase B-Phase When channel 1 is set to phase counting mode TCLKA TCLKB When channel 2 is set to phase counting mode TCLKC TCLKD Example of Phase Counting Mode Setting Procedure: Figure 8.21 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Phase counting mode Select phase counting mode [1] Start count [2] <Phase counting mode> Figure 8.21 Example of Phase Counting Mode Setting Procedure Rev. 2.00, 03/04, page 174 of 508 Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 8.22 shows an example of phase counting mode 1 operation, and table 8.20 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 8.22 Example of Phase Counting Mode 1 Operation Table 8.20 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count High level Low level Low level High level High level Down-count Low level High level Low level [Legend] : Rising edge : Falling edge Rev. 2.00, 03/04, page 175 of 508 2. Phase counting mode 2 Figure 8.23 shows an example of phase counting mode 2 operation, and table 8.21 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 8.23 Example of Phase Counting Mode 2 Operation Table 8.21 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Don't care Low level Don't care Low level Don't care High level Up-count High level Don't care Low level Don't care [Legend] : Rising edge : Falling edge Rev. 2.00, 03/04, page 176 of 508 High level Don't care Low level Down-count 3. Phase counting mode 3 Figure 8.24 shows an example of phase counting mode 3 operation, and table 8.22 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 8.24 Example of Phase Counting Mode 3 Operation Table 8.22 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Don't care Low level Don't care Low level Don't care High level Up-count High level Down-count Low level Don't care High level Don't care Low level Don't care [Legend] : Rising edge : Falling edge Rev. 2.00, 03/04, page 177 of 508 4. Phase counting mode 4 Figure 8.25 shows an example of phase counting mode 4 operation, and table 8.23 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 8.25 Example of Phase Counting Mode 4 Operation Table 8.23 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count High level Low level Low level Don't care High level High level Down-count Low level High level Low level [Legend] : Rising edge : Falling edge Rev. 2.00, 03/04, page 178 of 508 Don't care Phase Counting Mode Application Example: Figure 8.26 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed. Rev. 2.00, 03/04, page 179 of 508 Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed period capture) TGRB_1 (speed period capture) TCNT_0 TGRA_0 (speed control period) + - TGRC_0 (position control period) + - TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 8.26 Phase Counting Mode Application Example Rev. 2.00, 03/04, page 180 of 508 8.5 Interrupts There are three kinds of TPU interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 8.24 lists the TPU interrupt sources. Table 8.24 TPU Interrupts Channel Name Interrupt Source Interrupt Flag 0 TGI0A TGRA_0 input capture/compare match TGFA0 TGI0B TGRB_0 input capture/compare match TGFB0 TGI0C TGRC_0 input capture/compare match TGFC0 TGI0D TGRD_0 input capture/compare match TGFD0 TCI0V TCNT_0 overflow TCFV0 1 2 TGI1A TGRA_1 input capture/compare match TGFA1 TGI1B TGRB_1 input capture/compare match TGFB1 TCI1V TCNT_1 overflow TCFV1 TCI1U TCNT_1 underflow TCFU1 TGI2A TGRA_2 input capture/compare match TGFA2 TGI2B TGRB_2 input capture/compare match TGFB2 TCI2V TCNT_2 overflow TCFV2 TCI2U TCNT_2 underflow TCFU2 Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. Rev. 2.00, 03/04, page 181 of 508 Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has eight input capture/compare match interrupts, four for channel 0, and two each for channels 1 and 2. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has three overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has two underflow interrupts, one each for channels 1 and 2. 8.6 A/D Converter Activation The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to begin A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is begun. In the TPU, a total of three TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. Rev. 2.00, 03/04, page 182 of 508 8.7 Operation Timing 8.7.1 Input/Output Timing TCNT Count Timing: Figure 8.27 shows TCNT count timing in internal clock operation, and figure 8.28 shows TCNT count timing in external clock operation. Falling edge Internal clock Rising edge TCNT input clock N-1 TCNT N N+1 N+2 Figure 8.27 Count Timing in Internal Clock Operation External clock Rising edge Falling edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 8.28 Count Timing in External Clock Operation Rev. 2.00, 03/04, page 183 of 508 Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 8.29 shows output compare output timing. TCNT input clock N TCNT N+1 N TGR Compare match signal TIOC pin Figure 8.29 Output Compare Output Timing Input Capture Signal Timing: Figure 8.30 shows input capture signal timing. Input capture input Input capture signal TCNT N N+1 N+2 N TGR Figure 8.30 Input Capture Input Signal Timing Rev. 2.00, 03/04, page 184 of 508 N+2 Timing for Counter Clearing by Compare Match/Input Capture: Figure 8.31 shows the timing when counter clearing on compare match is specified, and figure 8.32 shows the timing when counter clearing on input capture is specified. Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 8.31 Counter Clear Timing (Compare Match) Input capture signal Counter clear signal TCNT TGR N H'0000 N Figure 8.32 Counter Clear Timing (Input Capture) Rev. 2.00, 03/04, page 185 of 508 Buffer Operation Timing: Figures 8.33 and 8.34 show the timing in buffer operation. n TCNT n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 8.33 Buffer Operation Timing (Compare Match) Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 8.34 Buffer Operation Timing (Input Capture) Rev. 2.00, 03/04, page 186 of 508 8.7.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 8.35 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 8.35 TGI Interrupt Timing (Compare Match) TGF Flag Setting Timing in Case of Input Capture: Figure 8.36 shows the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing. Input capture signal TCNT TGR N N TGF flag TGI interrupt Figure 8.36 TGI Interrupt Timing (Input Capture) Rev. 2.00, 03/04, page 187 of 508 TCFV Flag/TCFU Flag Setting Timing: Figure 8.37 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 8.38 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing. TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 8.37 TCIV Interrupt Setting Timing TCNT input clock TCNT (underflow) H'0000 H'FFFF Underflow signal TCFU flag TCIU interrupt Figure 8.38 TCIU Interrupt Setting Timing Rev. 2.00, 03/04, page 188 of 508 Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figure 8.39 shows the timing for status flag clearing by the CPU. TSR write cycle T1 T2 Address TSR address Write signal Status flag Interrupt request signal Figure 8.39 Timing for Status Flag Clearing by CPU Rev. 2.00, 03/04, page 189 of 508 8.8 Usage Notes 8.8.1 Module Stop Mode Setting TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 19, Power-Down Modes. 8.8.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 8.40 shows the input clock conditions in phase counting mode. Overlap Phase Phase differdifferOverlap ence ence Pulse width Pulse width TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 8.40 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev. 2.00, 03/04, page 190 of 508 8.8.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= (N + 1) Where 8.8.4 f: Counter frequency : Operating frequency N: TGR set value Contention between TCNT Write and Clear Operations If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 8.41 shows the timing in this case. TCNT write cycle T2 T1 TCNT address Address Write signal Counter clear signal TCNT N H'0000 Figure 8.41 Contention between TCNT Write and Clear Operations Rev. 2.00, 03/04, page 191 of 508 8.8.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 8.42 shows the timing in this case. TCNT write cycle T2 T1 TCNT address Address Write signal TCNT input clock TCNT N M TCNT write data Figure 8.42 Contention between TCNT Write and Increment Operations Rev. 2.00, 03/04, page 192 of 508 8.8.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the previous value is written. Figure 8.43 shows the timing in this case. TGR write cycle T1 T2 TGR address Address Write signal Compare match signal Inhibited TCNT N N+1 TGR N M TGR write data Figure 8.43 Contention between TGR Write and Compare Match Rev. 2.00, 03/04, page 193 of 508 8.8.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation will be that in the buffer prior to the write. Figure 8.44 shows the timing in this case. TGR write cycle T2 T1 Buffer register address Address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 8.44 Contention between Buffer Register Write and Compare Match Rev. 2.00, 03/04, page 194 of 508 8.8.8 Contention between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be that in the buffer after input capture transfer. Figure 8.45 shows the timing in this case. TGR read cycle T2 T1 TGR address Address Read signal Input capture signal TGR X Internal data bus M M Figure 8.45 Contention between TGR Read and Input Capture Rev. 2.00, 03/04, page 195 of 508 8.8.9 Contention between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 8.46 shows the timing in this case. TGR write cycle T2 T1 Address TGR address Write signal Input capture signal TCNT M M TGR Figure 8.46 Contention between TGR Write and Input Capture Rev. 2.00, 03/04, page 196 of 508 8.8.10 Contention between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 8.47 shows the timing in this case. Buffer register write cycle T2 T1 Buffer register address Address Write signal Input capture signal TCNT TGR Buffer register N M N M Figure 8.47 Contention between Buffer Register Write and Input Capture Rev. 2.00, 03/04, page 197 of 508 8.8.11 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 8.48 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. TCNT input clock TCNT H'FFFF H'0000 Counter clear signal TGF Disabled TCFV Figure 8.48 Contention between Overflow and Counter Clearing Rev. 2.00, 03/04, page 198 of 508 8.8.12 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 8.49 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T2 T1 TCNT address Address Write signal TCNT TCNT write data H'FFFF M TCFV flag Figure 8.49 Contention between TCNT Write and Overflow 8.8.13 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 8.8.14 Interrupts in Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source. Interrupts should therefore be disabled before entering module stop mode. 8.8.15 Interrupts in Subactive Mode/Watch Mode If subactive mode/watch mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source. Interrupts should therefore be disabled before entering subactive mode/watch mode. Rev. 2.00, 03/04, page 199 of 508 Rev. 2.00, 03/04, page 200 of 508 Section 9 Watchdog Timer The watchdog timer (WDT_0, WDT_1) is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. The block diagram of the WDT_0 is shown in figure 9.1. The block diagram of the WDT_1 is shown in figure 9.2. 9.1 Features * Selectable from eight counter input clocks. * Switchable between watchdog timer mode and interval timer mode In watchdog timer mode * If the counter overflows, it is possible to select whether this LSI is internally reset or the WDT generates an internal NMI interrupt. In interval timer mode * If the counter overflows, the WDT generates an interval timer interrupt (WOVI). WDT0105A_000120020200 Rev. 2.00, 03/04, page 201 of 508 Overflow /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock sources Interrupt control Clock Clock select Reset control Internal reset signal* RSTCSR TCNT_0 Internal bus WOVI (interrupt request signal) TCSR_0 Bus interface Module bus WDT [Legend] Timer control/status register TCSR: Timer counter TCNT: RSTCSR: Reset control/status register Note: * An internal reset signal can be generated by setting the register. Figure 9.1 Block Diagram of WDT_0 Interrupt control Overflow Internal NMI Internal reset signal Clock /2 /64 /128 /512 /2048 /8192 /32768 /131072 Clock select Reset control Internal reset signal* Internal clock TCNT_1 TSCR_1 Module bus WDT [Legend] TCSR: Timer control/status register TCNT: Timer counter Note: * An internal reset signal can be generated by setting the register. The generated reset is a power-on reset. Figure 9.2 Block Diagram of WDT_1 Rev. 2.00, 03/04, page 202 of 508 SUB/2 SUB/4 SUB/8 SUB/16 SUB/32 SUB/64 SUB/128 SUB/256 Internal bus WOVI (interrupt request signal) Bus interface 9.2 Register Descriptions The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to by a different method to normal registers. For details, see section 9.5.1, Notes on Register Access. * * * * * Timer control/status register_0 (TCSR_0) Timer counter_0 (TCNT_0) Timer control/status register_1 (TCSR_1) Timer counter_1 (TCNT_1) Reset control/status register (RSTCSR) 9.2.1 Timer Counter 0 and 1 (TCNT_0 and TCNT_1) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 by a reset, when the TME bit in TCSR is cleared to 0. 9.2.2 Timer Control/Status Register 0 and 1 (TCSR_0 and TCSR_1) TCSR selects the clock source to be input to TCNT, and selecting the timer mode. * TCSR_0 Bit Bit Name Initial Value R/W Description 7 OVF 0 R/(W)* Overflow Flag Indicates that TCNT has overflowed. Only a write of 0 is permitted, to clear the flag. [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode Rev. 2.00, 03/04, page 203 of 508 Bit Bit Name Initial Value R/W Description 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4, 3 All 1 Reserved These bits are always read as 1 and cannot be modified. 2 CKS2 0 R/W Clock Select 0 to 2 1 CKS1 0 R/W 0 CKS0 0 R/W Selects the clock source to be input to TCNT. The overflow frequency for = 20 MHz is enclosed in parentheses. 000: Clock /2 (frequency: 25.6 s) 001: Clock /64 (frequency: 819.2 s) 010: Clock /128 (frequency: 1.6 ms) 011: Clock /512 (frequency: 6.6 ms) 100: Clock /2048 (frequency: 26.2 ms) 101: Clock /8192 (frequency: 104.9 ms) 110: Clock /32768 (frequency: 419.4 ms) 111: Clock /131072 (frequency: 1.68 s) Note: * Only 0 can be written for flag clearing. * TCSR_1 Bit Bit Name Initial Value R/W 7 OVF 0 R/(W)* Overflow Flag Description Indicates that TCNT has overflowed from H'FF to H'00. Only a write of 0 is permitted, to clear the flag. [Setting condition] When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF Rev. 2.00, 03/04, page 204 of 508 Bit Bit Name Initial Value R/W Description 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4 PSS 0 R/W Prescaler Select Selects the clock source to be input to TCNT. 0: Counts the divided clock of based prescaler (PSM) 1: Counts the divided clock of SUBbased prescaler (PSS) 3 RST/NMI 0 R/W Reset or NMI Selects whether an internal reset request or an NMI interrupt request when the TCNT overflows during the watchdog timer mode. 0: NMI interrupt request 1: Internal reset request Rev. 2.00, 03/04, page 205 of 508 Bit Bit Name Initial Value R/W Description 2 CKS2 0 R/W Clock Select 2 to 0 1 CKS1 0 R/W 0 CKS0 0 R/W Selects the clock source to be input to TCNT. The overflow cycle for = 20 MHz (5-MHz input to this LSI multiplied by four, and SUB = 39.1 kHz) is enclosed in parentheses. The overflow cycle is the period from which TCNT starts counting and until it overflows. When PSS = 0: 000: /2 (cycle: 25.6 s) 001: /64 (cycle: 819.2 ms) 010: /128 (cycle: 1.6 ms) 011: /512 (cycle: 6.6 ms) 100: /2048 (cycle: 26.2 ms) 101: /8192 (cycle: 104.9 ms) 110: /32768 (cycle: 419.4 ms) 111: /131072 (cycle: 1.68s) When PSS = 1: 000: SUB/2 (cycle: 13.1 ms) 001: SUB/4 (cycle: 26.2 ms) 010: SUB/8 (cycle: 52.4 ms) 011: SUB/16 (cycle: 104.9 ms) 100: SUB/32 (cycle: 209.7 ms) 101: SUB/64 (cycle: 419.4 ms) 110: SUB/128 (cycle: 838.9 ms) 111: SUB/256 (cycle: 1.6777 s) Note: * Only 0 can be written for flag clearing. Rev. 2.00, 03/04, page 206 of 508 9.2.3 Reset Control/Status Register (RSTCSR) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, and not by the WDT internal reset signal caused by overflows. Bit Bit Name Initial Value R/W 7 WOVF 0 R/(W)* Watchdog Overflow Flag Description This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode, and only 0 can be written. [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) in watchdog timer mode [Clearing condition] Cleared by reading RSTCSR when WOVF = 1, and then writing 0 to WOVF 6 RSTE 0 R/W Reset Enable Specifies whether or not a reset signal is generated in the chip if TCNT overflows during watchdog timer operation. 0: Reset signal is not generated even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: Reset signal is generated if TCNT overflows 5 RSTS 0 R/W Reset Select Selects the internal reset type to be generated if TCNT overflows during watchdog timer operation. 0: Power-on reset 1: Setting prohibited 4 to 0 -- All 1 -- Reserved These bits are always read as 1 and cannot be modified. Note: * Only 0 can be written for flag clearing. Rev. 2.00, 03/04, page 207 of 508 9.3 Operation 9.3.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. When the WDT is used as a watchdog timer, and if TCNT overflows without being rewritten because of a system malfunction or other error, a WDTOVF signal is output. TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. In watchdog timer mode, the WDT can internally reset this LSI with a WDTOVF signal. When the RSTE bit of the RSTCSR is set to 1, and if the TCNT overflows, an internal reset signal for this LSI is issued at the same time as a WDTOVF signal. In this case, select power-on reset by setting the RSTS bit of the RSTCSR to 0. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. The WDTOVF signal is output for 132 states when the RSTE bit = 1 of RSTCSR, and for 130 states when the RSTE bit = 0. When the TCNT overflows in watchdog timer mode, the WOVF bit of the RSTCSR is set to 1. If the RSTE bit of the RSTCSR has been set to 1, an internal reset signal for the entire LSI is generated at TCNT overflow. Rev. 2.00, 03/04, page 208 of 508 TCNT value Overflow H'FF Time H'00 WT/IT = 1 TME = 1 Write H'00 to TCNT WOVF = 1*1 WT/IT = 1 Write H'00 TME = 1 to TCNT Internal reset is generated Internal reset signal* 2 518 states [Legend] WT/IT: Timer mode select bit Timer enable bit TME: Notes: 1. After the WOVF bit becomes 1, it is cleared to 0 by an internal reset. 2. The internal reset signal is generated only if the RSTE bit is set to 1. Figure 9.3 (a) WDT_0 Operation in Watchdog Timer Mode TCNT value Overflow H'FF Time H'00 WT/IT = 1 TME = 1 Write H'00 to TCNT WOVF = 1*1 WT/IT = 1 TME = 1 Write H'00 to TCNT Internal reset is generated Internal reset signal* 2 515/516 states [Legend] WT/IT: Timer mode select bit Timer enable bit TME: Notes: 1. After the WOVF bit becomes 1, it is cleared to 0 by an internal reset. 2. The internal reset signal is generated only if the RSTE bit is set to 1. Figure 9.3 (b) WDT_1 Operation in Watchdog Timer Mode Rev. 2.00, 03/04, page 209 of 508 9.3.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the time the OVF bit of the TCSR is set to 1. TCNT value Overflow H'FF Overflow Overflow Overflow Time H'00 WT/IT=0 TME=1 WOVI WOVI WOVI [Legend] WOVI: Interval timer interrupt request generation Figure 9.4 Operation in Interval Timer Mode Rev. 2.00, 03/04, page 210 of 508 WOVI 9.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. If an NMI interrupt request has been chosen in watchdog timer mode, an NMI interrupt request is generated when the TCNT overflows. Table 9.1 WDT Interrupt Source Name Interrupt Source Interrupt Flag WOVI TCNT overflow (interval timer mode) OVF NMI TCNT overflow (watchdog timer mode) OVF 9.5 Usage Notes 9.5.1 Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT, TCSR, and RSTCSR These registers must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, the relative condition shown in figure 9.5 needs to be satisfied in order to write to TCNT or TCSR. The transfer instruction writes the lower byte data to TCNT or TCSR according to the satisfied condition. To write to RSTCSR, execute a word transfer instruction for address H'FF76. A byte transfer instruction cannot write to RSTCSR. The method of writing 0 to the WOVF bit differs from that of writing to the RSTE and RSTS bits. To write 0 to the WOVF bit, satisfy the condition shown in figure 9.5. If satisfied, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write to the RSTE and RSTS bits, satisfy the condition shown in figure 9.5. If satisfied, the transfer instruction writes the values in bits 5 and 6 of the lower byte into the RSTE and RSTS bits, respectively, but has no effect on the WOVF bit. Rev. 2.00, 03/04, page 211 of 508 TCNT write Writing to RSTE and RSTS bits Address: H'FF74 H'FF76 15 8 H'5A 7 0 Write data TCSR write Writing 0 to WOVF bit Address: H'FF74 H'FF76 15 8 H'5A 7 0 Write data or H'00 Figure 9.5 Writing to TCNT, TCSR, and RSTCSR (example for WDT0) Reading TCNT, TCSR, and RSTCSR (WDT0) These registers are read in the same way as other registers. The read addresses are H'FF74 for TCSR, H'FF75 for TCNT, and H'FF77 for RSTCSR. 9.5.2 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 9.6 shows this operation. TCNT write cycle T1 T2 Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 9.6 Contention between TCNT Write and Increment Rev. 2.00, 03/04, page 212 of 508 9.5.3 Changing Value of CKS2 to CKS0 If bits CKS0 to CKS2 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS0 to CKS2. 9.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer while the WDT is operating, errors could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 9.5.5 Internal Reset in Watchdog Timer Mode This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, however TCNT and TCSR of the WDT are reset. TCNT, TCSR, or RSTCR cannot be written to for 132 states following an overflow. During this period, any attempt to read the WOVF flag is not acknowledged. Accordingly, wait 132 states after overflow to write 0 to the WOVF flag for clearing. 9.5.6 OVF Flag Clearing in Interval Timer Mode When setting of the OVF flag is in contention with reading of the OVF flag in interval timer mode, the OVF flag may not be cleared even when 0 is written to it after the OVF flag has been read as 1. When there is a possibility of contention between the setting and reading of the OVF flag when the OVF flag is polled while the interval timer interrupt is disabled, 0 should be only written to the OVF after reading the OVF at least twice in its '1' state to ensure clearing of the flag. Rev. 2.00, 03/04, page 213 of 508 Rev. 2.00, 03/04, page 214 of 508 Section 10 Serial Communication Interface (SCI) This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Figure 10.1 shows a block diagram of the SCI. 10.1 Features * Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected External clock can be selected as a transfer clock source (except for in Smart Card interface mode). * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources Transmit-end, transmit-data-empty, receive-data-full, and receive error -- that can issue requests. * Module stop mode can be set Asynchronous mode * * * * * Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RxD pin level directly in the case of a framing error Rev. 2.00, 03/04, page 215 of 508 Clocked Synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors detected Smart Card Interface Bus interface * Automatic transmission of error signal (parity error) in receive mode * Error signal detection and automatic data retransmission in transmit mode * Direct convention and inverse convention both supported Module data bus RDR TDR BRR SCMR SSR RxD TxD SCR RSR TSR SMR Baud rate generator Transmission/ reception control Parity generation /4 /16 /64 Clock Parity check External clock SCK [Legend] RSR: RDR: TSR: TDR: SMR: SCR: SSR: SCMR: BRR: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Smart card mode register Bit rate register Figure 10.1 Block Diagram of SCI Rev. 2.00, 03/04, page 216 of 508 TEI TXI RXI ERI Internal data bus 10.2 Input/Output Pins Table 10.1 shows the serial pins for each SCI channel. Table 10.1 Pin Configuration Channel Pin Name* I/O Function 0 SCK0 I/O SCI0 clock input/output 1 Note: 10.3 * RxD0 Input SCI0 receive data input TxD0 Output SCI0 transmit data output SCK1 I/O SCI1 clock input/output RxD1 Input SCI1 receive data input TxD1 Output SCI1 transmit data output Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. Register Descriptions The SCI has the following registers for each channel. The serial mode register (SMR), serial status register (SSR), and serial control register (SCR) are described separately for normal serial communication interface mode and Smart Card interface mode because their bit functions differ in part. * * * * * * * * * Receive shift register (RSR) Receive data register (RDR) Transmit data register (TDR) Transmit shift register (TSR) Serial mode register (SMR) Serial control register (SCR) Serial status register (SSR) Smart card mode register (SCMR) Bit rate register (BRR) Rev. 2.00, 03/04, page 217 of 508 10.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input to the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 10.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores received data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. 10.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores data for transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structure of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during serial transmission, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. 10.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, and then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. Rev. 2.00, 03/04, page 218 of 508 10.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bit functions of SMR differ between normal serial communication interface mode and Smart Card interface mode. * Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Bit Bit Name Initial Value R/W Description 7 C/A 0 R/W Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. The MSB (bit 7) of TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit character. Rev. 2.00, 03/04, page 219 of 508 Bit Bit Name Initial Value R/W Description 2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. 1 CKS1 0 R/W Clock Select 0 and 1 0 CKS0 0 R/W These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 10.3.9, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 10.3.9, Bit Rate Register (BRR)). * Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 GM 0 R/W GSM Mode When this bit is set to 1, the SCI operates in GSM mode. In GSM mode, the timing of the TEND setting is advanced by 11.0 etu (Elementary Time Unit: the time for transfer of one bit), and clock output control mode addition is performed. For details, see section 10.7.8, Clock Output Control. 6 BLK 0 R/W When this bit is set to 1, the SCI operates in block transfer mode. For details on block transfer mode, see section 10.7.3, Block Transfer Mode. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data in transmission, and the parity bit is checked in reception. In Smart Card interface mode, this bit must be set to 1. Rev. 2.00, 03/04, page 220 of 508 Bit Bit Name Initial Value R/W Description 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. For details on setting this bit in Smart Card interface mode, see section 10.7.2, Data Format (Except for Block Transfer Mode). 3 BCP1 0 R/W Basic Clock Pulse 1 and 0 2 BCP0 0 R/W These bits specify the number of basic clock periods in a 1-bit transfer interval on the Smart Card interface. 00: 32 clock (S = 32) 01: 64 clock (S = 64) 10: 372 clock (S = 372) 11: 256 clock (S = 256) For details, see section 10.7.4, Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode. S stands for the value of S in BRR (see section 10.3.9, Bit Rate Register (BRR)). 1 CKS1 0 R/W Clock Select 0 and 1 0 CKS0 0 R/W These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 10.3.9, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 10.3.9, Bit Rate Register (BRR)). Rev. 2.00, 03/04, page 221 of 508 10.3.6 Serial Control Register (SCR) SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also used to selection of the transfer clock source. For details on interrupt requests, see section 10.8, Interrupts. Some bit functions of SCR differ between normal serial communication interface mode and Smart Card interface mode. * Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, the TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 TE 0 R/W Transmit Enable When this bit s set to 1, transmission is enabled. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, see section 10.5, Multiprocessor Communication Function. 2 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, TEI interrupt request is enabled. Rev. 2.00, 03/04, page 222 of 508 Bit Bit Name Initial Value R/W Description 1 CKE1 0 R/W Clock Enable 0 and 1 0 CKE0 0 R/W Selects the clock source and SCK pin function. Asynchronous mode 00: Internal clock SCK pin functions as I/O port 01: Internal clock Outputs a clock of the same frequency as the bit rate from the SCK pin. 1X: External clock Inputs a clock with a frequency 16 times the bit rate from the SCK pin. Clocked synchronous mode 0X: Internal clock (SCK pin functions as clock output) 1X: External clock (SCK pin functions as clock input) [Legend] X: Don't care * Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in Smart Card interface mode. 2 TEIE 0 R/W Transmit End Interrupt Enable Write 0 to this bit in Smart Card interface mode. Rev. 2.00, 03/04, page 223 of 508 Bit Bit Name Initial Value R/W Description 1 CKE1 0 R/W Clock Enable 0 and 1 0 CKE0 0 Enables or disables clock output from the SCK pin. The clock output can be dynamically switched in GSM mode. For details, see section 10.7.8, Clock Output Control. When the GM bit in SMR is 0: 00: Output disabled (SCK pin can be used as an I/O port pin) 01: Clock output 1X: Reserved When the GM bit in SMR is 1: 00: Output fixed low 01: Clock output 10: Output fixed high 11: Clock output [Legend] X: Don't care Rev. 2.00, 03/04, page 224 of 508 10.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ between normal serial communication interface mode and Smart Card interface mode. * Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Bit Bit Name Initial Value R/W 7 TDRE 1 R/(W)* Transmit Data Register Empty Description Displays whether TDR contains transmit data. [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR [Clearing condition] * 6 RDRF 0 When 0 is written to TDRE after reading TDRE = 1 R/(W)* Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing condition] * When 0 is written to RDRF after reading RDRF = 1 The RDRF flag is not affected and retains its value when the RE bit in SCR is cleared to 0. 5 ORER 0 R/(W)* Overrun Error [Setting condition] * When the next serial reception is completed while RDRF = 1 [Clearing condition] * When 0 is written to ORER after reading ORER = 1 Rev. 2.00, 03/04, page 225 of 508 Bit Bit Name Initial Value R/W 4 FER 0 R/(W)* Framing Error Description [Setting condition] * When the stop bit is 0 [Clearing condition] * When 0 is written to FER after reading FER = 1 In 2-stop-bit mode, only the first stop bit is checked. 3 PER 0 R/(W)* Parity Error [Setting condition] * When a parity error is detected during reception [Clearing condition] * 2 TEND 1 R When 0 is written to PER after reading PER = 1 Transmit End [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] * 1 MPB 0 R When 0 is written to TDRE after reading TDRE = 1 Multiprocessor Bit MPB stores the multiprocessor bit in the receive data. When the RE bit in SCR is cleared to 0 its state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit data. Note: Only 0 for clearing the flag can be written. Rev. 2.00, 03/04, page 226 of 508 * Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Bit Name Initial Value R/W 7 TDRE 1 R/(W)* Transmit Data Register Empty Description Displays whether TDR contains transmit data. [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR [Clearing condition] * 6 RDRF 0 When 0 is written to TDRE after reading TDRE = 1 R/(W)* Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing condition] * When 0 is written to RDRF after reading RDRF = 1 The RDRF flag is not affected and retains its value when the RE bit in SCR is cleared to 0. 5 ORER 0 R/(W)* Overrun Error [Setting condition] * When the next serial reception is completed while RDRF = 1 [Clearing condition] * 4 ERS 0 When 0 is written to ORER after reading ORER = 1 R/(W)* Error Signal Status [Setting condition] * When the low level of the error signal is sampled [Clearing condition] * When 0 is written to ERS after reading ERS = 1 Rev. 2.00, 03/04, page 227 of 508 Bit Bit Name Initial Value R/W 3 PER 0 R/(W)* Parity Error Description [Setting condition] * When a parity error is detected during reception [Clearing condition] * 2 TEND 1 R When 0 is written to PER after reading PER = 1 Transmit End This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR. [Setting conditions] * When the TE bit in SCR is 0 and the ERS bit is also 0 * When the ESR bit is 0 and the TDRE bit is 1 after the specified interval following transmission of 1byte data. The timing of bit setting differs according to the register setting as follows: When GM = 0 and BLK = 0, 2.5 etu after transmission starts When GM = 0 and BLK = 1, 1.5 etu after transmission starts When GM = 1 and BLK = 0, 1.0 etu after transmission starts When GM = 1 and BLK = 1, 1.0 etu after transmission starts [Clearing condition] * 1 MPB 0 R When 0 is written to TDRE after reading TDRE = 1 Multiprocessor Bit This bit is not used in Smart Card interface mode. 0 MPBT 0 R/W Multiprocessor Bit Transfer Write 0 to this bit in Smart Card interface mode. Note: Only 0 for clearing the flag can be written. Rev. 2.00, 03/04, page 228 of 508 10.3.8 Smart Card Mode Register (SCMR) SCMR is a register that selects Smart Card interface mode and its format. Bit Bit Name Initial Value R/W Description 7 to 4 All 1 Reserved These bits are always read as 1. 3 SDIR 0 R/W Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: LSB-first in transfer 1: MSB-first in transfer The bit setting is valid only when the transfer data format is 8 bits. For 7-bit data, LSB-first is fixed. 2 SINV 0 R/W Smart Card Data Invert Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit. To invert the parity bit, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR 1 1 Reserved This bit is always read as 1. 0 SMIF 0 R/W Smart Card Interface Mode Select This bit is set to 1 to make the SCI operate in Smart Card interface mode. 0: Normal asynchronous mode or clocked synchronous mode 1: Smart card interface mode Rev. 2.00, 03/04, page 229 of 508 10.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 10.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and it can be read or written to by the CPU at all times. Table 10.2 The Relationships between The N Setting in BRR and Bit Rate B Mode Bit Rate Asynchronous Mode B= Clocked Synchronous Mode B= Smart Card Interface Mode [Legend] B: N: : n and S: B= Error x 106 64 x 2 2n-1 x (N + 1) Error (%) = { x 106 B x 64 x 2 2n-1 x (N + 1) -1 } x 100 x 106 8 x 2 2n-1 x (N + 1) x 106 Sx2 2n-1 x (N + 1) Error (%) = { x 106 B x S x 2 2n-1 x (N + 1) -1 } x 100 Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (MHz) Determined by the SMR settings shown in the following tables. SMR Setting SMR Setting CKS1 CKS0 n BCP1 BCP0 S 0 0 0 0 0 32 0 1 1 0 1 64 1 0 2 1 0 372 1 1 3 1 1 256 Table 10.3 shows sample N settings in BRR in normal asynchronous mode. Table 10.4 shows the maximum bit rate for each frequency in normal asynchronous mode. Table 10.6 shows sample N settings in BRR in clocked synchronous mode. Table 10.8 shows sample N settings in BRR in Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in a 1-bit transfer interval) can be selected. For details, see section 10.7.4, Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode. Tables 10.5 and 10.7 show the maximum bit rates with external clock input. Rev. 2.00, 03/04, page 230 of 508 Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency (MHz) 4 4.9152 5 6 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 70 0.03 2 86 0.31 2 88 -0.25 2 106 -0.44 150 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 300 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16 600 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16 1200 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16 2400 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16 4800 0 25 0.16 0 31 0.00 0 32 -1.36 0 38 0.16 9600 0 12 0.16 0 15 0.00 0 15 1.73 0 19 -2.34 19200 0 7 0.00 0 7 1.73 0 9 -2.34 31250 0 3 0.00 0 4 -1.70 0 4 0.00 0 5 0.00 38400 0 3 0.00 0 3 1.73 0 4 -2.34 Operating Frequency (MHz) 6.144 7.3728 8 9.8304 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 108 0.08 2 130 -0.07 2 141 0.03 2 174 -0.26 150 2 79 0.00 2 95 0.00 2 103 0.16 2 127 0.00 300 1 159 0.00 1 191 0.00 1 207 0.16 1 255 0.00 600 1 79 0.00 1 95 0.00 1 103 0.16 1 127 0.00 1200 0 159 0.00 0 191 0.00 0 207 0.16 0 255 0.00 2400 0 79 0.00 0 95 0.00 0 103 0.16 0 127 0.00 4800 0 39 0.00 0 47 0.00 0 51 0.16 0 63 0.00 9600 0 19 0.00 0 23 0.00 0 25 0.16 0 31 0.00 19200 0 9 0.00 0 11 0.00 0 12 0.16 0 15 0.00 31250 0 5 2.40 0 7 0.00 0 9 -1.70 38400 0 4 0.00 0 5 0.00 0 7 0.00 Rev. 2.00, 03/04, page 231 of 508 Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency (MHz) 10 12 12.288 14 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 177 -0.25 2 212 0.03 2 217 0.08 2 248 -0.17 150 2 129 0.16 2 155 0.16 2 159 0.00 2 181 0.13 300 2 64 0.16 2 77 0.16 2 79 0.00 2 90 0.13 600 1 129 0.16 1 155 0.16 1 159 0.00 1 181 0.13 1200 1 64 0.16 1 77 0.16 1 79 0.00 1 90 0.13 2400 0 129 0.16 0 155 0.16 0 159 0.00 0 181 0.13 4800 0 64 0.16 0 77 0.16 0 79 0.00 0 90 0.13 9600 0 32 -1.36 0 38 0.16 0 39 0.00 0 45 -0.93 19200 0 15 1.73 0 19 -2.34 0 19 0.00 0 22 -0.93 31250 0 9 0.00 0 11 0.00 0 11 2.40 0 13 0.00 38400 0 7 1.73 0 9 -2.34 0 9 0.00 Operating Frequency (MHz) 14.7456 16 17.2032 18 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 64 0.70 3 70 0.03 3 75 0.48 3 79 -0.12 150 2 191 0.00 2 207 0.13 2 223 0.00 2 233 0.16 300 2 95 0.00 2 103 0.13 2 111 0.00 2 116 0.16 600 1 191 0.00 1 207 0.13 1 223 0.00 1 233 0.16 1200 1 95 0.00 1 103 0.13 1 111 0.00 1 116 0.16 2400 0 191 0.00 0 207 0.13 0 223 0.00 0 233 0.16 4800 0 95 0.00 0 103 0.13 0 111 0.00 0 116 0.16 9600 0 47 0.00 0 51 0.13 0 55 0.00 0 58 -0.69 19200 0 23 0.00 0 25 0.13 0 27 0.00 0 28 1.02 31250 0 14 -1.70 0 15 0.00 0 13 1.20 0 17 0.00 38400 0 11 0.00 0 12 0.13 0 13 0.00 0 14 -2.34 Rev. 2.00, 03/04, page 232 of 508 Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency (MHz) 19.6608 20 Bit Rate (bit/s) n N Error (%) n N Error (%) 110 3 86 0.31 3 88 -0.25 150 2 255 0.00 3 64 0.16 300 2 127 0.00 2 129 0.16 600 1 255 0.00 2 64 0.16 1200 1 127 0.00 1 129 0.16 2400 0 255 0.00 1 64 0.16 4800 0 127 0.00 0 129 0.16 9600 0 63 0.00 0 64 0.16 19200 0 31 0.00 0 32 -1.36 31250 0 19 -1.70 0 19 0.00 38400 0 15 0.00 0 15 1.73 Rev. 2.00, 03/04, page 233 of 508 Table 10.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) (MHz) Maximum Bit Rate (bit/s) n N (MHz) Maximum Bit Rate (bit/s) n N 4 125000 0 0 12 375000 0 0 4.9152 153600 0 0 12.288 384000 0 0 5 156250 0 0 14 437500 0 0 0 6 187500 0 6.144 192000 0 14.7456 460800 0 0 16 500000 0 0 7.3728 230400 0 0 17.2032 537600 0 0 8 250000 0 0 18 562500 0 0 9.8304 307200 0 0 19.6608 614400 0 0 10 312500 0 0 20 625000 0 0 Table 10.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 4 1.0000 62500 12 3.0000 187500 4.9152 1.2288 76800 12.288 3.0720 192000 5 1.2500 78125 14 3.5000 218750 6 1.5000 93750 14.7456 3.6864 230400 6.144 1.5360 96000 16 4.0000 250000 7.3728 1.8432 115200 17.2032 4.3008 268800 8 2.0000 125000 18 4.5000 281250 9.8304 2.4576 153600 19.6608 4.9152 307200 10 2.5000 156250 20 5.0000 312500 Rev. 2.00, 03/04, page 234 of 508 Table 10.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency (MHz) 4 Bit Rate (bit/s) n N 110 250 2 500 8 10 16 n N n N n N 249 3 124 3 249 2 124 2 249 3 1k 1 249 2 124 2.5k 1 99 1 199 1 5k 0 199 1 99 10k 0 99 0 199 25k 0 39 0 50k 0 19 100k 0 250k 20 n N 124 2 249 249 2 99 2 124 1 124 1 199 1 249 0 249 1 99 1 124 79 0 99 0 159 0 199 0 39 0 49 0 79 0 99 9 0 19 0 24 0 39 0 49 0 3 0 7 0 9 0 15 0 19 500k 0 1 0 3 0 4 0 7 0 9 1M 0 0* 0 1 0 3 0 4 2.5M 0 0* 5M 0 1 0 0* [Legend] Blank: Cannot be set. --: Can be set, but there will be a degree of error. *: Continuous transfer is not possible. Note: * Make the settings so that the error does not exceed 1%. Table 10.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 4 0.6667 666666.7 14 2.3333 2333333.3 6 1.0000 1.000000.0 16 2.6667 2666666.7 8 1.3333 1333333.3 18 3.0000 3000000.0 10 1.6667 1666666.7 20 3.3333 3333333.3 12 2.0000 2000000.0 Rev. 2.00, 03/04, page 235 of 508 Table 10.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (When n = 0 and S = 372) Operating Frequency (MHz) 7.1424 10.00 10.7136 13.00 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 9600 0 0 0.00 0 1 30 0 1 25 0 1 8.99 Operating Frequency (MHz) 14.2848 16.00 18.00 20.00 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 9600 0 1 0.00 0 1 12.01 0 2 15.99 0 2 6.60 Table 10.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372) (MHz) Maximum Bit Rate (bit/s) n N (MHz) Maximum Bit Rate (bit/s) n N 7.1424 9600 0 0 14.2848 19200 0 0 10.00 13441 0 0 16.00 21505 0 0 10.7136 14400 0 0 18.00 24194 0 0 13.00 17473 0 0 20.00 26882 0 0 Rev. 2.00, 03/04, page 236 of 508 10.4 Operation in Asynchronous Mode Figure 10.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line. When the transmission line goes to the space state (low level), the SCI recognizes a start bit and starts serial communication. In asynchronous serial communication, the communication line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex. The transmitter and receiver both have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. LSB 1 Serial data 0 D0 Idle state (mark state) 1 MSB D1 D2 D3 D4 D5 Start bit Transmit/receive data 1 bit 7 or 8 bits D6 D7 0/1 Parity bit 1 bit, or none 1 1 Stop bit 1 or 2 bits One unit of transfer data (character or frame) Figure 10.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) 10.4.1 Data Transfer Format Table 10.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 10.5, Multiprocessor Communication Function. Rev. 2.00, 03/04, page 237 of 508 Table 10.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transfer Format and Frame Length CHR PE MP STOP 1 0 0 0 0 S 8-bit data STOP 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 -- 1 0 S 8-bit data MPB STOP 0 -- 1 1 S 8-bit data MPB STOP STOP 1 -- 1 0 S 7-bit data MPB STOP 1 -- 1 1 S 7-bit data MPB STOP STOP [Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev. 2.00, 03/04, page 238 of 508 2 3 4 5 6 7 8 9 10 11 12 10.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 10.3. Thus, the reception margin in asynchronous mode is given by formula (1) below. M = (0.5 - D - 0.5 1 )- N 2N - (L - 0.5) F 100 [%] ... Formula (1) Where M: N: D: L: F: Reception margin (%) Ratio of bit rate to clock (N = 16) Clock duty (D = 0.5 to 1.0) Frame length (L = 9 to 12) Absolute value of clock rate deviation Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 10.3 Receive Data Sampling Timing in Asynchronous Mode Rev. 2.00, 03/04, page 239 of 508 10.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in Figure 10.4. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 10.4 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) Rev. 2.00, 03/04, page 240 of 508 10.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, MPIE, TE, and RE to 0. Start initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [1] [2] Set the data transfer format in SMR and SCMR. Set data transfer format in SMR and SCMR [2] Set value in BRR [3] Wait No 1-bit interval elapsed? [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits to 1. Setting the TE and RE bits enables the TxD and RxD pins to be used. Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits to 1 When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [4] <Initialization completion> Figure 10.5 Sample SCI Initialization Flowchart Rev. 2.00, 03/04, page 241 of 508 10.4.5 Data Transmission (Asynchronous Mode) Figure 10.6 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Continuous transmission is possible because the TXI interrupt routine writes next transmit data to TDR before transmission of the current transmit data has been completed. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 10.7 shows a sample flowchart for transmission in asynchronous mode. 1 Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt service routine TEI interrupt request generated 1 frame Figure 10.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 2.00, 03/04, page 242 of 508 [1] Initialization Start transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [3] Serial transmission continuation procedure: No All data transmitted? Yes [3] Read TEND flag in SSR No Yes No To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. TEND = 1 Break output? [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [4] Yes Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 <End> Figure 10.7 Sample Serial Transmission Flowchart Rev. 2.00, 03/04, page 243 of 508 10.4.6 Serial Data Reception (Asynchronous Mode) Figure 10.8 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line. If a start bit is detected, the SCI performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has been completed. 1 Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 0 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine 1 frame Figure 10.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 2.00, 03/04, page 244 of 508 ERI interrupt request generated by framing error Table 10.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.9 shows a sample flow chart for serial data reception. Table 10.11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* ORER FER PER Receive Data Receive Error Type 1 1 0 0 Lost Overrun error 0 0 1 0 Transferred to RDR Framing error 0 0 0 1 Transferred to RDR Parity error 1 1 1 0 Lost Overrun error + framing error 1 1 0 1 Lost Overrun error + parity error 0 0 1 1 Transferred to RDR Framing error + parity error 1 1 1 1 Lost Overrun error + framing error + parity error Note: * The RDRF flag retains the state it had before data reception. Rev. 2.00, 03/04, page 245 of 508 Initialization [1] Start reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the Yes appropriate error processing, ensure PER FER ORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot be No Error processing resumed if any of these flags are set to 1. In the case of a framing error, a (Continued on next page) break can be detected by reading the value of the input port corresponding to [4] Read RDRF flag in SSR the RxD pin. Read ORER, PER, and FER flags in SSR [4] SCI status check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? [5] [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. Yes Clear RE bit in SCR to 0 <End> Figure 10.9 Sample Serial Reception Data Flowchart (1) Rev. 2.00, 03/04, page 246 of 508 [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 10.9 Sample Serial Reception Data Flowchart (2) Rev. 2.00, 03/04, page 247 of 508 10.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles; an ID transmission cycle that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 10.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER to 1, are inhibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev. 2.00, 03/04, page 248 of 508 Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 10.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Rev. 2.00, 03/04, page 249 of 508 10.5.1 Multiprocessor Serial Data Transmission Figure 10.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Initialization [1] Start transmission Read TDRE flag in SSR [2] No [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR [3] Serial transmission continuation procedure: Clear TDRE flag to 0 No [3] All data transmitted? Yes Read TEND flag in SSR To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to 1, clear DR to 0, then clear the TE bit in SCR to 0. No TEND = 1 Yes No Break output? [4] Yes Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 <End> Figure 10.11 Sample Multiprocessor Serial Transmission Flowchart Rev. 2.00, 03/04, page 250 of 508 10.5.2 Multiprocessor Serial Data Reception Figure 10.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 10.12 shows an example of SCI operation for multiprocessor format reception. 1 Start bit 0 Data (ID1) MPB D0 D1 D7 1 Stop bit Start bit 1 0 Data (Data1) D0 D1 Stop MPB bit D7 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state (a) Data does not match station's ID 1 Start bit 0 Data (ID2) D0 D1 Stop MPB bit D7 1 1 Start bit 0 Data (Data2) D0 D1 D7 Stop MPB bit 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 ID2 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine Data2 MPIE bit set to 1 again (b) Data matches station's ID Figure 10.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 2.00, 03/04, page 251 of 508 Initialization [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [1] Start reception Read MPIE bit in SCR [2] ID reception cycle: Set the MPIE bit in SCR to 1. [2] [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. Read ORER and FER flags in SSR Yes FER ORER = 1 No Read RDRF flag in SSR [3] No RDRF = 1 [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR Yes FER ORER = 1 No Read RDRF flag in SSR [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin [4] value. No RDRF = 1 Yes Read receive data in RDR No All data received? [5] Error processing Yes Clear RE bit in SCR to 0 (Continued on next page) <End> Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 2.00, 03/04, page 252 of 508 [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, and FER flags in SSR to 0 <End> Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 2.00, 03/04, page 253 of 508 10.6 Operation in Clocked Synchronous Mode Figure 10.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clocked synchronous mode, the SCI receives data in synchronous with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common clock. The transmitter and the receiver both have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. One unit of transfer data (character or frame) * * Synchronization clock LSB Bit 0 Serial data MSB Bit 1 Don't care Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Note: * High except in continuous transfer Figure 10.14 Data Format in Synchronous Communication (for LSB-First) 10.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of CKE0 and CKE1 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. Rev. 2.00, 03/04, page 254 of 508 10.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, the TE and RE bits in SCR should be cleared to 0, and then the SCI should be initialized as described in a sample flowchart in Figure 10.15. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, MPIE, TE, and RE to 0. Start initialization Clear TE and RE bits in SCR to 0 [2] Set the data transfer format in SMR and SCMR. Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR [2] Set value in BRR [3] Wait [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] <Transfer start> Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 10.15 Sample SCI Initialization Flowchart Rev. 2.00, 03/04, page 255 of 508 10.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 10.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. Continuous transmission is possible because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has been completed. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 10.17 shows a sample flow chart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 10.16 Sample SCI Transmission Operation in Clocked Synchronous Mode Rev. 2.00, 03/04, page 256 of 508 [1] Initialization Start transmission Read TDRE flag in SSR [2] No TDRE = 1 [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [3] Yes Read TEND flag in SSR No TEND = 1 Yes Clear TE bit in SCR to 0 <End> Figure 10.17 Sample Serial Transmission Flowchart Rev. 2.00, 03/04, page 257 of 508 10.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 10.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization synchronous with a synchronous clock input or output, starts receiving data, and stores the received data in RSR. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag in SSR is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the RDRF flag remains to be set to 1. 3. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished. Synchronization clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine RXI interrupt request generated ERI interrupt request generated by overrun error 1 frame Figure 10.18 Example of SCI Operation in Reception Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.19 shows a sample flow chart for serial data reception. Rev. 2.00, 03/04, page 258 of 508 Initialization [1] Start reception [2] Read ORER flag in SSR Yes ORER = 1 [3] No Error processing (Continued below) Read RDRF flag in SSR [4] No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? [5] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. Yes Clear RE bit in SCR to 0 <End> [3] Error processing Overrun error processing Clear ORER flag in SSR to 0 <End> Figure 10.19 Sample Serial Reception Flowchart Rev. 2.00, 03/04, page 259 of 508 10.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 10.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction. Rev. 2.00, 03/04, page 260 of 508 Initialization [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. Start transmission/reception Read TDRE flag in SSR [2] No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [3] Read ORER flag in SSR ORER = 1 No Read RDRF flag in SSR Yes [3] Error processing [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. [4] No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? [5] Yes Clear TE and RE bits in SCR to 0 <End> Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. Figure 10.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev. 2.00, 03/04, page 261 of 508 10.7 Operation in Smart Card Interface The SCI supports an IC card (Smart Card) interface that conforms to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface mode is carried out by means of a register setting. 10.7.1 Pin Connection Example Figure 10.21 shows an example of connection with the Smart Card. In communication with an IC card, as both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected to the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. This LSI port output is used as the reset signal. VCC TxD RxD SCK Rx (port) This LSI Data line Clock line Reset line I/O CLK RST IC card Connected equipment Figure 10.21 Schematic Diagram of Smart Card Interface Pin Connections Rev. 2.00, 03/04, page 262 of 508 10.7.2 Data Format (Except for Block Transfer Mode) Figure 10.22 shows the transfer data format in Smart Card interface mode. * One frame consists of 8-bit data plus a parity bit in asynchronous mode. * In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. * If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. * If an error signal is sampled during transmission, the same data is retransmitted automatically after a delay of 2 etu or longer. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 DE Transmitting station output [Legend] DS: D0 to D7: Dp: DE: Receiving station output Start bit Data bits Parity bit Error signal Figure 10.22 Normal Smart Card Interface Data Format Data transfer with other types of IC cards (direct convention and inverse convention) are performed as described in the following. (Z) A Z Z A Z Z Z A A Z Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (Z) State Figure 10.23 Direct Convention (SDIR = SINV = O/E = 0) Rev. 2.00, 03/04, page 263 of 508 With the direction convention type IC and the above sample start character, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV bits in SCMR to 0. According to Smart Card regulations, clear the O/E bit in SMR to 0 to select even parity mode. (Z) A Z Z A A A A A A Z Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp (Z) State Figure 10.24 Inverse Convention (SDIR = SINV = O/E = 1) With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data for the above is H'3F. For the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to Smart Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z. In this LSI, the SINV bit inverts only data bits D0 to D7. Therefore, set the O/E bit in SMR to 1 to invert the parity bit for both transmission and reception. 10.7.3 Block Transfer Mode Operation in block transfer mode is the same as that in SCI asynchronous mode, except for the following points. * In reception, though the parity check is performed, no error signal is output even if an error is detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the parity bit of the next frame. * In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the start of the next frame. * In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu after transmission start. * As with the normal Smart Card interface, the ERS flag indicates the error signal status, but since error signal transfer is not performed, this flag is always cleared to 0. Rev. 2.00, 03/04, page 264 of 508 10.7.4 Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (fixed at 16 times in normal asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. As shown in Figure 10.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given by the following formula. M = | (0.5 - Where M: N: D: L: F: | D - 0.5 | 1 ) - (L - 0.5) F - (1 + F) | N 2N 100% Reception margin (%) Ratio of bit rate to clock (N = 32, 64, 372, and 256) Clock duty (D = 0 to 1.0) Frame length (L = 10) Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin formula is as follows. M = (0.5 - 1/2 x 372) x 100% = 49.866% 372 clocks 186 clocks 0 185 185 371 0 371 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 10.25 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Transfer Rate) Rev. 2.00, 03/04, page 265 of 508 10.7.5 Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. 2. 3. 4. Clear the TE and RE bits in SCR to 0. Clear the error flags ERS, PER, and ORER in SSR to 0. Set the GM, BLK, O/E, BCP0, BCP1, CKS0, and CKS1 bits in SMR. Set the PE bit to 1. Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. 5. Set the value corresponding to the bit rate in BRR. 6. Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. 7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. To switch from receive mode to transmit mode, after checking that the SCI has finished reception, initialize the SCI, and set RE to 0 and TE to 1. Whether SCI has finished reception or not can be checked with the RDRF, PER, or ORER flags. To switch from transmit mode to receive mode, after checking that the SCI has finished transmission, initialize the SCI, and set TE to 0 and RE to 1. Whether SCI has finished transmission or not can be checked with the TEND flag. 10.7.6 Data Transmission (Except for Block Transfer Mode) As data transmission in Smart Card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). Figure 10.26 illustrates the retransfer operation when the SCI is in transmit mode. 1. If an error signal is sent back from the receiving end after transmission of one frame is complete, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. 2. The TEND bit in SSR is not set for a frame in which an error signal indicating an abnormality is received. Data is retransferred from TDR to TSR, and retransmitted automatically. 3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. Transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. Writing transmit data to TDR transfers the next transmit data. Rev. 2.00, 03/04, page 266 of 508 Figure 10.28 shows a flowchart for transmission. In a transmit operation, the TDRE flag is set to 1 at the same time as the TEND flag in SSR is set, and a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. In the event of an error, the SCI retransmits the same data automatically. During this period, the TEND flag remains cleared to 0. Therefore, the SCI and DTC will automatically transmit the specified number of bytes in the event of an error, including retransmission. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. nth transfer frame Transfer frame n+1 Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 TDRE Transfer to TSR from TDR Transfer to TSR from TDR Transfer to TSR from TDR TEND [2] [3] FER/ERS [1] [3] Figure 10.26 Retransfer Operation in SCI Transmit Mode Rev. 2.00, 03/04, page 267 of 508 The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in Figure 10.27. I/O data Ds D0 TXI (TEND interrupt) D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5 etu When GM = 0 11.0 etu When GM = 1 [Legend] Ds: D0 to D7: Dp: DE: Start bit Data bits Parity bit Error signal Figure 10.27 TEND Flag Generation Timing in Transmission Operation Rev. 2.00, 03/04, page 268 of 508 Start Initialization Start transmission ERS = 0? No Yes Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted ? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 10.28 Example of Transmission Processing Flow Rev. 2.00, 03/04, page 269 of 508 10.7.7 Serial Data Reception (Except for Block Transfer Mode) Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 10.29 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. 2. The RDRF bit in SSR is not set for a frame in which an error has occurred. 3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. Figure 10.30 shows a flowchart for reception. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If an error occurs in receive mode and the ORER or PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. Hence, so the error flag must be cleared to 0. Even when a parity error occurs in receive mode and the PER flag is set to 1, the data that has been received is transferred to RDR and can be read from there. Note: For details on receive operations in block transfer mode, see section 10.4, Operation in Asynchronous Mode. nth transfer frame Transfer frame n+1 Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 RDRF [2] [3] [1] [3] PER Figure 10.29 Retransfer Operation in SCI Receive Mode Rev. 2.00, 03/04, page 270 of 508 Start Initialization Start reception ORER = 0 and PER = 0 No Yes Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 10.30 Example of Reception Processing Flow 10.7.8 Clock Output Control When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and CKE1 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 10.31 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled. CKE0 SCK Specified pulse width Specified pulse width Figure 10.31 Timing for Fixing Clock Output Level Rev. 2.00, 03/04, page 271 of 508 When turning on the power or switching between Smart Card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty. Powering On: To secure clock duty from power-on, the following switching procedure should be followed. 1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. 2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR. 3. Set SMR and SCMR, and switch to smart card mode operation. 4. Set the CKE0 bit in SCR to 1 to start clock output. When Changing from Smart Card Interface Mode to Software Standby Mode: 1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. 2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to halt the clock. 4. Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty preserved. 5. Make the transition to the software standby state. When Returning to Smart Card Interface Mode from Software Standby Mode: 1. Exit the software standby state. 2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the normal duty. Software standby Normal operation [1] [2] [3] [4] [5] Normal operation [6] [7] Figure 10.32 Clock Halt and Restart Procedure Rev. 2.00, 03/04, page 272 of 508 10.8 Interrupts 10.8.1 Interrupts in Normal Serial Communication Interface Mode Table 10.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. A TEI interrupt is requested when the TEND flag is set to 1 and the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Table 10.12 SCI Interrupt Sources Channel Name Interrupt Source Interrupt Flag 0 ERI0 Receive Error ORER, FER, PER RXI0 Receive Data Full RDRF TXI0 Transmit Data Empty TDRE TEI0 Transmission End TEND ERI1 Receive Error ORER, FER, PER RXI1 Receive Data Full RDRF TXI1 Transmit Data Empty TDRE TEI1 Transmission End TEND 1 Rev. 2.00, 03/04, page 273 of 508 10.8.2 Interrupts in Smart Card Interface Mode Table 10.13 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt (TEI) request cannot be used in this mode. Table 10.13 SCI Interrupt Sources Channel Name Interrupt Source Interrupt Flag 0 ERI0 Receive Error, detection ORER, PER, ERS RXI0 Receive Data Full RDRF TXI0 Transmit Data Empty TEND 1 ERI1 Receive Error, detection ORER, PER, ERS RXI1 Receive Data Full RDRF TXI1 Transmit Data Empty TEND In transmit operations, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR is set, and a TXI interrupt is generated. In the event of an error, the SCI retransmits the same data automatically. During this period, the TEND flag remains cleared to 0. The ERS flag is not cleared automatically when an error occurs. Hence, the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If an error occurs, an error flag is set but the RDRF flag is not. An ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. 10.9 Usage Notes 10.9.1 Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 19, Power-Down Modes. 10.9.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Rev. 2.00, 03/04, page 274 of 508 10.9.3 Mark State and Break Detection When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both DDR and DR to 1. As TE is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 10.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Rev. 2.00, 03/04, page 275 of 508 Rev. 2.00, 03/04, page 276 of 508 Section 11 Controller Area Network (HCAN) The HCAN is a module for controlling a controller area network (CAN) for realtime communication in vehicular and industrial equipment systems, etc. For details on CAN specification, see Bosch CAN Specification Version 2.0 1991, Robert Bosch GmbH. The block diagram of the HCAN is shown in figure 11.1. 11.1 Features * CAN version: Bosch 2.0B active compatible Communication systems: NRZ (Non-Return to Zero) system (with bit-stuffing function) Broadcast communication system Transmission path: Bidirectional 2-wire serial communication Communication speed: Max. 1 Mbps Data length: 0 to 8 bytes * Number of channels: 1 * Data buffers: 16 (one receive-only buffer and 15 buffers settable for transmission/reception) * Data transmission: Two methods Mailbox (buffer) number order (low-to-high) Message priority (identifier) reverse-order (high-to-low) * Data reception: Two methods Message identifier match (transmit/receive-setting buffers) Reception with message identifier masked (receive-only) * CPU interrupts: 12 Error interrupt Reset processing interrupt Message reception interrupt Message transmission interrupt * HCAN operating modes * Support for various modes Hardware reset Software reset Normal status (error-active, error-passive) Bus off status HCAN configuration mode HCAN sleep mode HCAN halt mode IFCAN00B_000020020200 Rev. 2.00, 03/04, page 277 of 508 * Module stop mode can be set Peripheral data bus Peripheral address bus HCAN MBI Message buffer Mailboxes Message control Message data MC0-MC15, MD0-MD15 LAFM (CDLC) CAN Data Link Controller Bosch CAN 2.0B active HTxD Tx buffer MPI Microprocessor interface Rx buffer HRxD CPU interface Control register Status register Figure 11.1 HCAN Block Diagram * Message Buffer Interface (MBI) The MBI, consisting of mailboxes and a local acceptance filter mask (LAFM), stores CAN transmit/received messages (identifiers, data, etc.) Transmit messages are written by the CPU. For received messages, the data received by the CDLC is stored automatically. * Microprocessor Interface (MPI) The MPI, consisting of a bus interface, control register, status register, etc., controls HCAN internal data, status, and so forth. * CAN Data Link Controller (CDLC) The CDLC transmits and receives of messages conforming to the Bosch CAN Ver. 2.0B active standard (data frames, remote frames, error frames, overload frames, inter-frame spacing), as well as CRC checking, bus arbitration, and other functions. Rev. 2.00, 03/04, page 278 of 508 11.2 Input/Output Pins Table 11.1 shows the HCAN's pins. When using HCAN pins, settings must be made in the HCAN configuration mode (during initialization: MCR0 = 1 and GSR3 = 1). Table 11.1 Pin Configuration Name Abbreviation Input/Output Function HCAN transmit data pin HTxD Output CAN bus transmission pin HCAN receive data pin HRxD Input CAN bus reception pin A bus driver is necessary for the interface between the pins and the CAN bus. A Philips PCA82C250 compatible model is recommended. 11.3 Register Descriptions The HCAN has the following registers. * * * * * * * * * * * * * * * * * * * * Master control register (MCR) General status register (GSR) Bit configuration register (BCR) Mailbox configuration register (MBCR) Transmit wait register (TXPR) Transmit wait cancel register (TXCR) Transmit acknowledge register (TXACK) Abort acknowledge register (ABACK) Receive complete register (RXPR) Remote request register (RFPR) Interrupt register (IRR) Mailbox interrupt mask register (MBIMR) Interrupt mask register (IMR) Receive error counter (REC) Transmit error counter (TEC) Unread message status register (UMSR) Local acceptance filter mask H (LAFMH) Local acceptance filter mask L (LAFML) Message control (8-bit x 8 registers x 16 sets) (MC0 to MC15) Message data (8-bit x 8 registers x 16 sets) (MD0 to MD15) Rev. 2.00, 03/04, page 279 of 508 11.3.1 Master Control Register (MCR) MCR controls the HCAN. Bit Bit Name Initial Value R/W Description 7 MCR7 0 R/W HCAN Sleep Mode Release When this bit is set to 1, the HCAN automatically exits HCAN sleep mode on detection of CAN bus operation. 6 0 R Reserved This bit is always read as 0. The write value should always be 0. 5 MCR5 0 R/W HCAN Sleep Mode When this bit is set to 1, the HCAN transits to HCAN sleep mode. When this bit is cleared to 0, HCAN sleep mode is released. 4, 3 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 MCR2 0 R/W Message Transmission Method 0: Transmission order determined by message identifier priority 1: Transmission order determined by mailbox (buffer) number priority (TXPR1 > TXPR15) 1 MCR1 0 R/W Halt Request When this bit is set to 1, the HCAN transits to HCAN HALT mode. When this bit is cleared to 0, HCAN HALT mode is released. 0 MCR0 1 R/W Reset Request When this bit is set to 1, the HCAN transits to reset mode. For details, see section 11.4.1, Hardware Reset and Software Resets. [Setting conditions] * Power-on reset * Hardware standby * Software standby * 1-write (software reset) [Clearing condition] * Rev. 2.00, 03/04, page 280 of 508 When 0 is written to this bit while the GSR3 bit in GSR is 1 11.3.2 General Status Register (GSR) GSR indicates the status of the CAN bus. Bit Bit Name 7 to 4 Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 3 GSR3 1 R Reset Status Bit Indicates whether the HCAN module is in the normal operating state or the reset state. This bit cannot be modified. [Setting conditions] * When entering configuration mode after the HCAN internal reset has finished * Sleep mode [Clearing condition] * 2 GSR2 1 R When entering normal operation mode after the MCR0 bit in MCR is cleared to 0 (Note that there is a delay between clearing of the MCR0 bit and the GSR3 bit.) Message Transmission Status Flag Flag that indicates whether the module is currently in the message transmission period. This bit cannot be modified. [Setting condition] * Third bit of Intermission after EOF(END of Frame) [Clearing condition] * 1 GSR1 0 R Start of message transmission (SOF) Transmit/Receive Warning Flag This bit cannot be modified. [Setting condition] * When TEC 96 or REC 96 [Clearing condition] * When TEC < 96 and REC < 96 or TEC 256 Rev. 2.00, 03/04, page 281 of 508 Bit Bit Name Initial Value R/W 0 GSR0 0 R Description Bus Off Flag This bit cannot be modified. [Setting condition] * When TEC 256 (bus off state) [Clearing condition] * 11.3.3 Recovery from bus off state Bit Configuration Register (BCR) BCR that is used to set HCAN bit timing parameters and the baud rate prescaler. For details on parameters, see section 11.4.2, Initialization after Hardware Reset. Bit Bit Name Initial Value R/W Description 15 BCR7 0 R/W Re-Synchronization Jump Width (SJW) 14 BCR6 0 R/W Set the maximum bit synchronization width. 00: 1 time quantum 01: 2 time quanta 10: 3 time quanta 11: 4 time quanta 13 BCR5 0 R/W Baud Rate Prescaler (BRP) 12 BCR4 0 R/W Set the length of time quanta. 11 BCR3 0 R/W 000000: 2 x system clock 10 BCR2 0 R/W 000001: 4 x system clock 9 BCR1 0 R/W 000010: 6 x system clock 8 BCR0 0 R/W : 111111: 128 x system clock 7 BCR15 0 R/W Bit Sample Point (BSP) Sets the point at which data is sampled. 0: Bit sampling at one point (end of time segment 1 (TSEG1)) 1: Bit sampling at three points (end of TSEG1 and preceding and following time quanta) Rev. 2.00, 03/04, page 282 of 508 Bit Bit Name Initial Value R/W Description 6 BCR14 0 R/W Time Segment 2 (TSEG2) 5 BCR13 0 R/W 4 BCR12 0 R/W Set the TSEG2 width within a range of 2 to 8 time quanta. 000: Setting prohibited 001: 2 time quanta 010: 3 time quanta 011: 4 time quanta 100: 5 time quanta 101: 6 time quanta 110: 7 time quanta 111: 8 time quanta 3 BCR11 0 R/W Time Segment 1 (TSEG1) 2 BCR10 0 R/W 1 BCR9 0 R/W Set the TSEG1 (PRSEG + PHSEG1) width to between 4 and 16 time quanta. 0 BCR8 0 R/W 0000: Setting prohibited 0001: Setting prohibited 0010: Setting prohibited 0011: 4 time quanta 0100: 5 time quanta 0101: 6 time quanta 0110: 7 time quanta 0111: 8 time quanta 1000: 9 time quanta 1001: 10 time quanta 1010: 11 time quanta 1011: 12 time quanta 1100: 13 time quanta 1101: 14 time quanta 1110: 15 time quanta 1111: 16 time quanta Rev. 2.00, 03/04, page 283 of 508 11.3.4 Mailbox Configuration Register (MBCR) MBCR is used to set the transfer direction for each mailbox. Bit Bit Name Initial Value R/W Description 15 MBCR7 0 R/W 14 MBCR6 0 R/W 13 MBCR5 0 R/W These bits set the transfer direction for the corresponding mailboxes from 1 to 15. MBCRn determines the transfer direction for mailbox n (n =1 to 15). 12 MBCR4 0 R/W 0: Corresponding mailbox is set for transmission 11 MBCR3 0 R/W 1: Corresponding mailbox is set for reception 10 MBCR2 0 R/W 9 MBCR1 0 R/W Bit 8 is reserved. This bit is always read as 1 and the write value should always be 1. 8 1 R 7 MBCR15 0 R/W 6 MBCR14 0 R/W 5 MBCR13 0 R/W 4 MBCR12 0 R/W 3 MBCR11 0 R/W 2 MBCR10 0 R/W 1 MBCR9 0 R/W 0 MBCR8 0 R/W Rev. 2.00, 03/04, page 284 of 508 11.3.5 Transmit Wait Register (TXPR) TXPR is used to set a transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait). Bit Bit Name Initial Value R/W Description 15 TXPR7 0 R/W 14 TXPR6 0 R/W 13 TXPR5 0 R/W These bits set a transmit wait (CAN bus arbitration wait) for the corresponding mailboxes 1 to 15. When TXPRn (n = 1 to 15) is set to 1, the message in mailbox n becomes the transmit wait state. 12 TXPR4 0 R/W [Clearing conditions] 11 TXPR3 0 R/W * Completion of message transmission 10 TXPR2 0 R/W * Completion of transmission cancellation 9 TXPR1 0 R/W 8 0 R Bit 8 is reserved. This bit is always read as 1 and the write value should always be 1. 7 TXPR15 0 R/W 6 TXPR14 0 R/W 5 TXPR13 0 R/W 4 TXPR12 0 R/W 3 TXPR11 0 R/W 2 TXPR10 0 R/W 1 TXPR9 0 R/W 0 TXPR8 0 R/W Rev. 2.00, 03/04, page 285 of 508 11.3.6 Transmit Wait Cancel Register (TXCR) TXCR controls the cancellation of transmit wait messages in mailboxes (buffers). Bit Bit Name Initial Value R/W Description 15 TXCR7 0 R/W 14 TXCR6 0 R/W 13 TXCR5 0 R/W These bits cancel the transmit wait message in the corresponding mailboxes 1 to 15. When TXCRn (n = 1 to 15) is set to 1, the transmit wait message in mailbox n is canceled. 12 TXCR4 0 R/W [Clearing condition] 11 TXCR3 0 R/W * 10 TXCR2 0 R/W 9 TXCR1 0 R/W 8 0 R 7 TXCR15 0 R/W 6 TXCR14 0 R/W 5 TXCR13 0 R/W 4 TXCR12 0 R/W 3 TXCR11 0 R/W 2 TXCR10 0 R/W 1 TXCR9 0 R/W 0 TXCR8 0 R/W Rev. 2.00, 03/04, page 286 of 508 Completion of TXPR clearing when transmit message is canceled normally Bit 8 is reserved. This bit is always read as 0 and the write value should always be 0. 11.3.7 Transmit Acknowledge Register (TXACK) TXACK contains status flags that indicate the normal transmission of mailbox (buffer) transmit messages. Bit Bit Name Initial Value 15 TXACK7 0 14 TXACK6 0 13 TXACK5 0 12 TXACK4 0 R/(W)* These bits are status flags that indicate error-free R/(W)* transmission of the transmit message in the corresponding mailboxes 1 to 15. When the message in R/(W)* mailbox n (n = 1 to 15) has been transmitted error-free, R/(W)* TXACKn is set to 1. 11 TXACK3 0 R/(W)* [Setting condition] 10 TXACK2 0 R/(W)* * 9 TXACK1 0 R/(W)* 8 0 R 7 TXACK15 0 6 TXACK14 0 5 TXACK13 0 R/(W)* * Writing 1 R/(W)* Bit 8 is reserved. This bit is always read as 0 and the write value should always be 0. R/(W)* 4 TXACK12 0 R/(W)* 3 TXACK11 0 R/(W)* 2 TXACK10 0 R/(W)* 1 TXACK9 0 R/(W)* 0 TXACK 0 R/(W)* R/W Description Completion of message transmission for corresponding mailbox [Clearing condition] Note: Only 0 for clearing the flag can be written. Rev. 2.00, 03/04, page 287 of 508 11.3.8 Abort Acknowledge Register (ABACK) ABACK contains status flags that indicate the normal cancellation (aborting) of mailbox (buffer) transmit messages. Bit Bit Name Initial Value 15 ABACK7 0 14 ABACK6 0 13 ABACK5 0 12 ABACK4 0 R/(W)* These bits are status flags that indicate error-free R/(W)* cancellation (abortion) of the transmit message in the corresponding mailboxes 1 to 15. When the message in R/(W)* mailbox n (n = 1 to 15) has been canceled error-free, R/(W)* ABACKn is set to 1. 11 ABACK3 0 R/(W)* [Setting condition] 10 ABACK2 0 R/(W)* * 9 ABACK1 0 R/(W)* 8 0 R 7 ABACK15 0 6 ABACK14 0 5 ABACK13 0 R/(W)* * Writing 1 R/(W)* Bit 8 is reserved. This bit is always read as 0. The write value should always be 0. R/(W)* 4 ABACK12 0 R/(W)* 3 ABACK11 0 R/(W)* 2 ABACK10 0 R/(W)* 1 ABACK9 0 R/(W)* 0 ABACK8 0 R/(W)* R/W Description Completion of transmit message cancellation for corresponding mailbox [Clearing condition] Note: Only 0 for clearing the flag can be written. Rev. 2.00, 03/04, page 288 of 508 11.3.9 Receive Complete Register (RXPR) RXPR contains status flags that indicate the normal reception of messages in mailboxes (buffers). For reception of a remote frame, when a bit in this register is set to 1, the corresponding remote request register (RFPR) bit is also set to 1 simultaneously. Bit Bit Name Initial Value 15 RXPR7 0 14 RXPR6 0 13 RXPR5 0 R/(W)* When the message in mailbox n (n = 0 to 15) has been R/(W)* received error-free, RXPRn is set to 1. R/(W)* [Setting condition] 12 RXPR4 0 R/(W)* * 11 RXPR3 0 R/(W)* 10 RXPR2 0 R/(W)* 9 RXPR1 0 R/(W)* 8 RXPR0 0 R/(W)* 7 RXPR15 0 R/(W)* 6 RXPR14 0 R/(W)* 5 RXPR13 0 R/(W)* 4 RXPR12 0 R/(W)* 3 RXPR11 0 R/(W)* 2 RXPR10 0 R/(W)* 1 RXPR9 0 R/(W)* 0 RXPR8 0 R/(W)* R/W Description Completion of message (data frame or remote frame) reception in corresponding mailbox [Clearing condition] * Writing 1 Note: Only 0 for clearing the flag can be written. Rev. 2.00, 03/04, page 289 of 508 11.3.10 Remote Request Register (RFPR) RFPR contains status flags that indicate normal reception of remote frames in mailboxes (buffers). When a bit in this register is set to 1, the corresponding receive complete register (RXPR) bit is also set to 1 simultaneously. Bit Bit Name Initial Value 15 RFPR7 0 14 RFPR6 0 13 RFPR5 0 R/(W)* When mailbox n (n = 0 to 15) has received the remote R/(W)* frame error-free, ABACKn (n = 0 to 15) is set to 1. R/(W)* [Setting condition] 12 RFPR4 0 R/(W)* * 11 RFPR3 0 R/(W)* 10 RFPR2 0 R/(W)* 9 RFPR1 0 R/(W)* 8 RFPR0 0 R/(W)* 7 RFPR15 0 R/(W)* 6 RFPR14 0 R/(W)* 5 RFPR13 0 R/(W)* 4 RFPR12 0 R/(W)* 3 RFPR11 0 R/(W)* 2 RFPR10 0 R/(W)* 1 RFPR9 0 R/(W)* 0 RFPR8 0 R/(W)* R/W Description Completion of remote frame reception in corresponding mailbox [Clearing condition] * Writing 1 Note: Only 0 for clearing the flag can be written. Rev. 2.00, 03/04, page 290 of 508 11.3.11 Interrupt Register (IRR) IRR is an interrupt status flag register. Bit Bit Name Initial Value R/W 15 IRR7 0 R/(W)* Overload Frame Interrupt Flag Description [Setting condition] * When an overload frame is transmitted in error active/passive state [Clearing condition] * 14 IRR6 0 Writing 1 R/(W)* Bus Off Interrupt Flag Status flag indicating the bus off state caused by the transmit error counter. [Setting condition] * When TEC 256 [Clearing condition] * 13 IRR5 0 Writing 1 R/(W)* Error Passive Interrupt Flag Status flag indicating the error passive state caused by the transmit/receive error counter. [Setting condition] * When TEC 128 or REC 128 [Clearing condition] * 12 IRR4 0 Writing 1 R/(W)* Receive Overload Warning Interrupt Flag Status flag indicating the error warning state caused by the receive error counter. [Setting condition] * When REC 96 [Clearing condition] * Writing 1 Rev. 2.00, 03/04, page 291 of 508 Bit Bit Name Initial Value R/W 11 IRR3 0 R/(W)* Transmit Overload Warning Interrupt Flag Description Status flag indicating the error warning state caused by the transmit error counter. [Setting condition] * When TEC 96 [Clearing condition] * 10 IRR2 0 R Writing 1 Remote Frame Request Interrupt Flag Status flag indicating that a remote frame has been received in a mailbox (buffer). [Setting condition] * When remote frame reception is completed, when corresponding MBIMR = 0 [Clearing condition] * 9 IRR1 0 R Clearing of all bits in RFPR (remote request register) Received message Interrupt Flag Status flag indicating that a mailbox (buffer) received message has been received normally. [Setting condition] * When data frame or remote frame reception is completed, when corresponding MBIMR = 0 [Clearing condition] * 8 IRR0 1 Clearing of all bits in RXPR (receive complete register) R/(W)* Reset Interrupt Flag Status flag indicating that the HCAN module has been reset. This bit cannot be masked by the interrupt mask register (IMR). If this bit is not cleared to 0 after entering power-on reset or returning from software standby mode, interrupt processing will start immediately when the interrupt controller enables interrupts. [Setting condition] * When the reset operation has finished after entering power-on reset or software standby mode [Clearing condition] * Rev. 2.00, 03/04, page 292 of 508 Writing 1 Bit Bit Name 7 to 5 Initial Value R/W Description All 0 Reserved These bits are always read as 0. The write value should always be 0. 4 IRR12 0 R/(W)* Bus Operation Interrupt Flag Status flag indicating detection of a dominant bit due to bus operation when the HCAN module is in HCAN sleep mode. [Setting condition] * Bus operation (dominant bit) detection in HCAN sleep mode [Clearing condition] * 3, 2 All 0 Writing 1 Reserved These bits are always read as 0. The write value should always be 0. 1 IRR9 0 R Unread Interrupt Flag Status flag indicating that a received message has been overwritten before being read. [Setting condition] * When UMSR (unread message status register) is set [Clearing condition] * 0 IRR8 0 Clearing of all bits in UMSR (unread message status register) R/(W)* Mailbox Empty Interrupt Flag Status flag indicating that the next transmit message can be stored in the mailbox. [Setting condition] * When TXPR (transmit wait register) is cleared by completion of transmission or completion of transmission abort [Clearing condition] * Writing 1 Note: Only 0 for clearing the flag can be written. Rev. 2.00, 03/04, page 293 of 508 11.3.12 Mailbox Interrupt Mask Register (MBIMR) MBIMR controls the enabling or disabling of individual mailbox (buffer) interrupt requests. Bit Bit Name Initial Value R/W Description 15 MBIMR7 0 R/W Mailbox Interrupt Mask (MBIMRx) 14 MBIMR6 0 R/W 13 MBIMR5 0 R/W 12 MBIMR4 0 R/W When MBIMRn (n = 0 to 15) is cleared to 0, the interrupt request in mailbox n is enabled. When set to 1, the interrupt request is masked. 11 MBIMR3 0 R/W 10 MBIMR2 0 R/W 9 MBIMR1 0 R/W 8 MBIMR0 0 R/W 7 MBIMR15 0 R/W 6 MBIMR14 0 R/W 5 MBIMR13 0 R/W 4 MBIMR12 0 R/W 3 MBIMR11 0 R/W 2 MBIMR10 0 R/W 1 MBIMR9 0 R/W 0 MBIMR8 0 R/W Rev. 2.00, 03/04, page 294 of 508 The interrupt source in a transmit mailbox is TXPR clearing caused by transmission end or transmission cancellation. The interrupt source in a receive mailbox is RXPR setting on reception end. 11.3.13 Interrupt Mask Register (IMR) IMR contains flags that enable or disable requests by individual interrupt sources. The interrupt flag cannot be masked. Bit Bit Name Initial Value R/W Description 15 IMR7 1 R/W Overload Frame Interrupt Mask When this bit is cleared to 0, OVR0 (interrupt request by IRR7) is enabled. When set to 1, OVR0 is masked. 14 IMR6 1 R/W Bus Off Interrupt Mask When this bit is cleared to 0, ERS0 (interrupt request by IRR6) is enabled. When set to 1, ERS0 is masked. 13 IMR5 1 R/W Error Passive Interrupt Mask When this bit is cleared to 0, ERS0 (interrupt request by IRR5) is enabled. When set to 1, ERS0 is masked. 12 IMR4 1 R/W Receive Overload Warning Interrupt Mask When this bit is cleared to 0, OVR0 (interrupt request by IRR4) is enabled. When set to 1, OVR0 is masked. 11 IMR3 1 R/W Transmit Overload Warning Interrupt Mask When this bit is cleared to 0, OVR0 (interrupt request by IRR3) is enabled. When set to 1, OVR0 is masked. 10 IMR2 1 R/W Remote Frame Request Interrupt Mask When this bit is cleared to 0, OVR0 (interrupt request by IRR2) is enabled. When set to 1, OVR0is masked. 9 IMR1 1 R/W Received message Interrupt Mask When this bit is cleared to 0, RM1 (interrupt request by IRR1) is enabled. When set to 1, RMI is masked. 8 0 R Reserved This bit is always read as 0. Only 0 should be written to this bit. 7 to 5 All 1 R Reserved These bits are always read as 1. The write value should always be 0. Rev. 2.00, 03/04, page 295 of 508 Bit Bit Name Initial Value R/W 4 IMR12 1 R/W Description Bus Operation Interrupt Mask When this bit is cleared to 0, OVR0 (interrupt request by IRR12) is enabled. When set to 1, OVR0 is masked. 3, 2 All 1 R Reserved These bits are always read as 1. The write value should always be 0. 1 IMR9 1 R/W Unread Interrupt Mask When this bit is cleared to 0, OVR0 (interrupt request by IRR9) is enabled. When set to 1, OVR0 is masked. 0 IMR8 1 R/W Mailbox Empty Interrupt Mask When this bit is cleared to 0, SLE0 (interrupt request by IRR8) is enabled. When set to 1, SLE0 is masked. 11.3.14 Receive Error Counter (REC) REC is an 8-bit read-only register that functions as a counter indicating the number of received message errors on the CAN bus. The count value is stipulated in the CAN protocol. 11.3.15 Transmit Error Counter (TEC) TEC is an 8-bit read-only register that functions as a counter indicating the number of transmit message errors on the CAN bus. The count value is stipulated in the CAN protocol. Rev. 2.00, 03/04, page 296 of 508 11.3.16 Unread Message Status Register (UMSR) UMSR contains status flags that indicate, for individual mailboxes (buffers), that a received message has been overwritten by a new received message before being read. When overwritten by a new message, data in the unread received message is lost. Bit Bit Name Initial Value 15 UMSR7 0 R/(W)* [Setting condition] 14 UMSR6 0 R/(W)* * 13 UMSR5 0 R/(W)* 12 UMSR4 0 R/(W)* [Clearing condition] 11 UMSR3 0 R/(W)* * 10 UMSR2 0 R/(W)* 9 UMSR1 0 R/(W)* 8 UMSR0 0 R/(W)* 7 UMSR15 0 R/(W)* 6 UMSR14 0 R/(W)* 5 UMSR13 0 R/(W)* 4 UMSR12 0 R/(W)* 3 UMSR11 0 R/(W)* 2 UMSR10 0 R/(W)* 1 UMSR9 0 R/(W)* 0 UMSR8 0 R/(W)* Note: * R/W Description When a new message is received before RXPR is cleared Writing 1 Only 1 is writable to clear the flag. Rev. 2.00, 03/04, page 297 of 508 11.3.17 Local Acceptance Filter Masks (LAFML, LAFMH) LAFML and LAFMH individually set the identifier bits of the message to be stored in mailbox 0 as Don't Care. For details, see section 11.4.4, Message Reception. The relationship between the identifier bits and mask bits are shown in the following. * LAFML Bit Bit Name Initial Value R/W Description 15 LAFML7 0 R/W When this bit is set to 1, ID-7 of the received message identifier is not compared. 14 LAFML6 0 R/W When this bit is set to 1, ID-6 of the received message identifier is not compared. 13 LAFML5 0 R/W When this bit is set to 1, ID-5 of the received message identifier is not compared. 12 LAFML4 0 R/W When this bit is set to 1, ID-4 of the received message identifier is not compared. 11 LAFML3 0 R/W When this bit is set to 1, ID-3 of the received message identifier is not compared. 10 LAFML2 0 R/W When this bit is set to 1, ID-2 of the received message identifier is not compared. 9 LAFML1 0 R/W When this bit is set to 1, ID-1 of the received message identifier is not compared. 8 LAFML0 0 R/W When this bit is set to 1, ID-0 of the received message identifier is not compared. 7 LAFML15 0 R/W When this bit is set to 1, ID-15 of the received message identifier is not compared. 6 LAFML14 0 R/W When this bit is set to 1, ID-14 of the received message identifier is not compared. 5 LAFML13 0 R/W When this bit is set to 1, ID-13 of the received message identifier is not compared. 4 LAFML12 0 R/W When this bit is set to 1, ID-12 of the received message identifier is not compared. 3 LAFML11 0 R/W When this bit is set to 1, ID-11 of the received message identifier is not compared. 2 LAFML10 0 R/W When this bit is set to 1, ID-10 of the received message identifier is not compared. 1 LAFML9 0 R/W When this bit is set to 1, ID-9 of the received message identifier is not compared. 0 LAFML8 0 R/W When this bit is set to 1, ID-8 of the received message identifier is not compared. Rev. 2.00, 03/04, page 298 of 508 * LAFMH Bit Bit Name Initial Value R/W Description 15 LAFMH7 0 R/W When this bit is set to 1, ID-20 of the received message identifier is not compared. 14 LAFMH6 0 R/W When this bit is set to 1, ID-19 of the received message identifier is not compared. 13 LAFMH5 0 R/W When this bit is set to 1, ID-18 of the received message identifier is not compared. All 0 R Reserved 12 to 10 These bits are always read as 0. Only 0 should be written to these bits. 9 LAFMH1 0 R/W When this bit is set to 1, ID-17 of the received message identifier is not compared. 8 LAFMH0 0 R/W When this bit is set to 1, ID-16 of the received message identifier is not compared. 7 LAFMH15 0 R/W When this bit is set to 1, ID-28 of the received message identifier is not compared. 6 LAFMH14 0 R/W When this bit is set to 1, ID-27 of the received message identifier is not compared. 5 LAFMH13 0 R/W When this bit is set to 1, ID-26 of the received message identifier is not compared. 4 LAFMH12 0 R/W When this bit is set to 1, ID-25 of the received message identifier is not compared. 3 LAFMH11 0 R/W When this bit is set to 1, ID-24 of the received message identifier is not compared. 2 LAFMH10 0 R/W When this bit is set to 1, ID-23 of the received message identifier is not compared. 1 LAFMH9 0 R/W When this bit is set to 1, ID-22 of the received message identifier is not compared. 0 LAFMH8 0 R/W When this bit is set to 1, ID-21 of the received message identifier is not compared. Rev. 2.00, 03/04, page 299 of 508 11.3.18 Message Control (MC0 to MC15) The message control register sets consist of eight 8-bit registers for one mailbox. The HCAN has 16 sets of these registers. Because message control registers are in RAM, their initial values after power-on are undefined. Be sure to initialize them by writing 0 or 1. Figure 11.2 shows the register names for each mailbox. Mail box 0 MC0[1] MC0[2] MC0[3] MC0[4] MC0[5] MC0[6] MC0[7] MC0[8] Mail box 1 MC1[1] MC1[2] MC1[3] MC1[4] MC1[5] MC1[6] MC1[7] MC1[8] Mail box 2 MC2[1] MC2[2] MC2[3] MC2[4] MC2[5] MC2[6] MC2[7] MC2[8] Mail box 3 MC3[1] MC3[2] MC3[3] MC3[4] MC3[5] MC3[6] MC3[7] MC3[8] Mail box 15 MC15[1] MC15[2] MC15[3] MC15[4] MC15[5] MC15[6] MC15[7] MC15[8] Figure 11.2 Message Control Register Configuration The settings of message control registers are shown in the following. Figures 11.3 and 11.4 show the correspondence between the identifiers and register bit names. SOF ID-28 ID-27 ID-18 RTR IDE R0 identifier Figure 11.3 Standard Format SOF ID-28 ID-27 ID-18 Standard identifier SRR IDE ID-17 ID-16 Extended identifier Figure 11.4 Extended Format Rev. 2.00, 03/04, page 300 of 508 ID-0 RTR R1 Register Name Bit MCx[1] Bit Name 7 to 4 R/W Description R/W The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). 3 to 0 DLC3 to DLC0 R/W Data Length Code Set the data length of a data frame or the data length requested in a remote frame within the range of 0 to 8 bits. 0000: 0 byte 0001: 1 byte 0010: 2 bytes 0011: 3 bytes 0100: 4 bytes 0101: 5 bytes 0110: 6 bytes 0111: 7 bytes 1000: 8 bytes : : 1111: 8 bytes MCx[2] 7 to 0 MCx[3] 7 to 0 R/W The initial value of these bits is undefined; they must be initialized (by writing 0 or 1). R/W MCx[4] 7 to 0 R/W MCx[5] 7 to 5 ID-20 to ID-18 R/W Sets ID-20 to ID-18 in the identifier. 4 RTR R/W Remote Transmission Request Used to distinguish between data frames and remote frames. 0: Data frame 1: Remote frame 3 IDE R/W Identifier Extension Used to distinguish between the standard format and extended format of data frames and remote frames. 0: Standard format 1: Extended format 2 R/W The initial value of this bit is undefined. It must be initialized by writing 0 or 1. 1 to 0 ID-17 to ID-16 R/W Sets ID-17 and ID-16 in the identifier. MCx[6] 7 to 0 ID-28 to ID-21 R/W Sets ID-28 to ID-21 in the identifier. MCx[7] 7 to 0 ID-7 to ID-0 R/W Sets ID-7 to ID-0 in the identifier. MCx[8] 7 to 0 ID-15 to ID-8 R/W Sets ID-15 to ID-8 in the identifier. [Legend] x: Mailbox number Rev. 2.00, 03/04, page 301 of 508 11.3.19 Message Data (MD0 to MD15) The message data register sets consist of eight 8-bit registers for one mailbox. The HCAN has 16 sets of these registers. Because message data registers are in RAM, their initial values after poweron are undefined. Be sure to initialize them by writing 0 or 1. Figure 11.5 shows the register names for each mailbox. Mail box 0 MD0[1] MD0[2] MD0[3] MD0[4] MD0[5] MD0[6] MD0[7] MD0[8] Mail box 1 MD1[1] MD1[2] MD1[3] MD1[4] MD1[5] MD1[6] MD1[7] MD1[8] Mail box 2 MD2[1] MD2[2] MD2[3] MD2[4] MD2[5] MD2[6] MD2[7] MD2[8] Mail box 3 MD3[1] MD3[2] MD3[3] MD3[4] MD3[5] MD3[6] MD3[7] MD3[8] Mail box 15 MD15[1] MD15[2] MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8] Figure 11.5 Message Data Configuration Rev. 2.00, 03/04, page 302 of 508 11.4 Operation 11.4.1 Hardware and Software Resets The HCAN can be reset by a hardware reset or software reset. * Hardware Reset At power-on reset, or in hardware or software standby mode, the HCAN is initialized by automatically setting the MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3) in GSR. At the same time, all internal registers, except for message control and message data registers, are initialized by a hardware reset. * Software Reset The HCAN can be reset by setting the MCR reset request bit (MCR0) in MCR via software. In a software reset, the error counters (TEC and REC) are initialized, however other registers are not. If the MCR0 bit is set while the CAN controller is performing a communication operation (transmission or reception), the initialization state is not entered until message transfer has been completed. The reset status bit (GSR3) in GSR is set on completion of initialization. 11.4.2 Initialization after Hardware Reset After a hardware reset, the following initialization processing should be carried out: 1. 2. 3. 4. 5. Clearing of IRR0 bit in the interrupt register (IRR) Bit rate setting Mailbox transmit/receive settings Mailbox (RAM) initialization Message transmission method setting These initial settings must be made while the HCAN is in bit configuration mode. Configuration mode is a state in which the GSR3 bit in GSR is set to 1 by a reset. Configuration mode is exited by clearing the MCR0 bit in MCR to 0; when the MCR0 bit is cleared to 0, the HCAN automatically clears the GSR3 bit in GSR. There is a delay between clearing the MCR0 bit and clearing the GSR3 bit because the HCAN needs time to be internally reset, there is a delay between clearing of the MCR0 bit and GSR3 bit. After the HCAN exits configuration mode, the power-up sequence begins, and communication with the CAN bus is possible as soon as 11 consecutive recessive bits have been detected. IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. Rev. 2.00, 03/04, page 303 of 508 Hardware reset : Settings by user : Processing by hardware MCR0 = 1 (automatic) IRR0 = 1 (automatic) GSR3 = 1 (automatic) Initialization of HCAN module Bit configuration mode Period in which BCR, MBCR, etc., are initialized Clear IRR0 BCR setting MBCR setting Mailbox initialization Message transmission method initialization MCR0 = 0 GSR3 = 0? No Yes IMR setting (interrupt mask setting) MBIMR setting (interrupt mask setting) MC[x] setting (receive identifier setting) LAFM setting (receive identifier mask setting) GSR3 = 0 & 11 recessive bits received? No Yes Can bus communication enabled Figure 11.6 Hardware Reset Flowchart Rev. 2.00, 03/04, page 304 of 508 MCR0 = 1 : Settings by user Bus idle? No : Processing by hardware Yes GSR3 = 1 (automatic) Initialization of REC and TEC only Correction BCR setting MBCR setting Mailbox (RAM) initialization Message transmission method initialization OK? No Yes GSR3 = 1? No Yes MCR0 = 0 GSR3 = 0? No Yes Correction IMR setting MBIMR setting MC[x] setting LAFM setting OK? No Yes GSR3 = 0 & 11 recessive bits received? No Yes CAN bus communication enabled Figure 11.7 Software Reset Flowchart Rev. 2.00, 03/04, page 305 of 508 Bit Rate and Bit Timing Settings: The bit rate and bit timing settings are made in the bit configuration register (BCR). Settings should be made such that all CAN controllers connected to the CAN bus have the same baud rate and bit width. The 1-bit time consists of the total of the settable time quantum (tq). 1-bit time (8-25 time quanta) SYNC_SEG PRSEG PHSEG1 PHSEG2 Time segment 2 (TSEG2) Time segment 1 (TSEG1) 1 time quantum 2-16 time quanta 2-8 time quanta Figure 11.8 Detailed Description of One Bit SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal bit edge transitions occur in this segment. PRSEG is a segment for compensating for the physical delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This segment is extended when synchronization (resynchronization) is established. PHSEG2 is a buffer segment for correcting phase drift (negative). This segment is shortened when synchronization (resynchronization) is established. Limits on the settable value (TSEG1, TSEG2, BRP, sample point, and SJW) are shown in table 11.2. Table 11.2 Limits for the Settable Value Name Time segment 1 Abbreviation TSEG1 Min. Value Max. Value 3* 2 15 3 7 Time segment 2 TSEG2 1* Baud rate prescaler BRP 0 63 Bit sample point BSP 0 1 0 3 Re-synchronization jump width SJW* 1 Notes: 1. SJW is stipulated in the CAN specifications: 3 SJW 0 2. The minimum value of TSEG2 is stipulated in the CAN specifications: TSEG2 SJW 3. The minimum value of TSEG1 is stipulated in the CAN specifications: TSEG1 > TSEG2 Rev. 2.00, 03/04, page 306 of 508 Time Quanta (TQ) is an integer multiple of the number of system clocks, and is determined by the baud rate prescaler (BRP) as follows. fCLK is the system clock frequency. TQ = 2 x (BPR setting + 1)/fCLK The following formula is used to calculate the 1-bit time and bit rate. 1-bit time = TQ x (3 + TSEG1 + TSEG2) Bit rate = 1/Bit time = fCLK/{2 x (BPR setting + 1) x (3 + TSEG1 + TSEG2)} Note: fCLK = (system clock) A BCR value is used for BRP, TSEG1, and TSEG2. Example: With a system clock of 20 MHz, a BRP setting of B'000000, a TSEG1 setting of B'0100, and a TSEG2 setting of B'011: Bit rate = 20/{2 x (0 + 1) x (3 + 4 + 3)} = 1 Mbps Table 11.3 Setting Range for TSEG1 and TSEG2 in BCR TSEG2 (BCR[14:12]) 001 010 011 100 101 110 111 Yes No No No No No TSEG1 0011 No (BCR[11:8]) 0100 No* Yes Yes No No No No 0101 No* Yes Yes Yes No No No 0110 No* Yes Yes Yes Yes No No 0111 No* Yes Yes Yes Yes Yes No 1000 No* Yes Yes Yes Yes Yes Yes 1001 No* Yes Yes Yes Yes Yes Yes 1010 No* Yes Yes Yes Yes Yes Yes 1011 No* Yes Yes Yes Yes Yes Yes 1100 No* Yes Yes Yes Yes Yes Yes 1101 No* Yes Yes Yes Yes Yes Yes 1110 No* Yes Yes Yes Yes Yes Yes 1111 No* Yes Yes Yes Yes Yes Yes Note: * Do not set a Baud Rate Prescaler (BRP) value of B'000000 (2 x system clock). Rev. 2.00, 03/04, page 307 of 508 Mailbox Transmit/Receive Settings: The HCAN has 16 mailboxes. Mailbox 0 is receive-only, while mailboxes 1 to 15 can be set for transmission or reception. The Initial status of mailboxes 1 to 15 is for transmission. Mailbox transmit/receive settings are not initialized by a software reset. Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding mailbox for transmission use, whereas a setting of 1 in MBCR designates the corresponding mailbox for reception use. When setting mailboxes for reception, in order to improve message reception efficiency, high-priority messages should be set in low-to-high mailbox order. Mailbox (Message Control/Data) Initial Settings: Message control/data are held in RAM, and so their initial values are undefined after power is supplied. Initial values must therefore be set in all the mailboxes (by writing 0s or 1s). Setting the Message Transmission Method: The following two kinds of message transmission methods are available. * Transmission order determined by message identifier priority * Transmission order determined by mailbox number priority Either of the message transmission methods can be selected with the message transmission method bit (MCR2) in the master control register (MCR): When messages are set to be transmitted according to the message identifier priority, if several messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority in the message identifier is stored in the transmit buffer. CAN bus arbitration is then carried out for the message stored in the transmit buffer, and the message is transmitted when the transmission right is acquired. When the TXPR bit is set, the highest-priority message is found and stored in the transmit buffer. When messages are set to be transmitted according to the mailbox number priority, if several messages are designated as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer in low-to-high mailbox order. CAN bus arbitration is then carried out for the message stored in the transmit buffer, and the message is transmitted when the transmission right is acquired. Rev. 2.00, 03/04, page 308 of 508 11.4.3 Message Transmission Messages are transmitted using mailboxes 1 to 15. The transmission procedure after initial settings is described below, and a transmission flowchart is shown in figure 11.9. Initialization (after hardware reset only) Clear IRR0 BCR setting MBCR setting Mailbox initialization Message transmission method setting : Settings by user : Processing by hardware Interrupt settings Transmit data setting Arbitration field setting Control field setting Data field setting Message transmission wait TXPR setting Bus idle? No Yes Message transmission GSR2 = 0 (during transmission only) Transmission completed? No Yes TXACK = 1 IRR8 = 1 IMR8 = 1? Yes No Interrupt to CPU Clear TXACK Clear IRR8 End of transmission Figure 11.9 Transmission Flowchart Rev. 2.00, 03/04, page 309 of 508 CPU Interrupt Source Settings: The CPU interrupt source is set by the interrupt mask register (IMR) and mailbox interrupt mask register (MBIMR). Transmission acknowledge and transmission abort acknowledge interrupts can be generated for individual mailboxes in the mailbox interrupt mask register (MBIMR). Arbitration Field Setting: The arbitration field is set by message control registers MCx[5]- MCx[8] in a transmit mailbox. For a standard format, an 11-bit identifier (ID-28 to ID-18) and the RTR bit are set, and the IDE bit is cleared to 0. For an extended format, a 29-bit identifier (ID-28 to ID-0) and the RTR bit are set, and the IDE bit is set to 1. Control Field Setting: In the control field, the byte length of the data to be transmitted is set within the range of zero to eight bytes. The register to be set is the message control register MCx[1] in a transmit mailbox. Data Field Setting: In the data field, the data to be transmitted is set within the range zero to eight. The registers to be set are the message data registers MDx[1]-MDx[8]. The byte length of the data to be transmitted is determined by the data length code in the control field. Even if data exceeding the value set in the control field is set in the data field, up to the byte length set in the control field will actually be transmitted. Message Transmission: If the corresponding mailbox transmit wait bit (TXPR1-TXPR15) in the transmit wait register (TXPR) is set to 1 after message control and message data registers have been set, the message enters transmit wait state. If the message is transmitted error-free, the corresponding acknowledge bit (TXACK1-TXACK15) in the transmit acknowledge register (TXACK) is set to 1, and the corresponding transmit wait bit (TXPR1-TXPR15) in the transmit wait register (TXPR) is automatically cleared to 0. Also, if the corresponding bit (MBIMR1MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are both simultaneously set to enable interrupts, interrupts may be sent to the CPU. If transmission of a transmit message is aborted in the following cases, the message is retransmitted automatically: * CAN bus arbitration failure (failure to acquire the bus) * Error during transmission (bit error, stuff error, CRC error, frame error, or ACK error) Message Transmission Cancellation: Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait message. A transmit wait message is canceled by setting the bit for the corresponding mailbox (TXCR1-TXCR15) to 1 in the transmit cancel register (TXCR). Clearing the transmit wait register (TXPR) does not cancel transmission. When cancellation is executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is set to 1 in the abort acknowledge register (ABACK). An interrupt to the CPU can be requested, and if the mailbox empty interrupt (IRR8) is enabled for the bits (MBIMR1-MBIMR15) corresponding Rev. 2.00, 03/04, page 310 of 508 to the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR), interrupts may be sent to the CPU. However, a transmit wait message cannot be canceled at the following times: * During internal arbitration or CAN bus arbitration * During data frame or remote frame transmission Figure 11.10 shows a flowchart for transmit message cancellation. Message transmit wait TXPR setting : Settings by user : Processing by hardware Set TXCR bit corresponding to message to be canceled No Cancellation possible? Yes Message not sent Clear TXCR, TXPR ABACK = 1 IRR8 = 1 IMR8 = 1? Completion of message transmission TXACK = 1 Clear TXCR, TXPR IRR8 = 1 Yes No Interrupt to CPU Clear TXACK Clear ABACK Clear IRR8 End of transmission/transmission cancellation Figure 11.10 Transmit Message Cancellation Flowchart Rev. 2.00, 03/04, page 311 of 508 11.4.4 Message Reception The reception procedure after initial settings is described below. A reception flowchart is shown in figure 11.11. Initialization : Settings by user Clear IRR0 BCR setting MBCR setting Mailbox (RAM) initialization : Processing by hardware Interrupt settings Receive data setting Arbitration field setting Local acceptance filter settings Message reception (Match of identifier in mailbox?) No Yes Yes Same RXPR = 1? Unread message No Data frame? No Yes RXPR IRR1 = 1 RXPR, RFPR = 1 IRR2 = 1, IRR1 = 1 Yes IMR1 = 1? IMR2 = 1? No No Interrupt to CPU Interrupt to CPU Message control read Message data read Message control read Message data read Clear IRR1 Clear IRR2, IRR1 Transmission of data frame corresponding to remote frame End of reception Figure 11.11 Reception Flowchart Rev. 2.00, 03/04, page 312 of 508 Yes CPU Interrupt Source Settings: CPU interrupt source settings are made in the interrupt mask register (IMR) and mailbox interrupt register (MBIMR). The message to be received is also specified. Data frame and remote frame receive wait interrupt requests can be generated for individual mailboxes in the MBIMR. Arbitration Field Setting: To receive a message, the message identifier must be set in advance in the message control registers (MCx[1]-MCx[8]) for the receiving mailbox. When a message is received, all the bits in the received message identifier are compared with those in each message control register identifier, and if a 100% match is found, the message is stored in the matching mailbox. Mailbox 0 has a local acceptance filter mask (LAFM) that allows Don't Care settings to be made. The LAFM setting can be made only for mailbox 0. By making the Don't Care setting for all the bits in the received message identifier, messages of multiple identifiers can be received. Examples: * When the identifier of mailbox 1 is 010_1010_1010 (standard format), only one kind of message identifier can be received by mailbox 1: Identifier 1: 010_1010_1010 * When the identifier of mailbox 0 is 010_1010_1010 (standard format) and the LAFM setting is 000_0000_0011 (0: Care, 1: Don't Care), a total of four kinds of message identifiers can be received by mailbox 0: Identifier 1: 010_1010_1000 Identifier 2: 010_1010_1001 Identifier 3: 010_1010_1010 Identifier 4: 010_1010_1011 Message Reception: When a message is received, a CRC check is performed automatically. If the result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether the message can be received or not. * Data frame reception If the received message is confirmed to be error-free by the CRC check, the identifier in the mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the received message, are compared. If a complete match is found, the message is stored in the mailbox. The message identifier comparison is carried out on each mailbox in turn, starting with mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison ends at that point, the message is stored in the matching mailbox, and the corresponding receive complete bit (RXPR0-RXPR15) is set in the receive complete register (RXPR). However, when a mailbox 0 LAFM comparison is carried out, even if the identifier matches, the mailbox comparison sequence does not end at that point, but continues with mailbox 1 and then the remaining mailboxes. It is therefore possible for a message matching mailbox 0 to be received by another mailbox. Note that the same message cannot be stored in more than one of mailboxes 1 to 15. On receiving a message, a CPU interrupt request may be generated Rev. 2.00, 03/04, page 313 of 508 depending on the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR) settings. * Remote frame reception Two kinds of messages--data frames and remote frames--can be stored in mailboxes. A remote frame differs from a data frame in that the remote transmission request bit (RTR) in the message control register and the data field are 0 bytes long. The data length to be returned in a data frame must be stored in the data length code (DLC) in the control field. When a remote frame (RTR = recessive) is received, the corresponding bit is set in the remote request wait register (RFPR). If the corresponding bit (MBIMR0-MBIMR15) in the mailbox interrupt mask register (MBIMR) and the remote frame request interrupt mask (IRR2) in the interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU. Unread Message Overwrite: If the received message identifier matches the mailbox identifier, the received message is stored in the mailbox regardless of whether the mailbox contains an unread message or not. If a message overwrite occurs, the corresponding bit (UMSR0-UMSR15) is set in the unread message register (UMSR). In overwriting an unread message, when a new message is received before the corresponding bit in the receive complete register (RXPR) has been cleared, the unread message register (UMSR) is set. If the unread interrupt flag (IRR9) in the interrupt mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the CPU. Figure 11.12 shows a flowchart for unread message overwriting. Rev. 2.00, 03/04, page 314 of 508 : Settings by user Unread message overwrite : Processing by hardware UMSR = 1 IRR9 = 1 IMR9 = 1? Yes No Interrupt to CPU Clear IRR9 Message control/message data read End Figure 11.12 Unread Message Overwrite Flowchart 11.4.5 HCAN Sleep Mode The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep state in order to reduce current dissipation. Figure 11.13 shows a flowchart of the HCAN sleep mode. Rev. 2.00, 03/04, page 315 of 508 MCR5 = 1 : Settings by user : Processing by hardware No Bus idle? Initialize TEC and REC No Bus operation? Yes IRR12 = 1 Do not access MB during this sequence No IMR12 = 1? CPU interrupt Yes Sleep mode clearing method MCR7 = 0? No (automatic) Yes (manual) Clear sleep mode? No GSR3 = 1? No Yes Yes GSR3 = 1? MCR5 = 0 No Yes MCR5 = 0 No 11 recessive bits? Yes CAN bus communication possible Figure 11.13 HCAN Sleep Mode Flowchart Rev. 2.00, 03/04, page 316 of 508 HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is delayed until the bus becomes idle. Either of the following methods of clearing HCAN sleep mode can be selected: * Clearing by software * Clearing by CAN bus operation Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus communication is re-enabled. Clearing by Software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU. Clearing by CAN Bus Operation: The cancellation method is selected by the MCR7 bit setting in MCR. Clearing by CAN bus operation occurs automatically when the CAN bus performs an operation and this change is detected. In this case, the first message is not stored in a mailbox; messages will be received normally from the second message onward. When a change is detected on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the CPU. Rev. 2.00, 03/04, page 317 of 508 11.4.6 HCAN Halt Mode The HCAN halt mode is provided to enable mailbox settings to be changed without performing an HCAN hardware or software reset. Figure 11.14 shows a flowchart of the HCAN halt mode. MCR1 = 1 Bus idle? No Yes MBCR setting MCR1 = 0 : Settings by user CAN bus communication possible : Processing by hardware Figure 11.14 HCAN Halt Mode Flowchart HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until the bus becomes idle. HCAN halt mode is cleared by clearing MCR1 to 0. Rev. 2.00, 03/04, page 318 of 508 11.5 Interrupts Table 11.4 lists the HCAN interrupt sources. With the exception of the reset processing vector (IRR0), these sources can be masked. Masking is implemented using the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR). For details on the interrupt vector of each interrupt source, see section 5, Interrupt Controller. Table 11.4 HCAN Interrupt Sources Name Description Interrupt Flag ERS0/OVR0 Error passive interrupt (TEC 128 or REC 128) IRR5 Bus off interrupt (TEC 256) IRR6 Reset process interrupt by power-on reset IRR0 Remote frame reception IRR2 Error warning interrupt (TEC 96) IRR3 Error warning interrupt (REC 96) IRR4 Overload frame transmission interrupt IRR7 Unread message overwrite IRR9 Detection of CAN bus operation in HCAN sleep mode IRR12 RM0 Mailbox 0 message reception IRR1 RM1 Mailbox 1-15 message reception IRR1 SLE0 Message transmission/cancellation IRR8 Rev. 2.00, 03/04, page 319 of 508 11.6 CAN Bus Interface A bus transceiver IC is necessary to connect this LSI to a CAN bus. A Philips PCA82C250 transceiver IC is recommended. Any other product must be compatible with the PCA82C250. Figure 11.15 shows a sample connection diagram. 124 This LSI Vcc PCA82C250 RS Vcc HRxD RxD CANH HTxD TxD CANL Vref CAN bus GND NC 124 Note: NC: No Connection Figure 11.15 High-Speed Interface Using PCA82C250 11.7 Usage Notes 11.7.1 Module Stop Mode Setting HCAN operation can be disabled or enabled using the module stop control register. The initial setting is for HCAN operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 19, Power-Down Modes. 11.7.2 Reset The HCAN is reset by a power-on reset, in hardware standby mode, and in software standby mode. All the registers are initialized in a reset, however mailboxes (message control (MCx[x])/message data (MDx[x])) are not. After power-on, mailboxes (message control (MCx[x])/message data (MDx[x])) are not initialized, and their values are undefined. Therefore, mailbox initialization must always be carried out after a power-on reset, a transition to hardware standby mode, or software standby mode. The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software standby mode. As this bit cannot be masked in the interrupt mask register (IMR), if HCAN interrupt enabling is set in the interrupt controller without clearing the flag, an HCAN interrupt will be initiated immediately. IRR0 should therefore be cleared during initialization. Rev. 2.00, 03/04, page 320 of 508 11.7.3 HCAN Sleep Mode The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by CAN bus operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode release. Note that the reset status bit (GSR3) in the general status register (GSR) is set in sleep mode. 11.7.4 Interrupts When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8, IRR2, or IRR1) is not set by reception completion, transmission completion, or transmission cancellation for the set mailboxes. 11.7.5 Error Counters In the case of error active and error passive, REC and TEC normally count up and down. In the bus-off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96 during the count, IRR4 and GSR1 are set. 11.7.6 Register Access Byte or word access can be used on all HCAN registers. Longword access cannot be used. 11.7.7 HCAN Medium-Speed Mode In medium-speed mode, neither read nor write is possible for the HCAN registers. 11.7.8 Register Hold in Standby Modes All HCAN registers are initialized in hardware standby mode and software standby mode. 11.7.9 Usage of Bit Manipulation Instructions The HCAN status flags are cleared by writing 1, so do not use a bit manipulation instruction to clear a flag. When clearing a flag, use the MOV instruction to write 1 to only the bit that is to be cleared. Rev. 2.00, 03/04, page 321 of 508 11.7.10 HCAN TXCR Operation 1. When the transmit wait cancel register (TXCR) is used to cancel a transmit wait message in a transmit wait mailbox, the corresponding bit to TXCR and the transmit wait register (TXPR) may not be cleared even if transmission is canceled. This occurs when the following conditions are all satisfied. * The HRxD pin is stacked to 1 because of a CAN bus error, etc. * There is at least one mailbox waiting for transmission or being transmitted. * The message transmission in a mailbox being transmitted is canceled by TXCR. If this occurs, transmission is canceled. However, since TXPR and TXCR states are indicated wrongly that a message is being cancelled, transmission cannot be restarted even if the stack state of the HRxD pin is canceled and the CAN bus recovers the normal state. If there are at least two transmission messages, a message which is not being transmitted is canceled and a message being transmitted retains its state. To avoid this, one of the following countermeasures must be executed. * Transmission must not be canceled by TXCR. When transmission is normally completed after the CAN bus has recovered, TXPR is cleared and the HCAN recovers the normal state. * To cancel transmission, the corresponding bit to TXCR must be written to 1 continuously until the bit becomes 0. TXPR and TXCR are cleared and the HCAN recovers the normal state. 2. When the bus-off state is entered while TXPR is set and the transmit wait state is entered, the internal state machine does not operate even if TXCR is set during the bus-off state. Therefore transmission cannot be canceled. The message can be canceled when one message is transmitted or a transmission error occurs after the bus-off state is recovered. To clear a message after the bus-off state is recovered, the following countermeasures must be executed. * A transmit wait message must be cleared by resetting the HCAN during the bus-off period. To reset the HCAN, the module stop bit (MSTPC3 in MSTPCRC) must be set or cleared. In this case, the HCAN is entirely reset. Therefore the initial settings must be made again. Rev. 2.00, 03/04, page 322 of 508 11.7.11 HCAN Transmit Procedure When transmission is set while the bus is in the idle state, if the next transmission is set or the set transmission is canceled under the following conditions within 50 s, the transmit message ID of being set may be damaged. * * When the second transmission has the message whose priority is higher than the first one When the massage of the highest priority is canceled in the first transmission Make whichever setting shown below to avoid the message IDs from being damaged. * Set transmission in one TXPR. After transmission of all transmit messages is completed, set transmission again (mass transmission setting). The interval between transmission settings should be 50 s or longer. * Make the transmission setting according to the priority of transmit messages. * Set the interval to be 50 s or longer between TXPR and another TXPR or between TXPR and TXCR. Table 11.5 Interval Limitation between TXPR and TXPR or between TXPR and TXCR Baud Rate (bps) Set Interval (s) 1M 50 500 k 50 250 k 50 11.7.12 Note on Releasing the HCAN Software Reset and HCAN Sleep Before releasing the HCAN software reset or HCAN sleep (MCR0 = 0 or MCR5 = 0), confirm that the GSR3 bit (the reset status bit) is surely set to 1. 11.7.13 Note on Accessing Mailbox during the HCAN Sleep Do not access the mailbox during the HCAN sleep. If accessed, the CPU might halt. Accessing registers during the HCAN sleep does not cause the CPU halt, nor does accessing the mailbox in other than the HCAN sleep mode. Rev. 2.00, 03/04, page 323 of 508 Rev. 2.00, 03/04, page 324 of 508 Section 12 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. The Block diagram of the A/D converter is shown in figure 12.1. 12.1 * * * * * * * * * Features 10-bit resolution Eight input channels Conversion time: 13.3 s per channel (at 20 MHz operation) Two operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels Four data registers Conversion results are held in a 16-bit data register for each channel Sample and hold function Three methods conversion start Software 16-bit timer pulse unit (TPU) conversion start trigger External trigger signal Interrupt request An A/D conversion end interrupt request (ADI) can be generated Module stop mode can be set ADCMS36A_000020020200 Rev. 2.00, 03/04, page 325 of 508 Module data bus 10-bit D/A AVSS Bus interface Successive approximations register AVCC AN0 Internal data bus A D D R A A D D R B A D D R C A D D R D A D C S R A D C R /2 + AN1 /4 AN2 AN4 AN5 Multiplexer AN3 Comparator Control circuit /8 Sample-andhold circuit /16 ADI interrupt Conversion start trigger from TPU AN6 AN7 ADTRG [Legend] ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 12.1 Block Diagram of A/D Converter Rev. 2.00, 03/04, page 326 of 508 12.2 Input/Output Pins Table 12.1 summarizes the input pins used by the A/D converter. The eight analog input pins are divided into four channel sets and two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0 and analog input pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc and AVss pins are the power supply pins for the analog block in the A/D converter. Table 12.1 Pin Configuration Pin Name Symbol I/O Function Analog power supply pin AVCC Input Analog block power supply and reference voltage Analog ground pin AVSS Input Analog block ground and reference voltage Analog input pin 0 AN0 Input Group 0 analog input pins Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input A/D external trigger input pin ADTRG Input Group 1 analog input pins External trigger input pin for starting A/D conversion Rev. 2.00, 03/04, page 327 of 508 12.3 Register Descriptions The A/D converter has the following registers. The MSTPA1 bit in the module stop control register (MSTPCRA) specifies the modes of this module as module stop mode. For details on MSTPCRA, see section 19.1.3, Module Stop Control Registers A to D (MSTPCRA to MSTPCRD). * * * * * * A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) 12.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 12.2. The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0. The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read directly from the CPU, however the lower byte should be read via a temporary register. The temporary register contents are transferred from the ADDR when the upper byte data is read. When reading the ADDR, read the upper byte before the lower byte, or read in word unit. Reading the lower bytes alone does not guarantee the contents. Table 12.2 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Group 0 (CH2 = 0) Group 1 (CH2 = 1) A/D Data Register to Be Stored the Results of A/D Conversion AN0 AN4 ADDRA AN1 AN5 ADDRB AN2 AN6 ADDRC AN3 AN7 ADDRD Rev. 2.00, 03/04, page 328 of 508 12.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit Bit Name Initial Value R/W 7 ADF 0 R/(W)* A/D End Flag Description A status flag that indicates the end of A/D conversion. [Setting conditions] * When A/D conversion ends * When A/D conversion ends on all specified channels [Clearing condition] * 6 ADIE 0 R/W When 0 is written after reading ADF = 1 A/D Interrupt Enable A/D conversion end interrupt (ADI) request enabled when 1 is set 5 ADST 0 R/W A/D Start Clearing this bit to 0 stops A/D conversion, and the A/D converter enters the wait state. Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when conversion on the specified channel is complete. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to software standby mode, hardware standby mode or module stop mode. 4 SCAN 0 R/W Scan Mode Selects single mode or scan mode as the A/D conversion operating mode. 0: Single mode 1: Scan mode 3 0 R/W Reserved The write value should always be 0. Rev. 2.00, 03/04, page 329 of 508 Bit Bit Name Initial Value R/W Description 2 CH2 0 R/W Channel Select 2 to 0 1 CH1 0 R/W Select analog input channels. 0 CH0 0 R/W When SCAN = 0 When SCAN = 1 000: AN0 000: AN0 001: AN1 001: AN0 and AN1 010: AN2 010: AN0 to AN2 011: AN3 011: AN0 to AN3 100: AN4 100: AN4 101: AN5 101: AN4 and AN5 110: AN6 110: AN4 to AN6 111: AN7 111: AN4 to AN7 Note: * Only 0 for clearing the flag can be written. Rev. 2.00, 03/04, page 330 of 508 12.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion started by an external trigger signal. Bit Bit Name Initial Value R/W Description 7 TRGS1 0 R/W Timer Trigger Select 0 and 1 6 TRGS0 0 R/W Enables the start of A/D conversion by a trigger signal. Only set bits TRGS0 and TRGS1 while conversion is stopped (ADST = 0). 00: A/D conversion start by software is enabled 01: A/D conversion start by TPU conversion start trigger is enabled 10: Setting prohibited 11: A/D conversion start by external trigger pin (ADTRG) is enabled 5, 4 All 1 Reserved These bits are always read as 1. 3 CKS1 0 R/W Clock Select 0 and 1 2 CKS0 0 R/W These bits specify the A/D conversion time. The conversion time should be changed only when ADST = 0. Specify a setting that gives a value within the range shown in table 19.7 in section 19, Electrical Characteristics. 00: Conversion time = 530 states (max.) 01: Conversion time = 266 states (max.) 10: Conversion time = 134 states (max.) 11: Conversion time = 68 states (max.) 1, 0 All 1 Reserved These bits are always read as 1. Rev. 2.00, 03/04, page 331 of 508 12.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 12.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the specified single channel. The operations are as follows. 1. A/D conversion is started when the ADST bit is set to 1, according to software or external trigger input. 2. When A/D conversion is completed, the result is transferred to the corresponding A/D data register to the channel. 3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the wait state. 12.4.2 Scan Mode In scan mode, A/D conversion is to be performed sequentially on the specified channels (four channels maximum). The operations are as follows. 1. When the ADST bit is set to 1 by software, TPU or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0 or AN4 when CH2 = 1). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. Conversion of the first channel in the group starts again. 4. Steps [2] and [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters the wait state. Rev. 2.00, 03/04, page 332 of 508 12.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 12.2 shows the A/D conversion timing. Table 12.3 shows the A/D conversion time. As indicated in figure 12.2, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 12.3. In scan mode, the values given in table 12.3 apply to the first conversion time. The values given in table 12.4 apply to the second and subsequent conversions. In both cases, set bits CKS1 and CKS0 in ADCR to give an A/D conversion time within the range shown in table 19.7 in section 19, Electrical Characteristics. (1) Address (2) Write signal Input sampling timing ADF tD tSPL tCONV [Legend] (1): ADCSR write cycle (2): ADCSR address A/D conversion start delay tD: tSPL: Input sampling time tCONV: A/D conversion time Figure 12.2 A/D Conversion Timing Rev. 2.00, 03/04, page 333 of 508 Table 12.3 A/D Conversion Time (Single Mode) CKS1 = 0 CKS0 = 0 Item Symbol Min Typ Max CKS1 = 1 CKS0 = 1 CKS0 = 0 CKS0 = 1 Min Typ Max Min Typ Max Min Typ Max A/D conversion tD start delay 18 33 10 17 6 9 4 5 Input sampling time 127 63 31 15 266 131 134 67 68 tSPL 515 A/D conversion tCONV time 530 259 Note: All values represent the number of states. Table 12.4 A/D Conversion Time (Scan Mode) CKS1 CKS0 Conversion Time (State) 0 0 512 (Fixed) 1 256 (Fixed) 0 128 (Fixed) 1 64 (Fixed) 1 Rev. 2.00, 03/04, page 334 of 508 12.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS0 and TRGS1 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 12.3 shows the timing. ADTRG Internal trigger signal ADST A/D conversion Figure 12.3 External Trigger Input Timing 12.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables ADI interrupt requests while the bit ADF in ADCSR is set to 1 after A/D conversion is completed. Table 12.5 A/D Converter Interrupt Source Name Interrupt Source Interrupt Source Flag ADI A/D conversion completed ADF Rev. 2.00, 03/04, page 335 of 508 12.6 A/D Conversion Precision Definitions This LSI's A/D conversion precision definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 12.4). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 12.5). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 12.5). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between zero voltage and fullscale voltage. Does not include offset error, full-scale error, or quantization error (see figure 12.5). * Absolute precision The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error. Rev. 2.00, 03/04, page 336 of 508 Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 12.4 A/D Conversion Precision Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 12.5 A/D Conversion Precision Definitions Rev. 2.00, 03/04, page 337 of 508 12.7 Usage Notes 12.7.1 Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, see section 19, Power-Down Modes. 12.7.2 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee A/D conversion precision. However, for A/D conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, as a lowpass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 12.6). When converting a highspeed analog signal, a low-impedance buffer should be inserted. 12.7.3 Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board (i.e. acting as antennas). This LSI Sensor output impedance to 5 k A/D converter equivalent circuit 10 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF Figure 12.6 Example of Analog Input Circuit Rev. 2.00, 03/04, page 338 of 508 20 pF 12.7.4 Range of Analog Power Supply and Other Pin Settings If the conditions below are not met, the reliability of the device may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ANn AVcc. * Relationship between AVcc, AVss and Vcc, Vss Set AVss = Vss as the relationship between AVss and Vss. If the A/D converter is not used, set AVcc = Vcc as the relationship between AVcc and Vcc, and the AVcc and AVss pins must not be left open. 12.7.5 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable digital ground (Vss) on the board. 12.7.6 Notes on Noise Countermeasures A protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (AN0 to AN7), between AVcc and AVss, as shown in figure 12.7. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN0 to AN7 must be connected to AVss. If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding circuit constants. Rev. 2.00, 03/04, page 339 of 508 AVCC Rin*2 100 AN0 to AN7 *1 0.1 F AVSS Notes: Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 12.7 Example of Analog Input Protection Circuit Table 12.6 Analog Pin Specifications Item Min. Max. Unit Analog input capacitance 20 pF Permissible signal source impedance 5 k 10 k AN0 to AN7 To A/D converter 20 pF Note: Values are reference values. Figure 12.8 Analog Input Pin Equivalent Circuit Rev. 2.00, 03/04, page 340 of 508 Section 13 Motor Control PWM Timer (PWM) The H8S/2282 has an on-chip motor control PWM (pulse width modulator) with a maximum capability of 16 pulse outputs. 13.1 Features * Maximum of 16 pulse outputs Two 10-bit PWM channels, each with eight outputs. Each channel is provided with a 10-bit counter (PWCNT) and cycle register (PWCYR). Duty and output polarity can be set for each output. * Buffered duty registers Duty registers (PWDTR) are provided with buffer registers (PWBFR), with data transferred automatically every cycle. Channel 1 has four duty registers and four buffer registers. Channel 2 has eight duty registers and four buffer registers. * 0% to 100% duty * Five operating clocks There is a choice of five operating clocks (, /2, /4, /8, /16). * On-chip output driver * High-speed access is possible via a 16-bit bus interface * Two interrupt sources An interrupt can be requested independently for each channel by a cycle register compare match. * Module stop mode can be set Figure 13.1 shows a block diagram of PWM channel 1 and figure 13.2 shows a block diagram of PWM channel 2. MPWM000A_000020020200 Rev. 2.00, 03/04, page 341 of 508 , /2, /4, /8, /16 Interrupt request PWCR_1 Compare match 12 9 Bus interface Internal data bus [Legend] PWCR_1: PWOCR_1: PWPR_1: PWCNT_1: PWCYR_1: PWDTR_1A, 1C, 1E, 1G: PWBFR_1A, 1C, 1E, 1G: 0 PWCNT_1 PWOCR_1 PWCYR_1 PWPR_1 12 9 0 Port control PWBFR_1A PWDTR_1A P/N P/N PWM1A PWM1B PWBFR_1C PWDTR_1C P/N P/N PWM1C PWM1D PWBFR_1E PWDTR_1E P/N P/N PWM1E PWM1F PWBFR_1G PWDTR_1G P/N P/N PWM1G PWM1H PWM control register_1 PWM output control register_1 PWM polarity register_1 PWM counter_1 PWM cycle register_1 PWM duty register_1A, 1C, 1E, 1G PWM buffer register_1A, 1C, 1E, 1G Figure 13.1 Block Diagram of PWM Channel 1 Rev. 2.00, 03/04, page 342 of 508 , /2, /4, /8, /16 Interrupt request PWCR_2 Compare match 12 9 0 Internal data bus Bus interface PWBFR_2A PWBFR_2B PWBFR_2C PWBFR_2D [Legend] PWCR_2: PWOCR_2: PWPR_2: PWCNT_2: PWCYR_2: PWDTR_2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H: PWBFR_2A, 2B, 2C, 2D: PWCNT_2 PWOCR_2 PWCYR_2 PWPR_2 9 Port control 0 PWDTR_2A P/N PWM2A PWDTR_2B P/N PWM2B PWDTR_2C P/N PWM2C PWDTR_2D P/N PWM2D PWDTR_2E P/N PWM2E PWDTR_2F P/N PWM2F PWDTR_2G P/N PWM2G PWDTR_2H P/N PWM2H PWM control register_2 PWM output control register_2 PWM polarity register_2 PWM counter_2 PWM cycle register_2 PWM duty register_2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H PWM buffer register_2A, 2B, 2C, 2D Figure 13.2 Block Diagram of PWM Channel 2 Rev. 2.00, 03/04, page 343 of 508 13.2 Input/Output Pins Table 13.1 shows the PWM pin configuration. Table 13.1 Pin Configuration Name Abbrev. I/O Function PWM output pin 1A PWM1A Output Channel 1A PWM output PWM output pin 1B PWM1B Output Channel 1B PWM output PWM output pin 1C PWM1C Output Channel 1C PWM output PWM output pin 1D PWM1D Output Channel 1D PWM output PWM output pin 1E PWM1E Output Channel 1E PWM output PWM output pin 1F PWM1F Output Channel 1F PWM output PWM output pin 1G PWM1G Output Channel 1G PWM output PWM output pin 1H PWM1H Output Channel 1H PWM output PWM output pin 2A PWM2A Output Channel 2A PWM output PWM output pin 2B PWM2B Output Channel 2B PWM output PWM output pin 2C PWM2C Output Channel 2C PWM output PWM output pin 2D PWM2D Output Channel 2D PWM output PWM output pin 2E PWM2E Output Channel 2E PWM output PWM output pin 2F PWM2F Output Channel 2F PWM output PWM output pin 2G PWM2G Output Channel 2G PWM output PWM output pin 2H PWM2H Output Channel 2H PWM output 13.3 Register Descriptions The PWM has the following registers. For details on module stop control registers, see section 19.1.3, Module Stop Control Registers A to D (MSTPCRA to MSTPCRD). * * * * * * * * * PWM control register_1, 2 (PWCR_1, PWCR_2) PWM output control register_1, 2 (PWOCR_1, PWOCR_2) PWM polarity register_1, 2 (PWPR_1, PWPR_2) PWM counter_1, 2 (PWCNT_1, PWCNT_2) PWM cycle register_1,2 (PWCYR_1, PWCYR_2) PWM duty register_1A, 1C, 1E, 1G (PWDTR_1A, PWDTR_1C, PWDTR_1E, PWDTR_1G) PWM buffer register_1A, 1C, 1E, 1G (PWBFR_1A, PWBFR_1C, PWBFR_1E, PWBFR_1G) PWM duty register_2A to 2H (PWDTR_2A to PWDTRv2H) PWM buffer register_2A to 2D (PWBFR_2A to PWBFR_2D) Rev. 2.00, 03/04, page 344 of 508 13.3.1 PWM Control Register_1, 2 (PWCR_1, PWCR_2) PWCR performs interrupt control, starting/stopping of the counter, and counter clock selection. It also contains a flag that indicates a compare match with PWCYR. Bit Bit Name Initial Value R/W Reserved 7, 6 All 1 Reserved Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified. 5 IE 0 R/W Interrupt Enable Bit 5 enables or disables an interrupt request in the event of a compare match with PWCYR. 0: Interrupt disabled 1: Interrupt enabled 4 CMF 0 R/(W)* Compare Match Flag Bit 4 indicates the occurrence of a compare match with PWCYR. [Setting condition] When PWCNT = PWCYR [Clearing condition] When 0 is written to CMF after reading CMF = 1 3 CST 0 R/W Counter Start Bit 3 selects starting or stopping of PWCNT. 0: PWCNT is stopped 1: PWCNT is started 2 CKS2 0 R/W Clock Select 1 CKS1 0 R/W Bits 2 to 0 select the operating clock for PWCNT. 0 CKS0 0 R/W 000: Counts on /1 001: Counts on /2 010: Counts on /4 011: Counts on /8 1xx: Counts on /16 [Legend] x: Don't care Note: * Only 0 can be written to clear the flag. Rev. 2.00, 03/04, page 345 of 508 13.3.2 PWM Output Control Register_1, 2 (PWOCR_1, PWOCR_2) PWOCR enables or disables PWM output. PWOCR_1 controls outputs PWM1H to PWM1A, and PWOCR_2 controls outputs PWM2H to PWM2A. * PWOCR_1 Bit Bit Name Initial Value R/W Reserved 7 OE1H 0 R/W Output Enable 6 OE1G 0 R/W 5 OE1F 0 R/W Each of these bits enables or disables the corresponding PWM1H to PWM1A output. 4 OE1E 0 R/W 0: PWM output is disabled. 3 OE1D 0 R/W 1: PWM output is enabled. 2 OE1C 0 R/W 1 OE1B 0 R/W 0 OE1A 0 R/W * PWOCR_2 Bit Bit Name Initial Value R/W Reserved 7 OE2H 0 R/W Output Enable 6 OE2G 0 R/W 5 OE2F 0 R/W Each of these bits enables or disables the corresponding PWM2H to PWM2A output. 4 OE2E 0 R/W 0: PWM output is disabled. 3 OE2D 0 R/W 1: PWM output is enabled. 2 OE2C 0 R/W 1 OE2B 0 R/W 0 OE2A 0 R/W Rev. 2.00, 03/04, page 346 of 508 13.3.3 PWM Polarity Register_1, 2 (PWPR_1, PWPR_2) PWPR selects the PWM output polarity. PWPR_1 controls outputs PWM1H to PWM1A, and PWPR_2 controls outputs PWM2H to PWM2A. * PWPR_1 Bit Bit Name Initial Value R/W Reserved 7 OPS1H 0 R/W Polarity Select 6 OPS1G 0 R/W 5 OPS1F 0 R/W Each of these bits selects the output polarity to PWM1H to PWM1A. 4 OPS1E 0 R/W 0: PWM direct output. 3 OPS1D 0 R/W 1: PWM inverse output. 2 OPS1C 0 R/W 1 OPS1B 0 R/W 0 OPS1A 0 R/W * PWPR_2 Bit Bit Name Initial Value R/W Reserved 7 OPS2H 0 R/W Polarity Select 6 OPS2G 0 R/W 5 OPS2F 0 R/W Each of these bits selects the output polarity to PWM2H to PWM2A. 4 OPS2E 0 R/W 0: PWM direct output. 3 OPS2D 0 R/W 1: PWM inverse output. 2 OPS2C 0 R/W 1 OPS2B 0 R/W 0 OPS2A 0 R/W 13.3.4 PWM Counter_1, 2 (PWCNT_1, PWCNT_2) PWCNT is a 10-bit up-counter incremented by the input clock. The input clock is selected by clock select bits CKS2 to CKS0 in PWCR. PWCNT_1 and PWCNT_2 are used as the time base for channel 1 and channel 2 respectively. PWCNT is initialized when the CST in PWCR is cleared to 0, and also upon reset and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. PWCNT is initialized to H'FC00. Rev. 2.00, 03/04, page 347 of 508 13.3.5 PWM Cycle Register_1, 2 (PWCYR_1, PWCYR_2) PWCYR is a 16-bit read/write register that sets the PWM conversion cycle. When a PWCYR compare match occurs, PWCNT is cleared and data is transferred from the buffer register (PWBFR) to the duty register (PWDTR). PWCYR_1 and PWCYR_2 are used for conversion cycle setting for the channel 1 and channel 2 respectively. PWCYR should be written to only while PWCNT is stopped. A value of H'FC00 must not be set. PWCYR is initialized to H'FFFF upon reset. Figure 13.3 shows the compare match of the cycle registers. Compare match PWCNT (lower 10 bits) Compare match 0 1 PWCYR (lower 10 bits) N-2 N-1 0 1 N Figure 13.3 Cycle Register Compare Match 13.3.6 PWM Duty Register_1A, 1C, 1E, 1G (PWDTR_1A, PWDTR_1C, PWDTR_1E, PWDTR_1G) There are four PWDTR_1 registers. The PWM output is determined by the value of the OTS bit, and PWDTR_1A is used for outputs PWM1A and PWM1B, PWDTR_1C for outputs PWM1C and PWM1D, PWDTR_1E for outputs PWM1E and PWM1F, and PWDTR_1G for outputs PWM1G and PWM1H. The PWDTR_1 registers cannot be read from or written to directly. When a PWCYR_1 compare match occurs, data is transferred from buffer register 1 (PWBFR_1) to PWDTR_1. The PWDTR_1 registers are initialized when the CST bit in PWCR_1 is cleared to 0, and also upon reset and in standby mode and module stop mode. Rev. 2.00, 03/04, page 348 of 508 Bit Bit Name Initial Value R/W Reserved 15 to 13 All 1 Reserved These bits cannot be read from or written to. 12 OTS 0 Output Terminal Select Bit 12 indicates the value in bit 12 of PWBFR_1 sent by a PWCYR_1 compare match, and selects the pin used for PWM output. Unselected pins output a low level (or a high level when the corresponding bit in PWPR_1 is set to 1). PWDTR_1A register 0: PWM1A output selected 1: PWM1B output selected PWDTR_1C 0: PWM1C output selected 1: PWM1D output selected PWDTR_1E 0: PWM1E output selected 1: PWM1F output selected PWDTR_1G 0: PWM1G output selected 1: PWM1H output selected 11, 10 All 1 Reserved These bits are always read as 1 and cannot be modified. 9 DT9 0 Duty 8 DT8 0 7 DT7 0 6 DT6 0 5 DT5 0 4 DT4 0 3 DT3 0 2 DT2 0 Bits 9 to 0 indicate the data in bits 9 to 0 of PWBFR_1 sent by a PWCYR_1 compare match, and specify the PWM output duty. A high level (or a low level when the corresponding bit in PWPR_1 is set to 1) is output from the time PWCNT_1 is cleared by a PWCYR_1 compare match until a PWDTR_1 compare match occurs. When all of the bits are 0, there is no high-level (or low-level when the corresponding bit in PWPR_1 is set to 1) output period. 1 DT1 0 0 DT0 0 Rev. 2.00, 03/04, page 349 of 508 Compare match PWCNT_1 (lower 10 bits) 0 1 M-2 PWCYR_1 (lower 10 bits) N PWDTR_1 (lower 10 bits) M M-1 M N-1 0 PWM output on selected pin PWM output on unselected pin Figure 13.4 Duty Register Compare Match (OPS = 0 in PWPR_1) PWCNT_1 (lower 10 bits) 0 N-2 1 PWCYR_1 (lower 10 bits) N PWDTR_1 (lower 10 bits) M N-1 PWM output (M = 0) PWM output (0 < M < N) PWM output (N M) Figure 13.5 Differences in PWM Output According to Duty Register Set Value (OPS = 0 in PWPR_1) Rev. 2.00, 03/04, page 350 of 508 0 13.3.7 PWM Buffer Register_1A, 1C, 1E, 1G (PWBFR_1A, PWBFR_1C, PWBFR_1E, PWBFR_1G) There are four PWBFR_1 registers. When a PWCYR_1 compare match occurs, data is transferred from PWBFR_1A to PWDTR_1A, from PWBFR_1C to PWDTR_1C, from PWBFR_1E to PWDTR_1E, and from PWBFR_1G to PWDTR_1G. Bit Bit Name Initial Value R/W Reserved 15 to 13 All 1 Reserved These bits are always read as 1 and cannot be modified. 12 OTS 0 R/W Output Terminal Select 11, 10 All 1 Reserved Bit 12 is the data sent to bit 12 of PWDTR_1. These bits are always read as 1 and cannot be modified. 9 DT9 0 R/W Duty 8 DT8 0 R/W 7 DT7 0 R/W Bits 9 to 0 comprise the data sent to bits 9 to 0 in PWDTR_1. 6 DT6 0 R/W 5 DT5 0 R/W 4 DT4 0 R/W 3 DT3 0 R/W 2 DT2 0 R/W 1 DT1 0 R/W 0 DT0 0 R/W Rev. 2.00, 03/04, page 351 of 508 13.3.8 PWM Duty Register_2A to 2H (PWDTR_2A to PWDTR_2H) There are eight PWDTR_2 registers. PWDTR_2A is used for output PWM2A, PWDTR_2B for output PWM2B, PWDTR_2C for output PWM2C, PWDTR_2D for output PWM2D, PWDTR_2E for output PWM2E, PWDTR_2F for output PWM2F, PWDTR_2G for output PWM2G, and PWDTR_2H for output PWM2H. The PWDTR_2 registers cannot be read from or written to directly. When a PWCYR_2 compare match occurs, data is transferred from buffer register 2 (PWBFR_2) to PWDTR_2. The PWDTR_2 registers are initialized when the CST bit in PWCR_2 is cleared to 0, and also upon reset and in standby mode and module stop mode. Bit Bit Name Initial Value R/W Reserved 15 to 10 All 1 Reserved These bits cannot be read from or written to. 9 DT9 0 R/W Duty 8 DT8 0 R/W 7 DT7 0 R/W 6 DT6 0 R/W 5 DT5 0 R/W 4 DT4 0 R/W 3 DT3 0 R/W 2 DT2 0 R/W Bits 9 to 0 indicate the data in bits 9 to 0 of PWBFR_2 sent by a PWCYR_2 compare match, and specify the PWM output duty. A high level (or a low level when the corresponding bit in PWPR_2 is set to 1) is output from the time PWCNT_2 is cleared by a PWCYR_2 compare match until a PWDTR_2 compare match occurs. When all the bits are 0, there is no high-level (or low-level when the corresponding bit in PWPR_2 is set to 1) output period. 1 DT1 0 R/W 0 DT0 0 R/W Compare match PWCNT_2 (lower 10 bits) 0 1 M-2 PWCYR_2 (lower 10 bits) N PWDTR_2 (lower 10 bits) M M-1 M PWM output Figure 13.6 Duty Register Compare Match (OPS = 0 in PWPR_2) Rev. 2.00, 03/04, page 352 of 508 N-1 0 PWCNT_2 (lower 10 bits) 0 N-2 1 PWCYR_2 (lower 10 bits) N PWDTR_2 (lower 10 bits) M N-1 0 PWM output (M = 0) PWM output (0 < M < N) PWM output (N M) Figure 13.7 Differences in PWM Output According to Duty Register Set Value (OPS = 0 in PWPR_2) 13.3.9 PWM Buffer Register_2A to 2D (PWBFR2_A to PWBFR_2D) There are four PWBFR_2 registers. The transfer destination is determined by the value of the TDS bit, and when a PWCYR_2 compare match occurs, data is transferred from PWBFR_2A to PWDTR_2A or PWDTR_2E, from PWBFR_2B to PWDTR_2B or PWDTR_2F, from PWBFR_2C to PWDTR_2C or PWDTR_2G, and from PWBFR_2D to PWDTR_2D or PWDTR_2H. Rev. 2.00, 03/04, page 353 of 508 Bit Bit Name Initial Value R/W Reserved 15 to 13 All 1 Reserved These bits are always read as 1 and cannot be modified. 12 TDS 0 R/W Transfer Destination Select Bit 12 selects the PWDTR_2 register to which data is to be transferred. PWBFR_2A 0: PWDTR_2A selected 1: PWDTR_2E selected PWBFR_2B 0: PWDTR_2B selected 1: PWDTR_2F selected PWBFR_2C 0: PWDTR_2C selected 1: PWDTR_2G selected PWBFR_2D 0: PWDTR_2D selected 1: PWDTR_2H selected 11, 10 All 1 Reserved These bits are always read as 1 and cannot be modified. 9 DT9 0 R/W Duty 8 DT8 0 R/W 7 DT7 0 R/W Bits 9 to 0 comprise the data sent to bits 9 to 0 in PWDTR_2. 6 DT6 0 R/W 5 DT5 0 R/W 4 DT4 0 R/W 3 DT3 0 R/W 2 DT2 0 R/W 1 DT1 0 R/W 0 DT0 0 R/W Rev. 2.00, 03/04, page 354 of 508 13.4 Bus Master Interface 13.4.1 16-Bit Data Registers PWCYR_1, PWCYR_2, PWBFR_1A, PWBFR_1C, PWBFR_1E, PWBFR_1G, and PWBFR_2A to PWBFR_2D are 16-bit registers. These registers are linked to the bus master by a 16-bit data bus, and can be read or written in 16-bit units. They cannot be read or written by 8-bit access; 16bit access must always be used. Internal data bus H Bus master L Bus interface Module data bus PWCYR_1 Figure 13.8 16-Bit Register Access Operation (Bus Master PWCYR_1 (16 Bits)) 13.4.2 8-Bit Data Registers PWCR_1, PWCR_2, PWOCR_1, PWOCR_2, and PWPR_1, PWPR_2 are 8-bit registers that can be read and written to in 8-bit units. These registers are linked to the bus master by a 16-bit data bus, and can be read or written by 16-bit access; in this case, the lower 8 bits are read as an undefined value. Internal data bus H Bus master L Bus interface Module data bus PWCR_1 Figure 13.9 8-Bit Register Access Operation (Bus Master PWCR_1 (Upper 8 Bits)) Rev. 2.00, 03/04, page 355 of 508 13.5 Operation 13.5.1 PWM Channel 1 Operation PWM waveforms are output from pins PWM1A to PWM1H as shown in figure 13.10. Initial Settings: Set the PWM output polarity in PWPR_1; enable the PWM1A to PWM1H pins for PWM output with PWOCR_1; select the clock to be input to PWCNT_1 with bits CKS2 to CKS0 in PWCR_1; set the PWM conversion cycle in PWCYR_1; and set the first frame of data in PWBFR_1A, PWBFR_1C, PWBFR_1E, and PWBFR_1G. Activation: When the CST bit in PWCR_1 is set to 1, a compare match between PWCNT_1 and PWCYR_1 is generated. Data is transferred from PWBFR_1A to PWDTR_1A, from PWBFR_1C to PWDTR_1C, from PWBFR_1E to PWDTR_1E, and from PWBFR_1G to PWDTR_1G. PWCNT_1 starts counting up. At the same time the CMF bit in PWCR_1 is set, so that, if the IE bit in PWCR_1 has been set, an interrupt can be requested. Waveform Output: The PWM outputs selected by the OTS bits in PWDTR_1A, PWDTR_1C, PWDTR_1E, and PWDTR_1G go high when a compare match occurs between PWCNT_1 and PWCYR_1. The PWM outputs not selected are low. When a compare match occurs between PWCNT_1 and PWDTR_1A, PWDTR_1C, PWDTR_1E, PWDTR_1G, the corresponding PWM output goes low. If the corresponding bit in PWPR_1 is set to 1, the output is inverted. Next Frame: When a compare match occurs between PWCNT_1 and PWCYR_1, data is transferred from PWBFR_1A to PWDTR_1A, from PWBFR_1C to PWDTR_1C, from PWBFR_1E to PWDTR_1E, and from PWBFR_1G to PWDTR_1G. PWCNT_1 is reset and starts counting up from H'000. The CMF bit in PWCR_1 is set, and if the IE bit in PWCR_1 has been set, an interrupt can be requested. Stopping: When the CST bit in PWCR_1 is cleared to 0, PWCNT_1 is reset and stops. All PWM outputs go low (or high if the corresponding bit in PWPR_1 is set to 1). Rev. 2.00, 03/04, page 356 of 508 PWCYR_1 PWBFR_1A PWDTR_1A OTS (PWDTR_1A) = 0 OTS (PWDTR_1A) = 1 OTS (PWDTR_1A) = 0 OTS (PWDTR_1A) = 1 PWM1A PWM1B Figure 13.10 PWM Channel 1 Operation 13.5.2 PWM Channel 2 Operation PWM waveforms are output from pins PWM2A to PWM2H as shown in figure 13.11. Initial Settings: Set the PWM output polarity in PWPR_2; enable the PWM2A to PWM2H pins for PWM output with PWOCR_2; select the clock to be input to PWCNT_2 with bits CKS2 to CKS0 in PWCR_2; set the PWM conversion cycle in PWCYR_2; and set the first frame of data in PWBFR_2A, PWBFR_2B, PWBFR_2C, and PWBFR_2D. Activation: When the CST bit in PWCR_2 is set to 1, a compare match between PWCNT_2 and PWCYR_2 is generated. Data is transferred from PWBFR_2A to PWDTR_2A or PWDTR_2E, from PWBFR_2B to PWDTR_2B or PWDTR_2F, from PWBFR_2C to PWDTR_2C or PWDTR_2G, and from PWBFR_2D to PWDTR_2D or PWDTR_2H, according to the value of the TDS bit. PWCNT_2 starts counting up. At the same time the CMF bit in PWCR_2 is set, so that, if the IE bit in PWCR_2 has been set, an interrupt can be requested. Waveform Output: The PWM outputs go high when a compare match occurs between PWCNT_2 and PWCYR_2. When a compare match occurs between PWCNT_2 and PWDTR_2A to PWDTR_2H, the corresponding PWM output goes low. If the corresponding bit in PWPR_2 is set to 1, the output is inverted. Next Frame: When a compare match occurs between PWCNT_2 and PWCYR_2 data is transferred from PWBFR_2A to PWDTR_2A or PWDTR_2E, from PWBFR_2B to PWDTR_2B or PWDTR_2F, from PWBFR_2C to PWDTR_2C or PWDTR_2G, and from PWBFR_2D to PWDTR_2D or PWDTR_2H, according to the value of the TDS bit. PWCNT_2 is reset and starts counting up from H'000. The CMF bit in PWCR_2 is set, and if the IE bit in PWCR_2 has been set, an interrupt can be requested. Rev. 2.00, 03/04, page 357 of 508 Stopping: When the CST bit in PWCR_2 is cleared to 0, PWCNT_2 is reset and stops. PWDTR_2A to PWDTR_2H are reset. All PWM outputs go low (or high if the corresponding bit in PWPR_2 is set to 1). PWCYR_2 PWBFR_2A PWDTR_2A PWDTR_2E TDS (PWBFR_2A) = 0 TDS (PWBFR_2A) = 1 TDS (PWBFR_2A) = 0 PWM2A PWM2B Figure 13.11 PWM Channel 2 Operation 13.6 Interrupts If the IE bit in PWCR is set to 1 when the CMF flag in PWCR is set to 1 by a compare match between PWCNT and PWCYR, an interrupt is requested. Table 13.2 shows the PWM interrupt sources. Table 13.2 PWM Interrupt Sources Name Interrupt Source Interrupt Flag CMI1 PWCYR_1 compare match CMF CMI2 PWCYR_2 compare match CMF Rev. 2.00, 03/04, page 358 of 508 13.7 Usage Note Contention between Buffer Register Write and Compare Match: If a PWBFR write is performed in the state immediately after a cycle register compare match, the buffer register and duty register are overwritten. PWM output changed by the cycle register compare match is not changed in overwrite of the duty register due to contention. This may result in unanticipated duty output. In the case of channel 2, the duty register used as the transfer destination is selected by the TDS bit of the buffer register when an overwrite of the duty register occurs due to contention. This can also result in an unintended overwrite of the duty register. Buffer register rewriting must be completed before, exception handling due to a compare match interrupt, or the occurrence of a cycle register compare match on detection of the rise of the CMF flag in PWCR. T1 Tw Tw T2 Address Write signal Buffer register address Compare match PWCNT (lower 10 bits) PWBFR PWDTR 0 N M N M PWM output CMF Figure 13.12 Contention between Buffer register Write and Compare Match Rev. 2.00, 03/04, page 359 of 508 Rev. 2.00, 03/04, page 360 of 508 Section 14 LCD Controller/Driver (LCD) This LSI has an on-chip segment type LCD control circuit, LCD driver, and power supply circuit, enabling it to directly drive an LCD panel. 14.1 Features * Display capacity Duty Cycle Internal Driver Static 28 SEG 1/3 28 SEG 1/4 28 SEG * Display LCD RAM capacity 8 bits x 20 bytes (160 bits) Byte or word access to LCD RAM * The segment output pins can be used as ports in groups of four. * Common output pins not used because the duty cycle can be used for common doublebuffering (parallel connection). In static mode, parallel connection of COM1 to COM2, and of COM3 to COM4 can be used * Choice of 11 frame frequencies * A or B waveform selectable by software * Built-in power supply split-resistance * Display possible in operating modes other than standby mode and module stop mode LCDSG01A_000020020200 Rev. 2.00, 03/04, page 361 of 508 Figure 14.1 shows a block diagram of the LCD controller/driver. LPVCC V1 LCD drive power supply M /8 to /1024 V3 VSS CL2 Common data latch SUB Internal data bus V2 Common driver COM4 COM1 SEG28 SEG27 SEG26 SEG25 SEG24 LPCR LCR LCR2 Display timing generator 28-bit shift register CL1 Segment driver LCD RAM 20 bytes SEG1 SEGn, DO [Legend] LPCR: LCD port control register LCR: LCD control register LCR2: LCD control register 2 Figure 14.1 Block Diagram of LCD Controller/Driver 14.2 Input/Output Pins Table 14.1 shows the LCD controller/driver pin configuration. Table 14.1 Pin Configuration Name Abbrev. I/O Function Segment output pins SEG28 to SEG1 Output LCD segment drive pins Common output pins COM4 to COM1 LCD power supply pins V1, V2, V3 All pins are multiplexed as port pins (setting programmable) Output LCD common drive pins Pins can be used in parallel with static Rev. 2.00, 03/04, page 362 of 508 Used when a bypass capacitor is connected externally, and when an external power supply circuit is used 14.3 Register Descriptions The LCD controller/driver has the following registers. For details on module stop control, see section 19.1.3, Module Stop Control Registers A to D (MSTPCRA to MSTPCRD). * LCD port control register (LPCR) * LCD control register (LCR) * LCD control register 2 (LCR2) 14.3.1 LCD Port Control Register (LPCR) LPCR selects the duty cycle, LCD driver, and pin functions. Bit Bit Name Initial Value R/W Description 7 DTS1 0 R/W Duty Cycle Select 1 and 0 6 DTS0 0 R/W The combination of DTS1 and DTS0 selects static, 1/3, or 1/4 duty. For details, see table 14.2. 5 CMX 0 R/W Common Function Select Specifies whether or not the same waveform is to be output from multiple pins to increase the common drive power when all common pins are not used because of the duty setting. For details, see table 14.2. 4 0 R/W Reserved This bit should only be written with 0. 3 SGS3 0 R/W Segment Driver Select 3 to 0 2 SGS2 0 R/W 1 SGS1 0 R/W Bits 3 to 0 select the segment drivers to be used. For details, see table 14.3. 0 SGS0 0 R/W Rev. 2.00, 03/04, page 363 of 508 Table 14.2 Selection of the Duty Cycle and Common Functions Bit 7: DTS1 Bit 6: DTS0 Bit 5: CMX Duty Cycle Common Drivers Notes 0 0 0 Static COM1 COM4, COM3, and COM2 can be used as ports COM4 to COM1 COM4, COM3, and COM2 output the same waveform as COM1 1 1 1 X Setting prohibited 0 0 1/3 duty COM3 to COM1 COM4 can be used as a port COM4 to COM1 COM4 use is prohibited 1 1 X 1/4 duty COM4 to COM1 [Legend] X: Don't care Table 14.3 Selection of Segment Drivers Function of Pins SEG28 to SEG1 Bit 3: Bit 2: Bit 1: Bit 0: SGS3 SGS2 SGS1 SGS0 SEG28 to SEG20 to SEG16 to SEG12 to SEG8 to SEG21 SEG17 SEG13 SEG9 SEG5 SEG4 to SEG1 0 0 Port Port Port Port Port Port 1 SEG Port Port Port Port Port 0 SEG SEG Port Port Port Port 1 SEG SEG SEG Port Port Port 0 0 1 1 0 1 1 X X 0 SEG SEG SEG SEG Port Port 1 SEG SEG SEG SEG SEG Port 0 SEG SEG SEG SEG SEG SEG 1 Setting Setting Setting Setting Setting Setting prohibited prohibited prohibited prohibited prohibited prohibited X Setting Setting Setting Setting Setting Setting prohibited prohibited prohibited prohibited prohibited prohibited [Legend] X: Don't care Rev. 2.00, 03/04, page 364 of 508 14.3.2 LCD Control Register (LCR) LCR performs LCD power supply split-resistance connection control and display data control, and selects the frame frequency. Bit Bit Name Initial Value R/W Description 7 1 Reserved This bit is always read as 1 and cannot be modified. 6 PSW 0 R/W LCD Power Supply Split-Resistance Connection Control Bit 6 can be used to disconnect the LCD power supply split-resistance from VCC when LCD display is not required in a power-down mode, or when an external power supply is used. When ACT is 0 or in standby mode, the LCD power supply split-resistance is disconnected from VCC regardless of the setting of this bit. 0: LCD power supply split-resistance is disconnected from VCC 1: LCD power supply split-resistance is connected to VCC 5 ACT 0 R/W Display Function Activate Bit 5 specifies whether or not the LCD controller/driver is used. Clearing this bit to 0 halts operation of the LCD controller/driver. The LCD drive power supply ladder resistance is also turned off, regardless of the setting of the PSW bit. However, register contents are retained. 0: LCD controller/driver operation halted 1: LCD controller/driver operates 4 DISP 0 R/W Display Data Control Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed. 0: Blank data is displayed 1: LCD RAM data is displayed 3 CKS3 0 R/W Frame Frequency Select 3 to 0 2 CKS2 0 R/W 1 CKS1 0 R/W Bits 3 to 0 select the operating clock and the frame frequency. For details, see table 14.4. 0 CKS0 0 R/W Rev. 2.00, 03/04, page 365 of 508 Table 14.4 Selection of the Operating Clock and Frame Frequency Frame Frequency*1 Bit 3: CKS3 Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Operating Clock = 20 MHz 0 X 0 0 SUB 128 Hz*2 1 SUB/2 64 Hz*2 1 X SUB/4 32 Hz*2 0 0 /8 4880 Hz 1 /16 2440 Hz 1 0 1 1 0 1 0 /32 1220 Hz 1 /64 610 Hz 0 /128 305 Hz 1 /256 152.6 Hz 0 /512 76.3 Hz 1 /1024 38.1 Hz [Legend] X: Don't care Notes: 1. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown. 2. This is the frame frequency when SUB = 32.768 kHz. 14.3.3 LCD Control Register 2 (LCR2) LCR2 controls switching between the A waveform and B waveform. Bit Bit Name Initial Value R/W Description 7 LCDAB 0 R/W A Waveform/B Waveform Switching Control: Bit 7 specifies whether the A waveform or B waveform is used as the LCD drive waveform. 0: Drive using A waveform 1: Drive using B waveform 6, 5 All 1 Reserved These bits are always read as 1 and cannot be modified. 4 to 0 All 0 Reserved These bits should only be written with 0. Rev. 2.00, 03/04, page 366 of 508 14.4 Operation 14.4.1 Settings up to LCD Display To perform LCD display, the hardware and software related items described below must first be determined. Hardware Settings * Panel display As the impedance of the built-in power supply split-resistance is large, it may not be suitable for driving a panel. If the display lacks sharpness, see section 14.4.4, Boosting the LCD Drive Power Supply. When static is selected, the common output drive capability can be increased. Set the CMX bit in LPCR to 1 when selecting the duty cycle. With a static cycle, pins COM4 to COM1 output the same waveform. * LCD drive power supply setting With the H8S/2282, there are two ways of providing LCD power: by using the on-chip power supply circuit, or by using an external power supply circuit. When an external power supply circuit is used for the LCD drive power supply, connect the external power supply to the V1 pin. Software Settings * Duty selection Duty cycles can be selected by setting bits DTS1 and DTS0. * Segment selection The segment drivers to be used can be selected by setting bits SGS3 to SGS0. * Frame frequency selection The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency should be selected in accordance with the LCD panel specification. For the clock selection method in watch mode, subactive mode, and subsleep mode, see section 14.4.3, Operation in Power-Down Modes. * A or B waveform selection Either the A or B waveform can be selected as the LCD waveform to be used by means of the LCDAB bit. * LCD drive power supply selection When an external power supply circuit is used, turn the LCD drive power supply off by clearing the PSW bit to 0. Rev. 2.00, 03/04, page 367 of 508 14.4.2 Relationship between LCD RAM and Display The relationship between the LCD RAM and the display segments differs according to the duty cycle. LCD RAM maps for the different duty cycles are shown in figures 14.2 to 14.4. After setting the registers required for display, data is written to the part corresponding to the duty using the same kind of instruction as for ordinary RAM, and display is started automatically when turned on. Word- or byte-access instructions can be used for RAM setting. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FC40 Space not used for display H'FC45 H'FC46 SEG2 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 SEG1 Display space H'FC53 SEG28 SEG28 SEG28 SEG28 SEG27 SEG27 SEG27 SEG27 COM4 COM3 COM2 COM1 COM4 COM3 COM2 COM1 Figure 14.2 LCD RAM Map (1/4 Duty) Rev. 2.00, 03/04, page 368 of 508 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FC40 Space not used for display H'FC45 H'FC46 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 Display space H'FC53 SEG28 SEG28 SEG28 SEG27 SEG27 SEG27 COM3 COM2 COM1 COM3 COM2 COM1 Figure 14.3 LCD RAM Map (1/3 Duty) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FC40 H'FC41 SEG4 SEG3 SEG2 SEG1 H'FC42 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 H'FC44 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 Space not used for display Display space Space not used for display H'FC53 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 Figure 14.4 LCD RAM Map (Static Mode) Rev. 2.00, 03/04, page 369 of 508 1 frame 1 frame M M Data Data V1 V2 V3 VSS COM1 V1 V2 V3 VSS V1 V2 V3 VSS COM2 COM3 V1 V2 V3 VSS V1 V2 V3 VSS COM4 SEGn (a) Waveform with 1/4 duty V1 V2 V3 VSS COM1 V1 V2 V3 VSS V1 V2 V3 VSS COM2 COM3 V1 V2 V3 VSS SEGn (b) Waveform with 1/3 duty 1 frame M Data V1 COM1 VSS V1 SEGn VSS (c) Waveform with static output Figure 14.5 Output Waveforms for Each Duty Cycle (A Waveform) Rev. 2.00, 03/04, page 370 of 508 1 frame 1 frame 1 frame 1 frame 1 frame M M Data Data V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS COM1 COM2 COM3 COM4 V1 V2 V3 VSS SEGn (a) Waveform with 1/4 duty 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS COM1 COM2 COM3 V1 V2 V3 VSS SEGn (b) Waveform with 1/3 duty 1 frame M Data V1 COM1 VSS V1 SEGn VSS (c) Waveform with static output Figure 14.6 Output Waveforms for Each Duty Cycle (B Waveform) Rev. 2.00, 03/04, page 371 of 508 Table 14.5 Output Levels (A Waveform) Data 0 0 1 1 M 0 1 0 1 Common output V1 VSS V1 VSS Segment output V1 VSS VSS V1 Common output V3 V2 V1 VSS Segment output V2 V3 VSS V1 Common output V3 V2 V1 VSS Segment output V2 V3 VSS V1 Static 1/3 duty 1/4 duty 14.4.3 Operation in Power-Down Modes The LCD controller/driver can be operated even in the power-down modes. The operating state of the LCD controller/driver in the power-down modes is summarized in table 14.6. Though the read/write to the register for LCD in medium-speed mode is unable, LCD display operation continues as in high-speed mode. In subactive, subsleep or watch mode, the system clock switches to the subclock, requiring that SUB, SUB/2, or SUB/4 should be selected. In watch mode in particular, the clock is not supplied unless SUB, SUB/2, or SUB/4 is selected, causing the display halt. In this case, the DC voltage may be applied to the LCD panel. Thus, make sure to select SUB, SUB/2, or SUB/4. In software standby mode, when boosting the LCD drive power supply, the segment output and common output pins retain their values, and the DC voltage could be applied to the LCD panel. Therefore, before entering software standby mode, set DDR that is used for segment output and common output and the bits SGS3 to SGS0 to 0 Table 14.6 Power-Down Modes and Display Operation Mode Clock SUB Display ACT = 0 operation ACT = 1 Reset Active Sleep Watch Subactive Subsleep Module Standby Standby Runs Runs Runs Stops Stops Stops* Stops 1 Stops* 1 Stops* 2 Stops 2 Stops Runs Runs Runs Runs Runs Runs Stops* Stops Stops Stops Stops Stops Stops Stops* Stops 3 3 3 Functions Functions Functions* Functions* Functions* Stops* 1 1 Notes: 1. The clock supplied to the LCD stops. 2. The LCD drive power supply is turned off regardless of the setting of the PSW bit. 3. Display operation is performed only when SUB, SUB/2, or SUB/4 is selected as the clock. Rev. 2.00, 03/04, page 372 of 508 14.4.4 Boosting the LCD Drive Power Supply When a panel is driven, the on-chip power supply capacity may be insufficient. In this case, the power supply impedance must be reduced. This can be done by connecting bypass capacitors of around 0.1 to 0.3 F to pins V1 to V3, as shown in figure 14.7, or by adding a split-resistance externally. LPVCC VR V1 R H8S/2282 R = several k to several M V2 R C = 0.1 to 0.3 F V3 R VSS Figure 14.7 Connection of External Split-Resistance Rev. 2.00, 03/04, page 373 of 508 Rev. 2.00, 03/04, page 374 of 508 Section 15 RAM This LSI has 4 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, see section 3.2.2, System Control Register (SYSCR). Product Type Name ROM Type RAM Capacitance H8S/2282 Group HD64F2282 Flash memory version 4 kbytes H'FFE000 to H'FFEFBF, H'FFFFC0 to H'FFFFFF HD6432282 Mask ROM version 4 kbytes H'FFE000 to H'FFEFBF, H'FFFFC0 to H'FFFFFF 4 kbytes H'FFE000 to H'FFEFBF, H'FFFFC0 to H'FFFFFF HD6432281 RAM Address Rev. 2.00, 03/04, page 375 of 508 Rev. 2.00, 03/04, page 376 of 508 Section 16 Flash Memory (F-ZTAT Version) The features of the flash memory are summarized below. The block diagram of the flash memory is shown in figure 16.1. 16.1 Features * Size: 128 kbytes * Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 32 kbytes x 2 blocks, 28 kbytes x 1 block, 16 kbytes x 1 block, 8 kbytes x 2 blocks, and 1 kbyte x 4 blocks. To erase the entire flash memory, each block must be erased in turn. * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * Two on-board programming modes Boot mode User program mode Programmer mode On-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed. * Automatic bit rate adjustment For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection Sets hardware protection, software protection, or error protection against flash memory programming/erasing. * Programmer mode Flash memory can be programmed/erased in programmer mode using a PROM programmer, as well as in on-board programming mode. ROMF380A_000020020200 Rev. 2.00, 03/04, page 377 of 508 Internal address bus Module bus Internal data bus (16 bits) FLMCR1 FLMCR2 EBR1 Bus interface/controller Operating mode FWE pin Mode pin EBR2 RAMER FLPWCR Flash memory (128 kbytes) [Legend] FLMCR1: FLMCR2: EBR1: EBR2: RAMER: FLPWCR: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Flash memory power control register Figure 16.1 Block Diagram of Flash Memory 16.2 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 16.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory. The differences between boot mode and user program mode are shown in table 16.1. Figure 16.3 shows the operation flow for boot mode and figure 16.4 shows that for user program mode. Rev. 2.00, 03/04, page 378 of 508 MD2 = 1, MD0 = 1, FWE = 0 Reset state *1 User mode (on-chip ROM enabled) FWE = 1 =0 =0 MD2 = 1, MD0 = 1, FWE = 1 =0 MD2 = 0, MD0 = 1, FWE = 1 FWE = 0 User program mode *2 =0 Programmer mode *1 Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. RAM emulation possible 2. This LSI transits to programmer mode by using the dedicated PROM programmer. Figure 16.2 Flash Memory State Transitions Table 16.1 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Total erase Yes Yes Block erase No Yes Programming control program* (2) (1) (2) (3) (1) Erase/erase-verify (2) Program/program-verify (3) Emulation Note: * To be provided by the user, in accordance with the recommended algorithm. Rev. 2.00, 03/04, page 379 of 508 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host ; ; ;;;;; Programming control program New application program New application program This LSI This LSI SCI Boot program Flash memory RAM SCI Boot program RAM Flash memory Boot program area Application program (old version) Application program (old version) 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. Programming control program 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host Host New application program This LSI This LSI SCI Boot program Flash memory Flash memory RAM Boot program area Flash memory preprogramming erase Programming control program SCI Boot program RAM Boot program area New application program Programming control program Program execution state Figure 16.3 Boot Mode Rev. 2.00, 03/04, page 380 of 508 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM. ;;;; ;; 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. Host Host Programming/ erase control program New application program New application program This LSI This LSI SCI Boot program Flash memory RAM SCI Boot program RAM Flash memory FWE assessment program FWE assessment program Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host Host New application program This LSI This LSI SCI Boot program Flash memory RAM FWE assessment program Flash memory RAM FWE assessment program Transfer program Transfer program Programming/ erase control program Flash memory erase SCI Boot program Programming/ erase control program New application program Program execution state Figure 16.4 User Program Mode Rev. 2.00, 03/04, page 381 of 508 16.3 Block Configuration Figure 16.5 shows the block configuration of 128-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units and the values are addresses. The flash memory is divided into 32 kbytes (2 blocks), 28 kbytes (1 block), 16 kbytes (1 block), 8 kbytes (2 blocks), and 1 kbyte (4 blocks). Erasing is performed in these units. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80. EB0 Erase unit 1 kbyte H'000000 H'000001 H'000002 H'000380 H'000381 H'000382 EB1 Erase unit 1 kbyte H'000400 H'000401 H'000402 H'000780 H'000781 H'000782 EB2 Erase unit 1 kbyte H'000800 H'000801 H'000802 H'000B80 H'000B81 H'000B82 EB3 Erase unit 1 kbyte H'000C00 H'000C01 H'000C02 H'000F80 H'000F81 H'000F82 H'001000 H'001001 H'001002 H'007F80 H'007F81 H'007F82 H'008000 H'008001 H'008002 H'00BF80 H'00BF81 H'00BF82 H'00C000 H'00C001 H'00C002 H'00DF80 H'00DF81 H'00DF82 H'00E000 H'00E001 H'00E002 H'00FF80 H'00FF81 H'00FF82 H'010000 H'010001 H'010002 H'017F80 H'017F81 H'017F82 H'018000 H'018001 H'018002 H'01FF80 H'01FF81 H'01FF82 EB4 Erase unit 28 kbytes EB5 Erase unit 16 kbytes EB6 Erase unit 8 kbytes EB7 Erase unit 8 kbytes EB8 Erase unit 32 kbytes EB9 Erase unit 32 kbytes Programming unit: 128 bytes H'0003FF Programming unit: 128 bytes H'00047F H'0007FF Programming unit: 128 bytes H'00087F H'000BFF Programming unit: 128 bytes H'000C7F H'000FFF Programming unit: 128 bytes H'00107F H'007FFF Programming unit: 128 bytes H'00807F H'00BFFF Programming unit: 128 bytes H'00C07F H'00DFFF Programming unit: 128 bytes H'00E07F H'00FFFF Programming unit: 128 bytes H'01007F H'017FFF Programming unit: 128 bytes Figure 16.5 Flash Memory Block Configuration Rev. 2.00, 03/04, page 382 of 508 H'00007F H'01807F H'01FFFF 16.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 16.2. Table 16.2 Pin Configuration Pin Name I/O Function RES Input Reset FWE Input Flash program/erase protection by hardware MD2 Input Sets this LSI's operating mode MD1 Input Sets this LSI's operating mode MD0 Input Sets this LSI's operating mode TxD1 Output Serial transmit data output RxD1 Input Serial receive data input 16.5 Register Descriptions The flash memory has the following registers. * * * * * * Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Erase block register 2 (EBR2) RAM emulation register (RAMER) Flash memory power control register (FLPWCR) Rev. 2.00, 03/04, page 383 of 508 16.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, see section 16.8, Flash Memory Programming/Erasing. Bit Bit Name Initial Value R/W Description 7 FWE R Reflects the input level at the FWE pin. It is cleared to 0 when a low level is input to the FWE pin, and set to 1 when a high level is input. 6 SWE 0 R/W Software Write Enable Bit When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, other FLMCR1 register bits and all EBR1 bits cannot be set. 5 ESU 0 R/W Erase Setup Bit When this bit is set to 1, the flash memory changes to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. 4 PSU 0 R/W Program Setup Bit When this bit is set to 1, the flash memory changes to the program setup state. When it is cleared to 0, the program setup state is cancelled. Set this bit to 1 before setting the P1 bit in FLMCR1. 3 EV 0 R/W Erase-Verify When this bit is set to 1, the flash memory changes to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. 2 PV 0 R/W Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. 1 E 0 R/W Erase When this bit is set to 1, and while the SWE1 and ESU1 bits are 1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P 0 R/W Program When this bit is set to 1, and while the SWE1 and PSU1 bits are 1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled. Rev. 2.00, 03/04, page 384 of 508 16.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to. Bit Bit Name Initial Value R/W Description 7 FLER 0 R Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. See section 16.9.3, Error Protection, for details. 6 to 0 All 0 R Reserved These bits are always read as 0. 16.5.3 Erase Block Register 1 (EBR1) EBR1 and EBR2 specify the flash memory erase area block. EBR1 and EBR2 initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit in EBR1 and EBR2 together at a time, as this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0. * EBR1 Bit Bit Name Initial Value R/W Description 7 EB7 0 R/W When this bit is set to 1, 8 kbytes of EB7 (H'00E000 to H'00FFFF) will be erased. 6 EB6 0 R/W When this bit is set to 1, 8 kbytes of EB6 (H'00C000 to H'00DFFF) will be erased. 5 EB5 0 R/W When this bit is set to 1, 16 kbytes of EB5 (H'008000 to H'00BFFF) will be erased. 4 EB4 0 R/W When this bit is set to 1, 28 kbytes of EB4 (H'001000 to H'007FFF) will be erased. 3 EB3 0 R/W When this bit is set to 1, 1 kbyte of EB3 (H'000C00 to H'000FFF) will be erased. 2 EB2 0 R/W When this bit is set to 1, 1 kbyte of EB2 (H'000800 to H'000BFF) will be erased. 1 EB1 0 R/W When this bit is set to 1, 1 kbyte of EB1 (H'000400 to H'0007FF) will be erased. 0 EB0 0 R/W When this bit is set to 1, 1 kbyte of EB0 (H'000000 to H'0003FF) will be erased. Rev. 2.00, 03/04, page 385 of 508 * EBR2 Bit Bit Name Initial Value R/W Description 7 to 2 All 0 R/W Reserved These bits are always read as 0. 1 EB9 0 R/W When this bit is set to 1, 32 kbytes of EB9 (H'018000 to H'01FFFF) will be erased. 0 EB8 0 R/W When this bit is set to 1, 32 kbytes of EB8 (H'010000 to H'017FFF) will be erased. 16.5.4 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER settings should be made in user mode or user program mode. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bit Bit Name Initial Value R/W Description 7, 6 All 0 R Reserved 5, 4 All 0 R/W Reserved 3 RAMS 0 R/W RAM Select These bits are always read as 0. Only 0 should be written to these bits. Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, the flash memory is overlapped with part of RAM, and all flash memory block are program/erase-protected. 2 RAM2 0 R/W Flash Memory Area Selection 1 RAM1 0 R/W 0 RAM0 0 R/W When the RAMS bit is set to 1, one of the following flash memory areas are selected to overlap the RAM area of H'FFE000 to H'FFE3FF. The areas correspond with 1-kbyte erase blocks. 00X: H'000000 to H'0003FF (EB0) 01X: H'000400 to H'0007FF (EB1) 10X: H'000800 to H'000BFF (EB2) 11X: H'000C00 to H'000FFF (EB3) Note: X Don't care Rev. 2.00, 03/04, page 386 of 508 16.5.5 Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when this LSI switches to subactive mode. For details, see section 16.12, Flash Memory and Power-Down Modes. Bit Bit Name Initial Value R/W Description 7 PDWND 0 R/W Power-Down Disable When this bit is set to 1, the transition to flash memory power-down mode is disabled. 6 to 0 All 0 R Reserved These bits always read 0. 16.6 On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the MD pin settings and FWE pin setting, as shown in table 16.3. The input level of each pin must be defined four states before the reset ends. When changing to boot mode, the boot program built into this LSI is initiated. The boot program transfers the programming control program from the externally-connected host to on-chip RAM via SCI_1. After erasing the entire flash memory, the programming control program is executed. This can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. In user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. Table 16.3 Setting On-Board Programming Modes MD2 MD0 FWE LSI State after Reset End 1 1 1 User Mode 0 1 1 Boot Mode Rev. 2.00, 03/04, page 387 of 508 16.6.1 Boot Mode Table 16.4 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 16.8, Flash Memory Programming/Erasing. 2. SCI_1 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI_1 bit rate to match that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 16.5. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'FFE800 to H'FFEFBF is the area to which the programming control program is transferred from the host. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. Before branching to the programming control program, the chip terminates transfer operations by SCI_1 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of write data or verify data with the host. The TxD pin is high. The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, as the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at least 20 states, and then setting the mode (MD) pins. Boot mode is also cleared when a WDT overflow occurs. 8. Do not change the MD pin input levels in boot mode. 9. All interrupts are disabled during programming or erasing of the flash memory. Rev. 2.00, 03/04, page 388 of 508 Table 16.4 Boot Mode Operation Host Operation Item Boot mode start LSI Operation Processing Contents Communications Contents Processing Contents Branches to boot program at reset-start. Boot program initiation Bit rate adjustment Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. H'00, H'00 ...... H'00 H'00 * Measures low-level period of receive data H'00. * Calculates bit rate and sets it in BRR of SCI_1. * Transmits data H'00 to host as adjustment end indication. H'55 H'AA Transmits data H'AA to host when data H'55 is received. Receives data H'AA. Transfer of programming control program Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) Transmits 1-byte of programming control program (repeated for N times) High-order byte and low-order byte Echobacks the 2-byte data received. Echoback H'XX Echoback Flash memory erase Boot program erase error H'FF H'AA Receives data H'AA. Echobacks received data to host and also transfers it to RAM (repeated for N times) Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.) Branches to programming control program transferred to on-chip RAM and starts execution. Table 16.5 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps 20 MHz 9,600 bps 8 to 20 MHz 4,800 bps 4 to 20 MHz Rev. 2.00, 03/04, page 389 of 508 16.6.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. As the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot mode. Figure 16.6 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 16.8, Flash Memory Programming/Erasing. Reset-start No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program Branch to user program/erase control program in RAM FWE=high* Execute user program/erase control program (flash memory rewrite) Clear FWE Branch to flash memory application program Note: * Do not constantly apply a high level to the FWE pin. Only apply a high level to the FWE pin when programming or erasing the flash memory. To prevent excessive programming or excessive erasing, while a high level is being applied to the FWE pin, activate the watchdog timer in case of handling CPU runaways. Figure 16.6 Programming/Erasing Flowchart Example in User Program Mode Rev. 2.00, 03/04, page 390 of 508 16.7 Flash Memory Emulation in RAM A setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. Emulation can be performed in user mode or user program mode. Figure 16.7 shows an example of emulation of real-time flash memory programming. 1. Set RAMER to overlap part of RAM onto the area for which real-time programming is required. 2. Emulation is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, thus releasing the RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space (EB0). Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 16.7 Flowchart for Flash Memory Emulation in RAM Rev. 2.00, 03/04, page 391 of 508 An example in which flash memory block area EB0 is overlapped is shown in figure 16.8. 1. The RAM area to be overlapped is fixed at a 1-kbyte area in the range H'FFE000 to H'FFE3FF. 2. The flash memory area to overlap is selected by RAMER from a 1-kbyte area of the EB0 to EB3 blocks. 3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM addresses. 4. When the RAMS bit in RAMER is set to 1, program/erase protection is enabled for all flash memory blocks (emulation protection). In this state, setting the P or E bit in FLMCR1 to 1 does not cause a transition to program mode or erase mode. 5. A RAM area cannot be erased by execution of software in accordance with the erase algorithm. 6. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlap RAM. H'000000 Flash memory (EB0) Flash memory (EB0) (EB1) On-chip RAM (Shadow of H'FFE000 to H'FFE3FF) (EB2) Flash memory (EB2) (EB3) (EB3) H'0003FF H'000400 H'0007FF H'000800 H'000BFF H'000C00 H'000FFF H'FFE000 On-chip RAM (1 kbyte) On-chip RAM (1 kbyte) H'FFE3FF Normal memory map RAM overlap memory map Figure 16.8 Example of RAM Overlap Operation Rev. 2.00, 03/04, page 392 of 508 16.8 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 16.8.1, Program/Program-Verify and section 16.8.2, Erase/Erase-Verify, respectively. 16.8.1 Program/Program-Verify When writing data or programs to the flash memory, the program/program-verify flowchart shown in Figure 16.9 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation and additional programming data computation according to Figure 16.9. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower eight bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P bit is set to 1 is the programming time. Figure 16.9 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of ( + z2 + + ) s is allowed. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 8. The maximum number of repetitions of the program/program-verify sequence of the same bit must not exceed (N). Rev. 2.00, 03/04, page 393 of 508 Write pulse application subroutine Start of programming Apply Write Pulse START Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. Set SWE bit in FLMCR1 WDT enable Wait (x) s Set PSU bit in FLMCR1 Wait ( ) s *7 *4 n= 1 Start of programming Set P bit in FLMCR1 *7 Store 128-byte program data in program data area and reprogram data area m= 0 Wait (z1) s, (z2) s, or (z3) s Clear P bit in FLMCR1 *5*7 Write 128-byte data in RAM reprogram data area consecutively to flash memory End of programming *1 Sub-Routine-Call Wait ( ) s Apply Write pulse of (z1) s or (z2) s *7 Wait ( ) s See Note 6 for pulse width Set PV bit in FLMCR1 Clear PSU bit in FLMCR1 Wait ( ) s *7 *7 H'FF dummy write to verify address Disable WDT End Sub Wait ( ) s *7 Read verify data *2 Write data = verify data? NG nn+1 Increment address Note 6: Write Pulse Width Number of Writes n Write Time (z) s 30 * 30 * 30 * 30 * 30 * 30 * 1 2 3 4 5 6 7 8 9 10 11 12 13 200 200 200 200 200 200 200 998 999 1000 200 200 200 m=1 OK NG 6n? OK Additional-programming data computation Transfer additional-programming data to additional-programming data area *4 *3 Reprogram data computation Transfer reprogram data to reprogram data area NG *4 128-byte data verification completed? OK Clear PV bit in FLMCR1 Reprogram Wait ( ) s Note: * Use a 10 s write pulse for additional programming. *7 NG 6 n? OK Successively write 128-byte data from additional1 programming data area in RAM to flash memory * RAM Program data storage area (128 bytes) Sub-Routine-Call Apply write Pulse (Additional programming) of (z3) s Reprogram data storage area (128 bytes) NG m= 0 ? n (N)? OK Clear SWE bit in FLMCR1 Additional-programming data storage area (128 bytes) *7 NG OK Clear SWE bit in FLMCR1 Wait ( ) s Wait ( ) s End of programming Programming failure *7 Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. 3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG. 4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM. The contents of the reprogram data area and additional data area are modified as programming proceeds. 5. A write pulse of 30 s or 200 s is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of additional-programming data is executed, a 10 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. 7. The values of x, y, z1, z2, z3, , , , , , and N are are shown in section 21.5, Flash Memory Characteristics. Reprogram Data Computation Table Additional-Programming Data Computation Table Original Data Verify Data Reprogram Data (D) 0 (V) 0 (X) 1 0 1 0 1 0 1 1 1 1 Comments Reprogram Data (X') Verify Data Additional(V) Programming Data (Y) Programming completed 0 0 0 Programming incomplete; reprogram 0 1 1 1 0 1 1 1 1 Still in erased state; no action Figure 16.9 Program/Program-Verify Flowchart Rev. 2.00, 03/04, page 394 of 508 Comments Additional programming to be executed Additional programming not to be executed Additional programming not to be executed Additional programming not to be executed 16.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 16.10 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in erase block register1 (EBR1) and erase block register2 (EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An overflow cycle higher than (y + z + + ) ms is allowed. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence must not exceed (N). 16.8.3 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. Interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. If interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the CPU malfunctions. 3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out. Rev. 2.00, 03/04, page 395 of 508 START *1 Set SWE bit in FLMCR1 Wait (x) s *2 n=1 *4 Set EBR1, EBR2 Enable WDT Set EBU bit in FLMCR2 Wait (y) s *2 Start of erase Set E bit in FLMCR1 Wait (z) ms n *2 n+1 Halt erase Clear E bit in FLMCR1 Wait ( ) s *2 Clear ESU bit in FLMCR2 Wait ( ) s *2 Disable WDT Set EV bit in FLMCR1 Wait ( ) s *2 Set block start address to verify address H'FF dummy write to verify address Wait () s *2 Read verify data Increment address *3 NG Verify data = all 1 ? OK NG Last address of block ? OK Clear EV bit in FLMCR1 Clear EV bit in FLMCR1 Wait () s Wait () s *2 NG Notes: 1. 2. 3. 4. 5. *5 End of erasing of all erase blocks ? *2 *2 nN? OK Clear SWE bit in FLMCR1 Clear SWE bit in FLMCR1 Wait ( ) s Wait ( ) s End of erasing Erase failure NG OK Preprogramming (setting erase block data to all 0) is not necessary. The values of x, y, z, , , , , , and are shown in section 21.5, Flash Memory Characteristics. Verify data is read in 16-bit(W) units. Set only one bit in EBR1 or EBR2. More than one bit cannot be set. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially. Figure 16.10 Erase/Erase-Verify Flowchart Rev. 2.00, 03/04, page 396 of 508 16.9 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 16.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register2 (EBR2) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 16.9.2 Software Protection Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P1 or E1 bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting erase block register 1 (EBR1) or erase block register2 (EBR2), erase protection can be set for individual blocks. When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks. Setting the RAMS bit in RAMER also implements protection against programming/erasing of all flash memory blocks. Rev. 2.00, 03/04, page 397 of 508 16.9.3 Error Protection In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling (excluding a reset) during programming/erasing * When a SLEEP instruction is executed during programming/erasing The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a power-on reset. 16.10 Programmer Mode In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as for a discrete flash memory. Use a PROM programmer that supports the Renesas Technology's 128-kbyte flash memory on-chip MCU device type (FZTAT128V5A). Rev. 2.00, 03/04, page 398 of 508 16.11 Power-Down States for Flash Memory In user mode, the flash memory will operate in either of the following states: * Normal operating mode The flash memory can be read and written to. * Power-down mode: Part of the power supply circuitry is halted, and the flash memory can be read when the LSI is operating on the subclock. * Standby mode All flash memory circuits are halted. Table 16.6 shows the correspondence between the operating modes of this LSI and the flash memory. When the flash memory returns to its normal operating state from standby mode, a period to stabilize the power supply circuits that were stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 20 s, even when the external clock is being used. Table 16.6 Flash Memory Operating States LSI Operating State Flash Memory Operating State High-speed mode Normal mode Medium-speed mode Sleep mode Subactive mode When PDWND = 0: Power-down mode (read-only) Subsleep mode When PDWND = 1: Normal mode (read-only) Watch mode Standby mode Software standby mode Hardware standby mode 16.12 Flash Memory and Power-Down Modes In power-down modes, flash memory registers (FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and FLPWCR) cannot be read from or written to. Rev. 2.00, 03/04, page 399 of 508 Rev. 2.00, 03/04, page 400 of 508 Section 17 Mask ROM This LSI has 64 or 128 kbytes of on-chip mask ROM. On-chip ROM is connected to the CPU via a 16-bit data bus. Data in on-chip ROM can always be accessed by one state. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000001 H'000002 H'000003 H'01FFFE H'01FFFF Figure 17.1 Block Diagram of 128-Kbyte Masked ROM (HD6432282) Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000001 H'000002 H'000003 H'00FFFE H'00FFFF Figure 17.2 Block Diagram of 64-Kbyte Masked ROM (HD6432281) Rev. 2.00, 03/04, page 401 of 508 17.1 Note on Switching from F-ZTAT Version to Masked ROM Version The masked ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 17.1 lists the registers that are present in the F-ZTAT version but not in the masked ROM version. If a register listed in table 17.1 is read in the masked ROM version, an undefined value will be returned. Therefore, if application software developed on the F-ZTAT version is switched to a masked ROM version product, it must be modified to ensure that the registers in table 17.1 have no effect. Table 17.1 Register Present in F-ZTAT Version but Absent in Masked ROM Version Register Abbreviation Address Flash memory control register 1 FLMCR1 H'FFA8 Flash memory control register 2 FLMCR2 H'FFA9 Erase block designate register 1 EBR1 H'FFAA Erase block designate register 2 EBR2 H'FFAB RAM emulation register RAMER H'FEDB Flash memory power control register FLPWCR H'FFAC Rev. 2.00, 03/04, page 402 of 508 Section 18 Clock Pulse Generator This LSI has an on-chip clock pulse generator that generates the system clock (), the bus master clock, internal clocks, and subclock. The clock pulse generator consists of an oscillator, PLL circuit, subclock divider, clock selection circuit, medium-speed clock divider, and bus master clock selection circuit. A block diagram of the clock pulse generator is shown in figure 18.1. SCKCR LPWRCR SCK2 to SCK0 STC1, STC0 EXTAL Clock oscillator PLL circuit (x1, x2, x4) XTAL Clock selection circuit Mediumspeed clock divider SUB Subclock divider (division by 128) Subclock to WDT1, LCD /2 to /32 System clock to pin Bus master clock selection circuit Internal clock to supporting modules Bus master clock to CPU [Legend] LPWRCR: Low-power control register SCKCR: System clock control register Figure 18.1 Block Diagram of Clock Pulse Generator The frequency can be changed by means of the PLL circuit. Frequency changes are performed by software by settings in the low-power control register (LPWRCR) and system clock control register (SCKCR). CPG0502A_000020020200 Rev. 2.00, 03/04, page 403 of 508 18.1 Register Descriptions The on-chip clock pulse generator has the following registers. * System clock control register (SCKCR) * Low-power control register (LPWRCR) 18.1.1 System Clock Control Register (SCKCR) SCKCR performs clock output control, selection of operation when the PLL circuit frequency multiplication factor is changed, and medium-speed mode control. Bit Bit Name Initial Value R/W Description 7 PSTOP 0 R/W Clock Output Disable Controls output. * High-speed Mode, Medium-Speed Mode 0: output 1: Fixed high * Sleep Mode 0: output 1: Fixed high * Software Standby Mode 0: Fixed high 1: Fixed high * Hardware Standby Mode 0: High impedance 1: High impedance 6 to 4 All 0 Reserved These bits are always read as 0. 3 STCS 0 R/W Frequency Multiplication Factor Switching Mode Select Selects the operation when the PLL circuit frequency multiplication factor is changed. 0: Specified multiplication factor is valid after transition to software standby mode 1: Specified multiplication factor is valid immediately after the STC1 and STC0 bits are rewritten Rev. 2.00, 03/04, page 404 of 508 Bit Bit Name Initial Value R/W Description 2 SCK2 0 R/W System Clock Select 0 to 2 1 SCK1 0 R/W These bits select the bus master clock. 0 SCK0 0 R/W 000: High-speed mode 001: Medium-speed clock is /2 010: Medium-speed clock is /4 011: Medium-speed clock is /8 100: Medium-speed clock is /16 101: Medium-speed clock is /32 11X: Setting prohibited [Legend] X: Don't care Rev. 2.00, 03/04, page 405 of 508 18.1.2 Low-Power Control Register (LPWRCR) LPWRCR performs power-down mode control, subclock generation control, oscillation circuit feedback resistance control, and frequency multiplication factor setting. Bit Bit Name Initial Value R/W Description 7 DTON 0 R/W 6 LSON 0 R/W See section 19.1.2, Low-Power Control Register (LPWRCR). 5 0 R/W Reserved Only write 0 to this bit. 4 SUBSTP 0 R/W Subclock Generation Control 0: Enables subclock generation 1: Disables subclock generation 3 RFCUT 0 R/W Oscillation Circuit Feedback Resistance Control 0: When the main clock is oscillating, sets the feedback resistance ON. When the main clock is stopped, sets the feedback resistance OFF. 1: Sets the feedback resistance OFF. Modification becomes valid after returning to software standby transfer. Note: With a crystal resonator, the resonator will not operate if this bit is set to 1. 2 0 R/W Reserved Only write 0 to this bit. 1 STC1 0 R/W Frequency Multiplication Factor 0 STC0 0 R/W The STC bits specify the frequency multiplication factor of the PLL circuit. 00: x1 01: x2 10: x4 11: Setting prohibited Rev. 2.00, 03/04, page 406 of 508 18.2 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. In either case, the input clock should not exceed 4 MHz to 20 MHz. 18.2.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 18.2. Select the damping resistance Rd according to table 18.2. An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF Figure 18.2 Connection of Crystal Resonator (Example) Table 18.1 Damping Resistance Value Frequency (MHz) 4 8 12 16 20 Rd () 500 200 0 0 0 Figure 18.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 18.2. CL L XTAL Rs C0 EXTAL AT-cut parallel-resonance type Figure 18.3 Crystal Resonator Equivalent Circuit Table 18.2 Crystal Resonator Characteristics Frequency (MHz) 4 8 12 16 20 RS max () 120 80 60 50 40 C0 max (pF) 7 7 7 7 7 Rev. 2.00, 03/04, page 407 of 508 18.2.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 18.4. If the XTAL pin is left open, ensure that stray capacitance does not exceed 10 pF. When complementary clock is input to the XTAL pin, the external clock input should be fixed high in standby mode. External clock input EXTAL Open XTAL (a) XTAL pin left open External clock input EXTAL XTAL (b) Complementary clock input at XTAL pin Figure 18.4 External Clock Input (Examples) Table 18.3 shows the input conditions for the external clock. Table 18.3 External Clock Input Conditions VCC = 5.0 V 10% Item Symbol Min. Max. Unit Test Conditions External clock input low pulse width tEXL 15 ns Figure 18.5 External clock input high pulse width tEXH 15 ns External clock rise time tEXr 5 ns External clock fall time tEXf 5 ns Clock low pulse width level tCL 0.4 0.6 tcyc 5 MHz 80 ns < 5 MHz Clock high pulse width level tCH 0.4 0.6 tcyc 5 MHz 80 ns < 5 MHz Rev. 2.00, 03/04, page 408 of 508 Figure 21.2 tEXH tEXL VCC EXTAL tEXr 0.5 tEXf Figure 18.5 External Clock Input Timing 18.3 PLL Circuit The PLL circuit multiplies the frequency of the clock from the oscillator by a factor of 1, 2, or 4. The multiplication factor is set by the STC0 and STC1 bits in LPWRCR. The phase of the rising edge of the internal clock is controlled so as to match that at the EXTAL pin. When the multiplication factor of the PLL circuit is changed, the operation varies according to the setting of the STCS bit in SCKCR. When STCS = 0, the setting becomes valid after a transition to software standby mode. The transition time count is performed in accordance with the setting of bits STS0 to STS2 in SBYCR. For details on SBYCR, see section 19.1.1, Standby Control Register (SBYCR). 1. 2. 3. 4. 5. The initial PLL circuit multiplication factor is 1. STS0 to STS2 are set to give the specified transition time. The target value is set in STC0 and STC1, and a transition is made to software standby mode. The clock pulse generator stops and the value set in STC0 and STC1 becomes valid. Software standby mode is cleared, and a transition time is secured in accordance with the setting in STS0 to STS2. 6. After the set transition time has elapsed, this LSI resumes operation using the target multiplication factor. 18.4 Subclock Divider The subclock divider divides the clock generated by the oscillator by 128 to generate a subclock. When using the subclock as a system clock, the compensation by software is needed. 18.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32. Rev. 2.00, 03/04, page 409 of 508 18.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the clock supplied to the bus master by setting the bits SCK 2 to SCK0 in SCKCR. The bus master clock can be selected from high-speed mode, or medium-speed clocks (/2, /4, /8, /16, and /32). 18.7 Usage Notes 18.7.1 Note on Crystal Resonator As various characteristics related to the crystal resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a guide. As the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 18.7.2 Note on Board Design When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillator circuit, as shown in figure 18.6. This is to prevent induction from interfering with correct oscillation. Signal A Signal B Avoid CL2 This LSI XTAL EXTAL CL1 Figure 18.6 Note on Board Design of Oscillator Circuit Figure 18.7 shows external circuitry recommended to be provided around the PLL circuit. Place oscillation stabilization capacitor C1 and resistor R1 close to the PLLCAP pin, and ensure that no other signal lines cross this line. Separate PLLVcL and PLLVss from the other Vcc and Vss lines at the board power supply source, and be sure to insert bypass capacitors CB close to the pins. Rev. 2.00, 03/04, page 410 of 508 R1 : 3 k C1 : 470 pF PLLCAP PLLVSS VCL VCC CB : 0.1 F CB : 0.1 F VSS (Values are preliminary recommended values.) Note: CB are laminated ceramic. Figure 18.7 External Circuitry Recommended for PLL Circuit Rev. 2.00, 03/04, page 411 of 508 Rev. 2.00, 03/04, page 412 of 508 Section 19 Power-Down Modes In addition to the normal program execution state, this LSI has power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on. This LSI's operating modes are as follows: * * * * * * * * * High-speed mode Medium-speed mode Subactive mode Sleep mode Subsleep mode Watch mode Module stop mode Software standby mode Hardware standby mode Sleep mode and subsleep mode are CPU states, medium-speed mode is a CPU and bus master state, subactive mode is a CPU, bus master, and on-chip peripheral function state, and module stop mode is an on-chip peripheral function (including bus masters other than the CPU) state. Some of these states can be combined. After a reset, the LSI operates in high-speed mode or module stop mode. Figure 19.1 shows the mode transition diagram. Table 19.1 shows the conditions for transition to each mode when a SLEEP instruction is executed, and table 19.2 shows the internal state of the LSI in each mode. LPWS269A_000020020200 Rev. 2.00, 03/04, page 413 of 508 Program-halted state pin = Low Reset state pin = High, pin = Low Hardware standby mode pin = High program execution state SSBY = 0 Sleep command High-speed mode (main clock) SCK2 to SCK0 = 0 SCK2 to SCK0 0 Medium-speed mode (main clock) Sleep command Sleep command SSBY = 1, PSS = 1, DTON = 1, LSON = 0 SSBY = 1, PSS = 1, DTON = 1, LSON = 1 After the oscillation stabilization time (STS2 to STS0), clock switching exception processing Clock switching exception processing All interrupts *3 Sleep command External interrupt *4 Software standby mode SSBY = 1 PSS = 1, DTON = 0 Interrupt*1, LSON bit = 0 Watch mode (subclock) Sleep command Sleep command Interrupts *2 : Transition after exception processing Notes : *1 *2 *3 *4 SSBY = 1 Sleep command Interrupt*1, LSON bit = 1 Subactive mode (subclock) Sleep mode (main clock) SSBY = 0 PSS = 1, LSON = 1 Subsleep mode (subclock) : Power-down mode NMI, IRQ0 to IRQ5, and WDT_1 interrupts NMI, IRQ0 to IRQ5, WDT_0, and WDT_1 interrupts All interrupts NMI and IRQ0 to IRQ5 When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. From any state except hardware standby mode, a transition to the reset state occurs when is driven Low. From any state, a transition to hardware standby mode occurs when is driven low. Always select high-speed mode before making a transition to watch mode or subactive mode. Figure 19.1 Mode Transition Diagram Rev. 2.00, 03/04, page 414 of 508 Table 19.1 Power-Down Mode Transition Conditions PreTransition State Status of Control Bit at Transition State after Transition back from PowerDown Mode Invoked by Interrupt PSS LSON DTON State after Transition Invoked by SLEEP Instruction High-speed/ 0 Mediumspeed 0 * 0 * Sleep High-speed/Mediumspeed * 1 * 1 0 0 * Software standby High-speed/Mediumspeed 1 0 1 * 1 1 0 0 Watch High-speed 1 1 1 0 Watch Subactive 1 1 0 1 1 1 1 1 Subactive 0 0 * * 0 1 0 * 0 1 1 * Subsleep Subactive 1 0 * * 1 1 0 0 Watch High-speed 1 1 1 0 Watch Subactive 1 1 0 1 High-speed 1 1 1 1 Subactive SSBY [Legend] *: Don't care : Setting prohibited Rev. 2.00, 03/04, page 415 of 508 Table 19.2 LSI Internal States in Each Mode High- Medium- Function Speed Speed System clock pulse generator Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted CPU External interrupts Module Sleep Stop Watch Subactive Subsleep Software Hardware Standby Standby Halted Instructions Functioning Medium- Halted High/ Halted Subclock Halted Halted Halted Registers (retained) mediumspeed operation (retained) operation (retained) (retained) (undefined) NMI speed operation Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted IRQ0 to IRQ5 Peripheral WDT_1 Functioning Functioning Functioning Subclock Subclock Subclock Halted Halted operation operation operation (retained) (reset) Halted Subclock Subclock Halted Halted (retained) operation operation (retained) (reset) Halted Halted Halted Halted Halted (retained) (retained) (retained) (retained) (reset) Functioning Functioning Functioning Halted Halted Halted Halted Halted Halted (reset) (reset) (reset) (reset) (reset) (reset) Functioning Functioning Functioning Halted Halted functions WDT_0 TPU_0 Functioning Functioning Functioning Functioning Functioning Functioning Halted (retained) TPU_1 TPU_2 SCI_0 SCI_1 RWM HCAN A/D LCD Functioning Functioning Functioning Halted (retained) RAM Functioning Functioning Halted (retained) (reset) Retained Functioning Retained Functioning Retained Retained Functioning Functioning Functioning Functioning Retained Functioning Retained Retained (retained) I/O High impedance Notes: 1. "Halted (retained)" means that internal register values are retained. The internal state is "operation suspended." 2. "Halted (reset)" means that internal register values and internal states are initialized. 3. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). 4. When the LCD is operated in watch mode, subactive mode, or subsleep mode, select the subclock as a system clock. Rev. 2.00, 03/04, page 416 of 508 19.1 Register Descriptions Registers related to power-down modes are shown below. For details on the system clock control register (SCKCR), see section 18.1.1, System Clock Control Register (SCKCR). * * * * * * * System clock control register (SCKCR) Standby control register (SBYCR) Low-power control register (LPWRCR) Module stop control register A (MSTPCRA) Module stop control register B (MSTPCRB) Module stop control register C (MSTPCRC) Module stop control register D (MSTPCRD) 19.1.1 Standby Control Register (SBYCR) SBYCR performs software standby mode control. Bit Bit Name Initial Value R/W Description 7 SSBY 0 R/W Software Standby This bit specifies the transition mode after executing the SLEEP instruction 0: Shifts to sleep mode when the SLEEP instruction is executed 1: Shifts to software standby mode when the SLEEP instruction is executed This bit does not change when clearing the software standby mode by using external interrupts and shifting to normal operation. This bit should be written with 0 when clearing. Rev. 2.00, 03/04, page 417 of 508 Bit Bit Name Initial Value R/W Description 6 STS2 0 R/W Standby Timer Select 0 to 2 5 STS1 0 R/W 4 STS0 0 R/W These bits select the MCU wait time for clock stabilization when software standby mode is cancelled by an external interrupt. With a crystal oscillator (Table 19.3), select a wait time of 8 ms (oscillation stabilization time) or more, depending on the operating frequency. With an external clock, select a wait time of 2 ms or more. 000: Standby time = 8192 states 001: Standby time = 16384 states 010: Standby time = 32768 states 011: Standby time = 65536 states 100: Standby time = 131072 states 101: Standby time = 262144 states 110: Reserved 111: Standby time = 16 states 3 1 R/W Reserved All 0 Reserved The write value should always be 1. 2 to 0 These bits are always read as 0 and cannot be modified. Rev. 2.00, 03/04, page 418 of 508 19.1.2 Low-Power Control Register (LPWRCR) LPWRCR is an 8-bit readable/writable register that performs power-down mode control, subclock generation control, oscillation circuit feedback resistance control, and frequency multiplication factor setting. Bit Bit Name Initial Value R/W Description 7 DTON 0 R/W Direct Transition ON Flag 0: When the SLEEP instruction is executed in highspeed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*. When the SLEEP instruction is executed in subactive mode, operation shifts to subsleep mode or watch mode. 1: When the SLEEP instruction is executed in highspeed mode or medium-speed mode, operation shifts directly to subactive mode*, or shifts to sleep mode or software standby mode. When the SLEEP instruction is executed in subactive mode, operation shifts directly to high-speed mode, or shifts to subsleep mode. 6 LSON 0 R/W Low-Speed ON Flag 0: When the SLEEP instruction is executed in highspeed mode or medium-speed mode, operation shifts to sleep mode, software standby mode, or watch mode*. When the SLEEP instruction is executed in subactive mode, operation shifts to watch mode or shifts directly to high-speed mode. Operation shifts to high-speed mode when watch mode is cancelled. 1: When the SLEEP instruction is executed in highspeed mode, operation shifts to watch mode or subactive mode*. When the SLEEP instruction is executed in sub-active mode, operation shifts to subsleep mode or watch mode. Operation shifts to subactive mode when watch mode is cancelled. 5 0 R/W Reserved This bit can be read from and written to. However, do not write 1 to this bit. 4 SUBSTP 0 R/W Subclock Generation Control 0: Enables subclock generation 1: Disables subclock generation Rev. 2.00, 03/04, page 419 of 508 Bit Bit Name Initial Value R/W Description 3 RFCUT 0 R/W Oscillation Circuit Feedback Resistance Control 0: When the main clock is oscillating, sets the feedback resistance ON. When the main clock is stopped, sets the feedback resistance OFF. 1: Sets the feedback resistance OFF. Note: With a crystal resonator, the resonator will not operate if this bit is set to 1. 2 0 R/W Reserved This bit can be read from and written to. However, do not write 1 to this bit. 1 STC1 0 R/W Frequency Multiplication Factor Setting 0 STC0 0 R/W These bits specify the frequency multiplication factor of the PLL circuit. 00: x1 01: x2 10: x4 11: Setting prohibited Note: * Always set high-speed mode when shifting to watch mode or subactive mode. Rev. 2.00, 03/04, page 420 of 508 19.1.3 Module Stop Control Registers A to D (MSTPCRA to MSTPCRD) MSTPCR performs module stop mode control. Setting a bit to 1 causes the corresponding module to enter module stop mode. Clearing the bit to 0 clears the module stop mode. * MSTPCRA Bit Bit Name Initial Value R/W 7 MSTPA7* 0 R/W 6 MSTPA6* 0 R/W 5 MSTPA5 1 R/W 4 MSTPA4* 1 R/W 3 MSTPA3* 1 R/W 2 MSTPA2* 1 R/W 1 MSTPA1 1 R/W 0 MSTPA0* 1 R/W Module 16-bit timer pulse unit (TPU) A/D converter * MSTPCRB Bit Bit Name Initial Value R/W Module 7 MSTPB7 1 R/W Serial communication interface_0 (SCI_0) 6 MSTPB6 1 R/W Serial communication interface_1 (SCI_1) 5 MSTPB5* 1 R/W 4 MSTPB4* 1 R/W 3 MSTPB3* 1 R/W 2 MSTPB2* 1 R/W 1 MSTPB1* 1 R/W 0 MSTPB0* 1 R/W Rev. 2.00, 03/04, page 421 of 508 * MSTPCRC Bit Bit Name Initial Value R/W 7 MSTPC7* 1 R/W 6 MSTPC6* 1 R/W 5 MSTPC5* 1 R/W 4 MSTPC4* 1 R/W 3 MSTPC3 1 R/W 2 MSTPC2* 1 R/W 1 MSTPC1* 1 R/W 0 MSTPC0* 1 R/W Module Controller Area Network (HCAN) * MSTPCRD Bit Bit Name Initial Value R/W Module 7 MSTPD7 1 R/W Motor control PWM timer (PWM) 6 MSTPD6 1 R/W LCD controller/driver (LCD) 5 Undefined 4 Undefined 3 Undefined 2 Undefined 1 Undefined 0 Undefined Note: * MSTPA7 and MSTPA6 are readable/writable bits with an initial value of 0 and should always be written with 0. MSTPA4 to MSTPA2, MSTPA0, MSTPB5 to MSTPB0, MSTPC7 to MSTPC4 and MSTPC2 to MSTPC0 are readable/writable bits with an initial value of 1 and should always be written with 1. Rev. 2.00, 03/04, page 422 of 508 19.2 Medium-Speed Mode When the SCK0 to SCK2 bits in SCKCR are set to 1, the operating mode changes to mediumspeed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (/2, /4, /8, /16, or /32) specified by the SCK0 to SCK2 bits. On-chip peripheral modules other than bus masters always operate on the high-speed clock (). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip memory is accessed in four states, and internal I/O registers in eight states. Medium-speed mode is cleared by clearing all of bits SCK0 to SCK2 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit is set to 1, operation shifts to the software standby mode. When software standby mode is cleared by an external interrupt, mediumspeed mode is restored. When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 19.2 shows the timing for transition to and clearance of medium-speed mode. Medium-speed mode , supporting module clock Bus master clock Internal address bus SCKCR SCKCR Internal write signal Figure 19.2 Medium-Speed Mode Transition and Clearance Timing Rev. 2.00, 03/04, page 423 of 508 19.3 Sleep Mode 19.3.1 Transition to Sleep Mode If the SLEEP instruction is executed when the SSBY bit in SBYCR = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops, however the contents of the CPU's internal registers are retained. Other peripheral modules do not stop. 19.3.2 Clearing Sleep Mode Sleep mode is cleared by any interrupt, or signals at the RES or STBY pin. * Exiting sleep mode by interrupts: When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or if interrupts other than NMI are masked by the CPU. * Exiting sleep mode by RES pin: Setting the RES pin low selects the reset state. After the stipulated reset input duration, driving the RES pin high restart the CPU performing reset exception processing. * Exiting sleep mode by STBY pin: When the STBY pin level is driven low, a transition is made to hardware standby mode. Rev. 2.00, 03/04, page 424 of 508 19.4 Software Standby Mode 19.4.1 Transition to Software Standby Mode A transition is made to software standby mode if the SLEEP instruction is executed when the SSBY bit is set to 1. In this mode, the CPU, on-chip peripheral modules, and oscillator, all stop. However, the contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip peripheral modules other than the SCI, PWM, HCAN, and A/D converter, and the states of I/O ports, are retained. In this mode, the oscillator stops, and therefore power dissipation is significantly reduced. 19.4.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI and IRQ0 to IRQ5 pins), or by means of the RES pin or STBY pin. * Clearing with an interrupt When an NMI, IRQ0, or IRQ5 interrupt request signal is input, clock oscillation starts, and after the time set in bits STS0 to STS2 in SBYCR has elapsed, stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side. * Clearing with the RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. * Clearing with the STBY pin When the STBY pin is driven low, a transition is made to hardware standby mode. Rev. 2.00, 03/04, page 425 of 508 19.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. * Using a crystal oscillator: Set bits STS0 to STS2 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 19.3 shows the standby times for different operating frequencies and settings of bits STS0 to STS2. * Using an external clock The PLL circuit requires a time for stabilization. Set bits STS0 to STS2 so that the standby time is at least 2 ms (the oscillation stabilization time). Table 19.3 Oscillation Stabilization Time Settings 20 STS2 STS1 STS0 Standby Time MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz Unit 0 ms 0 1 0 8192 states 0.41 0.51 0.68 0.8 1.0 1.3 2.0 1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1 1 0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 8.2 1 65536 states 3.3 4.1 5.5 6.6 8.2 10.9 16.4 0 0 131072 states 6.6 8.2 10.9 13.1 16.4 21.8 32.8 1 262144 states 13.1 16.4 21.8 26.2 32.8 43.6 65.6 0 Reserved 1 16 states* 0.8 1.0 1.3 1.6 2.0 1.7 4.0 s 1 : Note: * Recommended time setting Do not use this setting Rev. 2.00, 03/04, page 426 of 508 19.4.4 Software Standby Mode Application Example Figure 19.3 shows an example in which a transition is made to software standby mode at a falling edge on the NMI pin, and software standby mode is cleared at a rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator NMI NMIEG SSBY Software standby mode NMI exception (power-down mode) processing NMIEG = 1 SSBY = 1 SLEEP command NMI exception processing Oscillation stabilization time tosc2 Figure 19.3 Software Standby Mode Application Example Rev. 2.00, 03/04, page 427 of 508 19.5 Hardware Standby Mode 19.5.1 Transition to Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD0 and MD2) while this LSI is in hardware standby mode. 19.5.2 Clearing Hardware Standby Mode Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms--the oscillation stabilization time--when using a crystal oscillator). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. Rev. 2.00, 03/04, page 428 of 508 19.5.3 Hardware Standby Mode Timings Timing of Transition to Hardware Standby Mode: 1. To retain RAM contents with the RAME bit set to 1 in SYSCR Drive the RES signal low at least 10 states before the STBY signal goes low, as shown in figure 19.4. After STBY has gone low, RES has to wait for at least 0 ns before becoming high. t110tcyc t20ns Figure 19.4 Timing of Transition to Hardware Standby Mode 2. To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained RES does not have to be driven low as in the above case. Timing of Recovery from Hardware Standby Mode: Drive the RES signal low approximately 100 ns or longer before STBY goes high to execute a power-on reset. t100ns tOSC1 Figure 19.5 Timing of Recovery from Hardware Standby Mode Rev. 2.00, 03/04, page 429 of 508 19.6 Module Stop Mode Module stop mode can be set for individual on-chip peripheral modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI (some SCI registers are retained), PWM, HCAN, and A/D converter are retained. After reset clearance, all modules are in module stop mode. When an on-chip peripheral module is in module stop mode, read/write access to its registers is disabled. Rev. 2.00, 03/04, page 430 of 508 19.7 Watch Mode 19.7.1 Transition to Watch Mode CPU operation makes a transition to watch mode when the SLEEP instruction is executed in highspeed mode or subactive mode with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 0, and the PSS bit in TCSR_1 (WDT_1) = 1. In watch mode, the CPU is stopped and peripheral modules other than WDT_1 and LCD are also stopped. The contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip peripheral modules other than the SCI, PWM, HCAN, and A/D converter, and the states of I/O ports, are retained. 19.7.2 Canceling Watch Mode Watch mode is canceled by any interrupt (WOVI1 interrupt, NMI pin, or IRQ0 to IRQ5 pin), or signals at the RES, or STBY pin. Canceling Watch Mode by Interrupt: When an interrupt occurs, watch mode is canceled and a transition is made to high-speed mode or medium-speed mode when the LSON bit in LPWRCR = 0 or to subactive mode when the LSON bit = 1. When a transition is made to high-speed mode, a stable clock is supplied to all LSI circuits and interrupt exception processing starts after the time set in the STS2 to STS0 bits of SBYCR has elapsed. In case of an IRQ0 to IRQ5 interrupt, watch mode is not canceled if the corresponding enable bit has been cleared to 0. In case of the interrupt from the on-chip peripheral modules, if the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the CPU, watch mode is not canceled. For the setting of the oscillation stabilization time when making a transition from watch mode to high-speed mode, see section 19.4.3, Setting Oscillation Stabilization Time after Clearing Software Standby Mode. Canceling Watch Mode by RES pin: For canceling watch mode by the RES pin, see section 19.4.2, Clearing Software Standby Mode. Canceling Watch Mode by STBY pin: When the STBY pin is driven low, a transition is made to hardware standby mode. Rev. 2.00, 03/04, page 431 of 508 19.8 Subsleep Mode 19.8.1 Transition to Subsleep Mode When the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR = 0, the LSON bit in LPWRCR = 1, and the PSS bit in TCSR_1 (WDT_1) = 1, CPU operation shifts to subsleep mode. In subsleep mode, the CPU is stopped and peripheral modules other than WDT_0, WDT_1, and LCD are also stopped. The contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip peripheral modules other than the SCI, PWM, HCAN, and A/D converter, and the states of I/O ports, are retained. 19.8.2 Canceling Subsleep Mode Subsleep mode is canceled by any interrupt (WOVI0 or WOVI1 interrupt, NMI pin, or IRQ0 to IRQ5 pin), or signals at the RES or STBY pin. Canceling Subsleep Mode by Interrupt: When an interrupt occurs, subsleep mode is canceled and interrupt exception processing starts. In case of an IRQ0 to IRQ5 interrupt, subsleep mode is not canceled if the corresponding enable bit has been cleared to 0. In case of the interrupt from the on-chip peripheral modules, if the interrupt enable register has been set to disable the reception of that interrupt, or is masked by the CPU, subsleep mode is not canceled. Canceling Subsleep Mode by RES pin: For canceling subsleep mode by the RES pin, see section 19.4.2, Clearing Software Standby Mode. Canceling Subsleep Mode by STBY pin: When the STBY pin is driven low, a transition is made to hardware standby mode. Rev. 2.00, 03/04, page 432 of 508 19.9 Subactive Mode 19.9.1 Transition to Subactive Mode CPU operation makes a transition to subactive mode when the SLEEP instruction is executed in high-speed mode with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 1, the LSON bit = 1, and the PSS bit in TCSR_1 (WDT_1) = 1. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1,a transition is made to subactive mode. And if an interrupt occurs in subsleep mode, a transition is made to subactive mode. In subactive mode, the CPU operates at low speed on the subclock, and the program is executed one after another. Peripheral modules other than WDT_0, WDT_1, and LCD are also stopped. When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SCKCR must be set to 0. 19.9.2 Canceling Subactive Mode Subactive mode is canceled by the SLEEP instruction or signals at the RES or STBY pin. Canceling Subactive Mode by SLEEP Instruction: When the SLEEP instruction is executed with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 0, and the PSS bit in TCSR_1 (WDT_1) = 1, subactive mode is canceled and a transition is made to watch mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR = 0, the LSON bit in LPWRCR = 1, and the PSS bit in TCSR_1 (WDT_1) = 1, a transition is made to subsleep mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 1, the LSON bit = 0, and the PSS bit in TCSR_1 (WDT_1) = 1, a direct transition is made to highspeed mode (SCK0 to SCK2 are all 0). Canceling Subactive Mode by RES pin: For canceling subactive mode by the RES pin, see section 19.4.2, Clearing Software Standby Mode. Canceling Subactive Mode by STBY pin: When the STBY pin is driven low, a transition is made to hardware standby mode. Rev. 2.00, 03/04, page 433 of 508 19.10 Direct Transitions There are three modes, high-speed, medium-speed, and subactive, in which the CPU executes programs. When a direct transition is made, there is no interruption of program execution in shifting between high-speed and subactive modes. Direct transitions are enabled by setting the DTON bit in LPWRCR to 1, then executing the SLEEP instruction. After a transition, direct transition interrupt exception processing starts. 19.10.1 Direct Transitions from High-Speed Mode to Subactive Mode Execute the SLEEP instruction in high-speed mode with the SSBY bit in SBYCR = 1, the LSON bit in LPWRCR= 1, the DTON bit = 1, and the PSS bit in TCSR_1 (WDT_1) = 1, to make a direct transition to subactive mode. 19.10.2 Direct Transitions from Subactive Mode to High-Speed Mode Execute the SLEEP instruction in subactive mode with the SSBY bit in SBYCR = 1, the LSON bit in LPWRCR = 0, the DTON bit = 1, and the PSS bit in TCSR_1 (WDT_1) = 1, to make a direct transition to high-speed mode after the time set in the STS2 to STS0 bits of SBYCR has elapsed. 19.11 Clock Output Disabling Function The output of the clock can be controlled by means of the PSTOP bit in SCKCR and DDR for the corresponding port. When the PSTOP bit is set to 1, the clock stops at the end of the bus cycle, and output goes high. clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, clock output is disabled and input port mode is set. Table 19.4 shows the state of the pin in each processing state. Table 19.4 Pin State in Each Processing State Register Settings Software Standby Mode Watch Mode Direct Sleep Mode Subsleep Mode Transitions DDR PSTOP High-Speed Mode Medium-Speed Subactive Mode Mode 0 X High impedance High impedance High impedance High impedance High impedance 1 0 output SUB output output Fixed high High impedance 1 1 Fixed high Fixed high Fixed high Fixed high High impedance [Legend] X: Don't care Rev. 2.00, 03/04, page 434 of 508 Hardware Standby Mode 19.12 Usage Notes 19.12.1 I/O Port Status The status of the I/O ports is retained in watch mode. Also, when the OPE bit is set to 1, the address bus and bus control signals continue to be output. Therefore, when a high level is output, the current consumption is not diminished by the amount of current to support the high level output. 19.12.2 Current Dissipation during Oscillation Stabilization Wait Period The current consumption increases during the oscillation stabilization wait period. 19.12.3 On-Chip Peripheral Module Interrupt The on-chip peripheral module (TPU), which halts in subactive mode, cannot cancel that interrupt in subactive mode. Thus, if a transition is made to subactive mode when an interrupt has been requested, it will not be possible to clear the CPU interrupt source. Interrupts should therefore be disabled before executing the SLEEP instruction, then entering subactive mode or watch mode. 19.12.4 Writing to MSTPCR MSTPCR should only be written to by the CPU. Rev. 2.00, 03/04, page 435 of 508 Rev. 2.00, 03/04, page 436 of 508 Section 20 List of Registers The address list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. * * * 2. * * * Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules. The access size is indicated. Register bits Bit configurations of the registers are described in the same order as the register addresses. Reserved bits are indicated by in the bit name column. No entry in the bit-name column indicates that the whole register is allocated as a counter or for holding data. 3. Register states in each operating mode * Register states are described in the same order as the register addresses. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. Rev. 2.00, 03/04, page 437 of 508 20.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Register Name Number Abbreviation of Bits Address* Module Data Bus Width Number of Access States Master control register MCR 8 H'F800 HCAN 16 4 General status register GSR 8 H'F801 HCAN 16 4 Bit configuration register BCR 16 H'F802 HCAN 16 4 Mailbox configuration register MBCR 16 H'F804 HCAN 16 4 Transmit wait register TXPR 16 H'F806 HCAN 16 4 Transmit wait cancel register TXCR 16 H'F808 HCAN 16 4 Transmit acknowledge register TXACK 16 H'F80A HCAN 16 4 Abort acknowledge register ABACK 16 H'F80C HCAN 16 4 Receive complete register RXPR 16 H'F80E HCAN 16 4 Remote request register RFPR 16 H'F810 HCAN 16 4 Interrupt register IRR 16 H'F812 HCAN 16 4 Mailbox interrupt mask register MBIMR 16 H'F814 HCAN 16 4 Interrupt mask register IMR 16 H'F816 HCAN 16 4 Receive error counter REC 8 H'F818 HCAN 16 4 Transmit error counter TEC 8 H'F819 HCAN 16 4 Unread message status register UMSR 16 H'F81A HCAN 16 4 Local acceptance filter mask L LAFML 16 H'F81C HCAN 16 4 Local acceptance filter mask H LAFMH 16 H'F81E HCAN 16 4 Message control 0[1] MC0[1] 8 H'F820 HCAN 16 4 Message control 0[2] MC0[2] 8 H'F821 HCAN 16 4 Message control 0[3] MC0[3] 8 H'F822 HCAN 16 4 Message control 0[4] MC0[4] 8 H'F823 HCAN 16 4 Message control 0[5] MC0[5] 8 H'F824 HCAN 16 4 Message control 0[6] MC0[6] 8 H'F825 HCAN 16 4 Message control 0[7] MC0[7] 8 H'F826 HCAN 16 4 Message control 0[8] MC0[8] 8 H'F827 HCAN 16 4 Rev. 2.00, 03/04, page 438 of 508 Register Name Number Abbreviation of Bits Address* Module Data Bus Width Number of Access States Message control 1[1] MC1[1] 8 H'F828 HCAN 16 4 Message control 1[2] MC1[2] 8 H'F829 HCAN 16 4 Message control 1[3] MC1[3] 8 H'F82A HCAN 16 4 Message control 1[4] MC1[4] 8 H'F82B HCAN 16 4 Message control 1[5] MC1[5] 8 H'F82C HCAN 16 4 Message control 1[6] MC1[6] 8 H'F82D HCAN 16 4 Message control 1[7] MC1[7] 8 H'F82E HCAN 16 4 Message control 1[8] MC1[8] 8 H'F82F HCAN 16 4 Message control 2[1] MC2[1] 8 H'F830 HCAN 16 4 Message control 2[2] MC2[2] 8 H'F831 HCAN 16 4 Message control 2[3] MC2[3] 8 H'F832 HCAN 16 4 Message control 2[4] MC2[4] 8 H'F833 HCAN 16 4 Message control 2[5] MC2[5] 8 H'F834 HCAN 16 4 Message control 2[6] MC2[6] 8 H'F835 HCAN 16 4 Message control 2[7] MC2[7] 8 H'F836 HCAN 16 4 Message control 2[8] MC2[8] 8 H'F837 HCAN 16 4 Message control 3[1] MC3[1] 8 H'F838 HCAN 16 4 Message control 3[2] MC3[2] 8 H'F839 HCAN 16 4 Message control 3[3] MC3[3] 8 H'F83A HCAN 16 4 Message control 3[4] MC3[4] 8 H'F83B HCAN 16 4 Message control 3[5] MC3[5] 8 H'F83C HCAN 16 4 Message control 3[6] MC3[6] 8 H'F83D HCAN 16 4 Message control 3[7] MC3[7] 8 H'F83E HCAN 16 4 Message control 3[8] MC3[8] 8 H'F83F HCAN 16 4 Message control 4[1] MC4[1] 8 H'F840 HCAN 16 4 Message control 4[2] MC4[2] 8 H'F841 HCAN 16 4 Message control 4[3] MC4[3] 8 H'F842 HCAN 16 4 Message control 4[4] MC4[4] 8 H'F843 HCAN 16 4 Message control 4[5] MC4[5] 8 H'F844 HCAN 16 4 Message control 4[6] MC4[6] 8 H'F845 HCAN 16 4 Message control 4[7] MC4[7] 8 H'F846 HCAN 16 4 Message control 4[8] MC4[8] 8 H'F847 HCAN 16 4 Rev. 2.00, 03/04, page 439 of 508 Register Name Number Abbreviation of Bits Address* Module Data Bus Width Number of Access States Message control 5[1] MC5[1] 8 H'F848 HCAN 16 4 Message control 5[2] MC5[2] 8 H'F849 HCAN 16 4 Message control 5[3] MC5[3] 8 H'F84A HCAN 16 4 Message control 5[4] MC5[4] 8 H'F84B HCAN 16 4 Message control 5[5] MC5[5] 8 H'F84C HCAN 16 4 Message control 5[6] MC5[6] 8 H'F84D HCAN 16 4 Message control 5[7] MC5[7] 8 H'F84E HCAN 16 4 Message control 5[8] MC5[8] 8 H'F84F HCAN 16 4 Message control 6[1] MC6[1] 8 H'F850 HCAN 16 4 Message control 6[2] MC6[2] 8 H'F851 HCAN 16 4 Message control 6[3] MC6[3] 8 H'F852 HCAN 16 4 Message control 6[4] MC6[4] 8 H'F853 HCAN 16 4 Message control 6[5] MC6[5] 8 H'F854 HCAN 16 4 Message control 6[6] MC6[6] 8 H'F855 HCAN 16 4 Message control 6[7] MC6[7] 8 H'F856 HCAN 16 4 Message control 6[8] MC6[8] 8 H'F857 HCAN 16 4 Message control 7[1] MC7[1] 8 H'F858 HCAN 16 4 Message control 7[2] MC7[2] 8 H'F859 HCAN 16 4 Message control 7[3] MC7[3] 8 H'F85A HCAN 16 4 Message control 7[4] MC7[4] 8 H'F85B HCAN 16 4 Message control 7[5] MC7[5] 8 H'F85C HCAN 16 4 Message control 7[6] MC7[6] 8 H'F85D HCAN 16 4 Message control 7[7] MC7[7] 8 H'F85E HCAN 16 4 Message control 7[8] MC7[8] 8 H'F85F HCAN 16 4 Message control 8[1] MC8[1] 8 H'F860 HCAN 16 4 Message control 8[2] MC8[2] 8 H'F861 HCAN 16 4 Message control 8[3] MC8[3] 8 H'F862 HCAN 16 4 Message control 8[4] MC8[4] 8 H'F863 HCAN 16 4 Message control 8[5] MC8[5] 8 H'F864 HCAN 16 4 Message control 8[6] MC8[6] 8 H'F865 HCAN 16 4 Message control 8[7] MC8[7] 8 H'F866 HCAN 16 4 Message control 8[8] MC8[8] 8 H'F867 HCAN 16 4 Rev. 2.00, 03/04, page 440 of 508 Register Name Number Abbreviation of Bits Address* Module Data Bus Width Number of Access States Message control 9[1] MC9[1] 8 H'F868 HCAN 16 4 Message control 9[2] MC9[2] 8 H'F869 HCAN 16 4 Message control 9[3] MC9[3] 8 H'F86A HCAN 16 4 Message control 9[4] MC9[4] 8 H'F86B HCAN 16 4 Message control 9[5] MC9[5] 8 H'F86C HCAN 16 4 Message control 9[6] MC9[6] 8 H'F86D HCAN 16 4 Message control 9[7] MC9[7] 8 H'F86E HCAN 16 4 Message control 9[8] MC9[8] 8 H'F86F HCAN 16 4 Message control 10[1] MC10[1] 8 H'F870 HCAN 16 4 Message control 10[2] MC10[2] 8 H'F871 HCAN 16 4 Message control 10[3] MC10[3] 8 H'F872 HCAN 16 4 Message control 10[4] MC10[4] 8 H'F873 HCAN 16 4 Message control 10[5] MC10[5] 8 H'F874 HCAN 16 4 Message control 10[6] MC10[6] 8 H'F875 HCAN 16 4 Message control 10[7] MC10[7] 8 H'F876 HCAN 16 4 Message control 10[8] MC10[8] 8 H'F877 HCAN 16 4 Message control 11[1] MC11[1] 8 H'F878 HCAN 16 4 Message control 11[2] MC11[2] 8 H'F879 HCAN 16 4 Message control 11[3] MC11[3] 8 H'F87A HCAN 16 4 Message control 11[4] MC11[4] 8 H'F87B HCAN 16 4 Message control 11[5] MC11[5] 8 H'F87C HCAN 16 4 Message control 11[6] MC11[6] 8 H'F87D HCAN 16 4 Message control 11[7] MC11[7] 8 H'F87E HCAN 16 4 Message control 11[8] MC11[8] 8 H'F87F HCAN 16 4 Message control 12[1] MC12[1] 8 H'F880 HCAN 16 4 Message control 12[2] MC12[2] 8 H'F881 HCAN 16 4 Message control 12[3] MC12[3] 8 H'F882 HCAN 16 4 Message control 12[4] MC12[4] 8 H'F883 HCAN 16 4 Message control 12[5] MC12[5] 8 H'F884 HCAN 16 4 Message control 12[6] MC12[6] 8 H'F885 HCAN 16 4 Message control 12[7] MC12[7] 8 H'F886 HCAN 16 4 Message control 12[8] MC12[8] 8 H'F887 HCAN 16 4 Rev. 2.00, 03/04, page 441 of 508 Register Name Number Abbreviation of Bits Address* Module Data Bus Width Number of Access States Message control 13[1] MC13[1] 8 H'F888 HCAN 16 4 Message control 13[2] MC13[2] 8 H'F889 HCAN 16 4 Message control 13[3] MC13[3] 8 H'F88A HCAN 16 4 Message control 13[4] MC13[4] 8 H'F88B HCAN 16 4 Message control 13[5] MC13[5] 8 H'F88C HCAN 16 4 Message control 13[6] MC13[6] 8 H'F88D HCAN 16 4 Message control 13[7] MC13[7] 8 H'F88E HCAN 16 4 Message control 13[8] MC13[8] 8 H'F88F HCAN 16 4 Message control 14[1] MC14[1] 8 H'F890 HCAN 16 4 Message control 14[2] MC14[2] 8 H'F891 HCAN 16 4 Message control 14[3] MC14[3] 8 H'F892 HCAN 16 4 Message control 14[4] MC14[4] 8 H'F893 HCAN 16 4 Message control 14[5] MC14[5] 8 H'F894 HCAN 16 4 Message control 14[6] MC14[6] 8 H'F895 HCAN 16 4 Message control 14[7] MC14[7] 8 H'F896 HCAN 16 4 Message control 14[8] MC14[8] 8 H'F897 HCAN 16 4 Message control 15[1] MC15[1] 8 H'F898 HCAN 16 4 Message control 15[2] MC15[2] 8 H'F899 HCAN 16 4 Message control 15[3] MC15[3] 8 H'F89A HCAN 16 4 Message control 15[4] MC15[4] 8 H'F89B HCAN 16 4 Message control 15[5] MC15[5] 8 H'F89C HCAN 16 4 Message control 15[6] MC15[6] 8 H'F89D HCAN 16 4 Message control 15[7] MC15[7] 8 H'F89E HCAN 16 4 Message control 15[8] MC15[8] 8 H'F89F HCAN 16 4 Message data 0[1] MD0[1] 8 H'F8B0 HCAN 16 4 Message data 0[2] MD0[2] 8 H'F8B1 HCAN 16 4 Message data 0[3] MD0[3] 8 H'F8B2 HCAN 16 4 Message data 0[4] MD0[4] 8 H'F8B3 HCAN 16 4 Message data 0[5] MD0[5] 8 H'F8B4 HCAN 16 4 Message data 0[6] MD0[6] 8 H'F8B5 HCAN 16 4 Message data 0[7] MD0[7] 8 H'F8B6 HCAN 16 4 Message data 0[8] MD0[8] 8 H'F8B7 HCAN 16 4 Rev. 2.00, 03/04, page 442 of 508 Register Name Number Abbreviation of Bits Address* Module Data Bus Width Number of Access States Message data 1[1] MD1[1] 8 H'F8B8 HCAN 16 4 Message data 1[2] MD1[2] 8 H'F8B9 HCAN 16 4 Message data 1[3] MD1[3] 8 H'F8BA HCAN 16 4 Message data 1[4] MD1[4] 8 H'F8BB HCAN 16 4 Message data 1[5] MD1[5] 8 H'F8BC HCAN 16 4 Message data 1[6] MD1[6] 8 H'F8BD HCAN 16 4 Message data 1[7] MD1[7] 8 H'F8BE HCAN 16 4 Message data 1[8] MD1[8] 8 H'F8BF HCAN 16 4 Message data 2[1] MD2[1] 8 H'F8C0 HCAN 16 4 Message data 2[2] MD2[2] 8 H'F8C1 HCAN 16 4 Message data 2[3] MD2[3] 8 H'F8C2 HCAN 16 4 Message data 2[4] MD2[4] 8 H'F8C3 HCAN 16 4 Message data 2[5] MD2[5] 8 H'F8C4 HCAN 16 4 Message data 2[6] MD2[6] 8 H'F8C5 HCAN 16 4 Message data 2[7] MD2[7] 8 H'F8C6 HCAN 16 4 Message data 2[8] MD2[8] 8 H'F8C7 HCAN 16 4 Message data 3[1] MD3[1] 8 H'F8C8 HCAN 16 4 Message data 3[2] MD3[2] 8 H'F8C9 HCAN 16 4 Message data 3[3] MD3[3] 8 H'F8CA HCAN 16 4 Message data 3[4] MD3[4] 8 H'F8CB HCAN 16 4 Message data 3[5] MD3[5] 8 H'F8CC HCAN 16 4 Message data 3[6] MD3[6] 8 H'F8CD HCAN 16 4 Message data 3[7] MD3[7] 8 H'F8CE HCAN 16 4 Message data 3[8] MD3[8] 8 H'F8CF HCAN 16 4 Message data 4[1] MD4[1] 8 H'F8D0 HCAN 16 4 Message data 4[2] MD4[2] 8 H'F8D1 HCAN 16 4 Message data 4[3] MD4[3] 8 H'F8D2 HCAN 16 4 Message data 4[4] MD4[4] 8 H'F8D3 HCAN 16 4 Message data 4[5] MD4[5] 8 H'F8D4 HCAN 16 4 Message data 4[6] MD4[6] 8 H'F8D5 HCAN 16 4 Message data 4[7] MD4[7] 8 H'F8D6 HCAN 16 4 Message data 4[8] MD4[8] 8 H'F8D7 HCAN 16 4 Rev. 2.00, 03/04, page 443 of 508 Register Name Number Abbreviation of Bits Address* Module Data Bus Width Number of Access States Message data 5[1] MD5[1] 8 H'F8D8 HCAN 16 4 Message data 5[2] MD5[2] 8 H'F8D9 HCAN 16 4 Message data 5[3] MD5[3] 8 H'F8DA HCAN 16 4 Message data 5[4] MD5[4] 8 H'F8DB HCAN 16 4 Message data 5[5] MD5[5] 8 H'F8DC HCAN 16 4 Message data 5[6] MD5[6] 8 H'F8DD HCAN 16 4 Message data 5[7] MD5[7] 8 H'F8DE HCAN 16 4 Message data 5[8] MD5[8] 8 H'F8DF HCAN 16 4 Message data 6[1] MD6[1] 8 H'F8E0 HCAN 16 4 Message data 6[2] MD6[2] 8 H'F8E1 HCAN 16 4 Message data 6[3] MD6[3] 8 H'F8E2 HCAN 16 4 Message data 6[4] MD6[4] 8 H'F8E3 HCAN 16 4 Message data 6[5] MD6[5] 8 H'F8E4 HCAN 16 4 Message data 6[6] MD6[6] 8 H'F8E5 HCAN 16 4 Message data 6[7] MD6[7] 8 H'F8E6 HCAN 16 4 Message data 6[8] MD6[8] 8 H'F8E7 HCAN 16 4 Message data 7[1] MD7[1] 8 H'F8E8 HCAN 16 4 Message data 7[2] MD7[2] 8 H'F8E9 HCAN 16 4 Message data 7[3] MD7[3] 8 H'F8EA HCAN 16 4 Message data 7[4] MD7[4] 8 H'F8EB HCAN 16 4 Message data 7[5] MD7[5] 8 H'F8EC HCAN 16 4 Message data 7[6] MD7[6] 8 H'F8ED HCAN 16 4 Message data 7[7] MD7[7] 8 H'F8EE HCAN 16 4 Message data 7[8] MD7[8] 8 H'F8EF HCAN 16 4 Message data 8[1] MD8[1] 8 H'F8F0 HCAN 16 4 Message data 8[2] MD8[2] 8 H'F8F1 HCAN 16 4 Message data 8[3] MD8[3] 8 H'F8F2 HCAN 16 4 Message data 8[4] MD8[4] 8 H'F8F3 HCAN 16 4 Message data 8[5] MD8[5] 8 H'F8F4 HCAN 16 4 Message data 8[6] MD8[6] 8 H'F8F5 HCAN 16 4 Message data 8[7] MD8[7] 8 H'F8F6 HCAN 16 4 Message data 8[8] MD8[8] 8 H'F8F7 HCAN 16 4 Rev. 2.00, 03/04, page 444 of 508 Register Name Number Abbreviation of Bits Address* Module Data Bus Width Number of Access States Message data 9[1] MD9[1] 8 H'F8F8 HCAN 16 4 Message data 9[2] MD9[2] 8 H'F8F9 HCAN 16 4 Message data 9[3] MD9[3] 8 H'F8FA HCAN 16 4 Message data 9[4] MD9[4] 8 H'F8FB HCAN 16 4 Message data 9[5] MD9[5] 8 H'F8FC HCAN 16 4 Message data 9[6] MD9[6] 8 H'F8FD HCAN 16 4 Message data 9[7] MD9[7] 8 H'F8FE HCAN 16 4 Message data 9[8] MD9[8] 8 H'F8FF HCAN 16 4 Message data 10[1] MD10[1] 8 H'F900 HCAN 16 4 Message data 10[2] MD10[2] 8 H'F901 HCAN 16 4 Message data 10[3] MD10[3] 8 H'F902 HCAN 16 4 Message data 10[4] MD10[4] 8 H'F903 HCAN 16 4 Message data 10[5] MD10[5] 8 H'F904 HCAN 16 4 Message data 10[6] MD10[6] 8 H'F905 HCAN 16 4 Message data 10[7] MD10[7] 8 H'F906 HCAN 16 4 Message data 10[8] MD10[8] 8 H'F907 HCAN 16 4 Message data 11[1] MD11[1] 8 H'F908 HCAN 16 4 Message data 11[2] MD11[2] 8 H'F909 HCAN 16 4 Message data 11[3] MD11[3] 8 H'F90A HCAN 16 4 Message data 11[4] MD11[4] 8 H'F90B HCAN 16 4 Message data 11[5] MD11[5] 8 H'F90C HCAN 16 4 Message data 11[6] MD11[6] 8 H'F90D HCAN 16 4 Message data 11[7] MD11[7] 8 H'F90E HCAN 16 4 Message data 11[8] MD11[8] 8 H'F90F HCAN 16 4 Message data 12[1] MD12[1] 8 H'F910 HCAN 16 4 Message data 12[2] MD12[2] 8 H'F911 HCAN 16 4 Message data 12[3] MD12[3] 8 H'F912 HCAN 16 4 Message data 12[4] MD12[4] 8 H'F913 HCAN 16 4 Message data 12[5] MD12[5] 8 H'F914 HCAN 16 4 Message data 12[6] MD12[6] 8 H'F915 HCAN 16 4 Message data 12[7] MD12[7] 8 H'F916 HCAN 16 4 Message data 12[8] MD12[8] 8 H'F917 HCAN 16 4 Rev. 2.00, 03/04, page 445 of 508 Register Name Number Abbreviation of Bits Address* Module Data Bus Width Number of Access States Message data 13[1] MD13[1] 8 H'F918 HCAN 16 4 Message data 13[2] MD13[2] 8 H'F919 HCAN 16 4 Message data 13[3] MD13[3] 8 H'F91A HCAN 16 4 Message data 13[4] MD13[4] 8 H'F91B HCAN 16 4 Message data 13[5] MD13[5] 8 H'F91C HCAN 16 4 Message data 13[6] MD13[6] 8 H'F91D HCAN 16 4 Message data 13[7] MD13[7] 8 H'F91E HCAN 16 4 Message data 13[8] MD13[8] 8 H'F91F HCAN 16 4 Message data 14[1] MD14[1] 8 H'F920 HCAN 16 4 Message data 14[2] MD14[2] 8 H'F921 HCAN 16 4 Message data 14[3] MD14[3] 8 H'F922 HCAN 16 4 Message data 14[4] MD14[4] 8 H'F923 HCAN 16 4 Message data 14[5] MD14[5] 8 H'F924 HCAN 16 4 Message data 14[6] MD14[6] 8 H'F925 HCAN 16 4 Message data 14[7] MD14[7] 8 H'F926 HCAN 16 4 Message data 14[8] MD14[8] 8 H'F927 HCAN 16 4 Message data 15[1] MD15[1] 8 H'F928 HCAN 16 4 Message data 15[2] MD15[2] 8 H'F929 HCAN 16 4 Message data 15[3] MD15[3] 8 H'F92A HCAN 16 4 Message data 15[4] MD15[4] 8 H'F92B HCAN 16 4 Message data 15[5] MD15[5] 8 H'F92C HCAN 16 4 Message data 15[6] MD15[6] 8 H'F92D HCAN 16 4 Message data 15[7] MD15[7] 8 H'F92E HCAN 16 4 Message data 15[8] MD15[8] 8 H'F92F HCAN 16 4 PWM control register_1 PWCR_1 8 H'FC00 PWM_1 16 4 PWM output control register_1 PWOCR_1 8 H'FC02 PWM_1 16 4 PWM polarity register_1 PWPR_1 8 H'FC04 PWM_1 16 4 PWM cycle register_1 PWCYR_1 16 H'FC06 PWM_1 16 4 PWM buffer register_1A PWBFR_1A 16 H'FC08 PWM_1 16 4 PWM buffer register_1C PWBFR_1C 16 H'FC0A PWM_1 16 4 PWM buffer register_1E PWBFR_1E 16 H'FC0C PWM_1 16 4 PWM buffer register_1G PWBFR_1G 16 H'FC0E PWM_1 16 4 Rev. 2.00, 03/04, page 446 of 508 Register Name Number Abbreviation of Bits Address* Module Data Bus Width Number of Access States PWM control register_2 PWCR_2 8 H'FC10 PWM_2 16 4 PWM output control register_2 PWOCR_2 8 H'FC12 PWM_2 16 4 PWM polarity register_2 PWPR_2 8 H'FC14 PWM_2 16 4 PWM cycle register_2 PWCYR_2 16 H'FC16 PWM_2 16 4 PWM buffer register_2A PWBFR_2A 16 H'FC18 PWM_2 16 4 PWM buffer register_2B PWBFR_2B 16 H'FC1A PWM_2 16 4 PWM buffer register_2C PWBFR_2C 16 H'FC1C PWM_2 16 4 PWM buffer register_2D PWBFR_2D 16 H'FC1E PWM_2 16 4 Port H data direction register PHDDR 8 H'FC20 PORT 16 4 Port J data direction register PJDDR 8 H'FC21 PORT 16 4 Port H data register PHDR 8 H'FC24 PORT 16 4 Port J data register PJDR 8 H'FC25 PORT 16 4 Port H register PORTH 8 H'FC28 PORT 16 4 Port J register PORTJ 8 H'FC29 PORT 16 4 Transport register TRPRT 8 H'FC2E PORT 8 4 LCD port control register LPCR 8 H'FC30 LCD 16 4 LCD control register LCR 8 H'FC31 LCD 16 4 LCD control register 2 LCR2 8 H'FC32 LCD 16 4 Module stop control register D MSTPCRD 8 H'FC60 SYSTEM 8 4 Standby control register SBYCR 8 H'FDE4 SYSTEM 8 2 System control register SYSCR 8 H'FDE5 SYSTEM 8 2 System clock control register SCKCR 8 H'FDE6 SYSTEM 8 2 Mode control register MDCR 8 H'FDE7 SYSTEM 8 2 Module stop control register A MSTPCRA 8 H'FDE8 SYSTEM 8 2 Module stop control register B MSTPCRB 8 H'FDE9 SYSTEM 8 2 Module stop control register C MSTPCRC 8 H'FDEA SYSTEM 8 2 Low-power control register LPWRCR 8 H'FDEC SYSTEM 8 2 IRQ sense control register H ISCRH 8 H'FE12 INT 8 2 IRQ sense control register L ISCRL 8 H'FE13 INT 8 2 IRQ enable register IER 8 H'FE14 INT 8 2 IRQ status register ISR 8 H'FE15 INT 8 2 Rev. 2.00, 03/04, page 447 of 508 Register Name Number Abbreviation of Bits Address* Module Data Bus Width Number of Access States Port 1 data direction register P1DDR 8 H'FE30 PORT 8 2 Port 3 data direction register P3DDR 8 H'FE32 PORT 8 2 Port A data direction register PADDR 8 H'FE39 PORT 8 2 Port B data direction register PBDDR 8 H'FE3A PORT 8 2 Port C data direction register PCDDR 8 H'FE3B PORT 8 2 Port D data direction register PDDDR 8 H'FE3C PORT 8 2 Port F data direction register PFDDR 8 H'FE3E PORT 8 2 Port 3 open drain control register P3ODR 8 H'FE46 PORT 8 2 Port A open drain control register PAODR 8 H'FE47 PORT 8 2 Port B open drain control register PBODR 8 H'FE48 PORT 8 2 Port C open drain control register PCODR 8 H'FE49 PORT 8 2 Timer start register TSTR 8 H'FEB0 TPU 16 2 Timer synchro register TSYR 8 H'FEB1 TPU 16 2 Interrupt priority register A IPRA 8 H'FEC0 INT 8 2 Interrupt priority register B IPRB 8 H'FEC1 INT 8 2 Interrupt priority register C IPRC 8 H'FEC2 INT 8 2 Interrupt priority register D IPRD 8 H'FEC3 INT 8 2 Interrupt priority register E IPRE 8 H'FEC4 INT 8 2 Interrupt priority register F IPRF 8 H'FEC5 INT 8 2 Interrupt priority register G IPRG 8 H'FEC6 INT 8 2 Interrupt priority register J IPRJ 8 H'FEC9 INT 8 2 Interrupt priority register K IPRK 8 H'FECA INT 8 2 Interrupt priority register M IPRM 8 H'FECC INT 8 2 RAM emulation register RAMER 8 H'FEDB FLASH (F-ZTAT version) 8 2 Port 1 data register P1DR 8 H'FF00 PORT 8 2 Port 3 data register P3DR 8 H'FF02 PORT 8 2 Port A data register PADR 8 H'FF09 PORT 8 2 Rev. 2.00, 03/04, page 448 of 508 Register Name Number Abbreviation of Bits Address* Module Data Bus Width Number of Access States Port B data register PBDR 8 H'FF0A PORT 8 2 Port C data register PCDR 8 H'FF0B PORT 8 2 Port D data register PDDR 8 H'FF0C PORT 8 2 Port F data register PFDR 8 H'FF0E PORT 8 2 Timer control register_0 TCR_0 8 H'FF10 TPU_0 16 2 Timer mode register_0 TMDR_0 8 H'FF11 TPU_0 16 2 Timer I/O control register H_0 TIORH_0 8 H'FF12 TPU_0 16 2 Timer I/O control register L_0 TIORL_0 8 H'FF13 TPU_0 16 2 Timer interrupt enable register_0 TIER_0 8 H'FF14 TPU_0 16 2 Timer status register_0 TSR_0 8 H'FF15 TPU_0 16 2 Timer counter H_0 TCNTH_0 8 H'FF16 TPU_0 16 2 Timer counter L_0 TCNTL_0 8 H'FF17 TPU_0 16 2 Timer general register AH_0 TGRAH_0 8 H'FF18 TPU_0 16 2 Timer general register AL_0 TGRAL_0 8 H'FF19 TPU_0 16 2 Timer general register BH_0 TGRBH_0 8 H'FF1A TPU_0 16 2 Timer general register BL_0 TGRBL_0 8 H'FF1B TPU_0 16 2 Timer general register CH_0 TGRCH_0 8 H'FF1C TPU_0 16 2 Timer general register CL_0 TGRCL_0 8 H'FF1D TPU_0 16 2 Timer general register DH_0 TGRDH_0 8 H'FF1E TPU_0 16 2 Timer general register DL_0 TGRDL_0 8 H'FF1F TPU_0 16 2 Timer control register_1 TCR_1 8 H'FF20 TPU_1 16 2 Timer mode register_1 TMDR_1 8 H'FF21 TPU_1 16 2 Timer I/O control register_1 TIOR_1 8 H'FF22 TPU_1 16 2 Timer interrupt enable register_1 TIER_1 8 H'FF24 TPU_1 16 2 Timer status register_1 TSR_1 8 H'FF25 TPU_1 16 2 Timer counter H_1 TCNTH_1 8 H'FF26 TPU_1 16 2 Timer counter L_1 TCNTL_1 8 H'FF27 TPU_1 16 2 Timer general register AH_1 TGRAH_1 8 H'FF28 TPU_1 16 2 Timer general register AL_1 TGRAL_1 8 H'FF29 TPU_1 16 2 Timer general register BH_1 TGRBH_1 8 H'FF2A TPU_1 16 2 Timer general register BL_1 TGRBL_1 8 H'FF2B TPU_1 16 2 Timer control register_2 TCR_2 8 H'FF30 TPU_2 16 2 Timer mode register_2 TMDR_2 8 H'FF31 TPU_2 16 2 Rev. 2.00, 03/04, page 449 of 508 Register Name Number Abbreviation of Bits Address* Module Data Bus Width Number of Access States Timer I/O control register_2 TIOR_2 8 H'FF32 TPU_2 16 2 Timer interrupt enable register_2 TIER_2 8 H'FF34 TPU_2 16 2 Timer status register_2 TSR_2 8 H'FF35 TPU_2 16 2 Timer counterH_2 TCNTH_2 8 H'FF36 TPU_2 16 2 Timer counter L_2 TCNTL_2 8 H'FF37 TPU_2 16 2 Timer general register AH_2 TGRAH_2 8 H'FF38 TPU_2 16 2 Timer general register AL_2 TGRAL_2 8 H'FF39 TPU_2 16 2 Timer general register BH_2 TGRBH_2 8 H'FF3A TPU_2 16 2 Timer general register BL_2 TGRBL_2 8 H'FF3B TPU_2 16 2 Timer control/status register_0 TCSR_0 8 H'FF74 WDT_0 16 2 Timer counter_0 TCNT_0 8 H'FF75 WDT_0 16 2 Reset control/status register RSTCSR 8 H'FF77 WDT_0 16 2 Serial mode register_0 SMR_0 8 H'FF78 SCI_0 8 2 Bit rate register_0 BRR_0 8 H'FF79 SCI_0 8 2 Serial control register_0 SCR_0 8 H'FF7A SCI_0 8 2 Transmit data register_0 TDR_0 8 H'FF7B SCI_0 8 2 Serial status register_0 SSR_0 8 H'FF7C SCI_0 8 2 Receive data register_0 RDR_0 8 H'FF7D SCI_0 8 2 Smart card mode register_0 SCMR_0 8 H'FF7E SCI_0 8 2 Serial mode register_1 SMR_1 8 H'FF80 SCI_1 8 2 Bit rate register_1 BRR_1 8 H'FF81 SCI_1 8 2 Serial control register_1 SCR_1 8 H'FF82 SCI_1 8 2 Transmit data register_1 TDR_1 8 H'FF83 SCI_1 8 2 Serial status register_1 SSR_1 8 H'FF84 SCI_1 8 2 Receive data register_1 RDR_1 8 H'FF85 SCI_1 8 2 Smart card mode register_1 SCMR_1 8 H'FF86 SCI_1 8 2 A/D data register AH ADDRAH 8 H'FF90 A/D 8 2 A/D data register AL ADDRAL 8 H'FF91 A/D 8 2 A/D data register BH ADDRBH 8 H'FF92 A/D 8 2 A/D data register BL ADDRBL 8 H'FF93 A/D 8 2 A/D data register CH ADDRCH 8 H'FF94 A/D 8 2 A/D data register CL ADDRCL 8 H'FF95 A/D 8 2 Rev. 2.00, 03/04, page 450 of 508 Register Name Number Abbreviation of Bits Address* Module Data Bus Width Number of Access States A/D data register DH ADDRDH 8 H'FF96 A/D 8 2 A/D data register DL ADDRDL 8 H'FF97 A/D 8 2 A/D control/status register ADCSR 8 H'FF98 A/D 8 2 A/D control register ADCR 8 H'FF99 A/D 8 2 Timer control/status register_1 TCSR_1 8 H'FFA2 WDT_1 16 2 Timer counter_1 TCNT_1 8 H'FFA3 WDT_1 16 2 Flash memory control register 1 FLMCR1 8 H'FFA8 FLASH (F-ZTAT version) 8 2 Flash memory control register 2 FLMCR2 8 H'FFA9 FLASH (F-ZTAT version) 8 2 Erase block register 1 EBR1 8 H'FFAA FLASH (F-ZTAT version) 8 2 Erase block register 2 EBR2 8 H'FFAB FLASH (F-ZTAT version) 8 2 Flash memory power control register FLPWCR 8 H'FFAC FLASH (F-ZTAT version) 8 2 Port 1 register PORT1 8 H'FFB0 PORT 8 2 Port 3 register PORT3 8 H'FFB2 PORT 8 2 Port 4 register PORT4 8 H'FFB3 PORT 8 2 Port A register PORTA 8 H'FFB9 PORT 8 2 Port B register PORTB 8 H'FFBA PORT 8 2 Port C register PORTC 8 H'FFBB PORT 8 2 Port D register PORTD 8 H'FFBC PORT 8 2 Port F register PORTF 8 H'FFBE PORT 8 2 Note: Lower 16 bits of the address. Rev. 2.00, 03/04, page 451 of 508 20.2 Register Bits Register bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines. Register Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MCR MCR7 MCR5 MCR2 MCR1 MCR0 HCAN GSR GSR3 GSR2 GSR1 GSR0 BCR BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0 MBCR TXPR TXCR TXACK ABACK RXPR RFPR IRR BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8 MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8 TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8 TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8 TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0 RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8 RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0 RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 IRR12 IRR9 IRR8 MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 IMR12 IMR9 IMR8 REC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TEC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 UMSR UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 MBIMR IMR Rev. 2.00, 03/04, page 452 of 508 Register Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module LAFML LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0 HCAN LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8 LAFMH7 LAFMH6 LAFMH5 LAFMH1 LAFMH0 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8 MC0[1] DLC3 DLC2 DLC1 DLC0 MC0[2] MC0[3] MC0[4] MC0[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC0[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC0[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC0[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC1[1] DLC3 DLC2 DLC1 DLC0 MC1[2] MC1[3] MC1[4] MC1[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC1[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC1[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC1[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC2[1] DLC3 DLC2 DLC1 DLC0 MC2[2] MC2[3] MC2[4] MC2[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC2[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC2[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC2[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC3[1] DLC3 DLC2 DLC1 DLC0 MC3[2] MC3[3] MC3[4] MC3[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 LAFMH Rev. 2.00, 03/04, page 453 of 508 Register Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MC3[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 HCAN MC3[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC3[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC4[1] DLC3 DLC2 DLC1 DLC0 MC4[2] MC4[3] MC4[4] MC4[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC4[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC4[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC4[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC5[1] DLC3 DLC2 DLC1 DLC0 MC5[2] MC5[3] MC5[4] MC5[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC5[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC5[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC5[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC6[1] DLC3 DLC2 DLC1 DLC0 MC6[2] MC6[3] MC6[4] MC6[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC6[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC6[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC6[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC7[1] DLC3 DLC2 DLC1 DLC0 MC7[2] MC7[3] MC7[4] MC7[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC7[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 Rev. 2.00, 03/04, page 454 of 508 Register Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MC7[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 HCAN MC7[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC8[1] DLC3 DLC2 DLC1 DLC0 MC8[2] MC8[3] MC8[4] MC8[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC8[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC8[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC8[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC9[1] DLC3 DLC2 DLC1 DLC0 MC9[2] MC9[3] MC9[4] MC9[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC9[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC9[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC9[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC10[1] DLC3 DLC2 DLC1 DLC0 MC10[2] MC10[3] MC10[4] MC10[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC10[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC10[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC10[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC11[1] DLC3 DLC2 DLC1 DLC0 MC11[2] MC11[3] MC11[4] MC11[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC11[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC11[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 Rev. 2.00, 03/04, page 455 of 508 Register Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MC11[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 HCAN MC12[1] DLC3 DLC2 DLC1 DLC0 MC12[2] MC12[3] MC12[4] MC12[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC12[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC12[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC12[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC13[1] DLC3 DLC2 DLC1 DLC0 MC13[2] MC13[3] MC13[4] MC13[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC13[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC13[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC13[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC14[1] DLC3 DLC2 DLC1 DLC0 MC14[2] MC14[3] MC14[4] MC14[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC14[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC14[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC14[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC15[1] DLC3 DLC2 DLC1 DLC0 MC15[2] MC15[3] MC15[4] MC15[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC15[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC15[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC15[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 Rev. 2.00, 03/04, page 456 of 508 Register Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MD0[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 HCAN MD0[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD0[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD0[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD0[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD0[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD0[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD0[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD1[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD1[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD1[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD1[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD1[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD1[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD1[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD1[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD2[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD2[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD2[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD2[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD2[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD2[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD2[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD2[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD3[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD3[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD3[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD3[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD3[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD3[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD3[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD3[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Rev. 2.00, 03/04, page 457 of 508 Register Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MD4[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 HCAN MD4[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD4[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD4[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD4[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD4[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD4[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD4[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD5[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD5[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD5[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD5[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD5[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD5[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD5[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD5[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD6[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD6[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD6[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD6[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD6[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD6[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD6[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD6[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD7[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD7[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD7[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD7[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD7[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD7[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD7[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD7[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Rev. 2.00, 03/04, page 458 of 508 Register Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MD8[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 HCAN MD8[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD8[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD8[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD8[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD8[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD8[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD8[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD9[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD9[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD9[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD9[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD9[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD9[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD9[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD9[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD10[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD10[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD10[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD10[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD10[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD10[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD10[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD10[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD11[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD11[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD11[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD11[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD11[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD11[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD11[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD11[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Rev. 2.00, 03/04, page 459 of 508 Register Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MD12[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 HCAN MD12[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD12[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD12[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD12[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD12[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD12[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD12[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD13[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD13[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD13[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD13[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD13[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD13[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD13[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD13[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD14[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD14[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD14[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD14[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD14[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD14[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD14[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD14[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD15[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD15[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD15[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD15[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD15[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD15[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD15[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MD15[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Rev. 2.00, 03/04, page 460 of 508 Register Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PWCR_1 IE CMF CST CKS2 CKS1 CKS0 PWM_1 PWOCR_1 OE1H OE1G OE1F OE1E OE1D OE1C OE1B OE1A PWPR1_ OPS1G OPS1F OPS1E OPS1D OPS1C OPS1B OPS1A Bit 9 Bit 8 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OTS DT9 DT8 DT6 DT5 DT4 DT3 DT2 DT1 DT0 OTS DT9 DT8 DT6 DT5 DT4 DT3 DT2 DT1 DT0 OTS DT9 DT8 DT6 DT5 DT4 DT3 DT2 DT1 DT0 OTS DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 IE CMF CST CKS2 CKS1 CKS0 PWOCR_2 OE2H OE2G OE2F OE2E OE2D OE2C OE2B OE2A PWPR_2 OPS2H OPS2G OPS2F OPS2E OPS2D OPS2C OPS2B OPS2A PWCYR2 Bit 9 Bit 8 OPS1H PWCYR_1 Bit 7 PWBFR_1A DT7 PWBFR_1C DT7 PWBFR_1E DT7 PWBFR_1G PWCR_2 Bit 7 PWBFR_2A DT7 PWBFR_2B DT7 PWBFR_2C DT7 PWBFR_2D Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDS DT9 DT8 DT6 DT5 DT4 DT3 DT2 DT1 DT0 TDS DT9 DT8 DT6 DT5 DT4 DT3 DT2 DT1 DT0 TDS DT9 DT8 DT6 DT5 DT4 DT3 DT2 DT1 DT0 TDS DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 PHDDR PH7DDR PH6DDR PH5DDR PH4DDR PH3DDR PH2DDR PH1DDR PH0DDR PJDDR PJ7DDR PJ6DDR PJ5DDR PJ4DDR PJ3DDR PJ2DDR PJ1DDR PJ0DDR PHDR PH7DR PH6DR PH5DR PH4DR PH3DR PH2DR PH1DR PH0DR PJDR PJ7DR PJ6DR PJ5DR PJ4DR PJ3DR PJ2DR PJ1DR PJ0DR PORTH PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PORTJ PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 TRPRT TRPB TRPA PWM_2 PORT Rev. 2.00, 03/04, page 461 of 508 Register Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module LPCR DTS1 DTS0 CMX SGS3 SGS2 SGS1 SGS0 LCD LCR PSW ACT DISP CKS3 CKS2 CKS1 CKS0 LCR2 LCDAB MSTPCRD MSTPD7 MSTPD6 SBYCR SSBY STS2 STS1 STS0 SYSCR INTM1 INTM0 NMIEG RAME SCKCR PSTOP STCS SCK2 SCK1 SCK0 MDCR MDS2 MDS0 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 MSTPCRA MSTPA7 MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 MSTPCRC MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 LPWRCR DTON LSON SUBSTP RFCUT STC1 STC0 ISCRH IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA IER IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E ISR IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR P3DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR PCDDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR PDDDR PD7DDR PD6DDR PD5DDR PD4DDR PFDDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR P3ODR P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR PAODR PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR PBODR PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR PCODR PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR TSTR CST2 CST1 CST0 TSYR SYNC2 SYNC1 SYNC0 Rev. 2.00, 03/04, page 462 of 508 SYSTEM INT PORT TPU common Register Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module IPRA IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 INT IPRB IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 IPRC IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 IPRD IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 IPRE IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 IPRF IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 IPRG IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 IPRJ IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 IPRK IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 IPRM IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 RAMER RAMS RAM2 RAM1 RAM0 FLASH (F-ZTAT version) P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR P3DR P35DR P34DR P33DR P32DR P31DR P30DR PADR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR PBDR PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR PCDR PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR PDDR PD7DR PD6DR PD5DR PD4DR PFDR PF6DR PF5DR PF4DR PF3DR PF2DR TCR_0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_0 BFB BFA MD3 MD2 MD1 MD0 TIORH_0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_0 TTGE TCIEV TGIED TGIEC TGIEB TGIEA TSR_0 TCFV TGFD TGFC TGFB TGFA TCNTH_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TCNTL_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TGRAH_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRAL_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TGRBH_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRBL_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TGRCH_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRCL_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PORT TPU_0 Rev. 2.00, 03/04, page 463 of 508 Register Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TGRDH_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TPU_0 TGRDL_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCR_1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_1 MD3 MD2 MD1 MD0 TIOR_1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_1 TTGE TCIEU TCIEV TGIEB TGIEA TSR_1 TCFD TCFU TCFV TGFB TGFA TCNTH_1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TCNTL_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TGRAH_1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRAL_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TGRBH_1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRBL_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCR_2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_2 MD3 MD2 MD1 MD0 TIOR_2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_2 TTGE TCIEU TCIEV TGIEB TGIEA TSR_2 TCFD TCFU TCFV TGFB TGFA TCNTH_2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TCNTL_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TGRAH_2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRAL_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TGRBH_2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRBL_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCSR_0 OVF WT/IT TME CKS2 CKS1 CKS0 TCNT_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RSTCSR WOVF RSTE RSTS SMR_0*3 C/A CHR PE O/E STOP MP CKS1 CKS0 (GM) (BLK) (PE) (O/E) (BCP1) (BCP0) (CKS1) (CKS0) BRR_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCR_0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDR_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Rev. 2.00, 03/04, page 464 of 508 TPU_1 TPU_2 WDT_0 SCI_0 Register Abbrev. Bit 7 3 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SCI_0 TDRE RDRF ORER FER PER TEND MPB MPBT (TDRE) (RDRF) (ORER) (ERS) (PER) (TEND) (MPB) (MPBT) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SDIR SINV SMIF C/A CHR PE O/E STOP MP CKS1 CKS0 (GM) (BLK) (PE) (O/E) (BCP1) (BCP0) (CKS1) (CKS0) BRR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCR_1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TDRE RDRF ORER FER PER TEND MPB MPBT (TDRE) (RDRF) (ORER) (ERS) (PER) (TEND) (MPB) (MPBT) RDR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCMR_1 SDIR SINV SMIF ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRAL AD1 AD0 ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRBL AD1 AD0 ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRCL AD1 AD0 ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRDL AD1 AD0 ADCSR ADF ADIE ADST SCAN CH2 CH1 CH0 SSR_0* RDR_0 SCMR_0 3 SMR_1* 3 SSR_1* SCI_1 A/D ADCR TRGS1 TRGS0 CKS1 CKS0 TCSR_1 OVF WT/IT TME PSS RST/ NMI CKS2 CKS1 CKS0 TCNT_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 FLMCR1 FWE SWE ESU PSU EV PV E P FLASH FLMCR2 FLER (F-ZTAT EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 EBR2 EB9 EB8 FLPWCR PDWND WDT_1 version) Rev. 2.00, 03/04, page 465 of 508 Register Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PORT1 P17 P16 P15 P14 P13 P12 P11 P10 PORT PORT3 P35 P34 P33 P32 P31 P30 PORT4 P47 P46 P45 P44 P43 P42 P41 P40 PORTA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PORTB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PORTD PD7 PD6 PD5 PD4 PORTF PF7 PF6 PF5 PF4 PF3 PF2 Notes: 1. For buffer operation. 2. For free operation. 3. Some bit functions differ in normal serial communication interface mode and Smart Card interface mode. The bit functions in Smart Card interface mode are enclosed in parentheses. Rev. 2.00, 03/04, page 466 of 508 20.3 Register States in Each Operating Mode Register High- Medium Module Abbrev. Reset Speed -Speed Sleep Stop Watch Subactive Subsleep Standby Software Hardware Standby Module MCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized HCAN GSR Initialized Initialized Initialized Initialized Initialized Initialized Initialized BCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized MBCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized TXPR Initialized Initialized Initialized Initialized Initialized Initialized Initialized TXCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized TXACK Initialized Initialized Initialized Initialized Initialized Initialized Initialized ABACK Initialized Initialized Initialized Initialized Initialized Initialized Initialized RXPR Initialized Initialized Initialized Initialized Initialized Initialized Initialized RFPR Initialized Initialized Initialized Initialized Initialized Initialized Initialized IRR Initialized Initialized Initialized Initialized Initialized Initialized Initialized MBIMR Initialized Initialized Initialized Initialized Initialized Initialized Initialized IMR Initialized Initialized Initialized Initialized Initialized Initialized Initialized REC Initialized Initialized Initialized Initialized Initialized Initialized Initialized TEC Initialized Initialized Initialized Initialized Initialized Initialized Initialized UMSR Initialized Initialized Initialized Initialized Initialized Initialized Initialized LAFML Initialized Initialized Initialized Initialized Initialized Initialized Initialized LAFMH Initialized Initialized Initialized Initialized Initialized Initialized Initialized MC0[1] MC0[2] MC0[3] MC0[4] MC0[5] MC0[6] MC0[7] MC0[8] MC1[1] MC1[2] MC1[3] MC1[4] MC1[5] MC1[6] Rev. 2.00, 03/04, page 467 of 508 Register High- Medium Module Abbrev. Reset Speed -Speed Sleep Stop Watch Subactive Subsleep Standby Standby Module MC1[7] HCAN MC1[8] MC2[1] MC2[2] MC2[3] MC2[4] MC2[5] MC2[6] MC2[7] MC2[8] MC3[1] MC3[2] MC3[3] MC3[4] MC3[5] MC3[6] MC3[7] MC3[8] MC4[1] MC4[2] MC4[3] MC4[4] MC4[5] MC4[6] MC4[7] MC4[8] MC5[1] MC5[2] MC5[3] MC5[4] MC5[5] MC5[6] MC5[7] MC5[8] Rev. 2.00, 03/04, page 468 of 508 Software Hardware Register High- Medium Module Abbrev. Reset Speed -Speed Sleep Stop Watch Subactive Subsleep Standby Software Hardware Standby Module MC6[1] HCAN MC6[2] MC6[3] MC6[4] MC6[5] MC6[6] MC6[7] MC6[8] MC7[1] MC7[2] MC7[3] MC7[4] MC7[5] MC7[6] MC7[7] MC7[8] MC8[1] MC8[2] MC8[3] MC8[4] MC8[5] MC8[6] MC8[7] MC8[8] MC9[1] MC9[2] MC9[3] MC9[4] MC9[5] MC9[6] MC9[7] MC9[8] MC10[1] Rev. 2.00, 03/04, page 469 of 508 Register High- Medium Module Abbrev. Reset Speed -Speed Sleep Stop Watch Subactive Subsleep Standby Standby Module MC10[2] HCAN MC10[3] MC10[4] MC10[5] MC10[6] MC10[7] MC10[8] MC11[1] MC11[2] MC11[3] MC11[4] MC11[5] MC11[6] MC11[7] MC11[8] MC12[1] MC12[2] MC12[3] MC12[4] MC12[5] MC12[6] MC12[7] MC12[8] MC13[1] MC13[2] MC13[3] MC13[4] MC13[5] MC13[6] MC13[7] MC13[8] MC14[1] MC14[2] Rev. 2.00, 03/04, page 470 of 508 Software Hardware Register High- Medium Module Abbrev. Reset Speed -Speed Sleep Stop Watch Subactive Subsleep Standby Software Hardware Standby Module MC14[3] HCAN MC14[4] MC14[5] MC14[6] MC14[7] MC14[8] MC15[1] MC15[2] MC15[3] MC15[4] MC15[5] MC15[6] MC15[7] MC15[8] MD0[1] MD0[2] MD0[3] MD0[4] MD0[5] MD0[6] MD0[7] MD0[8] MD1[1] MD1[2] MD1[3] MD1[4] MD1[5] MD1[6] MD1[7] MD1[8] MD2[1] MD2[2] MD2[3] Rev. 2.00, 03/04, page 471 of 508 Register High- Medium Module Abbrev. Reset Speed -Speed Sleep Stop Watch Subactive Subsleep Standby Standby Module MD2[4] HCAN MD2[5] MD2[6] MD2[7] MD2[8] MD3[1] MD3[2] MD3[3] MD3[4] MD3[5] MD3[6] MD3[7] MD3[8] MD4[1] MD4[2] MD4[3] MD4[4] MD4[5] MD4[6] MD4[7] MD4[8] MD5[1] MD5[2] MD5[3] MD5[4] MD5[5] MD5[6] MD5[7] MD5[8] MD6[1] MD6[2] MD6[3] MD6[4] Rev. 2.00, 03/04, page 472 of 508 Software Hardware Register High- Medium Module Abbrev. Reset Speed -Speed Sleep Stop Watch Subactive Subsleep Standby Software Hardware Standby Module MD6[5] HCAN MD6[6] MD6[7] MD6[8] MD7[1] MD7[2] MD7[3] MD7[4] MD7[5] MD7[6] MD7[7] MD7[8] MD8[1] MD8[2] MD8[3] MD8[4] MD8[5] MD8[6] MD8[7] MD8[8] MD9[1] MD9[2] MD9[3] MD9[4] MD9[5] MD9[6] MD9[7] MD9[8] MD10[1] MD10[2] MD10[3] MD10[4] MD10[5] Rev. 2.00, 03/04, page 473 of 508 Register High- Medium Module Abbrev. Reset Speed -Speed Sleep Stop Watch Subactive Subsleep Standby Standby Module MD10[6] HCAN MD10[7] MD10[8] MD11[1] MD11[2] MD11[3] MD11[4] MD11[5] MD11[6] MD11[7] MD11[8] MD12[1] MD12[2] MD12[3] MD12[4] MD12[5] MD12[6] MD12[7] MD12[8] MD13[1] MD13[2] MD13[3] MD13[4] MD13[5] MD13[6] MD13[7] MD13[8] MD14[1] MD14[2] MD14[3] MD14[4] MD14[5] MD14[6] Rev. 2.00, 03/04, page 474 of 508 Software Hardware Register High- Medium Module Abbrev. Reset Speed -Speed Sleep Stop Watch Subactive Subsleep Standby Software Hardware Standby Module MD14[7] HCAN MD14[8] MD15[1] MD15[2] MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8] PWCR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWOCR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWPR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWCYR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWBFR_1A Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWBFR_1C Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWBFR_1E Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWBFR_1G Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWCR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWOCR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWPR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWCYR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWBFR_2A Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWBFR_2B Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWBFR_2C Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWBFR_2D Initialized Initialized Initialized Initialized Initialized Initialized Initialized PHDDR Initialized Initialized PJDDR Initialized Initialized PHDR Initialized Initialized PJDR Initialized Initialized PORTH Initialized Initialized PORTJ Initialized Initialized TRPRT Initialized Initialized PWM_1 PWM_2 PORT Rev. 2.00, 03/04, page 475 of 508 Register High- Medium Module Abbrev. Reset Speed -Speed Sleep Stop Watch Subactive Subsleep Standby Standby Module LPCR Initialized Initialized LCD LCR Initialized Initialized LCR2 Initialized Initialized MSTPCRD Initialized Initialized SBYCR Initialized Initialized SYSCR Initialized Initialized SCKCR Initialized Initialized MDCR Initialized Initialized MSTPCRA Initialized Initialized MSTPCRB Initialized Initialized MSTPCRC Initialized Initialized LPWRCR Initialized Initialized ISCRH Initialized Initialized ISCRL Initialized Initialized IER Initialized Initialized ISR Initialized Initialized P1DDR Initialized Initialized P3DDR Initialized Initialized PADDR Initialized Initialized PBDDR Initialized Initialized PCDDR Initialized Initialized PDDDR Initialized Initialized PFDDR Initialized Initialized P3ODR Initialized Initialized PAODR Initialized Initialized PBODR Initialized Initialized PCODR Initialized Initialized TSTR Initialized Initialized TSYR Initialized Initialized IPRA Initialized Initialized IPRB Initialized Initialized IPRC Initialized Initialized IPRD Initialized Initialized Rev. 2.00, 03/04, page 476 of 508 Software Hardware SYSTEM INT PORT TPU INT Register High- Medium Module Abbrev. Reset Speed -Speed Sleep Stop Watch Subactive Subsleep Standby Software Hardware Standby Module IPRE Initialized Initialized INT IPRF Initialized Initialized IPRG Initialized Initialized IPRJ Initialized Initialized IPRK Initialized Initialized IPRM Initialized Initialized RAMER Initialized Initialized FLASH (F-ZTAT version) P1DR Initialized Initialized P3DR Initialized Initialized PADR Initialized Initialized PBDR Initialized Initialized PCDR Initialized Initialized PDDR Initialized Initialized PFDR Initialized Initialized TCR_0 Initialized Initialized TMDR_0 Initialized Initialized TIORH_0 Initialized Initialized TIORL_0 Initialized Initialized TIER_0 Initialized Initialized TSR_0 Initialized Initialized TCNTH_0 Initialized Initialized TCNTL_0 Initialized Initialized TGRAH_0 Initialized Initialized TGRAL_0 Initialized Initialized TGRBH_0 Initialized Initialized TGRBL_0 Initialized Initialized TGRCH_0 Initialized Initialized TGRCL_0 Initialized Initialized TGRDH_0 Initialized Initialized TGRDL_0 Initialized Initialized PORT TPU_0 Rev. 2.00, 03/04, page 477 of 508 Register High- Medium Module Abbrev. Reset Speed -Speed Sleep Stop Watch Subactive Subsleep Standby Standby Module TCR_1 Initialized Initialized TPU_1 TMDR_1 Initialized Initialized TIOR_1 Initialized Initialized TIER_1 Initialized Initialized TSR_1 Initialized Initialized TCNTH_1 Initialized Initialized TCNTL_1 Initialized Initialized TGRAH_1 Initialized Initialized TGRAL_1 Initialized Initialized TIOR_2 Initialized Initialized TIER_2 Initialized Initialized TSR_2 Initialized Initialized TCNTH_2 Initialized Initialized TCNTL_2 Initialized Initialized TGRAH_2 Initialized Initialized TGRAL_2 Initialized Initialized TGRBH_2 Initialized Initialized TGRBL_2 Initialized Initialized TCSR_0 Initialized Initialized TCNT_0 Initialized Initialized RSTCSR Initialized Initialized SMR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized BRR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized TDR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized SSR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized RDR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCMR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized SMR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized BRR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized TDR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized SSR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Rev. 2.00, 03/04, page 478 of 508 Software Hardware WDT_0 SCI_0 SCI_1 Register High- Medium Module Abbrev. Reset Speed -Speed Sleep Stop Watch Subactive Subsleep Standby Software Hardware Standby Module RDR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_1 SCMR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized ADDRAH Initialized Initialized Initialized Initialized Initialized Initialized Initialized ADDRAL Initialized Initialized Initialized Initialized Initialized Initialized Initialized ADDRBH Initialized Initialized Initialized Initialized Initialized Initialized Initialized ADDRBL Initialized Initialized Initialized Initialized Initialized Initialized Initialized ADDRCH Initialized Initialized Initialized Initialized Initialized Initialized Initialized ADDRCL Initialized Initialized Initialized Initialized Initialized Initialized Initialized ADDRDH Initialized Initialized Initialized Initialized Initialized Initialized Initialized ADDRDL Initialized Initialized Initialized Initialized Initialized Initialized Initialized ADCSR Initialized Initialized Initialized Initialized Initialized Initialized Initialized ADCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized TCSR_1 Initialized Initialized TCNT_1 Initialized Initialized FLMCR1 Initialized Initialized FLMCR2 Initialized Initialized EBR1 Initialized Initialized EBR2 Initialized Initialized FLPWCR Initialized Initialized PORT1 PORT3 PORT4 PORTA PORTB PORTC PORTD PORTF A/D WDT_1 FLASH (F-ZTAT version) PORT Note: is not initialized. Rev. 2.00, 03/04, page 479 of 508 Rev. 2.00, 03/04, page 480 of 508 Section 21 Electrical Characteristics 21.1 Absolute Maximum Ratings Table 21.1 lists the absolute maximum ratings. Table 21.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC, LPVCC -0.3 to +7.0 V PWMVCC -0.3 to +7.0 V Vin -0.3 to VCC + 0.3 V Input voltage (port 4) Vin -0.3 to AVCC +0.3 V Input voltage (except XTAL, EXTAL, and port 4) Vin -0.3 to VCC +0.3 V Input voltage (ports H and J) Vin -0.3 to PWMVCC +0.3 V Analog power supply voltage AVCC -0.3 to +7.0 V Analog input voltage VAN -0.3 to AVCC +0.3 V Operating temperature Topr Regular specifications: -20 to +75 C Wide-range specifications: -40 to +85 C -55 to +125 C Input voltage (XTAL, EXTAL) Storage temperature Tstg Caution: Permanent damage to this LSI may result if absolute maximum rating are exceeded. Rev. 2.00, 03/04, page 481 of 508 21.2 DC Characteristics Table 21.2 lists the DC characteristics. Table 21.3 lists the permissible output currents. Table 21.2 DC Characteristics Conditions: VCC = LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, VSS = AVSS = PWMVSS = PLLVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)*1 Item Symbol Min. Typ. Max. Test Unit Conditions Schmitt trigger input voltage IRQ0 to IRQ5, VT- VCC x 0.2 ports 1, 3, VT+ A to D, F, H, J + - VT - VT VCC x 0.05 V VCC x 0.7 V V Input high voltage RES, STBY, NMI, MD2, MD0, FWE Input low voltage Output high voltage Output low voltage VCC x 0.9 VCC + 0.3 V EXTAL VCC x 0.7 VCC + 0.3 V SCK0, SCK1, RxD0, RxD1, HRxD VCC x 0.7 VCC + 0.3 V Port 4 AVCC x 0.7 AVCC + 0.3 V RES, STBY, NMI, MD2, MD0, FWE VIH -0.3 VCC x 0.1 V EXTAL -0.3 VCC x 0.2 V SCK0, SCK1, RxD0, RxD1, HRxD -0.3 VCC x 0.2 V Port 4 -0.3 AVCC x 0.2 V All output pins VOH VCC - 0.5 V IOH = -200 A VCC - 1.0 V IOH = -1 mA 0.4 V IOL = 1.6 mA VIL All output pins VOL Rev. 2.00, 03/04, page 482 of 508 Typ. Max. Test Unit Conditions 1.0 A Vin = 0.5 to STBY, NMI, MD2, MD0, FWE, HRxD 1.0 A VCC - 0.5 V Port 4 1.0 A Vin = 0.5 to AVCC - 0.5 V Other than above ports 1.0 A Vin = 0.5 to VCC - 0.5 V 30 pF Vin = 0 V Item Input leakage current Symbol Min. RES Input RES capacitance NMI | Iin | Cin 30 pF f = 1 MHz 15 pF Ta = 25C 55 mA 45 (VCC = 5.0 V) (VCC = 5.5 V) f = 20 MHz Sleep mode 45 mA 35 (VCC = 5.0 V) (VCC = 5.5 V) f = 20 MHz All modules stopped 30 mA f = 20 MHz, VCC = 5.0 V (reference values) Medium-speed mode (/32) 30 mA f = 20 MHz, VCC = 5.0 V (reference values) Subactive mode 0.7 1.0 mA Using the subclock Subsleep mode 0.7 1.0 mA Using the subclock Watch mode 0.6 1.0 mA Using the subclock Standby mode 2 5.0 A Ta 50C 20 A 50C < Ta 10 20 mA All input pins except RES and NMI Normal Current 2 dissipation* operation ICC*3 LCD power- Operating supply port In standby power supply mode current LPICC Analog During A/D power supply conversion current Idle AlCC RAM standby voltage VRAM 0.1 10 A Ta 50C 80 A 50C < Ta 2.5 4.0 mA AVCC = 5.0 V 5.0 A 2.0 V Rev. 2.00, 03/04, page 483 of 508 Notes: 1. If the A/D converter is not used, do not leave the AVCC and AVSS pins open. Apply a voltage between 4.5 V and 5.5 V to the AVCC pin by connecting them to VCC, for instance. 2. Current dissipation values are for VIH = VCC (EXTAL), AVCC (port 4), PWMVCC, LPVCC, or VCC (other), and VIL = 0 V, with all output pins unloaded. 3. ICC depends on VCC and f as follows: ICC max = 22 + 0.3 x VCC x f (normal operation) ICC max = 18 + 0.25 x VCC x f (sleep mode) Table 21.3 Permissible Output Currents Conditions: VCC = LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, VSS = AVSS = PWMVSS = PLLVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)*1 Item Symbol All output pins except IOL Permissible PWM1A to 1H and output low current (per pin) PWM2A to 2H PWM1A to 1H, PWM2A to 2H Permissible output low current (total) IOL Typ. Max. Unit Test Conditions 10 mA 25 mA Ta = 75 to 85C 30 mA Ta = 25C Ta = -40C 40 mA Total of all output pins IOL except PWM1A to 1H and PWM2A to 2H 80 mA Total of PWM1A to IOL 1H and PWM2A to 2H 150 mA Ta = 75 to 85C 180 mA Ta = 25C 220 mA Ta = -40C 2.0 mA 25 mA Ta = 75 to 85C 30 mA Ta = 25C Ta = -40C Permissible All output pins except -IOH output high PWM1A to 1H and current (per pin) PWM2A to 2H PWM1A to 1H, PWM2A to 2H Permissible output high current (total) Min. -IOH 40 mA Total of all output pins -IOH except PWM1A to 1H and PWM2A to 2H 40 mA Total of PWM1A to -IOH 1H and PWM2A to 2H 150 mA Ta = 75 to 85C 180 mA Ta = 25C 220 mA Ta = -40C Note: To protect chip reliability, do not exceed the output current values in table 21.3. Rev. 2.00, 03/04, page 484 of 508 21.3 AC Characteristics Figure 21.1 shows the test conditions for the AC characteristics. 5V RL LSI output pin C RH C = 30pF: All ports RL = 2.4 k RH = 12 Input/output timing measurement levels * Low level : 0.8 V * High level : 2.0 V Figure 21.1 Output Load Circuit 21.3.1 Clock Timing Table 21.4 lists the clock timing Table 21.4 Clock Timing Conditions : VCC = LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, VSS = AVSS = PWMVSS = PLLVSS = 0 V, = 4 MHz to 20 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions Clock cycle time tcyc 50 250 ns Figure 21.2 Clock high pulse width tCH 15 ns Clock low pulse width tCL 15 ns Clock rise time tCr 5 ns Clock fall time tCf 5 ns Oscillation stabilization time at reset (crystal) tOSC1 20 ms Figure 21.3 Oscillation stabilization time in software standby (crystal) tOSC2 8 ms Figure 19.3 External clock output stabilization delay time tDEXT 2 ms Figure 21.3 Rev. 2.00, 03/04, page 485 of 508 tcyc tCH tCf tCL tCr Figure 21.2 System Clock Timing EXTAL tDEXT tDEXT VCC tOSC1 tOSC1 Figure 21.3 Oscillation Stabilization Timing Rev. 2.00, 03/04, page 486 of 508 21.3.2 Control Signal Timing Table 21.5 lists the control signal timing. Table 21.5 Control Signal Timing Conditions: VCC = LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, VSS = AVSS = PWMVSS = PLLVSS = 0 V, = 4 MHz to 20 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions RES setup time tRESS 200 ns Figure 21.4 RES pulse width tRESW 20 tcyc NMI setup time tNMIS 150 ns NMI hold time tNMIH 10 ns NMI pulse width (exiting software standby mode) tNMIW 200 ns IRQ setup time tIRQS 150 ns IRQ hold time tIRQH 10 ns IRQ pulse width (exiting software standby mode) tIRQW 200 ns Figure 21.5 tRESS tRESS tRESW Figure 21.4 Reset Input Timing Rev. 2.00, 03/04, page 487 of 508 tNMIS tNMIH NMI tNMIW tIRQW tIRQS tIRQH Edge input tIRQS Level input Figure 21.5 Interrupt Input Timing Rev. 2.00, 03/04, page 488 of 508 21.3.3 Timing of On-Chip Supporting Modules Table 21.6 lists the timing of on-chip supporting modules. Table 21.6 Timing of On-Chip Supporting Modules Conditions : VCC = LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, VSS = AVSS = PWMVSS = PLLVSS = 0 V, = 4 MHz to 20 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item I/O port TPU SCI Max. Unit Test Conditions Output data delay time tPWD Symbol Min. 50 ns Figure 21.6 Input data setup time tPRS 30 Input data hold time tPRH 30 Timer output delay time tTOCD 50 ns Figure 21.7 Timer input setup time tTICS 30 Timer clock input setup tTCKS time 30 ns Figure 21.8 Timer clock Single edge tTCKWH 1.5 tcyc pulse width Both edges tTCKWL 2.5 Input clock Asynchronous tScyc 4 cycle Synchronous tcyc 6 Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time 1.5 tcyc tSCKr Input clock fall time tSCKf 1.5 Transmit data delay time tTXD 50 Receive data setup time (synchronous) tRXS 50 Receive data hold time tRXH (synchronous) 50 ns Figure 21.9 Figure 21.10 Rev. 2.00, 03/04, page 489 of 508 Item Symbol Min. A/D Trigger input setup converter time tTRGS HCAN* Transmit data delay time Receive data setup time PWM Note: * Max. Unit Test Conditions 30 ns Figure 21.11 tHTXD 100 ns Figure 21.12 tHRXS 100 ns Figure 21.13 Receive data hold time tHRXH 100 Pulse output delay time tMPWMOD 50 The HCAN input signal is asynchronous. However, its state is judged to have changed at the rising-edge (two clock cycles) of the system clock signal () shown in figure 21.12. The HCAN output signal is also asynchronous. Its state changes are based on the rising-edge (two clock cycles) of the system clock signal () shown in figure 21.12. T2 T1 tPRS tPRH Port 1, 3, 4 A to D, F, H, J (read) tPWD Port 1, 3, A to D, F, H, J (write) T1 T2 T3 T4 tPRS tPRH Port H, J (read) tPWD Port H, J (write) Figure 21.6 I/O Port Input/Output Timing Rev. 2.00, 03/04, page 490 of 508 tTOCD Output compare output* tTICS Input capture input* Note : * TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, TIOCD0 Figure 21.7 TPU Input/Output Timing tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 21.8 TPU Clock Input Timing tSCKW tSCKr tSCKf SCK0, SCK1 tScyc Figure 21.9 SCK Clock Input Timing Rev. 2.00, 03/04, page 491 of 508 SCK0, SCK1 tTXD TxD0, TxD1 (transmit data) tRXS tRXH RxD0, RxD1 (receive data) Figure 21.10 SCI Input/Output Timing (Clock Synchronous Mode) tTRGS Figure 21.11 A/D Converter External Trigger Input Timing tHTXD HTxD (transmit data) tHRXS tHRXH HRxD (receive data) Figure 21.12 HCAN Input/Output Timing tMPWMOD PWM1A to PWM1H, PWM2A to PWM2H Figure 21.13 Motor Control PWM Output Timing Rev. 2.00, 03/04, page 492 of 508 21.4 A/D Conversion Characteristics Table 21.7 lists the A/D conversion characteristics. Table 21.7 A/D Conversion Characteristics Conditions : VCC = LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, VSS = AVSS = PWMVSS = PLLVSS = 0 V, = 4 MHz to 20 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Min. Typ. Max. Unit Resolution 10 10 10 bits Conversion time 10 200 s Analog input capacitance 20 pF Permissible signal-source impedance 5 k Nonlinearity error 3.5 LSB Offset error 3.5 LSB Full-scale error 3.5 LSB Quantization 0.5 LSB Absolute accuracy 4.0 LSB Rev. 2.00, 03/04, page 493 of 508 21.5 Flash Memory Characteristics Table 21.8 lists the flash memory characteristics. Table 21.8 Flash Memory Characteristics Conditions: VCC = PWMVCC = LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = 0 to +75C (Programming/erasing operating temperature range: regular specifications) Item Symbol Min. Typ. Max. Unit Programming time* * * tP 10 200 1, tE 100 1200 ms/block NWEC 100 1, 3, 2, 4 5 Erase time* * * Reprogramming count Test Condition ms/128 bytes Times Programming Wait time after SWE bit setting* tsswe 1 1 s 1 tspsu 50 50 s tsp30 28 30 32 s Programming time wait tsp200 198 200 202 s Programming time wait tsp10 8 10 12 s Additionalprogramming time wait 1 Wait time after PSU bit setting* 1, 4 Wait time after P bit setting* * 1 Wait time after P bit clear* 1 Wait time after PSU bit clear* 1 Wait time after PV bit setting* Wait time after H'FF dummy write* 1 1 Wait time after PV bit clear* 1 Wait time after SWE bit clear* 1, 4 Maximum programming count* * Erase 1 Wait time after SWE bit setting* 1 Wait time after ESU bit setting* 1, 5 Wait time after E bit setting* * 1 Wait time after E bit clear* 1 Wait time after ESU bit clear* 1 Wait time after EV bit setting* Wait time after H'FF dummy write* 1 Wait time after EV bit clear* 1 Wait time after SWE bit clear* 1, 5 Maximum erase count* * Rev. 2.00, 03/04, page 494 of 508 1 tcp 5 5 s tcpsu 5 5 s tspv 4 4 s tspvr 2 2 s tcpv 2 2 s s tcswe 100 100 N 1000 Times tsswe 1 1 tsesu 100 100 s tse 10 10 100 ms s tce 10 10 s tcesu 10 10 s tsev 20 20 s tsevr 2 2 s tcev 4 4 s tcswe 100 100 s N 12 120 Times Erase time wait Notes: 1. Follow the program/erase algorithms when making the time settings. 2. Programming time per 128 bytes. (Indicates the total time during which the P bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) 3. Time to erase one block. (Indicates the total time during which the E bit is set in FLMCR1. Does not include the erase-verify time.) 4. To specify the maximum programming time value (tp (max)) in the 128-byte programming algorithm, set the max. value (1000) for the maximum programming count (N). The wait time after P bit setting should be changed as follows according to the value of the programming counter (n). Programming counter (n) = 1 to 6: tsp30 = 30 s Programming counter (n) = 7 to 1000: tsp200 = 200 s (Additional programming) Programming counter (n) = 1 to 6: tsp10 = 10 s 5. For the maximum erase time (tE(max)), the following relationship applies between the wait time after E bit setting (tse) and the maximum erase count (N): tE(max) = Wait time after E bit setting (tse) x maximum erase count (N) To set the maximum erase time, the values of (tse) and (N) should be set so as to satisfy the above formula. Examples: When tse = 100 ms, N = 12 times When tse = 10 ms, N = 120 times Rev. 2.00, 03/04, page 495 of 508 21.6 LCD Characteristics Table 21.9 lists the LCD characteristics. Table 21.9 LCD Characteristics Conditions: VCC = LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, VSS = AVSS = PWMVSS = PLLVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)*1 Test Condition Min. Item Symbol Pins Typ. Max. Unit Remarks Segment driver step-down voltage VDS SEG1 to ID = 2 A SEG28 0.6 V *1 Common driver step-down voltage VDC COM1 to ID = 2 A COM4 0.3 V *1 LCD power-supply split-resistance RLCD V1 to VSS 40 300 1000 k LCD voltage VLCD 4.5 LPVCC V Notes: 1 2 V1 *2 The value shows the step-down voltage from the power-supply pins V1, V2, V3, and Vss to the respective segment pin or common pin. When the LCD voltage is supplied externally, the following relation should be maintained: LPVcc V1 V2 V3 Vss. Rev. 2.00, 03/04, page 496 of 508 Appendix A. I/O Port States in Each Pin State MCU Operating Port Name Mode Reset Hardware Standby Mode Software Standby Mode Subactive Mode Program Execution State Sleep Mode Port 1 7 T T Keep I/O port I/O port Port 3 7 T T Keep I/O port I/O port Port 4 7 T T T Input port Input port Port A 7 T T Keep I/O port I/O port Port B 7 T T Keep I/O port I/O port Port C 7 T T Keep I/O port I/O port Port D 7 T T Keep I/O port I/O port PF7 7 T T [DDR = 0] [DDR = 0] [DDR = 0] T T T [DDR = 1] [DDR = 1] [DDR = 1] H H Clock output PF6 7 T T Keep I/O port I/O port Port H 7 T T Keep I/O port I/O port Port J 7 T T Keep I/O port I/O port HTxD 7 H T H H Output HRxD 7 Input T T T Input PF5 PF4 PF3 PF2 PF0 [Legend] H: High level T: High impedance Keep: Input port becomes high-impedance, output port retains state Rev. 2.00, 03/04, page 497 of 508 B. Product Lineup Product H8S/2282 H8S/2281 Type Name Model Marking Package (Code) F-ZTAT version HD64F2282 HD64F2282 100-pin QFP (FP-100A) Mask ROM version HD6432282 HD6432282(***) 100-pin QFP (FP-100A) Mask ROM version HD6432281 HD6432281(***) 100-pin QFP (FP-100A) [Legend] (***): ROM code Note: The above products include those under development or being planned. For the status of each product, contact your nearest Renesas Technology sales office. C. Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has priority. Unit: mm 24.8 0.4 20 51 50 100 31 M 0.58 0.15 *Dimension including the plating thickness Base material dimension 2.70 0.13 0.20 +0.10 - 0.20 0.30 0.06 30 *0.17 0.05 0.15 0.04 1 *0.32 0.08 3.10 Max 0.65 81 14 18.8 0.4 80 0 - 10 1.2 0.2 Package Code JEDEC EIAJ Mass (reference value) Figure C.1 FP-100A Package Dimensions Rev. 2.00, 03/04, page 498 of 508 2.4 0.83 FP-100A 1.7 g Main Revisions and Additions in this Edition Item Page Revisions (See Manual for Details) 11.3.11 Interrupt Register (IRR) 291 Bit Bit Name Description 15 IRR7 Overload Frame Interrupt Flag [Setting condition] * When an overload frame is transmitted in error active/passive state [Clearing condition] * 11.3.13 Interrupt Mask Register (IMR) Writing 1 295 Bit Bit Name Description 15 IMR7 Overload Frame Interrupt Mask When this bit is cleared to 0, OVR0 (interrupt request by IRR7) is enabled. When set to 1, OVR0 is masked. 11.3.16 Unread Message Status Register (UMSR) 297 Symbols of bits 15 to 0 in R/W column switched from R/W to R/(W)* Note: * Only 1 is writable to clear the flag Figure 11.7 Software Reset 305 Flowchart OK? Yes GSR3 = 1? No Yes MCR0 = 0 GSR3 = 0? No Rev. 2.00, 03/04, page 499 of 508 Item Page Revisions (See Manual for Details) Table 11.2 Limits for the Settable Value 306 Notes: 1. SJW is stipulated in the CAN specifications: 3 SJW 0 2. The minimum value of TSEG2 is stipulated in the CAN specifications: TSEG2 SJW 3. The minimum value of TSEG1 is stipulated in the CAN specifications: TSEG1 > TSEG2 Table 11.3 Setting Range for TSEG1 and TSEG2 in BCR 307 TQ values deleted Figure 11.13 HCAN Sleep Mode Flowchart 316 MCR5 = 1 : Settings by user : Processing by hardware Bus idle? No Initialize TEC and REC Bus operation? No Yes IRR12 = 1 Do not access MB during this sequence No IMR12 = 1? CPU interrupt Yes Sleep mode clearing method MCR7 = 0? No (automatic) Yes (manual) Clear sleep mode? GSR3 = 1? No No Yes Yes MCR5 = 0 GSR3 = 1? Yes MCR5 = 0 Rev. 2.00, 03/04, page 500 of 508 No Item Page Revisions (See Manual for Details) Table 11.4 HCAN Interrupt 319 Sources Name Description Interrupt Flag ERS0/OVR0 Error passive interrupt IRR5 (TEC 128 or REC 128) Overload frame transmission interrupt 11.7.5 Error Counters 321 IRR7 Shadowed part below is deleted. In the case of error active and error passive, REC and TEC normally count up and down. In the bus-off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96 during the count, IRR4 and GSR1 are set, and if REC reaches 128, IRR7 is set. 11.7.10 HCAN TXCR Operation 322 Added 11.7.11 HCAN Transmit Procedure 323 Added 11.7.12 Note on Releasing the HCAN Software Reset and HCAN Sleep 11.7.13 Note on Accessing Mailbox during the HCAN Sleep 12.3.1 A/D Data Registers 328 A to D (ADDRA to ADDRD) 14.3.1 LCD Port Control Register (LPCR) 363 14.3.3 LCD Control Register 2 (LCR2) 366 Shadowed part added The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read directly from the CPU, however the lower byte should be read via a temporary register. The temporary register contents are transferred from the ADDR when the upper byte data is read. When reading the ADDR, read the upper byte before the lower byte, or read in word unit. Reading the lower bytes alone does not guarantee the contents. The symbol of bit 4 in column of R/W is switched from " -- " to " R/W ". Bit Bit Name Description 4 to 0 Reserved These bits should only be written with 0. Rev. 2.00, 03/04, page 501 of 508 Item Page Revisions (See Manual for Details) 14.4.2 Relationship between LCD RAM and Display 372 Output Levels (A Waveform) 14.4.3 Operation in Power- 372 Down Modes Section 15 RAM A term added More explanation on the subclock and LCD display is added 375 RAM Address H'FFE000 to H'FFEFBF, H'FFFFC0 to H'FFFFFF H'FFE000 to H'FFEFBF, H'FFFFC0 to H'FFFFFF H'FFE000 to H'FFEFBF, H'FFFFC0 to H'FFFFFF 17.1 Note on Switching from F-ZTAT Version to Masked ROM Version 402 18.1.2 Low-Power Control Register (LPWRCR) 406 This section added Bit Bit Name Description 3 RFCUT Oscillation Circuit Feedback Resistance Control 0: When the main clock is oscillating, sets the feedback resistance ON. When the main clock is stopped, sets the feedback resistance OFF. 1: Sets the feedback resistance OFF. Modification becomes valid after returning to software standby transfer. Note: With a crystal resonator, the resonator will not operate if this bit is set to 1. Table 19.2 LSI Internal States in Each Mode 416 19.4.3 Setting Oscillation 426 Stabilization Time after Clearing Software Standby Mode Rev. 2.00, 03/04, page 502 of 508 Row of subclock oscillator deleted Function Watch System clock pulse generator Functioning Functioning Functioning Below note added Note: * Do not use this setting Subactive Subsleep Item Page Revisions (See Manual for Details) 20.3 Register States in Each Operating Mode 21.2 DC Characteristics "Initialized" marks in message control (MC) and message data (MD) deleted 483 Item Input leakage current Table 21.2 DC Characteristics 483 Table 21.3 Permissible Output Currents 484 Table 21.6 Timing of OnChip Supporting Modules 489 Test Symbol Max. Unit Conditions Other than | Iin | above ports 1.0 A Vin = 0.5 to VCC - 0.5 V Some typ. and max. values of power dissipation specified, ICC max equations modified Values in column of max. specified Item HCAN* PWM Max. Transmit data delay time 100 Receive data setup time Receive data hold time Pulse output delay time 50 Rev. 2.00, 03/04, page 503 of 508 Rev. 2.00, 03/04, page 504 of 508 Index 16-Bit Timer Pulse Unit (TPU) .............. 131 Buffer Operation................................. 166 Buffer Operation Timing .................... 186 Counter Operation .............................. 158 Input Capture Function ....................... 162 Input Capture Signal Timing .............. 184 Output Compare Output Timing......... 184 Phase Counting Mode......................... 174 PWM Modes....................................... 169 Synchronous Operation ...................... 164 TCNT Count Timing .......................... 183 Waveform Output by Compare Match ............................. 160 A/D Converter ........................................ 325 A/D Conversion Time......................... 333 Analog Input Channel......................... 328 External Trigger.................................. 335 Scan Mode .......................................... 332 Single Mode........................................ 332 Address Map............................................. 50 Address Space........................................... 18 Addressing Modes .................................... 39 Absolute Address.................................. 40 Immediate ............................................. 41 Memory Indirect ................................... 41 Program-Counter Relative .................... 41 Register Direct...................................... 39 Register Indirect ................................... 39 Register Indirect with Displacement..... 39 Register indirect with post-increment... 40 Register indirect with pre-decrement.... 40 Bcc............................................................ 35 bus cycle ................................................... 83 Clock Pulse Generator ............................ 403 Condition Field ......................................... 38 Condition-Code Register (CCR)............... 22 Controller Area Network (HCAN).......... 277 CAN Bus Interface.............................. 320 Hardware Reset................................... 303 HCAN Halt Mode ............................... 318 HCAN Sleep Mode ............................. 315 Message Reception ............................. 312 Message Transmission ........................ 309 Software Reset .................................... 303 data direction register (DDR).................... 87 data register (DR)...................................... 87 Effective Address................................ 39, 42 Effective Address Extension..................... 38 Exception Handling .................................. 51 Interrupts............................................... 56 Reset Exception Handling..................... 53 Stack Status........................................... 58 Traces.................................................... 56 Trap Instruction..................................... 57 Exception Handling Vector Table............. 52 Extended Control Register (EXR) ............ 21 flash memory .......................................... 377 Boot Mode .......................................... 388 Emulation............................................ 391 Erase/Erase-Verify.............................. 395 erasing units ........................................ 382 Program/Program-Verify .................... 393 User Program Mode............................ 390 General Registers ...................................... 20 IC card (Smart Card) interface........ 215, 262 Instruction Set ........................................... 27 Arithmetic Operations Instructions ....... 30 Bit Manipulation Instructions ............... 33 Block Data Transfer Instructions .......... 37 Branch Instructions ............................... 35 Data Transfer Instructions..................... 29 Rev. 2.00, 03/04, page 505 of 508 Logic Operations Instructions............... 32 Shift Instructions .................................. 32 System Control Instructions ................. 36 Interrupt ADI..................................................... 335 CMI .................................................... 358 ERI...................................................... 273 ERS0................................................... 319 NMI ...................................................... 69 OVR0.................................................. 319 RM0.................................................... 319 RM1.................................................... 319 RXI ..................................................... 273 SLE0................................................... 319 TCI...................................................... 181 TEI...................................................... 273 TGI ..................................................... 181 TXI ..................................................... 273 WOVI ................................................. 211 Interrupt Control Modes ........................... 73 Interrupt Controller................................... 61 Interrupt Exception Handling Vector Table ............................................. 70 Interrupt Mask Bit .................................... 22 LCD Controller/Driver (LCD)................ 361 Common Drivers ................................ 364 Duty Cycle.......................................... 361 LCD Display....................................... 367 LCD RAM .......................................... 368 Segment Drivers ................................. 364 memory cycle ........................................... 83 Motor Control PWM Timer (PWM)....... 341 PWM Channel 1 ................................. 356 PWM Channel 2 ................................. 357 On-Board Programming Modes ............. 387 open-drain control register (ODR)............ 87 Operating Mode Selection ........................ 47 Operation Field......................................... 38 Power-Down Modes ............................... 413 Rev. 2.00, 03/04, page 506 of 508 Direct Transitions ............................... 434 Hardware Standby Mode .................... 428 Medium-Speed Mode.......................... 423 Module Stop Mode ............................. 430 Sleep Mode ......................................... 424 Software Standby Mode...................... 425 Subactive Mode .................................. 433 Subsleep Mode.................................... 432 Watch Mode........................................ 431 Program Counter (PC) .............................. 21 Program/Erase Protection ....................... 397 Programmer Mode .................................. 398 Register Field............................................ 38 Registers ABACK ...................... 288, 438, 452, 467 ADCR ......................... 331, 451, 465, 479 ADCSR ....................... 329, 451, 465, 479 ADDR ......................... 328, 450, 465, 479 BCR ............................ 282, 438, 452, 467 BRR ............................ 230, 450, 464, 478 EBR1........................... 385, 451, 465, 479 EBR2........................... 386, 451, 465, 479 FLMCR1..................... 384, 451, 465, 479 FLMCR2..................... 385, 451, 465, 479 FLPWCR .................... 387, 451, 465, 479 GSR............................. 281, 438, 452, 467 IER................................ 65, 447, 462, 476 IMR............................. 295, 438, 452, 467 IPR ................................ 64, 448, 463, 476 IRR.............................. 291, 438, 452, 467 ISCR ............................. 66, 447, 462, 476 ISR ................................ 68, 447, 462, 476 LAFM ......................... 298, 438, 453, 467 LCR............................. 365, 447, 462, 476 LCR2........................... 366, 447, 462, 476 LPCR .......................... 363, 447, 462, 476 LPWRCR.................... 419, 447, 462, 476 MBCR......................... 284, 438, 452, 467 MBIMR....................... 294, 438, 452, 467 MC .............................. 300, 438, 453, 467 MCR ........................... 280, 438, 452, 467 MD.............................. 302, 442, 457, 471 MDCR .......................... 47, 447, 462, 476 MSTPCR .................... 421, 447, 462, 476 P1DDR ......................... 91, 448, 462, 476 P1DR ............................ 91, 448, 463, 477 P3DDR ....................... 101, 448, 462, 476 P3DR .......................... 101, 448, 463, 477 P3ODR ....................... 102, 448, 462, 476 PADDR....................... 106, 448, 462, 476 PADR ......................... 106, 448, 463, 477 PAODR....................... 107, 448, 462, 476 PBDDR....................... 109, 448, 462, 476 PBDR.......................... 109, 449, 463, 477 PBODR....................... 110, 448, 462, 476 PCDDR....................... 112, 448, 462, 476 PCDR.......................... 112, 449, 463, 477 PCODR....................... 113, 448, 462, 476 PDDDR....................... 115, 448, 462, 476 PDDR ......................... 115, 449, 463, 477 PFDDR ....................... 117, 448, 462, 476 PFDR .......................... 118, 449, 463, 477 PHDDR....................... 121, 447, 461, 475 PHDR ......................... 121, 447, 461, 475 PJDDR........................ 125, 447, 461, 475 PJDR........................... 125, 447, 461, 475 PORT1.......................... 92, 451, 466, 479 PORT3........................ 102, 451, 466, 479 PORT4........................ 105, 451, 466, 479 PORTA ....................... 107, 451, 466, 479 PORTB ....................... 110, 451, 466, 479 PORTC ....................... 113, 451, 466, 479 PORTD ....................... 116, 451, 466, 479 PORTF........................ 118, 451, 466, 479 PORTH ....................... 122, 447, 461, 475 PORTJ ........................ 126, 447, 461, 475 PWBFR....................... 351, 446, 461, 475 PWCNT .............................................. 347 PWCR......................... 345, 446, 461, 475 PWCYR...................... 348, 446, 461, 475 PWDTR .............................................. 348 PWOCR...................... 346, 446, 461, 475 PWPR ......................... 347, 446, 461, 475 RAMER...................... 386, 448, 463, 477 RDR............................ 218, 450, 465, 478 REC............................. 296, 438, 452, 467 RFPR........................... 290, 438, 452, 467 RSR..................................................... 218 RSTCSR...................... 207, 450, 464, 478 RXPR .......................... 289, 438, 452, 467 SBYCR ....................... 417, 447, 462, 476 SCKCR ....................... 404, 447, 462, 476 SCMR ......................... 229, 450, 465, 478 SCR............................. 222, 450, 464, 478 SMR ............................ 219, 450, 464, 478 SSR ............................. 225, 450, 465, 478 SYSCR.......................... 48, 447, 462, 476 TCNT .......................... 155, 449, 463, 477 TCR............................. 137, 449, 463, 477 TCSR .......................... 203, 450, 464, 478 TDR ............................ 218, 450, 464, 478 TEC............................. 296, 438, 452, 467 TGR ............................ 155, 449, 463, 477 TIER............................ 151, 449, 463, 477 TIOR ........................... 142, 449, 463, 477 TMDR......................... 140, 449, 463, 477 TRPRT ........................ 129, 447, 461, 475 TSR ............................. 153, 449, 463, 477 TSTR........................... 156, 448, 462, 476 TSYR .......................... 157, 448, 462, 476 TXACK....................... 287, 438, 452, 467 TXCR.......................... 286, 438, 452, 467 TXPR .......................... 285, 438, 452, 467 UMSR ......................... 297, 438, 452, 467 Reset ......................................................... 53 Serial Communication Interface (SCI).... 215 Asynchronous Mode ........................... 237 Bit Rate ............................................... 230 Break................................................... 274 Clocked Synchronous Mode ............... 254 framing error ....................................... 244 Mark State........................................... 275 Multiprocessor Communication Function .............................................. 248 overrun error ....................................... 244 parity error .......................................... 244 stack pointer (SP)...................................... 20 Rev. 2.00, 03/04, page 507 of 508 Watchdog Timer ..................................... 201 Interval Timer Mode........................... 210 Rev. 2.00, 03/04, page 508 of 508 overflow.............................................. 211 Watchdog Timer Mode ....................... 208 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2282 Group Publication Date: 1st Edition Feb, 2002 Rev.2.00 Mar 18, 2004 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. 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