Revision Date: Mar. 18
,
2004
16 H8S/2282Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2200 Series
H8S/2282F HD64F2282
H8S/2282 HD6432282
H8S/2281 HD6432281
Rev.2.00
REJ09B0148-0200Z
The revision list can be viewed directly by
cliking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
Rev. 2.00, 03/04, page ii of xxx
Rev. 2.00, 03/04, page iii of xxx
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-
party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Keep safety first in your circuit designs!
Notes regarding these materials
Rev. 2.00, 03/04, page iv of xxx
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused In p ut Pi ns
Note: Fix all unused input pins to high or low level.
Generally, the inp ut pi ns of C M OS pr o duct s are high-impedance inp ut pi ns . If un used pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supp lied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also und efined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibiti on of Access t o Un d e fi ne d or Re se rved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
Rev. 2.00, 03/04, page v of xxx
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 2.00, 03/04, page vi of xxx
Preface
This LSI is a single-chip microcomputer made up of the high-speed H8S/2000 CPU as its core,
and the peripheral functions required to configure a system.
This LSI is equipped with ROM, RAM, a 16-bit timer pulse unit, a watchdog timer, serial
communication interfaces, a controller area network, an A/D converter, a motor control PWM
timer, an LCD controller/driver (LCD), a clock pulse generator, and I/O ports as on-chip
peripheral modules. This LSI is suitable for use as an embedded processor for high-level control
systems. Its on-chip ROM is flash memory (F-ZTATTM*) that provides flexibility as it can be
reprogrammed in no time to cope with all situations from the early stages of mass production to
full-scale mass production. This is particularly app licable to application dev ices with
specifications that will most probably change.
Note: * F-ZTATTM is a trademark of Renesas Technology Corp.
Target Users: This manual was written for users who will be using the H8S/2282 Group in the
design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective: This manual was written to exp lain the hardware functions and electrical
characteristics of the H8S/2282 Group to the target users.
See the H8S/2600 Series, H8S/2000 Series Programmi ng M anual fo r a det a il ed
description of the instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This ma nual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Programming Manual.
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 20,
List of Registers.
Examples: Register name: The following notat ion is used for cases when the same or a
similar function, e.g. serial communication interfaces, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order: The MSB is on the left and the LSB is on the right.
Rev. 2.00, 03/04, page vii of xxx
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx
Signal notation: An overbar is added to a low-active signal: xxxx
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
(http://www.renesas.com/eng/)
H8S/2282 Group manuals:
Document Title Document No.
H8S/2282 Group Hardware Manual This manual
H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083
User's manuals for development tools:
Document Title Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual
ADE-702-247
H8S, H8/300 Series Simulator/Debugger (for Windows) User’s Manual ADE-702-085
H8S, H8/300 Series Embedded Workshop, Debugging Interface Tutorial ADE-702-231
High-Performance Embedded Workshop User's Manual ADE-702-201
Rev. 2.00, 03/04, page viii of xxx
Rev. 2.00, 03/04, page ix of xxx
Contents
Section 1 Overview............................................................................................1
1.1 Overview...........................................................................................................................1
1.2 Internal Block Diagram.....................................................................................................2
1.3 Pin Arrangeme nt...............................................................................................................3
1.4 Pin Functions ....................................................................................................................4
Section 2 CPU....................................................................................................11
2.1 Features.............................................................................................................................11
2.1.1 Diffe rences between H8S/2600 CPU and H8S/2000 CPU..................................12
2.1.2 Diffe rences from H8/300 CPU ............................................................................13
2.1.3 Diffe rences from H8/300H CPU..........................................................................13
2.2 CPU Operating Modes......................................................................................................14
2.2.1 Normal Mode.......................................................................................................14
2.2.2 Advanced Mode...................................................................................................16
2.3 Address Space...................................................................................................................18
2.4 Register Configuration......................................................................................................19
2.4.1 General Registers.................................................................................................20
2.4.2 Program Counter (PC).........................................................................................21
2.4.3 Extended Control Register (EXR) .......................................................................21
2.4.4 Condition-Code Register (CCR)..........................................................................22
2.4.5 Initial Values of CPU Registers...........................................................................23
2.5 Data Formats.....................................................................................................................24
2.5.1 General Register Data Formats............................................................................24
2.5.2 Memor y Data Formats.........................................................................................26
2.6 Instruction Set...................................................................................................................27
2.6.1 Table of Instr uctions Classifie d by Function.......................................................28
2.6.2 Basic Instruction Formats....................................................................................37
2.7 Addressing Modes and Effective Address Calculation.....................................................39
2.7.1 Register Di rect—Rn ............................................................................................39
2.7.2 Register Indirect—@ERn....................................................................................39
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)..............39
2.7.4 Register Indirect with Post-Increment or
Pre-Decrement—@ER n+ or @-ERn...................................................................40
2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32....................................40
2.7.6 Imme diate—#xx:8, #xx:16, or #xx:32.................................................................41
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)....................................41
2.7.8 Memor y Indirect—@@aa:8 ................................................................................41
2.7.9 Effective Address Calculation .............................................................................42
2.8 Processing States...............................................................................................................45
Rev. 2.00, 03/04, page x of xxx
2.9 Usage Note........................................................................................................................46
2.9.1 Note on Bit Manipulation Instructions ................................................................46
Section 3 MCU Operating Modes.....................................................................47
3.1 Operating Mode Selection ................................................................................................47
3.2 Register Descriptions........................................................................................................47
3.2.1 Mode Control Register (MDCR).........................................................................47
3.2.2 System Control Register (SYSCR)......................................................................48
3.3 Pin Functions in Each Operating Mode............................................................................49
3.4 Address Map.....................................................................................................................50
Section 4 Exception Handling...........................................................................51
4.1 Exception Handling Types and Priority............................................................................51
4.2 Exception Sources and Exception Vector Table...............................................................51
4.3 Reset .................................................................................................................................53
4.3.1 Reset Exception Handling ...................................................................................53
4.3.2 Interrupts after Reset............................................................................................55
4.3.3 State of On-Chip Peripheral Modules after Reset Release ..................................55
4.4 Traces................................................................................................................................56
4.5 Interrupts...........................................................................................................................56
4.6 Trap Instruction.................................................................................................................57
4.7 Stack Status after Exce ption Ha ndling..............................................................................58
4.8 Usage Note........................................................................................................................59
Section 5 Interrupt Controller............................................................................61
5.1 Features.............................................................................................................................61
5.2 Input/Output Pins..............................................................................................................63
5.3 Register Descriptions........................................................................................................63
5.3.1 Interrupt Priority Registers A to G, J, K, M
(IPRA to IPRG, IPRJ, IPRK, IPRM)...................................................................64
5.3.2 IRQ Ena ble Re gister (IER)..................................................................................65
5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL).....................................66
5.3.4 IRQ Status Regi ster (ISR)....................................................................................68
5.4 Interrupt Sources...............................................................................................................69
5.4.1 External Interrupts...............................................................................................69
5.4.2 Inter nal Inter r u pts ................................................................................................70
5.5 Interrupt Exception Handling Vector Table......................................................................70
5.6 Interrupt Control Modes and Interr upt Ope ration.............................................................73
5.6.1 Interrupt Control Mode 0.....................................................................................73
5.6.2 Interrupt Control Mode 2.....................................................................................75
5.6.3 Interrupt Exception Handling Sequence..............................................................76
5.6.4 Interrupt Response Times....................................................................................78
5.7 Usage Notes......................................................................................................................79
Rev. 2.00, 03/04, page xi of xxx
5.7.1 Contention between Interrupt Generation and Disabling.....................................79
5.7.2 Instructions that Disable Interr upts......................................................................80
5.7.3 Whe n I nterrupts Are Disable d.............................................................................80
5.7.4 Inter rupts during Execution of EEPMOV Instruction..........................................81
5.7.5 IRQ I nterr upts......................................................................................................81
Section 6 Bus Controller....................................................................................83
6.1 Basic Timing.....................................................................................................................83
6.1.1 On-Chip Memory Access Timing (ROM, RAM)................................................83
6.1.2 On-Chip Peripheral Module Access Timing........................................................84
6.1.3 On-Chip HCAN Module Access Timing.............................................................85
6.1.4 On-Chip PWM, LCD, Ports H and J Module Access Timing .............................85
Section 7 I/O Ports.............................................................................................87
7.1 Port 1.................................................................................................................................91
7.1.1 Port 1 Data Direction Register (P1DDR).............................................................91
7.1.2 Port 1 Data Register (P1DR)................................................................................91
7.1.3 Port 1 Register (PORT1)......................................................................................92
7.1.4 Pin Functions .......................................................................................................92
7.2 Port 3.................................................................................................................................101
7.2.1 Port 3 Data Direction Register (P3DDR).............................................................101
7.2.2 Port 3 Data Register (P3DR)................................................................................101
7.2.3 Port 3 Register (PORT3)......................................................................................102
7.2.4 Port 3 Open-Drain Control Register (P3ODR)....................................................102
7.2.5 Pin Functions .......................................................................................................103
7.3 Port 4.................................................................................................................................105
7.3.1 Port 4 Register (PORT4)......................................................................................105
7.4 Port A................................................................................................................................106
7.4.1 Port A Data Direction Register (PADDR)...........................................................106
7.4.2 Port A Data Register (PADR)..............................................................................106
7.4.3 Port A Register (PORTA)....................................................................................107
7.4.4 Port A Open Drain Control Register (PAODR)...................................................107
7.4.5 Pin Functions .......................................................................................................108
7.5 Port B................................................................................................................................109
7.5.1 Port B Data Direction Register (PBDDR) ...........................................................109
7.5.2 Port B Data Register (PBDR)..............................................................................109
7.5.3 Port B Register (PORTB) ....................................................................................110
7.5.4 Port B Open Drain Control Register (PBODR)...................................................110
7.5.5 Pin Functions .......................................................................................................111
7.6 Port C................................................................................................................................112
7.6.1 Port C Data Direction Register (PCDDR) ...........................................................112
7.6.2 Port C Data Register (PCDR)..............................................................................112
7.6.3 Port C Register (PORTC) ....................................................................................113
Rev. 2.00, 03/04, page xii of xxx
7.6.4 Port C Open Drain Control Register (PCODR)...................................................113
7.6.5 Pin Functions.......................................................................................................114
7.7 Port D................................................................................................................................115
7.7.1 Port D Data Direction Register (PDDDR)...........................................................115
7.7.2 Port D Data Register (PDDR)..............................................................................115
7.7.3 Port D Register (PORTD)....................................................................................116
7.7.4 Pin Functions.......................................................................................................116
7.8 Port F ................................................................................................................................117
7.8.1 Port F Data Direction Register (PFDDR)............................................................117
7.8.2 Port F Data Register (PFDR)...............................................................................118
7.8.3 Port F Register (PORTF).....................................................................................118
7.8.4 Pin Functions.......................................................................................................119
7.9 Port H................................................................................................................................121
7.9.1 Port H Data Direction Register (PHDDR)...........................................................121
7.9.2 Port H Data Register (PHDR)..............................................................................121
7.9.3 Port H Register (PORTH)....................................................................................122
7.9.4 Pin Functions.......................................................................................................122
7.10 Port J.................................................................................................................................125
7.10.1 Port J Data Direction Register (PJDDR)..............................................................125
7.10.2 Port J Data Register (PJDR) ................................................................................125
7.10.3 Port J Register (P ORTJ) ......................................................................................126
7.10.4 Pin Functions.......................................................................................................126
7.11 Pin Switch Function..........................................................................................................129
7.11.1 Transport Register (TRPRT) ...............................................................................129
7.11.2 Reading of Port Registers by Switching t he Pin..................................................129
Section 8 16-Bit Timer Pulse Unit (TPU).........................................................131
8.1 Features.............................................................................................................................131
8.2 Input/Output Pins..............................................................................................................135
8.3 Register Descriptions........................................................................................................136
8.3.1 Timer Control Register (TCR).............................................................................137
8.3.2 Timer Mode Register (TMDR)............................................................................140
8.3.3 Timer I/O Control Register (TIOR).....................................................................142
8.3.4 Timer Interr upt Enable Register (TIER)..............................................................151
8.3.5 Timer Status Register (TSR)................................................................................153
8.3.6 Timer Counter (TCNT)........................................................................................155
8.3.7 Timer Gene ral Register (TGR)............................................................................155
8.3.8 Timer Start Register (TSTR) ...............................................................................156
8.3.9 Timer Synchro Register (TSYR).........................................................................157
8.4 Operation ..........................................................................................................................158
8.4.1 Basic Functions....................................................................................................158
8.4.2 Synchronous Operation........................................................................................164
8.4.3 Buf fer Operation..................................................................................................166
Rev. 2.00, 03/04, page xiii of xxx
8.4.4 PWM Modes........................................................................................................169
8.4.5 Phase Counting Mode..........................................................................................174
8.5 Interrupts...........................................................................................................................181
8.6 A/D Converter Activation.................................................................................................182
8.7 Operation Timing..............................................................................................................183
8.7.1 Input/Output Timing............................................................................................183
8.7.2 Inter rupt Signal Timing........................................................................................187
8.8 Usage Notes......................................................................................................................190
8.8.1 Module Stop Mode Setting..................................................................................190
8.8.2 Input Clock Restrictions ......................................................................................190
8.8.3 Caution on Period Setting....................................................................................191
8.8.4 Contention between TCNT Write and Clear Operations.....................................191
8.8.5 Contention between TCNT Write and Increment Operations..............................192
8.8.6 Contention between TGR Write and Compare Match.........................................193
8.8.7 Contention between Buffer Register Write and Compare Match ........................194
8.8.8 Contention between TGR Read and Input Capture..............................................195
8.8.9 Contention between TGR Write and Input Capture.............................................196
8.8.10 Contention between Buffer Register Write and Input Capture............................197
8.8.11 Contention between Overflow/Underflow and Counter Clearing........................198
8.8.12 Contention between TCNT Write and Overflow/Underflow...............................199
8.8.13 Multiplexing of I/O Pins......................................................................................199
8.8.14 Interrupts in Module Stop Mode..........................................................................199
8.8.15 Interrupts in Subactive Mode/Watch Mode.........................................................199
Section 9 Watchdog Timer................................................................................201
9.1 Features.............................................................................................................................201
9.2 Register Descriptions........................................................................................................203
9.2.1 Timer Counter 0 and 1 (TCNT_0 and TCNT_1).................................................203
9.2.2 Timer Control/Status Register 0 and 1 (TCSR_0 and TCSR_1)..........................203
9.2.3 Reset Control/Status Register (RSTCSR)............................................................207
9.3 Operation ..........................................................................................................................208
9.3.1 Watchdog Tim er Mode........................................................................................208
9.3.2 Interval Timer Mode............................................................................................210
9.4 Interrupts...........................................................................................................................211
9.5 Usage Notes......................................................................................................................211
9.5.1 Notes on Register Access.....................................................................................211
9.5.2 Contention between Timer Counter (TCNT) Write and Increment.....................212
9.5.3 Changing Value of CKS2 to CKS0......................................................................213
9.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................213
9.5.5 Internal Reset in Watchdog Timer Mode.............................................................213
9.5.6 OVF Flag Clearing in Interval Timer Mode........................................................213
Rev. 2.00, 03/04, page xiv of xxx
Section 10 Serial Communication Interface (SCI)............................................215
10.1 Features.............................................................................................................................215
10.2 Input/Output P i ns..............................................................................................................217
10.3 Register Descriptions........................................................................................................217
10.3.1 Receive Shift Register (RSR) ..............................................................................218
10.3.2 Receive Data Register (RDR)..............................................................................218
10.3.3 Transmit Data Register (TDR).............................................................................218
10.3.4 Transmit Shift Register (TSR).............................................................................218
10.3.5 Serial Mode Register (SMR) ...............................................................................219
10.3.6 Serial Control Register (SCR) .............................................................................222
10.3.7 Serial Status Register (SSR)................................................................................225
10.3.8 Smart Card Mode Register (SCMR)....................................................................229
10.3.9 Bit Rate Register (BRR)......................................................................................230
10.4 Operation in Asynchronous Mode....................................................................................237
10.4.1 Data Transfer Format...........................................................................................237
10.4.2 Receive Data Sampling Timing and Reception Margin in
Asynchronous Mode............................................................................................239
10.4.3 Clock....................................................................................................................240
10.4.4 SCI Initialization (Asynchronous Mode).............................................................241
10.4.5 Data Transmission (Asynchronous Mode) ..........................................................242
10.4.6 Serial Data Reception (Asynchronous Mode) .....................................................244
10.5 Multiprocessor Communication Function.........................................................................248
10.5.1 Multiprocessor Serial Data Transmission............................................................250
10.5.2 Multiprocessor Serial Data Reception.................................................................251
10.6 Operation in Clocked Synchronous Mode........................................................................254
10.6.1 Clock....................................................................................................................254
10.6.2 SCI Initialization (Clocked Synchronous Mode).................................................255
10.6.3 Serial Data Transmission (Clocked Synchronous Mode)....................................256
10.6.4 Serial Data Reception (Clocked Synchronous Mode) .........................................258
10.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mo de).............................................................................260
10.7 Operation in Smart Car d Inte rface....................................................................................262
10.7.1 Pin Connection Example .....................................................................................262
10.7.2 Data Format (Except for Block Transfer Mode)..................................................263
10.7.3 Block Transfer Mode...........................................................................................264
10.7.4 Receive Data Sampling Timing and Reception Margin in
Smart Card Interface Mode..................................................................................265
10.7.5 Initialization.........................................................................................................266
10.7.6 Data Transmission (Except for Block Transfer Mode)........................................266
10.7.7 Serial Data Reception (Except for Block Transfer Mode)...................................270
10.7.8 Clock Output Control...........................................................................................271
10.8 Interrupts...........................................................................................................................273
Rev. 2.00, 03/04, page xv of xxx
10.8.1 Interrupts in Normal Serial Comm unication Interface Mode ..............................273
10.8.2 Interrupts in Smart Card Interface Mo de.............................................................274
10.9 Usage Notes......................................................................................................................274
10.9.1 Module Stop Mode Setting..................................................................................274
10.9.2 Break Detection and Processing ..........................................................................274
10.9.3 Mark State and Break Detection..........................................................................275
10.9.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mo de Only).....................................................................275
Section 11 Controller Area Network (HCAN) ..................................................277
11.1 Features.............................................................................................................................277
11.2 Input/Output P i ns..............................................................................................................279
11.3 Register Descriptions........................................................................................................279
11.3.1 Master Control Register (MCR) ..........................................................................280
11.3.2 General Status Register (GSR) ............................................................................281
11.3.3 Bit Configuration Register (BCR) .......................................................................282
11.3.4 Mailbox Configuration Register (MBCR)...........................................................284
11.3.5 Transmit Wait Register (TXPR)..........................................................................285
11.3.6 Transmit Wait Cancel Register (TXCR)..............................................................286
11.3.7 Transmit Acknowledge Register (TXACK) ........................................................287
11.3.8 Abort Acknowledge Register (ABACK).............................................................288
11.3.9 Receive Complete Register (RXPR)....................................................................289
11.3.10 Remote Request Register (RFPR)........................................................................290
11.3.11 Interrupt Register (IRR).......................................................................................291
11.3.12 Mailbox Interrupt Mask Register (MBIMR)........................................................294
11.3.13 Interrupt Mask Register (IMR)............................................................................295
11.3.14 Receive Error Counter (REC)..............................................................................296
11.3.15 Transmit Error Counter (TEC).............................................................................296
11.3.16 Unread Message Status Register (UMSR)...........................................................297
11.3.17 Local Acceptance Filter Masks (LAFML, LAFMH)...........................................298
11.3.18 Message Control (MC0 to MC15).......................................................................300
11.3.19 Message Data (MD0 to MD15) ...........................................................................302
11.4 Operation ..........................................................................................................................303
11.4.1 Hardware and Software Resets............................................................................303
11.4.2 Initialization after Hardwa re Reset......................................................................303
11.4.3 Message Transmission.........................................................................................309
11.4.4 Message Reception..............................................................................................312
11.4.5 HCAN Sleep Mode..............................................................................................315
11.4.6 HCAN Halt Mode................................................................................................318
11.5 Interrupts...........................................................................................................................319
11.6 CAN Bus Interface............................................................................................................320
11.7 Usage Notes......................................................................................................................320
11.7.1 Module Stop Mode Setting..................................................................................320
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11.7.2 Reset ....................................................................................................................320
11.7.3 HCAN Sleep Mode..............................................................................................321
11.7.4 Interrupts..............................................................................................................321
11.7.5 Error Counters .....................................................................................................321
11.7.6 Register Access....................................................................................................321
11.7.7 HCAN Medium-Speed Mode..............................................................................321
11.7.8 Register Hold in Standby Modes.........................................................................321
11.7.9 Usage of Bit Manipulation Instructions...............................................................321
11.7.10 HCAN TXCR Operation .....................................................................................322
11.7.11 HCAN Transmit Procedure .................................................................................323
11.7.12 Note on Releasing the HCAN Software Reset and HCAN Sleep........................323
11.7.13 Note on Accessing Mailbox during the HCAN Sleep .........................................323
Section 12 A/D Converter.................................................................................325
12.1 Features.............................................................................................................................325
12.2 Input/Output P i ns..............................................................................................................327
12.3 Register Descriptions........................................................................................................328
12.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................328
12.3.2 A/D Control/Status Register (ADCSR)...............................................................329
12.3.3 A/D Control Register (ADCR) ............................................................................331
12.4 Operation ..........................................................................................................................332
12.4.1 Single Mode .........................................................................................................332
12.4.2 Scan Mode...........................................................................................................332
12.4.3 Input Sampling and A/D Conversion Time .........................................................333
12.4.4 External Trigger Input Timing.............................................................................335
12.5 Interrupts...........................................................................................................................335
12.6 A/D Conversion Precision Definitions .............................................................................336
12.7 Usage Notes......................................................................................................................338
12.7.1 Module Stop Mode Setting..................................................................................338
12.7.2 Permissible Signal Source Impedance.................................................................338
12.7.3 Influences on Absolute Precision.........................................................................338
12.7.4 Range of Analog Power Supply and Other Pin Settings......................................339
12.7.5 Notes on Board Design........................................................................................339
12.7.6 Notes on Noise Countermeasures........................................................................339
Section 13 Motor Control PWM Timer (PWM) ...............................................341
13.1 Features.............................................................................................................................341
13.2 Input/Output P i ns..............................................................................................................344
13.3 Register Descriptions........................................................................................................344
13.3.1 PWM Control Register_1, 2 (PWCR_1, PWCR_2) ............................................345
13.3.3 PWM Polarity Register_1, 2 (PWPR_1, PWPR_2).............................................347
13.3.4 PWM Counter_1, 2 (PWCNT_1, PWCNT_2).....................................................347
13.3.5 PWM Cycle Register_1, 2 (PWCYR_1, PWCYR_2) .........................................348
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13.3.6 PWM Duty Regi st er_ 1 A, 1C, 1E, 1G
(PWDTR_1A, PWDTR_1C, PWDTR_1E, PWDTR_1G)...................................348
13.3.7 PWM Buffer Register_1A, 1C, 1E, 1G
(PWBFR_1A, PWBFR_1C, PWBFR_1E, PWBFR_1G).....................................351
13.3.8 PWM Duty Register_2A to 2H (PWDTR_2A to PWDTR_2H)..........................352
13.3.9 PWM Buffer Register_2A to 2D (PWBFR2_A to PWBFR_2D)........................353
13.4 Bus Master Interface.........................................................................................................355
13.4.1 16-Bit Data Registers...........................................................................................355
13.4.2 8-Bit Data Registers.............................................................................................355
13.5 Operation ..........................................................................................................................356
13.5.1 PWM Channel 1 Operation..................................................................................356
13.5.2 PWM Channel 2 Operation..................................................................................357
13.6 Interrupts...........................................................................................................................358
13.7 Usage Note........................................................................................................................359
Section 14 LCD Controller/Driver (LCD).........................................................361
14.1 Features.............................................................................................................................361
14.2 Input/Output P i ns..............................................................................................................362
14.3 Register Descriptions........................................................................................................363
14.3.1 LCD Port Control Register (L PCR).....................................................................363
14.3.2 LCD Control Register (LCR)...............................................................................365
14.3.3 LCD Control Register 2 (LCR2)..........................................................................366
14.4 Operation ..........................................................................................................................367
14.4.1 Settings up to LCD Display.................................................................................367
14.4.2 Relationship between LCD RAM and Display....................................................368
14.4.3 Operation in Power-Down Modes.......................................................................372
14.4.4 Boosting the LCD Drive Power Supply...............................................................373
Section 15 RAM ................................................................................................375
Section 16 Flash Memory (F-ZTAT Version)...................................................377
16.1 Features.............................................................................................................................377
16.2 Mode Transitions..............................................................................................................378
16.3 Block Configuration..........................................................................................................382
16.4 Input/Output P i ns..............................................................................................................383
16.5 Register Descriptions........................................................................................................383
16.5.1 Flash Memory Control Register 1 (FLMCR1).....................................................384
16.5.2 Flash Memory Control Register 2 (FLMCR2).....................................................385
16.5.3 Erase Block Register 1 (EBR1) ...........................................................................385
16.5.4 RAM Emulation Register (RAMER)...................................................................386
16.5.5 Flash Memory Power Control Register (FLPWCR)............................................387
16.6 On-Board Programming Modes........................................................................................387
16.6.1 Boot Mode...........................................................................................................388
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16.6.2 Programming/Erasing in User Program Mode.....................................................390
16.7 Flash Memory Emulation in RAM ...................................................................................391
16.8 Flash Memory Programming/Erasing...............................................................................393
16.8.1 Program/Program-Verify.....................................................................................393
16.8.2 Erase/Erase-Verify...............................................................................................395
16.8.3 Interrupt Handling whe n Pr ogra mming/Erasing Flash Memory..........................395
16.9 Program/Erase Protection .................................................................................................397
16.9.1 Hardware Prot ection............................................................................................397
16.9.2 Software Protection .............................................................................................397
16.9.3 Error Protection ...................................................................................................398
16.10 Programmer Mode............................................................................................................398
16.11 Power-Down States for Flash Memory.............................................................................399
16.12 Flash Memory and Power-Down Modes ..........................................................................399
Section 17 Mask ROM......................................................................................401
17.1 Note on Switching from F-ZTAT Version to Masked ROM Version ..............................402
Section 18 Clock Pulse Generator.....................................................................403
18.1 Register Descriptions........................................................................................................404
18.1.1 System Clock Control Register (SCKCR)...........................................................404
18.1.2 Low-Power Control Register (LPWRCR)...........................................................406
18.2 Oscillator...........................................................................................................................407
18.2.1 Connecting a Crystal Resonator...........................................................................407
18.2.2 External Clock Input............................................................................................408
18.3 PLL Circuit.......................................................................................................................409
18.4 Subclock Divi der..............................................................................................................409
18.5 Medium-Speed Clock Divide r..........................................................................................409
18.6 Bus Master Clock Selection Circuit..................................................................................410
18.7 Usage Notes......................................................................................................................410
18.7.1 Note on Crystal Resonator...................................................................................410
18.7.2 Note on Board Design..........................................................................................410
Section 19 Power-Down Modes........................................................................413
19.1 Register Descriptions........................................................................................................417
19.1.1 Standby Control Register (SBYCR)....................................................................417
19.1.2 Low-Power Control Register (LPWRCR)...........................................................419
19.1.3 Module Stop Control Registers A to D (MSTPCRA to MSTPCRD)..................421
19.2 Medium-Speed Mode .......................................................................................................423
19.3 Sleep Mode.......................................................................................................................424
19.3.1 Transition to Sleep Mode.....................................................................................424
19.3.2 Clearing Sleep Mode ...........................................................................................424
19.4 Software Standby Mode....................................................................................................425
19.4.1 Transition to Software Standby Mode.................................................................425
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19.4.2 Clearing Software Standby Mode........................................................................425
19.4.3 Setting Oscillation Stabilization Time after Clearing
Software Standby Mode.......................................................................................426
19.4.4 Software Standby Mode Application Example....................................................427
19.5 Hardware Standby Mode ..................................................................................................428
19.5.1 Transition to Hardware Standby Mode................................................................428
19.5.2 Clearing Hardware Standby Mode.......................................................................428
19.5.3 Hardware Standby Mode Timings.......................................................................429
19.6 Module Stop Mode ...........................................................................................................430
19.7 Watch Mode......................................................................................................................431
19.7.1 Transition to Watch Mode...................................................................................431
19.7.2 Canceling Watch Mode........................................................................................431
19.8 Subsleep Mode..................................................................................................................432
19.8.1 Transition to Subsleep Mode...............................................................................432
19.8.2 Canceling Subsleep Mode....................................................................................432
19.9 Subactive Mode ................................................................................................................433
19.9.1 Transition to Subactive Mode..............................................................................433
19.9.2 Canceling Subactive Mode..................................................................................433
19.10 Direct Transitions..............................................................................................................434
19.10.1 Direct Transitions from High-Speed Mode to Subactive Mode...........................434
19.10.2 Direct Transitions from Subactive Mode to High-Speed Mode...........................434
19.11 φ Clock Output Disabling Function..................................................................................434
19.12 Usage Notes......................................................................................................................435
19.12.1 I/O Port Status......................................................................................................435
19.12.2 Cur rent Dissipation during Oscillation Stabilization Wait Period.......................435
19.12.3 On-Chip Peripheral Module I nterrupt..................................................................435
19.12.4 Writing to MSTPCR............................................................................................435
Section 20 List of Registers...............................................................................437
20.1 Register Addresses (Address Or der ).................................................................................438
20.2 Register Bits......................................................................................................................452
20.3 Register States in Each Operating Mode ..........................................................................467
Section 21 Electrical Characteristics .................................................................481
21.1 Absolute Maximum Ratings .............................................................................................481
21.2 DC Characteristics............................................................................................................482
21.3 AC Characteristics............................................................................................................485
21.3.1 Clock Timing.......................................................................................................485
21.3.2 Control Signal Timing.........................................................................................487
21.3.3 Timing of On-Chip Supporting Modules.............................................................489
21.4 A/D Conversion Characteristics........................................................................................493
21.5 Flash Memory Characteristics ..........................................................................................494
21.6 LCD Characteristics..........................................................................................................496
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Appendix .........................................................................................................497
A. I/O Port States in Each Pin State.......................................................................................497
B. Product Lineup..................................................................................................................498
C. Package Dimensions.........................................................................................................498
Main Revisions and Additions in this Edition.....................................................499
Index .........................................................................................................505
Rev. 2.00, 03/04, page xxi of xxx
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram.................................................................................................2
Figure 1.2 Pin Arrangement................................................................................................... .........3
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode).....................................................................15
Figure 2.2 Stack Structure in Normal Mode.................................................................................15
Figure 2.3 Exception Vector Table (Advanced Mode).................................................................16
Figure 2.4 Stack Structure in Advanced Mode.............................................................................17
Figure 2.5 Memory Map...............................................................................................................18
Figure 2.6 CPU Registers.............................................................................................................19
Figure 2.7 Usage of General Registers.........................................................................................20
Figure 2.8 Stack Status.................................................................................................................21
Figure 2.9 General Register Data Formats (1)..............................................................................24
Figure 2.9 General Register Data Formats (2)..............................................................................25
Figure 2.10 Memory Data Formats...............................................................................................26
Figure 2.11 Instruction Formats (Examples)................................................................................38
Figure 2.12 Branch Address Specification in Memory Indirect Mode.........................................42
Figure 2.13 State Transitions........................................................................................................46
Section 3 MCU Operating Modes
Figure 3.1 Address Map ...............................................................................................................50
Section 4 Exception Handling
Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)................................54
Figure 4.2 Reset Sequence
(Advanced Mode with On-chip ROM Disabled: Cannot be Used in this LSI)............55
Figure 4.3 Stack Status after Exception Handling........................................................................58
Figure 4.4 Operation when SP Value Is Odd................................................................................59
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller........................................................................62
Figure 5.2 Block Diagram of Interrupts IRQ5 to IRQ0................................................................69
Figure 5.3 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0......74
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2.....................76
Figure 5.5 Interrupt Exception Handling......................................................................................77
Figure 5.6 Contention between Interrupt Generation and Disabling............................................80
Section 6 Bus Controller
Figure 6.1 On-Chip Memory Access Cycle..................................................................................83
Figure 6.2 On-Chip Peripheral Module Access Cycle..................................................................84
Figure 6.3 On-Chip HCAN Module Access Cycle (Wait States Inserted)...................................85
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Figure 6.4 On-Chip PWM, LCD, Ports H and J Module Access Cycle.......................................85
Section 8 16-Bit Timer Pulse Unit (TPU)
Figure 8.1 Block Diagram of TPU .............................................................................................134
Figure 8.2 Example of Counter Operation Setting Procedure ....................................................158
Figure 8.3 Free-Running Counter Operation..............................................................................159
Figure 8.4 Periodic Counter Operation.......................................................................................160
Figure 8.5 Example of Setting Procedure for Waveform Output by Compare Match................160
Figure 8.6 Example of 0 Output/1 Output Operation .................................................................161
Figure 8.7 Example of Toggle Output Operation.......................................................................161
Figure 8.8 Example of Input Capture Operation Setting Procedure...........................................162
Figure 8.9 Example of Input Capture Operation ........................................................................163
Figure 8.10 Example of Synchronous Operation Setting Procedure ..........................................164
Figure 8.11 Example of Synchronous Operation........................................................................165
Figure 8.12 Compare Match Buffer Operation...........................................................................166
Figure 8.13 Input Capture Buffer Operation...............................................................................166
Figure 8.14 Example of Buffer Operation Setting Procedure.....................................................167
Figure 8.15 Example of Buffer Operation (1) ............................................................................168
Figure 8.16 Example of Buffer Operation (2) ............................................................................168
Figure 8.17 Example of PWM Mode Setting Procedure............................................................170
Figure 8.18 Example of PWM Mode Operation (1)...................................................................171
Figure 8.19 Example of PWM Mode Operation (2)...................................................................172
Figure 8.20 Example of PWM Mode Operation (3)...................................................................173
Figure 8.21 Example of Phase Counting Mode Setting Procedure.............................................174
Figure 8.22 Example of Phase Counting Mode 1 Operation......................................................175
Figure 8.23 Example of Phase Counting Mode 2 Operation......................................................176
Figure 8.24 Example of Phase Counting Mode 3 Operation......................................................177
Figure 8.25 Example of Phase Counting Mode 4 Operation......................................................178
Figure 8.26 Phase Counting Mode Application Example...........................................................180
Figure 8.27 Count Timing in Internal Clock Operation..............................................................183
Figure 8.28 Count Timing in External Clock Operation ............................................................183
Figure 8.29 Output Compare Output Timing .............................................................................184
Figure 8.30 Input Capture Input Signal Timing..........................................................................184
Figure 8.31 Counter Clear Timing (Compare Match) ................................................................185
Figure 8.32 Counter Clear Timing (Input Capture)....................................................................185
Figure 8.33 Buffer Operation Timing (Compare Match) ...........................................................186
Figure 8.34 Buffer Operation Timing (Input Capture)...............................................................186
Figure 8.35 TGI Interrupt Timing (Compare Match).................................................................187
Figure 8.36 TGI Interrupt Timing (Input Capture).....................................................................187
Figure 8.37 TCIV Interrupt Setting Timing................................................................................188
Figure 8.38 TCIU Interrupt Setting Timing................................................................................188
Figure 8.39 Timing for Status Flag Clearing by CPU ................................................................189
Figure 8.40 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode..................190
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Figure 8.41 Contention between TCNT Write and Clear Operations.........................................191
Figure 8.42 Contention between TCNT Write and Increment Operations.................................192
Figure 8.43 Contention between TGR Write and Compare Match.............................................193
Figure 8.44 Contention between Buffer Register Write and Compare Match............................194
Figure 8.45 Contention between TGR Read and Input Capture.................................................195
Figure 8.46 Contention between TGR Write and Input Capture ................................................196
Figure 8.47 Contention between Buffer Register Write and Input Capture................................197
Figure 8.48 Contention between Overflow and Counter Clearing..............................................198
Figure 8.49 Contention between TCNT Write and Overflow.....................................................199
Section 9 Watchdog Timer
Figure 9.1 Block Diagram of WDT_0........................................................................................202
Figure 9.2 Block Diagram of WDT_1........................................................................................202
Figure 9.3 (a) WDT_0 Operation in Watchdog Timer Mode.....................................................209
Figure 9.3 (b) WDT_1 Operation in Watchdog Timer Mode.....................................................209
Figure 9.4 Operation in Interval Timer Mode.............................................................................210
Figure 9.5 Writing to TCNT, TCSR, and RSTCSR (example for WDT0).................................212
Figure 9.6 Contention between TCNT Write and Inc rement......................................................212
Section 10 Serial Communication Interface (SCI)
Figure 10.1 Block Diagram of SCI.............................................................................................216
Figure 10.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits) ..................................................237
Figure 10.3 Receive Data Sampling Timing in Asynchronous Mode ........................................239
Figure 10.4 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode).............................................................................................240
Figure 10.5 Sample SCI Initialization Flowchart.......................................................................241
Figure 10.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) ....................................................242
Figure 10.7 Sample Serial Transmission Flowchart...................................................................243
Figure 10.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit) ....................................................244
Figure 10.9 Sample Serial Reception Data Flowchart (1) ..........................................................246
Figure 10.9 Sample Serial Reception Data Flowchart (2) ..........................................................247
Figure 10.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA t o Receiving Station A) ..........................................249
Figure 10.11 Sample Multiprocessor Serial Transmission Flowchart........................................250
Figure 10.12 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)..............................251
Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................252
Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................253
Figure 10.14 Data Format in Synchronous Communication (for LSB-First) .............................254
Figure 10.15 Sample SCI Initialization Flowchart .....................................................................255
Figure 10.16 Sample SCI Transmission Operation in Clocked Synchronous Mode..................256
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Figure 10.17 Sample Serial Transmission Flowchart.................................................................257
Figure 10.18 Example of SCI Operation in Reception...............................................................258
Figure 10.19 Sample Serial Reception Flowchart ......................................................................259
Figure 10.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ......261
Figure 10.21 Schematic Diagram of Smart Card Interface Pin Connections..............................262
Figure 10.22 Normal Smart Card Interface Data Format ...........................................................263
Figure 10.23 Direct Convention (SDIR = SINV = O/E = 0)......................................................263
Figure 10.24 Inve rse Convention (SDIR = SINV = O/E = 1) ....................................................264
Figure 10.25 Receive Data Sampling Timing in Smart Card Mode
(Using Clock of 372 Times the Transfer Rate) .....................................................265
Figure 10.26 Retransfer Operation in SCI Transmit Mode ........................................................267
Figure 10.27 TEND Flag Generation Timing in Transmission Operation .................................268
Figure 10.28 Example of Transmission Processing Flow...........................................................269
Figure 10.29 Retransfer Operation in SCI Receive Mode..........................................................270
Figure 10.30 Example of Reception Processing Flow................................................................271
Figure 10.31 Timing for Fixing Clock Output Level .................................................................271
Figure 10.32 Clock Halt and Restart Procedure .........................................................................272
Section 11 Controller Area Network (HCAN)
Figure 11.1 HCAN Block Diagram............................................................................................278
Figure 11.2 Message Control Register Configuration................................................................300
Figure 11.3 Standard Format......................................................................................................300
Figure 11.4 Extended Format.....................................................................................................300
Figure 11.5 Message Data Configuration...................................................................................302
Figure 11.6 Hardware Reset Flowchart......................................................................................304
Figure 11.7 Software Reset Flowchart .......................................................................................305
Figure 11.8 Detailed Description of One Bit..............................................................................306
Figure 11.9 Transmission Flowchart..........................................................................................309
Figure 11.10 Transmit Message Cancellation Flowchart...........................................................311
Figure 11.11 Reception Flowchart .............................................................................................312
Figure 11.12 Unread Message Overwrite Flowchart..................................................................315
Figure 11.13 HCAN Slee p Mode Flowc ha rt..............................................................................316
Figure 11.14 HCAN Halt Mode Flowchart................................................................................318
Figure 11.15 High-Speed Int erface Using PCA82C250.............................................................320
Section 12 A/D Converter
Figure 12.1 Block Diagram of A/D Converter ...........................................................................326
Figure 12.2 A/D Conversion Timing..........................................................................................333
Figure 12.3 External Trigger Input Timing ................................................................................335
Figure 12.4 A/D Conversion Precision Definitions....................................................................337
Figure 12.5 A/D Conversion Precision Definitions....................................................................337
Figure 12.6 Example of Analog Input Circuit............................................................................338
Figure 12.7 Example of Analog Input Protection Circuit...........................................................340
Figure 12.8 Analog Input Pin Equivalent Circuit.......................................................................340
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Section 13 Motor Control PWM Timer (PWM)
Figure 13.1 Block Diagram of PWM Channel 1 ........................................................................342
Figure 13.2 Block Diagram of PWM Channel 2 ........................................................................343
Figure 13.3 Cycle Register Compare Match...............................................................................348
Section 14 LCD Controller/Driver (LCD)
Figure 14.1 Block Diagram of LCD Controller/Driver ..............................................................362
Figure 14.2 LCD RAM Map (1/4 Duty).....................................................................................368
Figure 14.3 LCD RAM Map (1/3 Duty).....................................................................................369
Figure 14.4 LCD RAM Map (Static Mode)................................................................................369
Figure 14.5 Output Waveforms for Each Duty Cycle (A Waveform)........................................370
Figure 14.6 Output Waveforms for Each Duty Cycle (B Waveform)........................................371
Figure 14.7 Connection of External Split-Resistance.................................................................373
Section 16 Flash Memory (F-ZTAT Version)
Figure 16.1 Block Diagram of Flash Memory............................................................................378
Figure 16.2 Flash Memory State Transitions..............................................................................379
Figure 16.3 Boot Mode...............................................................................................................380
Figure 16.4 User Program Mode ................................................................................................381
Figure 16.5 Flash Memory Block Configuration........................................................................382
Figure 16.6 Programming/Erasing Flowchart Example in User Program Mode........................390
Figure 16.7 Flowchart for Flash Memory Emulation in RAM...................................................391
Figure 16.8 Example of RAM Overlap Operation ......................................................................392
Figure 16.9 Program/Program-Verify Flowchart........................................................................394
Figure 16.10 Erase/Erase-Verify Flowchart...............................................................................396
Section 17 Mask ROM
Figure 17.1 Block Diagram of 128-Kbyte Masked ROM (HD6432282) ...................................401
Figure 17.2 Block Diagram of 64-Kbyte Masked ROM (HD6432281) .....................................401
Section 18 Clock Pulse Generator
Figure 18.1 Block Diagram of Clock Pulse Generator...............................................................403
Figure 18.2 Connection of Crystal Resonator (Example)...........................................................407
Figure 18.3 Crystal Resonator Equivalent Circuit......................................................................407
Figure 18.4 External Clock Input (Examples)............................................................................408
Figure 18.5 External Clock Input Timing...................................................................................409
Figure 18.6 Note on Board Design of Oscillator Circuit............................................................410
Figure 18.7 External Circuitry Recommended for PLL Circuit..................................................411
Section 19 Power-Down Modes
Figure 19.1 Mode Transition Diagram .......................................................................................414
Figure 19.2 Medium-Speed Mode Transition and Clearance Timing ........................................423
Figure 19.3 Software Standby Mode Application Example .......................................................427
Figure 19.4 Timing of Transition to Hardware Standby Mode ..................................................429
Figure 19.5 Timing of Recovery from Hardware Standby Mode...............................................429
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Section 21 Electrical Characteristics
Figure 21.1 Output Load Circuit ................................................................................................485
Figure 21.2 System Clock Timing..............................................................................................486
Figure 21.3 Oscillation Stabilization Timing..............................................................................486
Figure 21.4 Reset Input Timing..................................................................................................487
Figure 21.5 Interrupt Input Timing .............................................................................................488
Figure 21.6 I/O Port Input/Output Timing..................................................................................490
Figure 21.7 TPU Input/Output Timing.......................................................................................491
Figure 21.8 TPU Clock Input Timing.........................................................................................491
Figure 21.9 SCK Clock Input Tim i ng ........................................................................................491
Figure 21.10 SCI Input/Output Timing (Clock Synchronous Mode).........................................492
Figure 21.11 A/D Converter External Trigger Input Timing......................................................492
Figure 21.12 HCAN Input/Out put Timing.................................................................................492
Figure 21.13 Motor Contr ol P WM Outp ut Timing ....................................................................492
Appendix
Figure C.1 FP-100A Package Dimensions.................................................................................498
Rev. 2.00, 03/04, page xxvii of xxx
Tables
Section 2 CPU
Table 2.1 Instruction Classification........................................................................................27
Table 2.2 Operation Notation .................................................................................................28
Table 2.3 Data Transfer Instructions.......................................................................................29
Table 2.4 Arithmetic Operations Instructions (1) ...................................................................30
Table 2.4 Arithmetic Operations Instructions (2) ...................................................................31
Table 2.5 Logic Operations Instructions.................................................................................32
Table 2.6 Shift Instructions.....................................................................................................32
Table 2.7 Bit Manipulation Instructions (1)............................................................................33
Table 2.7 Bit Manipulation Instructions (2)............................................................................34
Table 2.8 Branch Instructions.................................................................................................35
Table 2.9 System Control Instructions....................................................................................36
Table 2.10 Block Data Transfer Instructi ons............................................................................37
Table 2.11 Addressing Modes ..................................................................................................39
Table 2.12 Absolute Address Access Ranges...........................................................................40
Table 2.13 Effective Address Calculation (1)...........................................................................43
Table 2.13 Effective Address Calculation (2)...........................................................................44
Section 3 MCU Operating Modes
Table 3.1 MCU Operating Mode Selection ............................................................................47
Section 4 Exception Handling
Table 4.1 Exception Types and Priority..................................................................................51
Table 4.2 Exception Handling Vector Table...........................................................................52
Table 4.3 Status of CCR and EXR after Trace Exception Handling.......................................56
Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling......................57
Section 5 Interrupt Controller
Table 5.1 Pin Configuration....................................................................................................63
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities.................................71
Table 5.3 Interrupt Control Modes .........................................................................................73
Table 5.4 Interrupt Response Times.......................................................................................78
Table 5.5 Number of States in Interrupt Handling Routine Execution Status ........................79
Section 7 I/O Ports
Table 7.1 Port Functions (1) ...................................................................................................88
Table 7.1 Port Functions (2) ...................................................................................................89
Table 7.1 Port Functions (3) ...................................................................................................90
Table 7.2 Pins of Registers to be Read and PWM Output by Switching Pins ......................130
Rev. 2.00, 03/04, page xxviii of xxx
Section 8 16-Bit Timer Pulse Unit (TPU)
Table 8.1 TPU Functions (1) ................................................................................................132
Table 8.1 TPU Functions (2) ................................................................................................133
Table 8.2 Pin Configuration..................................................................................................135
Table 8.3 CCLR0 to CCLR2 (Cha nnel 0) ............................................................................138
Table 8.4 CCLR0 to CCLR2 (Channels 1 and 2).................................................................138
Table 8.5 TPSC0 to TPSC2 (Channel 0)..............................................................................139
Table 8.6 TPSC0 to TPSC2 (Channel 1)..............................................................................139
Table 8.7 TPSC0 to TPSC2 (Channel 2)..............................................................................140
Table 8.8 MD0 to MD3........................................................................................................141
Table 8.9 TIORH_0..............................................................................................................143
Table 8.10 TIORL_0 ..............................................................................................................144
Table 8.11 TIOR_1.................................................................................................................145
Table 8.12 TIOR_2.................................................................................................................146
Table 8.13 TIORH_0..............................................................................................................147
Table 8.14 TIORL_0 ..............................................................................................................148
Table 8.15 TIOR_1.................................................................................................................149
Table 8.16 TIOR_2.................................................................................................................150
Table 8.17 Register Combinations in Buffer Operation .........................................................166
Table 8.18 PWM Output Registers and Output Pins..............................................................170
Table 8.19 Phase Counting Mode Clock Input Pins...............................................................174
Table 8.20 Up/Down-Count Conditions in Phase Counting Mode 1......................................175
Table 8.21 Up/Down-Count Conditions in Phase Counting Mode 2......................................176
Table 8.22 Up/Down-Count Conditions in Phase Counting Mode 3......................................177
Table 8.23 Up/Down-Count Conditions in Phase Counting Mode 4......................................178
Table 8.24 TPU Interrupts......................................................................................................181
Section 9 Watchdog Timer
Table 9.1 WDT Interrupt Source..........................................................................................211
Section 10 Serial Communication Interface (SCI)
Table 10.1 Pin Configuration..................................................................................................217
Table 10.2 The Relationships between The N Setting in BRR and Bit Rate B ......................230
Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)...........................231
Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)...........................232
Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3)...........................233
Table 10.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ..........................234
Table 10.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................234
Table 10.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode).....................235
Table 10.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) ....235
Table 10.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)
(When n = 0 and S = 372).....................................................................................236
Rev. 2.00, 03/04, page xxix of xxx
Table 10.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(when S = 372)......................................................................................................236
Table 10.10 Serial Transfer Formats (Asynchronous Mode)....................................................238
Table 10.11 SSR Status Flags and Receive Data Handling......................................................245
Table 10.12 SCI Interrupt Sources............................................................................................273
Table 10.13 SCI Interrupt Sources............................................................................................274
Section 11 Controller Area Network (HCAN)
Table 11.1 Pin Configuration..................................................................................................279
Table 11.2 Limits for the Settable Value................................................................................306
Table 11.3 Setting Range for TSEG1 and TSEG2 in BCR.....................................................307
Table 11.4 HCAN Interrupt Sources.......................................................................................319
Table 11.5 Interval Limitation between TXPR and TXPR or between TXPR and TXCR.....323
Section 12 A/D Converter
Table 12.1 Pin Configuration..................................................................................................327
Table 12.2 Analog Input Channels and Corresponding ADDR Registers..............................328
Table 12.3 A/D Conversion Time (Single Mode)...................................................................334
Table 12.4 A/D Conversion Time (Scan Mode).....................................................................334
Table 12.5 A/D Converter Interrupt Source............................................................................335
Table 12.6 Analog Pin Specifications.....................................................................................340
Section 13 Motor Control PWM Timer (PWM)
Table 13.1 Pin Configuration..................................................................................................344
Table 13.2 PWM Interrupt Sources........................................................................................358
Section 14 LCD Controller/Driver (LCD)
Table 14.1 Pin Configuration..................................................................................................362
Table 14.2 Selection of the Duty Cycle and Common Functions...........................................364
Table 14.3 Selection of Segment Drivers ...............................................................................364
Table 14.4 Selection of the Operating Clock and Frame Frequency ......................................366
Table 14.5 Output Levels (A Wavefo rm)...............................................................................372
Table 14.6 Power-Down Modes and Display Operation ........................................................372
Section 16 Flash Memory (F-ZTAT Version)
Table 16.1 Differences between Boot Mode and U ser Pr ogram Mode ..................................379
Table 16.2 Pin Configuration..................................................................................................383
Table 16.3 Setting On-Board Programming Modes ...............................................................387
Table 16.4 Boot Mode Operation ...........................................................................................389
Table 16.5 System Clock Frequencies for which Automatic Adjustment of
LSI Bit Rate is Possible ........................................................................................389
Table 16.6 Flash Memory Operating States............................................................................399
Section 17 Mask ROM
Table 17.1 Register Present in F-ZTAT Version but Absent in Masked ROM Version.........402
Rev. 2.00, 03/04, page xxx of xxx
Section 18 Clock Pulse Generator
Table 18.1 Damping Resistance Value...................................................................................407
Table 18.2 Crystal Resonator Characteristics.........................................................................407
Table 18.3 External Clock Input Conditions ..........................................................................408
Section 19 Power-Down Modes
Table 19.1 Power-Down Mode Transition Conditions...........................................................415
Table 19.2 LSI Internal States in Each Mode.........................................................................416
Table 19.3 Oscillation Stabilization Time Settings ................................................................426
Table 19.4 φ Pin State in Each Processing State.....................................................................434
Section 21 Electrical Characteristics
Table 21.1 Absolute Maximum Ratings.................................................................................481
Table 21.2 DC Characteristics................................................................................................482
Table 21.3 Permissible Output Currents.................................................................................484
Table 21.4 Clock Timing........................................................................................................485
Table 21.5 Control Signal Timing..........................................................................................487
Table 21.6 Timing of On-Chip Supporting Modules..............................................................489
Table 21.7 A/D Conversion Characteristics ...........................................................................493
Table 21.8 Flash Memory Characteristics ..............................................................................494
Table 21.9 LCD Characteristics..............................................................................................496
Rev. 2.00, 03/04, page 1 of 508
Section 1 Overview
1.1 Overview
• High-speed H8S/2000 cent ral pr ocessing unit with an internal 16-bit architectur e
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit gene ral regi st ers
65 basic instructions
• Various peripheral functions
16-bit timer-pulse unit (TPU)
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial communication interface (SCI)
Controller area network (HCAN)
10-bit A/D converter
Motor contro l PWM timer (PWM)
LCD controller/driver (LCD)
Clock pulse generat or
• On-chip memory
ROM Model ROM RAM
F-ZTAT Version HD64F2282 128 kbytes 4 kbytes
Mask ROM Version HD6432282
HD6432281
128 kbytes
64 kbytes
4 kbytes
4 kbytes
• General I/O ports
• I/O pins: 64
• Input-only pins: 8
• Suppor ts various power-down states
• Compact package
Package (Code) Body Size Pin Pitch
QFP-100 FP-100A 14.0 × 20.0 mm 0.65 mm
Rev. 2.00, 03/04, page 2 of 508
1.2 Internal Block Diagram
PWMV
CC
PWMV
CC
PWMV
SS
PWMV
SS
LPV
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
CL
V1
V2
V3
AV
CC
AV
SS
P47/ AN7
P46/ AN6
P45/ AN5
P44/ AN4
P43/ AN3
P42/ AN2
P41/ AN1
P40/ AN0
HRxD/
HTxD
PH7/PWM1H
PH6/PWM1G
PH5/PWM1F
PH4/PWM1E
PH3/PWM1D
PH2/PWM1C
PH1/PWM1B
PH0/PWM1A
PJ7/PWM2H
PJ6/PWM2G
PJ5/PWM2F
PJ4/PWM2E
PJ3/PWM2D
PJ2/PWM2C
PJ1/PWM2B
PJ0/PWM2A
PF7/
PF6/SEG24
PF5/SEG23
PF4/SEG22
PF3/ /
PF2/SEG21
P17/TIOCB2/TCLKD
P16/TIOCA2/
P15/TIOCB1/TCLKC
P14/TIOCA1/
P13/TIOCD0/TCLKB
P12/TIOCC0/TCLKA
P11/TIOCB0
P10/TIOCA0
RAM
TPU
3 channels
SCI 2 channels
PWM
MD2
MD0
EXTAL
XTAL
PLLCAP
PLLV
SS
NMI
FWE*
H8S/2000 CPU
PA7/SEG28
PA6/SEG27
PA5/SEG26
PA4/SEG25
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
Port A
PB7/SEG20
PB6/SEG19
PB5/SEG18
PB4/SEG17
PB3/SEG16
PB2/SEG15
PB1/SEG14
PB0/SEG13
Port B
PC7/SEG12
PC6/SEG11
PC5/SEG10
PC4/SEG9
PC3/SEG8
PC2/SEG7
PC1/SEG6
PC0/SEG5
PD7/SEG4
PD6/SEG3
PD5/SEG2
PD4/SEG1
Port CPort D
P35/SCK1/
P34/RxD1
P33/TxD1
P32/SCK0/
P31/RxD0
P30/TxD0
Port 3
Port 4
Port H Port J
Port FPort 1
PLL
Clock pulse
generator
Interrupt controller
ROM
(Mask ROM,
flash memory)
WDT 2 channels
LCD
HCAN 1 channel
10-bit A/D converter
Peripheral address bus
Peripheral data bus
Bus controller
Internal address bus
Internal data bus
Note: The FWE pin is provided only in the flash memory version.
The NC pin is provided only in the mask ROM version.
φ
Figure 1.1 Internal Block Diagram
Rev. 2.00, 03/04, page 3 of 508
1.3 Pin Arrangement
PJ3/PWM2D
PJ2/PWM2C
PJ1/PWM2B
PJ0/PWM2A
PH7/PWM1H
PH6/PWM1G
PH5/PWM1F
PH4/PWM1E
PWMV
CC
PWMV
SS
PH3/PWM1D
PH2/PWM1C
PH1/PWM1B
PH0/PWM1A
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
PA7/SEG28
PA6/SEG27
Top view
(FP-100A)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P30/TxD0
PF3/ /
PF7/φ
V
CC
XTAL
EXTAL
V
SS
FWE
V
CL
PLLV
SS
PLLCAP
NMI
MD0
MD2
P17/TIOCB2/TCLKD
P16/TIOCA2/
P15/TIOCB1/TCLKC
P14/TIOCA1/
P13/TIOCD0/TCLKB
P12/TIOCD0/TCLKA
P11/TIOCB0
P10/TIOCA0
PJ7/PWM2H
PJ6/PWM2G
PJ5/PWM2F
PJ4/PWM2E
PWMV
CC
PWMV
SS
P31/RxD0
P32/SCK0/
P33/TxD1
P34/RxD1
P35/SCK1/
HRxD/
HTxD
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6
P47/AN7
AV
CC
AV
SS
V1
V2
V3
V
SS
V
CC
PD4/SEG1
PD5/SEG2
PD6/SEG3
PD7/SEG4
PC0/SEG5
PC1/SEG6
PC2/SEG7
PC3/SEG8
PC4/SEG9
PC5/SEG10
PC6/SEG11
PC7/SEG12
PB0/SEG13
PB1/SEG14
PB2/SEG15
PB3/SEG16
LPV
CC
V
SS
PB4/SEG17
PB5/SEG18
PB6/SEG19
PB7/SEG20
PF2/SEG21
PF4/SEG22
PF5/SEG23
PF6/SEG24
PA4/SEG25
PA5/SEG26
Figure 1.2 Pin Arrangement
Rev. 2.00, 03/04, page 4 of 508
1.4 Pin Functions
Type Symbol Pin NO. I/O Function
Power
Supply
VCC 2
77
Input Power supply pins. Connect all these pins to the
system power supply.
PWMVCC 42
52
Input Power supply pins for the ports H, J, and the
motor control PWM timer.
LPVCC 19 Input Power supply pins for the ports A to D and F
(PF2 and PF4 to PF6).
V1
V2
V3
98
99
100
Input Power supply pins for the LCD controller/driver.
These pins are internally connected to the
power-supply dividing resistors and in normal
use are open-circuit. When power is supplied,
the state is LPVCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS
V
SS 1
20
74
Input Ground pins. Connect all these pins to the
system power supply (0V).
PWMVSS 41
51
Input Power supply pins for the ports H, J, and the
motor control PWM timer. Connect all these pins
to the system power supply (0V).
V
CL 71 Output External capacitance pin for internal power-down
power supply. Connect this pin to VSS via a 0.1-
µF capacitor (placed close to the pins).
PLLVSS 70 Input On-chip PLL oscillator ground pin. Clock
PLLCAP 69 Output External capacitance pin for an on-chip PLL
oscillator.
XTAL 76 Input For connection to a crystal resonator. For
examples of crystal resonator connection and
external clock input, see section 18, Clock Pulse
Generator.
EXTAL 75 Input For connection to a crystal resonator. (An
external clock can be supplied from the EXTAL
pin.) For examples of crystal resonator
connection and external clock input, see section
18, Clock Pulse Generator.
φ 78 Output Supplies the system clock to external devices.
Operating
mode
control
MD2 MD0 65
66
Input Set the operating mode. Inputs at these pins
should not be changed during operation.
Rev. 2.00, 03/04, page 5 of 508
Type Symbol Pin NO. I/O Function
System
control
RES 73 Input Reset input pin. When this pin is low, the chip is
reset.
STBY 68 Input When this pin is low, a transition is made to
hardware standby mode.
FWE 72 Input Pin for use by flash memory. This pin is only
used in the flash memory version.
Interrupts NMI 67 Input Nonmaskable interrupt pin. If this pin is not used,
it should be fixed-high.
IRQ5 IRQ4
IRQ3 IRQ2
IRQ1 IRQ0
85
82
79
86
63
61
Input These pins request a maskable interrupt.
TCLKA
TCLKB
TCLKC
TCLKD
59
60
62
64
Input These pins input an external clock. 16-bit timer-
pulse unit
TIOCA0
TIOCB0
TIOCC0
TIOCD0
57
58
59
60
Input/Out
put
TGRA_0 to TGRD_0 input capture input/output
compare output/PWM output pins.
TIOCA1
TIOCB1
61
62
Input/Out
put
TGRA_1 to TGRB_1 input capture input/output
compare output/PWM output pins.
TIOCA2
TIOCB2
63
64
Input/Out
put
TGRA_2 to TGRB_2 input capture input/output
compare output/PWM output pins.
TxD1 TxD0 83
80
Output Data output pins
RxD1
RxD0
84
81
Input Data input pins
Serial
communi-
cation
Interface
(SCI)/
smart card
interface
SCK1
SCK0
85
82
Input/Out
put
Clock input/output pins
HTxD 87 Output CAN bus transmission pin HCAN
HRxD 86 Input CAN bus reception pin
Rev. 2.00, 03/04, page 6 of 508
Type Symbol Pin NO. I/O Function
A/D
converter
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
95
94
93
92
91
90
89
88
Input Analog input pins
ADTRG 79 Input Pin for input of an external trigger to start A/D
conversion
AVCC 96 Input Power supply pin for the A/D converter. When
the A/D converter is not used, connect this pin to
the system power supply (+5V).
AVSS 97 Input The ground pin for the A/D converter. Connect
this pin to the system power supply (0V).
Motor
control PWM
timer
PWM1H
PWM1G
PWM1F
PWM1E
PWM1D
PWM1C
PWM1B
PWM1A
46
45
44
43
40
39
38
37
Output PWM_1 pulse output pin
PWM2H
PWM2G
PWM2F
PWM2E
PWM2D
PWM2C
PWM2B
PWM2A
56
55
54
53
50
49
48
47
Output PWM_2 pulse output pin
Rev. 2.00, 03/04, page 7 of 508
Type Symbol Pin NO. I/O Function
LCD
controller/
driver
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
32
31
30
29
28
27
26
25
24
23
22
21
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
Output Output pins for the LCD-segment-driving signals.
COM4
COM3
COM2
COM1
36
35
34
33
Output Output pins for the LCD-common-driving signals.
I/O ports P17
P16
P15
P14
P13
P12
P11
P10
64
63
62
61
60
59
58
57
Input/
Output
Eight input/output pins
P35
P34
P33
P32
P31
P30
85
84
83
82
81
80
Input/
Output
Six input/output pins
Rev. 2.00, 03/04, page 8 of 508
Type Symbol Pin NO. I/O Function
I/O ports P47
P46
P45
P44
P43
P42
P41
P40
95
94
93
92
91
90
89
88
Input Eight input pins
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
32
31
30
29
36
35
34
33
Input/
Output
Eight input/output pins
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
24
23
22
21
18
17
16
15
Input/
Output
Eight input/output pins
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
14
13
12
11
10
9
8
7
Input/
Output
Eight input/output pins
PD7
PD6
PD5
PD4
6
5
4
3
Input/
Output
Four input/output pins
PF7
PF6
PF5
PF4
PF3
PF2
78
28
27
26
79
25
Input/
Output
Six input/output pins
Rev. 2.00, 03/04, page 9 of 508
Type Symbol Pin NO. I/O Function
I/O ports PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
46
45
44
43
40
39
38
37
Input/
Output
Eight input/output pins
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
56
55
54
53
50
49
48
47
Input/
Output
Eight input/output pins
Rev. 2.00, 03/04, page 10 of 508
Rev. 2.00, 03/04, page 11 of 508
Section 2 CPU
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, see section 3, MCU Operating Modes.
2.1 Features
• Upward-compatible with H8/300 and H8/300H CPUs
Can execute H8/300 and H8/300H CPUs object programs
• General-register architecture
Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
• Sixty-five basic instructions
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indire ct with di spl a cement [@(d:16 ,ER n ) or @( d:32,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx :8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @( d:1 6,PC )]
Memory indirect [@@aa:8]
• 16-Mbyte address space
Program: 16 Mbytes
Data: 16 Mbytes
• High-speed operation
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract: 1 state
8 × 8-bit register-register multiply: 12 states
16 ÷ 8-bit register-register divide: 12 states
16 × 16-bit register-register multiply: 20 states
32 ÷ 16-bit register-register divide: 20 states
CPUS212A_000620020200
Rev. 2.00, 03/04, page 12 of 508
• Two CPU operating modes
Normal mode*
Advanced mode
• Power-down state
Transition to power-down state by SLEEP instruction
CPU clock speed selection
Note: * Normal mode is not available in this LSI.
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.
• Register configuration
The MAC register is supported by the H8S/2600 CPU only.
• Basic instructions
The four instructions MAC, CLRMAC, LDMA C, and STMAC are supported by the H8S/2600
CPU only.
• The number of execution states of the MULX U and MULXS instructions;
Execution States
Instruction Mnemonic H8S/2600 H8S/2000
MULXU MULXU.B Rs, Rd 3 12
MULXU.W Rs, ERd 4 20
MULXS MULXS.B Rs, Rd 4 13
MULXS.W Rs, ERd 5 21
In addition, there are differences in address space, CCR and EXR register functions, and power-
down modes, etc., depending on the model.
Rev. 2.00, 03/04, page 13 of 508
2.1.2 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements:
• More general registers and control registers
Eight 16-bit expande d regist er s, a nd one 8-bit and two 32-bit cont rol registers, have been
added.
• Expanded address space
Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Addressing modes of bit - manipulation instru ct i ons have been enhanced.
Signed multiply and d ivid e instruction s have been added.
Two-bit shift instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
2.1.3 Differences from H8/300H CPU
In comparison to the H8/300H CPU , th e H8S/2000 CPU has the following enhancemen ts:
• Add itional control register
One 8-bit and two 32-bit control registers have been added.
• Enhanced instructions
Addressing modes of bit - manipulation instru ct i ons have been enhanced.
Two-bit shift instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
Rev. 2.00, 03/04, page 14 of 508
2.2 CPU Operating Modes
The H8S/2000 CPU has two operating modes: n ormal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advance d mode supports a maximum 16-Mbyte total address
space. The mode is selected by the mode pins.
2.2.1 Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU.
• Address Space
A maximum address space of 64 kbytes can be accessed.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even
when the corresponding general register (Rn) is used as an address register. If the general
register is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or
post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding
extended register (En) will be affected.
• Instruction Set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
• Exception Vector Table and Memory Indirect Branch Addresses
In normal mode the top area starting at H'0000 is allocated to the exception vecto r table. One
branch address is stored per 16 bits. The exception vector table in normal mode is shown in
figure 2.1. For details of the exception vector table, see section 4, Exception Handling.
The memory indirect addre ssing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode the operand is a 16-bit word operand,
providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000
to H'00FF. Note that this area is also used for the exception vector table.
• Stack Structure
When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC,
condition-cod e register (CCR), and ex tended control register (EXR) is pushed onto the stack in
exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack in
interrupt control mode 0. For details, see section 4, Exception Handling.
Note: Normal mode is not av ailable in this LSI.
Rev. 2.00, 03/04, page 15 of 508
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Exception vector 1
Exception vector 2
Exception vector 3
Exception vector 4
Exception vector 5
Exception vector 6
Exception
vector table
Figure 2.1 Exception Vector Table (Normal Mode)
PC
(16 bits)
EXR*1
Reserved*1,*3
CCR
CCR*3
PC
(16 bits)
SP SP
(SP*2
1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. lgnored when returning.
Notes:
(b) Exception Handling(a) Subroutine Branch
)
Figure 2.2 Stack Structure in Norm al Mo de
Rev. 2.00, 03/04, page 16 of 508
2.2.2 Advanced Mode
• Address Space
Linear access is provided to a 16-Mbyte maximum address space is provided.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers or address registers.
• Instruction Set
All instructions and addressing modes can be used.
• Exception Vector Table and Memory Indirect Branch Addresses
In advanced mode, the top area starting at H'00000000 is allocated to the exception vector
table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is
stored in the lower 24 bits (figu re 2.3). For details of the exception vector table, see section 4,
Exception Handlin g.
H'00000000
H'00000003
H'00000004
H'0000000B
H'0000000C
H'00000010
H'00000008
H'00000007
Reserved
Reserved
Reserved
Reserved
Reserved
Exception vector 1
Exception vector 2
Exception vector 3
Exception vector 4
Exception vector table
Exception vector 5
Figure 2.3 Exception Vector Table (Advanced Mode)
Rev. 2.00, 03/04, page 17 of 508
The memory indirect addre ssing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that cont ains a branch address. In advanced mode the operand is a 32 -bit longword operand,
providing a 32-bit branch address. The upper 8 bits of these 32 bits is a reserved area that is
regarded as H'00 . Branch address es can be stored in the area f r om H'00000000 to H'0000 00FF.
Note that the first part of this range is also the exception vector table.
• Stack Structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC, condition-code register (CCR), and extended control register (EXR) are
pushed onto the stack in excep tion handling, they are stored as shown in figure 2.4. When
EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.
PC
(24 bits)
EXR*
1
Reserved*
1
,*
3
CCR
PC
(24 bits)
SP
SP
(SP *
2
Reserved
(a) Subroutine Branch (b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored when returning.
)
Figure 2.4 Stack Structure in Advanced Mode
Rev. 2.00, 03/04, page 18 of 508
2.3 Address Space
Figure 2.5 shows a memory map for the H8S/2000 CPU. The H8S/2000 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, an d a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces
differ depending on the product. For details on each product, see section 3, MCU Operating
Modes.
H'0000
H'FFFF
H'00000000
H'FFFFFFFF
H'00FFFFFF
64 kbytes 16 Mbytes
Program area
Data area
(b) Advanced Mode
(a) Normal Mode*
Note: * Normal mode is not available in this LSI.
Figure 2.5 Memory Map
Rev. 2.00, 03/04, page 19 of 508
2.4 Register Configuration
The H8S/2000 CPU has the internal registers show n in figure 2.6. There are two types of registers;
general registers and control registers. The control registers are a 24-bit program counter (PC), an
8-bit extended control register (EXR), and an 8-bit condition code register (CCR).
TI2I1I0
EXR
76543210
PC
23 0
15 0 7 0 7 0
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
SP:
PC:
EXR:
T:
I2 to I0:
CCR:
I:
Stack pointer
Program counter
Extended control register
Trace bit
Interrupt mask bits
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7 (SP)
IUIHUNZVC
CCR
76543210
UI:
H:
U:
N:
Z:
V:
C:
General Registers (Rn) and Extended Registers (En)
Control Registers (CR)
[Legend]
----
Figure 2.6 CPU Registers
Rev. 2.00, 03/04, page 20 of 508
2.4.1 General Registers
The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally
identical and can be used as both address registers and data regist ers . When a general register is
used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates
the usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-
bit registers.
The usage of each register can be select ed inde pendently.
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the
stack.
• Address registers
• 32-bit registers
• 16-bit registers • 8-bit registers
ER registers
(ER0 to ER7)
E registers (extended registers)
(E0 to E7)
R registers
(R0 to R7)
RH registers
(R0H to R7H)
RL registers
(R0L to R7L)
Figure 2.7 Usage of General Regi sters
Rev. 2.00, 03/04, page 21 of 508
SP (ER7)
Free area
Stack area
Figure 2.8 Stack Status
2.4.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched , the least significant PC bit is regarded as 0).
2.4.3 Extended Control Register (EXR)
EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions.
When these instructions, except for the STC instruction, are executed, all interrupts including NMI
will be masked for three states after execution is completed.
Bit Bit Name
Initial
Value R/W Description
7 T 0 R/W Trace Bit
When this bit is set to 1, a trace exception is
generated each time an instruction is executed. When
this bit is cleared to 0, instructions are executed in
sequence.
6 to 3 All 1 Reserved
These bits are always read as 1.
2
1
0
I2
I1
I0
1
1
1
R/W
R/W
R/W
These bits designate the interrupt mask level (0 to 7).
For details, see section 5, Interrupt Controller.
Rev. 2.00, 03/04, page 22 of 508
2.4.4 Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Bit Bit Name
Initial
Value R/W Description
7 I 1 R/W Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set
to 1 by hardware at the start of an exception-handling
sequence. For details, see section 5, Interrupt
Controller.
6 UI Undefined R/W User Bit or Interrupt Mask Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions. This bit
cannot be used as an interrupt mask bit in this LSI.
5 H Undefined R/W Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or
NEG.L instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 27, and cleared to 0
otherwise.
4 U Undefined R/W User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
3 N Undefined R/W Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
2 Z Undefined R/W Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
Rev. 2.00, 03/04, page 23 of 508
Bit Bit Name
Initial
Value R/W Description
1 V Undefined R/W Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
0 C Undefined R/W Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
2.4.5 Initial Value s of CP U Registers
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the
trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits
and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized.
The stack pointer should therefore be initialized by an MOV.L in struction executed immediately
after a reset.
Rev. 2.00, 03/04, page 24 of 508
2.5 Data Formats
The H8S/2000 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data . The DA A an d D AS deci mal -a d j ust instructions treat byte data as two
digits of 4-bi t B C D data .
2.5.1 General Register Da ta F or m at s
Figure 2.9 shows the data formats in general registers.
70
70
MSB LSB
MSB LSB
7043
Don't care
Don't care
Don't care
7043
70
Don't care
65432710
70
Don't care 65432710
Don't care
RnH
RnL
RnH
RnL
RnH
RnL
Data Type Register Number Data Format
Byte data
Byte data
4-bit BCD data
4-bit BCD data
1-bit data
1-bit data
Upper Lower
Upper Lower
Figure 2.9 General Register Data Formats (1)
Rev. 2.00, 03/04, page 25 of 508
15 0
MSB LSB
15 0
MSB LSB
31 16
MSB
15 0
LSB
En Rn
ERn:
En:
Rn:
RnH:
RnL:
MSB:
LSB:
General register ER
General register E
General register R
General register RH
General register RL
Most significant bit
Least significant bit
Data Type Data FormatRegister Number
Word data
Word data
Rn
En
Longword data
[Legend]
ERn
Figure 2.9 General Register Data Formats (2)
Rev. 2.00, 03/04, page 26 of 508
2.5.2 Memory Data Formats
Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and
longword data in memory, however word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, an address error does not
occur, however the least sign ificant bit of the address is regarded as 0, so access begins the
preceding address. This also applies to instruction fetches.
When ER7 is used as an address register to access the stack, the ope rand size should be word or
longword.
70
76 543210
MSB LSB
MSB
MSB
LSB
LSB
Data Type Address
1-bit data
Byte data
Word data
Address L
Address L
Address 2M
Address 2M+1
Longword data Address 2N
Address 2N+1
Address 2N+2
Address 2N+3
Data Format
Figure 2.10 Memory Data Formats
Rev. 2.00, 03/04, page 27 of 508
2.6 Instruction Set
The H8S/2000 CPU has 65 instructions. The instructions are classified by function in table 2.1.
Table 2.1 Instruction Classification
Function Instructions Size Types
MOV B/W/L 5 Data transfer
POP*1, PUSH*1 W/L
LDM, STM L
MOVFPE*3, MOVTPE*3 B
ADD, SUB, CMP, NEG B/W/L 19 Arithmetic
operations ADDX, SUBX, DAA, DAS B
INC, DEC B/W/L
ADDS, SUBS L
MULXU, DIVXU, MULXS, DIVXS B/W
EXTU, EXTS W/L
TAS*4 B
Logic operations AND, OR, XOR, NOT B/W/L 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
B 14
Branch Bcc*2, JMP, BSR, JSR, RTS — 5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9
Block data transfer EEPMOV — 1
Total: 65
[Legend]
B: Byte
W: Word
L: Longword
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 2.00, 03/04, page 28 of 508
2.6.1 Table of Instructi ons Cl assified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.
Table 2.2 Operation Notation
Symbol Description
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
EXR Extended control register
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
× Multiplication
÷ Division
∧ Logical AND
∨ Logical OR
⊕ Logical XOR
→ Move
∼ NOT (logical complement)
:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
Rev. 2.00, 03/04, page 29 of 508
Table 2.3 Data Transfer Instructions
Instruction Size* Function
MOV B/W/L (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE B Cannot be used in this LSI.
MOVTPE B Cannot be used in this LSI.
POP W/L @SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH W/L Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.
LDM L @SP+ → Rn (register list)
Pops two or more general registers from the stack.
STM L Rn (register list) → @–SP
Pushes two or more general registers onto the stack.
[Legend]
B: Byte
W: Word
L: Longword
Note: * Refers to the operand size.
Rev. 2.00, 03/04, page 30 of 508
Table 2.4 Arithmetic Operations Instructions (1)
Instruction Size* Function
ADD
SUB
B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register (immediate byte data
cannot be subtracted from byte data in a general register. Use the SUBX
or ADD instruction.)
ADDX
SUBX
B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on byte data in two general
registers, or on immediate data and data in a general register.
INC
DEC
B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
ADDS
SUBS
L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
DAA
DAS
B Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
MULXU B/W Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.
MULXS B/W Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
[Legend]
B: Byte
W: Word
L: Longword
Note: * Refers to the operand size.
Rev. 2.00, 03/04, page 31 of 508
Table 2.4 Arithmetic Operations Instructions (2)
Instruction Size*1 Function
DIVXS B/W Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets CCR bits according to the
result.
NEG B/W/L 0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTU W/L Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS W/L Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
TAS*2 B @ERd – 0, 1 → (<bit 7> of @ERd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
[Legend]
B: Byte
W: Word
L: Longword
Notes: 1. Refers to the operand size.
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 2.00, 03/04, page 32 of 508
Table 2.5 Logic Operations Instructions
Instruction Size* Function
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT B/W/L ∼ (Rd) → (Rd)
Takes the one's complement of general register contents.
[Legend]
B: Byte
W: Word
L: Longword
Note: * Refers to the operand size.
Table 2.6 Shift Instructions
Instruction Size* Function
SHAL
SHAR
B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
1-bit or 2-bit shifts are possible.
SHLL
SHLR
B/W/L Rd (shift) → Rd
Performs a logical shift on general register contents.
1-bit or 2-bit shifts are possible.
ROTL
ROTR
B/W/L Rd (rotate) → Rd
Rotates general register contents.
1-bit or 2-bit rotations are possible.
ROTXL
ROTXR
B/W/L Rd (rotate) → Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotations are possible.
[Legend]
B: Byte
W: Word
L: Longword
Note: * Refers to the operand size.
Rev. 2.00, 03/04, page 33 of 508
Table 2.7 Bit Manipulation Instructions (1)
Instruction Size* Function
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1.
The bit number is specified by 3-bit immediate data or the lower three
bits of a general register.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0.
The bit number is specified by 3-bit immediate data or the lower three
bits of a general register.
BNOT B ∼ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand.
The bit number is specified by 3-bit immediate data or the lower three
bits of a general register.
BTST B ∼ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets
or clears the Z flag accordingly.
The bit number is specified by 3-bit immediate data or the lower three
bits of a general register.
BAND
BIAND
B
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ∧ ∼ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR
BIOR
B
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ∨ ∼ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
[Legend]
B: Byte
Note: * Refers to the operand size.
Rev. 2.00, 03/04, page 34 of 508
Table 2.7 Bit Manipulation Instructions (2)
Instruction Size* Function
BXOR
BIXOR
B
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ⊕ ∼ (<bit-No.> of <EAd>) → C
XORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD
BILD
B
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
∼ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
BIST
B
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
∼ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
[Legend]
B: Byte
Note: * Refers to the operand size.
Rev. 2.00, 03/04, page 35 of 508
Table 2.8 Branch Instructions
Instruction Size Function
Bcc Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic Description Condition
BRA(BT) Always (true) Always
BRN(BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
BCC(BHS) Carry clear
(high or same)
C = 0
BCS(BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z∨(N ⊕ V) = 0
BLE Less or equal Z∨(N ⊕ V) = 1
JMP Branches unconditionally to a specified address.
BSR Branches to a subroutine at a specified address.
JSR Branches to a subroutine at a specified address.
RTS Returns from a subroutine
Rev. 2.00, 03/04, page 36 of 508
Table 2.9 System Control Instructions
Instruction Size* Function
TRAPA Starts trap-instruction exception handling.
RTE Returns from an exception-handling routine.
SLEEP Causes a transition to a power-down state.
LDC B/W (EAs) → CCR, (EAs) → EXR
Moves the source operand contents or immediate data to CCR or EXR.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.
STC B/W CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or memory.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.
ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with immediate data.
ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate data.
XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically XORs the CCR or EXR contents with immediate data.
NOP PC + 2 → PC
Only increments the program counter.
[Legend]
B: Byte
W: Word
Note: * Refers to the operand size.
Rev. 2.00, 03/04, page 37 of 508
Table 2.10 Block Da ta Transfer Instructions
Instruction Size Function
EEPMOV.B
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
2.6.2 Basic Instruction Formats
This LSI's instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (op field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
Figure 2.11 shows examples of instruction formats.
Rev. 2.00, 03/04, page 38 of 508
• Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register Field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instr uct i o ns have two register fields. Some have no register fi eld.
• Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute addre ss, or a displacement.
• Condition Field
Specifies the branching condition of Bcc instructions.
op
op rn rm
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm, etc.
rn rm
op
EA(disp)
op cc EA(disp) BRA d:16, etc.
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
(4) Operation field, effective address extension, and condition field
Figure 2.11 Instruction Formats (Examples)
Rev. 2.00, 03/04, page 39 of 508
2.7 Addressing Modes and Effective Address Calculation
The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except program-
counter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or the absolute addressing mode to specify an operand, and register direct (BSET, BCLR,
BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in
the operand.
Table 2.11 Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)
4 Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8,PC)/@(d:16,PC)
8 Memory indirect @@aa:8
2.7.1 Register Direct—Rn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
2.7.2 Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of the operand on memory. If the address is a program instruction address, the lower 24
bits are valid and the upper 8 bits are all assumed to be 0 (H'00).
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
Rev. 2.00, 03/04, page 40 of 508
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
Register indirect with post-increment—@ERn+: The register field of the instruction code
specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for
longword transfer instruction. For the word or longword transfer instructions, the register value
should be even.
Register indirect with pre-decrement—@-ERn: The value 1, 2, or 4 is subtracted from an
address register (ERn) specified by the register field in the instruction code, and the result is the
address of a memory operand. The result is also stored in the address register. The value
subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer
instruction. For the word or longword transfer instructions, the register value should be even.
2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can
access the entire address space.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
Table 2.12 Absolute Address Access Ranges
Absolute Address Normal Mode* Advanced Mode
8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF Data address
16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
32 bits (@aa:32) H'000000 to H'FFFFFF
Program instruction
address
24 bits (@aa:24)
Note: Normal mode is not available in this LSI.
Rev. 2.00, 03/04, page 41 of 508
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate d ata in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
2.7.7 Program-Cou nter Relative—@(d:8, PC) or @(d:1 6, P C)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address.
Only the lowe r 24 bits of this branch address are valid; the upper 8 bits are all assumed t o be 0
(H'00). The PC value to which the displacement is added is the address of the first byte of the next
instruction, so the po ssible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to
+32768 bytes (–16383 to +16384 word s) from the branch instruction. The resulting value should
be an even number .
2.7.8 Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The upper bits of the absolute address are all assumed to be 0, so th e address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode,
the memory operand is a word operand and the branch address is 16 bits long. In advanced mode,
the memory operand is a longword op erand, the first byte of which is assumed to be 0 (H'00).
Note that the first part of the address range is also the exception vector area. For further details,
see section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)
Note: Normal mode is not av ailable in this LSI.
Rev. 2.00, 03/04, page 42 of 508
Specified
by @aa:8
Specified
by @aa:8
Branch address
Branch address
Reserved
(a) Normal Mode
*
(a) Advanced Mode
Note: * Normal mode is not available in this LSI.
Figure 2.12 Branch Address Specification in Memory Indirect Mode
2.7.9 Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Note: Normal mode is not av ailable in this LSI.
Rev. 2.00, 03/04, page 43 of 508
Table 2.13 Effective Address Calculation (1)
No
1
Offset
1
2
4
r
op
31 0
31 23
2
3Register indirect with displacement
@(d:16,ERn) or @(d:32,ERn)
4
r
op disp
r
op
rm
op rn
31 0
31 0
r
op
Don't care
31 23
31 0
Don't care
31 0
disp
31 0
31 0
31 23
31 0
Don't care
31 23
31 0
Don't care
24
24
24
24
Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
Register direct(Rn)
General register contents
General register contents
General register contents
General register contents
Sign extension
Register indirect(@ERn)
Register indirect with post-increment or
pre-decrement
•Register indirect with post-increment @ERn+
•Register indirect with pre-decrement @-ERn
1, 2, or 4
1, 2, or 4
Operand Size
Byte
Word
Longword
Operand is general register contents.
Rev. 2.00, 03/04, page 44 of 508
Table 2.13 Effective Address Calculation (2)
No
5
op
31 23
31 0
Don't care
abs
@aa:8 7
H'FFFF
op
31 23
31 0
Don't care
@aa:16
op
@aa:24
@aa:32
abs
15
16
31 23
31 0
Don't care
31 23
31 0
Don't care
abs
op
abs
6
op IMM
#xx:8/#xx:16/#xx:32
8
24
24
24
24
Addressing Mode and Instruction Format
Absolute address
Immediate
Effective Address Calculation Effective Address (EA)
Sign extension
Operand is immediate data.
31 23
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
Memory indirect @@aa:8
• Normal mode*
• Advanced mode
31 0
Don't care
23 0
disp
0
31 23
31 0
Don't care
disp
op
23
op
8
abs 31 0
abs
H'000000
7
8
0
15 31 23
31 0
Don't care
15
H'00
16
opabs 31 0
abs
H'000000
7
8
0
31
24
24
24
Note: * Normal mode is not available in this LSI.
PC contents
Sign
extension
Memory contents
Memory contents
Rev. 2.00, 03/04, page 45 of 508
2.8 Processing States
The H8S/2000 CPU has five main processing states: the reset state, exception handling state,
program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state
transitions.
• Reset State
In this state, the CPU and all on-chip peripheral modules are initialized and not operating.
When the RES input goes low, all current processing stops and the CPU enters the reset state.
All interrupts are masked in the reset state. Reset exception handling starts when the RES
signal changes from low to high. For details, see section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
• Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, see section 4, Exception Handling.
• Program Execution State
In this state, the CPU executes program instructions in sequence.
• Bus-Released State
The bus-released state occurs when the bus has been released in response to a bus request from
a bus master other than the CPU.
While the bus is released, the CPU halts operatio ns.
• Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instru ction is executed or the CPU enters hardware standby mode. For further
details, see section 19, Power-Down Modes.
Rev. 2.00, 03/04, page 46 of 508
Program execution state
Exception handling state
Program halt state
Bus-released state
Reset state
*
End of bus
request
Bus
request
Interrupt
request
SLEEP instruction
= High
= High,
= Low
Notes: From any state, a transition to hardware standby mode occurs when goes low.
*From any state except hardware standby mode, a transition to the reset state
occurs whenever goes low. A transition can also be made to the reset state
when the watchdog timer overflows.
Bus
request End of
bus request
Request for
exception
handling
End of
exception
handling
Figure 2.13 State Transitions
2.9 Usage Note
2.9.1 Note on Bit Manipulation Instruc tions
Bit manipulation instructions such as BSET, BCLR, BNOT, BST, and BIST read data in byte
units, perform bit manipulation, and write data in byte units. Thus, care must be taken when these
bit manipulation instructions are executed for a register or port including write-only bits.
In addition, the BCLR instru ction can be used to clear the flag of an internal I/O register. In this
case, if the flag to be cleared has been set by an interrupt processing routine, the flag need not be
read before executing the BCLR instruction.
Rev. 2.00, 03/04, page 47 of 508
Section 3 MCU Operating Modes
3.1 Operating Mode Selection
This LSI supports only operating mode 7, that is, the advanced single- chip mode. The operating
mode is determined by the setting of the mode pins (MD2 and MD0). Only mode 7 can be used in
this LSI. Therefore, all mode pins must be fixed high, as shown in table 3.1. Do not change the
mode pin settings during operation.
Table 3.1 MCU Operating Mode Selection
External Data Bus
MCU
Operating
Mode
MD2
MD0
CPU
Operating
Mode Description On-Chip
ROM Initial
Width Max.
Width
7 1 1 Advanced mode Single-chip mode Enabled
3.2 Register Descriptions
The following registers are related to the operating mode.
• Mode control register (MDCR)
• System control register (SYSCR)
3.2.1 Mode Control Re gi ster ( MD CR )
Bit Bit Name Initial
Value R/W Descriptions
7 1 R/W Reserved
Only 1 should be written to this bit.
6 to 3 All 0 Reserved
These bits are always read as 0 and cannot be
modified.
2 MDS2 R This bit indicates the input level at pin MD2 (the
current operating mode). This bit corresponds to MD2.
MDS2 is read-only bit and this cannot be written to.
The MD2 input level is latched into this bit when
MDCR is read. This latch is canceled by a reset. This
latch is canceled by a reset.
1 1 R Reserved
This bit is always read as 1 and cannot be modified.
Rev. 2.00, 03/04, page 48 of 508
Bit Bit Name Initial
Value R/W Descriptions
0 MDS0 R This bit indicates the input level at pin MD0 (the
current operating mode). This bit corresponds to MD0.
MDS0 is read-only bit and this cannot be written to.
The MD0 input level is latched into this bit when
MDCR is read. This latch is canceled by a reset. This
latch is canceled by a reset.
3.2.2 System Control Register (SYSCR)
SYSCR selects the interrupt control mode and the detected edge for NMI, and enables or disables
on-chip RAM.
Bit Bit Name Initial
Value R/W Descriptions
7 0 R/W Reserved
Only 0 should be written to this bit.
6 0 Reserved
This bit is always read as 0 and cannot be modified.
5
4
INTM1
INTM0
0
0
R/W
R/W
These bits select the control mode of the interrupt
controller. For details of the interrupt control modes,
see section 5.6, Interrupt Control Modes and Interrupt
Operation.
00: Interrupt control mode 0
01: Setting prohibited
10: Interrupt control mode 2
11: Setting prohibited
3 NMIEG 0 R/W NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input
2, 1 All 0 Reserved
These bits are always read as 0 and cannot be
modified.
Rev. 2.00, 03/04, page 49 of 508
Bit Bit Name Initial
Value R/W Descriptions
0 RAME 1 R/W RAM Enable
Enables or disables on-chip RAM. This bit is initialized
when the reset status is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
3.3 Pin Functions in Each Operating Mode
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,
however external addresses cannot be accessed.
All I/O ports are available for use as input-output ports.
Rev. 2.00, 03/04, page 50 of 508
3.4 Address Map
Figure 3.1 shows the address map in each operating mode.
H'000000
H'01FFFF
H'FFE000
H'FFEFBF
H'FFF800
H'FFFFC0
H'FFFFFF
H'FFFF3F
H'FFFF60
H'FFFFBF
On-chip ROM
(F-ZTAT/MASK ROM*)
On-chip RAM
On-chip RAM
Internal I/O registers
Internal I/O registers
ROM: 128 kbytes
RAM: 4 kbytes
Mode 7
Advanced single-chip mode
H8S/2282
H'000000
H'01FFFF
H'00FFFF
H'FFE000
H'FFEFBF
H'FFF800
H'FFFFC0
H'FFFFFF
H'FFFF3F
H'FFFF60
H'FFFFBF
On-chip ROM
(MASK ROM*)
On-chip RAM
On-chip RAM
Internal I/O registers
Internal I/O registers
ROM: 64 kbytes
RAM: 4 kbytes
Mode 7
Advanced single-chip mode
H8S/2281
Figure 3.1 Address Map
Rev. 2.00, 03/04, page 51 of 508
Section 4 Exception Handling
4.1 Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or
interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Exception sources, the stack
structure, and operation of the CPU vary depending on the interrupt control mode. For details on
the interrupt control mode, see section 5, Interrupt Controller.
Table 4.1 Exception Types and Priority
Priority Exception Type Start of Exception Handling
High Reset Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows. The CPU enters
the reset state when the RES pin is low.
Trace*1 Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in the EXR is set to 1
Direct transition Starts when a direction transition occurs as the result of
SLEEP instruction execution.
Interrupt Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued*2
Low Trap instruction*3 Started by execution of a trap instruction (TRAPA)
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in program
execution state.
4.2 Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses. Since the usable modes differ depending on the product, for
details on each product, see section 3, MCU Operating Modes.
Rev. 2.00, 03/04, page 52 of 508
Table 4.2 Exception Handling Vector Table
Vector Address*1
Exception Source Vector Number Normal Mode*2 Advanced Mode
Power-on reset 0 H'0000 to H'0001 H'0000 to H'0003
Manual reset *2 1 H'0002 to H'0003 H'0004 to H'0007
Reserved for system use 2 H'0004 to H'0005 H'0008 to H'000B
3 H'0006 to H'0007 H'000C to H'000F
4 H'0008 to H'0019 H'0010 to H'0013
Trace 5 H'000A to H'000B H'0014 to H'0017
Interrupt (direct transitions)*3 6 H'000C to H'000D H'0018 to H'001B
Interrupt (NMI) 7 H'000E to H'000F H'001C to H'001F
Trap instruction (#0) 8 H'0010 to H'0011 H'0020 to H'0023
(#1) 9 H'0012 to H'0013 H'0024 to H'0027
(#2) 10 H'0014 to H'0015 H'0028 to H'002B
(#3) 11 H'0016 to H'0017 H'002C to H'002F
Reserved for system use 12 H'0018 to H'0019 H'0030 to H'0033
13 H'001A to H'001B H'0034 to H'0037
14 H'001C to H'001D H'0038 to H'003B
15 H'001E to H'001F H'003C to H'003F
External interrupt IRQ0 16 H'0020 to H'0021 H'0040 to H'0043
IRQ1 17 H'0022 to H'0023 H'0044 to H'0047
IRQ2 18 H'0024 to H'0025 H'0048 to H'004B
IRQ3 19 H'0026 to H'0027 H'004C to H'004F
IRQ4 20 H'0028 to H'0029 H'0050 to H'0053
IRQ5 21 H'002A to H'002B H'0054 to H'0057
Reserved for system use 22 H'002C to H'002D H'0058 to H'005B
23 H'002E to H'002F H'005C to H'005F
Internal interrupt*4 24
127
H'0030 to H'0031
H'00FE to H'00FF
H'0060 to H'0063
H'01FC to H'01FF
Notes: 1. Lower 16 bits of the address.
2. Not available in this LSI.
3. For details on direct transitions, see section 19.10, Direct Transitions.
4. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling
Vector Table.
Rev. 2.00, 03/04, page 53 of 508
4.3 Reset
A reset has the highest exception priority.
When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this
LSI is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during
operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the
CPU and the registers of on-chip peripheral modules.
The chip can also be reset by overflow of the watchdog timer. Fo r details see section 9, Watchdog
Timer.
The interrupt control mode is 0 immediately after reset.
4.3.1 Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figure 4.1 and fig ure 4. 2 sh o w exam pl es of t he reset seque nce.
Rev. 2.00, 03/04, page 54 of 508
High
Vector fetch Internal
processing
Prefetch of first
program instruction
(1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
φ
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus
(1)
(2) (4) (6)
(3) (5)
Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)
Rev. 2.00, 03/04, page 55 of 508
RES
RD
HWR, LWR
D15 to D0
High
***
φ
Address bus
Vector fetch
Internal
processing
Prefetch of first
program instruction
(1)
(2) (4) (6)
(3) (5)
(1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
Note: * Three program wait states are inserted.
Figure 4.2 Reset Sequence (Advanced Mode wi th On-chip ROM Disabled: Cannot be Used
in this LSI)
4.3.2 Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrup t requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3 State of On-Chip Peripheral Modules after Reset Release
After reset release, MSTPCRA to MSTPCRD* are initialized to H'3F, H'FF, H'FF, and
B'11****** respectiv ely, and all modules enter modu le stop mode. Consequently, on-chip
peripheral module registers cannot be read or written to. Register reading and writing is enabled
when the module stop mode is exited.
Note: * The initial va lues of bits 5 to 0 in MSTPCRD are undefined.
Rev. 2.00, 03/04, page 56 of 508
4.4 Traces
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows
the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by
clearing the T bit in EXR to 0. The T bit saved on the stack retains its value of 1, and when con trol
is returned from the trace exception handling routine by the RTE instruction, trace mode resumes.
Trace exception handling is not carried out after execution of the RTE instruction.
Interrupts are accepted even within the trace exception handling routine.
Table 4.3 Status of CCR and EXR after Trace Excepti o n Han dl i ng
CCR EXR
Interrupt Control Mode I UI I2 to I0 T
0 Trace exception handling cannot be used.
2 1 0
[Legend]
1: Set to 1
0: Cleared to 0
: Retains value prior to execution
4.5 Interrupts
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt
control modes and can assign interrupts other than NMI to eight priority/mask levels to enable
multiplexed interrupt control. The source to start interrupt exception handling and the vector
address differ depe ndi n g on the pro duct . For detai ls, see se ct i on 5, I nte rr u pt Co ntroller.
Interrupt exception handling is conducted as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended control
register (EXR) are saved to the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution begins from that address.
Rev. 2.00, 03/04, page 57 of 508
4.6 Trap Instruction
Trap instruction excep tion handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
Trap instruction exception handling is conducted as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended control
register (EXR) are saved to the stack.
2. The interrupt mask bit is updated and the T bit is cleared.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.4 shows the status of CCR and EXR after execution of trap in struction exception hand ling.
Table 4.4 Status of CC R and EX R af ter Trap Instruction Exception Handling
CCR EXR
Interrupt Control Mode I UI I2 to I0 T
0 1
2 1 0
[Legend]
1: Set to 1
0: Cleared to 0
: Retains value prior to execution
Rev. 2.00, 03/04, page 58 of 508
4.7 Stack Status after Exception Handling
Figures 4.3 shows the stack after completion of trap instruction exception handling and interrupt
exception hand ling.
CCR
CCR*1
PC (16 bits)
SP
EXR
Reserved*1
CCR
CCR*1
PC (16 bits)
SP
CCR
PC (24 bits)
SP
EXR
Reserved*1
CCR
PC (24 bits)
SP
(a) Normal Modes
*2
(b) Advanced Modes
Interrupt control mode 0 Interrupt control mode 2
Interrupt control mode 0 Interrupt control mode 2
Note: 1.
2.
Ignored on return.
Normal modes are not available in this LSI.
Figure 4.3 Stack Status aft er Excep ti on Han dl i ng
Rev. 2.00, 03/04, page 59 of 508
4.8 Usage Note
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed by word transfer instruction or longword transfer instruction, and
the value of the stack pointer (SP , ER7) sh o uld al way s be kept even. Use the following
instructions to save registers:
PUSH.W Rn (or MOV.W Rn, @-SP)
PUSH.L ERn (or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W Rn (or MOV.W @SP+, Rn)
POP.L ERn (or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of what
happens when the SP value is odd.
SP
CCR:
PC:
R1L:
SP:
Condition code register
Program counter
General register R1L
Stack pointer
CCR
SP
SP R1L H'FFFEFA
H'FFFEFB
H'FFFEFC
H'FFFEFD
H'FFFEFE
H'FFFEFF
PC PC
TRAPA instruction executedSP set to H'FFFEFF
Data saved above SP
MOV.B R1L, @-ER7 executed
Contents of CCR lost
Address
[Legend]
Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.
Figure 4.4 Operation when SP Value Is Odd
Rev. 2.00, 03/04, page 60 of 508
Rev. 2.00, 03/04, page 61 of 508
Section 5 Interrupt Controller
5.1 Features
• Two interrupt control mo des
Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in
the system control register (SYSCR).
• Priorities settable with IPR
An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority
levels can be set for each module for all interrupts except NMI. NMI is assigned the
highest priority level of 8, and can be accepted at all times.
• Independent vector addresses
All interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be identified in the interrupt handling routine.
• Seven external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling
edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level
sensing, can be selected for IRQ5 to IRQ0.
Rev. 2.00, 03/04, page 62 of 508
A block diagram of the interrupt controller is shown in figure 5.1.
SYSCR
NMI input
IRQ input
Internal interrupt
request
WOVI0 to RM0
NMIEG
INTM1, INTM0
NMI input unit
IRQ input unit
ISR
ISCR IER
IPR
Interrupt controller
Priority
determination
Interrupt
request
Vector number
I
I2 to I0
CCR
EXR
CPU
ISCR:
IER:
ISR:
IPR:
SYSCR:
IRQ sense control register
IRQ enable register
IRQ status register
Interrupt priority register
System control register
[Legend]
Figure 5.1 Block Diagram of Interrupt Controller
Rev. 2.00, 03/04, page 63 of 508
5.2 Input/Output Pins
Table 5.1 summarizes the pins of the interrupt contro ller.
Table 5.1 Pin Configuration
Name I/O Function
NMI Input Nonmaskable external interrupt
Rising or falling edge can be selected
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
Input
Input
Input
Input
Input
Input
Maskable external interrupts
Rising, falling, or both edges, or level sensing, can be
selected
5.3 Register Descriptions
The interrupt controller has the follo wing registers. For details system control register (SYSCR),
see section 3.2.2, System Control Register(SYSCR).
• System control register (SYSCR)
• IRQ sense control register H (ISCRH)
• IRQ sense control register L (ISCRL)
• IRQ enable register (IER)
• IRQ status register (ISR)
• Interrupt priority register A (IPRA)
• Interrupt priority register B (IPRB)
• Interrupt priority register C (IPRC)
• Interrupt priority register D (IPRD)
• Interrupt priority register E (IPRE)
• Interrupt priority register F (IPRF)
• Interrupt priority register G (IPRG)
• Interrupt priority register J (IPRJ)
• Interrupt priority register K (IPRK)
• Interrupt priority register M (IPRM)
Rev. 2.00, 03/04, page 64 of 508
5.3.1 Interrupt Priority Registers A to G, J, K, M (IPRA to IPRG, IPRJ, IPRK, IPRM)
The IPR registers set priorities (levels 7 to 0) for interrupts other than NMI. There are ten IPR
registers. The correspondence between interrupt sources and IPR settings is shown in table 5.2.
Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 0 to 2 and 4 to 6 sets the
priority of the corresponding interrupt.
Bit Bit Name
Initial
Value R/W Description
7 0 Reserved
These bits are always read as 0.
6
5
4
IPR6
IPR5
IPR4
1
1
1
R/W
R/W
R/W
Sets the priority of the corresponding interrupt source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
3 0 Reserved
This bit is always read as 0.
2
1
0
IPR2
IPR1
IPR0
1
1
1
R/W
R/W
R/W
Sets the priority of the corresponding interrupt source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
Rev. 2.00, 03/04, page 65 of 508
5.3.2 IRQ Enable Register (IER)
IER controls the enabling and disabling of interrupt requests IRQ5 to IRQ0.
Bit Bit Name
Initial
Value R/W Description
7, 6 All 0 R/W Reserved
Only 0 should be written to these bits.
5 IRQ5E 0 R/W IRQ5 Enable
The IRQ5 interrupt request is enabled when this bit is 1.
4 IRQ4E 0 R/W IRQ4 Enable
The IRQ4 interrupt request is enabled when this bit is 1.
3 IRQ3E 0 R/W IRQ3 Enable
The IRQ3 interrupt request is enabled when this bit is 1.
2 IRQ2E 0 R/W IRQ2 Enable
The IRQ2 interrupt request is enabled when this bit is 1.
1 IRQ1E 0 R/W IRQ1 Enable
The IRQ1 interrupt request is enabled when this bit is 1.
0 IRQ0E 0 R/W IRQ0 Enable
The IRQ0 interrupt request is enabled when this bit is 1.
Rev. 2.00, 03/04, page 66 of 508
5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)
The ISCR registers select the source that generates an interrupt request at pins IRQ5 to IRQ0.
Bit Bit Name
Initial
Value R/W Description
15 to 12 All 0 R/W Reserved
Only 0 should be written to these bits.
11
10
IRQ5SCB
IRQ5SCA
0
0
R/W
R/W
IRQ5 Sense Control B
IRQ5 Sense Control A
00: Interrupt request generated at IRQ5 input level low
01: Interrupt request generated at falling edge of IRQ5
input
10: Interrupt request generated at rising edge of IRQ5
input
11: Interrupt request generated at both falling and rising
edges of IRQ5 input
9
8
IRQ4SCB
IRQ4SCA
0
0
R/W
R/W
IRQ4 Sense Control B
IRQ4 Sense Control A
00: Interrupt request generated at IRQ4 input level low
01: Interrupt request generated at falling edge of IRQ4
input
10: Interrupt request generated at rising edge of IRQ4
input
11: Interrupt request generated at both falling and rising
edges of IRQ4 input
7
6
IRQ3SCB
IRQ3SCA
0
0
R/W
R/W
IRQ3 Sense Control B
IRQ3 Sense Control A
00: Interrupt request generated at IRQ3 input level low
01: Interrupt request generated at falling edge of IRQ3
input
10: Interrupt request generated at rising edge of IRQ3
input
11: Interrupt request generated at both falling and rising
edges of IRQ3 input
Rev. 2.00, 03/04, page 67 of 508
Bit Bit Name
Initial
Value R/W Description
5
4
IRQ2SCB
IRQ2SCA
0
0
R/W
R/W
IRQ2 Sense Control B
IRQ2 Sense Control A
00: Interrupt request generated at IRQ2 input level low
01: Interrupt request generated at falling edge of IRQ2
input
10: Interrupt request generated at rising edge of IRQ2
input
11: Interrupt request generated at both falling and rising
edges of IRQ2 input
3
2
IRQ1SCB
IRQ1SCA
0
0
R/W
R/W
IRQ1 Sense Control B
IRQ1 Sense Control A
00: Interrupt request generated at IRQ1 input level low
01: Interrupt request generated at falling edge of IRQ1
input
10: Interrupt request generated at rising edge of IRQ1
input
11: Interrupt request generated at both falling and rising
edges of IRQ1 input
1
0
IRQ0SCB
IRQ0SCA
0
0
R/W
R/W
IRQ0 Sense Control B
IRQ0 Sense Control A
00: Interrupt request generated at IRQ0 input level low
01: Interrupt request generated at falling edge of IRQ0
input
10: Interrupt request generated at rising edge of IRQ0
input
11: Interrupt request generated at both falling and rising
edges of IRQ0 input
Rev. 2.00, 03/04, page 68 of 508
5.3.4 IRQ Status Register (IS R )
ISR indicates the status of IRQ5 to IRQ0 interrupt requests.
Bit Bit Name
Initial
Value R/W Description
7. 6 All 0 R/W Reserved
Only 0 should be written to these bits.
5
4
3
2
1
0
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
[Setting condition]
When the interrupt source selected by the ISCR
registers occurs
[Clearing conditions]
• Cleared by reading IRQnF flag when IRQnF = 1,
then writing 0 to IRQnF flag
• When interrupt exception handling is executed when
low-level detection is set and IRQn input is high
• When IRQn interrupt exception handling is executed
when falling, rising, or both-edge detection is set
(n = 5 to 0)
Rev. 2.00, 03/04, page 69 of 508
5.4 Interrupt Sources
5.4.1 External Interrupts
There are seven external in terrupts: NMI and IRQ5 to IRQ0. These interrupts can be used to
restore this LSI from software standby mode.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling
edge on the NMI pin.
IRQ5 to IRQ0 Interrupts: Interrupts IRQ5 to IRQ0 are requested by an input signal at pins IRQ5
to IRQ0 Interrupts IRQ5 to IRQ0 have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ5 to IRQ0.
• Enabling or disabling of interrupt requests IRQ5 to IRQ0 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ5 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
The detection of IR Q5 to IR Q0 inte r ru pts d oes n ot de pend on whether the releva nt pi n has been
set for input or output. However, when a pin is used as an external interrupt input pin, do not clear
the corresponding DDR to 0; and use the pin as an I/O pin for another function.
A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 5.2.
IRQn interrupt
request
IRQnE
IRQnF
S
R
Q
Clear signal
Edge / level
detection circuit
IRQnSCA, IRQnSCB
input
Note: n= 5 to 0
Figure 5.2 Block Diagram of Interrupts IRQ5 to IRQ0
Rev. 2.00, 03/04, page 70 of 508
5.4.2 Internal Interrupts
The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1
for a particular interrupt source, an interrupt request is issued to the interrupt controller.
• The interrupt priority level can be set by means of IPR.
5.5 Interrupt Exception Handling Vector Table
Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the v ector number, the higher the priority. Prio rities among
modules can be set by means of the IPR. Modules set at the same priority will conform to their
default priorities. Priorities within a modu le are fixed.
Rev. 2.00, 03/04, page 71 of 508
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities
Vector
Address*
Interrupt
Source Origin of
Interrupt Source Vector
Number Advanced
Mode
IPR
Priority
NMI 7 H'001C High External pin
IRQ0 16 H'0040 IPRA6 to IPRA4
IRQ1 17 H'0044 IPRA2 to IPRA0
IRQ2 18 H'0048 IPRB6 to IPRB4
IRQ3 19 H'004C IPRB6 to IPRB4
IRQ4 20 H'0050 IPRB2 to IPRB0
IRQ5 21 H'0054
22 H'0058 Reserved
for system
use 23 H'005C
Watchdog
timer 0
WOVI0 25 H'0064 IPRD6 to IPRD4
A/D ADI 28 H'0070 IPRE2 to IPRE0
Watchdog
timer 1
WOVI1 29 H'0074 IPRE2 to IPRE0
TPU TGI0A 32 H'0080 IPRF6 to IPRF4
channel 0 TGI0B 33 H'0084
TGI0C 34 H'0088
TGI0D 35 H'008C
TCI0V 36 H'0090
TPU TGI1A 40 H'00A0 IPRF2 to IPRF0
channel 1 TGI1B 41 H'00A4
TCI1V 42 H'00A8
TCI1U 43 H'00AC
TPU TGI2A 44 H'00B0 IPRG6 to IPRG4
channel 2 TGI2B 45 H'00B4
TCI2V 46 H'00B8
TCI2U 47 H'00BC Low
Rev. 2.00, 03/04, page 72 of 508
Vector
Address*
Interrupt
Source Origin of
Interrupt Source Vector
Number Advanced
Mode
IPR
Priority
SCI ERI0 80 H'0140 IPRJ2 to IPRJ0 High
channel 0 RXI0 81 H'0144
TXI0 82 H'0148
TEI0 83 H'014C
SCI ERI1 84 H'0150 IPRK6 to IPRK4
channel 1 RXI1 85 H'0154
TXI1 86 H'0158
TEI1 87 H'015C
PWM CMI1 104 H'01A0 IPRM6 to IPRM4
CMI2 105 H'01A4
106 H'01A8 Reserved
for system
use 107 H'01AC
HCAN 108 H'01B0 IPRM2 to IPRM0
ERS0/OVR0, RM0,
RM1, SLE0
(mailbox 0
reception)
109 H'01B4
Reserved
for system
use
111 H'01BC
Low
Note: * Lower 16 bits of the start address.
Rev. 2.00, 03/04, page 73 of 508
5.6 Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2.
Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is
selected by SYSCR. Table 5.3 shows the differences between interrupt control mode 0 and
interrupt control mode 2.
Table 5.3 Interrupt Control Modes
Interrupt
Control Mode Priority Setting
Registers Interrupt
Mask Bits Description
0 Default I The priorities of interrupt sources are fixed at the
default settings.
Interrupt sources, except for NMI, are masked
by the I bit.
2 IPR I2 to I0 8 priority levels other than NMI can be set with
IPR.
8-level interrupt mask control is performed by
bits I2 to I0.
5.6.1 Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests other than for NMI are masked by the I bit of the
CCR in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case.
1 If an in terrupt sou rce occu rs when the corresponding interrupt enable bit is set to 1 , an
interrupt request is sent to the interrupt controller.
2 If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held
pending. If the I bit is cleared, an interrupt request is accepted.
3 Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to
the priority system is accepted, and other interrupt requests are held pending.
4 When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instructi on has been completed.
5 The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instru ction to be executed after returning from the
interrupt handling rout ine.
6 Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
7 The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Rev. 2.00, 03/04, page 74 of 508
Program execution status
Interrupt generated?
NMI
IRQ0
IRQ1
RM0
I = 0
Save PC and CCR
I ← 1
Read vector address
Branch to interrupt handling routine
Yes
No
Yes
Yes
Yes No
No
No
Yes
Yes
No
Hold
pending
Figure 5.3 Flowchart of Procedure up to Interrupt Acceptance
in Interrupt Control Mode 0
Rev. 2.00, 03/04, page 75 of 508
5.6.2 Interrupt Control Mode 2
In interrupt control mode 2, mask control is applied to eight levels for interrupt requests other than
NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting.
Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.
1 If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt
request is sent to the interrupt controller.
2 When interrupt requests are sent to the interrupt controller, the interrupt with the highest
priority according to the interrupt priority levels set in IPR is selected, and lower-priority
interrupt requests are held pending. If a number of interrupt requests with the same priority are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in tab le 5.3 is selected.
3 Next, the priority of the selected interrupt request is compared with th e interru pt mask level set
in EXR. An interrupt request with a priority no higher than the mask leve l set at that time is
held pending, and only an interrupt request with a priority higher than the interrupt mask level
is accepted.
4 When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instru ct i on has been completed.
5 The PC, CCR, and EXR are saved to the stack area by interrupt exception handling . Th e PC
saved on the stack shows the address of the first instruction to be executed after returning from
the interrupt handling routine.
6 The T bit in EXR is cleared to 0. The in terrupt mask level is rewritten with the priority level of
the accepted interrupt.
If the accepted interrupt is NMI, the interrupt mask level is set to H'7.
7 The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Rev. 2.00, 03/04, page 76 of 508
Yes
Program execution status
Interrupt generated?
NMI
Level 6 interrupt?
Mask level 5
or below?
Level 7 interrupt?
Mask level 6
or below?
Save PC, CCR, and EXR
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Hold
pending
Level 1 interrupt?
Mask level 0?
Yes
Yes
No Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
No
No
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2
5.6.3 Interrupt Exception Handling Sequence
Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
Rev. 2.00, 03/04, page 77 of 508
(14)(12)(10)(6)(4)(2)
(1) (5) (7) (9) (11) (13)
Interrupt service
routine instruction
prefetch
Internal
operation
Vector fetch
Stack
Instruction
prefetch
Internal
operation
Interrupt
acceptance
Interrupt level determination
Wait for end of instruction
Interrupt
request signal
Internal
address bus
Internal
read signal
Internal
write signal
Internal
data bus
φ
(3)
(1)
(2) (4)
(3)
(5)
(7)
Instruction prefetch address (Not executed.
This is the contents of the saved PC, the return address.)
Instruction code (Not executed.)
Instruction prefetch address (Not executed.)
SP-2
SP-4
Saved PC and saved CCR
Vector address
Interrupt handling routine start address (Vector address contents)
Interrupt handling routine start address ((13) = (10)(12))
First instruction of interrupt handling routine
(6) (8)
(9) (11)
(10) (12)
(13)
(14)
(8)
Figure 5.5 Interrupt Exception Handling
Rev. 2.00, 03/04, page 78 of 508
5.6.4 Interrupt Response Times
Table 5.4 shows interrupt response times - the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handlin g routine. The execution status
symbols used in table 5.4 are explained in table 5.5.
This LSI is capable of fast word transfer to on-chip memory, has the program area in on-ch ip
ROM and the stack area in on-chip RAM, enabling high-speed processing.
Table 5.4 Interrupt Response Times
Normal Mode*5 Advanced Mode
No.
Execution Status
Interrupt
control
mode 0
Interrupt
control
mode 2
Interrupt
control
mode 0
Interrupt
control
mode 2
1 Interrupt priority determination*1 3 3 3 3
2 Number of wait states until executing
instruction ends*2
1 to 19 +2·SI1 to 19+2·SI1 to 19+2·SI 1 to 19+2·SI
3 PC, CCR, EXR stack save 2·SK 3·SK 2·SK 3·SK
4 Vector fetch SI S
I 2·SI 2·SI
5 Instruction fetch*3 2·SI 2·SI 2·SI 2·SI
6 Internal processing*4 2 2 2 2
Total (using on-chip memory) 11 to 31 12 to 32 12 to 32 13 to 33
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
5. Not available in this LSI.
Rev. 2.00, 03/04, page 79 of 508
Table 5.5 Number of States in Interrupt Handling Routine Execution Status
Object of Access
External Device *
8 Bit Bus 16 Bit Bus
Symbol Internal
Memory 2-State
Access 3-State
Access 2-State
Access 3-State
Access
Instruction fetch SI 1 4 6+2m 2 3+m
Branch address read SJ
Stack manipulation SK
[Legend]
m: Number of wait states in an external device access.
Note: * Cannot be used in this LSI.
5.7 Usage Notes
5.7.1 Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instru ction.
When an interrupt enable bit is c leared to 0 by an instruction such as BCLR or MOV, and if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 5.6 shows an example in which the TGIEA bit in the TPU's TIER_0 register is cleared to 0.
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
Rev. 2.00, 03/04, page 80 of 508
Internal
address bus
Internal
write signal
φ
TCIEV
TCFV
TCIV
interrupt signal
TIER_0 write cycle by CPU TCIVexception handling
TIER_0 address
Figure 5.6 Contention between Interrupt Generation and Disabling
5.7.2 Instructions that Disable Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions are executed , all interrupts including NMI are disabled an d the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.7.3 When Interrupts Are Disabled
There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level w ith an LDC, ANDC, ORC, or XORC instruction.
Rev. 2.00, 03/04, page 81 of 508
5.7.4 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs bet ween the EEPM OV .B instr u ct i on and the E EPM O V. W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instructio n, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
L1: EEPMOV.W
MOV.W R4,R4
BNE L1
5.7.5 IRQ Interrupts
When the clock is operating, IRQ inputs are accepted in synchronization with the clock input. In
software standby mode, IRQ inputs are accepted asynchronously. For details on the IRQ input
conditions, see section 21 .3.2, Control Signal Timing.
Rev. 2.00, 03/04, page 82 of 508
Rev. 2.00, 03/04, page 83 of 508
Section 6 Bus Controller
The H8S/2600 CPU is driven by a system cloc k, denoted by the symbol φ.
The bus controller controls a memory cycle and a bus cycle. Different methods are used to access
on-chip memory and on-chip peripheral modules. The bus controller also has a bus arbitration
function, and controls the operation of the internal bus master.
6.1 Basic Timing
The period from one rising edge of φ to the next is referred to as a "state." The memory cycle or
bus cycle consists of one, two, three, or four states. Different methods are used to access on-chip
memory, on-chip peripheral modules, and the external address space.
6.1.1 On-Chip Memory Access Timing (ROM, RAM)
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 6.1 shows the on-chip memory access cycle.
T1
φ
Internal address bus
Bus cycle
Address
Read data
Write data
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Read
access
Write
access
Figure 6.1 On-Chip Memory Access Cycle
BSCS209A_000020020200
Rev. 2.00, 03/04, page 84 of 508
6.1.2 On-Chip Peripheral Module Access Timing
The on-chip peripheral modules, except for HCAN, PWM, LCD, Ports H and J, are accessed in
two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O
register being accessed. For details, see section 20, List of Registers. Figure 6.2 shows access
timing for the on -chip peripheral m od ule s.
T1 T2
φ
Internal address bus
Bus cycle
Address
Read data
Write data
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Read
access
Write
access
Figure 6.2 On-Chip Peripheral Module Access Cycle
Rev. 2.00, 03/04, page 85 of 508
6.1.3 On-Chip HCAN Module Access Timing
On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait
states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access
timing is shown in figures 6.3.
T1 T3
T2 Tw Tw T4
φ
Internal address bus
Bus cycle
Address
Read data
Write data
HCAN read signal
Internal data bus
HCAN write signal
Internal data bus
Read
access
Write
access
Figure 6.3 On-Chip HCAN Module Access Cycle (Wait States Inserted)
6.1.4 On-Chip PWM, LCD, Ports H and J Module Access Timing
On-chip PWM, LCD, Ports H and J module access timing is performed in four states. The data bus
width is 16 bits. PWM, LCD, Ports H and J module access timing is shown in fi gure 6.4.
T1 T3
T2 T4
φ
Internal address bus
Bus cycle
Address
Read data
Write data
PWM, LCD, ports H
and J read signal
Internal data bus
PWM, LCD, ports H
and J write signal
Internal data bus
Read
access
Write
access
Figure 6.4 On-Chip PWM, LCD, Ports H and J Module Access Cycle
Rev. 2.00, 03/04, page 86 of 508
Rev. 2.00, 03/04, page 87 of 508
Section 7 I/O Ports
Table 7.1 summarizes the port functions. The pins of each port also have other functions such as
input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes
a data direction register (DDR) that controls input/output, a data register (DR) that stores output
data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR
or DDR register.
Ports 3 and A to C includes an open-drain control register (ODR) that controls the on/off state of
the output buffer PMOS.
All of the I/O ports can drive a single TTL load and 30 pF capacitive load.
Rev. 2.00, 03/04, page 88 of 508
Table 7.1 Port Functions (1)
Port
Description Port and
Other Functions Name Input/Output and
Output Type
P17/TIOCB2/TCLKD
P16/TIOCA2/IRQ1
P15/TIOCB1/TCLKC
P14/TIOCA1/IRQ0
P13/TIOCD0/TCLKB
P12/TIOCC0/TCLKA
P11/TIOCB0
Port 1 General I/O port also
functioning as TPU_0,
TPU_1,and TPU_2 I/O
pins and interrupt input
pins
P10/TIOCA0
P35/SCK1/IRQ5
P34/RxD1
P33/TxD1
P32/SCK0/IRQ4
P31/RxD0
Port 3 General I/O port also
functioning as SCI_0 and
SCI_1 I/O pins and
interrupt input pins
P30/TxD0
Push-pull or open-drain
output type selectable
P47/AN7
P46/AN6
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
Port 4 General input port also
functioning as A/D
converter analog input pins
P40/AN0
PA7/SEG28
PA6/SEG27
PA5/SEG26
PA4/SEG25
PA3/COM4
PA2/COM3
PA1/COM2
Port A General I/O port also
functioning as segment
and common output pins of
LCD
PA0/COM1
Push-pull or open-drain
output type selectable
Rev. 2.00, 03/04, page 89 of 508
Table 7.1 Port Functions (2)
Port
Description Port and
Other Functions Name Input/Output and
Output Type
PB7/SEG20
PB6/SEG19
PB5/SEG18
PB4/SEG17
PB3/SEG16
PB2/SEG15
PB1/SEG14
Port B General I/O port also
functioning as segment
output pins of LCD
PB0/SEG13
Push-pull or open-drain
output type selectable
PC7/SEG12
PC6/SEG11
PC5/SEG10
PC4/SEG9
PC3/SEG8
PC2/SEG7
PC1/SEG6
Port C General I/O port also
functioning as segment
output pins of LCD
PC0/SEG5
Push-pull or open-drain
output type selectable
PD7/SEG4
PD6/SEG3
PD5/SEG2
Port D General I/O port also
functioning as segment
output pins of LCD
PD4/SEG1
PF7/φ
PF6/SEG24
PF5/SEG23
PF4/SEG22
PF3/ADTRG/IRQ3
Port F General I/O port also
functioning as interrupt
input pin, A/D converter
start trigger input pin,
segment output pins of
LCD, and a system clock
output pin
PF2/SEG21
Rev. 2.00, 03/04, page 90 of 508
Table 7.1 Port Functions (3)
Port
Description Port and
Other Functions Name Input/Output and
Output Type
PH7/PWM1H
PH6/PWM1G
PH5/PWM1F
PH4/PWM1E
PH3/PWM1D
PH2/PWM1C
PH1/PWM1B
Port H General I/O port also
functioning as PWM_1
output pins
PH0/PWM1A
PJ7/PWM2H
PJ6/PWM2G
PJ5/PWM2F
PJ4/PWM2E
PJ3/PWM2D
PJ2/PWM2C
PJ1/PWM2B
Port J General I/O port also
functioning as PWM_2
output pins
PJ0/PWM2A
Rev. 2.00, 03/04, page 91 of 508
7.1 Port 1
Port 1 is an 8-bit I/O port. Port 1 has the following registers.
• Port 1 data direction register (P1DDR)
• Port 1 data register (P1DR)
• Port 1 register (PORT1)
7.1.1 Port 1 Data Direction Register (P1DDR)
The individual bits of P1DDR specify input or output for the pins of port 1.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
P17DDR
P16DDR
P15DDR
P14DDR
P13DDR
P12DDR
P11DDR
P10DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
When a pin function is specified to a general I/O port,
setting this bit to 1 makes the corresponding port 1 pin
an output pin, while clearing this bit to 0 makes the pin
an input pin.
7.1.2 Port 1 Data Register (P1DR)
P1DR stores output data for the port 1 pins.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
P17DR
P16DR
P15DR
P14DR
P13DR
P12DR
P11DR
P10DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output data for a pin is stored when the pin function is
specified to a general I/O port.
Rev. 2.00, 03/04, page 92 of 508
7.1.3 Port 1 Register (PORT1)
PORT1 shows port 1 pin states. PORT1 cannot be modified.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P13
P12
P11
P10
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
R
R
R
R
R
R
R
R
If a port 1 read is performed while P1DDR bits are set
to 1, the P1DR values are read. If a port 1 read is
performed while P1DDR bits are cleared to 0, the pin
states are read.
Note: * Determined by the states of pins P17 to P10.
7.1.4 Pin Functions
Port 1 pins also function as I/O pins of TPU_0, TPU_1, and TPU_2, and interrupt input pins. The
correspondence between the register specification and the pin functions is shown below.
Rev. 2.00, 03/04, page 93 of 508
• P17/TIOCB2/TCLKD
The pin function is switched as shown below according to the combination of the TPU channel
2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1
and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0, and bit P17DDR.
TPU channel 2
settings
(1) in table below (2) in table below
P17DDR 0 1
Pin function P17 input P17 output
TIOCB2 output
TIOCB2 input*1
TCLKD input*2
TPU channel 2
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
B'xx00 Other than B'xx00
CCLR1, CCLR0 Other than
B'10
B'10
Output function Output
compare
output
PWM mode
2 output
[Legend]
x: Don't care
Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx while IOB3 = 1.
2. TCLKD input when TPSC2 to TPSC0 = B'111 in TCR_0.
TCLKD input when phase counting mode is set to channel 2.
Rev. 2.00, 03/04, page 94 of 508
• P16/TIOCA2/IRQ1
The pin function is switched as shown below according to the combination of the TPU channel
2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1
and CCLR0 in TCR_2) and bit P16DDR.
TPU channel 2
settings
(1) in table below (2) in table below
P16DDR 0 1
Pin function P16 input P16 output
TIOCA2 output
TIOCA2 input*1
IRQ1 input
TPU channel 2
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011
IOA3 to IOA0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
B'xx00 Other than B'xx00
CCLR1, CCLR0 Other than
B'01
B'01
Output function Output
compare
output
PWM mode
1 output*2
PWM mode
2 output
[Legend]
x: Don't care
Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx while IOA3 = 1.
2. TIOCB2 output disabled.
Rev. 2.00, 03/04, page 95 of 508
• P15/TIOCB1/TCLKC
The pin function is switched as shown below according to the combination of the TPU channel
1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1
and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, and bit P15DDR.
TPU channel 1
settings
(1) in table below (2) in table below
P15DDR — 0 1
Pin function P15 input P15 output
TIOCB1 output
TIOCB1 input*1
TCLKC input*2
TPU channel 1
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
— B'xx00 Other than B'xx00
CCLR1, CCLR0 — — — — Other than
B'10
B'10
Output function — Output
compare
output
— — PWM mode
2 output
—
[Legend]
x: Don't care
Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx while IOB3 to IOB0 = B'10xx.
2. TCLKC input when the bits TPSC2 to TPSC0 in either TCR_0 or TCR_2 are set to
B'110. TCLKC input also when phase counting mode is set for channel 2.
Rev. 2.00, 03/04, page 96 of 508
• P14/TIOCA1/IRQ0
The pin function is switched as shown below according to the combination of the TPU channel
1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1
and CCLR0 in TCR_1) and bit P14DDR.
TPU channel 1
settings
(1) in table below (2) in table below
P14DDR — 0 1
Pin function P14 input P14 output
TIOCA1 output
TIOCA1 input*1
IRQ0 input
TPU channel 1
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011
IOA3 to IOA0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
B'xx00 Other than
B'xx00
Other than B'xx00
CCLR1, CCLR0 — — — — Other than
B'01
B'01
Output function — Output
compare
output
— PWM mode
1 output*2
PWM mode
2 output
—
[Legend]
x: Don't care
Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx while IOA3 to IOA0 = B'10xx.
2. TIOCB1 output disabled.
Rev. 2.00, 03/04, page 97 of 508
• P13/TIOCD0/TCLKB
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIORL_0, and bits
CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, and bit P13DDR.
TPU channel 0
settings
(1) in table below (2) in table below
P13DDR — 0 1
Pin function P13 input P13 output
TIOCD0 output
TIOCD0 input*1
TCLKB input*2
TPU channel 0
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000 B'0010 B'0011
IOD3 to IOD0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
— B'xx00 Other than B'xx00
CCLR2 to
CCLR0
— — — — Other than
B'110
B'110
Output function — Output
compare
output
— — PWM mode
2 output
—
[Legend]
x: Don't care
Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 while IOD3 to IOD0 = B'10xx.
2. TCLKB input when TPSC2 to TPSC0 = B'101 in any of TCR_0 to TCR_2.
TCLKB input also when phase counting mode is set for channel 1.
Rev. 2.00, 03/04, page 98 of 508
• P12/TIOCC0/TCLKA
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2
to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, and bit P12DDR.
TPU channel 0
settings
(1) in table below (2) in table below
P12DDR — 0 1
Pin function P12 input P12 output
TIOCC0 output
TIOCC0 input*1
TCLKA input*2
TPU channel 0
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOC3 to IOC0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
B'xx00 Other than
B'xx00
Other than B'xx00
CCLR2 to CCLR0 — — — — Other than
B'101
B'101
Output function — Output
compare
output
— PWM mode
1 output*3
PWM mode
2 output
—
[Legend]
x: Don't care
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 while IOC3 to IOC0 = B'10xx.
2. TCLKA input when TPSC2 to TPSC0 = B'100 in any of TCR_0 to TCR_2.
TCLKA input also when phase counting mode is set for channel 1.
3. TIOCC0 output disabled. Output disabled and settings (2) effective when BFA = 1 or
BFB = 1 in TMDR_0.
Rev. 2.00, 03/04, page 99 of 508
• P11/TIOCB0
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits
CCLR2 to CCLR0 in TCR_0) and bit P11DDR.
TPU channel 0
settings
(1) in table below (2) in table below
P11DDR — 0 1
Pin function P11 input P11 output
TIOCB0 output
TIOCB0 input
TPU channel 0
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000 B'0010 B'0011
IOB3 to IOB0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
— B'xx00 Other than B'xx00
CCLR2 to CCLR0 — — — — Other than
B'010
B'010
Output function — Output
compare
output
— — PWM mode
2 output
—
[Legend]
x: Don't care
Note: TIOCB0 input when MD3 to MD0 = B'0000 while IOB3 to IOB0 = B'10xx.
Rev. 2.00, 03/04, page 100 of 508
• P10/TIOCA0
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits
CCLR2 to CCLR0 in TCR_0) and bit P10DDR.
TPU channel 0
settings
(1) in table below (2) in table below
P10DDR — 0 1
Pin function P10 input P10 output
TIOCA0 output
TIOCA0 input*
TPU channel 0
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOA3 to IOA0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
B'xx00 Other than
B'xx00
Other than B'xx00
CCLR2 to CCLR0 — — — — Other than
B'001
B'001
Output function — Output
compare
output
— PWM mode
1 output*2
PWM mode
2 output
—
[Legend]
x: Don't care
Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000 while IOA3 to IOA0 = B'10xx.
2. TIOCA0 output disabled.
Rev. 2.00, 03/04, page 101 of 508
7.2 Port 3
Port 3 is a 6-bit I/O port that also has other functions. Port 3 has the following registers.
• Port 3 data direction register (P3DDR)
• Port 3 data register (P3DR)
• Port 3 register (PORT3)
• Port 3 open-drain control register (P3ODR)
7.2.1 Port 3 Data Direction Register (P3DDR)
The individual bits of P3DDR specify input or output for the pins of port 3.
Bit Bit Name Initial
Value R/W Description
7, 6 — Undefined — Reserved
These bits will return undefined values if read.
5
4
3
2
1
0
P35DDR
P34DDR
P33DDR
P32DDR
P31DDR
P30DDR
0
0
0
0
0
0
W
W
W
W
W
W
When a pin function is specified to a general I/O port,
setting this bit to 1 makes the corresponding port 1 pin
an output pin, while clearing this bit to 0 makes the pin
an input pin.
7.2.2 Port 3 Data Register (P3DR)
P3DR stores output data for the port 3 pins.
Bit Bit Name Initial
Value R/W Description
7, 6 — Undefined — Reserved
These bits will return undefined values if read.
5
4
3
2
1
0
P35DR
P34DR
P33DR
P32DR
P31DR
P30DR
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Output data for a pin is stored when the pin function is
specified to a general I/O port.
Rev. 2.00, 03/04, page 102 of 508
7.2.3 Port 3 Register (PORT3)
PORT3 shows port 3 pin states. PORT3 cannot be modified.
Bit Bit Name Initial
Value R/W Description
7, 6 — Undefined — Reserved
These bits will return undefined values if read.
5
4
3
2
1
0
P35
P34
P33
P32
P31
P30
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
R
R
R
R
R
R
If a port 3 read is performed while P3DDR bits are set
to 1, the P3DR values are read. If a port 3 read is
performed while P3DDR bits are cleared to 0, the pin
states are read.
Note: * Determined by the states of pins P35 to P30.
7.2.4 Port 3 Open-Drain Control Register (P3ODR)
P3ODR selects the output type of port 3.
Bit Bit Name Initial
Value R/W Description
7, 6 — Undefined — Reserved
These bits will return undefined values if read.
5
4
3
2
1
0
P35ODR
P34ODR
P33ODR
P32ODR
P31ODR
P30ODR
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Setting this bit to 1 turns off the PMOS of the
corresponding pin, and if the pin function is specified to
output, makes it an open-drain output pin, while clearing
this bit to 0 makes it a push-pull output pin.
Rev. 2.00, 03/04, page 103 of 508
7.2.5 Pin Functions
Port 3 pins also function as I/O pins for SCI_0 and SCI_1, and interrupt input pins. The
correspondence between the register specification and the pin functions is shown below.
• P35/SCK1/IRQ5
The pin function is switched as shown below according to the combination of bit C/A in SMR
and bits CKE0 and CKE1 in SCR of SCI_1, and bit P35DDR.
CKE1 0 1
C/A 0 1 —
CKE0 0 1 — —
P35DDR 0 1 — — —
P35 input P35 output SCK1 output SCK1 output SCK1 input Pin function
IRQ5 input
• P34/RxD1
The pin function is switched as shown below according to the combination of bit RE in SCR of
SCI_1 and bit P34DDR.
RE 0 1
P34DDR 0 1 —
Pin function P34 input P34 output RxD1 input
• P33/TxD1
The pin function is switched as shown below according to the combination of bit TE in SCR of
SCI_1 and bit P33DDR.
TE 0 1
P33DDR 0 1 —
Pin function P33 input P33 output TxD1 output
Rev. 2.00, 03/04, page 104 of 508
• P32/SCK0/IRQ4
The pin function is switched as shown below according to the combination of bit C/A in SMR
and bits CKE0 and CKE1 in SCR of SCI_0, and bit P32DDR.
CKE1 0 1
C/A 0 1 —
CKE0 0 1 — —
P32DDR 0 1 — — —
P32 input P32 output SCK0 output SCK0 output SCK0 input Pin function
IRQ4 input
• P31/RxD0
The pin function is switched as shown below according to the combination of bit RE in SCR of
SCI_0 and bit P31DDR.
RE 0 1
P31DDR 0 1 —
Pin function P31 input P31 output RxD0 input
• P30/TxD0
The pin function is switched as shown below according to the combination of bit TE in SCR of
SCI_0 and bit P30DDR.
TE 0 1
P30DDR 0 1 —
Pin function P30 input P30 output TxD0 input
Rev. 2.00, 03/04, page 105 of 508
7.3 Port 4
Port 4 is an 8-bit I/O port that also functions as an A/D converter analog input port. Port 4 has the
following register.
• Port 4 register (PORT4)
7.3.1 Port 4 Register (PORT4)
PORT4 shows port 4 pin states. PORT4 cannot be modified.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
P47
P46
P45
P44
P43
P42
P41
P40
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
R
R
R
R
R
R
R
R
The pin states are always read when a port 4 read is
performed.
Note: * Determined by the states of pins P47 to P40.
Rev. 2.00, 03/04, page 106 of 508
7.4 Port A
Port A is an 8-bit I/O port that also has other functions. Port A has the following registers.
• Port A data direction register (PADDR)
• Port A data register (PADR)
• Port A register (PORTA)
• Port A open-drain control register (PAODR)
7.4.1 Port A Data Direction Register (PADDR)
The individual bits of PADDR specify input or output for the pins of port A.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PA7DDR
PA6DDR
PA5DDR
PA4DDR
PA3DDR
PA2DDR
PA1DDR
PA0DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
When a pin function is specified to a general I/O port,
setting this bit to 1 makes the corresponding port A pin
an output pin, while clearing this bit to 0 makes the pin
an input pin.
7.4.2 Port A Data Register (PADR)
PADR stores output data f or t he po rt A pi ns.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PA7DR
PA6DR
PA5DR
PA4DR
PA3DR
PA2DR
PA1DR
PA0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output data for a pin is stored when the pin function is
specified to a general I/O port.
Rev. 2.00, 03/04, page 107 of 508
7.4.3 Port A Register (PORTA)
PORTA shows port A pin states. PORTA cannot be modified.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
R
R
R
R
R
R
R
R
If a port A read is performed while PADDR bits are set
to 1, the PADR values are read. If a port A read is
performed while PADDR bits are cleared to 0, the pin
states are read.
Note: * Determined by the states of pins PA7 to PA0.
7.4.4 Port A Open Drain Control Register (PAODR)
PAODR selects the output type of port A.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PA7ODR
PA6ODR
PA5ODR
PA4ODR
PA3ODR
PA2ODR
PA1ODR
PA0ODR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Setting this bit to 1 turns off the PMOS of the
corresponding pin, and if the pin function is specified to
output, makes it an open-drain output pin, while clearing
this bit to 0 makes it a push-pull output pin.
Rev. 2.00, 03/04, page 108 of 508
7.4.5 Pin Functions
Port A pins also function as segment output pins and common output pins of the LCD. The
correspondence between the register specification and the pin functions is shown below.
• PA7/SEG28, PA6/S E G 2 7, PA5/SEG2 6, P A4/ SEG25
The pin function is switched as shown below according to the combination of bits SGS3 to
SGS0 in LPCR of the LCD and bit PAnDD R.
SGS3 to SGS0 0000 Other than 0000
PAnDDR 0 1 —
Pin function PA7 to PA4 input PA7 to PA4 output SEG28 to SEG25 output
n = 7 to 4
• PA3/COM4, PA2/COM3, PA1/COM2, PA0/COM1
The pin function is switched as shown below according to the comb ination of bits SGS3 to
SGS0 in LPCR of the LCD and bit PAnDD R.
SGS3 to SGS0 0000 Other than 0000
PAnDDR 0 1 —
Pin function PA3 to PA0 input PA3 to PA0 output COM4 to COM1 output
n = 3 to 0
Rev. 2.00, 03/04, page 109 of 508
7.5 Port B
Port B is an 8-bit I/O port that also has other functions. Port B has the following registers.
• Port B data direction register (PBD DR )
• Port B data register (PBDR)
• Port B register (PORTB)
• Port B open-drain control register (PBODR)
7.5.1 Port B Data Direction Register (PBDDR)
The individual bits of PBDDR specify input or output for the pins of port B.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PB7DDR
PB6DDR
PB5DDR
PB4DDR
PB3DDR
PB2DDR
PB1DDR
PB0DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
When a pin function is specified to a general I/O port,
setting this bit to 1 makes the corresponding port 1 pin
an output pin, while clearing this bit to 0 makes the pin
an input pin.
7.5.2 Port B Data Register (PBDR)
PBDR stores output data for the port B pins.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PB7DR
PB6DR
PB5DR
PB4DR
PB3DR
PB2DR
PB1DR
PB0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output data for a pin is stored when the pin function is
specified to a general I/O port.
Rev. 2.00, 03/04, page 110 of 508
7.5.3 Port B Register (PORTB)
PORTB shows port B pin states. PORTB cannot be modified.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
R
R
R
R
R
R
R
R
If a port B read is performed while PBDDR bits are set
to 1, the PBDR values are read. If a port B read is
performed while PBDDR bits are cleared to 0, the pin
states are read.
Note: * Determined by the states of pins PB7 to PB0.
7.5.4 Port B Open Drain Control Register (PBODR)
PBODR selects the output type of port B.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PB7ODR
PB6ODR
PB5ODR
PB4ODR
PB3ODR
PB2ODR
PB1ODR
PB0ODR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Setting this bit to 1 turns off the PMOS of the
corresponding pin, and if the pin function is specified to
output, makes it an open-drain output pin, while clearing
this bit to 0 makes it a push-pull output pin.
Rev. 2.00, 03/04, page 111 of 508
7.5.5 Pin Functions
Port B pins also function as segment output pins of the LCD. The correspondence between the
register specification and the pin functions is shown below.
• PB7/SEG20, PB6/SEG19, PB5/SEG18, PB4/SEG17
The pin function is switched as shown below according to the combination of bits SGS3 to
SGS0 in LPCR of the LCD and bit PBnDDR.
SGS3 to SGS0 0000 or 0001 Other than 0000 or 0001
PBnDDR 0 1 —
Pin function PB7 to PB4 input PB7 to PB4 output SEG20 to SEG17 output
n = 7 to 4
• PB3/SEG16, PB2/SEG15, PB1/SEG14, PB0/SEG13
The pin function is switched as shown below according to the combination of bits SGS3 to
SGS0 in LPCR of the LCD and bit PBnDDR.
SGS3 to SGS0 0000 to 0010 Other than 0000 to 0010
PBnDDR 0 1 —
Pin function PB3 to PB0 input PB3 to PB0 output SEG16 to SEG13 output
n = 3 to 0
Rev. 2.00, 03/04, page 112 of 508
7.6 Port C
Port C is an 8-bit I/O port that also has other functions. Port C has the following registers.
• Port C data direction register (PCD DR )
• Port C data register (PCDR)
• Port C register (PORTC)
• Port C open-drain control register (PCODR)
7.6.1 Port C Data Direction Register (PCDDR)
The individual bits of PCDDR specify input or output for the pins of port C.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PC7DDR
PC6DDR
PC5DDR
PC4DDR
PC3DDR
PC2DDR
PC1DDR
PC0DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
When a pin function is specified to a general I/O port,
setting this bit to 1 makes the corresponding port 1 pin
an output pin, while clearing this bit to 0 makes the pin
an input pin.
7.6.2 Port C Data Register (PCDR)
PCDR stores output data for the port C pins.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PC7DR
PC6DR
PC5DR
PC4DR
PC3DR
PC2DR
PC1DR
PC0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output data for a pin is stored when the pin function is
specified to a general I/O port.
Rev. 2.00, 03/04, page 113 of 508
7.6.3 Port C Register (PORTC)
PORTC shows port C pin states. PORTC cannot be modified.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
R
R
R
R
R
R
R
R
If a port C read is performed while PCDDR bits are set
to 1, the PCDR values are read. If a port C read is
performed while PCDDR bits are cleared to 0, the pin
states are read.
Note: * Determined by the states of pins PC7 to PC0.
7.6.4 Port C Open Drain Control Register (PCODR)
PCODR selects the output type of port C.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PC7ODR
PC6ODR
PC5ODR
PC4ODR
PC3ODR
PC2ODR
PC1ODR
PC0ODR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Setting this bit to 1 turns off the PMOS of the
corresponding pin, and if the pin function is specified to
output, makes it an open-drain output pin, while clearing
this bit to 0 makes it a push-pull output pin.
Rev. 2.00, 03/04, page 114 of 508
7.6.5 Pin Functions
Port C pins also function as segment output pins of the LCD. The correspondence between the
register specification and the pin functions is shown below.
• PC7/SEG12, PC6/SEG11, PC5/SEG10, PC4/SEG9
The pin function is switched as shown below according to the comb ination of bits SGS3 to
SGS0 in LPCR of the LCD and bit PCnDDR.
SGS3 to SGS0 0000 to 0011 Other than 0000 to 0011
PCnDDR 0 1 —
Pin function PC7 to PC4 input PC7 to PC4 output SEG12 to SEG9 output
n = 7 to 4
• PC3/SEG8, PC2/SEG7, PC1/SEG6, PC0/SEG5
The pin function is switched as shown below according to the combination of bits SGS3 to
SGS0 in LPCR of the LCD and bit PCnDDR.
SGS3 to SGS0 0000 to 0100 Other than 0000 to 0100
PCnDDR 0 1 —
Pin function PC3 to PC0 input PC3 to PC0 output SEG8 to SEG5 output
n = 3 to 0
Rev. 2.00, 03/04, page 115 of 508
7.7 Port D
Port D is a 4-bit I/O port that also has other functions. Port D has the following registers.
• Port D data direction register (PDDDR)
• Port D data register (PDDR)
• Port D register (PORTD)
7.7.1 Port D Data Direction Register (PDDDR)
The individual bits of PDDDR specify input or output for the pins of port D.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
PD7DDR
PD6DDR
PD5DDR
PD4DDR
0
0
0
0
W
W
W
W
When a pin function is specified to a general I/O port,
setting this bit to 1 makes the corresponding port 1 pin
an output pin, while clearing this bit to 0 makes the pin
an input pin.
3 to 0 — Undefined — Reserved
These bits will return undefined values if read.
7.7.2 Port D Data Register (PDDR)
PDDR stores output data f or t he po rt D pi ns.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
PD7DR
PD6DR
PD5DR
PD4DR
0
0
0
0
R/W
R/W
R/W
R/W
Output data for a pin is stored when the pin function is
specified to a general I/O port.
3 to 0 — Undefined — Reserved
These bits will return undefined values if read.
Rev. 2.00, 03/04, page 116 of 508
7.7.3 Port D Register (PORTD)
PORTD shows port D pin states. PORTD cannot be modified.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
PD7
PD6
PD5
PD4
Undefined*
Undefined*
Undefined*
Undefined*
R
R
R
R
If a port D read is performed while PDDDR bits are set
to 1, the PDDR values are read. If a port D read is
performed while PDDDR bits are cleared to 0, the pin
states are read.
3 to 0 — Undefined — Reserved
These bits will return undefined values if read.
Note: * Determined by the states of pins PD7 to PD4.
7.7.4 Pin Functions
Port D pins also function as segment output pins of the LCD. The correspondence between the
register specification and the pin functions is shown below.
• PD7/SEG4, PD6/SEG3, PD5/S EG2, PD4/SEG1
The pin function is switched as shown below according to the comb ination of bits SGS3 to
SGS0 in LPCR of the LCD and bit PDnDD R.
SGS3 to SGS0 Other than 0110 0110
PDnDDR 0 1 —
Pin function PD7 to PD4 input PD7 to PD4 output SEG4 to SEG1 output
n = 7 to 4
Rev. 2.00, 03/04, page 117 of 508
7.8 Port F
Port F is an 8-bit I/O port that also has other functions. Port F has the following registers.
• Port F data direction register (PF DDR)
• Port F data register (PFDR)
• Port F register (PORTF)
7.8.1 Port F Data Direction Register (PFDDR)
The individual bits of PFDDR specify input or output for the pins of port F.
Bit Bit Name Initial
Value R/W Description
7 PF7DDR 0 W When the pin function is specified to a general I/O port,
setting this bit to 1 makes the PF7 pin the φ output pin,
while clearing this bit to 0 makes the pin an input pin.
6
5
4
3
2
PF6DDR
PF5DDR
PF4DDR
PF3DDR
PF2DDR
0
0
0
0
0
W
W
W
W
W
When a pin function is specified to a general I/O port,
setting this bit to 1 makes the corresponding port F pin
an output pin, while clearing this bit to 0 makes the pin
an input pin.
1, 0 — Undefined — Reserved
These bits will return undefined values if read.
Rev. 2.00, 03/04, page 118 of 508
7.8.2 Port F Data Register (PFDR)
PFDR stores output data for the port F pins.
Bit Bit Name Initial
Value R/W Description
7 — 0 R/W Reserved
Only 0 should be written to this bit.
6
5
4
3
2
PF6DR
PF5DR
PF4DR
PF3DR
PF2DR
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Output data for a pin is stored when the pin function is
specified to a general I/O port.
1, 0 — Undefined — Reserved
These bits will return undefined values if read.
7.8.3 Port F Register (PORTF)
PORTF shows port F pin states. PORTF cannot be modified.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
PF7
PF6
PF5
PF4
PF3
PF2
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
R
R
R
R
R
R
If a port F read is performed while PFDDR bits are set
to 1, the PFDR values are read. If a port F read is
performed while PFDDR bits are cleared to 0, the pin
states are read.
1, 0 — Undefined — Reserved
These bits will return undefined values if read.
Note: * Determined by the states of pins PF7 to PF2.
Rev. 2.00, 03/04, page 119 of 508
7.8.4 Pin Functions
Port F pins also function as an external interrupt input pin, an A/D converter start trigger input pin,
segment output pins of the LCD, and a system clock output pin. The correspondence between the
register specification and the pin functions is shown below.
• PF7/φ
The pin function is switched as shown below according to bit PF7DDR.
PF7DDR 0 1
Pin function PF7 input φ output
• PF6/SEG24
The pin function is switched as shown below according to the combination of bits SGS3 to
SGS0 in LPCR of the LCD and bit PF6DDR.
SGS3 to SGS0 0000 Other than 0000
PF6DDR 0 1 —
Pin function PF6 input PF6 output SEG24 output
• PF5/SEG23
The pin function is switched as shown below according to the combination of bits SGS3 to
SGS0 in LPCR of the LCD and bit PF5DDR.
SGS3 to SGS0 0000 Other than 0000
PF5DDR 0 1 —
Pin function PF5 input PF5 output SEG23 output
• PF4/SEG22
The pin function is switched as shown below according to the combination of bits SGS3 to
SGS0 in LPCR of the LCD and bit PF4DDR.
SGS3 to SGS0 0000 Other than 0000
PF4DDR 0 1 —
Pin function PF4 input PF4 output SEG22 output
Rev. 2.00, 03/04, page 120 of 508
• PF3/ADTRG/IRQ3
The pin function is switched as shown below according to the combination of bits TRGS1 and
TRGS0 in ADCR of the A/D converter and bit PF3DDR.
PF3DDR 0 1
PF3 input PF3 output
ADTRG input*
Pin function
IRQ3 input
Note: When TRGS1 = 1 and TRGS0 = 1, it becomes ADTRG input.
• PF2/SEG21
The pin function is switched as shown below according to the comb ination of bits SGS3 to
SGS0 in LPCR of the LCD and bit PF2DDR.
SGS3 to SGS0 0000 Other than 0000
PF2DDR 0 1 —
Pin function PF2 input PF2 output SEG21 output
Rev. 2.00, 03/04, page 121 of 508
7.9 Port H
Port H is an 8-bit I/O port that also has other functions. Port H has the following registers.
• Port H data direction register (PHDDR)
• Port H data register (PHDR)
• Port H register (PORTH)
7.9.1 Port H Data Direction Register (PHDDR)
The individual bits of PHDDR specify input or output for the pins of port H.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PH7DDR
PH6DDR
PH5DDR
PH4DDR
PH3DDR
PH2DDR
PH1DDR
PH0DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
When a pin function is specified to a general I/O port,
setting this bit to 1 makes the corresponding port 1 pin
an output pin, while clearing this bit to 0 makes the pin
an input pin.
7.9.2 Port H Data Register (PHDR)
PHDR stores output data f or t he po rt H pi ns.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PH7DR
PH6DR
PH5DR
PH4DR
PH3DR
PH2DR
PH1DR
PH0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output data for a pin is stored when the pin function is
specified to a general I/O port.
Rev. 2.00, 03/04, page 122 of 508
7.9.3 Port H Register (PORTH)
PORTH shows port H pin states. PORTH cannot be modified.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
R
R
R
R
R
R
R
R
If a port H read is performed while PHDDR bits are set
to 1, the PHDR values are read. If a port H read is
performed while PHDDR bits are cleared to 0, the pin
states are read.
Note: * Determined by the states of pins PH7 to PH0.
7.9.4 Pin Functions
Port H pins also function as the PWM_1 output pins. The correspondence between the register
specification and th e pin functions is shown below.
• PH7/PWM1H
The pin function is switched as shown below according to the combination of bit OE1H in
PWOCR_1 of PWM_1 and bit PH7DDR .
OE1H 0 1
PH7DDR 0 1 —
Pin function PH7 input PH7 output PWM1H output
• PH6/PWM1G
The pin function is switched as shown below according to the combination of bit OE1G in
PWOCR_1 of PWM_1 and bit PH6DDR .
OE1G 0 1
PH6DDR 0 1 —
Pin function PH6 input PH6 output PWM1G output
Rev. 2.00, 03/04, page 123 of 508
• PH5/PWM1F
The pin function is switched as shown below according to the combination of bit OE1F in
PWOCR_1 of PWM_1 and bit PH5DDR .
OE1F 0 1
PH5DDR 0 1 —
Pin function PH5 input PH5 output PWM1F output
• PH4/PWM1E
The pin function is switched as shown below according to the combination of bit OE1E in
PWOCR_1 of PWM_1 and bit PH4DDR .
OE1E 0 1
PH4DDR 0 1 —
Pin function PH4 input PH4 output PWM1E output
• PH3/PWM1D
The pin function is switched as shown below according to the combination of bit OE1D in
PWOCR_1 of PWM_1 and bit PH3DDR .
OE1D 0 1
PH3DDR 0 1 —
Pin function PH3 input PH3 output PWM1D output
• PH2/PWM1C
The pin function is switched as shown below according to the combination of bit OE1C in
PWOCR_1 of PWM_1 and bit PH2DDR .
OE1C 0 1
PH2DDR 0 1 —
Pin function PH2 input PH2 output PWM1C output
Rev. 2.00, 03/04, page 124 of 508
• PH1/PWM1B
The pin function is switched as shown below according to the combination of bit OE1B in
PWOCR_1 of PWM_1 and bit PH1DDR .
OE1B 0 1
PH1DDR 0 1 —
Pin function PH1 input PH1 output PWM1B output
• PH0/PWM1A
The pin function is switched as shown below according to the combination of bit OE1A in
PWOCR_1 of PWM_1 and bit PH0DDR .
OE1A 0 1
PH0DDR 0 1 —
Pin function PH0 input PH0 output PWM1A output
Rev. 2.00, 03/04, page 125 of 508
7.10 Port J
Port J is an 8-bit I/O port that also has other functions. Port J has the following registers.
• Port J data direction register (PJDDR)
• Port J data register (PJDR)
• Port J register (PORTJ)
7.10.1 Port J Data Direction Register (PJDDR)
The individual bits of PJDDR specify input or output for the pins of port J.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PJ7DDR
PJ6DDR
PJ5DDR
PJ4DDR
PJ3DDR
PJ2DDR
PJ1DDR
PJ0DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
When a pin function is specified to a general I/O port,
setting this bit to 1 makes the corresponding port 1 pin
an output pin, while clearing this bit to 0 makes the pin
an input pin.
7.10.2 Port J Data Register (PJDR)
PJDR stores out p ut data f or the po rt J pin s.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PJ7DR
PJ6DR
PJ5DR
PJ4DR
PJ3DR
PJ2DR
PJ1DR
PJ0DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output data for a pin is stored when the pin function is
specified to a general I/O port.
Rev. 2.00, 03/04, page 126 of 508
7.10.3 Port J Register (PORTJ)
PORTJ shows port J pin states. PORTJ cannot be modified.
Bit Bit Name Initial
Value R/W Description
7
6
5
4
3
2
1
0
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
Undefined*
R
R
R
R
R
R
R
R
If a port J read is performed while PJDDR bits are set to
1, the PJDR values are read. If a port J read is
performed while PJDDR bits are cleared to 0, the pin
states are read.
Note: * Determined by the states of pins PJ7 to PJ0.
7.10.4 Pin Functions
Port J pins also function as the PWM_2 output pins. The correspondence between the register
specification and th e pin functions is shown below.
• PJ7/PWM2H
The pin function is switched as shown below according to the combination of bit OE2H in
PWOCR_2 of PWM_2 and bit PJ7DDR .
OE2H 0 1
PJ7DDR 0 1 —
Pin function PJ7 input PJ7 output PWM2H output
• PJ6/PWM2G
The pin function is switched as shown below according to the combination of bit OE2G in
PWOCR_2 of PWM_2 and bit PJ6DDR .
OE2G 0 1
PJ6DDR 0 1 —
Pin function PJ6 input PJ6 output PWM2G output
Rev. 2.00, 03/04, page 127 of 508
• PJ5/PWM2F
The pin function is switched as shown below according to the combination of bit OE2F in
PWOCR_2 of PWM_2 and bit PJ5DDR .
OE2F 0 1
PJ5DDR 0 1 —
Pin function PJ5 input PJ5 output PWM2F output
• PJ4/PWM2E
The pin function is switched as shown below according to the combination of bit OE2E in
PWOCR_2 of PWM_2 and bit PJ4DDR .
OE2E 0 1
PJ4DDR 0 1 —
Pin function PJ4 input PJ4 output PWM2E output
• PJ3/PWM2D
The pin function is switched as shown below according to the combination of bit OE2D in
PWOCR_2 of PWM_2 and bit PJ3DDR .
OE2D 0 1
PJ3DDR 0 1 —
Pin function PJ3 input PJ3 output PWM2D output
• PJ2/PWM2C
The pin function is switched as shown below according to the combination of bit OE2C in
PWOCR_2 of PWM_2 and bit PJ2DDR .
OE2C 0 1
PJ2DDR 0 1 —
Pin function PJ2 input PJ2 output PWM2C output
Rev. 2.00, 03/04, page 128 of 508
• PJ1/PWM2B
The pin function is switched as shown below according to the combination of bit OE2B in
PWOCR_2 of PWM_2 and bit PJ1DDR .
OE2B 0 1
PJ1DDR 0 1 —
Pin function PJ1 input PJ1 output PWM2B output
• PJ0/PWM2A
The pin function is switched as shown below according to the combination of bit OE2A in
PWOCR_2 of PWM_2 and bit PJ0DDR .
OE2A 0 1
PJ0DDR 0 1 —
Pin function PJ0 input PJ0 output PWM2A output
Rev. 2.00, 03/04, page 129 of 508
7.11 Pin Switch Function
The upper or lower 4 bits of port H and port J are switched according to the combination of the
TRPB and TRPA bits in TRPRT.
7.11.1 Transport Register (TRPR T )
TRPRT specifies the switch of pin functions in port H and port J by the combination of the TRPB
and TRPA bits.
Bit Bit Name
Initial
Value R/W Description
7 to 2 — Undefined — Reserved
These bits will return undefined values if read.
1
0
TRPB
TRPA
0
0
R/W
R/W
The pin functions in ports H and J are switched as
shown below according to the combination of the TRPB
and TRPA bits.
00: Initial value
01: The pin functions of PH3 to PH0 are switched to
those of PJ3 to PJ0.
10: The pin functions of PH7 to PH4 are switched to
those of PJ7 to PJ4.
11: The pin functions of PH7 to PH4 and PH3 to PH0
are switched to those of PJ7 to PJ4 and PJ3 to
PJ0, respectively.
7.11.2 Reading of Port Registers by Swit ching the Pin
In reading PORTH and PORTJ, the pins to be read will differ by the TRPB and TRPA bits in
TRPRT. Table 7.2 lists the pins of registers to be read by switching the pins.
For the status of the pins to be read in PORTH and PORTJ, see section 7.9.3, Port H Register
(PORTH), and section 7.10.3, Port J Register (PORTJ). Set TRPRT before writing to data
direction registers (PHDDR and PJDDR) and data registers (PHDR and PJDR).
Rev. 2.00, 03/04, page 130 of 508
Table 7.2 Pins of Registers to be Read and PWM Output by Switching Pins
TRPB
7
Bit
Read
Data
6543210
PH7 input/
PWM1H/
PHDR7
PH6 input/
PWM1G/
PHDR6
PH5 input/
PWM1F/
PHDR5
PH4 input/
PWM1E/
PHDR4
PH3 input/
PWM1D/
PHDR3
PH2 input/
PWM1C/
PHDR2
PH1 input/
PWM1B/
PHDR1
PH0 input/
PWM1A/
PHDR0
01
10
11
TRPA Port H Port J
46
Pin No.
Pin
State
45 44 43 40 39 38 37
PH7 input/
PWM1H/
PHDR7
PH6 input/
PWM1G/
PHDR6
PH5 input/
PWM1F/
PHDR5
PH4 input/
PWM1E/
PHDR4
PH3 input/
PWM1D/
PHDR3
PH2 input/
PWM1C/
PHDR2
PH1 input/
PWM1B/
PHDR1
PH0 input/
PWM1A/
PHDR0
PJ7 input/
PWM2H/
PJDR7
PJ6 input/
PWM2G/
PJDR6
PJ5 input/
PWM2F/
PJDR5
PJ4 input/
PWM2E/
PJDR4
PJ3 input/
PWM2D/
PJDR3
PJ2 input/
PWM2C/
PJDR2
PJ1 input/
PWM2B/
PJDR1
PJ0 input/
PWM2A/
PJDR0
56 55 54 53 50 49 48 47
PJ7 input/
PWM2H/
PJDR7
PJ6 input/
PWM2G/
PJDR6
PJ5 input/
PWM2F/
PJDR5
PJ4 input/
PWM2E/
PJDR4
PJ3 input/
PWM2D/
PJDR3
PJ2 input/
PWM2C/
PJDR2
PJ1 input/
PWM2B/
PJDR1
PJ0 input/
PWM2A/
PJDR0
PJ7 input/
PWM2H/
PJDR7
PJ6 input/
PWM2G/
PJDR6
PJ5 input/
PWM2F/
PJDR5
PJ4 input/
PWM2E/
PJDR4
PH3 input/
PWM2D/
PJDR3
PH2 input/
PWM2C/
PJDR2
PH1 input/
PWM2B/
PJDR1
PH0 input/
PWM2A/
PJDR0
PJ7 input/
PWM2H/
PJDR7
PJ6 input/
PWM2G/
PJDR6
PJ5 input/
PWM2F/
PJDR5
PJ4 input/
PWM2E/
PJDR4
PJ3 input/
PWM1D/
PHDR3
PJ2 input/
PWM1C/
PHDR2
PJ1 input/
PWM1B/
PHDR1
PJ0 input/
PWM1A/
PHDR0
PH7 input/
PWM2H/
PJDR7
PH6 input/
PWM2G/
PJDR6
PH5 input/
PWM2F/
PJDR5
PH4 input/
PWM2E/
PJDR4
PJ3 input/
PWM2D/
PJDR3
PJ2 input/
PWM2C/
PJDR2
PJ1 input/
PWM2B/
PJDR1
PJ0 input/
PWM2A/
PJDR0
PJ7 input/
PWM1H/
PHDR7
PJ6 input/
PWM1G/
PHDR6
PJ5 input/
PWM1F/
PHDR5
PJ4 input/
PWM1E/
PHDR4
PJ3 input/
PWM2D/
PJDR3
PJ2 input/
PWM2C/
PJDR2
PJ1 input/
PWM2B/
PJDR1
PJ0 input/
PWM2A/
PJDR0
PH7 input/
PWM2H/
PJDR7
PH6 input/
PWM2G/
PJDR6
PH5 input/
PWM2F/
PJDR5
PH4 input/
PWM2E/
PJDR4
PH3 input/
PWM2D/
PJDR3
PH2 input/
PWM2C/
PJDR2
PH1 input/
PWM2B/
PJDR1
PH0 input/
PWM2A/
PJDR0
PJ7 input/
PWM1H/
PHDR7
PJ6 input/
PWM1G/
PHDR6
PJ5 input/
PWM1F/
PHDR5
PJ4 input/
PWM1E/
PHDR4
PJ3 input/
PWM1D/
PHDR3
PJ2 input/
PWM1C/
PHDR2
PJ1 input/
PWM1B/
PHDR1
PJ0 input/
PWM1A/
PHDR0
PH7 input/
PWM1H/
PHDR7
PH6 input/
PWM1G/
PHDR6
PH5 input/
PWM1F/
PHDR5
PH4 input/
PWM1E/
PHDR4
PJ3 input/
PWM1D/
PHDR3
PJ2 input/
PWM1C/
PHDR2
PJ1 input/
PWM1B/
PHDR1
PJ0 input/
PWM1A/
PHDR0
PH7 input/
PWM1H/
PHDR7
PH6 input/
PWM1G/
PHDR6
PH5 input/
PWM1F/
PHDR5
PH4 input/
PWM1E/
PHDR4
PH3 input/
PWM2D/
PJDR3
PH2 input/
PWM2C/
PJDR2
PH1 input/
PWM2B/
PJDR1
PH0 input/
PWM2A/
PJDR0
PJ7 input/
PWM1H/
PHDR7
PJ6 input/
PWM1G/
PHDR6
PJ5 input/
PWM1F/
PHDR5
PJ4 input/
PWM1E/
PHDR4
PH3 input/
PWM1D/
PHDR3
PH2 input/
PWM1C/
PHDR2
PH1 input/
PWM1B/
PHDR1
PH0 input/
PWM1A/
PHDR0
PH7 input/
PWM2H/
PJDR7
PH6 input/
PWM2G/
PJDR6
PH5 input/
PWM2F/
PJDR5
PH4 input/
PWM2E/
PJDR4
PH3 input/
PWM1D/
PHDR3
PH2 input/
PWM1C/
PHDR2
PH1 input/
PWM1B/
PHDR1
PH0 input/
PWM1A/
PHDR0
PJ7 input/
PWM1H/
PHDR7
PJ6 input/
PWM1G/
PHDR6
PJ5 input/
PWM1F/
PHDR5
PJ4 input/
PWM1E/
PHDR4
PJ3 input/
PWM1D/
PHDR3
PJ2 input/
PWM1C/
PHDR2
PJ1 input/
PWM1B/
PHDR1
PJ0 input/
PWM1A/
PHDR0
PH7 input/
PWM2H/
PJDR7
PH6 input/
PWM2G/
PJDR6
PH5 input/
PWM2F/
PJDR5
PH4 input/
PWM2E/
PJDR4
PH3 input/
PWM2D/
PJDR3
PH2 input/
PWM2C/
PJDR2
PH1 input/
PWM2B/
PJDR1
PH0 input/
PWM2A/
PJDR0
7
Bit
Read
Data
6543210
Pin No.
Pin
State
7
Bit
Read
Data
6543210
46
Pin No.
Pin
State
45 44 43 40 39 38 37 56 55 54 53 50 49 48 47
7
Bit
Read
Data
6543210
Pin No.
Pin
State
7
Bit
Read
Data
6543210
46
Pin No.
Pin
State
45 44 43 40 39 38 37 56 55 54 53 50 49 48 47
7
Bit
Read
Data
6543210
Pin No.
Pin
State
7
Bit
Read
Data
6543210
46
Pin No.
Pin
State
45 44 43 40 39 38 37 56 55 54 53 50 49 48 47
7
Bit
Read
Data
6543210
Pin No.
Pin
State
00
Rev. 2.00, 03/04, page 131 of 508
Section 8 16-Bit Timer Pulse Unit (TPU)
This LSI has an on-chip 16-bit timer pulse unit (TPU) comprised of three 16-bit timer channels.
The function list of the 16-bit timer unit and its block diagram are shown in table 8.1 and figure
8.1, respectively.
8.1 Features
• Maximum 8-pulse input/ output
• Selection of 8 counter input clocks for each channel
• The following operations can be set for eac h chan nel .
Waveform output at compare match
Input capture function
Counter clear operation
Synchronous operation:
Multiple timer counters (TCNT) can be written to simu ltaneously
Simultaneous clearing by compare match and inpu t capture is possible
Register simultane ous input/output is possible by synchronous cou nter operation
A maximum 7-phase PWM output is possible in combination with synchronous operation
• Buffer operation settable for channel 0
• Phase counting mode settable independently for each of channels 1 and 2
• Fast access via internal 16-bit bus
• 13 in terrupt sources
• A/D converter conversion start trigger can be generated
• Module stop mode can be set
TIMTPU4A_000020020200
Rev. 2.00, 03/04, page 132 of 508
Table 8.1 TPU Functions (1)
Item Channel 0 Channel 1 Channel 2
Count clock φ/1
φ/4
φ/16
φ/64
TCLKA
TCLKB
TCLKC
TCLKD
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKB
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKB
TCLKC
General registers TGRA_0
TGRB_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
General registers/
buffer registers
TGRC_0
TGRD_0
I/O pins TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
Counter clear
function
TGR compare match or
input capture
TGR compare match or
input capture
TGR compare match or
input capture
0 output
1 output
Compare
match
output
Toggle
output
Input capture
function
Synchronous
operation
PWM mode
Phase counting
mode
Buffer operation
Rev. 2.00, 03/04, page 133 of 508
Table 8.1 TPU Functions (2)
Item Channel 0 Channel 1 Channel 2
A/D converter trigger TGRA_0 compare
match or input capture
TGRA_1 compare
match or input capture
TGRA_2 compare
match or input capture
Interrupt sources 5 sources
• Compare
match or
input capture 0A
• Compare
match or
input capture 0B
• Compare
match or
input capture 0C
• Compare
match or
input capture 0D
• Overflow
4 sources
• Compare
match or
input capture 1A
• Compare
match or
input capture 1B
• Overflow
• Underflow
4 sources
• Compare
match or
input capture 2A
• Compare
match or
input capture 2B
• Overflow
• Underflow
[Legend]
: Possible
—: Not possible
Rev. 2.00, 03/04, page 134 of 508
Channel 2
TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
TGRC
Channel 1
TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
Channel 0
Control logic for channel 0 to 2
TGRA
TCNT
TGRB
TGRD
Bus
interface
Common
TSYR
Control logic
TSTR
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
TCLKA
TCLKB
TCLKC
TCLKD
[Legend]
TSTR:
TSYR:
TCR:
TMDR:
Timer start register
Timer synchro register
Timer control register
Timer mode register
Timer I/O control registers (H, L)
Timer interrupt enable register
Timer status register
TImer general registers (A, B, C, D)
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
Interrupt request signals
Channel 0:
Channel 1:
Channel 2:
Internal data bus
A/D converter convertion start signal
Module data bus
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
TGI1A
TGI1B
TCI1V
TCI1U
TGI2A
TGI2B
TCI2V
TCI2U
TMDR
TSR
TCR
TIORH
TIER
TIORL
Input/output pins
Channel 0:
Channel 1:
Channel 2:
Clock input
Internal clock:
External clock:
TIOR(H, L):
TIER:
TSR:
TGR(A, B, C, D):
Figure 8.1 Block Diagram of TPU
Rev. 2.00, 03/04, page 135 of 508
8.2 Input/Output Pins
Table 8.2 Pin Configuration
Channel Symbol I/O Function
All TCLKA Input External clock A input pin
(Channel 1 phase counting mode A phase input)
TCLKB Input External clock B input pin
(Channel 1 phase counting mode B phase input)
TCLKC Input External clock C input pin
(Channel 2 phase counting mode A phase input)
TCLKD Input External clock D input pin
(Channel 2 phase counting mode B phase input)
0 TIOCA0 I/O TGRA_0 input capture input/output compare output/PWM output pin
TIOCB0 I/O TGRB_0 input capture input/output compare output/PWM output pin
TIOCC0 I/O TGRC_0 input capture input/output compare output/PWM output pin
TIOCD0 I/O TGRD_0 input capture input/output compare output/PWM output pin
1 TIOCA1 I/O TGRA_1 input capture input/output compare output/PWM output pin
TIOCB1 I/O TGRB_1 input capture input/output compare output/PWM output pin
2 TIOCA2 I/O TGRA_2 input capture input/output compare output/PWM output pin
TIOCB2 I/O TGRB_2 input capture input/output compare output/PWM output pin
Rev. 2.00, 03/04, page 136 of 508
8.3 Register Descriptions
The TPU has the following registers. To distinguish registers in each channel, an underscore and
the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as
TCR_0.
• Timer control register_0 (TCR_0)
• Timer mode register_0 (TMDR_0)
• Timer I/O control register H_0 (TIORH_0)
• Timer I/O control register L_0 (TIORL_0)
• Timer interrupt enable register_0 (TIER_0)
• Timer status register_0 (TSR_0)
• Timer counter_0 (TCNT_0)
• Timer general register A_0 (TGRA_ 0)
• Timer general register B_0 (TGR B_ 0)
• Timer general register C_0 (TGR C_ 0)
• Timer general register D_0 (TGRD_ 0)
• Timer control register_1 (TCR_1)
• Timer mode register_1 (TMDR_1)
• Timer I/O control register _1 (TIOR_1)
• Timer interrupt enable register_1 (TIER_1)
• Timer status register_1 (TSR_1)
• Timer counter_1 (TCNT_1)
• Timer general register A_1 (TGRA_ 1)
• Timer general register B_1 (TGR B_ 1)
• Timer control register_2 (TCR_2)
• Timer mode register_2 (TMDR_2)
• Timer I/O control register_2 (TIOR_2)
• Timer interrupt enable register_2 (TIER_2)
• Timer status register_2 (TSR_2)
• Timer counter_2 (TCNT_2)
• Timer general register A_2 (TGRA_ 2)
• Timer general register B_2 (TGR B_ 2)
Common Registers
• Timer start register (TSTR)
• Timer synchro register (TSYR)
Rev. 2.00, 03/04, page 137 of 508
8.3.1 Timer Control Register (TCR)
The TCR registers control the TCNT operation for each channel. The TPU has a total of three
TCR registers, one for each channel. TCR register settings should be conducted only when TCNT
operation is stopped.
Bit Bit Name Initial
value R/W Description
7
6
5
CCLR2
CCLR1
CCLR0
0
0
0
R/W
R/W
R/W
Counter Clear 0 to 2
These bits select the TCNT counter clearing source.
See tables 8.3 and 8.4 for details.
4
3
CKEG1
CKEG0
0
0
R/W
R/W
Clock Edge 0 and 1
These bits select the input clock edge. When the input
clock is counted using both edges, the input clock
period is halved (e.g. φ/4 both edges = φ/2 rising edge).
If phase counting mode is used on channels 1 and 2,
this setting is ignored and the phase counting mode
setting has priority. Internal clock edge selection is valid
when the input clock is φ/4 or slower. This setting is
ignored if the input clock is φ/1, or when
overflow/underflow of another channel is selected.
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
R/W
R/W
R/W
Time Prescaler 0 to 2
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 8.5 to 8.7 for details.
[Legend]
X: Don't care
Rev. 2.00, 03/04, page 138 of 508
Table 8.3 CCLR0 to CCLR2 (Channel 0)
Channel Bit 7
CCLR2 Bit 6
CCLR1 Bit 5
CCLR0
Description
0 0 0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input
capture
1 0 TCNT cleared by TGRB compare match/input
capture
1 TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*1
1 0 0 TCNT clearing disabled
1 TCNT cleared by TGRC compare match/input
capture*2
1 0 TCNT cleared by TGRD compare match/input
capture*2
1 TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*1
Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
Table 8.4 CCLR0 to CCLR2 (Channels 1 and 2)
Channel Bit 7
Reserved*2 Bit 6
CCLR1 Bit 5
CCLR0
Description
1, 2 0 0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input
capture
1 0 TCNT cleared by TGRB compare match/input
capture
1 TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*1
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified.
Rev. 2.00, 03/04, page 139 of 508
Table 8.5 TPSC0 to TPSC2 (Channel 0)
Channel Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0
Description
0 0 0 0 Internal clock: counts on φ/1
1 Internal clock: counts on φ/4
1 0 Internal clock: counts on φ/16
1 Internal clock: counts on φ/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1 0 External clock: counts on TCLKC pin input
1 External clock: counts on TCLKD pin input
Table 8.6 TPSC0 to TPSC2 (Channel 1)
Channel Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0
Description
1 0 0 0 Internal clock: counts on φ/1
1 Internal clock: counts on φ/4
1 0 Internal clock: counts on φ/16
1 Internal clock: counts on φ/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1 0 Internal clock: counts on φ/256
1 Setting prohibited
Note: This setting is ignored when channel 1 is in phase counting mode.
Rev. 2.00, 03/04, page 140 of 508
Table 8.7 TPSC0 to TPSC2 (Channel 2)
Channel Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0
Description
2 0 0 0 Internal clock: counts on φ/1
1 Internal clock: counts on φ/4
1 0 Internal clock: counts on φ/16
1 Internal clock: counts on φ/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1 0 External clock: counts on TCLKC pin input
1 Internal clock: counts on φ/1024
Note: This setting is ignored when channel 2 is in phase counting mode.
8.3.2 Timer Mode Register (TMDR)
The TMDR registers are used to set the operating mode of each channel. The TPU has three
TMDR registers, one for each channel. TMDR register settings should be changed only when
TCNT operation is stopped.
Bit Bit Name Initial
value R/W Description
7, 6 All 1 Reserved
These bits are always read as 1 and cannot be
modified.
5 BFB 0 R/W Buffer Operation B
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together for
buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not
generated.
In channels 1 and 2, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation
Rev. 2.00, 03/04, page 141 of 508
Bit Bit Name Initial
value R/W Description
4 BFA 0 R/W Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together for
buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not
generated.
In channels 1, and 2, which have no TGRC, bit 4 is
reserved. It is always read as 0 and cannot be modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
3
2
1
0
MD3
MD2
MD1
MD0
0
0
0
0
R/W
R/W
R/W
R/W
Modes 0 to 3
These bits are used to set the timer operating mode.
MD3 is a reserved bit. In a write, it should always be
written with 0. See table 8.8 for details.
Table 8.8 MD0 to MD3
Bit 3
MD3*1 Bit 2
MD2*2 Bit 1
MD1 Bit 0
MD0
Description
0 0 0 0 Normal operation
1 Reserved
1 0 PWM mode 1
1 PWM mode 2
1 0 0 Phase counting mode 1
1 Phase counting mode 2
1 0 Phase counting mode 3
1 Phase counting mode 4
1 X X X
[Legend]
X: Don't care
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
2. Phase counting mode cannot be set for channel 0. In this case, 0 should always be
written to MD2.
Rev. 2.00, 03/04, page 142 of 508
8.3.3 Timer I/O Control Register (TIOR)
The TIOR registers control the TGR registers. The TPU has four TIOR registers, two for channel
0, and one each for channels 1 and 2.
Care is required as TIOR is affected by the TMDR settin g. The initial o utput specified by TIOR is
valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM
mode 2, the output at the po int at which the counter is cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
• TIORH_0, TIOR_1, TIOR_2
Bit
Bit Name Initial
value
R/W
Description
7
6
5
4
IOB3
IOB2
IOB1
IOB0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control B0 to B3
Specify the function of TGRB.
3
2
1
0
IOA3
IOA2
IOA1
IOA0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control A0 to A3
Specify the function of TGRA.
• TIORL_0
Bit
Bit Name Initial
value
R/W
Description
7
6
5
4
IOD3
IOD2
IOD1
IOD0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control D0 to D3
Specify the function of TGRD.
3
2
1
0
IOC3
IOC2
IOC1
IOC0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Control C0 to C3
Specify the function of TGRC.
Rev. 2.00, 03/04, page 143 of 508
Table 8.9 TIORH_0
Description
Bit 7
IOB3 Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 TGRB_0
Function
TIOCB0 Pin Function
0 0 0 0 Output disabled
1
Output
compare
register Initial output is 0
0 output at compare match
1 0 Initial output is 0
1 output at compare match
1 Initial output is 0
Toggle output at compare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare match
1 0 Initial output is 1
1 output at compare match
1 Initial output is 1
Toggle output at compare match
1 0 0 0 Input capture at rising edge
1 Input capture at falling edge
1 X Input capture at both edges
1 X X
Input capture
register
Capture input source is channel 1/count clock
Input capture at TCNT_1 count- up/count-down*
[Legend]
X: Don't care
Note: * When bits TPSC0 to TPSC2 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1
count clock, this setting is invalid and input capture is not generated.
Rev. 2.00, 03/04, page 144 of 508
Table 8.10 TIORL_0
Description
Bit 7
IOD3 Bit 6
IOD2 Bit 5
IOD1 Bit 4
IOD0 TGRD_0
Function
TIOCD0 Pin Function
0 0 0 0 Output disabled
1 Initial output is 0
0 output at compare match
1 0
Output
compare
register*2
Initial output is 0
1 output at compare match
1 Initial output is 0
Toggle output at compare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare match
1 0 Initial output is 1
1 output at compare match
1 Initial output is 1
Toggle output at compare match
1 0 0 0 Capture input source is TIOCD0 pin
Input capture at rising edge
1 Capture input source is TIOCD0 pin
Input capture at falling edge
1 X
Input capture
register*2
Capture input source is TIOCD0 pin
Input capture at both edges
1 X X Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down*1
[Legend]
X: Don't care
Notes: 1. When bits TPSC0 to TPSC2 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 2.00, 03/04, page 145 of 508
Table 8.11 TIOR_1
Description
Bit 7
IOB3 Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 TGRB_1
Function
TIOCB1 Pin Function
0 0 0 0 Output disabled
1 Initial output is 0
0 output at compare match
1 0
Output
compare
register
Initial output is 0
1 output at compare match
1 Initial output is 0
Toggle output at compare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare match
1 0 Initial output is 1
1 output at compare match
1 Initial output is 1
Toggle output at compare match
1 0 0 0 Capture input source is TIOCB1 pin
Input capture at rising edge
1 Capture input source is TIOCB1 pin
Input capture at falling edge
1 X
Input capture
register
Capture input source is TIOCB1 pin
Input capture at both edges
1 X X TGRC_0 compare match/ input capture
Input capture at generation of TGRC_0 compare
match/input capture
[Legend]
X: Don't care
Rev. 2.00, 03/04, page 146 of 508
Table 8.12 TIOR_2
Description
Bit 7
IOB3 Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 TGRB_2
Function
TIOCB2 Pin Function
0 0 0 0 Output disabled
1 Initial output is 0
0 output at compare match
1 0
Output
compare
register
Initial output is 0
1 output at compare match
1 Initial output is 0
Toggle output at compare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare match
1 0 Initial output is 1
1 output at compare match
1 Initial output is 1
Toggle output at compare match
1 X 0 0 Capture input source is TIOCB2 pin
Input capture at rising edge
1 Capture input source is TIOCB2 pin
Input capture at falling edge
1 X
Input capture
register
Capture input source is TIOCB2 pin
Input capture at both edges
[Legend]
X: Don't care
Rev. 2.00, 03/04, page 147 of 508
Table 8.13 TIORH_0
Description
Bit 3
IOA3 Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 TGRA_0
Function
TIOCA0 Pin Function
0 0 0 0 Output disabled
1 Initial output is 0
0 output at compare match
1 0
Output
compare
register
Initial output is 0
1 output at compare match
1 Initial output is 0
Toggle output at compare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare match
1 0 Initial output is 1
1 output at compare match
1 Initial output is 1
Toggle output at compare match
1 0 0 0 Capture input source is TIOCA0 pin
Input capture at rising edge
1 Capture input source is TIOCA0 pin
Input capture at falling edge
1 X
Input capture
register
Capture input source is TIOCA0 pin
Input capture at both edges
1 X X Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
[Legend]
X: Don't care
Rev. 2.00, 03/04, page 148 of 508
Table 8.14 TIORL_0
Description
Bit 3
IOC3 Bit 2
IOC2 Bit 1
IOC1 Bit 0
IOC0 TGRC_0
Function
TIOCC0 Pin Function
0 0 0 0 Output disabled
1 Initial output is 0
0 output at compare match
1 0
Output
compare
register*
Initial output is 0
1 output at compare match
1 Initial output is 0
Toggle output at compare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare match
1 0 Initial output is 1
1 output at compare match
1 Initial output is 1
Toggle output at compare match
1 0 0 0 Capture input source is TIOCC0 pin
Input capture at rising edge
1 Capture input source is TIOCC0 pin
Input capture at falling edge
1 X
Input capture
register*
Capture input source is TIOCC0 pin
Input capture at both edges
1 X X Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
[Legend]
X: Don't care
Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 2.00, 03/04, page 149 of 508
Table 8.15 TIOR_1
Description
Bit 3
IOA3 Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 TGRA_1
Function
TIOCA1 Pin Function
0 0 0 0 Output disabled
1 Initial output is 0
0 output at compare match
1 0
Output
compare
register
Initial output is 0
1 output at compare match
1 Initial output is 0
Toggle output at compare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare match
1 0 Initial output is 1
1 output at compare match
1 Initial output is 1
Toggle output at compare match
1 0 0 0 Capture input source is TIOCA1 pin
Input capture at rising edge
1 Capture input source is TIOCA1 pin
Input capture at falling edge
1 X
Input capture
register
Capture input source is TIOCA1 pin
Input capture at both edges
1 X X Capture input source is TGRA_0 compare
match/input capture
Input capture at generation of channel 0/TGRA_0
compare match/input capture
[Legend]
X: Don't care
Rev. 2.00, 03/04, page 150 of 508
Table 8.16 TIOR_2
Description
Bit 3
IOA3 Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 TGRA_2
Function
TIOCA2 Pin Function
0 0 0 0 Output disabled
1 Initial output is 0
0 output at compare match
1 0
Output
compare
register
Initial output is 0
1 output at compare match
1 Initial output is 0
Toggle output at compare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare match
1 0 Initial output is 1
1 output at compare match
1 Initial output is 1
Toggle output at compare match
1 X 0 0 Capture input source is TIOCA2 pin
Input capture at rising edge
1 Capture input source is TIOCA2 pin
Input capture at falling edge
1 X
Input capture
register
Capture input source is TIOCA2 pin
Input capture at both edges
[Legend]
X: Don't care
Rev. 2.00, 03/04, page 151 of 508
8.3.4 Timer Interrupt Enable Register (TIER)
The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU
has three TIER registers, one for each channel.
Bit Bit Name Initial
value R/W Description
7 TTGE 0 R/W A/D Conversion Start Request Enable
Enables or disables generation of A/D conversion start
requests by TGRA input capture/compare match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
6 1 Reserved
This bit is always read as 1 and cannot be modified.
5 TCIEU 0 R/W Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in
channels 1 and 2.
In channel 0, bit 5 is reserved. It is always read as 0
and cannot be modified.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
4 TCIEV 0 R/W Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
3 TGIED 0 R/W TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in
channel 0.
In channels 1 and 2, bit 3 is reserved. It is always read
as 0 and cannot be modified.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
Rev. 2.00, 03/04, page 152 of 508
Bit Bit Name Initial
value R/W Description
2 TGIEC 0 R/W TGR Interrupt Enable C
Enables or disables interrupt requests (TGIC) by the
TGFC bit when the TGFC bit in TSR is set to 1 in
channel 0.
In channels 1 and 2, bit 2 is reserved. It is always read
as 0 and cannot be modified.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
1 TGIEB 0 R/W TGR Interrupt Enable B
Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
0 TGIEA 0 R/W TGR Interrupt Enable A
Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA bit disabled
1: Interrupt requests (TGIA) by TGFA bit enabled
Rev. 2.00, 03/04, page 153 of 508
8.3.5 Timer Status Register (T SR )
The TSR registers indicate the status of each channel. The TPU has three TSR registers, one for
each channel.
Bit Bit Name Initial
value R/W Description
7 TCFD 1 R Count Direction Flag
Status flag that shows the direction in which TCNT
counts in channels 1 and 2.
In channel 0, bit 7 is reserved. It is always read as 1
and cannot be modified.
0: TCNT counts down
1: TCNT counts up
6 1 Reserved
This bit is always read as 1 and cannot be modified.
5 TCFU 0 R/(W)* Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1 and 2 are set to phase
counting mode. Only 0 can be written, for flag clearing.
In channel 0, bit 5 is reserved. It is always read as 0
and cannot be modified.
[Setting condition]
When the TCNT value underflows (changes from
H'0000 to H'FFFF)
[Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
4 TCFV 0 R/(W)* Overflow Flag
Status flag that indicates that TCNT overflow has
occurred. Only 0 can be written, for flag clearing.
[Setting condition]
When the TCNT value overflows (changes from H'FFFF
to H'0000 )
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
Rev. 2.00, 03/04, page 154 of 508
Bit Bit Name Initial
value R/W Description
3 TGFD 0 R/(W)* Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD input
capture or compare match in channel 0. In channels 1
and 2, bit 3 is reserved. It is always read as 0 and
cannot be modified.
[Setting conditions]
• When TCNT = TGRD and TGRD is functioning as
output compare register
• When TCNT value is transferred to TGRD by input
capture signal and TGRD is functioning as input
capture register
[Clearing condition]
• When 0 is written to TGFD after reading TGFD = 1
2 TGFC 0 R/(W)* Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC input
capture or compare match in channel 0. In channels 1
and 2, bit 2 is reserved. It is always read as 0 and
cannot be modified.
[Setting conditions]
• When TCNT = TGRC and TGRC is functioning as
output compare register
• When TCNT value is transferred to TGRC by input
capture signal and TGRC is functioning as input
capture register
[Clearing condition]
• When 0 is written to TGFC after reading TGFC = 1
1 TGFB 0 R/(W)* Input Capture/Output Compare Flag B
Status flag that indicates the occurrence of TGRB input
capture or compare match.
[Setting conditions]
• When TCNT = TGRB and TGRB is functioning as
output compare register
• When TCNT value is transferred to TGRB by input
capture signal and TGRB is functioning as input
capture register
[Clearing condition]
• When 0 is written to TGFB after reading TGFB = 1
Rev. 2.00, 03/04, page 155 of 508
Bit Bit Name Initial
value R/W Description
0 TGFA 0 R/(W)* Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA input
capture or compare match.
[Setting conditions]
• When TCNT = TGRA and TGRA is functioning as
output compare register
• When TCNT value is transferred to TGRA by input
capture signal and TGRA is functioning as input
capture register
[Clearing condition]
• When 0 is written to TGFA after reading TGFA = 1
Note: * Only 0 can be written, for flag clearing.
8.3.6 Timer Counter (TCNT)
The TCNT registers are 16-bit readable/writable counters. The TPU has three TCNT counters, one
for each channel.
The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
8.3.7 Timer General Register (TGR)
The TGR registers are dual function 16-bit readable/writable registers, functioning as either output
compare or input capture registers. The TPU has eight TGR registers, four for channel 0 and two
each for channels 1 and 2. TGRC and TGRD for channel 0 can also be designated for operation as
buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be
accessed as a 16-bit unit. TGR buffer register combinations are TGRA—TGRC and TGRB—
TGRD.
Rev. 2.00, 03/04, page 156 of 508
8.3.8 Timer Start Register (TST R )
TSTR selects operation/stoppage for channels 0 to 2. When setting the operating mode in TMDR
or setting the count clock in TCR, first stop the TCNT counter.
Bit Bit Name Initial
value R/W Description
7 to 3 All 0 Reserved
Only 0 should be written to these bits.
2
1
0
CST2
CST1
CST0
0 R/W Counter Start 2 to 0
These bits select operation or stoppage for TCNT.
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops but
the TIOC pin output compare output level is retained. If
TIOR is written to when the CST bit is cleared to 0, the
pin output level will be changed to the set initial output
value.
0: TCNT_2 to TCNT_0 count operation is stopped
1: TCNT_2 to TCNT_0 performs count operation
Rev. 2.00, 03/04, page 157 of 508
8.3.9 Timer Synchro Regis ter (T S YR )
TSYR selects independent operation or synchronous operation for the channel 0 to 2 TCNT
counters. A channel performs synchr on o us o perati o n w hen t he corre sp o ndi ng bi t in TS Y R is set to
1.
Bit Bit Name Initial
value R/W Description
7 to 3 All 0 R/W Reserved
Only 0 should be written to these bits.
2
1
0
SYNC2
SYNC1
SYNC0
0 R/W Timer Synchro 2 to 0
These bits are used to select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, the TCNT
synchronous presetting of multiple channels, and
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit, the
TCNT clearing source must also be set by means of
bits CCLR0 to CCLR2 in TCR.
0: TCNT_2 to TCNT_0 operates independently (TCNT
presetting /clearing is unrelated to other channels)
1: TCNT_2 to TCNT_0 performs synchronous operation
TCNT synchronous presetting/synchronous clearing is
possible
Rev. 2.00, 03/04, page 158 of 508
8.4 Operation
8.4.1 Basic Functions
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, synchrono us counting, and ex ternal event counting.
Each TGR can be used as an input capture register or output compare register.
Counter Operation: When one of bits CST0 to CST2 is set to 1 in TSTR, the TCNT counter for
the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic
counter, for example.
1. Example of count operation setting procedure
Figure 8.2 shows an example of the count operation setting procedure.
Operation selection
Select counter clock
Periodic counter
Select counter clearing source
Select output compare register
Set period
Free-running counter
Start count operation
<Free-running counter><Periodic counter>
Start count operation
Select the counter
clock with bits
TPSC2 to TPSC0 in
TCR. At the same
time, select the
input clock edge
with bits CKEG1
and CKEG0 in TCR.
For periodic counter
operation, select the
TGR to be used as
the TCNT clearing
source with bits
CCLR2 to CCLR0 in
TCR.
Designate the TGR
selected in [2] as an
output compare
register by means of
TIOR.
Set the periodic
counter cycle in the
TGR selected in [2].
Set the CST bit in
TSTR to 1 to start
the counter
operation.
[1]
[1]
[2]
[2]
[3][3]
[4]
[4]
[5]
[5]
Figure 8.2 Example of Counter Operation Setting Procedure
Rev. 2.00, 03/04, page 159 of 508
2. Free-running count operation and periodic count operation
Immediately after a reset, the TPU's TCNT counters are all designated as free-running
counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-
count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000),
the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at
this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from
H'0000.
Figure 8.3 illustrates free-running cou nter operation.
TCNT value
H'FFFF
H'0000
CST bit
TCFV
Time
Figure 8.3 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the
relevant channel performs periodic count operation. The TGR register for setting the period is
designated as an output compare register, and counter clearing by compare match is selected
by means of bits CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts
up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When
the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared
to H'0000.
If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an
interrupt. After a compare match, TCNT starts counting up again from H'0000.
Figure 8.4 illustrates periodic counter operation.
Rev. 2.00, 03/04, page 160 of 508
TCNT value
TGR
H'0000
CST bit
TGF
Time
Counter cleared by TGR
compare match
Flag cleared by software
Figure 8.4 Periodic Counter Operation
Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the
corresponding output pin using compare match.
1. Example of setting procedure for wavef orm output by compare match
Figure 8.5 shows an example of the setting procedure for waveform output by compare match
Output selection
Select waveform output mode
Set output timing
Start count operation
<Waveform output>
Select initial value 0 output or 1 output, and
compare match output value 0 output, 1 output,
or toggle output, by means of TIOR. The set
initial value is output at the TIOC pin unit the
first compare match occurs.
Set the timing for compare match generation in
TGR.
Set the CST bit in TSTR to 1 to start the count
operation.
[1]
[1] [2]
[2]
[3]
[3]
Figure 8.5 Example of Setti ng Proced ur e for Waveform Output by Compare Match
Rev. 2.00, 03/04, page 161 of 508
2. Examples of wavef orm output operation
Figure 8.6 shows an example of 0 output/1 output.
In this example TCNT has been designated as a free-running counter, and settings have been
made such that 1 is output by compare match A, and 0 is output by compare match B. When
the set level and the pin level coincide, the pin leve l does not change.
TCNT value
H'FFFF
H'0000
TIOCA
TIOCB
Time
TGRA
TGRB
No change No change
No change No change
1 output
0 output
Figure 8.6 Example of 0 Outp ut/ 1 Output Operation
Figure 8.7 shows an example of toggle output.
In this example, TCNT has been designated as a periodic counter (with counter clearing on
compare match B), and settings have been made such that the output is toggled by both
compare match A and compare match B.
TCNT value
H'FFFF
H'0000
TIOCB
TIOCA
Time
TGRB
TGRA
Toggle output
Toggle output
Counter cleared by TGRB compare match
Figure 8.7 Example of Toggle Output Operation
Rev. 2.00, 03/04, page 162 of 508
Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC
pin input edge.
Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1,
it is also possible to specify another channel's counter input clock or compare match signal as the
input capture source.
Note: When another channel's counter input clock is used as the input capture input for channel
0, φ/1 should not be selected as the counter input clock used for input capture input. Input
capture will not be generated if φ/1 is selected.
1. Example of input capture operation setting procedure
Figure 8.8 shows an example of the input capture operation setting procedure.
Input selection
Select input capture input
Start count
<Input capture operation>
Designate TGR as an input capture register by
means of TIOR, and select rising edge, falling
edge, or both edges as the input capture source
and input signal edge.
Set the CST bit in TSTR to 1 to start the count
operation.
[1]
[2]
[1]
[2]
Figure 8.8 Example of Input Capt ure Opera tion Setting Procedure
Rev. 2.00, 03/04, page 163 of 508
2. Example of input capture operation
Figure 8.9 shows an example of input capture operation.
In this example both rising and falling edges have been selected as the TIOCA pin input
capture input edge, the falling edge has been selected as the TIOCB pin input capture input
edge, and counter clearing by TGRB inpu t capture has been designated for TCNT.
TCNT value
H'0180
H'0000
TIOCA
TGRA
H'0010
H'0005
Counter cleared by TIOCB
input (falling edge)
H'0160
H'0005 H'0160 H'0010
TGRB H'0180
TIOCB
Time
Figure 8.9 Example of Input Capture Operation
Rev. 2.00, 03/04, page 164 of 508
8.4.2 Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten
simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared
simultaneously by making the appropriate setting in TCR (synchronous clearing).
Synchronous operation enables TGR to be incremented with respect to a single time base.
Channels 0 to 2 can all be designated for synchronous operation.
Example of Synchronous Operation Setting Procedure: Figure 8.10 shows an examp le of the
synchronous operation setting procedure.
No
Yes
Synchronous operation
selection
Set synchronous
operation
Synchronous presetting
Set TCNT
<Synchronous presetting> <Counter clearing> <Synchronous clearing>
Synchronous clearing
Clearing
source generation
channel?
Select counter
clearing source
Start count
Set synchronous
counter clearing
Start count
Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous
operation.
When the TCNT counter of any of the channels designated for synchronous operation is
written to, the same value is simultaneously written to the other TCNT counters.
Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare,
etc.
Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing
source.
Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
[1]
[2]
[3]
[4]
[5]
[1]
[3]
[4]
[4]
[5]
[2]
Figure 8.10 Example of Synchronous Operation Setting Procedure
Rev. 2.00, 03/04, page 165 of 508
Example of Synchronous Operation: Figure 8.11 shows an example of synchronous oper ation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to
2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and
synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this
time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are
performed for channel 0 to 2 TCNT c o unters, and the data set in TGRB_0 is used as the PWM
cycle.
For details of PWM modes, see section 8.4.4, PWM Modes.
TCNT0 to TCNT2 values
H'0000
TIOCA0
TIOCA1
TGRB_0
Synchronous clearing by TGRB_0 compare match
TGRA_2
TGRA_1
TGRB_2
TGRA_0
TGRB_1
TIOCA2
Time
Figure 8.11 Example of Synchronous Operation
Rev. 2.00, 03/04, page 166 of 508
8.4.3 Buffer Operation
Buffer operation, provided for channel 0, enables TGRC and TGRD to be used as buffer registers.
Buffer operation differs depending on wheth er T GR has been designated as an input capt ure
register or as a compare match register.
Table 8.17 shows the register combinations used in buffer operation.
Table 8.17 Regis ter Co mbinations in Buffer Operation
Channel Timer General Register Buffer Register
0 TGRA_0 TGRC_0
TGRB_0 TGRD_0
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 8.12.
Buffer register Timer general
register TCNTComparator
Compare match signal
Figure 8.12 Compare Match Buffer Operation
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register.
This operation is illustrated in figure 8.13.
Buffer register Timer general
register TCNT
Input capture
signal
Figure 8.13 Input Capture Buffer Operation
Rev. 2.00, 03/04, page 167 of 508
Example of Buffer Operation Setting Procedure: Figure 8.14 shows an example of the buffer
operation setting procedure.
Buffer operation
Select TGR function
Set buffer operation
Start count
<Buffer operation>
[1]
[2]
[3]
[1]
[2]
[3]
Designate TGR as an input capture register or
output compare register by means of TIOR.
Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
Set the CST bit in TSTR to 1 start the count
operation.
Figure 8.14 Example of Buffer Operation Setting Procedure
Examples of Buffer Oper at i on
1. When TGR is an output compare regi st er
Figure 8.15 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffe r o perat i o n has bee n desi gnat ed for TGRA and TGRC. T he setting s u s ed
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has bee n set, whe n com pare match A occurs the output changes and the
value in buffer register TGRC is simultaneously transferred to timer general register TGRA.
This operation is repeated each time that compare match A occurs.
For details of PWM modes, see section 8.4.4, PWM Modes.
Rev. 2.00, 03/04, page 168 of 508
TCNT value
TGRB_0
H'0000
TGRC_0
TGRA_0
H'0200 H'0520
TIOCA
H'0200
H'0450 H'0520
H'0450
TGRA_0 H'0450H'0200
Transfer
Time
Figure 8.15 Example of Buffer Operation (1)
2. When TGR is an input capture register
Figure 8.16 shows an operation example in which TGRA has been designated as an input
capture registe r, an d bu ffer operation has been desi gnat ed for TGR A an d TGR C .
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling
edges have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon the
occurrence of input capture A, the value previously stored in TGRA is simultaneously
transferred to TGRC.
TCNT value
H'09FB
H'0000
TGRC
Time
H'0532
TIOCA
TGRA H'0F07H'0532
H'0F07
H'0532
H'0F07
H'09FB
Figure 8.16 Example of Buffer Operation (2)
Rev. 2.00, 03/04, page 169 of 508
8.4.4 PWM Modes
In PWM mode, PWM waveforms are output from the output pins. The output level can be selected
as 0, 1, or toggle output in response to a compare match of each TGR.
TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty.
Designating TGR compare match as the counter clearing source enables the period to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as desc ri bed below.
• PWM mode 1
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. T he out put speci fi ed by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is
output from the TIOCA and TIOCC pins at compare matches A and C, and the output
specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B
and D. The initial outpu t va lue is the value set in TGRA or TGRC. If the set values of paired
TGRs are identical, the output value does not change when a compare match occurs.
In PWM mode 1, a maximum 4-phase PWM output is possible.
• PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty registers.
The output specified in TIOR is performed by means of compare matches. Upon counter
clearing by a synchronization register compare match, the output value of each pin is the initial
value set in TIOR. If the set values of the cycle and duty registers are identical, the output
value does not change when a compare match occurs.
In PWM mode 2, a maximum 7-phase PWM output is possible in combination use with
synchronous operation.
The correspondence between PWM output pins and registers is shown in table 8.18.
Rev. 2.00, 03/04, page 170 of 508
Table 8.18 PWM Output Registers and Output Pins
Output Pins
Channel Registers PWM Mode 1 PWM Mode 2
0 TGRA_0 TIOCA0 TIOCA0
TGRB_0 TIOCB0
TGRC_0 TIOCC0 TIOCC0
TGRD_0 TIOCD0
1 TGRA_1 TIOCA1 TIOCA1
TGRB_1 TIOCB1
2 TGRA_2 TIOCA2 TIOCA2
TGRB_2 TIOCB2
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
Example of PWM Mode Setting Procedure: Figure 8.17 shows an example of the PWM mode
setting procedure.
PWM mode
Select counter clock
Select counter clearing source
Select waveform output level
Set TGR
Set PWM mode
Start count
<PWM mode>
Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0
in TCR.
Use bits CCLR2 to CCLR0 in TCR to select the
TGR to be used as the TCNT clearing source.
Use TIOR to designate the TGR as an output
compare register, and select the initial value and
output value.
Set the cycle in the TGR selected in [2], and set
the duty in the other the TGR.
Select the PWM mode with bits MD3 to MD0 in
TMDR.
Set the CST bit in TSTR to 1 start the count
operation.
[1]
[2]
[3]
[4]
[5]
[6]
[1]
[2]
[3]
[4]
[5]
[6]
Figure 8.17 Example of PWM Mode Setting Procedure
Rev. 2.00, 03/04, page 171 of 508
Examples of PW M M ode O pera ti on: Figure 8.18 shows an exam pl e of PWM mo de 1 operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers
are used as the duty levels.
TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
Counter cleared by
TGRA compare match
Figure 8.18 Example of PWM M ode O pera ti on (1)
Rev. 2.00, 03/04, page 172 of 508
Figure 8.19 shows an example of PWM mode 2 operation.
In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare
match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the
output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase
PWM waveform.
In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are
used as the duty levels.
TCNT value
TGRB_1
H'0000
TIOCA0
Counter cleared by
TGRB_1 compare match
Time
TGRA_1
TGRD_0
TGRC_0
TGRB_0
TGRA_0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Figure 8.19 Example of PWM M ode O pera ti on (2)
Rev. 2.00, 03/04, page 173 of 508
Figure 8.20 shows examples of PWM waveform output with 0% duty and 100% duty in PWM
mode.
TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
0% duty
TGRB rewritten
TGRB
rewritten
TGRB rewritten
TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
100% duty
TGRB rewritten
TGRB rewritten
TGRB rewritten
Output does not change when cycle register and duty register
compare matches occur simultaneously
TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
100% duty
TGRB rewritten
TGRB rewritten
TGRB rewritten
Output does not change when cycle register and duty
register compare matches occur simultaneously
0% duty
Figure 8.20 Example of PWM M ode O pera ti on (3)
Rev. 2.00, 03/04, page 174 of 508
8.4.5 Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2.
When phase counting mode is set, an exter nal clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits
CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of
TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be
used.
This can be used for two -p ha se enc o der p uls e input .
If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs
when TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is
counting up or do wn.
Table 8.19 shows the correspondence between external clock pins and channels.
Table 8.19 Phase Counting Mode Cloc k Input Pins
External Clock Pins
Channels A-Phase B-Phase
When channel 1 is set to phase counting mode TCLKA TCLKB
When channel 2 is set to phase counting mode TCLKC TCLKD
Example of Phase Counting Mode Setting Procedure: Figure 8.21 shows an example of the
phase counting mode setting procedure.
Phase counting mode
Select phase counting mode
Start count
<Phase counting mode>
Select phase counting mode with bits MD3 to
MD0 in TMDR.
Set the CST bit in TSTR to 1 to start the count
operation.
[1]
[2]
[1]
[2]
Figure 8.21 Example of Phase Counting Mode Setting Procedure
Rev. 2.00, 03/04, page 175 of 508
Examples of Phase Counting Mode Operat i on: In phase counting mode, TCNT counts up or
down according to the phase difference between two external clocks. There are four modes,
according to the count conditions.
1. Phase counting mode 1
Figure 8.22 shows an example of phase counting mode 1 operation, and table 8.20 summarizes
the TCNT up/down-count conditions.
TCNT value
Time
Down-count
Up-count
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
Figure 8.22 Example of Phase Counting Mode 1 Operation
Table 8.20 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channel 1)
TCLKC (Channel 2) TCLKB (Channel 1)
TCLKD (Channel 2)
Operation
High level Up-count
Low level
Low level
High level
High level Down-count
Low level
High level
Low level
[Legend]
: Rising edge
: Falling edge
Rev. 2.00, 03/04, page 176 of 508
2. Phase counting mode 2
Figure 8.23 shows an example of phase counting mode 2 operation, and table 8.21 summarizes
the TCNT up/down-count conditions.
Time
Down-countUp-count
TCNT value
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
Figure 8.23 Example of Phase Counting Mode 2 Operation
Table 8.21 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channel 1)
TCLKC (Channel 2) TCLKB (Channel 1)
TCLKD (Channel 2)
Operation
High level Don't care
Low level Don't care
Low level Don't care
High level Up-count
High level Don't care
Low level Don't care
High level Don't care
Low level Down-count
[Legend]
: Rising edge
: Falling edge
Rev. 2.00, 03/04, page 177 of 508
3. Phase counting mode 3
Figure 8.24 shows an example of phase counting mode 3 operation, and table 8.22 summarizes
the TCNT up/down-count conditions.
Time
Up-count Down-count
TCNT value
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
Figure 8.24 Example of Phase Counting Mode 3 Operation
Table 8.22 Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channel 1)
TCLKC (Channel 2) TCLKB (Channel 1)
TCLKD (Channel 2)
Operation
High level Don't care
Low level Don't care
Low level Don't care
High level Up-count
High level Down-count
Low level Don't care
High level Don't care
Low level Don't care
[Legend]
: Rising edge
: Falling edge
Rev. 2.00, 03/04, page 178 of 508
4. Phase counting mode 4
Figure 8.25 shows an example of phase counting mode 4 operation, and table 8.23 summarizes
the TCNT up/down-count conditions.
Time
Up-count Down-count
TCNT value
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
Figure 8.25 Example of Phase Counting Mode 4 Operation
Table 8.23 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channel 1)
TCLKC (Channel 2) TCLKB (Channel 1)
TCLKD (Channel 2)
Operation
High level Up-count
Low level
Low level Don't care
High level
High level Down-count
Low level
High level Don't care
Low level
[Legend]
: Rising edge
: Falling edge
Rev. 2.00, 03/04, page 179 of 508
Phase Counting Mode Application Example: Figure 8.26 shows an example in which channel 1
is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase
encoder pulses in or der to det ect posi t i on or speed.
Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input
to TCLKA and TCLKB.
Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and
TGRC_0 are used for the compare match function and are set with the speed control period and
position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating
in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture
source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected.
TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and
TGRC_0 compare matches are selected as the input capture source and store the up/down-counter
values for the control periods.
This procedure enables the accurate detection of position and speed.
Rev. 2.00, 03/04, page 180 of 508
TCNT_1
TCNT_0
Channel 1
TGRA_1
(speed period capture)
TGRA_0
(speed control period)
TGRB_1
(speed period capture)
TGRC_0
(position control period)
TGRB_0 (pulse width capture)
TGRD_0 (buffer operation)
Channel 0
TCLKA
TCLKB
Edge
detection
circuit
+
-
+
-
Figure 8.26 Phase Counti ng M ode Ap pl i cati o n Example
Rev. 2.00, 03/04, page 181 of 508
8.5 Interrupts
There are three kinds of TPU interrupt source; TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled
bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interru pt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, however the priority order
within a channel is fixed. For details, see section 5, Interrupt Controller.
Table 8.24 lists the TPU interrupt sources.
Table 8.24 TPU Interrupts
Channel Name Interrupt Source Interrupt Flag
0 TGI0A TGRA_0 input capture/compare match TGFA0
TGI0B TGRB_0 input capture/compare match TGFB0
TGI0C TGRC_0 input capture/compare match TGFC0
TGI0D TGRD_0 input capture/compare match TGFD0
TCI0V TCNT_0 overflow TCFV0
1 TGI1A TGRA_1 input capture/compare match TGFA1
TGI1B TGRB_1 input capture/compare match TGFB1
TCI1V TCNT_1 overflow TCFV1
TCI1U TCNT_1 underflow TCFU1
2 TGI2A TGRA_2 input capture/compare match TGFA2
TGI2B TGRB_2 input capture/compare match TGFB2
TCI2V TCNT_2 overflow TCFV2
TCI2U TCNT_2 underflow TCFU2
Note: This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.
Rev. 2.00, 03/04, page 182 of 508
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is
set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare
match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The
TPU has eight input capture/compare match interrupts, four for channel 0, and two each for
channels 1 and 2.
Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channe l. The interrupt
request is cleared by clearing the TCFV flag to 0. The TPU has three overflow interrupts, one for
each channel.
Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the
TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt
request is cleared by clearing the TCFU flag to 0. The TPU has two underflow interrupts, one each
for channels 1 and 2.
8.6 A/D Converter Activation
The A/D converter can be activated by the TGRA input capture/compare match for a channel.
If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a
TGRA input capture/compare match on a particular channel, a request to begin A/D conversion is
sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D
converter side at this time, A/D conversion is begun.
In the TPU, a total of three TGRA input capture/compare match interrupts can be used as A/D
converter conversion start sources, one for each channel.
Rev. 2.00, 03/04, page 183 of 508
8.7 Operation Timing
8.7.1 Input/Output Timing
TCNT Count Timing: Figure 8.27 shows TCNT count timing in internal clock operation, and
figure 8.28 shows TCNT count timing in external cloc k operation.
TCNT
TCNT
input clock
Internal clock
φ
N-1 N N+1 N+2
Falling edge Rising edge
Figure 8.27 Count Timing in Internal Clock Operation
TCNT
TCNT
input clock
External clock
φ
N-1 N N+1 N+2
Falling edge Rising edge Falling edge
Figure 8.28 Count Timing in External Clock Operation
Rev. 2.00, 03/04, page 184 of 508
Output Compare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin. After a match between TCNT and TGR, the compare match signal is not
generated until the TCNT input clock is generated.
Figure 8.29 sh ow s output compare output timing.
TGR
TCNT
TCNT
input clock
N
N N+1
Compare
match signal
TIOC pin
φ
Figure 8.29 Output Compare Output Timing
Input Capture Signal Timing: Figure 8.30 shows input capture signal timing.
TCNT
Input capture
input
N N+1 N+2
NN+2
TGR
Input capture
signal
φ
Figure 8.30 Input Capture Input Sign al Timing
Rev. 2.00, 03/04, page 185 of 508
Timing for Counter Clearing by Compare Match/Inpu t Capture: Figure 8.31 shows the
timing when counter clearing on compare match is specified, and figure 8.32 shows the timing
when counter clearing on in put capture is specified.
TCNT
Counter
clear signal
Compare
match signal
TGR N
N H'0000
φ
Figure 8.31 Counter Clear Timing (Compare Match)
TCNT
Counter clear
signal
Input capture
signal
TGR
N H'0000
N
φ
Figure 8.32 Counter Clear Timing (Input Capture)
Rev. 2.00, 03/04, page 186 of 508
Buffer Operation Timing: Figures 8.33 and 8.34 show the timing in buffer operation.
TGRA,
TGRB
Compare
match signal
TCNT
TGRC,
TGRD
nN
N
n n+1
φ
Figure 8.33 Buffer Operation Timing (Compare Match)
TGRA,
TGRB
TCNT
Input capture
signal
TGRC,
TGRD
N
n
n N+1
N
N N+1
φ
Figure 8.34 Buffer Operation Timing (Input Capture)
Rev. 2.00, 03/04, page 187 of 508
8.7.2 Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match: Figure 8.35 shows the timing for setting
of the TGF flag in TSR on compare match, and TGI interrupt request signal timin g.
TGR
TCNT
TCNT input
clock
N
N N+1
Compare
match signal
TGF flag
TGI interrupt
φ
Figure 8.35 TGI Interrupt Timing (Compare Match)
TGF Flag Setting Timing in Case of Input Capture: Figure 8.36 shows the timing for setting of
the TGF flag in TSR on input capture, and TGI interrupt request signal timing.
TGR
TCNT
Input capture
signal
N
N
TGF flag
TGI interrupt
φ
Figure 8.36 TGI Interrupt Timing (Input Capture)
Rev. 2.00, 03/04, page 188 of 508
TCFV Flag/TCFU Flag Setting Timing: Figure 8.37 shows the timing for setting of the TCFV
flag in TSR on overflow, and TCIV interrupt request signal timing.
Figure 8.38 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU
interrupt request signal timing.
Overflow
signal
TCNT
(overflow)
TCNT input
clock
H'FFFF H'0000
TCFV flag
TCIV interrupt
φ
Figure 8.37 TCIV Interrupt Setting Timing
Underflow
signal
TCNT
(underflow)
TCNT
input clock
H'0000 H'FFFF
TCFU flag
TCIU interrupt
φ
Figure 8.38 TCIU Interrupt Setting Timing
Rev. 2.00, 03/04, page 189 of 508
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. Figure 8.39 shows the timing for status flag clearing by the CPU.
Status flag
Write signal
Address TSR address
Interrupt
request
signal
TSR write cycle
T1 T2
φ
Figure 8.39 Timing for Status Flag Clearing by CPU
Rev. 2.00, 03/04, page 190 of 508
8.8 Usage Notes
8.8.1 Module Stop Mode Setting
TPU operation can be disabled or enabled using the module stop control register. The initial
setting is for TPU operation to be halted. Register access is enabled by clearing module stop
mode. For details, see section 19, Power-Down Modes.
8.8.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower
pulse widths.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 8.40 shows the input clock
conditions in phase counting mode.
Overlap
Phase
differ-
ence
Phase
differ-
ence
Overlap
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width Pulse width
Pulse width Pulse width
Notes: Phase difference and overlap
Pulse width
: 1.5 states or more
: 2.5 states or more
Figure 8.40 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Rev. 2.00, 03/04, page 191 of 508
8.8.3 Caution on Period Setting
When counter clea ring on compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
f =
φ
(N + 1)
Where f: Counter frequency
φ: Operating frequency
N: TGR set value
8.8.4 Contention between TCNT Write and Clear Operations
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes
precedence and the TCNT write is not performed.
Figure 8.41 shows the timing in this case.
Counter clear
signal
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T1 T2
N H'0000
Figure 8.41 Contention between TCNT Write and Clear Operations
Rev. 2.00, 03/04, page 192 of 508
8.8.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented.
Figure 8.42 shows the timing in this case.
TCNT input
clock
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T1 T2
NM
TCNT write data
Figure 8.42 Contention between TCNT Write and Increment Operations
Rev. 2.00, 03/04, page 193 of 508
8.8.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is inhibited. A compare match does not occur even if the previous
value is written.
Figure 8.43 shows the timing in this case.
Compare
match signal
Write signal
Address
φ
TGR address
TCNT
TGR write cycle
T1 T2
NM
TGR write data
TGR
N N+1
Inhibited
Figure 8.43 Contentio n between TGR Write and Compare Matc h
Rev. 2.00, 03/04, page 194 of 508
8.8.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation will be that in the buffer prior to the write.
Figure 8.44 shows the timing in this case.
Compare
match signal
Write signal
Address
φ
Buffer register
address
Buffer
register
TGR write cycle
T1 T2
N
TGR
NM
Buffer register write data
Figure 8.44 Contention between Buffer Register Write and Compare Match
Rev. 2.00, 03/04, page 195 of 508
8.8.8 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be that in the buffer after input capture transfer.
Figure 8.45 shows the timing in this case.
Input capture
signal
Read signal
Address
φ
TGR address
TGR
TGR read cycle
T1 T2
M
Internal
data bus
X M
Figure 8.45 Contention between TGR Read and Input Capture
Rev. 2.00, 03/04, page 196 of 508
8.8.9 Contention between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 8.46 shows the timing in this case.
Input capture
signal
Write signal
Address
φ
TCNT
TGR write cycle
T1 T2
M
TGR
M
TGR address
Figure 8.46 Contentio n be twee n TGR Write and Input Capture
Rev. 2.00, 03/04, page 197 of 508
8.8.10 Contention between Buffer Register Write and Input Capture
If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer regist er is not performed.
Figure 8.47 shows the timing in this case.
Input capture
signal
Write signal
Address
φ
TCNT
Buffer register write cycle
T1 T2
N
TGR
N
M
M
Buffer
register
Buffer register
address
Figure 8.47 Contention between Buffer Register Write and Input Capture
Rev. 2.00, 03/04, page 198 of 508
8.8.11 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 8.48 shows th e operation timing when a TGR compare match is specified as the clearing
source, and when H'FFFF is set in TGR.
Counter
clear signal
TCNT input
clock
φ
TCNT
TGF
Disabled
TCFV
H'FFFF H'0000
Figure 8.48 Contention between Overflow and Counter Clearing
Rev. 2.00, 03/04, page 199 of 508
8.8.12 Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 8.49 shows the operation timing when there is contention between TCNT write and
overflow.
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T1 T2
H'FFFF M
TCNT write data
TCFV flag
Figure 8.49 Contentio n be twee n TCNT Write and Overflow
8.8.13 Multiplexing of I/O Pins
In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin
with the TIOCD0 I/O pin, th e TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input
pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not
be performed from a multi plexed pin.
8.8.14 Interrupts in Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source. Interrupts should therefore be disabled before entering module stop
mode.
8.8.15 Interrupts in Subactive Mode/Watch Mode
If subactive mode/watch mode is entered when an interrupt has been requested, it will not be
possible to clear the CPU interrupt source. Interrupts should therefore be disabled before entering
subactive mode/watch mode.
Rev. 2.00, 03/04, page 200 of 508
Rev. 2.00, 03/04, page 201 of 508
Section 9 Watchdog Timer
The watchdog timer (WDT_0, WDT_1) is an 8-bit timer that can generate an internal reset signal
for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it
to overflow.
When this watchdog function is not needed, the WDT can be used as an in terval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
The block diagram of the WDT_0 is shown in figure 9. 1. The block diagra m of the WD T_ 1 is
shown in figure 9.2.
9.1 Features
• Selectable f rom eight counter input clocks.
• Switchable between watchdog timer mode and interval timer mode
In watchdog timer mode
• If the counter overflows, it is possible to select whether this LSI is internally reset or the WDT
generates an internal NMI interrupt.
In interval timer mode
• If the counter overflows, the WDT generates an interval timer interrupt (WOVI).
WDT0105A_000120020200
Rev. 2.00, 03/04, page 202 of 508
Overflow
Interrupt
control
WOVI
(interrupt request
signal)
Internal reset signal*Reset
control
RSTCSR TCNT_0 TCSR_0
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock Clock
select
Internal clock
sources
Bus
interface
Module bus
TCSR:
TCNT:
RSTCSR:
Note: * An internal reset signal can be generated by setting the register.
Timer control/status register
Timer counter
Reset control/status register
WDT
[Legend]
Internal bus
Figure 9.1 Block Diagram of W DT_ 0
Overflow
Interrupt
control
WOVI
(interrupt request
signal)
Internal NMI
Internal reset signal
Internal reset signal*
Reset
control
TCNT_1 TSCR_1
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
φ
SUB
/2
φ
SUB
/4
φ
SUB
/8
φ
SUB
/16
φ
SUB
/32
φ
SUB
/64
φ
SUB
/128
φ
SUB
/256
Clock
Clock
select
Internal clock
Bus
interface
Module bus
TCSR:
TCNT:
Note: * An internal reset signal can be generated by setting the register.
The generated reset is a power-on reset.
Timer control/status register
Timer counter
WDT
[Legend]
Internal bus
Figure 9.2 Block Diagram of W DT_ 1
Rev. 2.00, 03/04, page 203 of 508
9.2 Register Descriptions
The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and
RSTCSR have to be written to by a different method to normal registers. For details, see section
9.5.1, Notes on Regi ster Access.
• Timer control/status register_0 (TCSR_0)
• Timer counter_0 (TCNT_0)
• Timer control/status register_1 (TCSR_1)
• Timer counter_1 (TCNT_1)
• Reset con trol/statu s register (RSTCSR)
9.2.1 Timer Counter 0 and 1 (T CNT_0 and TCNT_1)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 by a reset, when the
TME bit in TCSR is cleared to 0.
9.2.2 Timer Control / Stat us Register 0 and 1 (TCSR_ 0 and TCSR_1)
TCSR selects the clock source to be input to TCNT, and selecting th e timer mode.
• TCSR_0
Bit Bit Name Initial
Value R/W Description
7 OVF 0 R/(W)* Overflow Flag
Indicates that TCNT has overflowed. Only a write of 0 is
permitted, to clear the flag.
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically by
the internal reset.
[Clearing condition]
Cleared by reading TCSR when OVF = 1, then writing 0
to OVF
6 WT/IT 0 R/W Timer Mode Select
Selects whether the WDT is used as a watchdog timer
or interval timer.
0: Interval timer mode
1: Watchdog timer mode
Rev. 2.00, 03/04, page 204 of 508
Bit Bit Name Initial
Value R/W Description
5 TME 0 R/W Timer Enable
When this bit is set to 1, TCNT starts counting. When
this bit is cleared, TCNT stops counting and is initialized
to H'00.
4, 3 All 1 Reserved
These bits are always read as 1 and cannot be
modified.
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 0 to 2
Selects the clock source to be input to TCNT. The
overflow frequency for φ = 20 MHz is enclosed in
parentheses.
000: Clock φ/2 (frequency: 25.6 µs)
001: Clock φ/64 (frequency: 819.2 µs)
010: Clock φ/128 (frequency: 1.6 ms)
011: Clock φ/512 (frequency: 6.6 ms)
100: Clock φ/2048 (frequency: 26.2 ms)
101: Clock φ/8192 (frequency: 104.9 ms)
110: Clock φ/32768 (frequency: 419.4 ms)
111: Clock φ/131072 (frequency: 1.68 s)
Note: * Only 0 can be written for flag clearing.
• TCSR_1
Bit Bit Name Initial
Value R/W Description
7 OVF 0 R/(W)* Overflow Flag
Indicates that TCNT has overflowed from H'FF to H'00.
Only a write of 0 is permitted, to clear the flag.
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically by
the internal reset.
[Clearing condition]
Cleared by reading TCSR when OVF = 1, then writing 0
to OVF
Rev. 2.00, 03/04, page 205 of 508
Bit Bit Name Initial
Value R/W Description
6 WT/IT 0 R/W Timer Mode Select
Selects whether the WDT is used as a watchdog timer
or interval timer.
0: Interval timer mode
1: Watchdog timer mode
5 TME 0 R/W Timer Enable
When this bit is set to 1, TCNT starts counting. When
this bit is cleared, TCNT stops counting and is initialized
to H'00.
4 PSS 0 R/W Prescaler Select
Selects the clock source to be input to TCNT.
0: Counts the divided clock of φbased prescaler
(PSM)
1: Counts the divided clock of φSUBbased prescaler
(PSS)
3 RST/NMI 0 R/W Reset or NMI
Selects whether an internal reset request or an NMI
interrupt request when the TCNT overflows during the
watchdog timer mode.
0: NMI interrupt request
1: Internal reset request
Rev. 2.00, 03/04, page 206 of 508
Bit Bit Name Initial
Value R/W Description
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2 to 0
Selects the clock source to be input to TCNT. The
overflow cycle for φ = 20 MHz (5-MHz input to this LSI
multiplied by four, and φSUB = 39.1 kHz) is enclosed in
parentheses. The overflow cycle is the period from
which TCNT starts counting and until it overflows.
When PSS = 0:
000: φ/2 (cycle: 25.6 µs)
001: φ/64 (cycle: 819.2 ms)
010: φ/128 (cycle: 1.6 ms)
011: φ/512 (cycle: 6.6 ms)
100: φ/2048 (cycle: 26.2 ms)
101: φ/8192 (cycle: 104.9 ms)
110: φ/32768 (cycle: 419.4 ms)
111: φ/131072 (cycle: 1.68s)
When PSS = 1:
000: φSUB/2 (cycle: 13.1 ms)
001: φSUB/4 (cycle: 26.2 ms)
010: φSUB/8 (cycle: 52.4 ms)
011: φSUB/16 (cycle: 104.9 ms)
100: φSUB/32 (cycle: 209.7 ms)
101: φSUB/64 (cycle: 419.4 ms)
110: φSUB/128 (cycle: 838.9 ms)
111: φSUB/256 (cycle: 1.6777 s)
Note: * Only 0 can be written for flag clearing.
Rev. 2.00, 03/04, page 207 of 508
9.2.3 Reset Control/Status Register (RSTCSR)
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
and not by the WDT internal reset signal caused by overflows.
Bit Bit Name Initial
Value R/W Description
7 WOVF 0 R/(W)* Watchdog Overflow Flag
This bit is set when TCNT overflows in watchdog timer
mode. This bit cannot be set in interval timer mode, and
only 0 can be written.
[Setting condition]
Set when TCNT overflows (changed from H'FF to H'00)
in watchdog timer mode
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1, and
then writing 0 to WOVF
6 RSTE 0 R/W Reset Enable
Specifies whether or not a reset signal is generated in
the chip if TCNT overflows during watchdog timer
operation.
0: Reset signal is not generated even if TCNT overflows
(Though this LSI is not reset, TCNT and TCSR in
WDT are reset)
1: Reset signal is generated if TCNT overflows
5 RSTS 0 R/W Reset Select
Selects the internal reset type to be generated if TCNT
overflows during watchdog timer operation.
0: Power-on reset
1: Setting prohibited
4 to 0 — All 1 — Reserved
These bits are always read as 1 and cannot be
modified.
Note: * Only 0 can be written for flag clearing.
Rev. 2.00, 03/04, page 208 of 508
9.3 Operation
9.3.1 Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1.
When the WDT is used as a watchdog timer, and if TCNT overflows without being rewritten
because of a system malfunction or other error, a WDTOVF signal is output.
TCNT does not overflow while the system is operating normally. Software must prevent TCNT
overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs.
In watchdog timer mode, the WDT can internally reset this LSI with a WDTOVF signal.
When the RSTE bit of the RSTCSR is set to 1, and if the TCNT overflows, an internal reset signal
for this LSI is issued at the same time as a WDTOVF signal. In this case, select power-on reset by
setting the RSTS bit of the RSTCSR to 0.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a
WDT overflow , the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
The WDTOVF signal is output for 132 states when the RSTE bit = 1 of RSTCSR, and for 130
states when the RSTE bit = 0.
When the TCNT overflows in watchdog timer mode, the WOVF bit of the RSTCSR is set to 1.
If the RSTE bit of the RSTCSR has been set to 1, an intern al reset signal for the entire LSI is
generated at TCNT overflow.
Rev. 2.00, 03/04, page 209 of 508
TCNT value
H'00 Time
H'FF
WT/IT = 1
TME = 1
Write H'00
to TCNT
WT/IT = 1
TME = 1
Write H'00
to TCNT
518 states
Internal reset signal*
WT/IT:
TME:
Notes: 1.
2.
After the WOVF bit becomes 1, it is cleared to 0 by an internal reset.
The internal reset signal is generated only if the RSTE bit is set to 1.
Overflow
Internal reset is
generated
WOVF = 1*
Timer mode select bit
Timer enable bit
[Legend]
2
1
Figure 9.3 (a) WDT_0 Operation in Watchdog Timer Mode
TCNT value
H'00 Time
H'FF
WT/IT = 1
TME = 1
Write H'00
to TCNT
WT/IT = 1
TME = 1
Write H'00
to TCNT
515/516 states
WT/IT:
TME:
[Legend]
Overflow
Internal reset
is generated
WOVF = 1*
Timer mode select bit
Timer enable bit
1
Internal reset signal*
2
Notes: 1.
2.
After the WOVF bit becomes 1, it is cleared to 0 by an internal reset.
The internal reset signal is generated only if the RSTE bit is set to 1.
Figure 9.3 (b) WDT_1 Operation in Watchdog Timer Mode
Rev. 2.00, 03/04, page 210 of 508
9.3.2 Interval Timer Mode
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each
time the TCNT overflows. Therefore, an interrupt can be generated at intervals.
When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested
at the time the OVF bit of the TCSR is set to 1.
TCNT value
H'00 Time
H'FF
WT/IT=0
TME=1
WOVI
Overflow Overflow Overflow Overflow
[Legend]
WOVI: Interval timer interrupt request generation
WOVI WOVI WOVI
Figure 9.4 Operation in Interval Timer Mode
Rev. 2.00, 03/04, page 211 of 508
9.4 Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
If an NMI interrupt request has been chosen in watchdog timer mode, an NMI interrupt request is
generated when the TCNT overflows.
Table 9.1 WDT Interrupt Source
Name Interrupt Source Interrupt Flag
WOVI TCNT overflow (interval timer mode) OVF
NMI TCNT overflow (watchdog timer mode) OVF
9.5 Usage Notes
9.5.1 Notes on Register Access
The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for wr iting to and reading these registers are given
below.
Writing to TCNT, TCSR, and RSTCSR
These registers must be written to by a word transfer instruction. They cannot be written to by a
byte transfer instruction.
TCNT and TCSR both have the same write address. Therefore, the relative condition shown in
figure 9.5 needs to be satisfied in order to write to TCNT or TCSR. The transfer instruction writes
the lower byte data to TCNT or TCSR according to the satisfied condition.
To write to RSTCSR, execute a word transfer instruction for address H'FF76. A byte transfer
instruction cannot write to RSTCSR.
The method of writing 0 to the WOVF bit d iffers from that of writing to the RSTE and RSTS bits.
To write 0 to the WOVF bit, satisfy the condition shown in figure 9.5. If satisfied, the transfer
instruction clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write to
the RSTE and RSTS bits, satisfy the condition shown in figure 9.5. If satisfied, the transfer
instruction writes the values in bits 5 and 6 of the lower byte into the RSTE and RSTS bits,
respectively, but has no effect on the WOVF bit.
Rev. 2.00, 03/04, page 212 of 508
TCNT write
Writing to RSTE and RSTS bits
TCSR write
Writing 0 to WOVF bit
Address:
Address:
15 8 7 0
H'5A
H'FF74
H'FF76 Write data
15 8 7 0
H'5A
H'FF74
H'FF76 Write data or H'00
Figure 9.5 Writing to TCNT, TCSR, and RSTCSR (example for WDT0)
Reading TCNT, TCSR, and RSTCSR (WDT0)
These registers are read in the same way as other registers. The read addresses are H'FF74 for
TCSR, H'FF75 for TCNT, and H'FF77 for RSTCSR.
9.5.2 Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 9.6 shows this operation.
Address
φ
Internal write signal
TCNT input clock
TCNT NM
T1T2
TCNT write cycle
Counter write data
Figure 9.6 Contention between TCNT Write and Increment
Rev. 2.00, 03/04, page 213 of 508
9.5.3 Changing Value of CKS2 to CKS0
If bits CKS0 to CKS2 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation . Software must be used to stop the watchdog timer (by clearing the TME bit to
0) before changing the value of bits CKS0 to CKS2.
9.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer while the WDT is operating, errors
could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing
the TME bit to 0) before switching the mode.
9.5.5 Internal Reset in Watchdog Timer Mode
This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer operation, however TCNT and TCSR of the WDT are reset.
TCNT, TCSR, or RSTCR cannot be written to for 132 states following an overflow. During this
period, any attempt to read the WOVF flag is not acknowledged. Accordingly, wait 132 states
after overflow to write 0 to the WOVF flag for clearing.
9.5.6 OVF Flag Clearing in Interval Timer Mode
When setting of the OVF flag is in con tention with reading of the OVF flag in interval timer
mode, the OVF flag may not be c l eared ev en when 0 is writte n to it afte r the OVF flag has been
read as 1. When there is a possibility of contention between the setting and reading of the OVF
flag when the OVF flag is polled while the interval timer interrupt is disabled , 0 should be only
written to the OVF after reading the OVF at least twice in its '1' state to ensure clearing of the flag.
Rev. 2.00, 03/04, page 214 of 508
Rev. 2.00, 03/04, page 215 of 508
Section 10 Serial Communication Interface (SCI)
This LSI has two independent serial co mmunication interface (SCI) channels. The SCI can handle
both asynchronous and clocked synchronous serial communication. Serial data communication
can be carried out using standard asynchronous communication chips such as a Universal
Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface
Adapter (ACIA). A function is also provided for serial communication between processors
(multiprocessor communication function). The SCI also supports an IC card (Smart Card)
interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface
extension function.
Figure 10.1 show s a block diagram of the SC I.
10.1 Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
External clock can be selected as a transfer clock source (except for in Smart Card interface
mode).
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources
Transmit-end, transmit-data-empty, receive-data-full, and receive error — that can issue
requests.
• Module stop mode can be set
Asynchro no us mode
• Data length: 7 or 8 bits
• Stop b it length: 1 or 2 bits
• Parity: Even, odd, or none
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RxD pin leve l directly in the case of a
framing error
Rev. 2.00, 03/04, page 216 of 508
Clocked Synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors detected
Smart Card Interface
• Automatic transmission of error signal (parity error) in receive mode
• Error signal detection and automatic data retransmission in transmit mode
• Direct convention and inverse convention both supported
RxD
TxD
SCK
Clock
External clock
φ
φ/4
φ/16
φ/64
TEI
TXI
RXI
ERI
RSR:
RDR:
TSR:
TDR:
SMR:
SCR:
SSR:
SCMR:
BRR:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Smart card mode register
Bit rate register
SCMR
SSR
SCR
SMR
Transmission/
reception control
Baud rate
generator
BRR
Module data bus
Bus interface
RDR
TSRRSR
Parity generation
Parity check
[Legend]
TDR
Internal
data bus
Figure 10.1 Block Diagram of SCI
Rev. 2.00, 03/04, page 217 of 508
10.2 Input/Output Pins
Table 10.1 shows the serial pins for each SCI channel.
Table 10.1 Pin Configuration
Channel Pin Name* I/O Function
SCK0 I/O SCI0 clock input/output
RxD0 Input SCI0 receive data input
0
TxD0 Output SCI0 transmit data output
SCK1 I/O SCI1 clock input/output
RxD1 Input SCI1 receive data input
1
TxD1 Output SCI1 transmit data output
Note: * Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the
channel designation.
10.3 Register Descriptions
The SCI has the following registers for each channel. The serial mode register (SMR), serial status
register (SSR), and serial control register (SCR) are described separately for normal serial
communication interface mode and Smart Card interface mode because their bit functions differ in
part.
• Receive shift register (RSR)
• Receive data register (RDR)
• Transmit data register (TDR)
• Transmit shift register (TSR)
• Serial mode register (SMR)
• Serial control register (SCR)
• Serial status register (SSR)
• Smart card mode register (SCMR)
• Bit rate register (BRR)
Rev. 2.00, 03/04, page 218 of 508
10.3.1 Receive Shift Register (RSR)
RSR is a shift register that is used to receive serial data input to the RxD pin and convert it into
parallel data. When one byte of data has been received, it is transferred to RDR automatically.
RSR cannot be directly accessed by the CPU.
10.3.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores received data. When the SCI has received one byte of serial
data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is
receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive
operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only
once. RDR cannot be written to by th e CPU.
10.3.3 Transmit Data Regi s ter (T DR )
TDR is an 8-bit register that stores data for transmission. When the SCI detects that TSR is empty,
it transfers the transmit data written in TDR to TSR and starts transmission. The doub le-buffered
structure of TDR an d TSR enables continuous ser ial transmission. If the next transmit data has
already been written to TDR during serial transmission, the SCI transfers the written data to TSR
to continue transmission. Although TDR can be read or written to by the CPU at all times, to
achieve reliable serial transmission, write transmit data to TDR only once after confirming that the
TDRE bit in SSR is set to 1.
10.3.4 Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first
transfers transmit data from TDR to TSR, and then sends the data to the TxD pin. TSR cannot be
directly accessed by the CPU.
Rev. 2.00, 03/04, page 219 of 508
10.3.5 Serial Mode Register (SM R)
SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source.
Some bit functions of SMR differ between normal serial communication interface mode and Smart
Card interface mode.
• Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit Bit Name Initial
Value R/W Description
7 C/A 0 R/W Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
6 CHR 0 R/W Character Length (enabled only in asynchronous mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length.
The MSB (bit 7) of TDR is not transmitted in
transmission.
In clocked synchronous mode, a fixed data length of 8
bits is used.
5 PE 0 R/W Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception. For a multiprocessor format,
parity bit addition and checking are not performed
regardless of the PE bit setting.
4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked. If the
second stop bit is 0, it is treated as the start bit of the
next transmit character.
Rev. 2.00, 03/04, page 220 of 508
Bit Bit Name Initial
Value R/W Description
2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous
mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and O/E
bit settings are invalid in multiprocessor mode.
1
0
CKS1
CKS0
0
0
R/W
R/W
Clock Select 0 and 1
These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relationship between the bit rate register setting
and the baud rate, see section 10.3.9, Bit Rate Register
(BRR). n is the decimal representation of the value of n
in BRR (see section 10.3.9, Bit Rate Register (BRR)).
• Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit Bit Name Initial
Value R/W Description
7 GM 0 R/W GSM Mode
When this bit is set to 1, the SCI operates in GSM
mode. In GSM mode, the timing of the TEND setting is
advanced by 11.0 etu (Elementary Time Unit: the time
for transfer of one bit), and clock output control mode
addition is performed. For details, see section 10.7.8,
Clock Output Control.
6 BLK 0 R/W When this bit is set to 1, the SCI operates in block
transfer mode. For details on block transfer mode, see
section 10.7.3, Block Transfer Mode.
5 PE 0 R/W Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data in transmission, and the parity bit is
checked in reception. In Smart Card interface mode,
this bit must be set to 1.
Rev. 2.00, 03/04, page 221 of 508
Bit Bit Name Initial
Value R/W Description
4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
For details on setting this bit in Smart Card interface
mode, see section 10.7.2, Data Format (Except for
Block Transfer Mode).
3
2
BCP1
BCP0
0
0
R/W
R/W
Basic Clock Pulse 1 and 0
These bits specify the number of basic clock periods in
a 1-bit transfer interval on the Smart Card interface.
00: 32 clock (S = 32)
01: 64 clock (S = 64)
10: 372 clock (S = 372)
11: 256 clock (S = 256)
For details, see section 10.7.4, Receive Data Sampling
Timing and Reception Margin in Smart Card Interface
Mode. S stands for the value of S in BRR (see section
10.3.9, Bit Rate Register (BRR)).
1
0
CKS1
CKS0
0
0
R/W
R/W
Clock Select 0 and 1
These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relationship between the bit rate register setting
and the baud rate, see section 10.3.9, Bit Rate Register
(BRR). n is the decimal representation of the value of n
in BRR (see section 10.3.9, Bit Rate Register (BRR)).
Rev. 2.00, 03/04, page 222 of 508
10.3.6 Serial Control Register (SCR)
SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also
used to selection of the transfer clock source. For details on interrupt requests, see section 10.8,
Interrupts. Some bit functions of SCR differ between normal serial communication interface mode
and Smart Card interface mode.
• Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit Bit Name Initial
Value R/W Description
7 TIE 0 R/W Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled.
6 RIE 0 R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
5 TE 0 R/W Transmit Enable
When this bit s set to 1, transmission is enabled.
4 RE 0 R/W Receive Enable
When this bit is set to 1, reception is enabled.
3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically cleared
and normal reception is resumed. For details, see
section 10.5, Multiprocessor Communication Function.
2 TEIE 0 R/W Transmit End Interrupt Enable
When this bit is set to 1, TEI interrupt request is
enabled.
Rev. 2.00, 03/04, page 223 of 508
Bit Bit Name Initial
Value R/W Description
1
0
CKE1
CKE0
0
0
R/W
R/W
Clock Enable 0 and 1
Selects the clock source and SCK pin function.
Asynchronous mode
00: Internal clock
SCK pin functions as I/O port
01: Internal clock
Outputs a clock of the same frequency as the bit
rate from the SCK pin.
1X: External clock
Inputs a clock with a frequency 16 times the bit rate
from the SCK pin.
Clocked synchronous mode
0X: Internal clock (SCK pin functions as clock output)
1X: External clock (SCK pin functions as clock input)
[Legend]
X: Don't care
• Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit Bit Name Initial
Value R/W Description
7 TIE 0 R/W Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is
enabled.
6 RIE 0 R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
5 TE 0 R/W Transmit Enable
When this bit is set to 1, transmission is enabled.
4 RE 0 R/W Receive Enable
When this bit is set to 1, reception is enabled.
3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
Write 0 to this bit in Smart Card interface mode.
2 TEIE 0 R/W Transmit End Interrupt Enable
Write 0 to this bit in Smart Card interface mode.
Rev. 2.00, 03/04, page 224 of 508
Bit Bit Name Initial
Value R/W Description
1
0
CKE1
CKE0
0
0
R/W Clock Enable 0 and 1
Enables or disables clock output from the SCK pin. The
clock output can be dynamically switched in GSM
mode. For details, see section 10.7.8, Clock Output
Control.
When the GM bit in SMR is 0:
00: Output disabled (SCK pin can be used as an I/O
port pin)
01: Clock output
1X: Reserved
When the GM bit in SMR is 1:
00: Output fixed low
01: Clock output
10: Output fixed high
11: Clock output
[Legend]
X: Don't care
Rev. 2.00, 03/04, page 225 of 508
10.3.7 Serial Status Register (SS R )
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit
functions of SSR differ between normal serial communication interface mode and Smart Card
interface mode.
• Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit Bit Name Initial
Value R/W Description
7 TDRE 1 R/(W)* Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR
[Clearing condition]
• When 0 is written to TDRE after reading TDRE = 1
6 RDRF 0 R/(W)* Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
• When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing condition]
• When 0 is written to RDRF after reading RDRF = 1
The RDRF flag is not affected and retains its value
when the RE bit in SCR is cleared to 0.
5 ORER 0 R/(W)* Overrun Error
[Setting condition]
• When the next serial reception is completed while
RDRF = 1
[Clearing condition]
• When 0 is written to ORER after reading ORER = 1
Rev. 2.00, 03/04, page 226 of 508
Bit Bit Name Initial
Value R/W Description
4 FER 0 R/(W)* Framing Error
[Setting condition]
• When the stop bit is 0
[Clearing condition]
• When 0 is written to FER after reading FER = 1
In 2-stop-bit mode, only the first stop bit is checked.
3 PER 0 R/(W)* Parity Error
[Setting condition]
• When a parity error is detected during reception
[Clearing condition]
• When 0 is written to PER after reading PER = 1
2 TEND 1 R Transmit End
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a
1-byte serial transmit character
[Clearing condition]
• When 0 is written to TDRE after reading TDRE = 1
1 MPB 0 R Multiprocessor Bit
MPB stores the multiprocessor bit in the receive data.
When the RE bit in SCR is cleared to 0 its state is
retained.
0 MPBT 0 R/W Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit data.
Note: Only 0 for clearing the flag can be written.
Rev. 2.00, 03/04, page 227 of 508
• Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit Bit Name Initial
Value R/W Description
7 TDRE 1 R/(W)* Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data
can be written to TDR
[Clearing condition]
• When 0 is written to TDRE after reading TDRE = 1
6 RDRF 0 R/(W)* Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
• When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing condition]
• When 0 is written to RDRF after reading RDRF = 1
The RDRF flag is not affected and retains its value
when the RE bit in SCR is cleared to 0.
5 ORER 0 R/(W)* Overrun Error
[Setting condition]
• When the next serial reception is completed while
RDRF = 1
[Clearing condition]
• When 0 is written to ORER after reading ORER = 1
4 ERS 0 R/(W)* Error Signal Status
[Setting condition]
• When the low level of the error signal is sampled
[Clearing condition]
• When 0 is written to ERS after reading ERS = 1
Rev. 2.00, 03/04, page 228 of 508
Bit Bit Name Initial
Value R/W Description
3 PER 0 R/(W)* Parity Error
[Setting condition]
• When a parity error is detected during reception
[Clearing condition]
• When 0 is written to PER after reading PER = 1
2 TEND 1 R Transmit End
This bit is set to 1 when no error signal has been sent
back from the receiving end and the next transmit data
is ready to be transferred to TDR.
[Setting conditions]
• When the TE bit in SCR is 0 and the ERS bit is also
0
• When the ESR bit is 0 and the TDRE bit is 1 after
the specified interval following transmission of 1-
byte data.
The timing of bit setting differs according to the
register setting as follows:
When GM = 0 and BLK = 0, 2.5 etu after
transmission starts
When GM = 0 and BLK = 1, 1.5 etu after
transmission starts
When GM = 1 and BLK = 0, 1.0 etu after
transmission starts
When GM = 1 and BLK = 1, 1.0 etu after
transmission starts
[Clearing condition]
• When 0 is written to TDRE after reading TDRE = 1
1 MPB 0 R Multiprocessor Bit
This bit is not used in Smart Card interface mode.
0 MPBT 0 R/W Multiprocessor Bit Transfer
Write 0 to this bit in Smart Card interface mode.
Note: Only 0 for clearing the flag can be written.
Rev. 2.00, 03/04, page 229 of 508
10.3.8 Smart Card Mode Regi s ter (SCMR)
SCMR is a register that selects Smart Card interface mode and its format.
Bit Bit Name
Initial
Value R/W Description
7 to 4 All 1 Reserved
These bits are always read as 1.
3 SDIR 0 R/W Smart Card Data Transfer Direction
Selects the serial/parallel conversion format.
0: LSB-first in transfer
1: MSB-first in transfer
The bit setting is valid only when the transfer data
format is 8 bits. For 7-bit data, LSB-first is fixed.
2 SINV 0 R/W Smart Card Data Invert
Specifies inversion of the data logic level. The SINV bit
does not affect the logic level of the parity bit. To invert
the parity bit, invert the O/E bit in SMR.
0: TDR contents are transmitted as they are. Receive
data is stored as it is in RDR
1: TDR contents are inverted before being transmitted.
Receive data is stored in inverted form in RDR
1 1 Reserved
This bit is always read as 1.
0 SMIF 0 R/W Smart Card Interface Mode Select
This bit is set to 1 to make the SCI operate in Smart
Card interface mode.
0: Normal asynchronous mode or clocked synchronous
mode
1: Smart card interface mode
Rev. 2.00, 03/04, page 230 of 508
10.3.9 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 10.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Table 10.2 The Relationships between The N Setting in BRR and Bit Rate B
Mode Bit Rate Error
Asynchronous
Mode
B = 64 × 2
2n-1
× (N + 1)
φ × 10
6
Error (%) = { B × 64 × 2
2n-1
× (N + 1) -1 } × 100
φ × 10
6
Clocked
Synchronous
Mode
B = 8 × 2 2n-1 × (N + 1)
φ × 106
Smart Card
Interface Mode
B = S × 2 2n-1 × (N + 1)
φ × 106
Error (%) = { B × S × 2
2n-1
× (N + 1) -1 } × 100
φ × 10
6
[Legend]
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following tables.
SMR Setting SMR Setting
CKS1 CKS0 n BCP1 BCP0 S
0 0 0 0 0 32
0 1 1 0 1 64
1 0 2 1 0 372
1 1 3 1 1 256
Table 10.3 shows sample N settings in BRR in normal asynchronou s mode. Table 10.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 10.6 shows sample N
settings in BRR in clocked synchronous mode. Table 10.8 show s sample N settings in BRR in
Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in
a 1-bit transfer interval) can be selected. For details, see section 10.7.4, Receive Data Sampling
Timing and Reception Margin in Smart Card Interface Mode. Tables 10.5 and 10.7 show the
maximum bit rates with external clock input.
Rev. 2.00, 03/04, page 231 of 508
Table 10.3 BRR Settings for Various Bi t Ra tes (A sy n c hron ou s Mo de) (1 )
Operating Frequency φ (MHz)
4 4.9152 5 6
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 70 0.03 2 86 0.31 2 88 –0.25 2 106 –0.44
150 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16
300 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16
600 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16
1200 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16
2400 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16
4800 0 25 0.16 0 31 0.00 0 32 –1.36 0 38 0.16
9600 0 12 0.16 0 15 0.00 0 15 1.73 0 19 –2.34
19200 0 7 0.00 0 7 1.73 0 9 –2.34
31250 0 3 0.00 0 4 –1.70 0 4 0.00 0 5 0.00
38400 0 3 0.00 0 3 1.73 0 4 –2.34
Operating Frequency φ (MHz)
6.144 7.3728 8 9.8304
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 108 0.08 2 130 –0.07 2 141 0.03 2 174 –0.26
150 2 79 0.00 2 95 0.00 2 103 0.16 2 127 0.00
300 1 159 0.00 1 191 0.00 1 207 0.16 1 255 0.00
600 1 79 0.00 1 95 0.00 1 103 0.16 1 127 0.00
1200 0 159 0.00 0 191 0.00 0 207 0.16 0 255 0.00
2400 0 79 0.00 0 95 0.00 0 103 0.16 0 127 0.00
4800 0 39 0.00 0 47 0.00 0 51 0.16 0 63 0.00
9600 0 19 0.00 0 23 0.00 0 25 0.16 0 31 0.00
19200 0 9 0.00 0 11 0.00 0 12 0.16 0 15 0.00
31250 0 5 2.40 0 7 0.00 0 9 –1.70
38400 0 4 0.00 0 5 0.00 0 7 0.00
Rev. 2.00, 03/04, page 232 of 508
Table 10.3 BRR Settings for Various Bi t Ra tes (A sy n c hron ou s Mo de) (2 )
Operating Frequency φ (MHz)
10 12 12.288 14
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 177 –0.25 2 212 0.03 2 217 0.08 2 248 –0.17
150 2 129 0.16 2 155 0.16 2 159 0.00 2 181 0.13
300 2 64 0.16 2 77 0.16 2 79 0.00 2 90 0.13
600 1 129 0.16 1 155 0.16 1 159 0.00 1 181 0.13
1200 1 64 0.16 1 77 0.16 1 79 0.00 1 90 0.13
2400 0 129 0.16 0 155 0.16 0 159 0.00 0 181 0.13
4800 0 64 0.16 0 77 0.16 0 79 0.00 0 90 0.13
9600 0 32 –1.36 0 38 0.16 0 39 0.00 0 45 –0.93
19200 0 15 1.73 0 19 –2.34 0 19 0.00 0 22 –0.93
31250 0 9 0.00 0 11 0.00 0 11 2.40 0 13 0.00
38400 0 7 1.73 0 9 –2.34 0 9 0.00
Operating Frequency φ (MHz)
14.7456 16 17.2032 18
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 3 64 0.70 3 70 0.03 3 75 0.48 3 79 –0.12
150 2 191 0.00 2 207 0.13 2 223 0.00 2 233 0.16
300 2 95 0.00 2 103 0.13 2 111 0.00 2 116 0.16
600 1 191 0.00 1 207 0.13 1 223 0.00 1 233 0.16
1200 1 95 0.00 1 103 0.13 1 111 0.00 1 116 0.16
2400 0 191 0.00 0 207 0.13 0 223 0.00 0 233 0.16
4800 0 95 0.00 0 103 0.13 0 111 0.00 0 116 0.16
9600 0 47 0.00 0 51 0.13 0 55 0.00 0 58 –0.69
19200 0 23 0.00 0 25 0.13 0 27 0.00 0 28 1.02
31250 0 14 –1.70 0 15 0.00 0 13 1.20 0 17 0.00
38400 0 11 0.00 0 12 0.13 0 13 0.00 0 14 –2.34
Rev. 2.00, 03/04, page 233 of 508
Table 10.3 BRR Settings for Various Bi t Ra tes (A sy n c hron ou s Mo de) (3 )
Operating Frequency φ (MHz)
19.6608 20
Bit Rate
(bit/s) n N Error
(%) n N Error
(%)
110 3 86 0.31 3 88 –0.25
150 2 255 0.00 3 64 0.16
300 2 127 0.00 2 129 0.16
600 1 255 0.00 2 64 0.16
1200 1 127 0.00 1 129 0.16
2400 0 255 0.00 1 64 0.16
4800 0 127 0.00 0 129 0.16
9600 0 63 0.00 0 64 0.16
19200 0 31 0.00 0 32 –1.36
31250 0 19 –1.70 0 19 0.00
38400 0 15 0.00 0 15 1.73
Rev. 2.00, 03/04, page 234 of 508
Table 10.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
φ (MHz) Maximum Bit
Rate (bit/s) n N φ (MHz) Maximum Bit
Rate (bit/s) n N
4 125000 0 0 12 375000 0 0
4.9152 153600 0 0 12.288 384000 0 0
5 156250 0 0 14 437500 0 0
6 187500 0 0 14.7456 460800 0 0
6.144 192000 0 16 500000 0 0
7.3728 230400 0 0 17.2032 537600 0 0
8 250000 0 0 18 562500 0 0
9.8304 307200 0 0 19.6608 614400 0 0
10 312500 0 0 20 625000 0 0
Table 10.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
φ (MHz) External Input
Clock (MHz) Maximum Bit
Rate (bit/s) φ (MHz) External Input
Clock (MHz) Maximum Bit
Rate (bit/s)
4 1.0000 62500 12 3.0000 187500
4.9152 1.2288 76800 12.288 3.0720 192000
5 1.2500 78125 14 3.5000 218750
6 1.5000 93750 14.7456 3.6864 230400
6.144 1.5360 96000 16 4.0000 250000
7.3728 1.8432 115200 17.2032 4.3008 268800
8 2.0000 125000 18 4.5000 281250
9.8304 2.4576 153600 19.6608 4.9152 307200
10 2.5000 156250 20 5.0000 312500
Rev. 2.00, 03/04, page 235 of 508
Table 10.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mo de)
Operating Frequency φ (MHz)
4 8 10 16 20
Bit Rate
(bit/s) n N n N n N n N n N
110
250 2 249 3 124 3 249
500 2 124 2 249 3 124
1k 1 249 2 124 2 249
2.5k 1 99 1 199 1 249 2 99 2 124
5k 0 199 1 99 1 124 1 199 1 249
10k 0 99 0 199 0 249 1 99 1 124
25k 0 39 0 79 0 99 0 159 0 199
50k 0 19 0 39 0 49 0 79 0 99
100k 0 9 0 19 0 24 0 39 0 49
250k 0 3 0 7 0 9 0 15 0 19
500k 0 1 0 3 0 4 0 7 0 9
1M 0 0* 0 1 0 3 0 4
2.5M 0 0* 0 1
5M 0 0*
[Legend]
Blank: Cannot be set.
—: Can be set, but there will be a degree of error.
*: Continuous transfer is not possible.
Note: * Make the settings so that the error does not exceed 1%.
Table 10.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
φ (MHz) External Input
Clock (MHz) Maximum Bit
Rate (bit/s) φ (MHz) External Input
Clock (MHz) Maximum Bit
Rate (bit/s)
4 0.6667 666666.7 14 2.3333 2333333.3
6 1.0000 1.000000.0 16 2.6667 2666666.7
8 1.3333 1333333.3 18 3.0000 3000000.0
10 1.6667 1666666.7 20 3.3333 3333333.3
12 2.0000 2000000.0
Rev. 2.00, 03/04, page 236 of 508
Table 10.8 Examples of Bit Rate for Various BRR Settings (Smart Card Inter f a ce Mode )
(When n = 0 and S = 372)
Operating Frequency φ (MHz)
7.1424 10.00 10.7136 13.00
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
9600 0 0 0.00 0 1 30 0 1 25 0 1 8.99
Operating Frequency φ (MHz)
14.2848 16.00 18.00 20.00
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
9600 0 1 0.00 0 1 12.01 0 2 15.99 0 2 6.60
Table 10.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface M ode)
(when S = 372)
φ (MHz) Maximum Bit
Rate (bit/s) n N φ (MHz) Maximum Bit
Rate (bit/s) n N
7.1424 9600 0 0 14.2848 19200 0 0
10.00 13441 0 0 16.00 21505 0 0
10.7136 14400 0 0 18.00 24194 0 0
13.00 17473 0 0 20.00 26882 0 0
Rev. 2.00, 03/04, page 237 of 508
10.4 Operation in Asynchronous Mode
Figure 10.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and
finally stop bits (high level). In asynchronous serial communication, the transmission line is
usually held in the mark state (high level). The SCI monitors the transmission line. When the
transmission line goes to the space state (low level), the SCI recognizes a start bit and starts serial
communication. In asynchronous serial communication, the communication line is usually held in
the mark state (high level). The SCI monitors the communication line, and when it goes to the
space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the
transmitter and receiver are independent units, enabling full-duplex. The transmitter and receiver
both have a double -b uf fered structure, so dat a can be read o r wri t t en du ri n g tra nsmission or
reception, enabling continuous data transfer.
LSB
Start
bit
MSB
Idle state
(mark state)
Stop bit
0
Transmit/receive data
D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 1
Serial
data
Parity
bit
1 bit 1 or
2 bits
7 or 8 bits 1 bit,
or none
One unit of transfer data (character or frame)
Figure 10.2 Data Format in Asynchronous Communication (Example with 8-Bit Data,
Parity, Two Stop Bits)
10.4.1 Data Transfer Format
Table 10.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting. For details on the multiprocessor
bit, see section 10.5, Multiprocessor Communication Function.
Rev. 2.00, 03/04, page 238 of 508
Table 10.10 Serial Transfer Formats (Asynchronous Mode)
PE
0
0
1
1
0
0
1
1
—
—
—
—
S 8-bit data
STOP
S 7-bit data
STOP
S 8-bit data
STOP STOP
S 8-bit data P
STOP
S 7-bit data
STOP
P
S 8-bit data
MPB STOP
S 8-bit data
MPB STOP STOP
S 7-bit data
STOPMPB
S 7-bit data
STOPMPB STOP
S 7-bit data
STOPSTOP
CHR
0
0
0
0
1
1
1
1
0
0
1
1
MP
0
0
0
0
0
0
0
0
1
1
1
1
STOP
0
1
0
1
0
1
0
1
0
1
0
1
SMR Settings
123456789101112
Serial Transfer Format and Frame Length
STOP
S 8-bit data P
STOP
S 7-bit data
STOP
P
STOP
[Legend]
S: Start bit
STOP: Stop bit
P: Parity bit
MPB: Multiprocessor bit
Rev. 2.00, 03/04, page 239 of 508
10.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer
rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and
performs internal synchronization. Receive data is latched internally at the rising edge of the 8th
pulse of the basic clock as shown in figure 10.3. Thus, the reception margin in asynchronous mode
is given by formula (1) below.
M = (0.5 – ) – – (L – 0.5) F 100 [%]
1
2N
D – 0.5
N
... Formula (1)
Where M: Reception margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
Internal basic
clock
16 clocks
8 clocks
Receive data
(RxD)
Synchronization
sampling timing
Start bit D0 D1
Data sampling
timing
15 0 7 15 007
Figure 10.3 Receive Data Sampling Timing in Asynchronous Mode
Rev. 2.00, 03/04, page 240 of 508
10.4.3 Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in
SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK pin, the
clock frequenc y sh ould be 16 times the bit rat e use d.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in th is case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in Figure 10.4.
0
1 frame
D0 D1 D2 D3 D4 D5 D6 D7 0/1 11
SCK
TxD
Figure 10.4 Relationshi p bet ween Out p ut Cl ock and Transfer Data Phase
(Asynchronous Mode)
Rev. 2.00, 03/04, page 241 of 508
10.4.4 SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described below. When the operating mode, or transfer format, is changed for
example, the TE and RE bits must be cleared to 0 before making the change using the following
procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit
to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of
RDR. When the external clock is used in asynchronous mode, the clock must be supplied even
during initialization .
Wait
<Initialization completion>
Start initialization
Set data transfer format in
SMR and SCMR
[1]
Set CKE1 and CKE0 bits in SCR
(TE and RE bits are 0)
No
Yes
Set value in BRR
Clear TE and RE bits in SCR to 0
[2]
[3]
Set TE and RE bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits to 1
[4]
1-bit interval elapsed?
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE,
TEIE, MPIE, TE, and RE to 0.
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. Not necessary if
an external clock is used.
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits to 1.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
Figure 10.5 Sample SCI Initialization Flowchart
Rev. 2.00, 03/04, page 242 of 508
10.4.5 Data Transmission (Asynchronous Mode)
Figure 10.6 sho ws an example of operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that
data has been written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI)
is generated. Continuous transmission is possible because the TXI interrupt routine writes next
transmit data to TDR before transmission of the current transmit da ta has been completed.
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
multiprocessor b it (may be omitted depending on the format), and stop bit.
4. The SCI checks the TDRE flag at the timin g for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark
state" is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
Figure 10.7 shows a sample flowchart for transmission in asynchronous mode.
TDRE
TEND
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1
1 1
DataStart
bit
Parity
bit
Stop
bit
Start
bit
Data Parity
bit
Stop
bit
TXI interrupt
request generated
Data written to TDR and
TDRE flag cleared to 0 in
TXI interrupt service routine
TEI interrupt
request generated
Idle state
(mark state)
TXI interrupt
request generated
Figure 10.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
Rev. 2.00, 03/04, page 243 of 508
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR
and clear TDRE flag in SSR to 0
No
Yes
No
Yes
Read TEND flag in SSR
[3]
No
Yes
[4]
Clear DR to 0 and
set DDR to 1
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
Break output?
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Figure 10.7 Sample Serial Transmission Flowchart
Rev. 2.00, 03/04, page 244 of 508
10.4.6 Serial Data Reception (Asynchronous Mode)
Figure 10.8 sho ws an example of operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI monitors the communication line. If a start bit is detected, the SCI performs internal
synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the receive
data transferred to RDR before reception of the next receive data has been completed.
RDRF
FER
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0
1 1
DataStart
bit
Parity
bit
Stop
bit
Start
bit
Data Parity
bit
Stop
bit
ERI interrupt request
generated by framing
error
Idle state
(mark state)
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt service routine
RXI interrupt
request
generated
Figure 10.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
Rev. 2.00, 03/04, page 245 of 508
Table 10.11 shows the states of the SSR status flags and receive data handling when a receive
error is detected. If a receive error is detected, the RDRF flag retains its state before receiving
data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the
ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.9 shows a sample
flow chart for serial data reception.
Table 10.11 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF* ORER FER PER Recei ve Data Receive Error Type
1 1 0 0 Lost Overrun error
0 0 1 0 Transferred to RDR Framing error
0 0 0 1 Transferred to RDR Parity error
1 1 1 0 Lost Overrun error + framing error
1 1 0 1 Lost Overrun error + parity error
0 0 1 1 Transferred to RDR Framing error + parity error
1 1 1 1 Lost Overrun error + framing error
+ parity error
Note: * The RDRF flag retains the state it had before data reception.
Rev. 2.00, 03/04, page 246 of 508
Yes
<End>
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR [4]
[5]
Clear RE bit in SCR to 0
Read ORER, PER, and
FER flags in SSR
Error processing
(Continued on next page)
[3]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Yes
PER FER ORER = 1
RDRF = 1
All data received?
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data input
pin.
[2] [3] Receive error processing and break
detection:
If a receive error occurs, read the
ORER, PER, and FER flags in SSR to
identify the error. After performing the
appropriate error processing, ensure
that the ORER, PER, and FER flags are
all cleared to 0. Reception cannot be
resumed if any of these flags are set to
1. In the case of a framing error, a
break can be detected by reading the
value of the input port corresponding to
the RxD pin.
[4] SCI status check and receive data read:
Read SSR and check that RDRF = 1,
then read the receive data in RDR and
clear the RDRF flag to 0. Transition of
the RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
[5] Serial reception continuation procedure:
To continue serial reception, before the
stop bit for the current frame is
received, read the RDRF flag, read
RDR, and clear the RDRF flag to 0.
Figure 10.9 Sample Serial Reception Data Flowchart (1)
Rev. 2.00, 03/04, page 247 of 508
<End>
[3]
Error processing
Parity error processing
Yes
No
Clear ORER, PER, and
FER flags in SSR to 0
No
Yes
No
Yes
Framing error processing
No
Yes
Overrun error processing
ORER = 1
FER = 1
Break?
PER = 1
Clear RE bit in SCR to 0
Figure 10.9 Sample Serial Reception Data Flowchart (2)
Rev. 2.00, 03/04, page 248 of 508
10.5 Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer between a number of
processors sharing communication lines by asynchronous serial communication using the
multiprocessor format, in which a multiprocessor bit is added to the transfer data. When
multiprocessor communication is performed, each receiving station is addressed by a unique ID
code. The serial communication cycle consists of two component cycles; an ID transmission cycle
that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to
differentiate between the ID transmission cycle and the data transmission cycle. If the
multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the
cycle is a data transmission cycle. Figure 10.10 shows an example of inter-processor
communication using the multiprocessor format. The tran smitting station first sends the ID code
of the receiving station with which it wants to perform serial communication as data with a 1
multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not
match continue to skip data until data with a 1 multiprocessor bit is again received.
The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and ORER to 1, are inhibited until data with a 1 multiprocessor bit is received. On
reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the
MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to
1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit
settings are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchrono us mode.
Rev. 2.00, 03/04, page 249 of 508
Transmitting
station
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01) (ID = 02) (ID = 03) (ID = 04)
Serial transmission line
Serial
data
ID transmission cycle =
receiving station
specification
Data transmission cycle =
Data transmission to
receiving station specified by ID
(MPB = 1) (MPB = 0)
H'01 H'AA
[Legend]
MPB: Multiprocessor bit
Figure 10.10 Example of Communication Using Multiprocessor For mat
(Transmission of Data H'AA to Receiving Station A)
Rev. 2.00, 03/04, page 250 of 508
10.5.1 Multiprocessor Serial Data Transmission
Figure 10.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR and
set MPBT bit in SSR
No
Yes
No
Yes
Read TEND flag in SSR
[3]
No
Yes
[4]
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
Break output?
Clear TDRE flag to 0
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
frame of 1s is output, and
transmission is enabled.
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to
0.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to
1, clear DR to 0, then clear the
TE bit in SCR to 0.
Figure 10.11 Sample Multiprocessor Serial Transmission Flowchart
Rev. 2.00, 03/04, page 251 of 508
10.5.2 Multiprocessor Serial Data Reception
Figure 10.13 sh ows a sample flowchart for multipro cessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
10.12 shows an example of SCI operation for multiprocessor format reception.
MPIE
RDR
value
0 D0 D1 D7 1 1 0 D0 D1 D7 0 1
11
Data (ID1)Start
bit MPB
Stop
bit
Start
bit
Data (Data1)
MPB
Stop
bit
Data (ID2)Start
bit
Stop
bit
Start
bit
Data (Data2) Stop
bit
RXI interrupt
request
(multiprocessor
interrupt)
generated
Idle state
(mark state)
RDRF
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
service routine
If not this station’s ID,
MPIE bit is set to 1
again
RXI interrupt request is
not generated, and RDR
retains its state
ID1
(a) Data does not match station’s ID
MPIE
RDR
value
0 D0 D1 D7 1 1 0 D0 D1 D7 0 1
11
MPB MPB
RXI interrupt
request
(multiprocessor
interrupt)
generated
Idle state
(mark state)
RDRF
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
service routine
Matches this station’s ID,
so reception continues, and
data is received in RXI
interrupt service routine
MPIE bit set to 1
again
ID2
(b) Data matches station’s ID
Data2ID1
MPIE = 0
MPIE = 0
Figure 10.12 Example of SCI Operation in Reception (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit)
Rev. 2.00, 03/04, page 252 of 508
Yes
<End>
[1]
No
Initialization
Start reception
No
Yes
[4]
Clear RE bit in SCR to 0
Error processing
(Continued on
next page)
[5]
No
Yes
FER ORER = 1
RDRF = 1
All data received?
Read MPIE bit in SCR [2]
Read ORER and FER flags in SSR
Read RDRF flag in SSR [3]
Read receive data in RDR
No
Yes
This station’s ID?
Read ORER and FER flags in SSR
Yes
No
Read RDRF flag in SSR
No
Yes
FER ORER = 1
Read receive data in RDR
RDRF = 1
[1] SCI initialization:
The RxD pin is automatically designated
as the receive data input pin.
[2] ID reception cycle:
Set the MPIE bit in SCR to 1.
[3] SCI status check, ID reception and
comparison:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and compare it with this
station’s ID.
If the data is not this station’s ID, set the
MPIE bit to 1 again, and clear the RDRF
flag to 0.
If the data is this station’s ID, clear the
RDRF flag to 0.
[4] SCI status check and data reception:
Read SSR and check that the RDRF
flag is set to 1, then read the data in
RDR.
[5] Receive error processing and break
detection:
If a receive error occurs, read the ORER
and FER flags in SSR to identify the
error. After performing the appropriate
error processing, ensure that the ORER
and FER flags are all cleared to 0.
Reception cannot be resumed if either
of these flags is set to 1.
In the case of a framing error, a break
can be detected by reading the RxD pin
value.
Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 2.00, 03/04, page 253 of 508
<End>
Error processing
Yes
No
Clear ORER, and
FER flags in SSR to 0
No
Yes
No
Yes
Framing error processing
Overrun error processing
ORER = 1
FER = 1
Break?
Clear RE bit in SCR to 0
[5]
Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (2)
Rev. 2.00, 03/04, page 254 of 508
10.6 Operation in Clocked Synchronous Mode
Figure 10.14 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received synchronous with clock pulses. In clocked
synchronous serial communication, data on the tran smission line is output from one falling edge of
the serial clock to the next. In clocked synchronous mode, the SCI receives data in synchronous
with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the
MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI,
the transmitter and receiver are independent units, enabling full-duplex communication through
the use of a common clock. The transmitter and the receiver both have a double-buffered struct ure ,
so data can be read or written during transmission or reception, enabling continuous data t ransfer.
Don’t
care
Don’t
care
One unit of transfer data (character or frame)
Bit 0
Serial data
Synchronization
clock
Bit 1 Bit 3 Bit 4 Bit 5
LSB MSB
Bit 2 Bit 6 Bit 7
**
Note: * High except in continuous transfer
Figure 10.14 Data Format in Synchronous Communication (for LSB-First)
10.6.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK pin can be selected, according to the setting of CKE0 and
CKE1 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from
the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no
transfer is performed the clock is fixed high.
Rev. 2.00, 03/04, page 255 of 508
10.6.2 SCI Initialization (Clocked Synchronous Mode)
Before transmitting and receiving data, the TE and RE bits in SCR should be cleared to 0, and
then the SCI should be initialized as described in a sample flowchart in Figure 10.15. When the
operating mode, or tr ansfer format, is changed for example, the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0, the
TDRE flag is set to 1. Note that clearing the RE bit to 0 does not change the contents of the
RDRF, PER, FER, and ORER flags, or the contents of RDR.
Wait
<Transfer start>
Start initialization
Set data transfer format in
SMR and SCMR
No
Yes
Set value in BRR
Clear TE and RE bits in SCR to 0
[2]
[3]
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits [4]
1-bit interval elapsed?
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0) [1]
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, MPIE, TE,
and RE to 0.
[2] Set the data transfer format in SMR and
SCMR.
[3] Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
[4] Wait at least one bit interval, then set
the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE TEIE, and MPIE
bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used.
Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared
to 0 or set to 1 simultaneously.
Figure 10.15 Sample SCI Initialization Flowchart
Rev. 2.00, 03/04, page 256 of 508
10.6.3 Serial Data Transmission (Clocked Synchronous Mode)
Figure 10.16 shows an example of SCI operation for transmission in clocked synchronous mode.
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has
been written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI)
is generated. Continuous transmission is possible because the TXI interrupt routine writes the
next transmit data to TDR b efore transmission of the curren t transmit data has been completed.
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
mode has been specified, and synchronized with the input clock when use of an external clock
has been specified.
4. The SCI checks the TDRE flag at the timin g for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the
output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request
is generated. The SCK pin is fixed high.
Figure 10.17 shows a sample flow chart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure that the receive error flags are cleared to 0 before starting transmission. Note that
clearing the RE bit to 0 does not clear the receive error flags.
Transfer direction
Bit 0
Serial data
Synchronization
clock
1 frame
TDRE
TEND
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
service routine
TXI interrupt
request generated
Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TXI interrupt
request generated
TEI interrupt request
generated
Figure 10.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
Rev. 2.00, 03/04, page 257 of 508
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
Yes
No
Yes
Read TEND flag in SSR
[3]
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Figure 10.17 Sample Serial Transmission Flowchart
Rev. 2.00, 03/04, page 258 of 508
10.6.4 Serial Data Reception (Clocked Synchronous Mode)
Figure 10.18 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization synchronous with a synchronous clock input or output,
starts receiving data, and stores the received data in RSR.
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
in SSR is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this
time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
3. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the receive
data transferred to RDR before reception of the next receive data has finished.
Bit 7
Serial data
Synchronization
clock
1 frame
RDRF
ORER
ERI interrupt request
generated by overrun
error
RXI interrupt
request generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
service routine
RXI interrupt
request
generated
Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figure 10.18 Example of SCI Oper ation in Reception
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resu ming reception. Figur e 10.19 shows a sample flow
chart for serial data reception.
Rev. 2.00, 03/04, page 259 of 508
Yes
<End>
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR [4]
[5]
Clear RE bit in SCR to 0
Error processing
(Continued below)
[3]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Yes
ORER = 1
RDRF = 1
All data received?
Read ORER flag in SSR
<End>
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
[3]
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data input
pin.
[2] [3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Transfer cannot be resumed if the
ORER flag is set to 1.
[4] SCI status check and receive data
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0.
Transition of the RDRF flag from 0 to 1
can also be identified by an RXI
interrupt.
[5] Serial reception continuation
procedure:
To continue serial reception, before
the MSB (bit 7) of the current frame is
received, reading the RDRF flag,
reading RDR, and clearing the RDRF
flag to 0 should be finished.
Figure 10.19 Sample Serial Reception Flowchart
Rev. 2.00, 03/04, page 260 of 508
10.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous
Mode)
Figure 10.20 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations. To switch from transmit mode to simultaneous tran smit and receive mode, after
checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear
TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive
mode to simultaneous transmit and receive mode, after checking that the SCI has finished
reception, clear RE to 0. Then after checking that the RDRF and receive error flags (ORER, FER,
and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
Rev. 2.00, 03/04, page 261 of 508
Yes
<End>
[1]
No
Initialization
Start transmission/reception
[5]
Error processing
[3]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Yes
ORER = 1
All data received?
[2]
Read TDRE flag in SSR
No
Yes
TDRE = 1
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
Yes
RDRF = 1
Read ORER flag in SSR
[4]
Read RDRF flag in SSR
Clear TE and RE bits in SCR to 0
[1] SCI initialization:
The TxD pin is designated as the
transmit data output pin, and the RxD
pin is designated as the receive data
input pin, enabling simultaneous
transmit and receive operations.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR and clear the TDRE flag
to 0.
Transition of the TDRE flag from 0 to
1 can also be identified by a TXI
interrupt.
[3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to 1.
[4] SCI status check and receive data
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0. Transition of the RDRF flag from
0 to 1 can also be identified by an RXI
interrupt.
[5] Serial transmission/reception
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading RDR,
and clearing the RDRF flag to 0.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible. Then write data to
TDR and clear the TDRE flag to 0.
Note: When switching from transmit or receive operation to simultaneous
transmit and receive operations, first clear the TE bit and RE bit to 0,
then set both these bits to 1 simultaneously.
Figure 10.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Rev. 2.00, 03/04, page 262 of 508
10.7 Operation in Smart Card Interface
The SCI supports an IC card (Smart Card) interface that conforms to ISO/IEC 7816-3
(Identification Card) as a serial communication interface extension function. Switching between
the normal serial communication interface and the Smart Card interface mode is carried out by
means of a register setting.
10.7.1 Pin Connection Example
Figure 10.21 sh ows an example of connection with the Smart Card. In communication with an IC
card, as both transmission and reception are carried out on a single data transmission line, the TxD
pin and RxD pin should be connected to the LSI pin. The data transmission line should be pulled
up to the VCC power supply with a resistor. If an IC card is not connected, and the TE and RE bits
are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried
out. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin
output is input to the CLK pin of the IC card. This LSI port output is used as the reset signal.
TxD
RxD
This LSI
VCC
I/O
Connected equipment
IC card
Data line
Clock line
Reset line
CLK
RST
SCK
Rx (port)
Figure 10.21 Schematic Diagram of Smart Card Interface Pin Connections
Rev. 2.00, 03/04, page 263 of 508
10.7.2 Data Format (Except for Block Transfer Mode)
Figure 10.22 sh ows the transfer da ta format in Smart Card interface mod e.
• One frame consists of 8-bit data plus a parity bit in asynchronous mode.
• In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of
one bit) is left between th e end of the parity bit and the start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for one etu
period, 10.5 etu after the start bit.
• If an error signal is samp led during transmission, the same data is retransmitted automatically
after a delay of 2 etu or longer.
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
When there is no parity error
Transmitting station output
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
When a parity error occurs
Transmitting station output
DE
Receiving station
output
Start bit
Data bits
Parity bit
Error signal
[Legend]
DS:
D0 to D7:
Dp:
DE:
Figure 10.22 Normal Smart Card Interface Data Format
Data transfer with other types of IC cards (direct convention and inverse convention) are
performed as described in the following.
Ds
AZZAZZ ZZAA(Z) (Z) State
D0 D1 D2 D3 D4 D5 D6 D7 Dp
Figure 10.23 Direct Convention (SDIR = SINV = O/E = 0)
Rev. 2.00, 03/04, page 264 of 508
With the direction convention type IC and the above sample start character, the logic 1 level
corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order.
The start charac ter data above is H'3B. For the direct convention type, clear the SDI R and SINV
bits in SCMR to 0. According to Smart Card regulations, clear the O/E bit in SMR to 0 to select
even parity mode.
Ds
AZZAAA ZAAA(Z) (Z) State
D7 D6 D5 D4 D3 D2 D1 D0 Dp
Figure 10.24 Inverse Convention (SDIR = SINV = O/E = 1)
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to
state Z, and transfer is performed in MSB-first order. The start character data for the above is
H'3F. For the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to
Smart Card regulations, even parity mod e is the logic 0 level of the parity bit, and corresponds to
state Z. In this LSI, the SINV bit inverts only data bits D0 to D7. Therefore, set the O /E bit in
SMR to 1 to invert the parity bit for both transmission and reception.
10.7.3 Block Transfer Mode
Operation in block transfer mode is the same as that in SCI asynchronous mode, except for the
following points.
• In reception, though the parity check is performed, no error signal is output even if an error is
detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the
parity bit of the next frame.
• In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the
start of the next frame.
• In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu
after transmission start.
• As with the normal Smart Card interface, the ERS flag indicates the error signal status, but
since error signal transfer is not performed, this flag is always cleared to 0.
Rev. 2.00, 03/04, page 265 of 508
10.7.4 Receive Data Sampling Timing and Reception Margin in Smart Card Interface
Mode
In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372,
or 256 times the transfer rate (fixed at 16 times in normal asynchronous mode) as determined by
bits BCP1 and BCP0. In reception, the SCI samples the falling edge of the start bit using the basic
clock, and performs internal synchronization. As shown in Figure 10.25, by sampling receive data
at the rising-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at
the middle of the bit. The reception margin is given by the following formula.
M = | (0.5 – ) – (L – 0.5) F – (1 + F) | 100%
1
2N | D – 0.5 |
N
Where M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)
D: Clock duty (D = 0 to 1. 0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
M = (0. 5 – 1/ 2 × 372) × 100%
= 49.866%
Internal
basic clock
372 clocks
186 clocks
Receive data
(RxD)
Synchronization
sampling timing
D0 D1
Data sampling
timing
185 371 0
371
185 0
0
Start bit
Figure 10.25 Receive Data Sampling Timing in Smart Car d Mode
(Using Clock of 372 Times the Transfer Rate)
Rev. 2.00, 03/04, page 266 of 508
10.7.5 Initialization
Before transmitting and receiving data, initialize the SCI as described below. Initialization is also
necessary when switching from transmit mode to receive mode, or vice versa.
1. Clear the TE and RE bits in SCR to 0.
2. Clear the error flags ERS, PER, and ORER in SSR to 0.
3. Set the GM, BLK, O/E, BCP0, BCP1, CKS0, and CKS1 bits in SMR. Set the PE bit to 1.
4. Set the SMIF, SDIR, and SINV bits in SCMR.
When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins,
and are placed in the high-impedance state.
5. Set the value corresponding to the bit rate in BRR.
6. Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0.
If the CKE0 bit is set to 1, the clock is output from the SCK pin.
7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE
bit and RE bit at the same time, except for self-diagnosis.
To switch from receive mode to transmit mode, after checking that the SCI has finished reception,
initialize the SCI, and set RE to 0 and TE to 1. Whethe r SCI has finished reception or not can be
checked with the RDRF, PER, or ORER flags. To switch from transmit mode to receive mode,
after checking that the SCI has finished transmission, initialize the SCI, and set TE to 0 and RE to
1. Whether SCI has fini shed transmission or not can be c he c ked with the TEN D fl ag.
10.7.6 Data Transmission (Except for Block Transfer Mode)
As data transmission in Smart Card interface mode involves er ror signal sampling and
retransmission processing, the operations are different from those in normal serial communication
interface mode (except for block transfer mode). Figure 10.26 illustrates the retransfer operation
when the SCI is in transmit mode.
1. If an error signal is sent back from the receiving end after transmission of one frame is
complete, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 un til the next
parity bit is sampled.
2. The TEND bit in SSR is not set for a frame in which an error signal indicating an abnormality
is received. Data is retransferred from TDR to TSR, and retransmitted automatically.
3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
Transmission of one frame, including a retransfer, is judged to have been completed, and the
TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt
request is generated. Writing transmit data to TDR transfers the next transmit data.
Rev. 2.00, 03/04, page 267 of 508
Figure 10.28 shows a flowchart for transmission. In a transmit operation, the TDRE flag is set to 1
at the same time as the TEND flag in SSR is set, and a TXI interrupt will be generated if the TIE
bit in SCR has been set to 1. In the event of an error, the SCI retransmits the same data
automatically. During this period, the TEND flag remains cleared to 0. Therefore, the SCI and
DTC will automatically transmit the specified number of bytes in the event of an error, including
retransmission. However, the ERS flag is not cleared automatically when an error occurs, and so
the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of
an error, and the ERS flag will be cleared.
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4
Ds
Transfer
frame n+1
Retransferred framenth transfer frame
TDRE
TEND
[1]
FER/ERS
Transfer to TSR from TDR Transfer to TSR from TDR Transfer to TSR
from TDR
[2] [3]
[3]
Figure 10.26 Retransfer Operation in SCI Transmit Mode
Rev. 2.00, 03/04, page 268 of 508
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag
set timing is shown in Figure 10.27.
Ds D0 D1 D2 D3 D4 D5 D6 D7 DpI/O data
12.5 etu
TXI
(TEND interrupt)
11.0 etu
DE
Guard
time
When GM = 0
When GM = 1
Start bit
Data bits
Parity bit
Error signal
[Legend]
Ds:
D0 to D7:
Dp:
DE:
Figure 10.27 TEND Flag Generation Timing in Transmission Operation
Rev. 2.00, 03/04, page 269 of 508
Initialization
No
Yes
Clear TE bit to 0
Start transmission
Start
No
No
No
Yes
Yes
Yes
Yes
No
End
Write data to TDR,
and clear TDRE flag
in SSR to 0
Error processing
Error processing
TEND = 1?
All data transmitted ?
TEND = 1?
ERS = 0?
ERS = 0?
Figure 10.28 Example of Transmission Processing Flow
Rev. 2.00, 03/04, page 270 of 508
10.7.7 Serial Data Reception (Except for Block Transfer Mode)
Data reception in Smart Card interface mode uses the same operation procedure as for normal
serial communication interface mod e. Figure 10.29 illustrates the retransfer op eration when the
SCI is in receive mode.
1. If an error is found when the received parity bit is checked, the PER bit in SSR is
automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is
generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.
2. The RDRF bit in SSR is not set for a frame in which an error has occurred.
3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1,
the receive operation is judged to have been completed normally, and the RDRF flag in SSR is
automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is
generated.
Figure 10.30 shows a flowchart for reception. In a receive operation, an RXI interrupt request is
generated when the RDRF flag in SSR is set to 1. If an error occurs in receive mode and the
ORER or PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. Hence, so
the error flag must be cleared to 0. Even when a parity error occurs in receive mode and the PER
flag is set to 1, the data that has been received is transferred to RDR and can be read from there.
Note: For details on receive operations in block transfer mode, see section 10.4, Operation in
Asynchr o no us Mode.
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE)Ds D0 D1 D2 D3 D4
Ds
Transfer
frame n+1
Retransferred framenth transfer frame
RDRF
[1]
PER
[2]
[3]
[3]
Figure 10.29 Retransfer Operation in SCI Receive Mode
Rev. 2.00, 03/04, page 271 of 508
Initialization
Read RDR and clear
RDRF flag in SSR to 0
Clear RE bit to 0
Start reception
Start
Error processing
No
No
No
Yes
Yes
ORER = 0 and
PER = 0
RDRF = 1?
All data received?
Yes
Figure 10.30 Example of Reception Processing Flow
10.7.8 Clock Output Control
When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and
CKE1 in SCR. At this time, the minimum clock pulse width can be made the specified width.
Figure 10.31 sh ows the timing for fixing the clock ou tput level. In this example, GM is set to 1,
CKE1 is cleared to 0, and the CKE0 bit is controlled.
Specified pulse width
SCK
CKE0
Specified pulse width
Figure 10.31 Timing for Fixing Clock Output Level
Rev. 2.00, 03/04, page 272 of 508
When turning on the power or switching between Smart Card interface mode and software standby
mode, the following proced ures should be followed in order to maintain the clock duty.
Powering On: To secure clock duty from power-on, the following switching procedure should be
followed.
1. The initial state is port input and high impedance. Use a pu ll-up resistor or pull-down resistor
to fix the potential.
2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card mode operation.
4. Set the CKE0 bit in SCR to 1 to start clock output.
When Changing from Smart Card Interf ace Mode to Software Standby Mode:
1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to
the value for the fixed output state in software standby mode.
2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive
operation. At the same time, set the CKE1 bit to the value for th e fixed output state in software
standby mode.
3. Write 0 to the CKE0 bit in SCR to halt th e clock.
4. Wait for one serial clock period.
During this interval, clock output is fixed at the specified level, with the duty preserved.
5. Make the transition to the software standby state.
When Returning to Smart Card Interface Mode from So ft ware Standby Mode:
1. Exit the software standby state.
2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the
normal duty.
[1] [2] [3] [4] [5] [7]
Software
standby
Normal operation Normal operation
[6]
Figure 10.32 Clock Halt and Restart Procedure
Rev. 2.00, 03/04, page 273 of 508
10.8 Interrupts
10.8.1 Interrupts in Normal Serial Communication Interface Mode
Table 10.12 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated.
A TEI interrupt is requested when the TEND flag is set to 1 and the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt h as priority for
acceptance. However, if the TDRE and TEND flags are cleared simultaneously by the TXI
interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
Table 10.12 SCI Interrupt Sources
Channel Name Interrupt Source Interrupt Flag
ERI0 Receive Error ORER, FER, PER
RXI0 Receive Data Full RDRF
TXI0 Transmit Data Empty TDRE
0
TEI0 Transmission End TEND
ERI1 Receive Error ORER, FER, PER
RXI1 Receive Data Full RDRF
TXI1 Transmit Data Empty TDRE
1
TEI1 Transmission End TEND
Rev. 2.00, 03/04, page 274 of 508
10.8.2 Interrupts in Smart Card Interface Mode
Table 10.13 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt
(TEI) request cannot be used in this mode.
Table 10.13 SCI Interrupt Sources
Channel Name Interrupt Source Interrupt Flag
ERI0 Receive Error, detection ORER, PER, ERS
RXI0 Receive Data Full RDRF
0
TXI0 Transmit Data Empty TEND
ERI1 Receive Error, detection ORER, PER, ERS
RXI1 Receive Data Full RDRF
1
TXI1 Transmit Data Empty TEND
In transmit operations, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR is
set, and a TXI interrupt is generated. In th e event of an error, the SCI retransmits the same data
automatically. During this period, the TEND flag remains cleared to 0. The ERS flag is not cleared
automatically when an error occurs. Hence, the RIE bit should be set to 1 beforehand so that an
ERI request will be generated in the event of an error, and the ERS flag will be cleared.
In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to
1. If an error occurs, an error flag is set but the RDRF flag is not. An ERI interrupt request is sent
to the CPU. Therefore, the error flag should be cleared.
10.9 Usage Notes
10.9.1 Module Stop Mode Setting
SCI operation can be disabled or enabled using the module stop control register. The initial setting
is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For
details, see section 19, Power-Down Modes.
10.9.2 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly
the PER flag. Note that as the SCI continues the receive operation after recei ving a break, even if
the FER flag is cleared to 0, it will be set to 1 again.
Rev. 2.00, 03/04, page 275 of 508
10.9.3 Mark State and Break Detection
When TE is 0, the TxD pi n is used as an I/O port whose dir ect i on (input or output) and level are
determined by DR and DDR. This can be used to set the TxD pin to mark state (high level) or send
a break during serial data transmission. To maintain the communication line at mark state until TE
is set to 1, set both DDR and DR to 1. As TE is cleared to 0 at this point, the TxD pin becomes an
I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set
DDR to 1 and DR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is
initialized regardless of the current transmissio n state, the TxD pin becomes an I/O port, and 0 is
output from the TxD pin.
10.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
Rev. 2.00, 03/04, page 276 of 508
Rev. 2.00, 03/04, page 277 of 508
Section 11 Controller Area Network (HCAN)
The HCAN is a module for controlling a controller area network (CAN) for realtime
communication in vehicular and industrial equipment systems, etc. For details on CAN
specification, see Bosch CAN Specification Version 2.0 1991, Robert Bosch GmbH.
The block diagram of the HCAN is shown in figure 1 1. 1.
11.1 Features
• CAN v ersion: Bosch 2.0B active compatible
Communication systems: NRZ (Non-Return to Zero) system (with bit-stuffing function)
Broadcast communication system
Transmission path: Bidirectional 2-wire serial communication
Communication speed: Max. 1 Mbps
Data length: 0 to 8 bytes
• Number of channels: 1
• Data buffers: 16 (one receive-only buffer and 15 buffers settable for transmission/reception)
• Data transmission: Two methods
Mailbox (buffer) number order (low-to-high)
Message priorit y (i dent i fie r ) reverse-order (h i gh -t o-low)
• Data reception: Two methods
Message identifier match (transmit/receive-setting buffers)
Reception with message identifier masked (receive-only)
• CPU interrupts: 12
Error interrupt
Reset processing interrupt
Message reception interrupt
Message transmission interrupt
• HCAN operating modes
• Support for various modes
Hardware reset
Software reset
Normal status (error-active, error-passive)
Bus off status
HCAN conf iguration mode
HCAN sleep mode
HCAN halt mode
IFCAN00B_000020020200
Rev. 2.00, 03/04, page 278 of 508
• Module stop mode can be set
Peripheral address bus
Peripheral data bus
HTxD
MBI
HRxD
CAN
Data Link Controller
MPI
(CDLC)
Tx buffer
Rx buffer
Message buffer
Message control
Message data
MC0–MC15, MD0–MD15
LAFM
Mailboxes
Microprocessor interface
CPU interface
Control register
Status register
HCAN
Bosch CAN 2.0B active
Figure 11.1 HCAN Block Diagram
• Message Buffer Interface (MBI)
The MBI, consisting of mailboxes and a local acceptance filter mask (LAFM), stores CAN
transmit/received messages (identifiers, data, etc.) Transmit messages are written by the CPU.
For received messages, the data received by the CDLC is stored automatically.
• Microprocessor Interface (MPI)
The MPI, consisting of a bus interface, control register, status register, etc., controls HCAN
internal data, status, and so forth.
• CAN D ata Link Controller (CDLC)
The CDLC transmits and receives of messages conforming to the Bosch CAN Ver. 2.0B active
standard (data frames, remote frames, error frames, overload frames, inter-frame spacing), as
well as CRC checking, bus arbitration, and oth e r functions.
Rev. 2.00, 03/04, page 279 of 508
11.2 Input/Output Pins
Table 11.1 shows the HCAN's pins.
When using HCAN pins, settings must be made in the HCAN configuration mode (during
initialization: MCR0 = 1 and GSR3 = 1).
Table 11.1 Pin Configuration
Name Abbreviation Input/Output Function
HCAN transmit data pin HTxD Output CAN bus transmission pin
HCAN receive data pin HRxD Input CAN bus reception pin
A bus driver is necessary for the interface between the pins and the CAN bus. A Philips
PCA82C250 compatible model is recommended.
11.3 Register Descriptions
The HCAN has the following registers.
• Master control register (MCR)
• General status register (GSR)
• Bit con figuration register (BCR)
• Mailbo x con figuration register (MBCR)
• Transmit wait register (TXPR)
• Transmit wait cancel register (TXCR)
• Transmit acknowledge register (TXACK)
• Abor t acknowledge register (ABACK)
• Receive complete register (RXPR)
• Remote request register (RFPR)
• Interrupt register (IRR )
• Mailbox interrupt mask register (MBIMR)
• Interrupt mask register (IMR)
• Receive error counter (REC)
• Transmit error counter (TEC)
• Unread message status register (UMSR)
• Local acceptance filter mask H (LAFMH)
• Local acceptance filter mask L (LAFML)
• Message control (8-bit × 8 registers × 16 sets) (MC0 to MC15)
• Message data (8-bit × 8 registers × 16 sets) (MD0 to MD15)
Rev. 2.00, 03/04, page 280 of 508
11.3.1 Master Control Register (MCR)
MCR controls the HCAN.
Bit Bit Name Initial
Value R/W Description
7 MCR7 0 R/W HCAN Sleep Mode Release
When this bit is set to 1, the HCAN automatically exits
HCAN sleep mode on detection of CAN bus operation.
6 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
5 MCR5 0 R/W HCAN Sleep Mode
When this bit is set to 1, the HCAN transits to HCAN
sleep mode. When this bit is cleared to 0, HCAN sleep
mode is released.
4, 3 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
2 MCR2 0 R/W Message Transmission Method
0: Transmission order determined by message identifier
priority
1: Transmission order determined by mailbox (buffer)
number priority (TXPR1 > TXPR15)
1 MCR1 0 R/W Halt Request
When this bit is set to 1, the HCAN transits to HCAN
HALT mode. When this bit is cleared to 0, HCAN HALT
mode is released.
0 MCR0 1 R/W Reset Request
When this bit is set to 1, the HCAN transits to reset
mode. For details, see section 11.4.1, Hardware Reset
and Software Resets.
[Setting conditions]
• Power-on reset
• Hardware standby
• Software standby
• 1-write (software reset)
[Clearing condition]
• When 0 is written to this bit while the GSR3 bit in
GSR is 1
Rev. 2.00, 03/04, page 281 of 508
11.3.2 General Status Register (GSR)
GSR indicates the status of the CAN bus.
Bit Bit Name Initial
Value R/W Description
7 to 4 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
3 GSR3 1 R Reset Status Bit
Indicates whether the HCAN module is in the normal
operating state or the reset state. This bit cannot be
modified.
[Setting conditions]
• When entering configuration mode after the HCAN
internal reset has finished
• Sleep mode
[Clearing condition]
• When entering normal operation mode after the
MCR0 bit in MCR is cleared to 0 (Note that there is
a delay between clearing of the MCR0 bit and the
GSR3 bit.)
2 GSR2 1 R Message Transmission Status Flag
Flag that indicates whether the module is currently in
the message transmission period. This bit cannot be
modified.
[Setting condition]
• Third bit of Intermission after EOF(END of Frame)
[Clearing condition]
• Start of message transmission (SOF)
1 GSR1 0 R Transmit/Receive Warning Flag
This bit cannot be modified.
[Setting condition]
• When TEC ≥ 96 or REC ≥ 96
[Clearing condition]
• When TEC < 96 and REC < 96 or TEC ≥ 256
Rev. 2.00, 03/04, page 282 of 508
Bit Bit Name Initial
Value R/W Description
0 GSR0 0 R Bus Off Flag
This bit cannot be modified.
[Setting condition]
• When TEC ≥ 256 (bus off state)
[Clearing condition]
• Recovery from bus off state
11.3.3 Bit Configuration Register (BCR)
BCR that is used to set HCAN bit timing parameters and the baud rate prescaler. For details on
parameters, see section 11.4.2 , Initialization after Hardware Reset.
Bit Bit Name Initial
Value R/W Description
15
14
BCR7
BCR6
0
0
R/W
R/W
Re-Synchronization Jump Width (SJW)
Set the maximum bit synchronization width.
00: 1 time quantum
01: 2 time quanta
10: 3 time quanta
11: 4 time quanta
13
12
11
10
9
8
BCR5
BCR4
BCR3
BCR2
BCR1
BCR0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Baud Rate Prescaler (BRP)
Set the length of time quanta.
000000: 2 × system clock
000001: 4 × system clock
000010: 6 × system clock
:
111111: 128 × system clock
7 BCR15 0 R/W Bit Sample Point (BSP)
Sets the point at which data is sampled.
0: Bit sampling at one point (end of time segment 1
(TSEG1))
1: Bit sampling at three points (end of TSEG1 and
preceding and following time quanta)
Rev. 2.00, 03/04, page 283 of 508
Bit Bit Name Initial
Value R/W Description
6
5
4
BCR14
BCR13
BCR12
0
0
0
R/W
R/W
R/W
Time Segment 2 (TSEG2)
Set the TSEG2 width within a range of 2 to 8 time
quanta.
000: Setting prohibited
001: 2 time quanta
010: 3 time quanta
011: 4 time quanta
100: 5 time quanta
101: 6 time quanta
110: 7 time quanta
111: 8 time quanta
3
2
1
0
BCR11
BCR10
BCR9
BCR8
0
0
0
0
R/W
R/W
R/W
R/W
Time Segment 1 (TSEG1)
Set the TSEG1 (PRSEG + PHSEG1) width to between
4 and 16 time quanta.
0000: Setting prohibited
0001: Setting prohibited
0010: Setting prohibited
0011: 4 time quanta
0100: 5 time quanta
0101: 6 time quanta
0110: 7 time quanta
0111: 8 time quanta
1000: 9 time quanta
1001: 10 time quanta
1010: 11 time quanta
1011: 12 time quanta
1100: 13 time quanta
1101: 14 time quanta
1110: 15 time quanta
1111: 16 time quanta
Rev. 2.00, 03/04, page 284 of 508
11.3.4 Mailbox Configuration Register (MBCR)
MBCR is used to set the transfer direction for each mailbox.
Bit Bit Name Initial
Value R/W Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MBCR7
MBCR6
MBCR5
MBCR4
MBCR3
MBCR2
MBCR1
MBCR15
MBCR14
MBCR13
MBCR12
MBCR11
MBCR10
MBCR9
MBCR8
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
These bits set the transfer direction for the
corresponding mailboxes from 1 to 15. MBCRn
determines the transfer direction for mailbox n (n =1 to
15).
0: Corresponding mailbox is set for transmission
1: Corresponding mailbox is set for reception
Bit 8 is reserved. This bit is always read as 1 and the
write value should always be 1.
Rev. 2.00, 03/04, page 285 of 508
11.3.5 Transmit Wait Register (TXPR)
TXPR is used to set a transmit wait after a transmit message is stored in a mailbox (buffer) (CAN
bus arbitration wait).
Bit Bit Name Initial
Value R/W Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXPR7
TXPR6
TXPR5
TXPR4
TXPR3
TXPR2
TXPR1
TXPR15
TXPR14
TXPR13
TXPR12
TXPR11
TXPR10
TXPR9
TXPR8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
These bits set a transmit wait (CAN bus arbitration wait)
for the corresponding mailboxes 1 to 15. When TXPRn
(n = 1 to 15) is set to 1, the message in mailbox n
becomes the transmit wait state.
[Clearing conditions]
• Completion of message transmission
• Completion of transmission cancellation
Bit 8 is reserved. This bit is always read as 1 and the
write value should always be 1.
Rev. 2.00, 03/04, page 286 of 508
11.3.6 Transmit Wait Cancel Register (TXCR)
TXCR controls the cancellation of transmit wait messages in mailboxes (buffers).
Bit Bit Name Initial
Value R/W Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXCR7
TXCR6
TXCR5
TXCR4
TXCR3
TXCR2
TXCR1
TXCR15
TXCR14
TXCR13
TXCR12
TXCR11
TXCR10
TXCR9
TXCR8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
These bits cancel the transmit wait message in the
corresponding mailboxes 1 to 15. When TXCRn (n = 1
to 15) is set to 1, the transmit wait message in mailbox
n is canceled.
[Clearing condition]
• Completion of TXPR clearing when transmit
message is canceled normally
Bit 8 is reserved. This bit is always read as 0 and the
write value should always be 0.
Rev. 2.00, 03/04, page 287 of 508
11.3.7 Transmit Acknowledge Register (TXACK)
TXACK contains status flags that indicate the normal transmission of mailbox (buffer) transmit
messages.
Bit Bit Name Initial
Value R/W Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXACK7
TXACK6
TXACK5
TXACK4
TXACK3
TXACK2
TXACK1
TXACK15
TXACK14
TXACK13
TXACK12
TXACK11
TXACK10
TXACK9
TXACK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
These bits are status flags that indicate error-free
transmission of the transmit message in the
corresponding mailboxes 1 to 15. When the message in
mailbox n (n = 1 to 15) has been transmitted error-free,
TXACKn is set to 1.
[Setting condition]
• Completion of message transmission for
corresponding mailbox
[Clearing condition]
• Writing 1
Bit 8 is reserved. This bit is always read as 0 and the
write value should always be 0.
Note: Only 0 for clearing the flag can be written.
Rev. 2.00, 03/04, page 288 of 508
11.3.8 Abort Acknowledge Register (ABACK)
ABACK contains status flags that indicate the normal cancellation (aborting) of mailbox (buffer)
transmit messages.
Bit Bit Name Initial
Value R/W Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ABACK7
ABACK6
ABACK5
ABACK4
ABACK3
ABACK2
ABACK1
ABACK15
ABACK14
ABACK13
ABACK12
ABACK11
ABACK10
ABACK9
ABACK8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
These bits are status flags that indicate error-free
cancellation (abortion) of the transmit message in the
corresponding mailboxes 1 to 15. When the message in
mailbox n (n = 1 to 15) has been canceled error-free,
ABACKn is set to 1.
[Setting condition]
• Completion of transmit message cancellation for
corresponding mailbox
[Clearing condition]
• Writing 1
Bit 8 is reserved. This bit is always read as 0. The write
value should always be 0.
Note: Only 0 for clearing the flag can be written.
Rev. 2.00, 03/04, page 289 of 508
11.3.9 Receive Complete Register (RXPR)
RXPR contains status flags that indicate the normal reception of messages in mailboxes (buffers).
For reception of a remote frame, when a bit in this register is set to 1, the corresponding remote
request register (RFPR) bit is also set to 1 simultaneously.
Bit Bit Name Initial
Value R/W Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RXPR7
RXPR6
RXPR5
RXPR4
RXPR3
RXPR2
RXPR1
RXPR0
RXPR15
RXPR14
RXPR13
RXPR12
RXPR11
RXPR10
RXPR9
RXPR8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
When the message in mailbox n (n = 0 to 15) has been
received error-free, RXPRn is set to 1.
[Setting condition]
• Completion of message (data frame or remote
frame) reception in corresponding mailbox
[Clearing condition]
• Writing 1
Note: Only 0 for clearing the flag can be written.
Rev. 2.00, 03/04, page 290 of 508
11.3.10 Remote Req u e st Regi s ter ( RFP R)
RFPR contains status flags that indicate normal reception of remote frames in mailboxes (buffers).
When a bit in this reg ister is set to 1, the corresponding receive complete regist er (R XPR) bit is
also set to 1 simultaneously.
Bit Bit Name Initial
Value R/W Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RFPR7
RFPR6
RFPR5
RFPR4
RFPR3
RFPR2
RFPR1
RFPR0
RFPR15
RFPR14
RFPR13
RFPR12
RFPR11
RFPR10
RFPR9
RFPR8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
When mailbox n (n = 0 to 15) has received the remote
frame error-free, ABACKn (n = 0 to 15) is set to 1.
[Setting condition]
• Completion of remote frame reception in
corresponding mailbox
[Clearing condition]
• Writing 1
Note: Only 0 for clearing the flag can be written.
Rev. 2.00, 03/04, page 291 of 508
11.3.11 Interrupt Register (IRR)
IRR is an interrupt status flag register.
Bit Bit Name Initial
Value R/W Description
15 IRR7 0 R/(W)* Overload Frame Interrupt Flag
[Setting condition]
• When an overload frame is transmitted in error
active/passive state
[Clearing condition]
• Writing 1
14 IRR6 0 R/(W)* Bus Off Interrupt Flag
Status flag indicating the bus off state caused by the
transmit error counter.
[Setting condition]
• When TEC ≥ 256
[Clearing condition]
• Writing 1
13 IRR5 0 R/(W)* Error Passive Interrupt Flag
Status flag indicating the error passive state caused by
the transmit/receive error counter.
[Setting condition]
• When TEC ≥ 128 or REC ≥ 128
[Clearing condition]
• Writing 1
12 IRR4 0 R/(W)* Receive Overload Warning Interrupt Flag
Status flag indicating the error warning state caused by
the receive error counter.
[Setting condition]
• When REC ≥ 96
[Clearing condition]
• Writing 1
Rev. 2.00, 03/04, page 292 of 508
Bit Bit Name Initial
Value R/W Description
11 IRR3 0 R/(W)* Transmit Overload Warning Interrupt Flag
Status flag indicating the error warning state caused by
the transmit error counter.
[Setting condition]
• When TEC ≥ 96
[Clearing condition]
• Writing 1
10 IRR2 0 R Remote Frame Request Interrupt Flag
Status flag indicating that a remote frame has been
received in a mailbox (buffer).
[Setting condition]
• When remote frame reception is completed, when
corresponding MBIMR = 0
[Clearing condition]
• Clearing of all bits in RFPR (remote request
register)
9 IRR1 0 R Received message Interrupt Flag
Status flag indicating that a mailbox (buffer) received
message has been received normally.
[Setting condition]
• When data frame or remote frame reception is
completed, when corresponding MBIMR = 0
[Clearing condition]
• Clearing of all bits in RXPR (receive complete
register)
8 IRR0 1 R/(W)* Reset Interrupt Flag
Status flag indicating that the HCAN module has been
reset. This bit cannot be masked by the interrupt mask
register (IMR). If this bit is not cleared to 0 after entering
power-on reset or returning from software standby
mode, interrupt processing will start immediately when
the interrupt controller enables interrupts.
[Setting condition]
• When the reset operation has finished after entering
power-on reset or software standby mode
[Clearing condition]
• Writing 1
Rev. 2.00, 03/04, page 293 of 508
Bit Bit Name Initial
Value R/W Description
7 to 5 All 0 Reserved
These bits are always read as 0. The write value should
always be 0.
4 IRR12 0 R/(W)* Bus Operation Interrupt Flag
Status flag indicating detection of a dominant bit due to
bus operation when the HCAN module is in HCAN
sleep mode.
[Setting condition]
• Bus operation (dominant bit) detection in HCAN
sleep mode
[Clearing condition]
• Writing 1
3, 2 All 0 Reserved
These bits are always read as 0. The write value should
always be 0.
1 IRR9 0 R Unread Interrupt Flag
Status flag indicating that a received message has been
overwritten before being read.
[Setting condition]
• When UMSR (unread message status register) is
set
[Clearing condition]
• Clearing of all bits in UMSR (unread message
status register)
0 IRR8 0 R/(W)* Mailbox Empty Interrupt Flag
Status flag indicating that the next transmit message
can be stored in the mailbox.
[Setting condition]
• When TXPR (transmit wait register) is cleared by
completion of transmission or completion of
transmission abort
[Clearing condition]
• Writing 1
Note: Only 0 for clearing the flag can be written.
Rev. 2.00, 03/04, page 294 of 508
11.3.12 Mailbox Interrupt Mask Register (MBIMR)
MBIMR controls the enabling or disabling of individual mailbox (buffer) interrupt requests.
Bit Bit Name Initial
Value R/W Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MBIMR7
MBIMR6
MBIMR5
MBIMR4
MBIMR3
MBIMR2
MBIMR1
MBIMR0
MBIMR15
MBIMR14
MBIMR13
MBIMR12
MBIMR11
MBIMR10
MBIMR9
MBIMR8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mailbox Interrupt Mask (MBIMRx)
When MBIMRn (n = 0 to 15) is cleared to 0, the
interrupt request in mailbox n is enabled. When set to 1,
the interrupt request is masked.
The interrupt source in a transmit mailbox is TXPR
clearing caused by transmission end or transmission
cancellation. The interrupt source in a receive mailbox
is RXPR setting on reception end.
Rev. 2.00, 03/04, page 295 of 508
11.3.13 Interrupt Mask Register (IMR)
IMR contains flags that enable or disable requests by individual interrupt sources. The interrupt
flag cannot be masked.
Bit Bit Name Initial
Value R/W Description
15 IMR7 1 R/W Overload Frame Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt request by
IRR7) is enabled. When set to 1, OVR0 is masked.
14 IMR6 1 R/W Bus Off Interrupt Mask
When this bit is cleared to 0, ERS0 (interrupt request by
IRR6) is enabled. When set to 1, ERS0 is masked.
13 IMR5 1 R/W Error Passive Interrupt Mask
When this bit is cleared to 0, ERS0 (interrupt request by
IRR5) is enabled. When set to 1, ERS0 is masked.
12 IMR4 1 R/W Receive Overload Warning Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt request by
IRR4) is enabled. When set to 1, OVR0 is masked.
11 IMR3 1 R/W Transmit Overload Warning Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt request by
IRR3) is enabled. When set to 1, OVR0 is masked.
10 IMR2 1 R/W Remote Frame Request Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt request by
IRR2) is enabled. When set to 1, OVR0is masked.
9 IMR1 1 R/W Received message Interrupt Mask
When this bit is cleared to 0, RM1 (interrupt request by
IRR1) is enabled. When set to 1, RMI is masked.
8 0 R Reserved
This bit is always read as 0. Only 0 should be written to
this bit.
7 to 5 All 1 R Reserved
These bits are always read as 1. The write value should
always be 0.
Rev. 2.00, 03/04, page 296 of 508
Bit Bit Name Initial
Value R/W Description
4 IMR12 1 R/W Bus Operation Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt request by
IRR12) is enabled. When set to 1, OVR0 is masked.
3, 2 All 1 R Reserved
These bits are always read as 1. The write value should
always be 0.
1 IMR9 1 R/W Unread Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt request by
IRR9) is enabled. When set to 1, OVR0 is masked.
0 IMR8 1 R/W Mailbox Empty Interrupt Mask
When this bit is cleared to 0, SLE0 (interrupt request by
IRR8) is enabled. When set to 1, SLE0 is masked.
11.3.14 Receive Error Counter (REC)
REC is an 8-bit read-only register that functions as a counter indicating the number of received
message errors on the CAN bus. The count value is stipulated in the CAN protocol.
11.3.15 Transmit Error Counter (TEC)
TEC is an 8-bit read-only register that functions as a counter indicating the number of transmit
message errors on the CAN bus. The count value is stipulated in the CAN protocol.
Rev. 2.00, 03/04, page 297 of 508
11.3.16 Unread Message Status Register (U MSR)
UMSR contains status flags that indicate, for individual mailboxes (buffers), that a received
message has been overwritten by a new received message before being read. When overwritten by
a new message, data in the unread received message is lost.
Bit Bit Name Initial
Value R/W Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UMSR7
UMSR6
UMSR5
UMSR4
UMSR3
UMSR2
UMSR1
UMSR0
UMSR15
UMSR14
UMSR13
UMSR12
UMSR11
UMSR10
UMSR9
UMSR8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
[Setting condition]
• When a new message is received before RXPR is
cleared
[Clearing condition]
• Writing 1
Note: * Only 1 is writable to clear the flag.
Rev. 2.00, 03/04, page 298 of 508
11.3.17 Local Acceptance Filter Masks (LAFML, LAFMH)
LAFML and LAFMH individually set the iden tifier bits of the message to be stored in mailbox 0
as Don't Care. For details, see section 11.4.4, Message Reception. The relationship between the
identifier bits and mask bits are shown in the following.
• LAFML
Bit Bit Name
Initial
Value R/W Description
15 LAFML7 0 R/W When this bit is set to 1, ID-7 of the received message
identifier is not compared.
14 LAFML6 0 R/W When this bit is set to 1, ID-6 of the received message
identifier is not compared.
13 LAFML5 0 R/W When this bit is set to 1, ID-5 of the received message
identifier is not compared.
12 LAFML4 0 R/W When this bit is set to 1, ID-4 of the received message
identifier is not compared.
11 LAFML3 0 R/W When this bit is set to 1, ID-3 of the received message
identifier is not compared.
10 LAFML2 0 R/W When this bit is set to 1, ID-2 of the received message
identifier is not compared.
9 LAFML1 0 R/W When this bit is set to 1, ID-1 of the received message
identifier is not compared.
8 LAFML0 0 R/W When this bit is set to 1, ID-0 of the received message
identifier is not compared.
7 LAFML15 0 R/W When this bit is set to 1, ID-15 of the received message
identifier is not compared.
6 LAFML14 0 R/W When this bit is set to 1, ID-14 of the received message
identifier is not compared.
5 LAFML13 0 R/W When this bit is set to 1, ID-13 of the received message
identifier is not compared.
4 LAFML12 0 R/W When this bit is set to 1, ID-12 of the received message
identifier is not compared.
3 LAFML11 0 R/W When this bit is set to 1, ID-11 of the received message
identifier is not compared.
2 LAFML10 0 R/W When this bit is set to 1, ID-10 of the received message
identifier is not compared.
1 LAFML9 0 R/W When this bit is set to 1, ID-9 of the received message
identifier is not compared.
0 LAFML8 0 R/W When this bit is set to 1, ID-8 of the received message
identifier is not compared.
Rev. 2.00, 03/04, page 299 of 508
• LAFMH
Bit Bit Name Initial
Value R/W Description
15 LAFMH7 0 R/W When this bit is set to 1, ID-20 of the received message
identifier is not compared.
14 LAFMH6 0 R/W When this bit is set to 1, ID-19 of the received message
identifier is not compared.
13 LAFMH5 0 R/W When this bit is set to 1, ID-18 of the received message
identifier is not compared.
12 to 10 All 0 R Reserved
These bits are always read as 0. Only 0 should be
written to these bits.
9 LAFMH1 0 R/W When this bit is set to 1, ID-17 of the received message
identifier is not compared.
8 LAFMH0 0 R/W When this bit is set to 1, ID-16 of the received message
identifier is not compared.
7 LAFMH15 0 R/W When this bit is set to 1, ID-28 of the received message
identifier is not compared.
6 LAFMH14 0 R/W When this bit is set to 1, ID-27 of the received message
identifier is not compared.
5 LAFMH13 0 R/W When this bit is set to 1, ID-26 of the received message
identifier is not compared.
4 LAFMH12 0 R/W When this bit is set to 1, ID-25 of the received message
identifier is not compared.
3 LAFMH11 0 R/W When this bit is set to 1, ID-24 of the received message
identifier is not compared.
2 LAFMH10 0 R/W When this bit is set to 1, ID-23 of the received message
identifier is not compared.
1 LAFMH9 0 R/W When this bit is set to 1, ID-22 of the received message
identifier is not compared.
0 LAFMH8 0 R/W When this bit is set to 1, ID-21 of the received message
identifier is not compared.
Rev. 2.00, 03/04, page 300 of 508
11.3.18 Message Control (MC0 to MC15)
The message control register sets consist of eight 8-bit registers for one mailbox. The HCAN has
16 sets of these registers. Because message control registers are in RAM, their initial values after
power-on are undefined. Be sure to initialize them by writing 0 or 1. Figure 11.2 shows the
register names for each mailbox.
MC0[1]
MC1[1]
MC2[1]
MC3[1]
MC15[1]
MC0[2]
MC1[2]
MC2[2]
MC3[2]
MC15[2]
MC0[3]
MC1[3]
MC2[3]
MC3[3]
MC15[3]
MC0[4]
MC1[4]
MC2[4]
MC3[4]
MC15[4]
MC0[5]
MC1[5]
MC2[5]
MC3[5]
MC15[5]
MC0[6]
MC1[6]
MC2[6]
MC3[6]
MC15[6]
MC0[7]
MC1[7]
MC2[7]
MC3[7]
MC15[7]
MC0[8]
MC1[8]
MC2[8]
MC3[8]
MC15[8]
Mail box 0
Mail box 1
Mail box 2
Mail box 3
Mail box 15
Figure 11.2 Message Control Register Configuration
The settings of message control registers are shown in the following. Figures 11.3 and 11.4 show
the correspondence between the identifiers and register bit names.
SOF ID-28 ID-27 ID-18 RTR IDE R0
identifier
Figure 11.3 Standard Format
SOF ID-28 ID-27 ID-18 SRR IDE ID-17 ID-16 ID-0 RTR R1
Standard identifier Extended identifier
Figure 11.4 Extended Format
Rev. 2.00, 03/04, page 301 of 508
Register
Name Bit Bit Name R/W Description
7 to 4 R/W The initial value of these bits is undefined; they must be
initialized (by writing 0 or 1).
MCx[1]
3 to 0 DLC3 to DLC0 R/W Data Length Code
Set the data length of a data frame or the data length
requested in a remote frame within the range of 0 to 8 bits.
0000: 0 byte
0001: 1 byte
0010: 2 bytes
0011: 3 bytes
0100: 4 bytes
0101: 5 bytes
0110: 6 bytes
0111: 7 bytes
1000: 8 bytes
:
:
1111: 8 bytes
MCx[2] 7 to 0 R/W
MCx[3] 7 to 0 R/W
MCx[4] 7 to 0 R/W
The initial value of these bits is undefined; they must be
initialized (by writing 0 or 1).
7 to 5 ID-20 to ID-18 R/W Sets ID-20 to ID-18 in the identifier.
4 RTR R/W Remote Transmission Request
Used to distinguish between data frames and remote
frames.
0: Data frame
1: Remote frame
3 IDE R/W Identifier Extension
Used to distinguish between the standard format and
extended format of data frames and remote frames.
0: Standard format
1: Extended format
2 R/W The initial value of this bit is undefined. It must be
initialized by writing 0 or 1.
MCx[5]
1 to 0 ID-17 to ID-16 R/W Sets ID-17 and ID-16 in the identifier.
MCx[6] 7 to 0 ID-28 to ID-21 R/W Sets ID-28 to ID-21 in the identifier.
MCx[7] 7 to 0 ID-7 to ID-0 R/W Sets ID-7 to ID-0 in the identifier.
MCx[8] 7 to 0 ID-15 to ID-8 R/W Sets ID-15 to ID-8 in the identifier.
[Legend]
x: Mailbox number
Rev. 2.00, 03/04, page 302 of 508
11.3.19 Message Data (MD0 to MD15)
The message data register sets consist of eight 8-bit registers for one mailbox. The HCAN has 16
sets of these registers. Because message data registers are in RAM, their initial values after power-
on are undefined. Be sure to initialize them by writing 0 or 1. Figure 11.5 shows the register
names for each mailbox.
MD0[1]
MD1[1]
MD2[1]
MD3[1]
MD15[1]
MD0[2]
MD1[2]
MD2[2]
MD3[2]
MD15[2]
MD0[3]
MD1[3]
MD2[3]
MD3[3]
MD15[3]
MD0[4]
MD1[4]
MD2[4]
MD3[4]
MD15[4]
MD0[5]
MD1[5]
MD2[5]
MD3[5]
MD15[5]
MD0[6]
MD1[6]
MD2[6]
MD3[6]
MD15[6]
MD0[7]
MD1[7]
MD2[7]
MD3[7]
MD15[7]
MD0[8]
MD1[8]
MD2[8]
MD3[8]
MD15[8]
Mail box 0
Mail box 1
Mail box 2
Mail box 3
Mail box 15
Figure 11.5 Message Data Confi gur ation
Rev. 2.00, 03/04, page 303 of 508
11.4 Operation
11.4.1 Hardware and Software Resets
The HCAN can be reset by a hardware reset or software reset.
• Hardware Reset
At power-on reset, or in hardware or so ftware standby mode, the HCAN is initialized by
automatically setting the MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3)
in GSR. At the same time, all internal registers, except for message control and message data
registers, are initialized by a hardware reset.
• Software Reset
The HCAN can be reset by setting the MCR reset request bit (MCR0) in MCR via software. In
a software reset, the error counters (TEC and REC) are initialized, however other registers are
not. If the MCR0 bit is set while the CAN controller is performing a communication operation
(transmission or reception), the initialization state is not entered until message transfer has
been completed. The reset status bit (GSR3) in GSR is set on completion of initializatio n.
11.4.2 Initialization after Hardware Reset
After a hardware reset, the follow ing initialization processing shou ld be carried out:
1. Clearing of IRR0 bit in the interrupt register (IRR)
2. Bit rate setting
3. Mailbox transmit/receive settings
4. Mailbox (RAM) initialization
5. Message transmission method setting
These initial settings must be made while th e HCAN is in bit configuration mode. Conf igur ation
mode is a state in which th e GS R3 bit in GSR is set to 1 by a reset. Configuration mode is exited
by clearing the MCR0 bit in MCR to 0; when the MCR0 bit is cleared to 0, the HCAN
automatically clears the GSR3 bit in GSR. There is a delay between clearing the MCR0 bit and
clearing the GSR3 bit because the HCAN needs time to be internally reset, there is a delay
between clearing of the MCR0 bit and GSR3 bit. After the HCAN exits configuration mode, the
power-up sequence begins, and communication with the CAN bus is possible as soon as 11
consecutive recessive bits have been detected.
IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a power-on reset or recovery
from software standb y mode. As an HCA N interr u pt is initiated immediately when interrupts are
enabled, IRR0 should be cleared.
Rev. 2.00, 03/04, page 304 of 508
Hardware reset
MCR0 = 1 (automatic)
IRR0 = 1 (automatic)
GSR3 = 1 (automatic)
MCR0 = 0
GSR3 = 0?
Yes
No
GSR3 = 0 & 11
recessive bits received?
Can bus communication enabled
Yes
No
Bit configuration mode
Period in which BCR, MBCR, etc.,
are initialized
: Settings by user
: Processing by hardware
Initialization of HCAN module
Clear IRR0
BCR setting
MBCR setting
Mailbox initialization
Message transmission method initialization
IMR setting (interrupt mask setting)
MBIMR setting (interrupt mask setting)
MC[x] setting (receive identifier setting)
LAFM setting (receive identifier mask setting)
Figure 11.6 Hardware Reset Flowchart
Rev. 2.00, 03/04, page 305 of 508
MCR0 = 1
GSR3 = 1 (automatic)
Initialization of REC and TEC only
MCR0 = 0
GSR3 = 0?
CAN bus communication enabled
Bus idle?
Yes
Correction
Yes
Correction
: Settings by user
: Processing by hardware
No
No
No
No
No
BCR setting
MBCR setting
Mailbox (RAM) initialization
Message transmission method
initialization
OK?
IMR setting
MBIMR setting
MC[x] setting
LAFM setting
OK?
GSR3 = 0 & 11
recessive bits received?
Yes
GSR3 = 1? No
Yes
Yes
Yes
Figure 11.7 Software Reset Flowchart
Rev. 2.00, 03/04, page 306 of 508
Bit Rate and Bit Timing Settings: The bit rate and bit timing settings are made in the bit
configuration register (BCR). Settings should be made such that all CAN controllers connected to
the CAN bus have the same baud rate and bit w idth. The 1-bit time consists of the total of the
settable time quantum (tq).
SYNC_SEG PRSEG PHSEG1 PHSEG2
Time segment 2
(TSEG2)
Time segment 1 (TSEG1)
1-bit time (8–25 time quanta)
2–16 time quanta 2–8 time quanta1 time quantum
Figure 11.8 Detailed Description of One Bit
SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal
bit edge transition s o c cur in this segment. PRSEG is a segment for compensating for the physical
delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This
segment is extended when synchronization (resynchronization) is established. PHSEG2 is a buffer
segment for correcting phase drift (negative). This segment is shortened when synchronization
(resynchronization) is established. Limits on the settable value (TSEG1, TSEG2, BRP, sample
point, and SJW) are shown in table 11.2.
Table 11.2 Limits for the Settable Value
Name Abbreviation Min. Value Max. Value
Time segment 1 TSEG1 3*2 15
Time segment 2 TSEG2 1*3 7
Baud rate prescaler BRP 0 63
Bit sample point BSP 0 1
Re-synchronization jump width SJW*1 0 3
Notes: 1. SJW is stipulated in the CAN specifications:
3 ≥ SJW ≥ 0
2. The minimum value of TSEG2 is stipulated in the CAN specifications:
TSEG2 ≥ SJW
3. The minimum value of TSEG1 is stipulated in the CAN specifications:
TSEG1 > TSEG2
Rev. 2.00, 03/04, page 307 of 508
Time Quanta (TQ) is an integer multiple of the number of system clocks, and is determined by the
baud rate prescaler (BRP) as follows. fCLK is the system clock frequency.
TQ = 2 × (BPR setting + 1)/fCLK
The following formula is used to calculate the 1-bit time and bit rate.
1-bit time = TQ × (3 + TSEG1 + TSEG2)
Bit rate = 1/Bit time
= fCLK/{2 × (BPR setting + 1) × (3 + TSEG1 + TSEG2)}
Note: fCLK = φ (system clock)
A BCR value is used for BRP, TSEG1, and TSEG2.
Example: With a system clock of 20 MHz, a BRP setting of B'000000, a TSEG1 setting of
B'0100, and a TSEG2 setting of B'011:
Bit rate = 20/{2 × (0 + 1) × (3 + 4 + 3)} = 1 Mbps
Table 11.3 Setting Range for TSEG1 and TSEG2 in BCR
TSEG2 (BCR[14:12])
001 010 011 100 101 110 111
0011 No Yes No No No No No
0100 No* Yes Yes No No No No
0101 No* Yes Yes Yes No No No
TSEG1
(BCR[11:8])
0110 No* Yes Yes Yes Yes No No
0111 No* Yes Yes Yes Yes Yes No
1000 No* Yes Yes Yes Yes Yes Yes
1001 No* Yes Yes Yes Yes Yes Yes
1010 No* Yes Yes Yes Yes Yes Yes
1011 No* Yes Yes Yes Yes Yes Yes
1100 No* Yes Yes Yes Yes Yes Yes
1101 No* Yes Yes Yes Yes Yes Yes
1110 No* Yes Yes Yes Yes Yes Yes
1111 No* Yes Yes Yes Yes Yes Yes
Note: * Do not set a Baud Rate Prescaler (BRP) value of B'000000 (2 × system clock).
Rev. 2.00, 03/04, page 308 of 508
Mailbox Transmit/Receive Settings: The HCAN has 16 mailboxes. Mailbox 0 is receive-only,
while mailboxes 1 to 15 can be set for transmission or reception. The Initial status of mailboxes 1
to 15 is for transmission. Mailbox transmit/receive settings are not initialized by a software reset.
Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding
mailbox for transmission use, whereas a setting of 1 in MBCR designates the corresponding
mailbox for reception use. When setting mailboxes for reception, in order to improve message
reception efficiency, high-priority messages should be set in low-to-high mailbox order.
Mailbox (Message Control/Data) Initial Settings: Message control/data are held in RAM, and
so their initial values are undefined after power is supplied. Initial va lues must therefore be set in
all the mailboxes (by writing 0s or 1s).
Setting the Message Transmission Method: The following two kinds of message transmission
methods are available.
• Transmission order determined by message identifier priority
• Transmission order determined by mailbox number priorit y
Either of the message transmission methods can be selected with the message transmission method
bit (MCR2) in the master control register (MCR): When messages are set to be transmitted
according to the message identifier priority, if several messages are designated as waiting for
transmission (TXPR = 1), the message with the highest priority in the message identifier is stored
in the transmit buffer. CAN bus arbitration is then carried out for the message stored in the
transmit buffer, and the message is transmitted wh en the transmission right is acquired. When the
TXPR bit is set, the highest-priority message is found and stored in the transmit buffer.
When messages are set to be transmitted according to the mailbox number priority, if several
messages are designated as waiting for transmission (TXPR = 1), messages are stored in the
transmit buffer in low-to-high mailbox order. CAN bus arbitration is then carried out for the
message stored in the transmit buffer, an d the message is transmitted when the transmission right
is acquired.
Rev. 2.00, 03/04, page 309 of 508
11.4.3 Message Transmission
Messages are transmitted using mailboxes 1 to 15. Th e transmission procedure after initial settings
is described below, and a transmission flowchart is shown in figure 11.9.
Initialization (after hardware reset only)
Clear IRR0
BCR setting
MBCR setting
Mailbox initialization
Message transmission method setting
Yes
No
Yes
Yes
: Settings by user
: Processing by hardware
No
No
Interrupt settings
Transmit data setting
Arbitration field setting
Control field setting
Data field setting
Message transmission
GSR2 = 0 (during transmission only)
TXACK = 1
IRR8 = 1
Clear TXACK
Clear IRR8
Message transmission wait
TXPR setting
Bus idle?
Transmission completed?
IMR8 = 1?
Interrupt to CPU
End of transmission
Figure 11.9 Transmission Fl owchart
Rev. 2.00, 03/04, page 310 of 508
CPU Interrupt Source Settings: The CPU interrup t sour ce is set by the interrupt mask register
(IMR) and mailbox interrupt mask register (MBIMR). Transmission acknowledge and
transmission abort acknowledge interrupts can be generated for individual mailboxes in the
mailbox interrupt mask register (MBIMR).
Arbitration Field Setting: The arbitration field is set by message control registers MCx[5]–
MCx[8] in a transmit mailbox. For a standard format, an 11-bit identifier (ID -28 to ID-18) and the
RTR bit are set, and the IDE bit is cleared to 0. For an extended format, a 29-bit identifier (ID-28
to ID-0) and the RTR bit are set, and the IDE bit is set to 1.
Control Field Setting: In the control field, the byte length of the data to be transmitted is set
within the range of zero to eight bytes. The register to be set is the message control register
MCx[1] in a transmit mailbox.
Data Field Setting: In the data field, the data to be transmitted is set within the range zero to
eight. The registers to be set are the message data registers MDx[1]–MDx[8]. The byte length of
the data to be transmitted is determined by the data length code in the control field. Even if data
exceeding the value set in the control field is set in the data field, up to the byte length set in the
control field will actually be transmitted.
Message Transmission: If the corresponding mailbox transmit wait bit (TXPR1–TXPR1 5) in the
transmit wait register (TXPR) is set to 1 after message control and message data registers have
been set, the message enters transmit wait state. If the message is transmitted error-free, the
corresponding acknowledge bit (TXACK1–TXACK15) in the transmit acknowledge register
(TXACK) is set to 1, and the correspond ing transmit wait bit (TXPR1–TXPR15) in the transmit
wait register (TXPR) is automatically cleared to 0. Also, if the corresponding bit (MBIMR1-
MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit
(IRR8) in the interrupt mask register (IMR) are both simultaneously set to enable interrupts,
interrupts may be sent to the CPU.
If transmission of a transmit message is aborted in the following cases, the message is
retransmitted automatically:
• CAN bu s arbitration failure (failure to acquire the bus)
• Error during transmission (bit error, stuff error, CRC error, frame error, or ACK error)
Message Transmission Cancellation: Transmission cancellation can be specified for a message
stored in a mailbox as a transmit wa it message. A transmit wait message is canceled by setting the
bit for the corresponding mailbox (TXCR1–TXCR15) to 1 in the transmit cancel register (TXCR).
Clearing the transmit wait register (TXPR) does not cancel transmission. When cancellation is
executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is set
to 1 in the abort acknowledge register (ABACK). An interrupt to the CPU can be requested, and if
the mailbox empty interrupt (IRR8) is enabled for the bits (MBIMR1-MBIMR15) corresponding
Rev. 2.00, 03/04, page 311 of 508
to the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR), interrupts may
be sent to the CPU.
However, a transmit wait message cannot be canceled at the following times:
• During internal arbitratio n or CAN bus arbitration
• During data frame or remote frame transmission
Figure 11.10 shows a flowchart for transmit message cancellation.
Message transmit wait TXPR setting
Yes
No
Yes
No
: Settings by user
: Processing by hardware
Set TXCR bit corresponding to
message to be canceled
Message not sent
Clear TXCR, TXPR
ABACK = 1
IRR8 = 1
Clear TXACK
Clear ABACK
Clear IRR8
Completion of message transmission
TXACK = 1
Clear TXCR, TXPR
IRR8 = 1
Cancellation possible?
IMR8 = 1?
End of transmission/transmission
cancellation
Interrupt to CPU
Figure 11.10 Transmit Message Cancellation Flowchart
Rev. 2.00, 03/04, page 312 of 508
11.4.4 Message Reception
The reception procedure after initial settings is described below. A reception flowchart is shown in
figure 11.11.
RXPR
IRR1 = 1
No
IMR2 = 1?
Interrupt to CPU
Yes
No
Yes
Yes Yes
No
: Settings by user
: Processing by hardware
No
Yes
Initialization
Clear IRR0
BCR setting
MBCR setting
Mailbox (RAM) initialization
Receive data setting
Arbitration field setting
Local acceptance filter settings
Interrupt settings
Message reception
(Match of identifier
in mailbox?)
Same RXPR = 1?
IMR1 = 1?
Data frame?
Interrupt to CPU
Clear IRR1
End of reception
Clear IRR2, IRR1
Unread message
No
RXPR, RFPR = 1
IRR2 = 1, IRR1 = 1
Message control read
Message data read
Message control read
Message data read
Transmission of data frame corresponding
to remote frame
Figure 11.11 Reception Flowchart
Rev. 2.00, 03/04, page 313 of 508
CPU Interrupt Source Settings: CPU interrupt source settings are made in the interrupt mask
register (IMR) and mailbox interrupt register (MBIMR). The message to be received is also
specified. Data frame and remote frame receive wait interrupt requests can be generated for
individual mailboxes in the MBIMR.
Arbitration Field Setting: To receive a message, the message identifier must be set in advance in
the message control r egisters (MCx[1]–MCx[8]) for the receiving mailbo x. When a message is
received, all the bits in the received message identifier are compared with those in each message
control register identifier, and if a 100% match is found, the message is stored in the matching
mailbox. Mailbox 0 has a local acceptance filter mask (LAFM) that allows Don't Care settings to
be made. The LAFM setting can be ma de onl y f or mail box 0. B y maki n g the Don't Car e setti ng
for all the bits in the received message identifier, messages of multiple identifiers can be received.
Examples:
• When the identifier of mailbox 1 is 010_1010_1010 (standard format) , only one kind of
message identifier can be received by mailbox 1:
Identifier 1: 010_1010_1010
• When the identifier of mailbox 0 is 010_1010_1010 (standard format) and the LAFM setting is
000_0000_0011 (0: Care, 1: Don't Care), a total of four kinds of message identifiers can be
received by mailbox 0:
Identifier 1: 010_1010_1000
Identifier 2: 010_1010_1001
Identifier 3: 010_1010_1010
Identifier 4: 010_1010_1011
Message Reception: When a message is received, a CRC check is performed automatically. If the
result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether
the message can be received or not.
• Data frame reception
If the received message is confirmed to be error-free by the CRC check, the identifier in the
mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the received
message, are co mpared. If a complete match is found, the message is stored in the mailbox.
The message identifier comparison is carried out on each mailbox in turn, starting w ith
mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison ends at
that point, the message is stored in the matching mailbox, and the corresponding receive
complete bit (RXPR0–RXPR15) is set in the receive complete register (RXPR). However,
when a m ailbox 0 LAFM comparison is carried out, ev en if the identifier matches, the mailbox
comparison sequence does not end at that point, but continues with mailbox 1 and then the
remaining mailboxes. It is therefore possible for a message matching mailbox 0 to be received
by another mailbox. Note that the same message cannot be stored in more than one of
mailboxes 1 to 15. On receiving a message, a CPU interrupt request may be generated
Rev. 2.00, 03/04, page 314 of 508
depending on the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR)
settings.
• Remote frame reception
Two kinds of messages—data frames and remote frames—can be stored in mailboxes. A
remote frame differs from a data frame in that the remote transmission request bit (RTR) in the
message control register and the data field are 0 bytes long. The data length to be returned in a
data frame must be stored in the data length code (DLC) in the control field.
When a remote frame (RTR = recessive) is received, the corresponding bit is set in the remote
request wait register (RFPR). If the corresponding bit (MBIMR0–MBIMR15) in the mailbox
interrupt mask register (MBIMR) and the remote frame request in terrupt mask (IRR2) in th e
interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can
be sent to the CPU.
Unread Message Overwrite: If the received message identifier matches the mailbox identifier,
the received message is stored in the mailbox regardless of whether the mailbox contains an
unread message or not. If a message overwrite occurs , the correspond ing bit (UMSR0–UMSR15)
is set in the unread message register (UMSR). In overwriting an unread message, when a new
message is received before the corresponding bit in the receive complete register (RXPR) has been
cleared, the unread message register (UMSR) is set. If the unread interrupt flag (IRR9) in the
interrupt mask register (IMR) is set to the interrupt enable value at this time, an interrup t can be
sent to the CPU. Figure 11.12 shows a flowchart for unread message overwriting.
Rev. 2.00, 03/04, page 315 of 508
No
: Settings by user
Unread message overwrite
Interrupt to CPU
End
IMR9 = 1?
UMSR = 1
IRR9 = 1
Clear IRR9
Message control/message data read
: Processing by hardware
Yes
Figure 11.12 Unread Message Overwrite Flowchart
11.4.5 HCAN Sleep Mode
The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep
state in order to redu ce current dissipation. Figure 11.13 shows a flowchart of the H CAN sleep
mode.
Rev. 2.00, 03/04, page 316 of 508
IRR12 = 1
Yes
MCR5 = 0
Yes
Yes
MCR5 = 0
Clear sleep mode?
Yes
No
No
No
Yes (manual)
No (automatic)
MCR5 = 1
Bus idle?
Initialize TEC and REC
Bus operation?
: Settings by user
: Processing by hardware
No
No
IMR12 = 1?
Sleep mode clearing method
MCR7 = 0?
11 recessive bits?
Yes
No
GSR3 = 1?
Yes
No
GSR3 = 1?
CAN bus communication possible
CPU interrupt
Do not access MB
during this sequence
Figure 11.13 HCAN Sleep Mode Flowchart
Rev. 2.00, 03/04, page 317 of 508
HCAN sleep mode is entered by settin g the HCAN sleep mode bit (MCR5) to 1 in the master
control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is
delayed until the bus beco me s idle .
Either of the following methods of clearing HCAN sleep mode can be selected:
• Clearing by software
• Clearing by CAN bus operation
Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus
communication is re-enabled.
Clearing by Software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU.
Clearing by CAN Bus Operation: The cancellation method is selected by the MCR7 bit setting
in MCR. Clearing by CAN bus operation occurs automatically when the CAN bus performs an
operation and this change is detected. In this case, the first message is not stored in a mailbox;
messages will be received normally from the second message onward. When a change is detected
on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the
interrupt register (IRR). If the bus interrup t mask (IMR12) in the interr upt mask register (IMR) is
set to the interrup t enable value at this time, an interrupt can be sent to the CPU.
Rev. 2.00, 03/04, page 318 of 508
11.4.6 HCAN Halt Mode
The HCAN halt mode is provided to enable mailbox settings to be changed without performing an
HCAN hardwa re or soft ware reset. Figure 11.14 shows a flo wcha rt of t he HCA N hal t mo de.
MCR1 = 1
Yes
: Settings by user
: Processing by hardware
No
Bus idle?
MBCR setting
MCR1 = 0
CAN bus communication possible
Figure 11.14 HCAN Halt Mode Flowchart
HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control
register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until
the bus becomes idle.
HCAN halt mode is cleared by clearing MCR1 to 0.
Rev. 2.00, 03/04, page 319 of 508
11.5 Interrupts
Table 11.4 lists the HCAN interrupt sources. With the exception of the reset processing vector
(IRR0), these sources can be masked. Masking is implemented using the mailbox interrupt mask
register (MBIMR) and interrupt mask register (IMR). For details on the interrupt vector of each
interrupt source, see section 5, Interrupt Controller.
Table 11.4 HCAN Interrupt Sources
Name Description Interrupt Flag
Error passive interrupt (TEC ≥ 128 or REC ≥ 128) IRR5
Bus off interrupt (TEC ≥ 256) IRR6
Reset process interrupt by power-on reset IRR0
Remote frame reception IRR2
Error warning interrupt (TEC ≥ 96) IRR3
Error warning interrupt (REC ≥ 96) IRR4
Overload frame transmission interrupt IRR7
Unread message overwrite IRR9
ERS0/OVR0
Detection of CAN bus operation in HCAN sleep mode IRR12
RM0 Mailbox 0 message reception IRR1
RM1 Mailbox 1-15 message reception IRR1
SLE0 Message transmission/cancellation IRR8
Rev. 2.00, 03/04, page 320 of 508
11.6 CAN Bus Interface
A bus transceiver IC is necessary to connect this LSI to a CAN bus. A Philips PCA82C250
transceiver IC is recommended. Any other product must be compatible with the PCA82C250.
Figure 11.15 sh ows a sample connection diagram.
RS
RxD
TxD
Vref
Vcc
CANH
CANL
GND
HRxD
NC
Note: NC: No Connection
HTxD
This LSI
CAN bus
124
124
Vcc
PCA82C250
Figure 11.15 High-Speed Interface Using PCA82C250
11.7 Usage Notes
11.7.1 Module Stop Mode Setting
HCAN operation can be disabled or enabled using the module stop control register. The initial
setting is for HCAN operation to be halted. Register access is enabled by clearing module stop
mode. For details, see section 19, Power-Down Modes.
11.7.2 Reset
The HCAN is reset by a power-on reset, in hardwa re standby mode, and in software standby
mode. All the registers are initialized in a reset, however mailboxes (message control
(MCx[x])/message data (MDx[x])) are not. After power-on, mailboxes (message control
(MCx[x])/message data (MDx[x])) are not initialized, and their values are undefined. Therefore,
mailbox initialization must always be carried out after a power-on reset, a transition to hardware
standby mode, or software standby mode. The reset interrupt flag (IRR0) is always set after a
power-on reset or recovery from software standby mode. As this bit cannot be masked in the
interrupt mask register (IMR), if HCAN interrupt enabling is set in the interrupt controller without
clearing the flag, an HCAN interrupt will be initiated immediately. IRR0 should therefore be
cleared during initialization.
Rev. 2.00, 03/04, page 321 of 508
11.7.3 HCAN Sleep Mode
The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by CAN bus
operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep
mode release. Note that the reset status bit (GSR3) in the general status register (GSR) is set in
sleep mode.
11.7.4 Interrupts
When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8, IRR2, or
IRR1) is not set by reception completion, transmission completion, or transmission cancellation
for the set mailboxes.
11.7.5 Error Counters
In the case of error active and error passive, REC and TEC normally count up and down. In the
bus-off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96
during the count, IRR4 and GSR1 are set.
11.7.6 Register Access
Byte or word access can be used on all HCAN registers. Longword access cannot be used.
11.7.7 HCAN Medium-Speed Mode
In medium-speed mode, neither read nor write is possible for the HCAN registers.
11.7.8 Register Hold in Standby Modes
All HCAN registers are initialized in hardware standby mode and software standby mode.
11.7.9 Usage of Bit Manipulation Instr uctions
The HCAN status flags are cleared by writing 1, so do not use a bit manipulation instruction to
clear a flag. When clearing a flag, use the MOV instruction to write 1 to only the bit that is to be
cleared.
Rev. 2.00, 03/04, page 322 of 508
11.7.10 HCAN TXCR Operation
1. When the transmit wait cancel register (TXCR) is used to cancel a transmit wait message in a
transmit wait mailbox, the corresponding bit to TXCR and the transm it w ait register (TXPR)
may not be cleared even if transmission is canceled. This occurs when the following conditions
are all satisfied.
• The HRxD pin is stacked to 1 because of a CAN bus error, etc.
• There is at least one mailbox waiting for transmission or being transmitted.
• The message transmission in a mailbox being transmitted is canceled by TXCR.
If this occurs, transmission is canceled. However, since TXPR and TXCR states are indicated
wrongly that a message is being cancelled, transmission cannot be restarted even if the stack
state of the HRxD pin is canceled and the CAN bus recovers the normal state. If there are at
least two transmission messages, a message which is not being transmitted is canceled and a
message being transmitted retains its state.
To avoid this, one of the following countermeasures must be executed.
• Transmission must not be canceled by TXCR. When transmission is normally completed after
the CAN bus has recovered, TXPR is cleared and the HCAN recovers the normal state.
• To cancel transmission, the corresponding bit to TXCR must be written to 1 continuously until
the bit becomes 0. TXPR and TXCR are cleared and the HCAN recovers the normal state.
2. When the bus-off state is entered while TXPR is set and the transmit wait state is entered, the
internal state machine does not operate even if TXCR is set during the bus-off state. Therefore
transmission cannot be canceled. The message can be canceled when one message is
transmitted or a transmission error occu rs after the bus-off state is recovered. To clear a
message after the bus-off state is recovered, the following countermeasures must be executed.
• A tran smit wait messag e must be cleared by resetting the HCAN during the bus-off period.
To reset the HCAN, the module stop bit (MSTPC3 in MSTPCRC) must be set or cleared. In
this case, the HCAN is entirely reset. Therefore the initial settings must be made again.
Rev. 2.00, 03/04, page 323 of 508
11.7.11 HCAN Transmit Procedure
When transmission is set while the bus is in the idle state, if the next transmission is set or the set
transmission is canceled under the following conditions within 50 µs, the transmit message ID of
being set may be damaged.
• When the second transmission has the message whose priority is higher than the first one
• When the massage of the highest priority is canceled in the first transmission
Make whichever setting sh own below to avoid the message IDs from being damaged.
• Set transmission in one TXPR. After transmission of all transmit messages is completed, set
transmission again (mass transmission setting). The interval between transmission settings
should be 50 µs or longer.
• Make the transmission setting according to the priority of transmit messages.
• Set the interval to be 50 µs or longer between TXPR and another TXPR or between TXPR and
TXCR.
Table 11.5 Interval Limi t ation between TXPR and TXP R or be twe e n TXP R an d T XC R
Baud Rate (bps) Set Interval (µs)
1 M 50
500 k 50
250 k 50
11.7.12 Note on Releasing the HCAN Software Reset and HCAN Sleep
Before releasing the HCAN software reset or HCAN sleep (MCR0 = 0 or MCR5 = 0), confirm
that the GSR3 bit (the reset status bit) is surely set to 1.
11.7.13 Note on Accessing Mailbox during the HCAN Sleep
Do not access the mailbox during the HCAN sleep. If accessed, the CPU might halt. Accessing
registers during the HCAN sleep does not cause the CPU halt, nor does accessing the mailbox in
other than the HCAN sleep mode.
Rev. 2.00, 03/04, page 324 of 508
Rev. 2.00, 03/04, page 325 of 508
Section 12 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allow s up to eight
analog input channels to be selected. The Block diagram of the A/D converter is shown in figure
12.1.
12.1 Features
• 10-bit resolution
• Eight input channels
• Conversion time: 13.3 µs per channel (at 20 MHz operation)
• Two operating modes
Single mode: Single-channel A/D conversion
Scan mode: Continuous A/D conversion on 1 to 4 channels
• Four data registers
Conversion results are held in a 16-bit data register for each channel
• Sample and hold function
• Three methods conversion start
Software
16-bit timer pulse unit (TPU) conversion start trigger
External trigger signal
• Interrupt request
An A/D conversion end interrupt request (ADI) can be generated
• Module stop mode can be set
ADCMS36A_000020020200
Rev. 2.00, 03/04, page 326 of 508
Module data bus
Control circuit
Internal data bus
10-bit D/A
Comparator
+
Sample-and-
hold circuit
ADI
interrupt
Bus interface
Successive approximations
register
Multiplexer
A
D
C
S
R
A
D
C
R
A
D
D
R
D
A
D
D
R
C
A
D
D
R
B
A
D
D
R
A
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
[Legend]
ADCR: A/D control register
ADCSR: A/D control/status register
ADDRA: A/D data register A
ADDRB: A/D data register B
ADDRC: A/D data register C
ADDRD: A/D data register D
ADTRG
Conversion start
trigger from TPU
φ/2
φ/4
φ/8
φ/16
AV
CC
AV
SS
Figure 12.1 Block Diagram of A/D Converter
Rev. 2.00, 03/04, page 327 of 508
12.2 Input/Output Pins
Table 12.1 summarizes the input pins used by the A/D converter. The eight analog input pins are
divided into four channel sets and two groups; analog input pins 0 to 3 (AN0 to AN3) comprising
group 0 and analog input pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc and AVss pins
are the power supply pins for the analog block in the A/D converter.
Table 12.1 Pin Configuration
Pin Name Symbol I/O Function
Analog power supply pin AVCC Input Analog block power supply and reference
voltage
Analog ground pin AVSS Input Analog block ground and reference voltage
Analog input pin 0 AN0 Input
Analog input pin 1 AN1 Input
Analog input pin 2 AN2 Input
Analog input pin 3 AN3 Input
Group 0 analog input pins
Analog input pin 4 AN4 Input
Analog input pin 5 AN5 Input
Analog input pin 6 AN6 Input
Analog input pin 7 AN7 Input
Group 1 analog input pins
A/D external trigger input pin ADTRG Input External trigger input pin for starting A/D
conversion
Rev. 2.00, 03/04, page 328 of 508
12.3 Register Descriptions
The A/D converter has the following registers. The MSTPA1 bit in the module stop control
register (MSTPCRA) specifies the modes of this module as module stop mode. For details o n
MSTPCRA, see section 19.1.3, Module Stop Control Registers A to D (MSTPCRA to
MSTPCRD).
• A/D data register A (ADDRA )
• A/D data register B (ADDRB)
• A/D data register C (ADDRC)
• A/D data register D (ADDRD )
• A/D control/status register (ADCSR)
• A/D control register (ADCR)
12.3.1 A/D Data Registers A to D (ADDRA to ADDRD)
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are
shown in table 12.2.
The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.
The data bus between the CPU a nd the A/D con verter is 8 bits wide. The uppe r byt e ca n be read
directly from the CPU, however the lower byte shou ld be read via a temporary register. The
temporary register contents are transferred from the ADDR when the upper byte data is read.
When reading the ADDR, read the upper byte before the lower byte, or read in word unit. Reading
the lower bytes alone does not guarantee the contents.
Table 12.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Group 0 (CH2 = 0) Group 1 (CH2 = 1) A/D Data Register to Be Stored the Results
of A/D Conversion
AN0 AN4 ADDRA
AN1 AN5 ADDRB
AN2 AN6 ADDRC
AN3 AN7 ADDRD
Rev. 2.00, 03/04, page 329 of 508
12.3.2 A/D Control/Status Register (ADCSR)
ADCSR controls A/D conversion operations.
Bit Bit Name Initial
Value R/W Description
7 ADF 0 R/(W)* A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
• When A/D conversion ends
• When A/D conversion ends on all specified
channels
[Clearing condition]
• When 0 is written after reading ADF = 1
6 ADIE 0 R/W A/D Interrupt Enable
A/D conversion end interrupt (ADI) request enabled
when 1 is set
5 ADST 0 R/W A/D Start
Clearing this bit to 0 stops A/D conversion, and the A/D
converter enters the wait state.
Setting this bit to 1 starts A/D conversion. In single
mode, this bit is cleared to 0 automatically when
conversion on the specified channel is complete. In
scan mode, conversion continues sequentially on the
specified channels until this bit is cleared to 0 by
software, a reset, or a transition to software standby
mode, hardware standby mode or module stop mode.
4 SCAN 0 R/W Scan Mode
Selects single mode or scan mode as the A/D
conversion operating mode.
0: Single mode
1: Scan mode
3 0 R/W Reserved
The write value should always be 0.
Rev. 2.00, 03/04, page 330 of 508
Bit Bit Name Initial
Value R/W Description
2
1
0
CH2
CH1
CH0
0
0
0
R/W
R/W
R/W
Channel Select 2 to 0
Select analog input channels.
When SCAN = 0 When SCAN = 1
000: AN0 000: AN0
001: AN1 001: AN0 and AN1
010: AN2 010: AN0 to AN2
011: AN3 011: AN0 to AN3
100: AN4 100: AN4
101: AN5 101: AN4 and AN5
110: AN6 110: AN4 to AN6
111: AN7 111: AN4 to AN7
Note: * Only 0 for clearing the flag can be written.
Rev. 2.00, 03/04, page 331 of 508
12.3.3 A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Bit Bit Name Initial
Value R/W Description
7
6
TRGS1
TRGS0
0
0
R/W
R/W
Timer Trigger Select 0 and 1
Enables the start of A/D conversion by a trigger signal.
Only set bits TRGS0 and TRGS1 while conversion is
stopped (ADST = 0).
00: A/D conversion start by software is enabled
01: A/D conversion start by TPU conversion start trigger
is enabled
10: Setting prohibited
11: A/D conversion start by external trigger pin
(ADTRG) is enabled
5, 4 All 1 Reserved
These bits are always read as 1.
3
2
CKS1
CKS0
0
0
R/W
R/W
Clock Select 0 and 1
These bits specify the A/D conversion time. The
conversion time should be changed only when ADST =
0. Specify a setting that gives a value within the range
shown in table 19.7 in section 19, Electrical
Characteristics.
00: Conversion time = 530 states (max.)
01: Conversion time = 266 states (max.)
10: Conversion time = 134 states (max.)
11: Conversion time = 68 states (max.)
1, 0 All 1 Reserved
These bits are always read as 1.
Rev. 2.00, 03/04, page 332 of 508
12.4 Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes; single mode and scan mode. When changing the operating mode or analog input
channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The
ADST bit can be set at the same time as the operating mode or analog input ch annel is changed.
12.4.1 Single Mode
In single mode, A/D conversion is to be performed only once on the specified single channel. The
operations are as follows.
1. A/D conversion is started when the ADST bit is set to 1, according to software or external
trigger input.
2. When A/D conversion is completed, the result is transferred to the corresponding A/D data
register to the channel.
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrupt request is generated.
4. The ADST bit remains set to 1 du ri n g A/D c onversion. When A/D conversion ends, the ADST
bit is automatically cleared to 0 and th e A/D converter enters the wait state.
12.4.2 Scan Mode
In scan mode, A/D conversion is to be performed sequentially on the specified channels (four
channels maximum). The operations are as follows.
1. When the ADST bit is set to 1 by software, TPU or external trigger input, A/D conversion
starts on the first channel in the group (AN0 when CH2 = 0 or AN4 when CH2 = 1).
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
the A/D data register corresponding to each channel.
3. When conversion of all the selected channels is completed, the ADF flag is set to 1. If the
ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends.
Conversion of the first channel in the group starts again.
4. Steps [2] and [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops and the A/D converter enters the wait state.
Rev. 2.00, 03/04, page 333 of 508
12.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold cir cu it. The A/D converter samples the analog
input when th e A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then
starts conversion. Figure 12.2 shows the A/D conversion timing. Table 12.3 shows the A/D
conversion time.
As indicated in figure 12.2, the A/D conversion time (tCONV) includes tD and the input sampling time
(tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total
conversion time therefore varies within the ranges indicated in table 12.3.
In scan mode, the values given in table 12.3 apply to the first conversion time. The values given in
table 12.4 app ly to the second and subsequent conversions. In both cases, set bits CKS1 and CKS0
in ADCR to give an A/D conversion time within the range shown in table 19.7 in section 19,
Electrical Characteristics.
(1)
(2)
t
D
t
SPL
t
CONV
φ
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
t
D
: A/D conversion start delay
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
Figure 12.2 A/D Conversion Timing
Rev. 2.00, 03/04, page 334 of 508
Table 12.3 A/D Conversion Time (Single Mode)
CKS1 = 0 CKS1 = 1
CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1
Item Symbol
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
A/D conversion
start delay
tD 18 33 10 17 6 9 4 5
Input sampling
time
tSPL 127 63 31 15
A/D conversion
time
tCONV 515 530 259 266 131 134 67 68
Note: All values represent the number of states.
Table 12.4 A/D Conversion Time (Scan Mode)
CKS1 CKS0 Conversion Time (State)
0 512 (Fixed) 0
1 256 (Fixed)
0 128 (Fixed) 1
1 64 (Fixed)
Rev. 2.00, 03/04, page 335 of 508
12.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS0 and TRGS1 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A fall i ng edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the bit ADST has been set to 1 by software. Figure 12.3 shows the
timing.
φ
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 12.3 External Trigger Input Timing
12.5 Interrupts
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.
Setting the ADIE bit to 1 en ables ADI interrupt requests while the bit ADF in ADCSR is set to 1
after A/D conversion is completed.
Table 12.5 A/D Converter Interrupt Source
Name Interrupt Source Interrupt Source Flag
ADI A/D conversion completed ADF
Rev. 2.00, 03/04, page 336 of 508
12.6 A/D Conversion Precision Definitions
This LSI's A/D conversion precision definitions are given below.
• Resolution
The number of A/D converter digital output codes
• Quantization erro r
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 12.4).
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value B'0000000000 (H'000) to
B'0000000001 (H' 0 01 ) (see figu re 1 2. 5).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see
figure 12.5).
• Nonlinearity error
The error with respect to the ideal A/D conversion characteristic between zero voltage and full-
scale voltage. Does not include offset error, full-scale error, or quantization error (see figure
12.5).
• Absolute precision
The deviation between the digital value and the analog input value. Includes offset error, full-
scale error, quantization error, and nonlinearity error.
Rev. 2.00, 03/04, page 337 of 508
111
110
101
100
011
010
001
000
1
1024
2
1024
1022
1024
1023
1024
FS
Quantization error
Digital output
Ideal A/D conversion
characteristic
Analog
input voltage
Figure 12.4 A/D Conversion Precision Definitions
FS
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Analog
input voltage
Offset error
Actual A/D conversion
characteristic
Full-scale error
Figure 12.5 A/D Conversion Precision Definitions
Rev. 2.00, 03/04, page 338 of 508
12.7 Usage Notes
12.7.1 Module Stop Mode Setting
Operation of the A/D converter can be disabled or enabled using the module stop control register.
The initial setting is for operation of the A/D converter to be halted. Register access is enabled by
clearing module stop mode. For details, see section 19, Power-Down Modes.
12.7.2 Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion precision is guaranteed for an input signal
for which the signal source impedance is 10 kΩ or less. This specification is provided to enable
the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling
time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it may not
be possible to guarantee A/D conversio n pre c is i on. Ho wev er, fo r A/ D con version in single mode
with a large capacitance provided externally, the input load will essentially comprise only the
internal input resistance of 10 kΩ, and the signal source impedance is ignored. However, as a low-
pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a
large differential coefficient (e.g., 5 mV/µs or greater) (see figure 12.6). When converting a high-
speed analog signal, a low-impedance buffer should be inserted.
12.7.3 Influences on Absolute Precision
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute precision. Be sure to make the connection to an electrically stable GND such as
AVss.
Care is also required to insure that filter circuits do not communicate with digital signals on the
mounting board (i .e. acting as antennas).
20 pF
10 k
Cin =
15 pF
Sensor output
impedance
to 5 k
This LSI
Low-pass
filter
C to 0.1 F
Sensor input
A/D converter
equivalent circuit
Figure 12.6 Example of Analog Input Circuit
Rev. 2.00, 03/04, page 339 of 508
12.7.4 Range of Analog Power Supply and Other Pin Settings
If the conditions below are not met, the reliability of the device may be adversely affected.
• Analog input voltage range
The voltage applied to analog input pin ANn during A/D conversion should be in the range
AVss ≤ ANn ≤ AVcc.
• Relationship between AVcc, AVss and Vcc, Vss
Set AVss = Vss as the relationship between AVss and Vss. If the A/D converter is not used, set
AVcc = Vcc as the relationship between AVcc and Vcc, and the AVcc and AVss pins must not
be left open.
12.7.5 Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,
and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close
proximity should be avoided as far as possible. Failure to do so may result in incorrect operation
of the analog cir c uitry due to inductance, adversely affecting A/D conversion values. Also, digital
circuitry must be isolated from the analog input signals (AN0 to AN7), and analog power supply
(AVcc) by the analog ground (AVss). Also , the analog ground (AVss) should be connected at one
point to a stable digital ground (Vss) on the board.
12.7.6 Notes on Noise Countermeasures
A protection circuit should be connected in order to prevent damage due to abnormal voltage, such
as an excessive surge at the analog input pins (AN0 to AN7), between AVcc and AVss, as shown
in figure 12.7. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to
AN0 to AN7 must be connected to AVss.
If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN7) are
aver aged, and so an er ror may ar ise. Also, when A/D conversion is performed frequently, as in
scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit
in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in
the analog input pin voltage. Careful consideration is therefore required when deciding circuit
constants.
Rev. 2.00, 03/04, page 340 of 508
AVCC
*
1
AN0 to AN7
AVSS
R
in
*
2
100
0.1 F
0.01 F10 F
Notes: Values are reference values.
1.
2. R
in
: Input impedance
Figure 12.7 Example of Anal o g Inp ut Protection Circui t
Table 12.6 Anal o g Pin Specifications
Item Min. Max. Unit
Analog input capacitance 20 pF
Permissible signal source impedance 5 kΩ
20 pF
AN0 to AN7
Note: Values are reference values.
10 k
To A/D converter
Figure 12.8 Analog Input Pin Equivalent Circuit
Rev. 2.00, 03/04, page 341 of 508
Section 13 Motor Control PWM Timer (PWM)
The H8S/2282 has an o n-c hi p mot o r c o nt rol PWM (p ul se w i dth m o dul at o r ) wi t h a maxim um
capability of 16 pulse outputs.
13.1 Features
• Maximum of 16 pulse output s
Two 10-bit PWM channels, each with eight outputs.
Each channe l is provided with a 10-bit counter (PWCNT) and cycle register (PWCYR).
Duty and output polarity can be set for each output.
• Buffered duty registers
Duty registers (PWDTR ) are pr ovided with buffer registers (PWBFR), with data
transferred automatically every cycle.
Channel 1 has four duty regi sters and four buffer regist ers.
Channel 2 has eight dut y registers and four buffer regi sters.
• 0% to 100% duty
• Five operating clocks
There is a choice of five operating clocks (φ, φ/2, φ/4, φ/8, φ/16).
• On-chip output dri ver
• High-speed access is possible via a 16-bit bus interface
• Two interrupt sources
An interrupt can be requested independently for each channel by a cycle register compare
match.
• Module stop mode can be set
Figure 13.1 show s a block diagram of PWM cha nnel 1 a nd fi gu re 13 .2 shows a block diag ram of
PWM channel 2.
MPWM000A_000020020200
Rev. 2.00, 03/04, page 342 of 508
PWCNT_1
PWCYR_1
PWDTR_1A
12 9 0
PWPR_1
P/N
P/N
PWM1A
PWM1B
PWBFR_1A
12 9 0
PWDTR_1C P/N
P/N
PWM1C
PWM1D
PWBFR_1C
PWDTR_1E P/N
P/N
PWM1E
PWM1F
PWBFR_1E
PWDTR_1G P/N
P/N
PWM1G
PWM1H
PWBFR_1G
PWCR_1 PWOCR_1
Compare
match
Interrupt
request
Internal
data bus
Bus interface
Port
control
[Legend]
PWCR_1: PWM control register_1
PWOCR_1: PWM output control register_1
PWPR_1: PWM polarity register_1
PWCNT_1: PWM counter_1
PWCYR_1: PWM cycle register_1
PWDTR_1A, 1C, 1E, 1G: PWM duty register_1A, 1C, 1E, 1G
PWBFR_1A, 1C, 1E, 1G: PWM buffer register_1A, 1C, 1E, 1G
φ, φ/2, φ/4, φ/8, φ/16
Figure 13.1 Block Diagram of PWM Channel 1
Rev. 2.00, 03/04, page 343 of 508
PWBFR_2A
12 9 0
PWBFR_2B
PWBFR_2C
PWBFR_2D
PWCNT_2
PWCYR_2
PWOCR_2
PWPR_2
PWDTR_2A
PWDTR_2B
PWDTR_2C
PWDTR_2D
PWDTR_2E
PWDTR_2F
PWDTR_2G
PWDTR_2H
P/N
PWCR_2
P/N
P/N
P/N
P/N
P/N
P/N
P/N
PWM2A
PWM2B
PWM2C
PWM2D
PWM2E
PWM2F
PWM2G
PWM2H
9 0
Compare match
φ, φ/2, φ/4, φ/8, φ/16
[Legend]
PWCR_2: PWM control register_2
PWOCR_2: PWM output control register_2
PWPR_2: PWM polarity register_2
PWCNT_2: PWM counter_2
PWCYR_2: PWM cycle register_2
PWDTR_2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H: PWM duty register_2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H
PWBFR_2A, 2B, 2C, 2D: PWM buffer register_2A, 2B, 2C, 2D
Internal
data bus
Interrupt
request
Bus interface
Port
control
Figure 13.2 Block Diagram of PWM Channel 2
Rev. 2.00, 03/04, page 344 of 508
13.2 Input/Output Pins
Table 13.1 shows the PWM pin configuration.
Table 13.1 Pin Configuration
Name Abbrev. I/O Function
PWM output pin 1A PWM1A Output Channel 1A PWM output
PWM output pin 1B PWM1B Output Channel 1B PWM output
PWM output pin 1C PWM1C Output Channel 1C PWM output
PWM output pin 1D PWM1D Output Channel 1D PWM output
PWM output pin 1E PWM1E Output Channel 1E PWM output
PWM output pin 1F PWM1F Output Channel 1F PWM output
PWM output pin 1G PWM1G Output Channel 1G PWM output
PWM output pin 1H PWM1H Output Channel 1H PWM output
PWM output pin 2A PWM2A Output Channel 2A PWM output
PWM output pin 2B PWM2B Output Channel 2B PWM output
PWM output pin 2C PWM2C Output Channel 2C PWM output
PWM output pin 2D PWM2D Output Channel 2D PWM output
PWM output pin 2E PWM2E Output Channel 2E PWM output
PWM output pin 2F PWM2F Output Channel 2F PWM output
PWM output pin 2G PWM2G Output Channel 2G PWM output
PWM output pin 2H PWM2H Output Channel 2H PWM output
13.3 Register Descriptions
The PWM has the following registers. For details on module stop control registers, see section
19.1.3, Module Stop Control Registers A to D (MSTPCRA to MSTPCRD).
• PWM control register_1, 2 (PWCR_1, PWCR_2)
• PWM output control regi st er _ 1, 2 (P WOCR_1, PWOCR_ 2 )
• PWM polarity register_1, 2 (PWPR_1, PWPR_2)
• PWM counter_1, 2 (PWCNT_1, PWCNT_2)
• PWM cycle register_1,2 (PWCYR_1, PWCYR_2)
• PWM duty register_1A, 1C, 1E, 1G (PWDTR_1A, PWDTR_1C, PWDTR_1E, PWDTR_1G)
• PWM buffer register_1 A, 1C, 1E, 1G (PWBFR _1 A, P WB F R _1C , P WB F R _1E, PWBFR_1G)
• PWM duty register_2A to 2H (PWDTR_2A to PWDTRv2H)
• PWM buffer register_2A to 2D (PWBFR_2A to PWBFR_2 D)
Rev. 2.00, 03/04, page 345 of 508
13.3.1 PWM Control Register_1, 2 (PWCR_1, PWCR_2)
PWCR performs interrupt control, starting/stopping of the counter, and counter clock selection. It
also contains a flag that indicates a compare match with PWCYR.
Bit Bit Name
Initial
Value R/W Reserved
7, 6 All 1 Reserved
Bits 7 and 6 are reserved; they are always read as 1
and cannot be modified.
5 IE 0 R/W Interrupt Enable
Bit 5 enables or disables an interrupt request in the
event of a compare match with PWCYR.
0: Interrupt disabled
1: Interrupt enabled
4 CMF 0 R/(W)* Compare Match Flag
Bit 4 indicates the occurrence of a compare match with
PWCYR.
[Setting condition]
When PWCNT = PWCYR
[Clearing condition]
When 0 is written to CMF after reading CMF = 1
3 CST 0 R/W Counter Start
Bit 3 selects starting or stopping of PWCNT.
0: PWCNT is stopped
1: PWCNT is started
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select
Bits 2 to 0 select the operating clock for PWCNT.
000: Counts on φ/1
001: Counts on φ/2
010: Counts on φ/4
011: Counts on φ/8
1xx: Counts on φ/16
[Legend]
x: Don't care
Note: * Only 0 can be written to clear the flag.
Rev. 2.00, 03/04, page 346 of 508
13.3.2 PWM Output Control Register_1, 2 (PWOCR_1, PWOCR_2)
PWOCR enable s or disabl es PWM o ut p ut . PW OC R _ 1 co nt rols outputs PWM1H to PWM 1 A, and
PWOCR_2 controls outputs PWM2H to PWM2A.
• PWOCR_1
Bit Bit Name
Initial
Value R/W Reserved
7
6
5
4
3
2
1
0
OE1H
OE1G
OE1F
OE1E
OE1D
OE1C
OE1B
OE1A
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output Enable
Each of these bits enables or disables the
corresponding PWM1H to PWM1A output.
0: PWM output is disabled.
1: PWM output is enabled.
• PWOCR_2
Bit Bit Name
Initial
Value R/W Reserved
7
6
5
4
3
2
1
0
OE2H
OE2G
OE2F
OE2E
OE2D
OE2C
OE2B
OE2A
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output Enable
Each of these bits enables or disables the
corresponding PWM2H to PWM2A output.
0: PWM output is disabled.
1: PWM output is enabled.
Rev. 2.00, 03/04, page 347 of 508
13.3.3 PWM Polarity Register_1, 2 (PWPR_1, PWPR_2)
PWPR selects the PWM output polarity. PWPR_1 controls outputs PWM1H to PWM1A, and
PWPR_2 contr ol s outputs PWM2H to PWM 2A .
• PWPR_1
Bit Bit Name
Initial
Value R/W Reserved
7
6
5
4
3
2
1
0
OPS1H
OPS1G
OPS1F
OPS1E
OPS1D
OPS1C
OPS1B
OPS1A
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Polarity Select
Each of these bits selects the output polarity to PWM1H
to PWM1A.
0: PWM direct output.
1: PWM inverse output.
• PWPR_2
Bit Bit Name
Initial
Value R/W Reserved
7
6
5
4
3
2
1
0
OPS2H
OPS2G
OPS2F
OPS2E
OPS2D
OPS2C
OPS2B
OPS2A
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Polarity Select
Each of these bits selects the output polarity to PWM2H
to PWM2A.
0: PWM direct output.
1: PWM inverse output.
13.3.4 PWM Counter_1, 2 (PW CN T _1 , PWCNT_2)
PWCNT is a 10-bit up-counter incremented by the input clock. The input clock is selected by
clock select bits CKS2 to CKS0 in PWCR.
PWCNT_1 and PWCNT_2 are used as the time base for channel 1 and channel 2 respectively.
PWCNT is initialized when the CST in PWCR is cleared to 0, and also upon reset and in standby
mode, watch mode, subactive mode, subsleep mode, and module stop mode. PWCNT is initialized
to H'FC00.
Rev. 2.00, 03/04, page 348 of 508
13.3.5 PWM Cycle Reg ister_1, 2 (PWCYR_1, PWCYR_2 )
PWCYR is a 16-bit read/write register that sets th e PWM conversion cycle. When a PWCYR
compare match occurs, PWCNT is cleared and data is transferred from the buffer register
(PWBFR) to the duty register (PWDTR). PWCYR_1 and PWCYR_2 are used for conversion
cycle setting for the channel 1 and channel 2 respectively.
PWCYR should be written to only while PWCNT is stopped. A value of H'FC00 must not be set.
PWCYR is initialized to H'FFFF upon reset. Figure 13.3 shows the compare match of the cy cle
registers.
01 01
N
N–1
PWCNT
(lower 10 bits)
PWCYR
(lower 10 bits)
N–2
Compare matchCompare match
Figure 13.3 Cycle Register Compare Match
13.3.6 PWM Duty Register_1A, 1C, 1E, 1G (PWDTR_1A, PWDTR_1C, PWDTR_1E,
PWDTR_1G)
There a re four PWDTR_1 registers. The PWM output is determined by the value of the OTS bit,
and PWDTR_1A is used for outputs PWM1A and PWM1B, PWDTR_1C for outputs PWM1C
and PWM1D, PWDTR_1E for outputs PWM1E and PWM1F, and PWDTR_1G for outputs
PWM1G and PWM1H.
The PWDTR_1 registers cannot be read from or written to directly. When a PWCYR_1 compare
match occurs, data is transferred from buffer register 1 (PWBFR_1) to PWDTR_1.
The PWDTR_1 registers are initialized when the CST bit in PWCR_1 is cleared to 0, and also
upon reset and in standby mode and module stop mode.
Rev. 2.00, 03/04, page 349 of 508
Bit Bit Name
Initial
Value R/W Reserved
15 to 13 All 1 Reserved
These bits cannot be read from or written to.
12 OTS 0 Output Terminal Select
Bit 12 indicates the value in bit 12 of PWBFR_1 sent by
a PWCYR_1 compare match, and selects the pin used
for PWM output. Unselected pins output a low level (or
a high level when the corresponding bit in PWPR_1 is
set to 1).
PWDTR_1A register
0: PWM1A output selected
1: PWM1B output selected
PWDTR_1C
0: PWM1C output selected
1: PWM1D output selected
PWDTR_1E
0: PWM1E output selected
1: PWM1F output selected
PWDTR_1G
0: PWM1G output selected
1: PWM1H output selected
11, 10 All 1 Reserved
These bits are always read as 1 and cannot be
modified.
9
8
7
6
5
4
3
2
1
0
DT9
DT8
DT7
DT6
DT5
DT4
DT3
DT2
DT1
DT0
0
0
0
0
0
0
0
0
0
0
Duty
Bits 9 to 0 indicate the data in bits 9 to 0 of PWBFR_1
sent by a PWCYR_1 compare match, and specify the
PWM output duty. A high level (or a low level when the
corresponding bit in PWPR_1 is set to 1) is output from
the time PWCNT_1 is cleared by a PWCYR_1 compare
match until a PWDTR_1 compare match occurs. When
all of the bits are 0, there is no high-level (or low-level
when the corresponding bit in PWPR_1 is set to 1)
output period.
Rev. 2.00, 03/04, page 350 of 508
PWCNT_1
(lower 10 bits)
PWCYR_1
(lower 10 bits)
PWDTR_1
(lower 10 bits)
PWM output on
selected pin
PWM output on
unselected pin
Compare match
01
N
M
M–2 M–1 M N–1 0
Figure 13.4 Duty Register Comp are M a tch (OP S = 0 in PWPR _1 )
0 1 N–1 0
N
M
N–2
PWCNT_1
(lower 10 bits)
PWCYR_1
(lower 10 bits)
PWDTR_1
(lower 10 bits)
PWM output
(M = 0)
PWM output
(0 < M < N)
PWM output
(N ≤ M)
Figure 13.5 Differences in PWM Output According to Duty Register Set Value
(OPS = 0 in PWPR_1)
Rev. 2.00, 03/04, page 351 of 508
13.3.7 PWM Buffer Register_1 A, 1C , 1E , 1G (P WBFR_1A, PWBFR_1 C, PWB F R _1E,
PWBFR_1G)
Ther e are four PWBFR_1 r egisters. When a PW CYR_1 compare match occurs, data is transferred
from PWBFR_ 1A to PW DTR_1A, from PWBF R _1C to PWDTR_1C, fr om PWBFR_1E to
PWDTR_1E, and from PWBFR_1G to PWDTR_1G.
Bit Bit Name
Initial
Value R/W Reserved
15 to 13 All 1 Reserved
These bits are always read as 1 and cannot be
modified.
12 OTS 0 R/W Output Terminal Select
Bit 12 is the data sent to bit 12 of PWDTR_1.
11, 10 All 1 Reserved
These bits are always read as 1 and cannot be
modified.
9
8
7
6
5
4
3
2
1
0
DT9
DT8
DT7
DT6
DT5
DT4
DT3
DT2
DT1
DT0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Duty
Bits 9 to 0 comprise the data sent to bits 9 to 0 in
PWDTR_1.
Rev. 2.00, 03/04, page 352 of 508
13.3.8 PWM Duty Register_2A to 2H (PWDTR_ 2A to PW DTR_2H)
There are eight PWDTR_2 registers. PWDTR_2A is used for output PWM2A, PWDTR_2B for
output PWM 2 B , PWDTR_2C for out p ut PWM 2C , PWDTR_2D for o ut put PWM2D, PWDTR_2E
for output PW M 2E, PW DTR_2F for output PWM2F, PWDTR_2 G fo r o ut p ut PWM 2 G , and
PWDTR_2H for output PWM2H.
The PWDTR_2 registers cannot be read from or written to directly. When a PWCYR_2 compare
match occurs, data is transferred from buffer register 2 (PWBFR_2) to PWDTR_2.
The PWDTR_2 registers are initialized when the CST bit in PWCR_2 is cleared to 0, and also
upon reset and in standby mode and module stop mode.
Bit Bit Name
Initial
Value R/W Reserved
15 to 10 All 1 Reserved
These bits cannot be read from or written to.
9
8
7
6
5
4
3
2
1
0
DT9
DT8
DT7
DT6
DT5
DT4
DT3
DT2
DT1
DT0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Duty
Bits 9 to 0 indicate the data in bits 9 to 0 of PWBFR_2
sent by a PWCYR_2 compare match, and specify the
PWM output duty. A high level (or a low level when the
corresponding bit in PWPR_2 is set to 1) is output from
the time PWCNT_2 is cleared by a PWCYR_2 compare
match until a PWDTR_2 compare match occurs. When
all the bits are 0, there is no high-level (or low-level
when the corresponding bit in PWPR_2 is set to 1)
output period.
PWCNT_2
(lower 10 bits)
PWCYR_2
(lower 10 bits)
PWDTR_2
(lower 10 bits)
PWM output
Compare match
01
N
M
M–2 M–1 M N–1 0
Figure 13.6 Duty Register Comp are M a tch (OP S = 0 in PWPR _2 )
Rev. 2.00, 03/04, page 353 of 508
0 1 N–1 0
N
M
N–2
PWCNT_2
(lower 10 bits)
PWCYR_2
(lower 10 bits)
PWDTR_2
(lower 10 bits)
PWM output
(M = 0)
PWM output
(0 < M < N)
PWM output
(N ≤ M)
Figure 13.7 Differences in PWM Output According to Duty Register Set Value
(OPS = 0 in PWPR_2)
13.3.9 PWM Buffer Register_2A to 2D (PWBFR2_A to PWBFR_2D)
There are four PWBFR_2 registers. The transfer destination is determined by the value of th e TDS
bit, and when a PWCYR_2 compare match occurs, data is transferred from PWBFR_2A to
PWDTR_2A or PWDTR_2E, from PWBFR_2B to PWDTR_2B or PWDTR_2F, from
PWBFR_2C to PWDTR_2C or PWDTR_2G, and from PWBFR_2D to PWDTR_2D or
PWDTR_2H.
Rev. 2.00, 03/04, page 354 of 508
Bit Bit Name
Initial
Value R/W Reserved
15 to 13 All 1 Reserved
These bits are always read as 1 and cannot be
modified.
12 TDS 0 R/W Transfer Destination Select
Bit 12 selects the PWDTR_2 register to which data is to
be transferred.
PWBFR_2A
0: PWDTR_2A selected
1: PWDTR_2E selected
PWBFR_2B
0: PWDTR_2B selected
1: PWDTR_2F selected
PWBFR_2C
0: PWDTR_2C selected
1: PWDTR_2G selected
PWBFR_2D
0: PWDTR_2D selected
1: PWDTR_2H selected
11, 10 All 1 Reserved
These bits are always read as 1 and cannot be
modified.
9
8
7
6
5
4
3
2
1
0
DT9
DT8
DT7
DT6
DT5
DT4
DT3
DT2
DT1
DT0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Duty
Bits 9 to 0 comprise the data sent to bits 9 to 0 in
PWDTR_2.
Rev. 2.00, 03/04, page 355 of 508
13.4 Bus Master Interface
13.4.1 16-Bit Data Re gi sters
PWCYR_1, PWCYR_2, PWBFR_1A, PWBFR_1C, PWBFR_1E, PWBFR_1G, and PWBFR_2A
to PWBFR_2D are 16-bit registers. These registers are linked to the bus master by a 16-bit data
bus, and can be read or written in 16-bit units. They cannot be read or written by 8-bit access; 16-
bit access must always be used.
H
L
PWCYR_1
Bus
master
Internal data bus
Bus
interface
Module
data bus
Figure 13.8 16-Bit Register Access Operation (Bus Master ↔ PWCYR_1 (16 Bits))
13.4.2 8-Bit Data Registers
PWCR_1, PWCR_2, PWOCR_1, PWOCR_2, and PWPR_1, PWPR_2 are 8-bit registers that can
be read and written to in 8-bit units. These registers are linked to the bus master by a 16-bit da ta
bus, and can be read or written by 16-bit access; in this case, the lower 8 bits are read as an
undefine d val u e.
H
L
PWCR_1
Bus
master
Internal data bus
Bus
interface
Module
data bus
Figure 13.9 8-Bit Register Access Operation (Bus Master ↔ PWCR_1 (Upper 8 Bits))
Rev. 2.00, 03/04, page 356 of 508
13.5 Operation
13.5.1 PWM Channel 1 Operation
PWM waveforms are outp ut f ro m pi ns PW M 1A to PWM1H as shown in figure 13. 10 .
Initial Settings: Set the PWM output polarity in PWPR_1; enable the PWM1A to PWM1H pins
for PWM output with PWOCR_1; select the clock to be input to PWCNT_1 with bits CKS2 to
CKS0 in PWCR_1; set the PWM conversion cycle in PWCYR_1; and set the first frame of data in
PWBFR_1A, PWBFR_1C, PWBFR_1E, and PWBFR_1G.
Activation: When the CST bit in PWCR_1 is set to 1, a compare match between PWCNT_1 and
PWCYR_1 is generated. Data is transferred from PW BFR_1A to PWDTR_1A, from PWBFR_1C
to PWDTR_1C, from PWBFR_1E to PWDTR_1E, and from PWBFR_1G to PWDTR_1G.
PWCNT_1 starts counting up. At the same time the CMF bit in PWCR_1 is set, so that, if the IE
bit in PWCR_1 has been set, an interrupt can be requested.
Waveform Output: The PWM outputs selected by the OTS bits in PWDTR_1A, PWDTR_1C,
PWDTR_1E, and PWDTR_1G go high when a compare match occurs between PWCNT_1 and
PWCYR_1. The PWM outputs not selected are low. When a compare match occurs between
PWCNT_1 and PWDTR_1A, PWDTR_1C, PWDTR_1E, PWDTR_1G, the corresponding PWM
output goes low. If the corresponding bit in PWPR_1 is set to 1, the output is inverted.
Next Frame: When a compare match occurs between PWCNT_1 and PWCYR_1, data is
transferred from PWBFR_1A to PWDTR_1A, from PWBFR_1C to PWDTR_1C, from
PWBFR_1E to PWDTR_1E, and from PWBFR_1G to PWDTR_1G. PWCNT_1 is reset and starts
counting up from H'000. The CMF bit in PWCR_1 is set, and if the IE bit in PWCR_1 has been
set, an interrupt can be requested.
Stopping: When the CST bit in PWCR_1 is cleared to 0, PWCNT_1 is reset and stops. All PWM
outputs go low (or high if the corresponding bit in PWPR_1 is set to 1).
Rev. 2.00, 03/04, page 357 of 508
PWBFR_1A
PWCYR_1
PWM1A
PWDTR_1A
PWM1B
OTS (PWDTR_1A) = 1OTS (PWDTR_1A) = 0OTS (PWDTR_1A) = 1OTS (PWDTR_1A) = 0
Figure 13.10 PWM Channel 1 Operation
13.5.2 PWM Channel 2 Operation
PWM waveforms are outp ut f ro m pi ns PW M 2A to PWM2H as shown in figure 13. 11 .
Initial Settings: Set the PWM output polarity in PWPR_2; enable the PWM2A to PWM2H pins
for PWM output with PWOCR_2; select the clock to be input to PWCNT_2 with bits CKS2 to
CKS0 in PWCR_2; set the PWM conversion cycle in PWCYR_2; and set the first frame of data in
PWBFR_2A, PWBFR_2B, PWBFR_2C, and PWBFR_2D.
Activation: When the CST bit in PWCR_2 is set to 1, a compare match between PWCNT_2 and
PWCYR_2 is generated. Data is transferred from PWBFR_2A to PWDTR_2A or PWDTR_2E,
from PWBFR_2B to PWDTR_2B or PWDTR_2F, from PWBFR_2C to PWDTR_2C or
PWDTR_2G, and from PWBFR_2D to PWDTR_2D or PWDTR_2H, according to the value of
the TDS bit. PWCNT_2 starts counting up. At the same time the CMF bit in PWCR_2 is set, so
that, if the IE bit in PWCR_2 has been set, an interrupt can be requested.
Waveform Output: The PWM outputs go high when a compare match occurs between
PWCNT_2 and PWCYR_2. When a compare match occurs between PWCNT_2 and PWDTR_2A
to PWDTR_2H, the corresponding PWM output goes low. If the corresponding bit in PWPR_2 is
set to 1, the output is inverted.
Next Frame: When a compare match occurs between PWCNT_2 and PWCYR_2 data is
transferred from PWBFR_2A to PWDTR_2A or PW DTR_2E, from PWBFR_2B to PWDT R_2B
or PWDTR_2F, from PWBFR_2C to PWDTR_2C or PWDTR_2G, and from PWBFR_2D to
PWDTR_2D or PWDTR_2H, according to the value of the TDS bit. PWCNT_2 is reset and starts
counting up from H'000. The CMF bit in PWCR_2 is set, and if the IE bit in PWCR_2 has been
set, an interrupt can be requested.
Rev. 2.00, 03/04, page 358 of 508
Stopping: When the CST bit in PWCR_2 is cleared to 0, PWCNT_2 is reset and stops .
PWDTR_2A to PWDTR_2H are reset. All PWM outputs go low (or high if the corresponding bit
in PWPR_2 is set to 1).
TDS (PWBFR
_
2A) = 0 TDS (PWBFR
_
2A) = 1 TDS (PWBFR
_
2A) = 0
PWBFR_2A
PWCYR_2
PWM2A
PWDTR_2A
PWM2B
PWDTR_2E
Figure 13.11 PWM Channel 2 Operation
13.6 Interrupts
If the IE bit in PWCR is set to 1 when the CMF flag in PWCR is set to 1 by a compare match
between PWCNT and PWCYR, an interrupt is requested. Table 13.2 shows the PWM interrupt
sources.
Table 13.2 PWM Interrupt Sources
Name Interrupt Source Interrupt Flag
CMI1 PWCYR_1 compare match CMF
CMI2 PWCYR_2 compare match CMF
Rev. 2.00, 03/04, page 359 of 508
13.7 Usage Note
Contention between Buffer Register Write and Compare Match: If a PWBFR write is
performed in the state immediately after a cycle register compare match, the buffer register and
duty register are overwritten . PWM output changed by the cycle register compare match is not
changed in overwrite of the duty register due to contention. This may result in unanticipated duty
output. In the case of channel 2, the duty register used as the transfer destination is selected by the
TDS bit of the buffer regi st er when an overwrit e of the duty register occurs due to contention. This
can also result in an unintended overwrite of the duty register. Buffer register rewriting must be
completed before, exception handling due to a compare match interrupt, or the occurrence of a
cycle register compare match on detection of the rise of the CMF flag in PWCR.
T1 Tw Tw T2
φ
Address
Write signal
PWCNT
(lower 10 bits)
PWBFR
PWDTR
PWM output
CMF
Buffer register address
Compare match
0
MN
MN
Figure 13.12 Contention between Buffer register Write and Compare Match
Rev. 2.00, 03/04, page 360 of 508
Rev. 2.00, 03/04, page 361 of 508
Section 14 LCD Controller/Driver (LCD)
This LSI has an on-chip segment type LCD control circuit, LCD driver, and power supply circuit,
enabling it to directly drive an LCD panel.
14.1 Features
• Display capacity
Duty Cycle Internal Driver
Static 28 SEG
1/3 28 SEG
1/4 28 SEG
• Display LCD RAM capacity
8 bits × 20 bytes (160 bits)
Byte or word access to LCD RAM
• The segment output pins can be use d as port s in gro up s of f ou r.
• Common output pins not used because the duty cycle can be used for common double-
buffering (parallel connection ).
In static mode, parallel connection of COM1 to COM2, and of CO M3 to COM4 can be
used
• Choice of 11 frame frequencies
• A or B waveform selectable by software
• Built-in power supply split-resistance
• Display possible in operating modes other than standby mode and module stop mode
LCDSG01A_000020020200
Rev. 2.00, 03/04, page 362 of 508
Figure 14.1 shows a block diagram of the LCD controller/driver.
φ/8 to φ/1024
φ
SUB
CL2
CL1
SEGn, DO
LPCR
LCR
LCR2
Display timing generator
LCD RAM
20 bytes
Internal data bus
28-bit
shift
register
LCD drive
power supply
Segment
driver
Common
data latch
Common
driver
M
V1
V2
V3
V
SS
COM4
COM1
SEG28
SEG27
SEG26
SEG25
SEG24
SEG1
[Legend]
LPCR: LCD port control register
LCR: LCD control register
LCR2: LCD control register 2
LPV
CC
Figure 14.1 Block Diagram of LCD Controller/Driver
14.2 Input/Output Pins
Table 14.1 shows the LCD controller/driver pin configuration.
Table 14.1 Pin Configuration
Name Abbrev. I/O Function
Segment output
pins
SEG28 to SEG1 Output LCD segment drive pins
All pins are multiplexed as port pins (setting
programmable)
Common output
pins
COM4 to COM1 Output LCD common drive pins
Pins can be used in parallel with static
LCD power supply
pins
V1, V2, V3 Used when a bypass capacitor is connected
externally, and when an external power
supply circuit is used
Rev. 2.00, 03/04, page 363 of 508
14.3 Register Descriptions
The LCD controller/driver has the following register s. For details on module stop control, see
section 19.1.3, Module Stop Control Registers A to D (MSTPCRA to MSTPCRD).
• LCD port control register (LPCR)
• LCD control register (LCR)
• LCD control register 2 (LCR2)
14.3.1 LCD Port Control Register ( LPCR)
LPCR selects the duty cycle, LCD driver, and pin functions.
Bit Bit Name
Initial
Value R/W Description
7
6
DTS1
DTS0
0
0
R/W
R/W
Duty Cycle Select 1 and 0
The combination of DTS1 and DTS0 selects static, 1/3,
or 1/4 duty. For details, see table 14.2.
5 CMX 0 R/W Common Function Select
Specifies whether or not the same waveform is to be
output from multiple pins to increase the common drive
power when all common pins are not used because of
the duty setting. For details, see table 14.2.
4 0 R/W Reserved
This bit should only be written with 0.
3
2
1
0
SGS3
SGS2
SGS1
SGS0
0
0
0
0
R/W
R/W
R/W
R/W
Segment Driver Select 3 to 0
Bits 3 to 0 select the segment drivers to be used. For
details, see table 14.3.
Rev. 2.00, 03/04, page 364 of 508
Table 14.2 Selection of the Duty Cycle and Common Functions
Bit 7:
DTS1 Bit 6:
DTS0 Bit 5:
CMX
Duty Cycle
Common Drivers
Notes
0 0 0 Static COM1 COM4, COM3, and COM2 can be
used as ports
1 COM4 to COM1 COM4, COM3, and COM2 output
the same waveform as COM1
1 X Setting prohibited
1 0 0 1/3 duty COM3 to COM1 COM4 can be used as a port
1 COM4 to COM1 COM4 use is prohibited
1 X 1/4 duty COM4 to COM1
[Legend]
X: Don't care
Table 14.3 Selection of Segment Drivers
Function of Pins SEG28 to SEG1
Bit 3:
SGS3 Bit 2:
SGS2 Bit 1:
SGS1 Bit 0:
SGS0 SEG28 to
SEG21 SEG20 to
SEG17 SEG16 to
SEG13 SEG12 to
SEG9 SEG8 to
SEG5 SEG4 to
SEG1
0 0 0 0 Port Port Port Port Port Port
1 SEG Port Port Port Port Port
1 0 SEG SEG Port Port Port Port
1 SEG SEG SEG Port Port Port
1 0 0 SEG SEG SEG SEG Port Port
1 SEG SEG SEG SEG SEG Port
1 0 SEG SEG SEG SEG SEG SEG
1 Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
1 X X X Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
[Legend]
X: Don't care
Rev. 2.00, 03/04, page 365 of 508
14.3.2 LCD Control Register (LCR)
LCR performs LCD power supply split-resistance connection control and display data control, and
selects the frame frequency.
Bit Bit Name
Initial
Value R/W Description
7 1 Reserved
This bit is always read as 1 and cannot be modified.
6 PSW 0 R/W LCD Power Supply Split-Resistance Connection Control
Bit 6 can be used to disconnect the LCD power supply
split-resistance from VCC when LCD display is not
required in a power-down mode, or when an external
power supply is used. When ACT is 0 or in standby
mode, the LCD power supply split-resistance is
disconnected from VCC regardless of the setting of this
bit.
0: LCD power supply split-resistance is disconnected
from VCC
1: LCD power supply split-resistance is connected to
VCC
5 ACT 0 R/W Display Function Activate
Bit 5 specifies whether or not the LCD controller/driver
is used. Clearing this bit to 0 halts operation of the LCD
controller/driver. The LCD drive power supply ladder
resistance is also turned off, regardless of the setting of
the PSW bit. However, register contents are retained.
0: LCD controller/driver operation halted
1: LCD controller/driver operates
4 DISP 0 R/W Display Data Control
Bit 4 specifies whether the LCD RAM contents are
displayed or blank data is displayed.
0: Blank data is displayed
1: LCD RAM data is displayed
3
2
1
0
CKS3
CKS2
CKS1
CKS0
0
0
0
0
R/W
R/W
R/W
R/W
Frame Frequency Select 3 to 0
Bits 3 to 0 select the operating clock and the frame
frequency. For details, see table 14.4.
Rev. 2.00, 03/04, page 366 of 508
Table 14.4 Selection of the Operating Clock and Frame Frequency
Frame Frequency*1
Bit 3:
CKS3
Bit 2:
CKS2
Bit 1:
CKS1
Bit 0:
CKS0 Operating Clock φ = 20 MHz
0 X 0 0 φSUB 128 Hz*2
1 φSUB/2 64 Hz*2
1 X φSUB/4 32 Hz*2
1 0 0 0 φ/8 4880 Hz
1 φ/16 2440 Hz
1 0 φ/32 1220 Hz
1 φ/64 610 Hz
1 0 0 φ/128 305 Hz
1 φ/256 152.6 Hz
1 0 φ/512 76.3 Hz
1 φ/1024 38.1 Hz
[Legend]
X: Don't care
Notes: 1. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown.
2. This is the frame frequency when φSUB = 32.768 kHz.
14.3.3 LCD Control Regis ter 2 (L CR 2 )
LCR2 controls switching between the A waveform and B waveform.
Bit Bit Name
Initial
Value R/W Description
7 LCDAB 0 R/W A Waveform/B Waveform Switching Control: Bit 7
specifies whether the A waveform or B waveform is
used as the LCD drive waveform.
0: Drive using A waveform
1: Drive using B waveform
6, 5 All 1 Reserved
These bits are always read as 1 and cannot be
modified.
4 to 0 All 0 Reserved
These bits should only be written with 0.
Rev. 2.00, 03/04, page 367 of 508
14.4 Operation
14.4.1 Settings up to LCD Display
To perform LCD display, the hardware and software related items described below must first be
determined.
Hardware Settings
• Panel display
As the impedance of the built-in power supply split-resistance is large, it may not be suitable
for driving a panel. If the display lacks sharpness, see section 14.4.4, Boosting the LCD Drive
Power Supply. When static is selected, the common output drive capability can be increased.
Set the CMX bit in LPCR to 1 when selecting th e duty cycle. With a static cycle, pins COM4
to COM1 output the same waveform.
• LCD drive power supply setting
With the H8S/2282, there are two ways of providing LCD power: by using the on-chip power
supply circuit, or by using an external power supply circuit.
When an external power supply circuit is used for the LCD drive power supply, connect the
external power supply to the V1 pin.
Software Settings
• Du ty selection
Duty cycles can be selected by setting bits DTS1 and DTS0.
• Segment selection
The segment drivers to be used can be selected by setting bits SGS3 to SGS0.
• Frame frequency selection
The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency
should be selected in accordance with the LCD panel specification. For the clock selection
method in watch mode, subactive mode, and subsleep mode, see section 14.4.3, Operation in
Power-Down M odes.
• A or B waveform selection
Either the A or B waveform can be selected as the LCD waveform to be used by means of the
LCDAB bit.
• LCD drive power supply selection
When an ex ternal power supply circuit is used, turn the LCD drive power supply off by
clearing the PSW bit to 0.
Rev. 2.00, 03/04, page 368 of 508
14.4.2 Relationship between LCD RAM and Dis pl ay
The relationship between the LCD RAM and the display segments differs according to the duty
cycle. LCD RAM maps for the different duty cycles are shown in figures 14.2 to 14.4.
After setting the registers required for display, data is written to the part corresponding to the duty
using the same kind of instruction as for ordinary RAM, and display is started automatically when
turned on. Word- or byte-access instructions can be used for RAM setting.
Bit 7
H'FC40
H'FC45
COM4
Bit 6
COM3
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SEG2
H'FC46 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 SEG1
SEG28 SEG28 SEG28 SEG28 SEG27 SEG27 SEG27 SEG27
H'FC53
COM2 COM1 COM4 COM3 COM2 COM1
Display space
Space not used
for display
Figure 14.2 LCD RAM Map (1/4 Duty)
Rev. 2.00, 03/04, page 369 of 508
Bit 7
H'FC40
H'FC45
Bit 6
COM3
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
H'FC46 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1
SEG28 SEG28 SEG28 SEG27 SEG27 SEG27
H'FC53
COM2 COM1 COM3 COM2 COM1
Display space
Space not used
for display
Figure 14.3 LCD RAM Map (1/3 Duty)
Bit 7
COM1
Bit 6
COM1
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
H'FC40
H'FC41
SEG12H'FC42 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5
SEG28H'FC44 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21
H'FC53
COM1 COM1 COM1 COM1 COM1 COM1
Space not used
for display
Space not
used for
display
Display
space
SEG4 SEG3 SEG2 SEG1
Figure 14.4 LCD RAM Map (Static Mode)
Rev. 2.00, 03/04, page 370 of 508
M
COM1
COM2
COM3
COM4
SEGn
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
M
COM1
COM2
COM3
SEGn
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
M
COM1
SEGn
V1
VSS
V1
VSS
1 frame
Data
1 frame
Data
(a) Waveform with 1/4 duty
1 frame
Data
(b) Waveform with 1/3 duty
(c) Waveform with static output
Figure 14.5 Output Waveforms f or Each Duty Cycle (A Waveform)
Rev. 2.00, 03/04, page 371 of 508
M
Data
COM1
SEGn
V1
VSS
V1
VSS
(c) Waveform with static output
(b) Waveform with 1/3 duty
M
Data
COM3
SEGn
COM1
V1
V2
V3
V
SS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
V
SS
V1
V2
V3
VSS
COM2
(a) Waveform with 1/4 duty
M
Data
COM1
COM2
COM3
COM4
SEGn
1 frame 1 frame 1 frame 1 frame
1 frame 1 frame 1 frame 1 frame
1 frame 1 frame 1 frame 1 frame
Figure 14.6 Output Waveforms f or Each Duty Cycle (B Waveform)
Rev. 2.00, 03/04, page 372 of 508
Table 14.5 Output Levels (A Waveform)
Data 0 0 1 1
M 0 1 0 1
Static Common output V1 VSS V1 VSS
Segment output V1 VSS V
SS V1
1/3 duty Common output V3 V2 V1 VSS
Segment output V2 V3 VSS V1
1/4 duty Common output V3 V2 V1 VSS
Segment output V2 V3 VSS V1
14.4.3 Operation in Power-Down Modes
The LCD controller/driver can be operated even in the power-down modes. The operating state of
the LCD controller/driver in the power-down modes is summarized in table 14.6.
Though the read/write to the register for LCD in medium-speed mode is unable, LCD display
operation continues as in high-speed mode. In subactive, subsleep or watch mode, the system
clock switches to the subclock, requiring that φSUB, φSUB/2, or φSUB/4 should be selected. In watch
mode in particular, the φ clock is not supplied unless φSUB, φSUB/2, or φSUB/4 is selected, causing the
display halt. In this case, the DC voltage may be applied to the LCD panel. Thus, make sure to
select φSUB, φSUB/2, or φSUB/4.
In software standby mode, when boosting the LCD drive power supply, the segment output and
common output pins retain their values, and the DC voltage could be applied to the LCD panel.
Therefore, before entering software standby mode, set DDR that is used for segment output and
common output and th e bits SGS3 to SGS0 to 0
Table 14.6 Power-Down Modes and Display Opera tion
Mode
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby Module
Standby
φ Runs Runs Runs Stops Stops Stops Stops*1 Stops*1 Clock
φSUB Runs Runs Runs Runs Runs Runs Stops*1 Stops*1
ACT = 0 Stops Stops Stops Stops Stops Stops Stops*2 Stops Display
operation ACT = 1 Stops Functions Functions Functions*3Functions*3Functions*3 Stops*2 Stops
Notes: 1. The clock supplied to the LCD stops.
2. The LCD drive power supply is turned off regardless of the setting of the PSW bit.
3. Display operation is performed only when φSUB, φSUB/2, or φSUB/4 is selected as the clock.
Rev. 2.00, 03/04, page 373 of 508
14.4.4 Boosting the LCD Drive Power Supply
When a panel is driven, the on-chip power supply capacity may be insufficient. In this case, the
power supply impedance must be reduced. This can be done by connecting bypass capacitors of
around 0.1 to 0.3 µF to pins V1 to V3, as shown in figure 14.7, or by adding a split-resistance
externally.
H8S/2282
LPV
CC
V
SS
V1
V2
V3
VR
R
R
R
R =
C = 0.1 to 0.3 µF
several kΩ to
several MΩ
Figure 14.7 Connection of External Split-Resistance
Rev. 2.00, 03/04, page 374 of 508
Rev. 2.00, 03/04, page 375 of 508
Section 15 RAM
This LSI has 4 kbytes of on-chip high- speed static RAM. The RAM is connected to the CPU by a
16-bit data bus, enabling one-state access by the CPU to both byte data and word data.
The on-chip RAM ca n be enabled or disabled by means of t he RAME bit in the system control
register (SYSCR). For details on SYSCR, see section 3.2.2, System Control Register (SYSCR).
Product Type Name ROM Type RAM
Capacitance RAM Address
HD64F2282 Flash memory version 4 kbytes H'FFE000 to H'FFEFBF,
H'FFFFC0 to H'FFFFFF
HD6432282 4 kbytes H'FFE000 to H'FFEFBF,
H'FFFFC0 to H'FFFFFF
H8S/2282
Group
HD6432281
Mask ROM version
4 kbytes H'FFE000 to H'FFEFBF,
H'FFFFC0 to H'FFFFFF
Rev. 2.00, 03/04, page 376 of 508
Rev. 2.00, 03/04, page 377 of 508
Section 16 Flash Memory (F-ZTAT Version)
The features of the flash memory are summarized below.
The block diagram of the flash memory is shown in fi g ure 1 6. 1.
16.1 Features
• Size: 128 kbytes
• Programming/erase methods
The flash memory is programmed 128 by tes at a time. Erase is performed in single-block
units. The flash memory is configured as follow s: 32 kbytes × 2 blocks, 28 kbyt e s × 1
block, 16 kbytes × 1 block, 8 kb yt es × 2 bl ocks, and 1 kbyte × 4 blocks. To erase the entire
flash memory, each block must be erased in turn.
• Repro gramming capability
The flash memory can be reprogrammed up to 100 times.
• Two on-board program m ing modes
Boot mode
User program mode
Programmer mode
On-board programming/erasing can be done in boot mode, in which the boot program built
into the chip is started to erase or program of the entire flash memory. In normal user
program mode, individual blocks can be erased or programmed.
• Au tomatic bit rate adjustment
For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match
the transfer bit rate of the host.
• Programming/erasing pr ot ect i on
Sets hardware protection, software protection, or error protection against flash memory
programming/erasing.
• Programmer mode
Flash memory can be programmed/ erased in programmer mode usi n g a PR OM
programmer, as well as in on-board programming mode.
ROMF380A_000020020200
Rev. 2.00, 03/04, page 378 of 508
Module bus
Bus interface/controller
Flash memory
(128 kbytes)
Operating
mode
FLMCR2
Internal address bus
Internal data bus (16 bits)
FWE pin
Mode pin
EBR1
EBR2
RAMER
FLPWCR
FLMCR1
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
RAM emulation register
Flash memory power control register
[Legend]
FLMCR1:
FLMCR2:
EBR1:
EBR2:
RAMER:
FLPWCR:
Figure 16.1 Block Diagram of Flash Memory
16.2 Mode Transitions
When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, this
LSI enters an operating mode as shown in figure 16.2. In user mode, flash memory can be read but
not programmed or erased.
The boot, user program and programmer modes are provided as modes to write and erase the flash
memory.
The differences between boot mode and user program mode are shown in table 16.1.
Figure 16.3 shows the operation flow for boot mode and figure 16.4 shows that for user program
mode.
Rev. 2.00, 03/04, page 379 of 508
Boot mode
On-board programming mode
User
program mode
User mode
(on-chip ROM
enabled)
Reset state
Programmer
mode
= 0
FWE = 1 FWE = 0
*1
*1
*2
Notes: Only make a transition between user mode and user program mode when the CPU is
not accessing the flash memory.
1. RAM emulation possible
2. This LSI transits to programmer mode by using the dedicated PROM programmer.
= 0
MD2 = 0,
MD0 = 1,
FWE = 1
= 0
= 0
MD2 = 1,
MD0 = 1,
FWE = 0
MD2 = 1,
MD0 = 1,
FWE = 1
Figure 16.2 Flash Memory State Tr ansitions
Table 16.1 Differences between Boot Mode and User Program Mode
Boot Mode User Program Mode
Total erase Yes Yes
Block erase No Yes
Programming control program* (2) (1) (2) (3)
(1) Erase/erase-verify
(2) Program/program-verify
(3) Emulation
Note: * To be provided by the user, in accordance with the recommended algorithm.
Rev. 2.00, 03/04, page 380 of 508
Flash memory
This LSI
RAM
Host
Programming control
program
SCI
Application program
(old version)
;;
New application
program
Flash memory
This LSI
RAM
Host
SCI
Application program
(old version)
Boot program area
New application
program
Flash memory
This LSI
RAM
Host
SCI
Flash memory
preprogramming
erase
Boot program
New application
program
Flash memory
This LSI
Program execution state
RAM
Host
SCI
New application
program
Boot program
Programming control
program
;;
;;
;
;
;
;
1. Initial state
The old program version or data remains written
in the flash memory. The user should prepare the
programming control program and new
application program beforehand in the host.
2. Programming control program transfer
When boot mode is entered, the boot program in
this LSI (originally incorporated in the chip) is
started and the programming control program in
the host is transferred to RAM via SCI
communication. The boot program required for
flash memory erasing is automatically transferred
to the RAM boot program area.
3. Flash memory initialization
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, total flash
memory erasure is performed, without regard to
blocks.
4. Writing new application program
The programming control program transferred
from the host to RAM is executed, and the new
application program in the host is written into the
flash memory.
Programming control
program
Boot programBoot program
Boot program area Boot program area
Programming control
program
Figure 16.3 Boot Mode
Rev. 2.00, 03/04, page 381 of 508
Flash memory
This LSI
RAM
Host
Programming/
erase control program
SCI
Boot program
New application
program
Flash memory
This LSI
RAM
Host
SCI
New application
program
Flash memory
This LSI
RAM
Host
SCI
Flash memory
erase
Boot program
New application
program
Flash memory
This LSI
Program execution state
RAM
Host
SCI
Boot program
;
;
Boot program
FWE assessment
program
Application program
(old version)
;
;;
New application
program
;;
1. Initial state
The FWE assessment program that confirms that
user program mode has been entered, and the
program that will transfer the programming/erase
control program from flash memory to on-chip
RAM should be written into the flash memory by
the user beforehand. The programming/erase
control program should be prepared in the host
or in the flash memory.
2. Programming/erase control program transfer
When user program mode is entered, user
software confirms this fact, executes transfer
program in the flash memory, and transfers the
programming/erase control program to RAM.
3. Flash memory initialization
The programming/erase program in RAM is
executed, and the flash memory is initialized (to
H'FF). Erasing can be performed in block units,
but not in byte units.
4. Writing new application program
Next, the new application program in the host is
written into the erased flash memory blocks. Do
not write to unerased blocks.
Programming/
erase control program
Programming/
erase control program
Programming/
erase control program
Transfer program
Application program
(old version)
Transfer program
FWE assessment
program
FWE assessment
program
Transfer program
FWE assessment
program
Transfer program
Figure 16.4 User Program Mode
Rev. 2.00, 03/04, page 382 of 508
16.3 Block Configuration
Figure 16.5 shows the bl ock con fi gurat i o n o f 12 8- k byt e flash memory. The thick lines in di cat e
erasing units, the narrow lines indicate programming units and the values are addresses. The flash
memory is divi ded int o 32 k b yt es (2 bl ocks), 28 kbytes (1 bl ock ), 1 6 kb yt es (1 block), 8 k byt es (2
blocks), and 1 kbyte (4 blocks). Erasing is performed in these units. Programming is performed in
128-byte uni ts st art i ng fr om a n a ddress with lower eight bits H'00 or H'80.
EB0
Erase unit
1 kbyte
EB1
Erase unit
1 kbyte
EB2
Erase unit
1 kbyte
EB3
Erase unit
1 kbyte
EB4
Erase unit
28 kbytes
EB5
Erase unit
16 kbytes
EB6
Erase unit
8 kbytes
EB7
Erase unit
8 kbytes
EB8
Erase unit
32 kbytes
EB9
Erase unit
32 kbytes
H'000000 H'000001 H'000002 H'00007F
H'0003FF
H'00047F
H'00087F
H'000C7F
H'00107F
H'007FFF
H'00807F
H'00BFFF
H'0007FF
H'000BFF
H'000FFF
H'01FFFF
H'00C07F
H'00DFFF
H'00E07F
H'00FFFF
H'01007F
H'017FFF
H'01807F
H'000400 H'000401 H'000402
H'000780 H'000781 H'000782
H'000800 H'000801 H'000802
H'000B80 H'000B81 H'000B82
H'000F80 H'000F81 H'000F82
H'007F80 H'007F81 H'007F82
H'00BF80 H'00BF81 H'00BF82
H'00DF80 H'00DF81 H'00DF82
H'00FF80 H'00FF81 H'00FF82
H'017F80 H'017F81 H'017F82
H'01FF80 H'01FF81 H'01FF82
H'000C00 H'000C01 H'000C02
H'001000 H'001001 H'001002
H'008000 H'008001 H'008002
H'00C000 H'00C001 H'00C002
H'00E000 H'00E001 H'00E002
H'010000 H'010001 H'010002
H'018000 H'018001 H'018002
H'000380 H'000381 H'000382
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Figure 16.5 Flash Memory Block Configur ation
Rev. 2.00, 03/04, page 383 of 508
16.4 Input/Output Pins
The flash memory is controlled by means of the pins shown in table 16.2.
Table 16.2 Pin Configuration
Pin Name I/O Function
RES Input Reset
FWE Input Flash program/erase protection by hardware
MD2 Input Sets this LSI's operating mode
MD1 Input Sets this LSI's operating mode
MD0 Input Sets this LSI's operating mode
TxD1 Output Serial transmit data output
RxD1 Input Serial receive data input
16.5 Register Descriptions
The flash memory has the following registers.
• Flash memory control register 1 (FLMCR1)
• Flash memory control register 2 (FLMCR2)
• Erase block register 1 (EBR1 )
• Erase block register 2 (EBR2 )
• RAM emulation register (RAMER)
• Flash memory power control regi st er (FLPWCR)
Rev. 2.00, 03/04, page 384 of 508
16.5.1 Flash Memory Control Reg i ster 1 (FL M CR 1 )
FLMCR1 makes the flash memory change to program mode, program-verify mode, erase mode, or
erase-verify mode. For details on register setting, see section 16.8, Flash Memory
Programming/Erasing.
Bit Bit Name Initial
Value R/W Description
7 FWE R Reflects the input level at the FWE pin. It is cleared to 0
when a low level is input to the FWE pin, and set to 1
when a high level is input.
6 SWE 0 R/W Software Write Enable Bit
When this bit is set to 1, flash memory
programming/erasing is enabled. When this bit is
cleared to 0, other FLMCR1 register bits and all EBR1
bits cannot be set.
5 ESU 0 R/W Erase Setup Bit
When this bit is set to 1, the flash memory changes to
the erase setup state. When it is cleared to 0, the erase
setup state is cancelled.
4 PSU 0 R/W Program Setup Bit
When this bit is set to 1, the flash memory changes to
the program setup state. When it is cleared to 0, the
program setup state is cancelled. Set this bit to 1 before
setting the P1 bit in FLMCR1.
3 EV 0 R/W Erase-Verify
When this bit is set to 1, the flash memory changes to
erase-verify mode. When it is cleared to 0, erase-verify
mode is cancelled.
2 PV 0 R/W Program-Verify
When this bit is set to 1, the flash memory changes to
program-verify mode. When it is cleared to 0, program-
verify mode is cancelled.
1 E 0 R/W Erase
When this bit is set to 1, and while the SWE1 and ESU1
bits are 1, the flash memory changes to erase mode.
When it is cleared to 0, erase mode is cancelled.
0 P 0 R/W Program
When this bit is set to 1, and while the SWE1 and PSU1
bits are 1, the flash memory changes to program mode.
When it is cleared to 0, program mode is cancelled.
Rev. 2.00, 03/04, page 385 of 508
16.5.2 Flash Memory Control Reg i ster 2 (FLM CR 2 )
FLMCR2 displays the state of flash memory programming/erasing. FLMCR2 is a read-only
register, and should not be written to.
Bit Bit Name
Initial
Value R/W Description
7 FLER 0 R Indicates that an error has occurred during an operation
on flash memory (programming or erasing). When
FLER is set to 1, flash memory goes to the error-
protection state.
See section 16.9.3, Error Protection, for details.
6 to 0 All 0 R Reserved
These bits are always read as 0.
16.5.3 Erase Block Register 1 (EBR1)
EBR1 and EBR2 specify the flash memory erase area block. EBR1 and EBR2 initialized to H'00
when the SWE bit in FLMCR1 is 0. Do not set more than one bit in EBR1 and EBR2 together at a
time, as this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0.
• EBR1
Bit Bit Name
Initial
Value R/W Description
7 EB7 0 R/W When this bit is set to 1, 8 kbytes of EB7 (H'00E000 to
H'00FFFF) will be erased.
6 EB6 0 R/W When this bit is set to 1, 8 kbytes of EB6 (H'00C000 to
H'00DFFF) will be erased.
5 EB5 0 R/W When this bit is set to 1, 16 kbytes of EB5 (H'008000 to
H'00BFFF) will be erased.
4 EB4 0 R/W When this bit is set to 1, 28 kbytes of EB4 (H'001000 to
H'007FFF) will be erased.
3 EB3 0 R/W When this bit is set to 1, 1 kbyte of EB3 (H'000C00 to
H'000FFF) will be erased.
2 EB2 0 R/W When this bit is set to 1, 1 kbyte of EB2 (H'000800 to
H'000BFF) will be erased.
1 EB1 0 R/W When this bit is set to 1, 1 kbyte of EB1 (H'000400 to
H'0007FF) will be erased.
0 EB0 0 R/W When this bit is set to 1, 1 kbyte of EB0 (H'000000 to
H'0003FF) will be erased.
Rev. 2.00, 03/04, page 386 of 508
• EBR2
Bit Bit Name
Initial
Value R/W Description
7 to 2 All 0 R/W Reserved
These bits are always read as 0.
1 EB9 0 R/W When this bit is set to 1, 32 kbytes of EB9 (H'018000 to
H'01FFFF) will be erased.
0 EB8 0 R/W When this bit is set to 1, 32 kbytes of EB8 (H'010000 to
H'017FFF) will be erased.
16.5.4 RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped wit h part of RAM when emulat i ng
real-time flash memory programming. RAMER settings should be made in user mode or user
program mode. To ensure correct operation of the emulation function, the ROM for which RAM
emulation is performed should not be accessed immediately after this register has been modified.
Normal execution of an access immediately after register modification is not guaranteed.
Bit Bit Name
Initial
Value R/W Description
7, 6 All 0 R Reserved
These bits are always read as 0.
5, 4 All 0 R/W Reserved
Only 0 should be written to these bits.
3 RAMS 0 R/W RAM Select
Specifies selection or non-selection of flash memory
emulation in RAM. When RAMS = 1, the flash memory
is overlapped with part of RAM, and all flash memory
block are program/erase-protected.
2
1
0
RAM2
RAM1
RAM0
0
0
0
R/W
R/W
R/W
Flash Memory Area Selection
When the RAMS bit is set to 1, one of the following
flash memory areas are selected to overlap the RAM
area of H'FFE000 to H'FFE3FF. The areas correspond
with 1-kbyte erase blocks.
00X: H'000000 to H'0003FF (EB0)
01X: H'000400 to H'0007FF (EB1)
10X: H'000800 to H'000BFF (EB2)
11X: H'000C00 to H'000FFF (EB3)
Note: X Don't care
Rev. 2.00, 03/04, page 387 of 508
16.5.5 Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when this LSI
switches to subactive mode. For details, see section 16.12, Flash Memory and Power-Down
Modes.
Bit Bit Name
Initial
Value R/W Description
7 PDWND 0 R/W Power-Down Disable
When this bit is set to 1, the transition to flash memory
power-down mode is disabled.
6 to 0 All 0 R Reserved
These bits always read 0.
16.6 On-Board Programming Modes
There are two modes for programming/erasing of the flash memory; boot mode, which enables on-
board programming/erasing, and programmer mode, in which programming/erasing is performed
with a PROM programmer. On-board programming/erasing can also be performed in user
program mode. At reset-start in reset mode, this LSI changes to a mode depending on the MD pin
settings and FWE pin setting, as shown in table 16.3. The input level of each pin must be defined
four states before the reset ends.
When changing to boot mod e, th e boot program built into this LSI is initiated. The boot program
transfers the programming control program from the externally-connected host to on-chip RA M
via SCI_1. After erasing the entire flash memory, the programming control program is executed.
This can be used for programming initial values in the on-board state or for a forcible return when
programming/erasing can no longer be done in user program mode. In user program mode,
individual blocks can be erased and programmed by branching to the user program/erase control
program prepared by the user.
Table 16.3 Setting On-Board Programming Modes
MD2 MD0 FWE LSI State after Reset End
1 1 1 User Mode
0 1 1 Boot Mode
Rev. 2.00, 03/04, page 388 of 508
16.6.1 Boot Mode
Table 16.4 shows the boot mode operations between reset end and branching to the programming
control pro gram.
1. When boot mode is used, the flash memory programming control program must be prepared in
the host beforehand. Pr epare a programming control pr ogram in accordance with the
description in section 16.8, Flash Memory Programming/Erasing.
2. SCI_1 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1
stop bit, and no parity.
3. When the boot program is initiated, the chip measures the low-level period of asynchronous
SCI communication data (H '00) transmitted continuously from the host. The chip then
calculates the bit rate of transmission from the host, and adjusts the SCI_1 bit rate to match
that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be
pulled up on the board if necessary. After the reset is complete, it takes approximately 100
states before the chip is ready to measu re the low-level period.
4. After matching the bit rates, the chip tran smits one H'00 byte to the host to indicate the
completion of bit rate adjustment. The host should confirm that this adjustmen t end indication
(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could
not be performed normally, initiate boot mode again by a reset. Depending on the host's
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate
and system clock frequency of this LSI within the ranges listed in table 16.5 .
5. In boot mode, a part of the on-chip RAM area is used by the boo t program. The area H'FFE800
to H'FFEFBF is the area to which the programming control program is transferred from the
host. The boot program area cannot be used until the execution state in boo t mode switches to
the programming control program.
6. Before branching to the programming control program, the chip termin ates transfer operations
by SCI_1 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming contro l program can still use it for transfer of
write data or verify data with the host. The TxD pin is high. The contents of the CPU general
registers are undefined immediately after branching to the programming control program.
These registers must be initialized at the beginning of the programming control program, as the
stack pointer (SP), in particular, is used implicitly in subroutine calls, etc.
7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at
least 20 states, and then setting the mode (MD) pins. Boot mode is also cleared when a WDT
overflow occurs.
8. Do not change the MD pin input levels in boot mode.
9. All interrupts are disabled during programming or erasing of the flash memory.
Rev. 2.00, 03/04, page 389 of 508
Table 16.4 Boot Mode Operation
Item Host Operation Communications Contents LSI Operation
Boot mode
start
Branches to boot program at reset-start.
Processing Contents Processing Contents
Bit rate
adjustment
Continuously transmits data H'00 at
specified bit rate.
H'00, H'00 ...... H'00
H'00
H'55
· Measures low-level period of receive data
H'00.
· Calculates bit rate and sets it in BRR of
SCI_1.
· Transmits data H'00 to host as adjustment
end indication.
Transmits data H'AA to host when data
H'55 is received.
Transmits data H'55 when data H'00
is received error-free.
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data (low-order
byte following high-order byte)
Receives data H'AA.
Transmits 1-byte of programming
control program (repeated for
N times)
Receives data H'AA.
Transfer of
programming
control
program
Flash memory
erase
Boot program initiation
Echobacks the 2-byte data received.
Branches to programming control program
transferred to on-chip RAM and starts
execution.
Echobacks received data to host and also
transfers it to RAM (repeated for N times)
Checks flash memory data, erases all
flash memory blocks in case of written
data existing, and transmits data H'AA to
host. (If erase could not be done,
transmits data H'FF to host and aborts
operation.)
High-order byte and
low-order byte
H'XX
H'AA
Echoback
Echoback
H'FF
H'AA
Boot program
erase error
Table 16.5 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible
Host Bit Rate System Clock Frequency Range of LSI
19,200 bps 20 MHz
9,600 bps 8 to 20 MHz
4,800 bps 4 to 20 MHz
Rev. 2.00, 03/04, page 390 of 508
16.6.2 Programming/Erasing in User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user
program mode by branching to a user program/erase control program. The user must set branching
conditions and provide on-board means of supplying programming data. The flash memory must
contain the user program/erase control program or a program that prov ides the user program/era se
control program from external memory. As the flash memory itself cannot be read during
programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot
mode. Figure 16.6 shows a sample procedure for programming/erasing in user program mode.
Prepare a user program/erase control program in accordance with the description in section 16.8,
Flash Memory Programming/Erasing.
Ye s
No
Program/erase?
Transfer user program/erase control
program to RAM
Reset-start
Branch to user program/erase control
program in RAM
Execute user program/erase control
program (flash memory rewrite)
Branch to flash memory application
program
Branch to flash memory application
program
FWE=high*
Clear FWE
Do not constantly apply a high level to the FWE pin. Only apply a high level to the FWE pin
when programming or erasing the flash memory. To prevent excessive programming or excessive
erasing, while a high level is being applied to the FWE pin, activate the watchdog timer in case of
handling CPU runaways.
Note: *
Figure 16.6 Programming/Erasing Flowchart Example in User Program Mode
Rev. 2.00, 03/04, page 391 of 508
16.7 Flash Memory Emulation in RAM
A setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto
the flash memory area so that data to be written to flash memory can be emulated in RAM in real
time. Emulation can be performed in user mode or user program mode. Figure 16.7 shows an
example of emulation of real-time flash memory programming.
1. Set RAMER to overlap part of RAM onto the area for which real-time programming is
required.
2. Emulation is performed using the overlapping RAM.
3. After the program data has been confirmed, the RAMS bit is cleared, thus releasing the RAM
overlap.
4. The data written in the overlapping RAM is written into the flash memory space (EB0).
Start of emulation program
Set RAMER
Write tuning data to overlap
RAM
Execute application program
Tuning OK?
Clear RAMER
Write to flash memory
emulation block
End of emulation program
No
Ye s
Figure 16.7 Flowchart for Flash Memory Emulation in RAM
Rev. 2.00, 03/04, page 392 of 508
An example in which flash memory block area EB0 is overlapped is shown in figure 16.8.
1. The RAM area to be overlapped is fixed at a 1-kbyte area in the range H'FFE000 to H'FFE3FF.
2. The flash memory area to overlap is selected by RAMER from a 1-kbyte area of the EB0 to
EB3 blocks.
3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM
addresses.
4. When the RAMS bit in RAMER is set to 1, program/erase protection is enabled for all flash
memory blocks (emulation protection). In this state, setting the P or E bit in FLMCR1 to 1
does not cause a transition to program mode or erase mode.
5. A RAM area cannot be erased by execution of software in accordance with the erase
algorithm.
6. Block area EB0 contains the vector table. When performing RAM emulation, the vector table
is needed in the overlap RAM.
H'000000 Flash memory
(EB0)
Flash memory
(EB0)
(EB1)
(EB2)
(EB3)
H'0003FF
H'000400
H'0007FF
H'000800
H'000BFF
H'000C00
H'000FFF
H'FFE000
H'FFE3FF
On-chip RAM
(1 kbyte)
On-chip RAM
(Shadow of
H'FFE000 to
H'FFE3FF)
Flash memory
(EB2)
On-chip RAM
(1 kbyte)
(EB3)
Normal memory map RAM overlap memory map
Figure 16.8 Example of RAM Overlap Operation
Rev. 2.00, 03/04, page 393 of 508
16.8 Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the on-
board program mi ng modes. Depending on the FLMCR1 set t i ng, the fl ash memo r y ope rat e s in one
of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify
mode. The programming control program in boot mode and the user program/erase control
program in user program mode use these operating modes in combination to perform
programming/erasing . Flash memory programming and erasing should be performed in
accordance with the descriptions in section 16.8.1, Program/Program-Verify and section 16.8.2,
Erase/Erase-Verify, respectively.
16.8.1 Program/Program-Verify
When writing dat a or pr o gra ms to the flash memory, the program/pr ogram-verify flo wchart shown
in Figure 16.9 should be followed. Performing programming operations according to this
flowchart will enable data or programs to be written to the flash memory with out subjecting the
chip to voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
programming has alrea d y been performed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128-
byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation and additional programming data computation according to
Figure 16.9.
4. Consecutively transfer 128 bytes of data in byte units from the repr ogramming data area or
additional-programming data area to the flash memory. The prog ram address and 128-byte
data are latched in the flash memory. The lower eight bits of the start addr ess in the flash
memory destination area must be H'00 or H'80.
5. The time during which th e P bit is set to 1 is the programming time. Figure 16.9 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to prev ent overprogramming due to progr am runaway, etc.
An overflow cycle of (γ + z2 + α + β) µs is allowed.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two
bits are B'00. Verify data can be read in longwor ds from the address to which a dummy writ e
was performed.
8. The maximum number of repetitions of the program/program-verify sequence of the same bit
must not exceed (N).
Rev. 2.00, 03/04, page 394 of 508
START
End of programming
Set SWE bit in FLMCR1
Start of programming
Write pulse application subroutine
Wait (x) µs
Apply Write Pulse
End Sub
Set PSU bit in FLMCR1
WDT enable
Disable WDT
Number of Writes n
1
2
3
4
5
6
7
8
9
10
11
12
13
998
999
1000
Note 6: Write Pulse Width
Write Time (z) µs
30
30
30
30
30
30
200
200
200
200
200
200
200
200
200
200
Wait ( ) µs
Set P bit in FLMCR1
Wait (z1) µs, (z2) µs, or (z3) µs
Clear P bit in FLMCR1
Wait ( ) µs
Clear PSU bit in FLMCR1
Wait ( ) µs
n= 1
m= 0
NG
NG
NG NG
OK
OK
OK
Wait ( ) µs
Wait ( ) µs
*
2
*
7
*
7
*
4
*
7
*
7
Start of programming
End of programming
*
5
*
7
*
7
*
7
*
1
Wait ( ) µs
Apply
Write pulse of (z1) s or (z2) s
Sub-Routine-Call
Set PV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Write data =
verify data?
*4
*3
*7
*7
*7
*1
Transfer reprogram data to reprogram data area
Reprogram data computation
*4
Transfer additional-programming data to
additional-programming data area
Additional-programming data computation
Clear PV bit in FLMCR1
Clear SWE bit in FLMCR1
m = 1
Reprogram
See Note 6 for pulse width
m= 0 ?
Increment address
Programming failure
OK
Clear SWE bit in FLMCR1
Wait ( ) µs
NG
OK
6
≥
n?
NG
OK
6
≥
n ?
Wait ( ) µs
n ≥ (N)?
n ← n + 1
Original Data
(D)
Verify Data
(V)
Reprogram Data
(X)
Comments
Programming completed
Still in erased state; no action
Programming incomplete;
reprogram
Note: * Use a 10 µs write pulse for additional programming.
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Additional-programming
data storage area
(128 bytes)
Store 128-byte program data in program
data area and reprogram data area
Apply write Pulse (Additional programming) of (z3) µs
Sub-Routine-Call
128-byte
data verification completed?
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
Reprogram Data Computation Table
Reprogram Data
(X')
Verify Data
(V)
Additional-
Programming Data
(Y)
1
1
1
1
0
1
0
000
1
1
Comments
Additional programming
to be executed
Additional programming
not to be executed
Additional programming
not to be executed
Additional programming
not to be executed
0
1
1
1
0
1
0
100
1
1
Additional-Programming Data Computation Table
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for
which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to
programming once again if the result of the subsequent verify operation is NG.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of
additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
7.
The values of x, y, z1, z2, z3, , , , , , and N are
are shown in section 21.5, Flash Memory Characteristics.
*
*
*
*
*
*
Figure 16.9 Program/Program-Verify Flowchart
Rev. 2.00, 03/04, page 395 of 508
16.8.2 Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 16.10 should b e
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in erase block
register1 (EBR1) and erase block register2 (EBR2). To erase multiple blocks, each block must
be erased in turn.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overerasing due to program ru na way , etc. An
overflow cycle higher than (y + z + α + β) ms is allowed.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two
bits are B'00. Verify data can be read in longwor ds from the address to which a dummy writ e
was performed.
6. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase-
verify sequence as before. The maximum number of repetitions of the erase/erase-verify
sequence must not exceed (N).
16.8.3 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed
or erased, or while the boot program is executing, for the following three reasons:
1. Interrupt d uring programming/ erasi n g may cause a viol at i on of the pr og ramming or erasing
algorithm, with the result that normal operation cannot be assured.
2. If interrupt exception handling starts before the vector address is written or during
programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
carried out.
Rev. 2.00, 03/04, page 396 of 508
START
End of erasing
Set SWE bit in FLMCR1
Wait (x)
µs
n = 1
Enable WDT
Set EBU bit in FLMCR2
Wait (y)
µs
Set E bit in FLMCR1
Wait (z)
ms
Clear E bit in FLMCR1
Wait (
α
)
µs
Clear ESU bit in FLMCR2
Wait (
β
)
µs
Disable WDT
Set EV bit in FLMCR1
Wait (
γ
)
µs
H'FF dummy write to verify address
Wait (
ε
)
µs
Read verify data
Clear EV bit in FLMCR1
Wait (
η
)
µs
Set block start address to verify address
Set EBR1, EBR2
NG
NG
NGNG
OK
OK
*2
*4
*1
*2
*2
*2
*2
*2
*2
*3
*2
*5*2
*2
Verify data = all 1 ?
Clear SWE bit in FLMCR1
Increment
address
Erase failure
Wait ( )
µs
Last address of block ?
OK
End of
erasing of all erase
blocks ?
Clear EV bit in FLMCR1
Wait (
η
)
µs
OK
Wait ( )
µs
n ≥ N ?
Clear SWE bit in FLMCR1
n n + 1
Start of erase
Halt erase
Preprogramming (setting erase block data to all 0) is not necessary.
The values of x, y, z, , , , , , and are shown in section 21.5, Flash Memory Characteristics.
Verify data is read in 16-bit(W) units.
Set only one bit in EBR1 or EBR2. More than one bit cannot be set.
Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
1.
2.
3.
4.
5.
Notes:
Figure 16.10 Erase/Erase-Verify Flowchart
Rev. 2.00, 03/04, page 397 of 508
16.9 Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software
protection, and error protection.
16.9.1 Hardware Protection
Hardware protect i on refe rs to a state in which pr o gram mi n g/ erasi n g o f fla sh memory is forcibly
disabled or aborted because of a transition to reset or standby mode. Flash memory control register
1 (FLMCR1), fl ash memo ry control register 2 (FLMC R 2 ), erase block register 1 (EBR1), and
erase block register2 (EBR2) are initialized. In a reset via the RES pin, the reset state is not
entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of
a reset during operation, hold the RES pin low for the RES pulse width specified in the AC
Characteristics section.
16.9.2 Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P1 or E1
bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting erase block
register 1 (EBR1) or erase block register2 (EBR2), erase protection can be set for individual
blocks. When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks.
Setting the RAMS bit in RAMER also implements protection against programming/erasing of all
flash memory bloc ks.
Rev. 2.00, 03/04, page 398 of 508
16.9.3 Error Protection
In error protection, an error is detected when CPU runa way occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents d amage to the flash memory due to overprogramming or overerasing.
When the follow ing errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory of the relevant address ar ea is read during prog ramming/erasing
(including vector read and instruction fetch)
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, however program mode or er ase
mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be
re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition
can be made to verify mode. Error protection can be cleared only by a power-on reset.
16.10 Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a
socket adapter, just as for a discrete flash memory. Use a PROM programmer that supports the
Renesas Technology's 128-kbyte flash memory on-chip MCU device type (FZTAT128V5A).
Rev. 2.00, 03/04, page 399 of 508
16.11 Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the follow ing states:
• Normal operating mode
The flash memory can be read and written to.
• Power-down mode: Part of the power supply circuitry is halted, and the flash memory can be
read when the LSI is operating on the subclock.
• Standby mode
All flash memory circuits are h alted.
Table 16.6 shows the correspondence between the operating modes of this LSI and the flash
memory. When the flash memory returns to its normal operating state from standby mode, a
period to stabilize the power supply circuits that were stopped is needed. When the flash memory
returns to its normal operating state, bits STS2 to STS0 in SBYCR must be set to provide a wait
time of at least 20 µs, even when the external clock is being used.
Table 16.6 Flash Memory Operating States
LSI Operating State Flash Memory Operating State
High-speed mode
Medium-speed mode
Sleep mode
Normal mode
Subactive mode
Subsleep mode
When PDWND = 0: Power-down mode (read-only)
When PDWND = 1: Normal mode (read-only)
Watch mode
Software standby mode
Hardware standby mode
Standby mode
16.12 Flash Memory and Power-Down Modes
In power-down modes, f lash memory registers (FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and
FLPWCR) cannot be read from or written to.
Rev. 2.00, 03/04, page 400 of 508
Rev. 2.00, 03/04, page 401 of 508
Section 17 Mask ROM
This LSI has 64 or 128 kbytes of on-chip mask ROM. On-chip ROM is connected to the CPU via
a 16-bit data bus. Data in on-chip ROM can always be accessed by one state.
H'000000
H'000002
H'01FFFE
H'000001
H'000003
H'01FFFF
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Figure 17.1 Block Diagram of 128-Kbyte Masked ROM (HD6432282)
H'000000
H'000002
H'00FFFE
H'000001
H'000003
H'00FFFF
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Figure 17.2 Block Diagram of 64-Kbyte Masked ROM (HD6432281)
Rev. 2.00, 03/04, page 402 of 508
17.1 Note on Switching from F-ZTAT Version to Masked ROM Version
The masked ROM version does not have the intern al registers for flash memory control that are
provided in the F-ZTAT version. Table 17.1 lists the registers that are present in the F-ZTAT
version but not in the masked ROM version. If a register listed in table 17.1 is read in the masked
ROM version, an undefined value will be returned. Therefore, if application software developed
on the F-ZTAT version is switched to a masked ROM version product, it must be modified to
ensure that the registers in table 17.1 have no effect.
Table 17.1 Register Present in F-ZTAT Version but Absent in Masked ROM Version
Register Abbreviation Address
Flash memory control register 1 FLMCR1 H'FFA8
Flash memory control register 2 FLMCR2 H'FFA9
Erase block designate register 1 EBR1 H'FFAA
Erase block designate register 2 EBR2 H'FFAB
RAM emulation register RAMER H'FEDB
Flash memory power control register FLPWCR H'FFAC
Rev. 2.00, 03/04, page 403 of 508
Section 18 Clock Pulse Generator
This LSI has an on-chip clock pulse generator that generates the system clock (φ), the bus master
clock, internal clocks, and subclock. The clock pulse generator consists of an oscillator, PLL
circuit, subclock divider, clock selection circuit, medium-speed clock divider, and bus master
clock selection circuit. A block diagram of the clock pulse generator is shown in figure 18.1.
EXTAL
XTAL
SCK2 to SCK0
SCKCR
STC1, STC0
LPWRCR
[Legend]
LPWRCR: Low-power control register
SCKCR: System clock control register
Clock
oscillator
PLL circuit
(×1, ×2, ×4)
Clock
selection
circuit
System clock
to φ pin
Subclock
to WDT1, LCD
Internal clock to
supporting modules
Bus master cloc
k
to CPU
Medium-
speed
clock divider
Subclock
divider
(division
by 128)
Bus
master
clock
selection
circuit
φ/2 to
φ/32
φ
φSUB
Figure 18.1 Block Diagram of Clock Pulse Generato r
The frequency can be changed by means of the PLL circuit. Frequency changes are performed by
software by settings in the low-power control register (LPWRCR) and system clock control
register (SCKCR).
CPG0502A_000020020200
Rev. 2.00, 03/04, page 404 of 508
18.1 Register Descriptions
The on-chip clock pulse generator has the following registers.
• System clock control register (SCKCR)
• Low-power control register (LPWRCR)
18.1.1 System Clock Control Register (SCKCR)
SCKCR performs φ clock output control, selection of operation when the PLL circuit frequency
multiplication factor is changed, and medium-speed mode control.
Bit Bit Name
Initial
Value R/W Description
7 PSTOP 0 R/W φ Clock Output Disable
Controls φ output.
• High-speed Mode, Medium-Speed Mode
0: φ output
1: Fixed high
• Sleep Mode
0: φ output
1: Fixed high
• Software Standby Mode
0: Fixed high
1: Fixed high
• Hardware Standby Mode
0: High impedance
1: High impedance
6 to 4 All 0 Reserved
These bits are always read as 0.
3 STCS 0 R/W Frequency Multiplication Factor Switching Mode Select
Selects the operation when the PLL circuit frequency
multiplication factor is changed.
0: Specified multiplication factor is valid after transition
to software standby mode
1: Specified multiplication factor is valid immediately
after the STC1 and STC0 bits are rewritten
Rev. 2.00, 03/04, page 405 of 508
Bit Bit Name
Initial
Value R/W Description
2
1
0
SCK2
SCK1
SCK0
0
0
0
R/W
R/W
R/W
System Clock Select 0 to 2
These bits select the bus master clock.
000: High-speed mode
001: Medium-speed clock is φ/2
010: Medium-speed clock is φ/4
011: Medium-speed clock is φ/8
100: Medium-speed clock is φ/16
101: Medium-speed clock is φ/32
11X: Setting prohibited
[Legend]
X: Don't care
Rev. 2.00, 03/04, page 406 of 508
18.1.2 Low-Power Control Register (LPWRCR)
LPWRCR performs power-down mode control, subclock generation control, oscillation circuit
feedback resistance control, and frequency multiplication factor setting.
Bit Bit Name
Initial
Value R/W Description
7
6
DTON
LSON
0
0
R/W
R/W
See section 19.1.2, Low-Power Control Register
(LPWRCR).
5 0 R/W Reserved
Only write 0 to this bit.
4 SUBSTP 0 R/W Subclock Generation Control
0: Enables subclock generation
1: Disables subclock generation
3 RFCUT 0 R/W Oscillation Circuit Feedback Resistance Control
0: When the main clock is oscillating, sets the feedback
resistance ON. When the main clock is stopped, sets
the feedback resistance OFF.
1: Sets the feedback resistance OFF. Modification
becomes valid after returning to software standby
transfer.
Note: With a crystal resonator, the resonator will not
operate if this bit is set to 1.
2 0 R/W Reserved
Only write 0 to this bit.
1
0
STC1
STC0
0
0
R/W
R/W
Frequency Multiplication Factor
The STC bits specify the frequency multiplication factor
of the PLL circuit.
00: ×1
01: ×2
10: ×4
11: Setting prohibited
Rev. 2.00, 03/04, page 407 of 508
18.2 Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. In
either case, the input clock should not exceed 4 MHz to 20 MHz.
18.2.1 Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as shown in the example in figure
18.2. Select the damping resistance Rd according to table 18.2. An AT-cut parallel-resonance
crystal shoul d be used.
EXTAL
XTAL
R
d
C
L2
C
L1
C
L1
= C
L2
= 10 to 22 pF
Figure 18.2 Connection of Cr yst al Res o na tor (Example)
Table 18.1 Damping Resistance Value
Frequency (MHz) 4 8 12 16 20
Rd (Ω) 500 200 0 0 0
Figure 18.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has
the characteristics shown in table 18.2.
XTAL
C
L
AT-cut parallel-resonance type
EXTAL
C
0
LR
s
Figure 18.3 Crystal Resonator Equivalent Circuit
Table 18.2 Crystal Re so n at or Ch aracteristics
Frequency (MHz) 4 8 12 16 20
RS max (Ω) 120 80 60 50 40
C0 max (pF) 7 7 7 7 7
Rev. 2.00, 03/04, page 408 of 508
18.2.2 External Clock Input
Circuit Configuration : An external clock signal can be input as shown in the examples in figure
18.4. If the XTAL pin is left open, ensure that stray capacitance does not exceed 10 pF. When
complementary clock is input to the XTAL pin, the external clock input should be fixed high in
standby mode.
EXTAL
XTAL
EXTAL
XTAL
External clock input
Open
External clock input
(a) XTAL pin left open
(b) Complementary clock input at XTAL pin
Figure 18.4 External Cloc k Input (E xa mple s)
Table 18.3 shows the input conditions for the external clock.
Table 18.3 External Clock Input Conditions
VCC = 5.0 V ± 10%
Item Symbol Min. Max. Unit Test Conditions
External clock input low
pulse width
tEXL 15 ns
External clock input high
pulse width
tEXH 15 ns
External clock rise time tEXr 5 ns
External clock fall time tEXf 5 ns
Figure 18.5
0.4 0.6 tcyc φ ≥ 5 MHz Clock low pulse width
level
tCL
80 ns φ < 5 MHz
0.4 0.6 tcyc φ ≥ 5 MHz Clock high pulse width
level
tCH
80 ns φ < 5 MHz
Figure 21.2
Rev. 2.00, 03/04, page 409 of 508
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
0.5
EXTAL
Figure 18.5 External Clock Input Timing
18.3 PLL Circuit
The PLL circuit multiplies the frequency of the clock from the oscillator by a factor of 1, 2, or 4.
The multiplication factor is set by the STC0 and STC1 bits in LPWRCR. The phase of the rising
edge of the internal clock is controlled so as to match that at the EXTAL pin.
When the multiplication factor of the PLL circuit is changed, the operation varies according to the
setting of the STCS bit in SCKCR.
When STCS = 0, the setting becomes valid after a transition to software standby mode. The
transition time count is performed in acco rdance with the setting of bits STS0 to STS2 in SBYCR.
For details on SBYCR, see section 19.1.1, Standby Control Register (SBYCR).
1. The initial PLL circuit multiplication factor is 1.
2. STS0 to STS2 are set to give the specified transition time.
3. The target value is set in STC0 and STC1, and a transition is made to software standby mode.
4. The clock pulse generator stops and the value set in STC0 and STC1 becomes valid.
5. Software standby mod e is cleare d, and a transition time is secured in accordance with the
setting in STS0 to STS2.
6. After the set transition time has elapsed, this LSI resumes operation using the target
multiplication factor.
18.4 Subclock Divider
The subclock divider divides the clock generated by the oscillator by 128 to generate a subclock.
When u sing the subclock as a system clock, the compensation by software is needed.
18.5 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32.
Rev. 2.00, 03/04, page 410 of 508
18.6 Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the clock supplied to the bus master by setting the
bits SCK 2 to SCK0 in SCKCR. The bus master clock can be selected from high-speed mode, or
medium-speed cl ocks (φ/2, φ/4, φ/8, φ/16, and φ/32).
18.7 Usage Notes
18.7.1 Note on Crystal Resonator
As various characteristics related to the crystal resonator are closely linked to the user's board
design, thorough evaluation is necessary on the user's part, using the resonator connection
examples shown in this section as a guide. As the resonator circuit ratings will depend on the
floating capacitance of the resonator and the mounting circuit, the ratings should be determined in
consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the
maximum rating is not applied to the oscillator pin.
18.7.2 Note on Board Design
When designing the board, place the crystal resonator and its load capacitors as close as possible
to the XTAL and EXTAL pins. Othe r signal lines should be routed away from the oscillator
circuit, as shown in figure 18.6. This is to prevent induction from interfering with correct
oscillation.
CL2
Avoid
Signal A Signal B
CL1
This LSI
XTAL
EXTAL
Figure 18.6 Note on Board Design of Oscillator Circuit
Figure 18.7 shows external circuitry recommended to be provided around the PLL circuit. Place
oscillation stabilizatio n capacitor C1 and resistor R1 close to the PLLCAP pin, and ensure that no
other signal lines cross this line. Separate PLLVcL and PLLVss from the other Vcc and Vss lines
at the board power supp ly source, and be sure to insert bypass capacitors CB close to the pins.
Rev. 2.00, 03/04, page 411 of 508
PLLCAP
PLLVSS
VCC
VCL
VSS
(Values are preliminary recommended values.)
Note: CB are laminated ceramic.
R1 : 3 k C1 : 470 pF
CB : 0.1 F CB : 0.1 F
Figure 18.7 External Circuitry Recommended for PLL Circuit
Rev. 2.00, 03/04, page 412 of 508
Rev. 2.00, 03/04, page 413 of 508
Section 19 Power-Down Modes
In addition to the normal program execution state, this LSI has power-down modes in which
operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power
operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and
so on.
This LSI's operating mod es are as follows:
• High-speed mode
• Medium-speed mode
• Subactive mode
• Sleep mode
• Subsleep mode
• Watch mode
• Module stop mode
• Softw a re standby mode
• Hardware standby mode
Sleep mode and subsleep mode are CPU states, medium-speed mode is a CPU and bus master
state, subactive mode is a CPU, bus master, and on-chip peripheral function state, and module stop
mode is an on-chip peripheral function (including bus masters other than the CPU) state. Some of
these states can be combined.
After a reset, the LSI operates in high-speed mode or module stop mode.
Figure 19.1 shows the mode transition diagram. Table 19.1 shows the conditions for transition to
each mode when a SLEEP instruction is executed, and table 19.2 shows the internal state of the
LSI in each mode.
LPWS269A_000020020200
Rev. 2.00, 03/04, page 414 of 508
SSBY = 0
Reset state
Program-halted state
pin = High,
pin = Low
pin = High
program execution state
Sleep command
All interrupts
Interrupts
Interrupt*
1
,
LSON bit = 0
Interrupt*
1
,
LSON bit = 1
Sleep command
Sleep command
Sleep command
Sleep command
External interrupt
High-speed mode
(main clock)
Sleep command
After the oscillation
stabilization time
(STS2 to STS0), clock
switching exception
processing
SSBY = 1, PSS = 1,
DTON = 1, LSON = 0
Sleep command
Clock switching
exception processing
SSBY = 1, PSS = 1,
DTON = 1, LSON = 1
SSBY = 1
SSBY = 1
PSS = 1, DTON = 0
SSBY = 0
PSS = 1, LSON = 1
*1
*2
*3
*4
NMI, IRQ0 to IRQ5, and WDT_1 interrupts
NMI, IRQ0 to IRQ5, WDT_0, and WDT_1 interrupts
All interrupts
NMI and IRQ0 to IRQ5
When a transition is made between modes by means of an interrupt, the transition cannot be made
on interrupt source generation alone. Ensure that interrupt handling is performed after accepting
the interrupt request.
From any state except hardware standby mode, a transition to the reset state occurs when
is driven Low.
From any state, a transition to hardware standby mode occurs when is driven low.
Always select high-speed mode before making a transition to watch mode or subactive mode.
Medium-speed
mode
(main clock)
Subactive
mode (subclock)
Subsleep
mode (subclock)
Watch mode
(subclock)
*
3
*
4
*
2
pin = Low
Hardware
standby mode
Software
standby mode
Sleep mode
(main clock)
: Power-down mode: Transition after exception processing
Notes :
SCK2 to
SCK0 = 0
SCK2 to
SCK0 0
Figure 19.1 Mode Transiti on Dia gram
Rev. 2.00, 03/04, page 415 of 508
Table 19.1 Power-Do wn Mode Transition C onditions
Status of Control Bit at
Transition Pre-
Transition
State SSBY PSS LSON DTON
State after Transition
Invoked by SLEEP
Instruction
State after Transition
back from Power-
Down Mode Invoked
by Interrupt
0 * 0 * Sleep High-speed/Medium-
speed
0 * 1 *
1 0 0 * Software standby High-speed/Medium-
speed
1 0 1 *
1 1 0 0 Watch High-speed
1 1 1 0 Watch Subactive
1 1 0 1
High-speed/
Medium-
speed
1 1 1 1 Subactive
0 0 * *
0 1 0 *
0 1 1 * Subsleep Subactive
1 0 * *
1 1 0 0 Watch High-speed
1 1 1 0 Watch Subactive
1 1 0 1 High-speed
Subactive
1 1 1 1
[Legend]
*: Don't care
: Setting prohibited
Rev. 2.00, 03/04, page 416 of 508
Table 19.2 LSI Internal States in Each Mode
Function High-
Speed Medium-
Speed Sleep Module
Stop
Watch
Subactive
Subsleep Software
Standby Hardware
Standby
System clock pulse
generator
Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted Halted
CPU Instructions
Registers
Functioning Medium-
speed
operation
Halted
(retained)
High/
medium-
speed
operation
Halted
(retained)
Subclock
operation
Halted
(retained)
Halted
(retained)
Halted
(undefined)
NMI External
interrupts IRQ0 to
IRQ5
Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted
Peripheral
functions
WDT_1 Functioning Functioning Functioning Subclock
operation
Subclock
operation
Subclock
operation
Halted
(retained)
Halted
(reset)
WDT_0 Functioning Functioning Functioning Halted
(retained)
Subclock
operation
Subclock
operation
Halted
(retained)
Halted
(reset)
TPU_0
TPU_1
TPU_2
Functioning Functioning Functioning Halted
(retained)
Halted
(retained)
Halted
(retained)
Halted
(retained)
Halted
(retained)
Halted
(reset)
SCI_0 Functioning Functioning Functioning Halted
(reset)
Halted
(reset)
Halted
(reset)
Halted
(reset)
Halted
(reset)
Halted
(reset)
SCI_1
RWM
HCAN
A/D
LCD Functioning Functioning Functioning Halted
(retained)
Functioning Functioning Functioning Halted
(retained)
Halted
(reset)
RAM Functioning Functioning Halted
(retained)
Functioning Retained Functioning Retained Retained Retained
I/O Functioning Functioning Functioning Functioning Retained Functioning Retained Retained High
impedance
Notes: 1. "Halted (retained)" means that internal register values are retained. The internal state is
"operation suspended."
2. "Halted (reset)" means that internal register values and internal states are initialized.
3. In module stop mode, only modules for which a stop setting has been made are halted
(reset or retained).
4. When the LCD is operated in watch mode, subactive mode, or subsleep mode, select
the subclock as a system clock.
Rev. 2.00, 03/04, page 417 of 508
19.1 Register Descriptions
Registers related to power-down modes are shown below. For details on the system clock control
register (SCKCR), see section 18.1.1, System Clock Control Register (SCKCR).
• System clock control register (SCKCR)
• Standby control register (SBYCR)
• Low-power control register (LPWRCR)
• Module stop control register A (M STPCRA)
• Module stop control register B (MSTPCRB)
• Module stop control register C (MSTPCRC)
• Module stop control register D (M STPCRD)
19.1.1 Standby Control Register (SBYCR)
SBYCR performs software standby mode control.
Bit Bit Name Initial
Value R/W Description
7 SSBY 0 R/W Software Standby
This bit specifies the transition mode after executing the
SLEEP instruction
0: Shifts to sleep mode when the SLEEP instruction is
executed
1: Shifts to software standby mode when the SLEEP
instruction is executed
This bit does not change when clearing the software
standby mode by using external interrupts and shifting
to normal operation. This bit should be written with 0
when clearing.
Rev. 2.00, 03/04, page 418 of 508
Bit Bit Name Initial
Value R/W Description
6
5
4
STS2
STS1
STS0
0
0
0
R/W
R/W
R/W
Standby Timer Select 0 to 2
These bits select the MCU wait time for clock
stabilization when software standby mode is cancelled
by an external interrupt. With a crystal oscillator (Table
19.3), select a wait time of 8 ms (oscillation stabilization
time) or more, depending on the operating frequency.
With an external clock, select a wait time of 2 ms or
more.
000: Standby time = 8192 states
001: Standby time = 16384 states
010: Standby time = 32768 states
011: Standby time = 65536 states
100: Standby time = 131072 states
101: Standby time = 262144 states
110: Reserved
111: Standby time = 16 states
3 1 R/W Reserved
The write value should always be 1.
2 to 0 All 0 Reserved
These bits are always read as 0 and cannot be
modified.
Rev. 2.00, 03/04, page 419 of 508
19.1.2 Low-Power Control Register (LPWRCR)
LPWRCR is an 8-bit readable/writable register that performs power-down mode control, subclock
generation control, oscillation circuit feedback resistance control, and frequency multiplication
factor setting.
Bit Bit Name Initial
Value R/W Description
7 DTON 0 R/W Direct Transition ON Flag
0: When the SLEEP instruction is executed in high-
speed mode or medium-speed mode, operation shifts
to sleep mode, software standby mode, or watch
mode*.
When the SLEEP instruction is executed in subactive
mode, operation shifts to subsleep mode or watch
mode.
1: When the SLEEP instruction is executed in high-
speed mode or medium-speed mode, operation shifts
directly to subactive mode*, or shifts to sleep mode
or software standby mode. When the SLEEP
instruction is executed in subactive mode, operation
shifts directly to high-speed mode, or shifts to
subsleep mode.
6 LSON 0 R/W Low-Speed ON Flag
0: When the SLEEP instruction is executed in high-
speed mode or medium-speed mode, operation shifts
to sleep mode, software standby mode, or watch
mode*. When the SLEEP instruction is executed in
subactive mode, operation shifts to watch mode or
shifts directly to high-speed mode. Operation shifts to
high-speed mode when watch mode is cancelled.
1: When the SLEEP instruction is executed in high-
speed mode, operation shifts to watch mode or
subactive mode*. When the SLEEP instruction is
executed in sub-active mode, operation shifts to
subsleep mode or watch mode. Operation shifts to
subactive mode when watch mode is cancelled.
5 0 R/W Reserved
This bit can be read from and written to. However, do
not write 1 to this bit.
4 SUBSTP 0 R/W Subclock Generation Control
0: Enables subclock generation
1: Disables subclock generation
Rev. 2.00, 03/04, page 420 of 508
Bit Bit Name Initial
Value R/W Description
3 RFCUT 0 R/W Oscillation Circuit Feedback Resistance Control
0: When the main clock is oscillating, sets the feedback
resistance ON. When the main clock is stopped, sets
the feedback resistance OFF.
1: Sets the feedback resistance OFF.
Note: With a crystal resonator, the resonator will not
operate if this bit is set to 1.
2 0 R/W Reserved
This bit can be read from and written to. However, do
not write 1 to this bit.
1
0
STC1
STC0
0
0
R/W
R/W
Frequency Multiplication Factor Setting
These bits specify the frequency multiplication factor of
the PLL circuit.
00: x1
01: x2
10: x4
11: Setting prohibited
Note: * Always set high-speed mode when shifting to watch mode or subactive mode.
Rev. 2.00, 03/04, page 421 of 508
19.1.3 Module Stop Control Registers A to D (MSTPCRA to MSTPCRD)
MSTPCR performs module stop mode control. Setting a bit to 1 causes the corresponding module
to enter module stop mode. Clearing the bit to 0 clears the module stop mode.
• MSTPCRA
Bit Bit Name Initial
Value R/W Module
7 MSTPA7* 0 R/W
6 MSTPA6* 0 R/W
5 MSTPA5 1 R/W 16-bit timer pulse unit (TPU)
4 MSTPA4* 1 R/W
3 MSTPA3* 1 R/W
2 MSTPA2* 1 R/W
1 MSTPA1 1 R/W A/D converter
0 MSTPA0* 1 R/W
• MSTPCRB
Bit Bit Name Initial
Value R/W Module
7 MSTPB7 1 R/W Serial communication interface_0 (SCI_0)
6 MSTPB6 1 R/W Serial communication interface_1 (SCI_1)
5 MSTPB5* 1 R/W
4 MSTPB4* 1 R/W
3 MSTPB3* 1 R/W
2 MSTPB2* 1 R/W
1 MSTPB1* 1 R/W
0 MSTPB0* 1 R/W
Rev. 2.00, 03/04, page 422 of 508
• MSTPCRC
Bit Bit Name Initial
Value R/W Module
7 MSTPC7* 1 R/W
6 MSTPC6* 1 R/W
5 MSTPC5* 1 R/W
4 MSTPC4* 1 R/W
3 MSTPC3 1 R/W Controller Area Network (HCAN)
2 MSTPC2* 1 R/W
1 MSTPC1* 1 R/W
0 MSTPC0* 1 R/W
• MSTPCRD
Bit Bit Name Initial
Value R/W Module
7 MSTPD7 1 R/W Motor control PWM timer (PWM)
6 MSTPD6 1 R/W LCD controller/driver (LCD)
5 Undefined
4 Undefined
3 Undefined
2 Undefined
1 Undefined
0 Undefined
Note: * MSTPA7 and MSTPA6 are readable/writable bits with an initial value of 0 and should
always be written with 0.
MSTPA4 to MSTPA2, MSTPA0, MSTPB5 to MSTPB0, MSTPC7 to MSTPC4 and
MSTPC2 to MSTPC0 are readable/writable bits with an initial value of 1 and should
always be written with 1.
Rev. 2.00, 03/04, page 423 of 508
19.2 Medium-Speed Mode
When the SCK0 to SCK2 bits in SCKCR are set to 1, the operating mode changes to medium-
speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on
the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK0 to SCK2 bits. On-chip
peripheral modules other than bus masters always operate on the high-speed clock (φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip
memory is accessed in four states, and internal I/O registers in eight states.
Medium-speed mode is cleared by clearing all of bits SCK0 to SCK2 to 0. A transition is made to
high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
If the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is
made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored.
When the SLEEP instruction is executed with the SSBY bit is set to 1, operation shifts to the
software standby mode. When software standby mode is cleared by an external interrupt, medium-
speed mode is restored.
When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset
state. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, a transition is made to hardwar e standby mode.
Figure 19.2 shows the timing for transition to and clearance of medium-speed mode.
SCKCR SCKCR
φ,
supporting module clock
Bus master clock
Internal address bus
Internal write signal
Medium-speed mode
Figure 19.2 Medium-Speed Mode Transition and Clearance Timing
Rev. 2.00, 03/04, page 424 of 508
19.3 Sleep Mode
19.3.1 Transition to Sleep Mode
If the SLEEP instruction is executed when the SSBY bit in SBYCR = 0, the CPU enters the sleep
mode. In sleep mode, CPU operation stops, however the contents of the CPU's internal registers
are retained. Other peripheral modules do not stop.
19.3.2 Clearing Sleep Mode
Sleep mode is cleared by any interrupt, or signals at the RES or STBY pin.
• Exiting sleep mode by interrupts:
When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or if interrupts other than NMI are masked by the
CPU.
• Exiting sleep mode by RES pin:
Setting the RES pin low selects the reset state. After the stipulated reset input duration, driving
the RES pin high restart the CPU performing reset exception processing.
• Exiting sleep mode by STBY pin:
When the STBY pin level is driven low, a transition is mad e to ha rdware standby mode.
Rev. 2.00, 03/04, page 425 of 508
19.4 Software Standby Mode
19.4.1 Transition to Software Standby Mode
A transition is made to software standby mode if the SLEEP instruction is executed when the
SSBY bit is set to 1. In this mode, the CPU, on-chip peripheral modules, and oscillator, all stop.
However, the contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip
peripheral modules other than the SCI, PWM, HCAN, and A/D converter, and the states of I/O
ports, are retained. In this mode, the oscillator stops, and therefore power dissipation is
significant l y re duced.
19.4.2 Clearing Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI and IRQ0 to IRQ5 pins), or by
means of the RES pin or STBY pin.
• Clearing with an interrupt
When an NMI, IRQ0, or IRQ5 interrupt r equest signal is input, clock oscillation starts, and
after the time set in bits STS0 to STS2 in SBYCR has elapsed, stable clocks are supplied to the
entire chip, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5
is generated. Software standby mode cannot be cleared if the interrupt has been masked on the
CPU side.
• Clearing with the RES pin
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are sup plied to the entire chip. Note that the RES pin must be held low
until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset except i on
handling.
• Clearing with the STBY pin
When the STBY pin is driven low, a transition is made to hardwar e standby mode.
Rev. 2.00, 03/04, page 426 of 508
19.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode
Bits STS2 to STS0 in SBYCR should be set as described below.
• Us ing a crystal oscillator:
Set bits STS0 to STS2 so that the standby time is at least 8 ms (the oscillation stabilizatio n
time).
Table 19.3 shows the standby times for different operating frequencies and settings of bits
STS0 to STS2.
• Using an external clock
The PLL circuit requires a time for stabilization. Set bits STS0 to STS2 so that the standby time is
at least 2 ms (the oscillation stabilization time).
Table 19.3 Oscillation Stabilization Time Settings
STS2 STS1 STS0 Standby Time 20
MHz 16
MHz 12
MHz 10
MHz 8
MHz 6
MHz 4
MHz Unit
0 8192 states 0.41 0.51 0.68 0.8 1.0 1.3 2.0 0
1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1
0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 8.2
0
1
1 65536 states 3.3 4.1 5.5 6.6 8.2 10.9 16.4
0 131072 states 6.6 8.2 10.9 13.1 16.4 21.8 32.8 0
1 262144 states 13.1 16.4 21.8 26.2 32.8 43.6 65.6
ms
0 Reserved
1
1
1 16 states* 0.8 1.0 1.3 1.6 2.0 1.7 4.0 µs
: Recommended time setting
Note: * Do not use this setting
Rev. 2.00, 03/04, page 427 of 508
19.4.4 Software Standby Mode Application Example
Figure 19.3 shows an ex ample in which a transition is made to software standby mode at a falling
edge on the NMI pin, and software standby mode is cleared at a rising edge on the NMI pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is th en cleared at the rising edge on the NMI pin.
Oscillator
φ
NMI
NMIEG
SSBY
NMI exception
processing
NMIEG = 1
SSBY = 1 Oscillation
stabilization
time t
osc2
Software standby mode
(power-down mode)
NMI exception
processing
SLEEP command
Figure 19.3 Software Standby M ode Ap pl i cati o n Example
Rev. 2.00, 03/04, page 428 of 508
19.5 Hardware Standby Mode
19.5.1 Transition to Hard w are St a ndb y Mo de
When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the STBY pin low.
Do not change the state of the mode pins (MD0 and MD2) while this LSI is in hardware standby
mode.
19.5.2 Clearing Hardware Standby Mode
Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY
pin is driven hig h while the RES pin is low, the reset state is set and clock oscillation is started.
Ensure that the RES pin is held low until th e clock oscillator stabilizes (at least 8 ms—the
oscillation stabilizatio n time—when using a crystal oscillator). When the RES pin is subsequently
driven high, a transition is made to the program execution state via the reset exception handling
state.
Rev. 2.00, 03/04, page 429 of 508
19.5.3 Hardware Standby Mode Timings
Timing of Trans ition to Hardware Standby Mod e:
1. To retain RAM contents with the RAME bit set to 1 in SYSCR
Drive the RES signal low at least 10 states before the STBY signal goes low, as shown in
figure 19.4. After STBY has gone low , RES has to wait for at least 0 ns before becoming high.
t
2
≥0ns
t
1
≥10t
cyc
Figure 19.4 Timing of Transition to Hardwa re Standby Mode
2. To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do
not need to be retained
RES does not have to be driven low as in the above case.
Timing of Recovery from Hardware Standby Mode:
Drive the RES signal low approximately 100 ns or longer befor e STBY goes high to execute a
power-on reset.
t
OSC1
t≥100ns
Figure 19.5 Timing of Recovery fr om H ardware Standby Mode
Rev. 2.00, 03/04, page 430 of 508
19.6 Module Stop Mode
Module stop mode can be set for individual on-chip peripheral modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a tran sition is made to module stop mode. The CPU continu es operating
independently.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the SCI (some SCI registers are retained), PWM, HCAN, and A/D converter are
retained.
After reset clearance, all modu les are in module stop mode.
When an on-chip peripheral module is in module stop mode, read/write access to its registers is
disabled.
Rev. 2.00, 03/04, page 431 of 508
19.7 Watch Mode
19.7.1 Transition to Wa tch M ode
CPU operation makes a transition to watch mode when the SLEEP instruction is executed in high-
speed mode or subactive mode with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 0,
and the PSS bit in TCSR_1 (WDT_1) = 1.
In watch mode, the CPU is stopped and peripheral modules other than WDT_1 and LCD are also
stopped. The contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip
peripheral modules other than the SCI, PWM, HCAN, and A/D converter, and the states of I/O
ports, are retained.
19.7.2 Canceling Watch Mode
Watch mode is canceled by any interrupt (WOVI1 interrupt, NMI pin, or IRQ0 to IRQ5 pin), or
signals at the RES, or STBY pin.
Canceling Watch Mode by Interrupt: When an interrupt occurs, watch mode is canceled and a
transition is made to high-speed mode or medium-speed mode when the LSON bit in LPWRCR =
0 or to subactive mode when the LSON bit = 1. When a transition is made to high-speed mode, a
stable clock is supplied to all LSI circuits and interrup t exception processing starts after the time
set in the STS2 to STS0 bits of SBYCR has elapsed. In case of an IRQ0 to IRQ5 interrupt, watch
mode is not canceled if the corresponding enable bit has been cleared to 0. In case of the interrupt
from the on-chip peripheral modules, if the interrupt enable register has been set to disable the
reception of that interrupt, or is masked by the CPU, watch mode is not canceled.
For the setting of the oscillation stabilization time when making a transition from watch mode to
high-speed mode, see section 19.4.3, Setting Oscillation Stabilization Time after Clearing
Software Standby Mode.
Canceling Watch Mode by RES pin: For canceling watch mode by the RES pin, see section
19.4.2, Clearing Software Standby Mode.
Canceling Watch Mode by STBY pin: When the STBY pin is driven low, a transition is made to
hardware standby mode.
Rev. 2.00, 03/04, page 432 of 508
19.8 Subsleep Mode
19.8.1 Transition to Subsleep Mode
When the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR = 0, the
LSON bit in LPWRCR = 1, and the PSS bit in TCSR_1 (WDT_1) = 1, CPU operation shifts to
subsleep mode.
In subsleep mode, the CPU is stopped and peripheral modules other than WDT_0, WDT_1, and
LCD are also stopped. The contents of the CPU's internal registers, on-chip RAM data, and the
states of on-chip peripheral modules other than the SCI, PWM, HCAN, and A/D converter, and
the states of I/O ports, are retained.
19.8.2 Canceling Subsleep Mode
Subsleep mode is canceled by any interrupt (WOVI0 or WOVI1 interrupt, NMI pin, or IRQ0 to
IRQ5 pin), or signals at the RES or STBY pin.
Canceling Subsleep Mode by Interrupt: When an interrupt oc curs, subsleep mode is cancel ed
and interrupt exception processing starts.
In case of an IRQ0 to IRQ5 interrupt, subsleep mode is not canceled if the corresponding enable
bit has been cleared to 0. In case of the interrupt from the on-chip peripheral modules, if the
interrupt enable register has been set to disable the reception of that interrupt, or is masked by the
CPU, subsleep mode is not canceled.
Canceling Subsleep Mode by RES pin: For canceling subsleep mode by the RES pin, see section
19.4.2, Clearing Software Standby Mode.
Canceling Subsleep Mode by STBY pin: When the STBY pin is driven low, a transition is made
to hardware standby mode.
Rev. 2.00, 03/04, page 433 of 508
19.9 Subactive Mode
19.9.1 Transition to Subactive Mode
CPU operation makes a transition to subactive mode when the SLEEP instruction is executed in
high-speed mode with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 1, the LSON bit
= 1, and the PSS bit in TCSR_1 (WDT_1) = 1. When an interrupt occurs in watch mode, and if the
LSON bit of LPWRCR is 1,a transition is made to su bactive mode. And if an interrupt occurs in
subsleep mode, a transition is made to subactive mo de.
In subactive mode, the CPU operates at low speed on the subclock, and the program is executed
one after another. Peripheral modules other than WDT_0, WDT_1, and LCD are also stopped.
When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SCKCR must be set to 0.
19.9.2 Canceling Subactive Mode
Subactive mode is canceled by the SLEEP instruction or signals at the RES or STBY pin.
Canceling Subactive Mode by SLEEP Instruction: When the SLEEP instruction is execute d
with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 0, and the PSS bit in TCSR_1
(WDT_1) = 1, subactive mode is canceled and a transition is made to watch mode. When the
SLEEP instruction is executed with the SSBY bit in SBYCR = 0, the LSON bit in LPWRCR = 1,
and the PSS bit in TCSR_1 (WDT_1) = 1, a transition is made to subsleep mode. When the
SLEEP instruction is executed with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 1,
the LSON bit = 0, and the PSS bit in TCSR_1 (WDT_1) = 1, a direct transition is made to high-
speed mode (SCK0 to SCK2 are all 0).
Canceling Subactive Mode by RES pin: For canceling subactive mode by the RES pin, see
section 19.4.2, Cl eari ng So ft w a re Sta nd b y Mode.
Canceling Subactive Mode by STBY pin: When the STBY pin is driven low, a transitio n is
made to hardware standby mode.
Rev. 2.00, 03/04, page 434 of 508
19.10 Direct Transitions
There a re three modes, high-speed, medium-speed, and subactive, in which the CPU executes
programs. When a direct transition is made, there is no interruption of program execu tion in
shifting between high-speed and subactive modes. Direct transitions are enabled by setting the
DTON bit in LPWRCR to 1, then executing the SLEEP instruction. After a transition, direct
transition interrupt exception processing starts.
19.10.1 Direct Transitions from High-Speed Mode to Subactive Mode
Execute the SLEEP instruction in high-speed mode with the SSBY bit in SBYCR = 1, the LSON
bit in LPWRCR= 1, the DTON bit = 1, and the PSS bit in TCSR_1 (WDT_1) = 1, to mak e a direct
transition to subactive mode.
19.10.2 Direct Transitions from Subactive Mode to High-Speed Mode
Execute the SLEEP instruction in subactive mode with the SSBY bit in SBYCR = 1, the LSON bit
in LPWRCR = 0, the DTON bit = 1, and the PSS bit in TCSR_1 (WDT_1) = 1, to make a direct
transition to high-speed mode after the time set in the STS2 to STS0 bits of SBYCR h as elapsed.
19.11 φ Clock Output Disabling Function
The output of the φ clock can be controlled by means of the PSTOP bit in SCKCR and DDR for
the corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus
cycle, and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When
DDR for the co rresponding port is cleared to 0, φ clock output is disabled and input port mode is
set. Table 19.4 shows the state of the φ pin in each processing state.
Table 19.4 φ Pin State in Each Processing State
Register Settings
DDR PSTOP
High-Speed
Mode
Medium-Speed
Mode Subactive
Mode Sleep Mode
Subsleep Mode
Software
Standby Mode
Watch Mode
Direct
Transitions Hardware
Standby Mode
0 X High impedance High impedance High impedance High impedance High impedance
1 0 φ output φSUB output φ output Fixed high High impedance
1 1 Fixed high Fixed high Fixed high Fixed high High impedance
[Legend]
X: Don't care
Rev. 2.00, 03/04, page 435 of 508
19.12 Usage Notes
19.12.1 I/O Port Status
The status of the I/O ports is retained in watch mode. Also, when the OPE bit is set to 1, the
address bus and bus control signals continue to be output. Therefore, when a high level is output,
the current consumption is not diminished by the amount of current to support the high level
output.
19.12.2 Current Dissipation during Oscillation Stabilization Wait Period
The current consu mption increases during the oscillation stabilization wait period.
19.12.3 On-Chip Peripheral Module Interrupt
The on-chip peripheral module (TPU), which halts in subactive mode, cannot cancel that interrupt
in subactive mode. Thus, if a transition is made to subactive mode when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source.
Interrupts should therefore be disabled before executing the SLEEP instruction, then entering
subactive mode or watch mode.
19.12.4 Writing to MSTPCR
MSTPCR should only be written to by the CPU.
Rev. 2.00, 03/04, page 436 of 508
Rev. 2.00, 03/04, page 437 of 508
Section 20 List of Registers
The address list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1. Register addresses (address order)
• Registers are listed from the lower allocation addresses.
• Registers are classified by functional modules.
• The access size is indicated.
2. Register bits
• Bit configurations of the registers are described in the same order as the register addresses.
• Reserved bits are indicated by in the bit name column.
• No entry in the bit-name column indicates that the whole register is allocated as a counter or
for holdin g dat a.
3. Register states in each operating mode
• Register states are described in the same order as the register addresses.
• The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral module, refer to the section on that on-chip peripheral mo dule.
Rev. 2.00, 03/04, page 438 of 508
20.1 Register Addresses (Address Order)
The data bus width indicat es t he numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
Abbreviation
Number
of Bits
Address*
Module
Data
Bus
Width
Number
of Access
States
Master control register MCR 8 H'F800 HCAN 16 4
General status register GSR 8 H'F801 HCAN 16 4
Bit configuration register BCR 16 H'F802 HCAN 16 4
Mailbox configuration register MBCR 16 H'F804 HCAN 16 4
Transmit wait register TXPR 16 H'F806 HCAN 16 4
Transmit wait cancel register TXCR 16 H'F808 HCAN 16 4
Transmit acknowledge register TXACK 16 H'F80A HCAN 16 4
Abort acknowledge register ABACK 16 H'F80C HCAN 16 4
Receive complete register RXPR 16 H'F80E HCAN 16 4
Remote request register RFPR 16 H'F810 HCAN 16 4
Interrupt register IRR 16 H'F812 HCAN 16 4
Mailbox interrupt mask register MBIMR 16 H'F814 HCAN 16 4
Interrupt mask register IMR 16 H'F816 HCAN 16 4
Receive error counter REC 8 H'F818 HCAN 16 4
Transmit error counter TEC 8 H'F819 HCAN 16 4
Unread message status register UMSR 16 H'F81A HCAN 16 4
Local acceptance filter mask L LAFML 16 H'F81C HCAN 16 4
Local acceptance filter mask H LAFMH 16 H'F81E HCAN 16 4
Message control 0[1] MC0[1] 8 H'F820 HCAN 16 4
Message control 0[2] MC0[2] 8 H'F821 HCAN 16 4
Message control 0[3] MC0[3] 8 H'F822 HCAN 16 4
Message control 0[4] MC0[4] 8 H'F823 HCAN 16 4
Message control 0[5] MC0[5] 8 H'F824 HCAN 16 4
Message control 0[6] MC0[6] 8 H'F825 HCAN 16 4
Message control 0[7] MC0[7] 8 H'F826 HCAN 16 4
Message control 0[8] MC0[8] 8 H'F827 HCAN 16 4
Rev. 2.00, 03/04, page 439 of 508
Register Name
Abbreviation
Number
of Bits
Address*
Module
Data
Bus
Width
Number
of Access
States
Message control 1[1] MC1[1] 8 H'F828 HCAN 16 4
Message control 1[2] MC1[2] 8 H'F829 HCAN 16 4
Message control 1[3] MC1[3] 8 H'F82A HCAN 16 4
Message control 1[4] MC1[4] 8 H'F82B HCAN 16 4
Message control 1[5] MC1[5] 8 H'F82C HCAN 16 4
Message control 1[6] MC1[6] 8 H'F82D HCAN 16 4
Message control 1[7] MC1[7] 8 H'F82E HCAN 16 4
Message control 1[8] MC1[8] 8 H'F82F
HCAN 16 4
Message control 2[1] MC2[1] 8 H'F830 HCAN 16 4
Message control 2[2] MC2[2] 8 H'F831 HCAN 16 4
Message control 2[3] MC2[3] 8 H'F832 HCAN 16 4
Message control 2[4] MC2[4] 8 H'F833 HCAN 16 4
Message control 2[5] MC2[5] 8 H'F834 HCAN 16 4
Message control 2[6] MC2[6] 8 H'F835 HCAN 16 4
Message control 2[7] MC2[7] 8 H'F836 HCAN 16 4
Message control 2[8] MC2[8] 8 H'F837 HCAN 16 4
Message control 3[1] MC3[1] 8 H'F838 HCAN 16 4
Message control 3[2] MC3[2] 8 H'F839 HCAN 16 4
Message control 3[3] MC3[3] 8 H'F83A HCAN 16 4
Message control 3[4] MC3[4] 8 H'F83B HCAN 16 4
Message control 3[5] MC3[5] 8 H'F83C HCAN 16 4
Message control 3[6] MC3[6] 8 H'F83D HCAN 16 4
Message control 3[7] MC3[7] 8 H'F83E HCAN 16 4
Message control 3[8] MC3[8] 8 H'F83F
HCAN 16 4
Message control 4[1] MC4[1] 8 H'F840 HCAN 16 4
Message control 4[2] MC4[2] 8 H'F841 HCAN 16 4
Message control 4[3] MC4[3] 8 H'F842 HCAN 16 4
Message control 4[4] MC4[4] 8 H'F843 HCAN 16 4
Message control 4[5] MC4[5] 8 H'F844 HCAN 16 4
Message control 4[6] MC4[6] 8 H'F845 HCAN 16 4
Message control 4[7] MC4[7] 8 H'F846 HCAN 16 4
Message control 4[8] MC4[8] 8 H'F847 HCAN 16 4
Rev. 2.00, 03/04, page 440 of 508
Register Name
Abbreviation
Number
of Bits
Address*
Module
Data
Bus
Width
Number
of Access
States
Message control 5[1] MC5[1] 8 H'F848 HCAN 16 4
Message control 5[2] MC5[2] 8 H'F849 HCAN 16 4
Message control 5[3] MC5[3] 8 H'F84A HCAN 16 4
Message control 5[4] MC5[4] 8 H'F84B HCAN 16 4
Message control 5[5] MC5[5] 8 H'F84C HCAN 16 4
Message control 5[6] MC5[6] 8 H'F84D HCAN 16 4
Message control 5[7] MC5[7] 8 H'F84E HCAN 16 4
Message control 5[8] MC5[8] 8 H'F84F
HCAN 16 4
Message control 6[1] MC6[1] 8 H'F850 HCAN 16 4
Message control 6[2] MC6[2] 8 H'F851 HCAN 16 4
Message control 6[3] MC6[3] 8 H'F852 HCAN 16 4
Message control 6[4] MC6[4] 8 H'F853 HCAN 16 4
Message control 6[5] MC6[5] 8 H'F854 HCAN 16 4
Message control 6[6] MC6[6] 8 H'F855 HCAN 16 4
Message control 6[7] MC6[7] 8 H'F856 HCAN 16 4
Message control 6[8] MC6[8] 8 H'F857 HCAN 16 4
Message control 7[1] MC7[1] 8 H'F858 HCAN 16 4
Message control 7[2] MC7[2] 8 H'F859 HCAN 16 4
Message control 7[3] MC7[3] 8 H'F85A HCAN 16 4
Message control 7[4] MC7[4] 8 H'F85B HCAN 16 4
Message control 7[5] MC7[5] 8 H'F85C HCAN 16 4
Message control 7[6] MC7[6] 8 H'F85D HCAN 16 4
Message control 7[7] MC7[7] 8 H'F85E HCAN 16 4
Message control 7[8] MC7[8] 8 H'F85F
HCAN 16 4
Message control 8[1] MC8[1] 8 H'F860 HCAN 16 4
Message control 8[2] MC8[2] 8 H'F861 HCAN 16 4
Message control 8[3] MC8[3] 8 H'F862 HCAN 16 4
Message control 8[4] MC8[4] 8 H'F863 HCAN 16 4
Message control 8[5] MC8[5] 8 H'F864 HCAN 16 4
Message control 8[6] MC8[6] 8 H'F865 HCAN 16 4
Message control 8[7] MC8[7] 8 H'F866 HCAN 16 4
Message control 8[8] MC8[8] 8 H'F867 HCAN 16 4
Rev. 2.00, 03/04, page 441 of 508
Register Name
Abbreviation
Number
of Bits
Address*
Module
Data
Bus
Width
Number
of Access
States
Message control 9[1] MC9[1] 8 H'F868 HCAN 16 4
Message control 9[2] MC9[2] 8 H'F869 HCAN 16 4
Message control 9[3] MC9[3] 8 H'F86A HCAN 16 4
Message control 9[4] MC9[4] 8 H'F86B HCAN 16 4
Message control 9[5] MC9[5] 8 H'F86C HCAN 16 4
Message control 9[6] MC9[6] 8 H'F86D HCAN 16 4
Message control 9[7] MC9[7] 8 H'F86E HCAN 16 4
Message control 9[8] MC9[8] 8 H'F86F HCAN 16 4
Message control 10[1] MC10[1] 8 H'F870 HCAN 16 4
Message control 10[2] MC10[2] 8 H'F871 HCAN 16 4
Message control 10[3] MC10[3] 8 H'F872 HCAN 16 4
Message control 10[4] MC10[4] 8 H'F873 HCAN 16 4
Message control 10[5] MC10[5] 8 H'F874 HCAN 16 4
Message control 10[6] MC10[6] 8 H'F875 HCAN 16 4
Message control 10[7] MC10[7] 8 H'F876 HCAN 16 4
Message control 10[8] MC10[8] 8 H'F877 HCAN 16 4
Message control 11[1] MC11[1] 8 H'F878 HCAN 16 4
Message control 11[2] MC11[2] 8 H'F879 HCAN 16 4
Message control 11[3] MC11[3] 8 H'F87A HCAN 16 4
Message control 11[4] MC11[4] 8 H'F87B HCAN 16 4
Message control 11[5] MC11[5] 8 H'F87C HCAN 16 4
Message control 11[6] MC11[6] 8 H'F87D HCAN 16 4
Message control 11[7] MC11[7] 8 H'F87E HCAN 16 4
Message control 11[8] MC11[8] 8 H'F87F HCAN 16 4
Message control 12[1] MC12[1] 8 H'F880 HCAN 16 4
Message control 12[2] MC12[2] 8 H'F881 HCAN 16 4
Message control 12[3] MC12[3] 8 H'F882 HCAN 16 4
Message control 12[4] MC12[4] 8 H'F883 HCAN 16 4
Message control 12[5] MC12[5] 8 H'F884 HCAN 16 4
Message control 12[6] MC12[6] 8 H'F885 HCAN 16 4
Message control 12[7] MC12[7] 8 H'F886 HCAN 16 4
Message control 12[8] MC12[8] 8 H'F887 HCAN 16 4
Rev. 2.00, 03/04, page 442 of 508
Register Name
Abbreviation
Number
of Bits
Address*
Module
Data
Bus
Width
Number
of Access
States
Message control 13[1] MC13[1] 8 H'F888 HCAN 16 4
Message control 13[2] MC13[2] 8 H'F889 HCAN 16 4
Message control 13[3] MC13[3] 8 H'F88A HCAN 16 4
Message control 13[4] MC13[4] 8 H'F88B HCAN 16 4
Message control 13[5] MC13[5] 8 H'F88C HCAN 16 4
Message control 13[6] MC13[6] 8 H'F88D HCAN 16 4
Message control 13[7] MC13[7] 8 H'F88E HCAN 16 4
Message control 13[8] MC13[8] 8 H'F88F HCAN 16 4
Message control 14[1] MC14[1] 8 H'F890 HCAN 16 4
Message control 14[2] MC14[2] 8 H'F891 HCAN 16 4
Message control 14[3] MC14[3] 8 H'F892 HCAN 16 4
Message control 14[4] MC14[4] 8 H'F893 HCAN 16 4
Message control 14[5] MC14[5] 8 H'F894 HCAN 16 4
Message control 14[6] MC14[6] 8 H'F895 HCAN 16 4
Message control 14[7] MC14[7] 8 H'F896 HCAN 16 4
Message control 14[8] MC14[8] 8 H'F897 HCAN 16 4
Message control 15[1] MC15[1] 8 H'F898 HCAN 16 4
Message control 15[2] MC15[2] 8 H'F899 HCAN 16 4
Message control 15[3] MC15[3] 8 H'F89A HCAN 16 4
Message control 15[4] MC15[4] 8 H'F89B HCAN 16 4
Message control 15[5] MC15[5] 8 H'F89C HCAN 16 4
Message control 15[6] MC15[6] 8 H'F89D HCAN 16 4
Message control 15[7] MC15[7] 8 H'F89E HCAN 16 4
Message control 15[8] MC15[8] 8 H'F89F HCAN 16 4
Message data 0[1] MD0[1] 8 H'F8B0 HCAN 16 4
Message data 0[2] MD0[2] 8 H'F8B1 HCAN 16 4
Message data 0[3] MD0[3] 8 H'F8B2 HCAN 16 4
Message data 0[4] MD0[4] 8 H'F8B3 HCAN 16 4
Message data 0[5] MD0[5] 8 H'F8B4 HCAN 16 4
Message data 0[6] MD0[6] 8 H'F8B5 HCAN 16 4
Message data 0[7] MD0[7] 8 H'F8B6 HCAN 16 4
Message data 0[8] MD0[8] 8 H'F8B7 HCAN 16 4
Rev. 2.00, 03/04, page 443 of 508
Register Name
Abbreviation
Number
of Bits
Address*
Module
Data
Bus
Width
Number
of Access
States
Message data 1[1] MD1[1] 8 H'F8B8 HCAN 16 4
Message data 1[2] MD1[2] 8 H'F8B9 HCAN 16 4
Message data 1[3] MD1[3] 8 H'F8BA HCAN 16 4
Message data 1[4] MD1[4] 8 H'F8BB HCAN 16 4
Message data 1[5] MD1[5] 8 H'F8BC HCAN 16 4
Message data 1[6] MD1[6] 8 H'F8BD HCAN 16 4
Message data 1[7] MD1[7] 8 H'F8BE HCAN 16 4
Message data 1[8] MD1[8] 8 H'F8BF HCAN 16 4
Message data 2[1] MD2[1] 8 H'F8C0 HCAN 16 4
Message data 2[2] MD2[2] 8 H'F8C1 HCAN 16 4
Message data 2[3] MD2[3] 8 H'F8C2 HCAN 16 4
Message data 2[4] MD2[4] 8 H'F8C3 HCAN 16 4
Message data 2[5] MD2[5] 8 H'F8C4 HCAN 16 4
Message data 2[6] MD2[6] 8 H'F8C5 HCAN 16 4
Message data 2[7] MD2[7] 8 H'F8C6 HCAN 16 4
Message data 2[8] MD2[8] 8 H'F8C7 HCAN 16 4
Message data 3[1] MD3[1] 8 H'F8C8 HCAN 16 4
Message data 3[2] MD3[2] 8 H'F8C9 HCAN 16 4
Message data 3[3] MD3[3] 8 H'F8CA HCAN 16 4
Message data 3[4] MD3[4] 8 H'F8CB HCAN 16 4
Message data 3[5] MD3[5] 8 H'F8CC HCAN 16 4
Message data 3[6] MD3[6] 8 H'F8CD HCAN 16 4
Message data 3[7] MD3[7] 8 H'F8CE HCAN 16 4
Message data 3[8] MD3[8] 8 H'F8CF HCAN 16 4
Message data 4[1] MD4[1] 8 H'F8D0 HCAN 16 4
Message data 4[2] MD4[2] 8 H'F8D1 HCAN 16 4
Message data 4[3] MD4[3] 8 H'F8D2 HCAN 16 4
Message data 4[4] MD4[4] 8 H'F8D3 HCAN 16 4
Message data 4[5] MD4[5] 8 H'F8D4 HCAN 16 4
Message data 4[6] MD4[6] 8 H'F8D5 HCAN 16 4
Message data 4[7] MD4[7] 8 H'F8D6 HCAN 16 4
Message data 4[8] MD4[8] 8 H'F8D7 HCAN 16 4
Rev. 2.00, 03/04, page 444 of 508
Register Name
Abbreviation
Number
of Bits
Address*
Module
Data
Bus
Width
Number
of Access
States
Message data 5[1] MD5[1] 8 H'F8D8 HCAN 16 4
Message data 5[2] MD5[2] 8 H'F8D9 HCAN 16 4
Message data 5[3] MD5[3] 8 H'F8DA HCAN 16 4
Message data 5[4] MD5[4] 8 H'F8DB HCAN 16 4
Message data 5[5] MD5[5] 8 H'F8DC HCAN 16 4
Message data 5[6] MD5[6] 8 H'F8DD HCAN 16 4
Message data 5[7] MD5[7] 8 H'F8DE HCAN 16 4
Message data 5[8] MD5[8] 8 H'F8DF HCAN 16 4
Message data 6[1] MD6[1] 8 H'F8E0 HCAN 16 4
Message data 6[2] MD6[2] 8 H'F8E1 HCAN 16 4
Message data 6[3] MD6[3] 8 H'F8E2 HCAN 16 4
Message data 6[4] MD6[4] 8 H'F8E3 HCAN 16 4
Message data 6[5] MD6[5] 8 H'F8E4 HCAN 16 4
Message data 6[6] MD6[6] 8 H'F8E5 HCAN 16 4
Message data 6[7] MD6[7] 8 H'F8E6 HCAN 16 4
Message data 6[8] MD6[8] 8 H'F8E7 HCAN 16 4
Message data 7[1] MD7[1] 8 H'F8E8 HCAN 16 4
Message data 7[2] MD7[2] 8 H'F8E9 HCAN 16 4
Message data 7[3] MD7[3] 8 H'F8EA HCAN 16 4
Message data 7[4] MD7[4] 8 H'F8EB HCAN 16 4
Message data 7[5] MD7[5] 8 H'F8EC HCAN 16 4
Message data 7[6] MD7[6] 8 H'F8ED HCAN 16 4
Message data 7[7] MD7[7] 8 H'F8EE HCAN 16 4
Message data 7[8] MD7[8] 8 H'F8EF HCAN 16 4
Message data 8[1] MD8[1] 8 H'F8F0 HCAN 16 4
Message data 8[2] MD8[2] 8 H'F8F1 HCAN 16 4
Message data 8[3] MD8[3] 8 H'F8F2 HCAN 16 4
Message data 8[4] MD8[4] 8 H'F8F3 HCAN 16 4
Message data 8[5] MD8[5] 8 H'F8F4 HCAN 16 4
Message data 8[6] MD8[6] 8 H'F8F5 HCAN 16 4
Message data 8[7] MD8[7] 8 H'F8F6 HCAN 16 4
Message data 8[8] MD8[8] 8 H'F8F7 HCAN 16 4
Rev. 2.00, 03/04, page 445 of 508
Register Name
Abbreviation
Number
of Bits
Address*
Module
Data
Bus
Width
Number
of Access
States
Message data 9[1] MD9[1] 8 H'F8F8 HCAN 16 4
Message data 9[2] MD9[2] 8 H'F8F9 HCAN 16 4
Message data 9[3] MD9[3] 8 H'F8FA HCAN 16 4
Message data 9[4] MD9[4] 8 H'F8FB HCAN 16 4
Message data 9[5] MD9[5] 8 H'F8FC HCAN 16 4
Message data 9[6] MD9[6] 8 H'F8FD HCAN 16 4
Message data 9[7] MD9[7] 8 H'F8FE HCAN 16 4
Message data 9[8] MD9[8] 8 H'F8FF HCAN 16 4
Message data 10[1] MD10[1] 8 H'F900 HCAN 16 4
Message data 10[2] MD10[2] 8 H'F901 HCAN 16 4
Message data 10[3] MD10[3] 8 H'F902 HCAN 16 4
Message data 10[4] MD10[4] 8 H'F903 HCAN 16 4
Message data 10[5] MD10[5] 8 H'F904 HCAN 16 4
Message data 10[6] MD10[6] 8 H'F905 HCAN 16 4
Message data 10[7] MD10[7] 8 H'F906 HCAN 16 4
Message data 10[8] MD10[8] 8 H'F907 HCAN 16 4
Message data 11[1] MD11[1] 8 H'F908 HCAN 16 4
Message data 11[2] MD11[2] 8 H'F909 HCAN 16 4
Message data 11[3] MD11[3] 8 H'F90A HCAN 16 4
Message data 11[4] MD11[4] 8 H'F90B HCAN 16 4
Message data 11[5] MD11[5] 8 H'F90C HCAN 16 4
Message data 11[6] MD11[6] 8 H'F90D HCAN 16 4
Message data 11[7] MD11[7] 8 H'F90E HCAN 16 4
Message data 11[8] MD11[8] 8 H'F90F HCAN 16 4
Message data 12[1] MD12[1] 8 H'F910 HCAN 16 4
Message data 12[2] MD12[2] 8 H'F911 HCAN 16 4
Message data 12[3] MD12[3] 8 H'F912 HCAN 16 4
Message data 12[4] MD12[4] 8 H'F913 HCAN 16 4
Message data 12[5] MD12[5] 8 H'F914 HCAN 16 4
Message data 12[6] MD12[6] 8 H'F915 HCAN 16 4
Message data 12[7] MD12[7] 8 H'F916 HCAN 16 4
Message data 12[8] MD12[8] 8 H'F917 HCAN 16 4
Rev. 2.00, 03/04, page 446 of 508
Register Name
Abbreviation
Number
of Bits
Address*
Module
Data
Bus
Width
Number
of Access
States
Message data 13[1] MD13[1] 8 H'F918 HCAN 16 4
Message data 13[2] MD13[2] 8 H'F919 HCAN 16 4
Message data 13[3] MD13[3] 8 H'F91A HCAN 16 4
Message data 13[4] MD13[4] 8 H'F91B HCAN 16 4
Message data 13[5] MD13[5] 8 H'F91C HCAN 16 4
Message data 13[6] MD13[6] 8 H'F91D HCAN 16 4
Message data 13[7] MD13[7] 8 H'F91E HCAN 16 4
Message data 13[8] MD13[8] 8 H'F91F HCAN 16 4
Message data 14[1] MD14[1] 8 H'F920 HCAN 16 4
Message data 14[2] MD14[2] 8 H'F921 HCAN 16 4
Message data 14[3] MD14[3] 8 H'F922 HCAN 16 4
Message data 14[4] MD14[4] 8 H'F923 HCAN 16 4
Message data 14[5] MD14[5] 8 H'F924 HCAN 16 4
Message data 14[6] MD14[6] 8 H'F925 HCAN 16 4
Message data 14[7] MD14[7] 8 H'F926 HCAN 16 4
Message data 14[8] MD14[8] 8 H'F927 HCAN 16 4
Message data 15[1] MD15[1] 8 H'F928 HCAN 16 4
Message data 15[2] MD15[2] 8 H'F929 HCAN 16 4
Message data 15[3] MD15[3] 8 H'F92A HCAN 16 4
Message data 15[4] MD15[4] 8 H'F92B HCAN 16 4
Message data 15[5] MD15[5] 8 H'F92C HCAN 16 4
Message data 15[6] MD15[6] 8 H'F92D HCAN 16 4
Message data 15[7] MD15[7] 8 H'F92E HCAN 16 4
Message data 15[8] MD15[8] 8 H'F92F HCAN 16 4
PWM control register_1 PWCR_1 8 H'FC00 PWM_1 16 4
PWM output control register_1 PWOCR_1 8 H'FC02 PWM_1 16 4
PWM polarity register_1 PWPR_1 8 H'FC04 PWM_1 16 4
PWM cycle register_1 PWCYR_1 16 H'FC06 PWM_1 16 4
PWM buffer register_1A PWBFR_1A 16 H'FC08 PWM_1 16 4
PWM buffer register_1C PWBFR_1C 16 H'FC0A PWM_1 16 4
PWM buffer register_1E PWBFR_1E 16 H'FC0C PWM_1 16 4
PWM buffer register_1G PWBFR_1G 16 H'FC0E PWM_1 16 4
Rev. 2.00, 03/04, page 447 of 508
Register Name
Abbreviation
Number
of Bits
Address*
Module
Data
Bus
Width
Number
of Access
States
PWM control register_2 PWCR_2 8 H'FC10 PWM_2 16 4
PWM output control register_2 PWOCR_2 8 H'FC12 PWM_2 16 4
PWM polarity register_2 PWPR_2 8 H'FC14 PWM_2 16 4
PWM cycle register_2 PWCYR_2 16 H'FC16 PWM_2 16 4
PWM buffer register_2A PWBFR_2A 16 H'FC18 PWM_2 16 4
PWM buffer register_2B PWBFR_2B 16 H'FC1A PWM_2 16 4
PWM buffer register_2C PWBFR_2C 16 H'FC1C PWM_2 16 4
PWM buffer register_2D PWBFR_2D 16 H'FC1E PWM_2 16 4
Port H data direction register PHDDR 8 H'FC20 PORT 16 4
Port J data direction register PJDDR 8 H'FC21 PORT 16 4
Port H data register PHDR 8 H'FC24 PORT 16 4
Port J data register PJDR 8 H'FC25 PORT 16 4
Port H register PORTH 8 H'FC28 PORT 16 4
Port J register PORTJ 8 H'FC29 PORT 16 4
Transport register TRPRT 8 H'FC2E PORT 8 4
LCD port control register LPCR 8 H'FC30 LCD 16 4
LCD control register LCR 8 H'FC31 LCD 16 4
LCD control register 2 LCR2 8 H'FC32 LCD 16 4
Module stop control register D MSTPCRD 8 H'FC60 SYSTEM 8 4
Standby control register SBYCR 8 H'FDE4 SYSTEM 8 2
System control register SYSCR 8 H'FDE5 SYSTEM 8 2
System clock control register SCKCR 8 H'FDE6 SYSTEM 8 2
Mode control register MDCR 8 H'FDE7 SYSTEM 8 2
Module stop control register A MSTPCRA 8 H'FDE8 SYSTEM 8 2
Module stop control register B MSTPCRB 8 H'FDE9 SYSTEM 8 2
Module stop control register C MSTPCRC 8 H'FDEA SYSTEM 8 2
Low-power control register LPWRCR 8 H'FDEC SYSTEM 8 2
IRQ sense control register H ISCRH 8 H'FE12 INT 8 2
IRQ sense control register L ISCRL 8 H'FE13 INT 8 2
IRQ enable register IER 8 H'FE14 INT 8 2
IRQ status register ISR 8 H'FE15 INT 8 2
Rev. 2.00, 03/04, page 448 of 508
Register Name
Abbreviation
Number
of Bits
Address*
Module
Data
Bus
Width
Number
of Access
States
Port 1 data direction register P1DDR 8 H'FE30 PORT 8 2
Port 3 data direction register P3DDR 8 H'FE32 PORT 8 2
Port A data direction register PADDR 8 H'FE39 PORT 8 2
Port B data direction register PBDDR 8 H'FE3A PORT 8 2
Port C data direction register PCDDR 8 H'FE3B PORT 8 2
Port D data direction register PDDDR 8 H'FE3C PORT 8 2
Port F data direction register PFDDR 8 H'FE3E PORT 8 2
Port 3 open drain control register P3ODR 8 H'FE46 PORT 8 2
Port A open drain control register PAODR 8 H'FE47 PORT 8 2
Port B open drain control register PBODR 8 H'FE48 PORT 8 2
Port C open drain control register PCODR 8 H'FE49 PORT 8 2
Timer start register TSTR 8 H'FEB0 TPU 16 2
Timer synchro register TSYR 8 H'FEB1 TPU 16 2
Interrupt priority register A IPRA 8 H'FEC0 INT 8 2
Interrupt priority register B IPRB 8 H'FEC1 INT 8 2
Interrupt priority register C IPRC 8 H'FEC2 INT 8 2
Interrupt priority register D IPRD 8 H'FEC3 INT 8 2
Interrupt priority register E IPRE 8 H'FEC4 INT 8 2
Interrupt priority register F IPRF 8 H'FEC5 INT 8 2
Interrupt priority register G IPRG 8 H'FEC6 INT 8 2
Interrupt priority register J IPRJ 8 H'FEC9 INT 8 2
Interrupt priority register K IPRK 8 H'FECA INT 8 2
Interrupt priority register M IPRM 8 H'FECC INT 8 2
RAM emulation register RAMER 8 H'FEDB FLASH
(F-ZTAT
version)
8 2
Port 1 data register P1DR 8 H'FF00 PORT 8 2
Port 3 data register P3DR 8 H'FF02 PORT 8 2
Port A data register PADR 8 H'FF09 PORT 8 2
Rev. 2.00, 03/04, page 449 of 508
Register Name
Abbreviation
Number
of Bits
Address*
Module
Data
Bus
Width
Number
of Access
States
Port B data register PBDR 8 H'FF0A PORT 8 2
Port C data register PCDR 8 H'FF0B PORT 8 2
Port D data register PDDR 8 H'FF0C PORT 8 2
Port F data register PFDR 8 H'FF0E PORT 8 2
Timer control register_0 TCR_0 8 H'FF10 TPU_0 16 2
Timer mode register_0 TMDR_0 8 H'FF11 TPU_0 16 2
Timer I/O control register H_0 TIORH_0 8 H'FF12 TPU_0 16 2
Timer I/O control register L_0 TIORL_0 8 H'FF13 TPU_0 16 2
Timer interrupt enable register_0 TIER_0 8 H'FF14 TPU_0 16 2
Timer status register_0 TSR_0 8 H'FF15 TPU_0 16 2
Timer counter H_0 TCNTH_0 8 H'FF16 TPU_0 16 2
Timer counter L_0 TCNTL_0 8 H'FF17 TPU_0 16 2
Timer general register AH_0 TGRAH_0 8 H'FF18 TPU_0 16 2
Timer general register AL_0 TGRAL_0 8 H'FF19 TPU_0 16 2
Timer general register BH_0 TGRBH_0 8 H'FF1A TPU_0 16 2
Timer general register BL_0 TGRBL_0 8 H'FF1B TPU_0 16 2
Timer general register CH_0 TGRCH_0 8 H'FF1C TPU_0 16 2
Timer general register CL_0 TGRCL_0 8 H'FF1D TPU_0 16 2
Timer general register DH_0 TGRDH_0 8 H'FF1E TPU_0 16 2
Timer general register DL_0 TGRDL_0 8 H'FF1F TPU_0 16 2
Timer control register_1 TCR_1 8 H'FF20 TPU_1 16 2
Timer mode register_1 TMDR_1 8 H'FF21 TPU_1 16 2
Timer I/O control register_1 TIOR_1 8 H'FF22 TPU_1 16 2
Timer interrupt enable register_1 TIER_1 8 H'FF24 TPU_1 16 2
Timer status register_1 TSR_1 8 H'FF25 TPU_1 16 2
Timer counter H_1 TCNTH_1 8 H'FF26 TPU_1 16 2
Timer counter L_1 TCNTL_1 8 H'FF27 TPU_1 16 2
Timer general register AH_1 TGRAH_1 8 H'FF28 TPU_1 16 2
Timer general register AL_1 TGRAL_1 8 H'FF29 TPU_1 16 2
Timer general register BH_1 TGRBH_1 8 H'FF2A TPU_1 16 2
Timer general register BL_1 TGRBL_1 8 H'FF2B TPU_1 16 2
Timer control register_2 TCR_2 8 H'FF30 TPU_2 16 2
Timer mode register_2 TMDR_2 8 H'FF31 TPU_2 16 2
Rev. 2.00, 03/04, page 450 of 508
Register Name
Abbreviation
Number
of Bits
Address*
Module
Data
Bus
Width
Number
of Access
States
Timer I/O control register_2 TIOR_2 8 H'FF32 TPU_2 16 2
Timer interrupt enable register_2 TIER_2 8 H'FF34 TPU_2 16 2
Timer status register_2 TSR_2 8 H'FF35 TPU_2 16 2
Timer counterH_2 TCNTH_2 8 H'FF36 TPU_2 16 2
Timer counter L_2 TCNTL_2 8 H'FF37 TPU_2 16 2
Timer general register AH_2 TGRAH_2 8 H'FF38 TPU_2 16 2
Timer general register AL_2 TGRAL_2 8 H'FF39 TPU_2 16 2
Timer general register BH_2 TGRBH_2 8 H'FF3A TPU_2 16 2
Timer general register BL_2 TGRBL_2 8 H'FF3B TPU_2 16 2
Timer control/status register_0 TCSR_0 8 H'FF74 WDT_0 16 2
Timer counter_0 TCNT_0 8 H'FF75 WDT_0 16 2
Reset control/status register RSTCSR 8 H'FF77 WDT_0 16 2
Serial mode register_0 SMR_0 8 H'FF78 SCI_0 8 2
Bit rate register_0 BRR_0 8 H'FF79 SCI_0 8 2
Serial control register_0 SCR_0 8 H'FF7A SCI_0 8 2
Transmit data register_0 TDR_0 8 H'FF7B SCI_0 8 2
Serial status register_0 SSR_0 8 H'FF7C SCI_0 8 2
Receive data register_0 RDR_0 8 H'FF7D SCI_0 8 2
Smart card mode register_0 SCMR_0 8 H'FF7E SCI_0 8 2
Serial mode register_1 SMR_1 8 H'FF80 SCI_1 8 2
Bit rate register_1 BRR_1 8 H'FF81 SCI_1 8 2
Serial control register_1 SCR_1 8 H'FF82 SCI_1 8 2
Transmit data register_1 TDR_1 8 H'FF83 SCI_1 8 2
Serial status register_1 SSR_1 8 H'FF84 SCI_1 8 2
Receive data register_1 RDR_1 8 H'FF85 SCI_1 8 2
Smart card mode register_1 SCMR_1 8 H'FF86 SCI_1 8 2
A/D data register AH ADDRAH 8 H'FF90 A/D 8 2
A/D data register AL ADDRAL 8 H'FF91 A/D 8 2
A/D data register BH ADDRBH 8 H'FF92 A/D 8 2
A/D data register BL ADDRBL 8 H'FF93 A/D 8 2
A/D data register CH ADDRCH 8 H'FF94 A/D 8 2
A/D data register CL ADDRCL 8 H'FF95 A/D 8 2
Rev. 2.00, 03/04, page 451 of 508
Register Name
Abbreviation
Number
of Bits
Address*
Module
Data
Bus
Width
Number
of Access
States
A/D data register DH ADDRDH 8 H'FF96 A/D 8 2
A/D data register DL ADDRDL 8 H'FF97 A/D 8 2
A/D control/status register ADCSR 8 H'FF98 A/D 8 2
A/D control register ADCR 8 H'FF99 A/D 8 2
Timer control/status register_1 TCSR_1 8 H'FFA2 WDT_1 16 2
Timer counter_1 TCNT_1 8 H'FFA3 WDT_1 16 2
Flash memory control register 1 FLMCR1 8 H'FFA8 FLASH
(F-ZTAT
version)
8 2
Flash memory control register 2 FLMCR2 8 H'FFA9 FLASH
(F-ZTAT
version)
8 2
Erase block register 1 EBR1 8 H'FFAA FLASH
(F-ZTAT
version)
8 2
Erase block register 2 EBR2 8 H'FFAB FLASH
(F-ZTAT
version)
8 2
Flash memory power control
register
FLPWCR 8 H'FFAC FLASH
(F-ZTAT
version)
8 2
Port 1 register PORT1 8 H'FFB0 PORT 8 2
Port 3 register PORT3 8 H'FFB2 PORT 8 2
Port 4 register PORT4 8 H'FFB3 PORT 8 2
Port A register PORTA 8 H'FFB9 PORT 8 2
Port B register PORTB 8 H'FFBA PORT 8 2
Port C register PORTC 8 H'FFBB PORT 8 2
Port D register PORTD 8 H'FFBC PORT 8 2
Port F register PORTF 8 H'FFBE PORT 8 2
Note: Lower 16 bits of the address.
Rev. 2.00, 03/04, page 452 of 508
20.2 Register Bits
Register bit names of the on-chip peripheral modules are described below.
Each line covers eight bits, and 16-bit registers are shown as 2 lines.
Register
Abbrev.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MCR MCR7 MCR5 MCR2 MCR1 MCR0 HCAN
GSR GSR3 GSR2 GSR1 GSR0
BCR BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0
BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8
MBCR MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1
MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8
TXPR TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1
TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8
TXCR TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1
TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8
TXACK TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1
TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8
ABACK ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1
ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8
RXPR RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0
RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8
RFPR RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0
RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8
IRR IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0
IRR12 IRR9 IRR8
MBIMR MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0
MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8
IMR IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1
IMR12 IMR9 IMR8
REC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TEC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
UMSR UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0
UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8
Rev. 2.00, 03/04, page 453 of 508
Register
Abbrev.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
LAFML LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0 HCAN
LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8
LAFMH LAFMH7 LAFMH6 LAFMH5 LAFMH1 LAFMH0
LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8
MC0[1] DLC3 DLC2 DLC1 DLC0
MC0[2]
MC0[3]
MC0[4]
MC0[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC0[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC0[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC0[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC1[1] DLC3 DLC2 DLC1 DLC0
MC1[2]
MC1[3]
MC1[4]
MC1[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC1[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC1[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC1[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC2[1] DLC3 DLC2 DLC1 DLC0
MC2[2]
MC2[3]
MC2[4]
MC2[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC2[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC2[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC2[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC3[1] DLC3 DLC2 DLC1 DLC0
MC3[2]
MC3[3]
MC3[4]
MC3[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
Rev. 2.00, 03/04, page 454 of 508
Register
Abbrev.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MC3[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 HCAN
MC3[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC3[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC4[1] DLC3 DLC2 DLC1 DLC0
MC4[2]
MC4[3]
MC4[4]
MC4[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC4[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC4[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC4[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC5[1] DLC3 DLC2 DLC1 DLC0
MC5[2]
MC5[3]
MC5[4]
MC5[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC5[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC5[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC5[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC6[1] DLC3 DLC2 DLC1 DLC0
MC6[2]
MC6[3]
MC6[4]
MC6[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC6[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC6[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC6[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC7[1] DLC3 DLC2 DLC1 DLC0
MC7[2]
MC7[3]
MC7[4]
MC7[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC7[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
Rev. 2.00, 03/04, page 455 of 508
Register
Abbrev.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MC7[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 HCAN
MC7[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC8[1] DLC3 DLC2 DLC1 DLC0
MC8[2]
MC8[3]
MC8[4]
MC8[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC8[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC8[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC8[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC9[1] DLC3 DLC2 DLC1 DLC0
MC9[2]
MC9[3]
MC9[4]
MC9[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC9[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC9[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC9[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC10[1] DLC3 DLC2 DLC1 DLC0
MC10[2]
MC10[3]
MC10[4]
MC10[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC10[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC10[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC10[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC11[1] DLC3 DLC2 DLC1 DLC0
MC11[2]
MC11[3]
MC11[4]
MC11[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC11[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC11[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
Rev. 2.00, 03/04, page 456 of 508
Register
Abbrev.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MC11[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 HCAN
MC12[1] DLC3 DLC2 DLC1 DLC0
MC12[2]
MC12[3]
MC12[4]
MC12[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC12[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC12[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC12[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC13[1] DLC3 DLC2 DLC1 DLC0
MC13[2]
MC13[3]
MC13[4]
MC13[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC13[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC13[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC13[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC14[1] DLC3 DLC2 DLC1 DLC0
MC14[2]
MC14[3]
MC14[4]
MC14[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC14[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC14[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC14[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC15[1] DLC3 DLC2 DLC1 DLC0
MC15[2]
MC15[3]
MC15[4]
MC15[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC15[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC15[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC15[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
Rev. 2.00, 03/04, page 457 of 508
Register
Abbrev.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MD0[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 HCAN
MD0[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD0[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD0[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD0[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD0[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD0[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD0[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD1[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD1[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD1[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD1[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD1[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD1[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD1[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD1[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD2[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD2[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD2[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD2[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD2[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD2[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD2[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD2[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD3[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD3[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD3[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD3[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD3[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD3[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD3[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD3[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Rev. 2.00, 03/04, page 458 of 508
Register
Abbrev.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MD4[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 HCAN
MD4[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD4[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD4[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD4[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD4[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD4[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD4[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD5[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD5[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD5[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD5[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD5[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD5[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD5[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD5[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD6[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD6[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD6[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD6[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD6[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD6[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD6[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD6[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD7[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD7[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD7[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD7[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD7[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD7[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD7[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD7[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Rev. 2.00, 03/04, page 459 of 508
Register
Abbrev.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MD8[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 HCAN
MD8[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD8[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD8[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD8[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD8[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD8[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD8[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD9[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD9[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD9[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD9[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD9[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD9[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD9[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD9[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD10[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD10[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD10[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD10[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD10[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD10[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD10[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD10[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD11[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD11[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD11[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD11[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD11[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD11[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD11[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD11[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Rev. 2.00, 03/04, page 460 of 508
Register
Abbrev.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MD12[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 HCAN
MD12[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD12[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD12[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD12[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD12[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD12[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD12[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD13[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD13[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD13[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD13[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD13[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD13[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD13[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD13[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD14[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD14[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD14[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD14[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD14[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD14[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD14[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD14[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD15[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD15[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD15[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD15[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD15[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD15[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD15[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD15[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Rev. 2.00, 03/04, page 461 of 508
Register
Abbrev.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
PWCR_1 IE CMF CST CKS2 CKS1 CKS0 PWM_1
PWOCR_1 OE1H OE1G OE1F OE1E OE1D OE1C OE1B OE1A
PWPR1_ OPS1H OPS1G OPS1F OPS1E OPS1D OPS1C OPS1B OPS1A
PWCYR_1 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWBFR_1A OTS DT9 DT8
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
PWBFR_1C OTS DT9 DT8
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
PWBFR_1E OTS DT9 DT8
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
PWBFR_1G OTS DT9 DT8
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
PWCR_2 IE CMF CST CKS2 CKS1 CKS0 PWM_2
PWOCR_2 OE2H OE2G OE2F OE2E OE2D OE2C OE2B OE2A
PWPR_2 OPS2H OPS2G OPS2F OPS2E OPS2D OPS2C OPS2B OPS2A
PWCYR2 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWBFR_2A TDS DT9 DT8
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
PWBFR_2B TDS DT9 DT8
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
PWBFR_2C TDS DT9 DT8
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
PWBFR_2D TDS DT9 DT8
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
PHDDR PH7DDR PH6DDR PH5DDR PH4DDR PH3DDR PH2DDR PH1DDR PH0DDR PORT
PJDDR PJ7DDR PJ6DDR PJ5DDR PJ4DDR PJ3DDR PJ2DDR PJ1DDR PJ0DDR
PHDR PH7DR PH6DR PH5DR PH4DR PH3DR PH2DR PH1DR PH0DR
PJDR PJ7DR PJ6DR PJ5DR PJ4DR PJ3DR PJ2DR PJ1DR PJ0DR
PORTH PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0
PORTJ PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0
TRPRT TRPB TRPA
Rev. 2.00, 03/04, page 462 of 508
Register
Abbrev.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
LPCR DTS1 DTS0 CMX SGS3 SGS2 SGS1 SGS0 LCD
LCR PSW ACT DISP CKS3 CKS2 CKS1 CKS0
LCR2 LCDAB
MSTPCRD MSTPD7 MSTPD6 SYSTEM
SBYCR SSBY STS2 STS1 STS0
SYSCR INTM1 INTM0 NMIEG RAME
SCKCR PSTOP STCS SCK2 SCK1 SCK0
MDCR MDS2 MDS0
MSTPCRA MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0
MSTPCRC MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
LPWRCR DTON LSON SUBSTP RFCUT STC1 STC0
ISCRH IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA INT
ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
IER IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
ISR IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR PORT
P3DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
PCDDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
PDDDR PD7DDR PD6DDR PD5DDR PD4DDR
PFDDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR
P3ODR P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
PAODR PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR
PBODR PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR
PCODR PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR
TSTR CST2 CST1 CST0
TSYR SYNC2 SYNC1 SYNC0
TPU
common
Rev. 2.00, 03/04, page 463 of 508
Register
Abbrev.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
IPRA IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 INT
IPRB IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
IPRC IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
IPRD IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
IPRE IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
IPRF IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
IPRG IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
IPRJ IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
IPRK IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
IPRM IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
RAMER RAMS RAM2 RAM1 RAM0 FLASH
(F-ZTAT
version)
P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR PORT
P3DR P35DR P34DR P33DR P32DR P31DR P30DR
PADR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR
PBDR PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR
PCDR PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR
PDDR PD7DR PD6DR PD5DR PD4DR
PFDR PF6DR PF5DR PF4DR PF3DR PF2DR
TCR_0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_0
TMDR_0 BFB BFA MD3 MD2 MD1 MD0
TIORH_0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
TIORL_0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0
TIER_0 TTGE TCIEV TGIED TGIEC TGIEB TGIEA
TSR_0 TCFV TGFD TGFC TGFB TGFA
TCNTH_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TCNTL_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRAH_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TGRAL_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRBH_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TGRBL_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRCH_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TGRCL_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Rev. 2.00, 03/04, page 464 of 508
Register
Abbrev.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
TGRDH_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TPU_0
TGRDL_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TCR_1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_1
TMDR_1 MD3 MD2 MD1 MD0
TIOR_1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
TIER_1 TTGE TCIEU TCIEV TGIEB TGIEA
TSR_1 TCFD TCFU TCFV TGFB TGFA
TCNTH_1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TCNTL_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRAH_1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TGRAL_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRBH_1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TGRBL_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TCR_2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_2
TMDR_2 MD3 MD2 MD1 MD0
TIOR_2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
TIER_2 TTGE TCIEU TCIEV TGIEB TGIEA
TSR_2 TCFD TCFU TCFV TGFB TGFA
TCNTH_2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TCNTL_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRAH_2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TGRAL_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRBH_2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TGRBL_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TCSR_0 OVF WT/IT TME CKS2 CKS1 CKS0 WDT_0
TCNT_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RSTCSR WOVF RSTE RSTS
SMR_0*3 C/A CHR PE O/E STOP MP CKS1 CKS0 SCI_0
(GM) (BLK) (PE) (O/E) (BCP1) (BCP0) (CKS1) (CKS0)
BRR_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCR_0 TIE RIE TE RE MPIE TEIE CKE1 CKE0
TDR_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Rev. 2.00, 03/04, page 465 of 508
Register
Abbrev.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
SSR_0*3 TDRE RDRF ORER FER PER TEND MPB MPBT SCI_0
(TDRE) (RDRF) (ORER) (ERS) (PER) (TEND) (MPB) (MPBT)
RDR_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCMR_0 SDIR SINV SMIF
SMR_1*3 C/A CHR PE O/E STOP MP CKS1 CKS0 SCI_1
(GM) (BLK) (PE) (O/E) (BCP1) (BCP0) (CKS1) (CKS0)
BRR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCR_1 TIE RIE TE RE MPIE TEIE CKE1 CKE0
TDR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SSR_1*3 TDRE RDRF ORER FER PER TEND MPB MPBT
(TDRE) (RDRF) (ORER) (ERS) (PER) (TEND) (MPB) (MPBT)
RDR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCMR_1 SDIR SINV SMIF
ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D
ADDRAL AD1 AD0
ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
ADDRBL AD1 AD0
ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
ADDRCL AD1 AD0
ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
ADDRDL AD1 AD0
ADCSR ADF ADIE ADST SCAN CH2 CH1 CH0
ADCR TRGS1 TRGS0 CKS1 CKS0
TCSR_1 OVF WT/IT TME PSS RST/ NMI CKS2 CKS1 CKS0 WDT_1
TCNT_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
FLMCR1 FWE SWE ESU PSU EV PV E P
FLMCR2 FLER
EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
EBR2 EB9 EB8
FLPWCR PDWND
FLASH
(F-ZTAT
version)
Rev. 2.00, 03/04, page 466 of 508
Register
Abbrev.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
PORT1 P17 P16 P15 P14 P13 P12 P11 P10 PORT
PORT3 P35 P34 P33 P32 P31 P30
PORT4 P47 P46 P45 P44 P43 P42 P41 P40
PORTA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
PORTB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
PORTD PD7 PD6 PD5 PD4
PORTF PF7 PF6 PF5 PF4 PF3 PF2
Notes: 1. For buffer operation.
2. For free operation.
3. Some bit functions differ in normal serial communication interface mode and Smart
Card interface mode. The bit functions in Smart Card interface mode are enclosed in
parentheses.
Rev. 2.00, 03/04, page 467 of 508
20.3 Register States in Each Operating Mode
Register
Abbrev.
Reset
High-
Speed
Medium
-Speed
Sleep
Module
Stop
Watch
Subactive
Subsleep
Software
Standby
Hardware
Standby
Module
MCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized HCAN
GSR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
BCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MBCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
TXPR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
TXCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
TXACK Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ABACK Initialized Initialized Initialized Initialized Initialized Initialized Initialized
RXPR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
RFPR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
IRR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MBIMR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
IMR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
REC Initialized Initialized Initialized Initialized Initialized Initialized Initialized
TEC Initialized Initialized Initialized Initialized Initialized Initialized Initialized
UMSR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
LAFML Initialized Initialized Initialized Initialized Initialized Initialized Initialized
LAFMH Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC0[1]
MC0[2]
MC0[3]
MC0[4]
MC0[5]
MC0[6]
MC0[7]
MC0[8]
MC1[1]
MC1[2]
MC1[3]
MC1[4]
MC1[5]
MC1[6]
Rev. 2.00, 03/04, page 468 of 508
Register
Abbrev.
Reset
High-
Speed
Medium
-Speed
Sleep
Module
Stop
Watch
Subactive
Subsleep
Software
Standby
Hardware
Standby
Module
MC1[7] HCAN
MC1[8]
MC2[1]
MC2[2]
MC2[3]
MC2[4]
MC2[5]
MC2[6]
MC2[7]
MC2[8]
MC3[1]
MC3[2]
MC3[3]
MC3[4]
MC3[5]
MC3[6]
MC3[7]
MC3[8]
MC4[1]
MC4[2]
MC4[3]
MC4[4]
MC4[5]
MC4[6]
MC4[7]
MC4[8]
MC5[1]
MC5[2]
MC5[3]
MC5[4]
MC5[5]
MC5[6]
MC5[7]
MC5[8]
Rev. 2.00, 03/04, page 469 of 508
Register
Abbrev.
Reset
High-
Speed
Medium
-Speed
Sleep
Module
Stop
Watch
Subactive
Subsleep
Software
Standby
Hardware
Standby
Module
MC6[1] HCAN
MC6[2]
MC6[3]
MC6[4]
MC6[5]
MC6[6]
MC6[7]
MC6[8]
MC7[1]
MC7[2]
MC7[3]
MC7[4]
MC7[5]
MC7[6]
MC7[7]
MC7[8]
MC8[1]
MC8[2]
MC8[3]
MC8[4]
MC8[5]
MC8[6]
MC8[7]
MC8[8]
MC9[1]
MC9[2]
MC9[3]
MC9[4]
MC9[5]
MC9[6]
MC9[7]
MC9[8]
MC10[1]
Rev. 2.00, 03/04, page 470 of 508
Register
Abbrev.
Reset
High-
Speed
Medium
-Speed
Sleep
Module
Stop
Watch
Subactive
Subsleep
Software
Standby
Hardware
Standby
Module
MC10[2] HCAN
MC10[3]
MC10[4]
MC10[5]
MC10[6]
MC10[7]
MC10[8]
MC11[1]
MC11[2]
MC11[3]
MC11[4]
MC11[5]
MC11[6]
MC11[7]
MC11[8]
MC12[1]
MC12[2]
MC12[3]
MC12[4]
MC12[5]
MC12[6]
MC12[7]
MC12[8]
MC13[1]
MC13[2]
MC13[3]
MC13[4]
MC13[5]
MC13[6]
MC13[7]
MC13[8]
MC14[1]
MC14[2]
Rev. 2.00, 03/04, page 471 of 508
Register
Abbrev.
Reset
High-
Speed
Medium
-Speed
Sleep
Module
Stop
Watch
Subactive
Subsleep
Software
Standby
Hardware
Standby
Module
MC14[3] HCAN
MC14[4]
MC14[5]
MC14[6]
MC14[7]
MC14[8]
MC15[1]
MC15[2]
MC15[3]
MC15[4]
MC15[5]
MC15[6]
MC15[7]
MC15[8]
MD0[1]
MD0[2]
MD0[3]
MD0[4]
MD0[5]
MD0[6]
MD0[7]
MD0[8]
MD1[1]
MD1[2]
MD1[3]
MD1[4]
MD1[5]
MD1[6]
MD1[7]
MD1[8]
MD2[1]
MD2[2]
MD2[3]
Rev. 2.00, 03/04, page 472 of 508
Register
Abbrev.
Reset
High-
Speed
Medium
-Speed
Sleep
Module
Stop
Watch
Subactive
Subsleep
Software
Standby
Hardware
Standby
Module
MD2[4] HCAN
MD2[5]
MD2[6]
MD2[7]
MD2[8]
MD3[1]
MD3[2]
MD3[3]
MD3[4]
MD3[5]
MD3[6]
MD3[7]
MD3[8]
MD4[1]
MD4[2]
MD4[3]
MD4[4]
MD4[5]
MD4[6]
MD4[7]
MD4[8]
MD5[1]
MD5[2]
MD5[3]
MD5[4]
MD5[5]
MD5[6]
MD5[7]
MD5[8]
MD6[1]
MD6[2]
MD6[3]
MD6[4]
Rev. 2.00, 03/04, page 473 of 508
Register
Abbrev.
Reset
High-
Speed
Medium
-Speed
Sleep
Module
Stop
Watch
Subactive
Subsleep
Software
Standby
Hardware
Standby
Module
MD6[5] HCAN
MD6[6]
MD6[7]
MD6[8]
MD7[1]
MD7[2]
MD7[3]
MD7[4]
MD7[5]
MD7[6]
MD7[7]
MD7[8]
MD8[1]
MD8[2]
MD8[3]
MD8[4]
MD8[5]
MD8[6]
MD8[7]
MD8[8]
MD9[1]
MD9[2]
MD9[3]
MD9[4]
MD9[5]
MD9[6]
MD9[7]
MD9[8]
MD10[1]
MD10[2]
MD10[3]
MD10[4]
MD10[5]
Rev. 2.00, 03/04, page 474 of 508
Register
Abbrev.
Reset
High-
Speed
Medium
-Speed
Sleep
Module
Stop
Watch
Subactive
Subsleep
Software
Standby
Hardware
Standby
Module
MD10[6] HCAN
MD10[7]
MD10[8]
MD11[1]
MD11[2]
MD11[3]
MD11[4]
MD11[5]
MD11[6]
MD11[7]
MD11[8]
MD12[1]
MD12[2]
MD12[3]
MD12[4]
MD12[5]
MD12[6]
MD12[7]
MD12[8]
MD13[1]
MD13[2]
MD13[3]
MD13[4]
MD13[5]
MD13[6]
MD13[7]
MD13[8]
MD14[1]
MD14[2]
MD14[3]
MD14[4]
MD14[5]
MD14[6]
Rev. 2.00, 03/04, page 475 of 508
Register
Abbrev.
Reset
High-
Speed
Medium
-Speed
Sleep
Module
Stop
Watch
Subactive
Subsleep
Software
Standby
Hardware
Standby
Module
MD14[7] HCAN
MD14[8]
MD15[1]
MD15[2]
MD15[3]
MD15[4]
MD15[5]
MD15[6]
MD15[7]
MD15[8]
PWCR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWM_1
PWOCR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWPR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWCYR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWBFR_1A Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWBFR_1C Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWBFR_1E Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWBFR_1G Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWCR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWM_2
PWOCR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWPR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWCYR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWBFR_2A Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWBFR_2B Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWBFR_2C Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWBFR_2D Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PHDDR Initialized Initialized PORT
PJDDR Initialized Initialized
PHDR Initialized Initialized
PJDR Initialized Initialized
PORTH Initialized Initialized
PORTJ Initialized Initialized
TRPRT Initialized Initialized
Rev. 2.00, 03/04, page 476 of 508
Register
Abbrev.
Reset
High-
Speed
Medium
-Speed
Sleep
Module
Stop
Watch
Subactive
Subsleep
Software
Standby
Hardware
Standby
Module
LPCR Initialized Initialized LCD
LCR Initialized Initialized
LCR2 Initialized Initialized
MSTPCRD Initialized Initialized SYSTEM
SBYCR Initialized Initialized
SYSCR Initialized Initialized
SCKCR Initialized Initialized
MDCR Initialized Initialized
MSTPCRA Initialized Initialized
MSTPCRB Initialized Initialized
MSTPCRC Initialized Initialized
LPWRCR Initialized Initialized
ISCRH Initialized Initialized INT
ISCRL Initialized Initialized
IER Initialized Initialized
ISR Initialized Initialized
P1DDR Initialized Initialized PORT
P3DDR Initialized Initialized
PADDR Initialized Initialized
PBDDR Initialized Initialized
PCDDR Initialized Initialized
PDDDR Initialized Initialized
PFDDR Initialized Initialized
P3ODR Initialized Initialized
PAODR Initialized Initialized
PBODR Initialized Initialized
PCODR Initialized Initialized
TSTR Initialized Initialized TPU
TSYR Initialized Initialized
IPRA Initialized Initialized INT
IPRB Initialized Initialized
IPRC Initialized Initialized
IPRD Initialized Initialized
Rev. 2.00, 03/04, page 477 of 508
Register
Abbrev.
Reset
High-
Speed
Medium
-Speed
Sleep
Module
Stop
Watch
Subactive
Subsleep
Software
Standby
Hardware
Standby
Module
IPRE Initialized Initialized INT
IPRF Initialized Initialized
IPRG Initialized Initialized
IPRJ Initialized Initialized
IPRK Initialized Initialized
IPRM Initialized Initialized
RAMER Initialized Initialized FLASH
(F-ZTAT
version)
P1DR Initialized Initialized PORT
P3DR Initialized Initialized
PADR Initialized Initialized
PBDR Initialized Initialized
PCDR Initialized Initialized
PDDR Initialized Initialized
PFDR Initialized Initialized
TCR_0 Initialized Initialized TPU_0
TMDR_0 Initialized Initialized
TIORH_0 Initialized Initialized
TIORL_0 Initialized Initialized
TIER_0 Initialized Initialized
TSR_0 Initialized Initialized
TCNTH_0 Initialized Initialized
TCNTL_0 Initialized Initialized
TGRAH_0 Initialized Initialized
TGRAL_0 Initialized Initialized
TGRBH_0 Initialized Initialized
TGRBL_0 Initialized Initialized
TGRCH_0 Initialized Initialized
TGRCL_0 Initialized Initialized
TGRDH_0 Initialized Initialized
TGRDL_0 Initialized Initialized
Rev. 2.00, 03/04, page 478 of 508
Register
Abbrev.
Reset
High-
Speed
Medium
-Speed
Sleep
Module
Stop
Watch
Subactive
Subsleep
Software
Standby
Hardware
Standby
Module
TCR_1 Initialized Initialized TPU_1
TMDR_1 Initialized Initialized
TIOR_1 Initialized Initialized
TIER_1 Initialized Initialized
TSR_1 Initialized Initialized
TCNTH_1 Initialized Initialized
TCNTL_1 Initialized Initialized
TGRAH_1 Initialized Initialized
TGRAL_1 Initialized Initialized
TIOR_2 Initialized Initialized
TIER_2 Initialized Initialized
TSR_2 Initialized Initialized
TCNTH_2 Initialized Initialized
TCNTL_2 Initialized Initialized
TGRAH_2 Initialized Initialized
TGRAL_2 Initialized Initialized
TGRBH_2 Initialized Initialized
TGRBL_2 Initialized Initialized
TCSR_0 Initialized Initialized WDT_0
TCNT_0 Initialized Initialized
RSTCSR Initialized Initialized
SMR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_0
BRR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SCR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
TDR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SSR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
RDR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SCMR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SMR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_1
BRR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SCR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
TDR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SSR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Rev. 2.00, 03/04, page 479 of 508
Register
Abbrev.
Reset
High-
Speed
Medium
-Speed
Sleep
Module
Stop
Watch
Subactive
Subsleep
Software
Standby
Hardware
Standby
Module
RDR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_1
SCMR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ADDRAH Initialized Initialized Initialized Initialized Initialized Initialized Initialized A/D
ADDRAL Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ADDRBH Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ADDRBL Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ADDRCH Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ADDRCL Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ADDRDH Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ADDRDL Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ADCSR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ADCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
TCSR_1 Initialized Initialized WDT_1
TCNT_1 Initialized Initialized
FLMCR1 Initialized Initialized
FLMCR2 Initialized Initialized
EBR1 Initialized Initialized
EBR2 Initialized Initialized
FLPWCR Initialized Initialized
FLASH
(F-ZTAT
version)
PORT1 PORT
PORT3
PORT4
PORTA
PORTB
PORTC
PORTD
PORTF
Note: is not initialized.
Rev. 2.00, 03/04, page 480 of 508
Rev. 2.00, 03/04, page 481 of 508
Section 21 Electrical Characteristics
21.1 Absolute Maximum Ratings
Table 21.1 lists the absolute maximum ratings.
Table 21.1 Absolute Maximum Ratings
Item Symbol Value Unit
Power supply voltage VCC, LPVCC –0.3 to +7.0 V
PWMVCC –0.3 to +7.0 V
Input voltage (XTAL, EXTAL) Vin –0.3 to VCC + 0.3 V
Input voltage (port 4) Vin –0.3 to AVCC +0.3 V
Input voltage (except XTAL,
EXTAL, and port 4)
Vin –0.3 to VCC +0.3 V
Input voltage (ports H and J) Vin –0.3 to PWMVCC +0.3 V
Analog power supply voltage AVCC –0.3 to +7.0 V
Analog input voltage VAN –0.3 to AVCC +0.3 V
Operating temperature Topr Regular specifications: –20 to +75 °C
Wide-range specifications: –40 to +85 °C
Storage temperature Tstg –55 to +125 °C
Caution: Permanent damage to this LSI may result if absolute maximum rating are exceeded.
Rev. 2.00, 03/04, page 482 of 508
21.2 DC Characteristics
Table 21.2 lists the DC characteristics. Table 21.3 lists the permissible out p ut curre nt s.
Table 21.2 DC Char acteristics
Conditions: VCC = LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
VSS = AVSS = PWMVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)*1
Item
Symbol
Min.
Typ.
Max.
Unit Test
Conditions
VT
– V
CC × 0.2 V
VT
+ V
CC × 0.7 V
Schmitt
trigger input
voltage
IRQ0 to IRQ5,
ports 1, 3,
A to D, F, H, J VT
+ – VT
– V
CC × 0.05 V
Input high
voltage
RES, STBY,
NMI,
MD2, MD0,
FWE
VIH V
CC × 0.9 V
CC + 0.3 V
EXTAL VCC × 0.7 V
CC + 0.3 V
SCK0, SCK1,
RxD0, RxD1,
HRxD
V
CC × 0.7 V
CC + 0.3 V
Port 4 AVCC × 0.7 AVCC + 0.3 V
Input low
voltage
RES, STBY,
NMI,
MD2, MD0,
FWE
VIL –0.3 V
CC × 0.1 V
EXTAL –0.3 V
CC × 0.2 V
SCK0, SCK1,
RxD0, RxD1,
HRxD
–0.3 V
CC × 0.2 V
Port 4 –0.3 AVCC × 0.2 V
VCC – 0.5 V IOH = –200
µA
Output high
voltage
All output pins VOH
VCC – 1.0 V IOH = –1 mA
Output low
voltage
All output pins VOL 0.4 V IOL = 1.6 mA
Rev. 2.00, 03/04, page 483 of 508
Item
Symbol
Min.
Typ.
Max.
Unit Test
Conditions
RES | Iin | 1.0 µA Vin = 0.5 to Input
leakage
current
STBY, NMI,
MD2, MD0,
FWE, HRxD
1.0 µA VCC – 0.5 V
Port 4 1.0 µA Vin = 0.5 to
AVCC – 0.5 V
Other than
above ports
1.0 µA Vin = 0.5 to
VCC – 0.5 V
RES C
in 30 pF Vin = 0 V
NMI 30 pF f = 1 MHz
Input
capacitance
All input pins
except RES
and NMI
15 pF Ta = 25°C
Current
dissipation*2
Normal
operation
ICC*3 45
(VCC = 5.0 V)
55
(VCC = 5.5 V)
mA f = 20 MHz
Sleep mode 35
(VCC = 5.0 V)
45
(VCC = 5.5 V)
mA f = 20 MHz
All modules
stopped
30 mA f = 20 MHz,
VCC = 5.0 V
(reference
values)
Medium-speed
mode (φ/32)
30 mA f = 20 MHz,
VCC = 5.0 V
(reference
values)
Subactive
mode
0.7 1.0 mA Using the
subclock
Subsleep
mode
0.7 1.0 mA Using the
subclock
Watch mode 0.6 1.0 mA Using the
subclock
2 5.0 µA Ta ≤ 50°C
Standby mode
20 µA 50°C < Ta
Operating LPICC 10 20 mA
0.1 10 µA Ta ≤ 50°C
LCD power-
supply port
power supply
current
In standby
mode 80 µA 50°C < Ta
During A/D
conversion
AlCC 2.5 4.0 mA AVCC = 5.0 VAnalog
power supply
current Idle 5.0 µA
RAM standby voltage VRAM 2.0 V
Rev. 2.00, 03/04, page 484 of 508
Notes: 1. If the A/D converter is not used, do not leave the AVCC and AVSS pins open. Apply a
voltage between 4.5 V and 5.5 V to the AVCC pin by connecting them to VCC, for
instance.
2. Current dissipation values are for VIH = VCC (EXTAL), AVCC (port 4), PWMVCC, LPVCC, or
VCC (other), and VIL = 0 V, with all output pins unloaded.
3. ICC depends on VCC and f as follows:
I
CC max = 22 + 0.3 × VCC × f (normal operation)
I
CC max = 18 + 0.25 × VCC × f (sleep mode)
Table 21.3 Permissible Output Currents
Conditions: VCC = LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
VSS = AVSS = PWMVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)*1
Item Symbol Min. Typ. Max. Unit Test Conditions
All output pins except
PWM1A to 1H and
PWM2A to 2H
IOL 10 mA
25 mA Ta = 75 to 85°C
30 mA Ta = 25°C
Permissible
output low
current (per pin)
PWM1A to 1H,
PWM2A to 2H
IOL
40 mA Ta = –40°C
Total of all output pins
except PWM1A to 1H
and PWM2A to 2H
ΣIOL 80 mA
150 mA Ta = 75 to 85°C
180 mA Ta = 25°C
Permissible
output low
current (total)
Total of PWM1A to
1H and PWM2A to 2H
ΣIOL
220 mA Ta = –40°C
All output pins except
PWM1A to 1H and
PWM2A to 2H
–IOH 2.0 mA
25 mA Ta = 75 to 85°C
30 mA Ta = 25°C
Permissible
output high
current (per pin)
PWM1A to 1H,
PWM2A to 2H
–IOH
40 mA Ta = –40°C
Total of all output pins
except PWM1A to 1H
and PWM2A to 2H
Σ–IOH 40 mA
150 mA Ta = 75 to 85°C
180 mA Ta = 25°C
Permissible
output high
current (total)
Total of PWM1A to
1H and PWM2A to 2H
Σ–IOH
220 mA Ta = –40°C
Note: To protect chip reliability, do not exceed the output current values in table 21.3.
Rev. 2.00, 03/04, page 485 of 508
21.3 AC Characteristics
Figure 21.1 shows the test cond itions for the AC characteristics.
5 V
R
L
R
H
C
LSI output pin
C = 30pF: All ports
R
L
= 2.4 kΩ
R
H
= 12 Ω
Input/output timing measurement levels
• Low level : 0.8 V
• High level : 2.0 V
Figure 21.1 Output Load Circuit
21.3.1 Clock Timing
Table 21.4 lists the clock timing
Table 21.4 Clock Timi ng
Conditions : VCC = LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
VSS = AVSS = PWMVSS = PLLVSS = 0 V, φ = 4 MHz to 20 MHz,
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Item Symbol Min. Max. Unit Test Conditions
Clock cycle time tcyc 50 250 ns Figure 21.2
Clock high pulse width tCH 15 ns
Clock low pulse width tCL 15 ns
Clock rise time tCr 5 ns
Clock fall time tCf 5 ns
Oscillation stabilization time at
reset (crystal)
tOSC1 20 ms Figure 21.3
Oscillation stabilization time in
software standby (crystal)
tOSC2 8 ms Figure 19.3
External clock output
stabilization delay time
tDEXT 2 ms Figure 21.3
Rev. 2.00, 03/04, page 486 of 508
t
Cr
t
CL
t
Cf
t
CH
φ
t
cyc
Figure 21.2 System Clock Timing
t
OSC1
t
OSC1
EXTAL
VCC
φ
tDEXT tDEXT
Figure 21.3 Oscillation Stabi l iz ation Timing
Rev. 2.00, 03/04, page 487 of 508
21.3.2 Control Signal Timing
Table 21.5 lists the control signal timing.
Table 21.5 Control Signal Timing
Conditions: VCC = LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
VSS = AVSS = PWMVSS = PLLVSS = 0 V, φ = 4 MHz to 20 MHz,
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Item Symbol Min. Max. Unit Test Conditions
RES setup time tRESS 200 ns Figure 21.4
RES pulse width tRESW 20 t
cyc
NMI setup time tNMIS 150 ns Figure 21.5
NMI hold time tNMIH 10 ns
NMI pulse width (exiting
software standby mode)
tNMIW 200 ns
IRQ setup time tIRQS 150 ns
IRQ hold time tIRQH 10 ns
IRQ pulse width (exiting
software standby mode)
tIRQW 200 ns
t
RESW
t
RESS
φ
t
RESS
Figure 21.4 Reset Input Timing
Rev. 2.00, 03/04, page 488 of 508
φ
tIRQS
Edge input
tIRQH
tNMIS tNMIH
tIRQS
Level input
NMI
tNMIW
tIRQW
Figure 21.5 Interrupt Input Timing
Rev. 2.00, 03/04, page 489 of 508
21.3.3 Timing of On-Chip Supporting Modules
Table 21.6 lists the timing of on-chip supporting modules.
Table 21.6 Timing of On-Chip Supporting Modules
Conditions : VCC = LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
VSS = AVSS = PWMVSS = PLLVSS = 0 V, φ = 4 MHz to 20 MHz,
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Item Symbol Min. Max. Unit Test Conditions
I/O port Output data delay time tPWD 50 ns Figure 21.6
Input data setup time tPRS 30
Input data hold time tPRH 30
TPU Timer output delay
time
tTOCD 50 ns Figure 21.7
Timer input setup time tTICS 30
Timer clock input setup
time
tTCKS 30 ns Figure 21.8
Timer
clock
Single edge tTCKWH 1.5 t
cyc
pulse
width
Both edges tTCKWL 2.5
SCI Input
clock
Asynchronous tScyc 4 t
cyc Figure 21.9
cycle Synchronous 6
Input clock pulse width tSCKW 0.4 0.6 tScyc
Input clock rise time tSCKr 1.5 tcyc
Input clock fall time tSCKf 1.5
Transmit data delay
time
tTXD 50 ns Figure 21.10
Receive data setup
time (synchronous)
tRXS 50
Receive data hold time
(synchronous)
tRXH 50
Rev. 2.00, 03/04, page 490 of 508
Item Symbol Min. Max. Unit Test Conditions
A/D
converter
Trigger input setup
time
tTRGS 30 ns Figure 21.11
HCAN* Transmit data delay
time
tHTXD 100 ns Figure 21.12
Receive data setup
time
tHRXS 100
Receive data hold time tHRXH 100
PWM Pulse output delay time tMPWMOD 50 ns Figure 21.13
Note: * The HCAN input signal is asynchronous. However, its state is judged to have changed
at the rising-edge (two clock cycles) of the system clock signal (φ) shown in figure
21.12. The HCAN output signal is also asynchronous. Its state changes are based on
the rising-edge (two clock cycles) of the system clock signal (φ) shown in figure 21.12.
φ
Port 1, 3, 4
A to D, F, H, J (read)
tPRS
T1T2
tPWD
tPRH
Port 1, 3, A to D, F,
H, J (write)
φ
Port H, J (read)
tPRS
T1T2
tPWD
tPRH
Port H, J (write)
T3T4
Figure 21.6 I/O Port Input/Output Timing
Rev. 2.00, 03/04, page 491 of 508
φ
tTICS
tTOCD
Output compare
output*
Input capture
input*
Note : * TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, TIOCD0
Figure 21.7 TPU Input/Output Timing
tTCKS
φ
tTCKS
TCLKA to TCLKD
tTCKWH
tTCKWL
Figure 21.8 TPU Clock Input Timing
t
Scyc
t
SCKr
t
SCKW
SCK0, SCK1
t
SCKf
Figure 21.9 SCK Clock Input Timing
Rev. 2.00, 03/04, page 492 of 508
SCK0, SCK1
TxD0, TxD1
(transmit data)
RxD0, RxD1
(receive data)
t
TXD
t
RXH
t
RXS
Figure 21.10 SCI Input/Output Timing (Clock Synchronous Mode)
φ
t
TRGS
Figure 21.11 A/D Converter External Trigger Input Timing
φ
HTxD
(transmit data)
HRxD
(receive data)
t
HTXD
t
HRXS
t
HRXH
Figure 21.12 HCAN Input/Output Timing
PWM1A to PWM1H,
PWM2A to PWM2H
t
MPWMOD
Figure 21.13 Motor Control PWM Output Timing
Rev. 2.00, 03/04, page 493 of 508
21.4 A/D Conversion Characteristics
Table 21.7 lists the A/D conversion characteristics.
Table 21.7 A/D Conversion Characteristics
Conditions : VCC = LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
VSS = AVSS = PWMVSS = PLLVSS = 0 V, φ = 4 MHz to 20 MHz,
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Item Min. Typ. Max. Unit
Resolution 10 10 10 bits
Conversion time 10 200 µs
Analog input capacitance 20 pF
Permissible signal-source impedance 5 kΩ
Nonlinearity error ±3.5 LSB
Offset error ±3.5 LSB
Full-scale error ±3.5 LSB
Quantization ±0.5 LSB
Absolute accuracy ±4.0 LSB
Rev. 2.00, 03/04, page 494 of 508
21.5 Flash Memory Characteristics
Table 21.8 lists the flash memory characteristics.
Table 21.8 Flash Mem or y Ch aracteristics
Conditions: VCC = PWMVCC = LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V,
VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = 0 to +75°C (Programming/erasing
operating temperature range: regular specifications)
Item
Symbol
Min.
Typ.
Max.
Unit Test
Condition
Programming time*1, *2, *4 t
P 10 200 ms/128 bytes
Erase time*1, *3, *5 t
E 100 1200 ms/block
Reprogramming count NWEC 100 Times
Programming Wait time after SWE bit setting*1 t
sswe 1 1 µs
Wait time after PSU bit setting*1 t
spsu 50 50 µs
Wait time after P bit setting*1, *4 t
sp30 28 30 32 µs Programming
time wait
t
sp200 198 200 202 µs Programming
time wait
t
sp10 8 10 12 µs Additional-
programming
time wait
Wait time after P bit clear*1 t
cp 5 5 µs
Wait time after PSU bit clear*1 t
cpsu 5 5 µs
Wait time after PV bit setting*1 t
spv 4 4 µs
Wait time after H'FF dummy write*1tspvr 2 2 µs
Wait time after PV bit clear*1 t
cpv 2 2 µs
Wait time after SWE bit clear*1 t
cswe 100 100 µs
Maximum programming count*1, *4 N 1000 Times
Erase Wait time after SWE bit setting*1 t
sswe 1 1 µs
Wait time after ESU bit setting*1 t
sesu 100 100 µs
Wait time after E bit setting*1, *5 t
se 10 10 100 ms Erase time
wait
Wait time after E bit clear*1 t
ce 10 10 µs
Wait time after ESU bit clear*1 t
cesu 10 10 µs
Wait time after EV bit setting*1 t
sev 20 20 µs
Wait time after H'FF dummy write*1tsevr 2 2 µs
Wait time after EV bit clear*1 t
cev 4 4 µs
Wait time after SWE bit clear*1 t
cswe 100 100 µs
Maximum erase count*1, *5 N 12 120 Times
Rev. 2.00, 03/04, page 495 of 508
Notes: 1. Follow the program/erase algorithms when making the time settings.
2. Programming time per 128 bytes. (Indicates the total time during which the P bit is set
in flash memory control register 1 (FLMCR1). Does not include the program-verify
time.)
3. Time to erase one block. (Indicates the total time during which the E bit is set in
FLMCR1. Does not include the erase-verify time.)
4. To specify the maximum programming time value (tp (max)) in the 128-byte
programming algorithm, set the max. value (1000) for the maximum programming count
(N).
The wait time after P bit setting should be changed as follows according to the value of
the programming counter (n).
Programming counter (n) = 1 to 6: tsp30 = 30 µs
Programming counter (n) = 7 to 1000: tsp200 = 200 µs
(Additional programming)
Programming counter (n) = 1 to 6: tsp10 = 10 µs
5. For the maximum erase time (tE(max)), the following relationship applies between the
wait time after E bit setting (tse) and the maximum erase count (N):
t
E(max) = Wait time after E bit setting (tse) x maximum erase count (N)
To set the maximum erase time, the values of (tse) and (N) should be set so as to satisfy
the above formula.
Examples: When tse = 100 ms, N = 12 times
When tse = 10 ms, N = 120 times
Rev. 2.00, 03/04, page 496 of 508
21.6 LCD Characteristics
Table 21.9 lists the LCD characteristics.
Table 21.9 LCD Char act eristi c s
Conditions: VCC = LPVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
VSS = AVSS = PWMVSS = PLLVSS = 0 V, Ta = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-range specifications)*1
Item
Symbol
Pins Test
Condition
Min.
Typ.
Max.
Unit
Remarks
Segment driver
step-down voltage
VDS SEG1 to
SEG28
ID = 2 µA 0.6 V *1
Common driver
step-down voltage
VDC COM1 to
COM4
ID = 2 µA 0.3 V *1
LCD power-supply
split-resistance
RLCD V1 to VSS 40 300 1000 kΩ
LCD voltage VLCD V1 4.5 LPVCC V *2
Notes: 1 The value shows the step-down voltage from the power-supply pins V1, V2, V3, and
Vss to the respective segment pin or common pin.
2 When the LCD voltage is supplied externally, the following relation should be
maintained: LPVcc ≥ V1 ≥ V2 ≥ V3 ≥ Vss.
Rev. 2.00, 03/04, page 497 of 508
Appendix
A. I/O Port States in Each Pin State
Port Name
MCU
Operating
Mode
Reset
Hardware
Standby
Mode
Software
Standby
Mode
Subactive
Mode
Program
Execution
State Sleep
Mode
Port 1 7 T T Keep I/O port I/O port
Port 3 7 T T Keep I/O port I/O port
Port 4 7 T T T Input port Input port
Port A 7 T T Keep I/O port I/O port
Port B 7 T T Keep I/O port I/O port
Port C 7 T T Keep I/O port I/O port
Port D 7 T T Keep I/O port I/O port
PF7 7 T T [DDR = 0]
T
[DDR = 1]
H
[DDR = 0]
T
[DDR = 1]
H
[DDR = 0]
T
[DDR = 1]
Clock output
PF6
PF5
PF4
PF3
PF2
PF0
7 T T Keep I/O port I/O port
Port H 7 T T Keep I/O port I/O port
Port J 7 T T Keep I/O port I/O port
HTxD 7 H T H H Output
HRxD 7 Input T T T Input
[Legend]
H: High level
T: High impedance
Keep: Input port becomes high-impedance, output port retains state
Rev. 2.00, 03/04, page 498 of 508
B. Product Lineup
Product Type Name Model Marking Package (Code)
H8S/2282 F-ZTAT version HD64F2282 HD64F2282 100-pin QFP (FP-100A)
Mask ROM version HD6432282 HD6432282(***) 100-pin QFP (FP-100A)
H8S/2281 Mask ROM version HD6432281 HD6432281(***) 100-pin QFP (FP-100A)
[Legend]
(***): ROM code
Note: The above products include those under development or being planned. For the status of
each product, contact your nearest Renesas Technology sales office.
C. Package Dimensions
The package dimension th at is shown in the Renesas Semiconductor Package Data Book has
priority.
Package Code
JEDEC
EIAJ
Mass
(reference value)
FP-100A
-
-
1.7 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
0.13 M
0˚ - 10˚
*
0.32 ± 0.08
*0.17 ± 0.05
3.10 Max
1.2 ± 0.2
24.8 ± 0.4
20
80 51
50
31
30
1
100
81
18.8 ± 0.4
14
0.15
0.65
2.70
2.4
0.20
+0.10
- 0.20
0.58 0.83
0.30 ± 0.06
0.15 ± 0.04
Figure C.1 FP-100A Package Dimensions
Rev. 2.00, 03/04, page 499 of 508
Main Revisions and Additions in this Edition
Item Page Revisions (See Manual for Details)
Bit Bit Name Description
15 IRR7 Overload Frame Interrupt Flag
[Setting condition]
• When an overload frame is
transmitted in error active/passive
state
[Clearing condition]
• Writing 1
11.3.11 Interrupt Register
(IRR)
291
Bit Bit Name Description
15 IMR7 Overload Frame Interrupt Mask
When this bit is cleared to 0, OVR0
(interrupt request by IRR7) is
enabled. When set to 1, OVR0 is
masked.
11.3.13 Interrupt Mask
Register (IMR)
295
11.3.16 Unread Message
Status Register (UMSR)
297 Symbols of bits 15 to 0 in R/W column switched from R/W to
R/(W)*
Note: * Only 1 is writable to clear the flag
Figure 11.7 Software Reset
Flowchart
305
MCR0 = 0
GSR3 = 0?
Yes
No
OK?
GSR3 = 1? No
Yes
Rev. 2.00, 03/04, page 500 of 508
Item Page Revisions (See Manual for Details)
Table 11.2 Limits for the
Settable Value
306 Notes: 1. SJW is stipulated in the CAN specifications:
3 ≥ SJW ≥ 0
2. The minimum value of TSEG2 is stipulated in the
CAN specifications:
TSEG2 ≥ SJW
3. The minimum value of TSEG1 is stipulated in the
CAN specifications:
TSEG1 > TSEG2
Table 11.3 Setting Range
for TSEG1 and TSEG2 in
BCR
307 TQ values deleted
Figure 11.13 HCAN Sleep
Mode Flowchart
316
IRR12 = 1
Yes
MCR5 = 0
Yes
Clear sleep mode?
Yes
No
No
No
Yes (manual)
No (automatic)
MCR5 = 1
Bus idle?
Initialize TEC and REC
Bus operation?
: Settings by user
: Processing by hardware
No
IMR12 = 1?
Sleep mode clearing method
MCR7 = 0?
Yes
No
GSR3 = 1?
Yes
No
GSR3 = 1?
CPU interrupt
Do not access MB
during this sequence
MCR5 = 0
Rev. 2.00, 03/04, page 501 of 508
Item Page Revisions (See Manual for Details)
Name Description Interrupt Flag
Error passive interrupt
(TEC ≥ 128 or REC ≥ 128)
IRR5
ERS0/OVR0
Overload frame
transmission interrupt
IRR7
Table 11.4 HCAN Interrupt
Sources
319
11.7.5 Error Counters 321 Shadowed part below is deleted.
In the case of error active and error passive, REC and TEC
normally count up and down. In the bus-off state, 11-bit
recessive sequences are counted (REC + 1) using REC. If
REC reaches 96 during the count, IRR4 and GSR1 are set,
and if REC reaches 128, IRR7 is set.
11.7.10 HCAN TXCR
Operation
322 Added
11.7.11 HCAN Transmit
Procedure
11.7.12 Note on Releasing
the HCAN Software Reset
and HCAN Sleep
11.7.13 Note on Accessing
Mailbox during the HCAN
Sleep
323 Added
12.3.1 A/D Data Registers
A to D (ADDRA to ADDRD)
328 Shadowed part added
The data bus between the CPU and the A/D converter is 8 bits
wide. The upper byte can be read directly from the CPU,
however the lower byte should be read via a temporary
register. The temporary register contents are transferred from
the ADDR when the upper byte data is read. When reading the
ADDR, read the upper byte before the lower byte, or read in
word unit. Reading the lower bytes alone does not guarantee
the contents.
14.3.1 LCD Port Control
Register (LPCR)
363 The symbol of bit 4 in column of R/W is switched from " — " to
" R/W ".
Bit Bit Name Description
4 to 0 Reserved
These bits should only be written
with 0.
14.3.3 LCD Control
Register 2 (LCR2)
366
Rev. 2.00, 03/04, page 502 of 508
Item Page Revisions (See Manual for Details)
14.4.2 Relationship
between LCD RAM and
Display
372 A term added
Output Levels (A Waveform)
14.4.3 Operation in Power-
Down Modes
372 More explanation on the subclock and LCD display is added
RAM Address
H'FFE000 to H'FFEFBF, H'FFFFC0 to H'FFFFFF
H'FFE000 to H'FFEFBF, H'FFFFC0 to H'FFFFFF
H'FFE000 to H'FFEFBF, H'FFFFC0 to H'FFFFFF
Section 15 RAM 375
17.1 Note on Switching
from F-ZTAT Version to
Masked ROM Version
402 This section added
Bit Bit Name Description
3 RFCUT Oscillation Circuit Feedback
Resistance Control
0: When the main clock is
oscillating, sets the feedback
resistance ON. When the main
clock is stopped, sets the
feedback resistance OFF.
1: Sets the feedback resistance
OFF. Modification becomes
valid after returning to software
standby transfer.
Note: With a crystal resonator,
the resonator will not
operate if this bit is set to 1.
18.1.2 Low-Power Control
Register (LPWRCR)
406
Row of subclock oscillator deleted
Function Watch Subactive Subsleep
System clock
pulse generator
Functioning Functioning Functioning
Table 19.2 LSI Internal
States in Each Mode
416
19.4.3 Setting Oscillation
Stabilization Time after
Clearing Software Standby
Mode
426 Below note added
Note: * Do not use this setting
Rev. 2.00, 03/04, page 503 of 508
Item Page Revisions (See Manual for Details)
20.3 Register States in
Each Operating Mode
"Initialized" marks in message control (MC) and message data
(MD) deleted
Item Symbol Max. Unit
Test
Conditions
Input
leakage
current
Other than
above
ports
| Iin | 1.0 µA Vin = 0.5 to
VCC – 0.5 V
21.2 DC Characteristics 483
Table 21.2 DC
Characteristics
483 Some typ. and max. values of power dissipation specified,
ICC max equations modified
Table 21.3 Permissible
Output Currents
484 Values in column of max. specified
Item Max.
Transmit data delay time 100
Receive data setup time
HCAN*
Receive data hold time
PWM Pulse output delay time 50
Table 21.6 Timing of On-
Chip Supporting Modules
489
Rev. 2.00, 03/04, page 504 of 508
Rev. 2.00, 03/04, page 505 of 508
Index
16-Bit Timer Pulse Unit (TPU) .............. 131
Buffer Operation.................................166
Buffer Operation Timing.................... 186
Counter Operation .............................. 158
Input Capture Function....................... 162
Input Capture Signal Timing .............. 184
Output Compare Output Timing......... 184
Phase Counting Mode......................... 174
PWM Modes....................................... 169
Synchronous Operation ...................... 164
TCNT Count Timing .......................... 183
Waveform Output
by Compare Match ............................. 160
A/D Converter........................................ 325
A/D Conversion Time......................... 333
Analog Input Channel......................... 328
External Trigger.................................. 335
Scan Mode.......................................... 332
Single Mode........................................ 332
Address Map............................................. 50
Address Space........................................... 18
Addressing Modes.................................... 39
Absolute Address .................................. 40
Immediate............................................. 41
Memory Indirect................................... 41
Program-Counter Relative.................... 41
Register Direct...................................... 39
Register Indirect ...................................39
Register Indirect with Displacement..... 39
Register indirect with post-increment... 40
Register indirect with pre-decrement....40
Bcc............................................................ 35
bus cycle................................................... 83
Clock Pulse Generator............................ 403
Condition Field......................................... 38
Condition-Code Register (CCR)............... 22
Controller Area Network (HCAN)..........277
CAN Bus Interface..............................320
Hardware Reset...................................303
HCAN Halt Mode...............................318
HCAN Sleep Mode.............................315
Message Reception .............................312
Message Transmission........................309
Software Reset....................................303
data direction register (DDR)....................87
data register (DR)......................................87
Effective Address................................39, 42
Effective Address Extension.....................38
Exception Handling ..................................51
Interrupts...............................................56
Reset Exception Handling .....................53
Stack Status...........................................58
Traces....................................................56
Trap Instruction .....................................57
Exception Handling Vector Table .............52
Extended Control Register (EXR) ............21
flash memory ..........................................377
Boot Mode ..........................................388
Emulation............................................391
Erase/Erase-Verify..............................395
erasing units........................................382
Program/Program-Verify....................393
User Program Mode............................390
General Registers......................................20
IC card (Smart Card) interface........215, 262
Instruction Set...........................................27
Arithmetic Operations Instructions.......30
Bit Manipulation Instructions ...............33
Block Data Transfer Instructions..........37
Branch Instruc tions...............................35
Data Transfer Instructions.....................29
Rev. 2.00, 03/04, page 506 of 508
Logic Operations Instructions............... 32
Shift Instructions .................................. 32
System Control Instructions ................. 36
Interrupt
ADI..................................................... 335
CMI .................................................... 358
ERI...................................................... 273
ERS0................................................... 319
NMI...................................................... 69
OVR0.................................................. 319
RM0.................................................... 319
RM1.................................................... 319
RXI..................................................... 273
SLE0................................................... 319
TCI...................................................... 181
TEI...................................................... 273
TGI ..................................................... 181
TXI ..................................................... 273
WOVI................................................. 211
Interrupt Control Modes........................... 73
Interrupt Controller................................... 61
Interrupt Excep tion Handling
Vector Table............................................. 70
Interrupt Mask Bit .................................... 22
LCD Controller/Driver (LCD) ................ 361
Common Drivers................................ 364
Duty Cycle.......................................... 361
LCD Display....................................... 367
LCD RAM.......................................... 368
Segment Drivers................................. 364
memory cycle ........................................... 83
Motor Control PWM Timer (PWM)....... 341
PWM Channel 1................................. 356
PWM Channel 2................................. 357
On-Board Programming Modes ............. 387
open-drain control register (ODR)............ 87
Operating Mode Selection........................ 47
Operation Field......................................... 38
Power-Down Modes............................... 413
Direct Transitions ...............................434
Hardware Standby Mode ....................428
Medium-Speed Mode..........................423
Module Stop Mode .............................430
Sleep Mode.........................................424
Software Standby Mode......................425
Subactive Mode ..................................433
Subsleep Mode....................................432
Watch Mode........................................431
Program Counter (PC)..............................21
Program/Erase Protection .......................397
Programmer Mode..................................398
Register Field............................................38
Registers
ABACK ...................... 288, 438, 452, 467
ADCR......................... 331, 451, 465, 479
ADCSR....................... 329, 451, 465, 479
ADDR......................... 328, 450, 465, 479
BCR ............................ 282, 438, 452, 467
BRR ............................ 230, 450, 464, 478
EBR1........................... 385, 451, 465, 479
EBR2........................... 386, 451, 465, 479
FLMCR1..................... 384, 451, 465, 479
FLMCR2..................... 385, 451, 465, 479
FLPWCR .................... 387, 451, 465, 479
GSR.............................281, 438, 452, 467
IER................................ 65, 447, 462, 476
IMR............................. 295, 438, 452, 467
IPR................................ 64, 448, 463, 476
IRR.............................. 291, 438, 452, 467
ISCR .............................66, 447, 462, 476
ISR................................ 68, 447, 462, 476
LAFM......................... 298, 438, 453, 467
LCR............................. 365, 447, 462, 476
LCR2........................... 366, 447, 462, 476
LPCR .......................... 363, 447, 462, 476
LPWRCR.................... 419, 447, 462, 476
MBCR......................... 284, 438, 452, 467
MBIMR....................... 294, 438, 452, 467
MC.............................. 300, 438, 453, 467
MCR ........................... 280, 438, 452, 467
MD.............................. 302, 442, 457, 471
Rev. 2.00, 03/04, page 507 of 508
MDCR .......................... 47, 447, 462, 476
MSTPCR .................... 421, 447, 462, 476
P1DDR ......................... 91, 448, 462, 476
P1DR ............................ 91, 448, 463, 477
P3DDR ....................... 101, 448, 462, 476
P3DR .......................... 101, 448, 463, 477
P3ODR ....................... 102, 448, 462, 476
PADDR....................... 106, 448, 462, 476
PADR ......................... 106, 448, 463, 477
PAODR....................... 107, 448, 462, 476
PBDDR....................... 109, 448, 462, 476
PBDR.......................... 109, 449, 463, 477
PBODR....................... 110, 448, 462, 476
PCDDR....................... 112, 448, 462, 476
PCDR.......................... 112, 449, 463, 477
PCODR....................... 113, 448, 462, 476
PDDDR....................... 115, 448, 462, 476
PDDR ......................... 115, 449, 463, 477
PFDDR....................... 117, 448, 462, 476
PFDR.......................... 118, 449, 463, 477
PHDDR....................... 121, 447, 461, 475
PHDR ......................... 121, 447, 461, 475
PJDDR........................ 125, 447, 461, 475
PJDR........................... 125, 447, 461, 475
PORT1.......................... 92, 451, 466, 479
PORT3........................ 102, 451, 466, 479
PORT4........................ 105, 451, 466, 479
PORTA....................... 107, 451, 466, 479
PORTB....................... 110, 451, 466, 479
PORTC....................... 113, 451, 466, 479
PORTD....................... 116, 451, 466, 479
PORTF........................ 118, 451, 466, 479
PORTH....................... 122, 447, 461, 475
PORTJ ........................ 126, 447, 461, 475
PWBFR....................... 351, 446, 461, 475
PWCNT.............................................. 347
PWCR......................... 345, 446, 461, 475
PWCYR...................... 348, 446, 461, 475
PWDTR.............................................. 348
PWOCR...................... 346, 446, 461, 475
PWPR......................... 347, 446, 461, 475
RAMER...................... 386, 448, 463, 477
RDR............................ 218, 450, 465, 478
REC............................. 296, 438, 452, 467
RFPR........................... 290, 438, 452, 467
RSR.....................................................218
RSTCSR......................207, 450, 464, 478
RXPR..........................289, 438, 452, 467
SBYCR .......................417, 447, 462, 476
SCKCR .......................404, 447, 462, 476
SCMR .........................229, 450, 465, 478
SCR.............................222, 450, 464, 478
SMR............................219, 450, 464, 478
SSR.............................225, 450, 465, 478
SYSCR.......................... 48, 447, 462, 476
TCNT..........................155, 449, 463, 477
TCR............................. 137, 449, 463, 477
TCSR ..........................203, 450, 464, 478
TDR ............................218, 450, 464, 478
TEC.............................296, 438, 452, 467
TGR ............................155, 449, 463, 477
TIER............................151, 449, 463, 477
TIOR........................... 142, 449, 463, 477
TMDR.........................140, 449, 463, 477
TRPRT........................129, 447, 461, 475
TSR............................. 153, 449, 463, 477
TSTR........................... 156, 448, 462, 476
TSYR..........................157, 448, 462, 476
TXACK.......................287, 438, 452, 467
TXCR.......................... 286, 438, 452, 467
TXPR..........................285, 438, 452, 467
UMSR.........................297, 438, 452, 467
Reset .........................................................53
Serial Communication Interface (SCI)....215
Asynchronous Mode...........................237
Bit Rate...............................................230
Break...................................................274
Clocked Synchronous Mode...............254
framing error.......................................244
Mark State...........................................275
Multiprocessor Communication
Function..............................................248
overrun error .......................................244
parity error ..........................................244
stack pointer (SP)......................................20
Rev. 2.00, 03/04, page 508 of 508
Watchdog Timer..................................... 201
Interval Timer Mode........................... 210
overflow..............................................211
Watchdog Timer Mode.......................208
Renesas 16-Bit Single-Chip Microcomputer
Hardware Manual
H8S/2282 Group
Publication Date: 1st Edition Feb, 2002
Rev.2.00 Mar 18, 2004
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by: Technical Documentation & Information Department
Renesas Kodaira Semiconductor Co., Ltd.
2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon 1.0
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
http://www.renesas.com
Renesas Technology America, Inc.
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Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501
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RENESAS SALES OFFICES
H8S/2282 Group
Hardware Manual
