M41ST85WMH6 - STMicroelectronics

December 2008 Rev 10 1/41

M41ST85W

3.0/3.3 V I2C combination serial RTC, NVRAM

supervisor and microprocessor supervisor

Features

■Automatic battery switchover and WRITE

protect for:

– Internal serial RTC and

– External low power SRAM (LPSRAM)

■400 kHz I2C serial interface

■3.0/3.3 V operating voltage

–V

CC = 2.7 to 3.6 V

■Ultralow battery supply current of 500 nA (max)

■RoHS compliant

– Lead-free second level interconnect

Serial RTC features

■400 kHz I2C

■44 bytes of general purpose NVRAM

■Counters for:

– Seconds, minutes, hours, day, date, month,

and year

–Century

– Tenths/hundredths of seconds

– Clock calibration register allows

compensation for crystal variations over

temperature

■Programmable alarm with repeat modes

– Functions in battery back-up mode

■Power-down timestamp (HT bit)

■2.5 to 5.5 V oscillator operating voltage

Microprocessor supervisor features

■Programmable watchdog

– 62.5 ms to 128 s time-out period

■Early power-fail warning circuit (PFI/PFO) with

1.25 V precision reference

■Power-on reset/low voltage detect

– Open drain reset output

– Reset voltage, VPFD = 2.60 V (nom)

– Two reset input pins

– Watchdog can be steered to reset output

NVRAM supervisor features

■Non-volatizes external LPSRAM

– Automatically switches to back-up battery

and deselects (write-protects) external

LPSRAM via chip-enable gate

– Power-fail deselect (write protect) voltage,

VPFD = 2.60 V (nom)

– Switchover, VSO = 2.50 V (nom)

■Battery monitor (battery low flag)

Other features

■Programmable squarewave generator (1 Hz to

32 KHz)

■–40°C to +85°C operation

■Package options:

– 28-lead SNAPHAT® IC (SOH28) SNAPHAT

battery/crystal top to be ordered separately

– 28-lead embedded crystal SOIC (SOX28)

SNAPHAT (SH) battery & crystal

SOH28 (MH)

Embedded crystal

SOX28 (MX)

www.st.com

Contents M41ST85W
2/41   
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  12
1.1 Bus not busy   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2 Start data transfer   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3 Stop data transfer   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4 Data valid  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5 Acknowledge  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
3 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
4 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
Clock operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1 Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
2 TIMEKEEPER® registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
3 Calibrating the clock  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
4 Setting alarm clock registers   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
5 Watchdog timer   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24
6 Square wave output  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25
7 Power-on reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25
8 Reset inputs (RSTIN1 & RSTIN2)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26
9 Power-fail input/output  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26
10 Century bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27
11 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27
12 Battery low warning  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27
13 trec bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
14 Initial power-on defaults  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC and AC parameters  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

M41ST85W Contents

3/41

6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

List of tables M41ST85W
4/41   
List of tables
Table 1. Signal names  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. TIMEKEEPER® register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3. Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 4. Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5. Reset AC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6. trec definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. Default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9. DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10. Capacitance  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 12. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 14. SOH28 – 28-lead plastic small outline, battery SNAPHAT®, package mechanical data  . . 34
Table 15. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, mechanical data . . . . . . . . 35
Table 16. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, mechanical data . . . . . . . 36
Table 17. SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal, mechanical data  . . . 37
Table 18. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 19. SNAPHAT® battery/crystal table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 20. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

M41ST85W List of figures
 5/41
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. 28-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. 28-pin, 300 mil SOIC (MX) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Serial bus data transfer sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Write cycle timing: RTC & external SRAM control signals . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Alternate read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Write mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14. Calibration waveform  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16. Backup mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. RSTIN1 & RSTIN2 timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 18. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19. Bus timing requirements sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 21. SOH28 – 28-lead plastic small outline, battery SNAPHAT®, package outline . . . . . . . . . . 34
Figure 22. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package outline. . . . . . . . . 35
Figure 23. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package outline. . . . . . . . 36
Figure 24. SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal, package outline . . . . 37
Figure 25. Recycling symbols  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Description M41ST85W

6/41

1 Description

The M41ST85W is a combination serial real-time clock, microprocessor supervisor, and

NVRAM supervisor. It is built in a low power CMOS SRAM process and has a 64-byte

memory space with 44 bytes of NVRAM and 20 memory-mapped RTC registers (see

Table 2 on page 20). The RTC registers are configured in binary coded decimal (BCD)

format.

The M41ST85W combines a 400 kHz I2C serial RTC with an automatic backup battery

switchover circuit for powering an external LPSRAM as well as the internal RTC. When

power begins to fail, the switchover automatically connects to the backup battery to keep the

RTC and external LPSRAM alive in the absence of system power. Access to the LPSRAM is

also cut off via a chip-enable gate function, thereby write-protecting the memory. A

programmable watchdog and power-on reset/low voltage detect function are the key

elements in the microprocessor supervisor section.

The real-time clock includes a built-in 32.768 kHz oscillator (crystal-controlled), which

provides the time base for the timekeeping and calendar functions. Eight of the 20 clock

registers provide the basic clock/calendar functions while the other 12 bytes provide

status/control for the alarm, watchdog, and squarewave functions.

RTC addresses and data are transferred serially via the two-line, bidirectional I2C interface.

The built-in address register is incremented automatically after each WRITE or READ data

byte.

The M41ST85W has a built-in power sense circuit which detects power failures and

automatically switches to the backup battery when a power failure occurs. During an outage,

the power to sustain the SRAM and clock operations is typically supplied by a small lithium

button-cell battery as is the case when using the SNAPHAT® package option.

Functions available to the user include a non-volatile, time-of-day clock/calendar, alarm

interrupts, watchdog timer, and programmable squarewave generator. Other features

include a power-on reset as well as two additional debounce reset inputs (RSTIN1 and

RSTIN2) which can also generate an output reset (RST).

The eight registers for basic clock/calendar functions contain the century, year, month, date,

day, hour, minute, second, and tenths/hundredths of a second in 24-hour BCD format.

Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made

automatically.

The M41ST85W is offered in two 28-lead SOIC packages. The 300 mil SOH28 SNAPHAT®

IC package mates with ST’s SNAPHAT battery/crystal top (ordered separately). SNAPHAT

battery options include 48 mAh and 120 mAh. ST’s 300 mil SOX28 embedded crystal IC

includes the 32 KHz crystal and is perfect for applications where a low profile is a must.

The SOH28 SNAPHAT SOIC includes sockets with gold plated contacts at both ends for

direct connection to the SNAPHAT top. The SNAPHAT battery/crystal top is inserted atop

the IC package after the completion of the surface mount assembly process which avoids

potential battery and crystal damage due to the high temperatures required for device

surface-mounting. The unique design allows the battery to be replaced, thus extending the

life of the RTC and NVRAM indefinitely.

The SNAPHAT top is keyed to prevent reverse insertion. The SNAPHAT IC and SNAPHAT

tops are shipped separately. The ICs are available in plastic anti-static tubes or in tape &

reel form. The SNAPHAT tops are shipped in plastic anti-static tubes. The part numbers are

M41ST85W Description

7/41

M4T28-BR12SH1 (48 mAh) and M4T32-BR12SH1 (120 mAh). For the extended

temperature requirement, the 120 mAh M4T32-BR12SH6 is available. For more information,

see Table 19 on page 38.

Caution: Do not place the SNAPHAT® battery/crystal top in conductive foam, as this will drain the

lithium button-cell battery.

The 300 mil SOX embedded crystal SOIC typically requires a user-supplied battery for non-

volatile operation. Capacitor backup can also be implemented with this package.

Figure 1. Logic diagram

1. For 28-pin, 300 mil embedded crystal SOIC only.

AI03658

SCL

VCC

M41ST85W

VSS

VBAT(1)

SDA

RSTIN1

IRQ/FT/OUT

SQW

WDI

RSTIN2

PFI

ECON

RST

PFO

VOUT

Description M41ST85W

8/41

Table 1. Signal names

Figure 2. 28-pin SOIC connections

ECON Conditioned chip enable output

EX External chip enable

IRQ/FT/OUT Interrupt/frequency test/out output (open drain)

PFI Power fail input

PFO Power fail output

RST Reset output (open drain)

RSTIN1 Reset 1 Input

RSTIN2 Reset 2 Input

SCL Serial clock input

SDA Serial data input/output

SQW Square wave output

WDI Watchdog input

VCC Supply voltage

VOUT Voltage output

VSS Ground

VBAT(1)

1. For 28-pin, 300 mil embedded crystal SOIC only.

Battery supply voltage

NC No connect

NF No function

AI03659

RSTIN1

RSTIN2

WDI

IRQ/FT/OUT

VOUT

PFI

SCL

NCNC

PFO

ECON

VSS

SDA

RST

SQW VCC

M41ST85W

M41ST85W Description

9/41

Figure 3. 28-pin, 300 mil SOIC (MX) connections

Note: No function (NF) pins should be tied to VSS. Pins 1, 2, 3, and 4 are internally

shorted together.

AI06370d

RSTIN1

RSTIN2

SQW

WDI

IRQ/FT/OUT

VOUT

PFI

SCL

PFO

ECON

VSS VBAT

SDA

RST

NF VCC

M41ST85W

Description M41ST85W

10/41

Figure 4. Block diagram

1. Open drain output.

2. Crystal integrated into SOIC package for MX package option.

AI03932

COMPARE

VPFD = 2.65V

VCC

COMPARE

VSO = 2.5V

VOUT

VBL= 2.5V BL

COMPARE

Crystal(2)

I2C

INTERFACE

REAL TIME CLOCK

CALENDAR

44 BYTES

USER RAM

RTC w/ALARM

& CALIBRATION

WATCHDOG

SQUARE WAVE

SDA

SCL

1.25V

PFI

PFO

RSTIN1

POR

SQW

RST(1)

WDI

WDS

AFE

IRQ/FT/OUT(1)

VBAT

32KHz

OSCILLATOR

COMPARE

RSTIN2

EX ECON

(Internal)

M41ST85W Description

11/41

Figure 5. Hardware hookup

1. Required for embedded crystal (MX) package only.

AI03660

VCC

PFO

SCL

M41ST85W

WDI

RSTIN1

RSTIN2

PFI

VSS

VBAT(1) IRQ/FT/OUT

SQW

RST

VOUT

ECON

SDA

Unregulated

Voltage

Regulator

VCC

VIN

Pushbutton

Reset

From MCU

LPSRAM

VCC

To RST

To LED Display

To NMI

To INT

Operating modes M41ST85W

12/41

2 Operating modes

The M41ST85W clock operates as a slave device on the serial bus. Access is obtained by

implementing a start condition followed by the correct slave address (D0h). The 64 bytes

contained in the device can then be accessed sequentially in the following order:

1. Tenths/hundredths of a second register

2. Seconds register

3. Minutes register

4. Century/hours register

5. Day register

6. Date register

7. Month register

8. Year register

9. Control register

10. Watchdog register

11 - 16. Alarm registers

17 - 19. Reserved

20. Square wave register

21 - 64. User RAM

The M41ST85W clock continually monitors VCC for an out-of-tolerance condition. Should

VCC fall below VPFD, the device terminates an access in progress and resets the device

address counter. Inputs to the device will not be recognized at this time to prevent erroneous

data from being written to the device from a an out-of-tolerance system. When VCC falls

below VSO, the device automatically switches over to the battery and powers down into an

ultralow current mode of operation to conserve battery life. As system power returns and

VCC rises above VSO, the battery is disconnected, and the power supply is switched to

external VCC.

Write protection continues until VCC reaches VPFD(min) plus trec (min).

For more information on battery storage life refer to application note AN1012.

2.1 2-wire bus characteristics

The bus is intended for communication between different ICs. It consists of two lines: a bi-

directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be

connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

●Data transfer may be initiated only when the bus is not busy.

●During data transfer, the data line must remain stable whenever the clock line is high.

●Changes in the data line, while the clock line is high, will be interpreted as control

signals.

M41ST85W Operating modes

13/41

Accordingly, the following bus conditions have been defined:

2.1.1 Bus not busy

Both data and clock lines remain high.

2.1.2 Start data transfer

A change in the state of the data line, from high to low, while the clock is high, defines the

START condition.

2.1.3 Stop data transfer

A change in the state of the data line, from low to high, while the clock is high, defines the

STOP condition.

2.1.4 Data valid

The state of the data line represents valid data when after a start condition, the data line is

stable for the duration of the high period of the clock signal. The data on the line may be

changed during the low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition.

The number of data bytes transferred between the start and stop conditions is not limited.

The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.

By definition a device that gives out a message is called “transmitter,” the receiving device

that gets the message is called “receiver.” The device that controls the message is called

“master.” The devices that are controlled by the master are called “slaves.”

2.1.5 Acknowledge

Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low

level put on the bus by the receiver whereas the master generates an extra acknowledge

related clock pulse. A slave receiver which is addressed is obliged to generate an

acknowledge after the reception of each byte that has been clocked out of the slave

transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock

pulse in such a way that the SDA line is a stable low during the high period of the

acknowledge related clock pulse. Of course, setup and hold times must be taken into

account. A master receiver must signal an end of data to the slave transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In this

case the transmitter must leave the data line high to enable the master to generate the

STOP condition.

Operating modes M41ST85W

14/41

Figure 6. Serial bus data transfer sequence

Figure 7. Acknowledgement sequence

Figure 8. Write cycle timing: RTC & external SRAM control signals

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION

CHANGE OF

DATA ALLOWED

STOP

CONDITION

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCL FROM

MASTER

START

CLOCK PULSE FOR

ACKNOWLEDGEMENT

12 89

MSB LSB

AI03663

ECON

tEXPD

M41ST85W Operating modes

15/41

2.2 Read mode

In this mode the master reads the M41ST85W slave after setting the slave address (see

Figure 9). Following the WRITE mode control bit (R/W=0) and the acknowledge bit, the word

address 'An' is written to the on-chip address pointer. Next the START condition and slave

address are repeated followed by the READ mode control bit (R/W=1). At this point the

master transmitter becomes the master receiver.

The data byte which was addressed will be transmitted and the master receiver will send an

acknowledge bit to the slave transmitter (see Figure 10 on page 16). The address pointer is

only incremented on reception of an acknowledge clock. The M41ST85W slave transmitter

will now place the data byte at address An+1 on the bus, the master receiver reads and

acknowledges the new byte and the address pointer is incremented to An+2.

This cycle of reading consecutive addresses will continue until the master receiver sends a

STOP condition to the slave transmitter.

The system-to-user transfer of clock data will be halted whenever the address being read is

a clock address (00h to 07h). The update will resume either due to a stop condition or when

the pointer increments to a non-clock or RAM address.

Note: This is true both in READ mode and WRITE mode.

An alternate READ mode may also be implemented whereby the master reads the

M41ST85W slave without first writing to the (volatile) address pointer. The first address that

is read is the last one stored in the pointer (see Figure 11 on page 16).

Figure 9. Slave address location

AI00602

R/W

SLAVE ADDRESS

START A

0100011

MSB

LSB

Operating modes M41ST85W

16/41

Figure 10. Read mode sequence

Figure 11. Alternate read mode sequence

AI00899

BUS ACTIVITY:

ACK

NO ACK STOP

START

SDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

START

R/W

SLAVE

ADDRESS

ACK

AI00895

BUS ACTIVITY:

ACK

NO ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

SLAVE

ADDRESS

M41ST85W Operating modes

17/41

2.3 Write mode

In this mode the master transmitter transmits to the M41ST85W slave receiver. Bus protocol

is shown in Figure 12. Following the START condition and slave address, a logic '0' (R/W=0)

is placed on the bus and indicates to the addressed device that word address An will follow

and is to be written to the on-chip address pointer. The data word to be written to the

memory is strobed in next and the internal address pointer is incremented to the next

memory location within the RAM on the reception of an acknowledge clock. The M41ST85W

slave receiver will send an acknowledge clock to the master transmitter after it has received

the slave address and again after it has received the word address and each data byte.

Figure 12. Write mode sequence

2.4 Data retention mode

With valid VCC applied, the M41ST85W can be accessed as described above with READ or

WRITE cycles. Should the supply voltage decay, the M41ST85W will automatically deselect,

write protecting itself (and any external SRAM) when VCC falls between VPFD(max) and

VPFD(min). This is accomplished by internally inhibiting access to the clock registers. At this

time, the reset pin (RST) is driven active and will remain active until VCC returns to nominal

levels. External RAM access is inhibited in a similar manner by forcing ECON to a high level.

This level is within 0.2 volts of the VBAT

. ECON will remain at this level as long as VCC

remains at an out-of-tolerance condition. When VCC falls below the battery backup

switchover voltage (VSO), power input is switched from the VCC pin to the SNAPHAT®

battery, and the clock registers and external SRAM are maintained from the attached

battery supply.

All outputs become high impedance. The VOUT pin is capable of supplying 100 µA of current

to the attached memory with less than 0.3 volts drop under this condition. On power-up,

when VCC returns to a nominal value, write protection continues for trec by inhibiting ECON.

The RST signal also remains active during this time (see Figure 20 on page 33).

Note: Most low power SRAMs on the market today can be used with the M41ST85W RTC

SUPERVISOR. There are, however some criteria which should be used in making the final

choice of an SRAM to use. The SRAM must be designed in a way where the chip enable

input disables all other inputs to the SRAM. This allows inputs to the M41ST85W and

SRAMs to be “Don’t Care” once VCC falls below VPFD(min). The SRAM should also

guarantee data retention down to VCC = 2.0 volts. The chip enable access time must be

sufficient to meet the system needs with the chip enable output propagation delays

included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to

VOUT

AI00591

BUS ACTIVITY:

ACK

ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

Operating modes M41ST85W

18/41

If data retention lifetime is a critical parameter for the system, it is important to review the

data retention current specifications for the particular SRAMs being evaluated. Most SRAMs

specify a data retention current at 3.0 volts. Manufacturers generally specify a typical

condition for room temperature along with a worst case condition (generally at elevated

temperatures). The system level requirements will determine the choice of which value to

use. The data retention current value of the SRAMs can then be added to the IBAT value of

the M41ST85W to determine the total current requirements for data retention. The available

battery capacity for the SNAPHAT® top of your choice can then be divided by this current to

determine the amount of data retention available (see Table 19 on page 38).

For a further more detailed review of lifetime calculations, please see application note

AN1012.

M41ST85W Clock operation

19/41

3 Clock operation

The eight byte clock register (see Table 2 on page 20) is used to both set the clock and to

read the date and time from the clock, in a binary coded decimal format. Tenths/hundredths

of seconds, seconds, minutes, and hours are contained within the first four registers.

Note: A WRITE to any clock register will result in the tenths/hundredths of seconds being reset to

“00,” and tenths/hundredths of seconds cannot be written to any value other than “00.”

Bits D6 and D7 of clock register 03h (century/hours register) contain the CENTURY

ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle,

either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial

state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of register 04h contain the

day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month and

years. The ninth clock register is the control register (this is described in the clock calibration

section). Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause

the oscillator to stop. If the device is expected to spend a significant amount of time on the

shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator

restarts within one second.

The eight clock registers may be read one byte at a time, or in a sequential block. The

control register (address location 08h) may be accessed independently. Provision has been

made to assure that a clock update does not occur while any of the eight clock addresses

are being read. If a clock address is being read, an update of the clock registers will be

halted. This will prevent a transition of data during the READ.

3.1 Power-down time-stamp

When a power failure occurs, the halt update bit (HT) will automatically be set to a '1.' This

will prevent the clock from updating the TIMEKEEPER® registers, and will allow the user to

read the exact time of the power-down event. Resetting the HT bit to a '0' will allow the clock

to update the TIMEKEEPER registers with the current time. For more information, see

application note AN1572.

3.2 TIMEKEEPER® registers

The M41ST85W offers 20 internal registers which contain clock, alarm, watchdog, flag,

square wave and control data. These registers are memory locations which contain external

(user accessible) and internal copies of the data (usually referred to as BiPORT™

TIMEKEEPER cells). The external copies are independent of internal functions except that

they are updated periodically by the simultaneous transfer of the incremented internal copy.

The internal divider (or clock) chain will be reset upon the completion of a WRITE to any

clock address.

The system-to-user transfer of clock data will be halted whenever the address being read is

a clock address (00h to 07h). The update will resume either due to a stop condition or when

the pointer increments to a non-clock or RAM address.

TIMEKEEPER and alarm registers store data in BCD. control, watchdog and square wave

registers store data in binary format.

Clock operation M41ST85W

20/41

Table 2. TIMEKEEPER® register map

Address

Data Function/range

BCD format

D7 D6 D5 D4 D3 D2 D1 D0

00h 0.1 seconds 0.01 seconds Seconds 00-99

01h ST 10 seconds Seconds Seconds 00-59

02h 0 10 minutes Minutes Minutes 00-59

03h CEB CB 10 hours Hours (24-hour format) Century/hours 0-1/00-23

04h TR 0 0 0 0 Day of week Day 01-7

05h 0 0 10 date Date: day of month Date 01-31

06h 0 0 0 10M Month Month 01-12

07h 10 years Year Year 00-99

08h OUT FT S Calibration Control

09h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

0Ah AFE SQWE ABE Al 10M Alarm month Al month 01-12

0Bh RPT4 RPT5 AI 10 date Alarm date Al date 01-31

0Ch RPT3 HT AI 10 hour Alarm hour Al hour 00-23

0Dh RPT2 Alarm 10 minutes Alarm minutes Al min 00-59

0Eh RPT1 Alarm 10 seconds Alarm seconds Al sec 00-59

0Fh WDF AF 0 BL 0 0 0 0 Flags

10h 0 0 0 0 0 0 0 0 Reserved

11h 0 0 0 0 0 0 0 0 Reserved

12h 0 0 0 0 0 0 0 0 Reserved

13h RS3 RS2 RS1 RS0 0 0 0 0 SQW

Keys: S = Sign bit RB0-RB1 = Watchdog resolution bits

FT = Frequency test bit WDS = Watchdog steering bit

ST = Stop bit ABE = Alarm in battery backup mode enable bit

0 = Must be set to zero RPT1-RPT5 = Alarm repeat mode bits

BL = Battery low flag (read only) WDF = Watchdog flag (read only)

BMB0-BMB4 = Watchdog multiplier bits AF = Alarm flag (read only)

CEB = Century enable bit SQWE = Square wave enable

CB = Century bit RS0-RS3 = SQW frequency

OUT = Output level HT = Halt update bit

AFE = Alarm flag enable flag TR = trec bit

M41ST85W Clock operation

21/41

3.3 Calibrating the clock

The M41ST85W is driven by a quartz controlled oscillator with a nominal frequency of

32,768 Hz. The devices are tested not exceed +/–35 ppm (parts per million) oscillator

frequency error at 25oC, which equates to about +/–1.53 minutes per month. When the

Calibration circuit is properly employed, accuracy improves to better than ±2 ppm at 25°C.

The oscillation rate of crystals changes with temperature (see Figure 13 on page 22).

Therefore, the M41ST85W design employs periodic counter correction. The calibration

circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage,

as shown in Figure 14 on page 22. The number of times pulses which are blanked

(subtracted, negative calibration) or split (added, positive calibration) depends upon the

value loaded into the five calibration bits found in the control register. Adding counts speeds

the clock up, subtracting counts slows the clock down.

The calibration bits occupy the five lower order bits (D4-D0) in the control register (08h).

These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a

sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs

within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one

second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is

loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a

binary 6 is loaded, the first 12 will be affected, and so on.

Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator

cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of

adjustment per calibration step in the calibration register. Assuming that the oscillator is

running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would

represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or

–2.75 minutes per month.

Two methods are available for ascertaining how much calibration a given M41ST85W may

require.

The first involves setting the clock, letting it run for a month and comparing it to a known

accurate reference and recording deviation over a fixed period of time. Calibration values,

including the number of seconds lost or gained in a given period, can be found in application

note AN934, “TIMEKEEPER® calibration.” This allows the designer to give the end user the

ability to calibrate the clock as the environment requires, even if the final product is

packaged in a non-user serviceable enclosure. The designer could provide a simple utility

that accesses the calibration byte.

The second approach is better suited to a manufacturing environment, and involves the use

of the IRQ/FT/OUT pin. The pin will toggle at 512 Hz, when the stop bit (ST, D7 of 01h) is '0,'

the frequency test bit (FT, D6 of 08h) is '1,' the alarm flag enable bit (AFE, D7 of 0Ah) is '0,'

and the watchdog steering bit (WDS, D7 of 09h) is '1' or the watchdog register (09h = 0) is

reset.

Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at

the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm

oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration byte

for correction. Note that setting or changing the calibration byte does not affect the

frequency test output frequency.

The IRQ/FT/OUT pin is an open drain output which requires a pull-up resistor to VCC for

proper operation. A 500 to 10 k resistor is recommended in order to control the rise time.

The FT bit is cleared on power-down.

Clock operation M41ST85W

22/41

Figure 13. Crystal accuracy across temperature

Figure 14. Calibration waveform

AI07888

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

= –0.036 ppm/°C2 ± 0.006 ppm/°C2

ΔF= K x (T – TO)2

TO = 25°C ± 5°C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

M41ST85W Clock operation

23/41

3.4 Setting alarm clock registers

Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go

off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every

year, month, day, hour, minute, or second. It can also be programmed to go off while the

M41ST85W is in the battery backup to serve as a system wake-up call.

Bits RPT5–RPT1 put the alarm in the repeat mode of operation. Ta bl e 3 shows the possible

configurations. Codes not listed in the table default to the once per second mode to quickly

alert the user of an incorrect alarm setting.

When the clock information matches the alarm clock settings based on the match criteria

defined by RPT5–RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set, the

alarm condition activates the IRQ/FT/OUT pin as shown in Figure 15. To disable alarm,

write '0' to the alarm date register and to RPT5–RPT1.

Note: If the address pointer is allowed to increment to the flag register address, an alarm condition

will not cause the interrupt/flag to occur until the address pointer is moved to a different

address. It should also be noted that if the last address written is the “Alarm Seconds,” the

address pointer will increment to the flag address, causing this situation to occur.

The IRQ/FT/OUT output is cleared by a READ to the flags register. A subsequent READ of

the flags register is necessary to see that the value of the alarm flag has been reset to '0.'

The IRQ/FT/OUT pin can also be activated in the battery backup mode. The IRQ/FT/OUT

will go low if an alarm occurs and both ABE (alarm in battery backup mode enable) and AFE

are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated

during power-up will only set AF. The user can read the flag register at system boot-up to

determine if an alarm was generated while the M41ST85W was in the deselect mode during

power-up. Figure 16 on page 24 illustrates the backup mode alarm timing.

Figure 15. Alarm interrupt reset waveform

Table 3. Alarm repeat modes

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm setting

11111Once per second

11110Once per minute

11100Once per hour

11000Once per day

10000Once per month

00000Once per year

AI03664

IRQ/FT/OUT

ACTIVE FLAG

0Fh0Eh 10h

HIGH-Z

Clock operation M41ST85W

24/41

Figure 16. Backup mode alarm waveform

3.5 Watchdog timer

The watchdog timer can be used to detect an out-of-control microprocessor. The user

programs the watchdog timer by setting the desired amount of time-out into the watchdog

RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second,

and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of

the five-bit multiplier value with the resolution. (For example: writing 00001110 in the

watchdog register = 3*1 or 3 seconds).

Note: The accuracy of the timer is within ± the selected resolution.

If the processor does not reset the timer within the specified period, the M41ST85W sets the

WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset.

The most significant bit of the watchdog register is the watchdog steering bit (WDS). When

set to a '0,' the watchdog will activate the IRQ/FT/OUT pin when timed-out. When WDS is

set to a '1,' the watchdog will output a negative pulse on the RST pin for trec. The watchdog

when the WDS bit is set to a '1.'

The watchdog timer can be reset by two methods: 1) a transition (high-to-low or low-to-high)

can be applied to the watchdog input pin (WDI) or 2) the microprocessor can perform a

WRITE of the watchdog register. The time-out period then starts over.

Note: The WDI pin should be tied to VSS if not used.

In order to perform a software reset of the watchdog timer, the original time-out period can

be written into the watchdog register, effectively restarting the count-down cycle.

Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt,

a value of 00h needs to be written to the watchdog register in order to clear the IRQ/FT/OUT

AI03920

VCC

IRQ/FT/OUT

VPFD

ABE, AFE Bits in Interrupt Register

AF bit in Flags Register

HIGH-Z

VSO

HIGH-Z

trec

M41ST85W Clock operation

25/41

pin. This will also disable the watchdog function until it is again programmed correctly. A

READ of the flags register will reset the watchdog flag (bit D7; register 0Fh).

The watchdog function is automatically disabled upon power-up and the watchdog register

is cleared. If the watchdog function is set to output to the IRQ/FT/OUT pin and the frequency

test function is activated, the watchdog function prevails and the frequency test function is

denied.

3.6 Square wave output

The M41ST85W offers the user a programmable square wave function which is output on

the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency.

These frequencies are listed in Ta bl e 4 . Once the selection of the SQW frequency has been

completed, the SQW pin can be turned on and off under software control with the square

wave enable bit (SQWE) located in register 0Ah.

Table 4. Square wave output frequency

3.7 Power-on reset

The M41ST85W continuously monitors VCC. When VCC falls to the power fail detect trip

point, the RST pulls low (open drain) and remains low on power-up for trec after VCC passes

VPFD(max). The RST pin is an open drain output and an appropriate pull-up resistor should

be chosen to control rise time.

Square wave bits Square wave

RS3 RS2 RS1 RS0 Frequency Units

0000None–

000132.768kHz

00108.192kHz

00114.096kHz

01002.048kHz

01011.024kHz

0110512Hz

0111256Hz

1000128Hz

100164Hz

101032Hz

101116Hz

11008Hz

11014Hz

11102Hz

11111Hz

Clock operation M41ST85W

26/41

3.8 Reset inputs (RSTIN1 & RSTIN2)

The M41ST85W provides two independent inputs which can generate an output reset. The

duration and function of these resets is identical to a reset generated by a power cycle.

Ta bl e 5 and Figure 17 illustrate the AC reset characteristics of this function. Pulses shorter

than tRLRH1 and tRLRH2 will not generate a reset condition. RSTIN1 and RSTIN2 are each

internally pulled up to VCC through a 100 kΩ resistor.

Figure 17. RSTIN1 & RSTIN2 timing waveforms

Note: With pull-up resistor

Table 5. Reset AC characteristics

3.9 Power-fail input/output

The power-fail input (PFI) is compared to an internal reference voltage (1.25 V). If PFI is less

than the power-fail threshold (VPFI), the power-fail output (PFO) will go low. This function is

intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is

connected through an external voltage divider (see Figure 5 on page 11) to either the

unregulated DC input (if it is available) or the regulated output of the VCC regulator. The

voltage divider can be set up such that the voltage at PFI falls below VPFI several

milliseconds before the regulated VCC input to the M41ST85W or the microprocessor drops

below the minimum operating voltage.

During battery backup, the power-fail comparator turns off and PFO goes (or remains) low.

This occurs after VCC drops below VPFD(min). When power returns, PFO is forced high,

irrespective of VPFI for the write protect time (trec), which is the time from VPFD(max) until the

inputs are recognized. At the end of this time, the power-fail comparator is enabled and PFO

Symbol Parameter(1)

1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6 V (except where noted).

Min Max Unit

tRLRH1(2)

2. Pulse width less than 50 ns will result in no RESET (for noise immunity).

RSTIN1 low to RSTIN1 high 200 ns

tRLRH2(3)

3. Pulse width less than 20 ms will result in no RESET (for noise immunity).

RSTIN2 low to RSTIN2 high 100 ms

tR1HRH(4)

4. Programmable (see Table 6 on page 28).

RSTIN1 high to RST high 40 200 ms

tR2HRH(4) RSTIN2 high to RST high 40 200 ms

AI03665

RSTIN2

RST (1)

RSTIN1

tRLRH1

tRLRH2

tR1HRH tR2HRH

M41ST85W Clock operation

27/41

follows PFI. If the comparator is unused, PFI should be connected to VSS and PFO left

unconnected.

3.10 Century bit

Bits D7 and D6 of clock register 03h contain the CENTURY ENABLE bit (CEB) and the

CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or

from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'

CB will not toggle.

3.11 Output driver pin

When the FT bit, AFE bit and watchdog register are not set, the IRQ/FT/OUT pin becomes

an output driver that reflects the contents of D7 of the control register. In other words, when

D7 (OUT bit) and D6 (FT bit) of address location 08h are a '0,' then the IRQ/FT/OUT pin will

be driven low.

Note: The IRQ/FT/OUT pin is an open drain which requires an external pull-up resistor.

3.12 Battery low warning

The M41ST85W automatically performs battery voltage monitoring upon power-up and at

factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit

D4 of flags register 0Fh, will be asserted if the battery voltage is found to be less than

approximately 2.5 V. The BL bit will remain asserted until completion of battery replacement

and subsequent battery low monitoring tests, either during the next power-up sequence or

the next scheduled 24-hour interval.

If a battery low is generated during a power-up sequence, this indicates that the battery is

below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM.

Data should be considered suspect and verified as correct. A fresh battery should be

installed.

If a battery low indication is generated during the 24-hour interval check, this indicates that

the battery is near end of life. However, data is not compromised due to the fact that a

nominal VCC is supplied. In order to insure data integrity during subsequent periods of

battery backup mode, the battery should be replaced. The SNAPHAT® top may be replaced

while VCC is applied to the device.

Note: This will cause the clock to lose time during the interval the SNAPHAT battery/crystal top is

disconnected.

The M41ST85W only monitors the battery when a nominal VCC is applied to the device.

Thus applications which require extensive durations in the battery backup mode should be

powered-up periodically (at least once every few months) in order for this technique to be

beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon

power-up via a checksum or other technique.

Clock operation M41ST85W

28/41

3.13 trec bit

Bit D7 of clock register 04h contains the trec bit (TR). trec refers to the automatic

continuation of the deselect time after VCC reaches VPFD. This allows for a voltage settling

time before WRITEs may again be performed to the device after a power-down condition.

The trec bit will allow the user to set the length of this deselect time as defined by Ta bl e 6 .

3.14 Initial power-on defaults

Upon initial application of power to the device, the following register bits are set to a '0' state:

watchdog register, FT, AFE, ABE, SQWE, and TR. The following bits are set to a '1' state:

ST, OUT, and HT (see Ta bl e 7 ).

Table 6. trec definitions

Table 7. Default values

trec bit (TR) STOP bit (ST)

trec time

Units

Min Max

009698ms

0140200

(1)

1. Default setting

1 X 50 2000 µs

Condition TR ST HT Out FT AFE ABE SQWE Watchdog

1. WDS, BMB0-BMB4, RB0, RB1.

Initial power-up(2)

2. State of other control bits undefined.

0111000 0 0

Subsequent power-up

(with battery backup)(3)

3. UC = Unchanged

UC UC 1 UC 0 0 0 0 0

M41ST85W Maximum ratings

29/41

4 Maximum ratings

Stressing the device above the rating listed in the absolute maximum ratings table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality documents.

Table 8. Absolute maximum ratings

Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup

mode.

Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

Symbol Parameter Value Unit

TSTG

Storage temperature (VCC off, oscillator

off)

SNAPHAT®–40 to 85 °C

SOIC –55 to 150 °C

TSLD Lead solder temperature for 10 seconds SOH28(1)

1. For SOH28 package, lead-free (pb-free) lead finish: reflow at peak temperature of 260°C (the time above

255°C must not exceed 30 seconds).

260 °C

SOX28(2)

2. The SOX28 package has lead-free (pb-free) lead finish, but cannot be exposed to peak reflow temperature

in excess of 240°C. Reflow at peak temperature of 240°C (the time above 235°C must not exceed 20

seconds).

240 °C

VIO Input or output voltage –0.3 to VCC+0.3 V

VCC Supply voltage –0.3 to 4.6 V

IOOutput current 20 mA

PDPower dissipation 1 W

DC and AC parameters M41ST85W

30/41

5 DC and AC parameters

This section summarizes the operating and measurement conditions, as well as the DC and

AC characteristics of the device. The parameters in the following DC and AC characteristic

tables are derived from tests performed under the measurement conditions listed in the

relevant tables. Designers should check that the operating conditions in their projects match

the measurement conditions when using the quoted parameters.

Table 9. DC and AC measurement conditions

Note: Output High Z is defined as the point where data is no longer driven.

Figure 18. AC testing input/output waveforms

Table 10. Capacitance

Parameter M41ST85W

VCC supply voltage 2.7 to 3.6 V

Ambient operating temperature –40 to 85°C

Load capacitance (CL)50 pF

Input rise and fall times ≤ 50 ns

Input pulse voltages 0.2 to 0.8VCC

Input and output timing ref. voltages 0.3 to 0.7VCC

Symbol Parameter(1)(2)

1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested.

2. At 25°C, f = 1 MHz.

Min Max Unit

CIN Input capacitance 7 pF

COUT(3)

3. Outputs are deselected.

Output capacitance 10 pF

tLP Low-pass filter input time constant (SDA and SCL) 50 ns

AI02568

0.8VCC

0.2VCC

0.7VCC

0.3VCC

M41ST85W DC and AC parameters

31/41

Table 11. DC characteristics

Sym Parameter Test condition(1)

1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6 V (except where noted).

M41ST85W

Unit

Min Typ Max

IBAT(2)

2. Measured with VOUT and ECON open.

Battery current OSC ON TA = 25°C, VCC = 0 V, VBAT = 3 V 400 500 nA

Battery current OSC OFF 50 nA

ICC1 Supply current f = 400 kHz 0.75 mA

ICC2 Supply current (standby) SCL, SDA = VCC – 0.3 V

or VSS + 0.3 V 0.50 mA

ILI(3)

3. RSTIN1 and RSTIN2 internally pulled-up to VCC through 100 KΩ resistor. WDI internally pulled-down to VSS through

100 KΩ resistor.

Input leakage current 0V ≤ VIN ≤ VCC ±1 µA

Input leakage current (PFI) –25 2 25 nA

ILO(4)

4. Outputs deselected.

Output leakage current 0V ≤ VIN ≤ VCC ±1 µA

IOUT1(5)

5. External SRAM must match RTC supervisor chip VCC specification.

VOUT current (active) VOUT1 > VCC – 0.3 V 100 mA

IOUT2 VOUT current (battery backup) VOUT2 > VBAT – 0.3 V 100 µA

VIH Input high voltage 0.7VCC VCC + 0.3 V

VIL Input low voltage –0.3 0.3VCC V

VBAT Battery voltage 2.5 3.0 3.5(6)

6. For rechargeable backup, VBAT (max) may be considered VCC.

VOH Output high voltage(7)

7. For PFO and SQW pins (CMOS).

IOH = –1.0 mA 2.4 V

Pull-up supply voltage (open drain) RST, IRQ/FT/OUT 3.6 V

VOHB(8)

8. Conditioned output (ECON) can only sustain CMOS leakage current in the battery backup mode. Higher leakage currents

will reduce battery life.

VOH (battery backup) IOUT2 = –1.0 µA 2.5 2.9 3.5 V

VOL

Output low voltage IOL = 3.0 mA 0.4 V

Output low voltage (open drain)(9)

9. For IRQ/FT/OUT, RST pins (open drain): if pulled-up to supply other than VCC, this supply must be equal to, or less than

3.0 V when VCC = 0 V (during battery backup mode).

IOL = 10 mA 0.4 V

VPFD Power fail deselect 2.55 2.60 2.70 V

VPFI

PFI input threshold VCC = 3 V(W) 1.225 1.250 1.275 V

PFI hysteresis PFI rising 20 70 mV

VSO Battery backup switchover 2.5 V

DC and AC parameters M41ST85W

32/41

Figure 19. Bus timing requirements sequence

Table 12. AC characteristics

Symbol Parameter(1)

1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6 V (except where otherwise noted).

Min Max Unit

fSCL SCL clock frequency 0 400 kHz

tBUF Time the bus must be free before a new transmission can start 1.3 µs

tEXPD EX to ECON propagation delay 15 ns

tFSDA and SCL fall time 300 ns

tHD:DAT(2)

2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.

Data hold time 0 µs

tHD:STA START condition hold time (after this period the first clock pulse is generated) 600 ns

tHIGH Clock high period 600 ns

tLOW Clock low period 1.3 µs

tRSDA and SCL rise time 300 ns

tSU:DAT Data setup time 100 ns

tSU:STA START condition setup time (only relevant for a repeated start condition) 600 ns

tSU:STO STOP condition setup time 600 ns

AI00589

SDA

tSU:STOtSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STAtBUF

M41ST85W DC and AC parameters

33/41

Figure 20. Power down/up mode AC waveforms

Table 13. Power down/up AC characteristics

Symbol Parameter(1)

1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6 V (except where otherwise noted).

Min Typ Max Unit

tF(2)

2. VPFD(max) to VPFD(min) fall time of less than tF may result in deselection/write protection not occurring until

200 µs after VCC passes VPFD(min).

VPFD(max) to VPFD(min) VCC fall time 300 µs

tFB(3)

3. VPFD(min) to VSS fall time of less than tFB may cause corruption of RAM data.

VPFD(min) to VSS VCC fall time 10 µs

tPD EX at VIH before power down 0 µs

tPFD PFI to PFO propagation delay 15 25 µs

tRVPFD(min) to VPFD(max) VCC rise time 10 µs

tRB VSS to VPFD(min) VCC rise time 1 µs

trec(4)

4. Programmable (see Table 6 on page 28)

Power-up deselect time 40 200 ms

AI03661

VCC

INPUTS

(PER CONTROL INPUT)

OUTPUTS

DON'T CARE

HIGH-Z

tFB

tPD

tRB

tDR

VALID VALID

(PER CONTROL INPUT)

RECOGNIZEDRECOGNIZED

VPFD (max)

VPFD (min)

VSO

trec

RST

ECON

PFO

Package mechanical data M41ST85W

34/41

6 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

Figure 21. SOH28 – 28-lead plastic small outline, battery SNAPHAT®, package outline

Note: Drawing is not to scale.

SOH-A

LA1 α

Table 14. SOH28 – 28-lead plastic small outline, battery SNAPHAT®, package mechanical data

Symbol

millimeters inches

Typ Min Max Typ Min Max

A 3.05 0.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.51 0.014 0.020

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e 1.27 – – 0.050 – –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

a0°8°0°8°

N 28 28

CP 0.10 0.004

M41ST85W Package mechanical data

35/41

Figure 22. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package outline

Note: Drawing is not to scale.

SHTK-A

A1 A

Table 15. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, mechanical data

Symbol

millimeters inches

Typ Min Max Typ Min Max

A 9.78 0.3850

A1 6.73 7.24 0.2650 0.2850

A2 6.48 6.99 0.2551 0.2752

A3 0.38 0.0150

B 0.46 0.56 0.0181 0.0220

D 21.21 21.84 0.8350 0.8598

E 14.22 14.99 0.5598 0.5902

eA 15.55 15.95 0.6122 0.6280

eB 3.20 3.61 0.1260 0.1421

L 2.03 2.29 0.0799 0.0902

Package mechanical data M41ST85W

36/41

Figure 23. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package outline

Note: Drawing is not to scale.

SHTK-A

A1 A

Table 16. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, mechanical data

Symbol

millimeters inches

Typ Min Max Typ Min Max

A 10.54 0.415

A1 8.00 8.51 0.315 0.335

A2 7.24 8.00 0.285 0.315

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 0.710

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

M41ST85W Package mechanical data

37/41

Figure 24. SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal, package outline

Note: Drawing is not to scale.

15 28

SO-E

A1 LA1 α

h x 45°

AA2

ddd

Table 17. SOX28 – 28-lead plastic small outline, 300 mils, embedded crystal, mechanical data

Symbol

millimeters inches

Typ Min Max Typ Min Max

A 2.44 2.69 0.096 0.106

A1 0.15 0.31 0.006 0.012

A2 2.29 2.39 0.090 0.094

B 0.41 0.51 0.016 0.020

C 0.20 0.31 0.008 0.012

D 17.91 18.01 0.705 0.709

ddd 0.10 0.004

E 7.57 7.67 0.298 0.302

e 1.27 – – 0.050 – –

H 10.16 10.52 0.400 0.414

L 0.51 0.81 0.020 0.032

a0°8°0°8°

N 28 28

Part numbering M41ST85W

38/41

7 Part numbering

Table 18. Ordering information scheme

Caution: Do not place the SNAPHAT® battery package “M4Txx-BR12SH” in conductive foam as it will

drain the lithium button-cell battery.

For other options, or for more information on any aspect of this device, please contact the ST sales office

nearest you.

Table 19. SNAPHAT® battery/crystal table

Example: M41ST 85W MH 6 E

Device type

M41ST

Supply voltage and write protect voltage

85W = VCC = 2.7 to 3.6 V; 2.55V ≤ VPFD ≤ 2.70 V

Package

MH(1) = SOH28

1. The 28-pin SOIC package (SOH28) requires the SNAPHAT® battery/crystal package which is ordered

separately under the part number “M4TXX-BR12SHX” in plastic tube or “M4Txx-BR12SHXTR” in tape &

reel form (see Table 19).

MX(2) = SOX28

2. The SOX28 package includes an embedded 32,768 Hz crystal.

Temperature range

6 = –40 to 85°C

Shipping method

For SOH28:

Blank = tubes (Not for New Design - use E)

E = ECOPACK® package, tubes

F = ECOPACK® package, tape & reel

TR = tape & reel (Not for New Design - use F)

For SOX28:

Blank = ECOPACK® package, tubes

TR = ECOPACK® package, tape & reel

Part number Description Package

M4T28-BR12SH Lithium battery (48 mAh) and crystal SNAPHAT® top SH

M4T32-BR12SH Lithium battery (120 mAh) and crystal SNAPHAT® top SH

M41ST85W Environmental information

39/41

8 Environmental information

Figure 25. Recycling symbols

This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)

button cell battery fully encapsulated in the final product.

Recycle or dispose of batteries in accordance with the battery manufacturer's instructions

and local/national disposal and recycling regulations.

Please refer to the following web site address for additional information regarding

compliance statements and waste recycling.

Go to www.st.com/rtc, then select "Lithium Battery Recycling" from "Related Topics".

Revision history M41ST85W
40/41   
9 Revision history
Table 20. Document revision history
Date Revision Changes
Aug-2000 1 First issue
24-Aug-2000 1.1 Block Diagram added (Figure 4)
12-Oct-2000 1.2 trec Table removed, cross references corrected
18-Dec-2000 2 Reformatted, TOC added, and PFI Input Leakage Current added (Tabl e 11 )
18-Jun-2001 2.1
Addition of trec information, table changed, one added (Ta bl e 2 , 6); changed PFI/PFO 
graphic (see Figure 4); change to DC and AC Characteristics, Order Information 
(Ta b l e 1 1 , 12, 18); note added to “Setting Alarm Clock Registers” section; added 
temp./voltage info. to tables (Ta b l e 1 0 , 11, 6, 12, 13); addition of Default Values 
(Ta b l e 7 )
22-Jun-2001 2.2 Note added to Clock Operation section
26-Jul-2001 3 Change in Product Maturity
07-Aug-2001 3.1 Improve text in “Setting the Alarm Clock” section
20-Aug-2001 3.2 Change VPFD values in document
06-Sep-2001 3.3 DC Characteristics VBAT changed; VOHB changed; PFI Hysteresis (PFI Rising) spec. 
added; and Crystal Electrical Characteristics table removed (Ta b le 1 1 , 6)
03-Dec-2001 3.4 Changed READ/WRITE Mode Sequences (Figure 10, 12); change in VPFD lower limit 
for 5V (M41ST85Y) part only (Ta bl e 1 1 , 18)
01-May-2002 3.5 Change trec Definition (Ta ble 6 ); modify reflow time and temperature footnote (Ta b l e 8 )
03-Jul-2002 3.6 Modify DC Characteristics table footnote, Default Values (Ta bl e 1 1 , 7)
15-Nov-2002 3.7 Added embedded crystal (MX) package option; corrected initial power-up condition 
(cover page, Figure 1, 3, 4, 5, 24, Ta bl e 1 , 7, 18, )
24-Jan-2003 3.8 Update diagrams (Figure 4, 5, 24); update values (Ta bl e 1 3 , 5, 6, 7, )
25-Feb20-03 4 New Si changes (Ta b l e 1 3 , 5, 6); corrected dimensions (Figure 24; Ta b l e )
20-May-2004 5 Reformatted; correct dimensions; update Lead-free information (Figure 20, 13, 16; 
Ta b le 8 , 16, 18)
15-Jun-2004 6 Update characteristics; add package shipping (Figure 3; Ta b l e 1 , 11, 18)
13-Sep-2004 7 Update Maximum ratings (Ta bl e 8 )
10-Jan-2006 8 Updated template, Lead-free text, removed 5V references (Figure 1, 2, 3, 4, 5; Tabl e 5, 
8, 9, 11, 12, 13, 18, 19)
03-Oct-2007 9 Reformatted document, some text changes; added lead-free second level interconnect 
information to cover page and Section 6: Package mechanical data; updated Ta b l e 8 .
16-Dec-2008 10 Added Section 8: Environmental information; updated Ta b l e 8 , Section 6: Package 
mechanical data; minor reformatting.

M41ST85W

41/41

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