Version 2.0, 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Off-Line SMPS Current Mode Controller with integrated 800V CoolMOS(R) and Startup cell (brownout & CCM) in DIP-7 Power Management & Supply N e v e r s t o p t h i n k i n g . CoolSET(R)-F3R80 ICE3AR4780CJZ Revision History: 2013-04-19 Datasheet Version 2.0 Previous Version: V 0.1 For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http:// www.infineon.com CoolMOS(R), CoolSET(R) are trademarks of Infineon Technologies AG. Edition 2013-04-19 Published by Infineon Technologies AG 81726 Munchen, Germany (c) Infineon Technologies AG 4/19/13. All Rights Reserved. Attention please! The information given in this data sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. CoolSET(R)-F3R80 ICE3AR4780CJZ Off-Line SMPS Current Mode Controller with integrated 800V CoolMOS(R) and Startup cell (brownout & CCM) in DIP-7 Product Highlights * 800V avalanche rugged CoolMOS(R) with startup cell * CCM and DCM operation with slope compensation * Active Burst Mode to reach the lowest Standby Power <100mW * Active burst mode with selectable entry and exit burst mode level * Frequency jitter and soft driving for low EMI * Brownout feature * Latch enable and fast AC reset * Auto Restart protection for over load, over temperature and over voltage * Pb-free lead plating; RoHS compliant Description Features * * * * * * * * * * * * * * P-DIP-7-1 PG-DIP7 800V avalanche rugged CoolMOS(R) with Startup Cell Active Burst Mode for lowest Standby Power Slope compensation for CCM operation Selectable entry and exit burst mode level 100kHz internally fixed switching frequency with jittering feature Auto Restart Protection for Over load, Open Loop, VCC Under voltage & Over voltage and Over temperature External latch enable pin and fast AC reset Over temperature protection with 50C hysteresis Built-in 10ms Soft Start Built-in 40ms blanking time for short duration peak power Propagation delay compensation for both maximum load and burst mode Brownout feature BiCMOS technology for low power consumption and wide VCC voltage range Soft gate drive with 50 turn on resistor The ICE3ARxx80CJZ is an enhanced version of ICE3ARxx80JZ (CoolSET(R)-F3R80). The PWM controller is based on F3R80 with new and enhanced features. The major new features include slope compensation for CCM operation and fast AC reset after latch enabled. The major enhanced features include fixed voltage brownout detect and voltage detect for the burst selection. In particular it is a device running at 100KHz, implemented with brownout features, installing 800V CoolMOS(R) with startup cell and packaged into DIP-7. It targets for the low power SMPS with increased MOSFET voltage margin requirement such as Off-Line battery adapters, DVD R/ W, DVD Combi, Blue ray, set top box, auxiliary power supply for PC and server, etc. In summary, this enhanced ICE3ARxx80CJZ provides 800V MOSFET, lowest standby power, CCM opeation, selectable burst level, brownout feature, maximum power compensated for both maximum and standby load, low EMI with frequency jittering and soft gate drive, built-in and flexible protections, etc. Therefore, ICE3ARxx80CJZ is a complete solution for the low power SMPS application. Typical Application + 85 ... 270 VAC Converter DC Output Snubber CBulk - CVCC VCC Drain Startup Cell Power Management PWM Controller Current Mode CS Precise Low Tolerance Peak Current Limitation CoolMOS(R) RSense FBB RBO1 RBO2 BRL Control Unit Active Burst Mode Brownout mode Auto Restart/ Latch Mode CoolSET(R)-F3R80 (Brownout & CCM) GND Rsel Type Package Marking VDS FOSC RDSon1) 230VAC 15%2) 85-265 VAC2) ICE3AR4780CJZ PG-DIP-7 3AR4780CJZ 800V 100kHz 4.7 31W 20W 1) typ @ T=25C 2) Calculated maximum input power rating at Ta=50C, Ti=125C and without copper area as heat sink. Version 2.0 3 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Table of Contents Page 1 1.1 1.2 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Configuration with PG-DIP-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.5 3.5.1 3.5.2 3.5.3 3.6 3.6.1 3.6.2 3.7 3.7.1 3.7.1.1 3.7.1.2 3.7.1.3 3.7.1.4 3.7.2 3.7.2.1 3.7.2.2 3.7.3 3.7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Improved Current Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 PWM-OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 PWM-Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Slope Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Combined OPP curve considering Propagation Delay and Slope Compensation 14 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Active Burst Mode (patented) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Selectable burst entry level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Vcc OVP, OTP, external protection enable and Vcc under voltage . . .18 Over load, open loop protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Brownout Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Fast AC reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Soft Start time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Version 2.0 4 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ CoolMOS(R) Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4.3.7 5 CoolMOS(R) Perfromance Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . .26 6 Input Power Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 7 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 8 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 9 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .31 Version 2.0 5 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Pin Configuration and Functionality 1 Pin Configuration and Functionality 1.1 Pin Configuration with PG-DIP-7 Pin Symbol 1.2 Function 1 BRL Brownout, fast AC Reset & Latch enable 2 FBB Feedback & Burst entry/exit control 3 CS Current Sense/ 800V CoolMOS(R) Source 4 n.c. not connected 5 Drain 6 - FBB (Feedback & Burst entry select) The FBB pin combines the feedback function and the burst entry/exit control. The regulation information is provided by the FBB pin to the internal Protection Unit and the internal PWM-Comparator to control the duty cycle. The FBB-signal is the only control signal in case of light load at the Active Burst Mode. The burst entry select provides an access to select the entry/exit burst mode level. 800V CoolMOS(R) Drain (no pin) 7 VCC Controller Supply Voltage 8 GND Controller Ground Package PG-DIP-7 BRL 1 8 GND FBB 2 7 VCC CS n.c. Figure 1 Version 2.0 CS (Current Sense) The Current Sense pin senses the voltage developed on the shunt resistor inserted in the source of the integrated CoolMOS(R). If CS reaches the internal threshold of the Current Limit Comparator, the Driver output is immediately switched off. Furthermore the current information is provided for the PWMComparator to realize the Current Mode operation. Drain (Drain of integrated CoolMOS(R)) The Drain pin is the connection to the Drain of the integrated CoolMOS(R). 3 4 Pin Functionality BRL (Brownout, fast AC Reset & Latch enable) The BRL pin combines the functions of brownout, fast AC reset and the external latch enable. The brownout feature is to stop the switching pulse when the input voltage is dropped to lower than 1V. The Fast AC reset feature is to recover from latch feature when the voltage of BRL pin has a rising rate of <1.33V/ms from 0.4V to 1V. The external latch enable function is an external access to stop the gate switching and force the IC to enter latch mode. It is triggered by pulling the pin voltage to less than 0.4V. 5 VCC (Power Supply) The VCC pin is the power supply of the IC. The voltage operating range is between 10.5V and 24.7V. Drain GND (Ground) The GND pin is the ground of the controller. Pin Configuration PG-DIP-7 (top view) 6 19 Apr 2013 Figure 2 Version 2.0 #2 TLE Latch Enable Signal RBO1 RBO0 7 Rsel FBB #1 Cap2 RBO2 BRL #1 #1 25k 2pF C11 C2b C2a C3 C2 C1b C1a 3.2V 3.5V VFB_burst 4.0V 4.5V C6b C6a C5 C9 C4 G3 Blanking time 450s Blanking time 210us 120us Blanking Blanking time 270s FF2 S Spike Blanking 30us 5.0V 17V G3 PWM OP 0.6V x3.25 PWM comparator C8 Current Mode C7 & Soft Start Soft start comparator 10.5V Undervoltage Lockout Voltage Reference or G8 1 C12 Vcsth_burst Vcsth G4 Propagation-Delay Compensation-Burst Current Limiting & G6 C10 Maximum power limit Freq. jitter Clock Duty Cycle max Oscillator 0.75 G5 & Gate Driver LEB 180/220ns Mc S5 Slope compensation 5.0V LEB 180/220ns FF1 S R Q Drain 10k 1pF D2 Rslope 10k 1pF D1 CoolMOS(R) Startup Cell PWM Section CVCC #1 :RBO0, RBO1 & RBO2 are used for brownout feature (need to tie high BRL if no brownout feature needed) #2 : TLE is used to enable the external Latch-Mode feature & G7 G11 Active Burst Mode Auto Restart Mode Soft Start Block Power-Down Reset Internal Bias Control Unit 20ms Blanking Time Tj >130C Thermal Shutdown Latch Reset Brownout mode 40ms Blanking Time & G2 Latch Mode R Q Power Management ICE3ARxxx80CJZ / CoolSET(R)-F3R80CCM Vcs_burst VFB_burst Burst detect and adjust RFB 5.0V 8V Vcc 1V 0.4V 0.4V 25.5V Vcc 1V 1.25V VCC Snubber RSense CS GND + Converter DC Output VOUT - 2 CBR0 85 ... 270 VAC CBulk CoolSET(R)-F3R80 ICE3AR4780CJZ Representative Blockdiagram Representative Blockdiagram Representative Blockdiagram 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Functional Description 3 Functional Description 3.2 All values which are used in the functional description are typical values. For calculating the worst cases the min/max values which can be found in section 4 Electrical Characteristics have to be considered. 3.1 Power Management Drain VCC Startup Cell CoolMOS (R) Introduction ICE3ARxx80CJZ brownout and CCM 800V version is an enhanced version of the CoolSET(R)-F3R80. The major new and enhanced features include slope compensation for CCM operation, fast AC reset after latch enabled, fixed voltage brownout detect and voltage detect for the burst selection. It is particular good for high voltage margin low power SMPS application such as auxiliary power supply for PC and server. The major characteristics are that the IC is developed with 800V CoolMOS(R) with start up cell, having adjustable brownout feature, running at 100KHz switching frequency, CCM operation and packed in DIP-7 package. The features include BiCMOS technology to reduce power consumption and increase the Vcc voltage range, cycle by cycle current mode control, built-in 10ms soft start to reduce the stress of switching elements during start up, built-in 40ms for short period of peak power before entering protection, active burst mode for lowest standby power, propagation delay compensation for close power limit between high line and low line which also takes into consideration of slope compensation, frequency jittering for low EMI performance, the built-in auto-restart mode protections for open loop, over load, Vcc OVP, Vcc under voltage, and latch enable feature etc. The other features include narrowing the feedback voltage swing to 0.3V (from 0.5V) during burst mode so that the output voltage ripple can be reduced by 40%, reduction of the fast voltage fall time of the MOSFET by increasing the soft turn-on time and addition of 50 turn-on resistor, faster start up time by optimizing the Vcc capacitor to 10uF and over temperature protection with 50C hysteresis. The new features include slope compensation for stable operation in CCM mode when duty is larger than 0.5, fixed voltage triggering for the bronwout feature for easier design, voltage levels select for entry/exit burst level, fast AC reset fto reset the latch feature, etc. In summary, the CoolSET(R) ICE3ARxx80CJZ provides good voltage margin of MOSFET, lowest standby power, flexible burst level, CCM operation, reduced output ripple during burst mode, accurate power limit for both maximum power and burst power, low EMI with frequency jittering and soft gate drive, built-in and flexible protections, etc. Therefore, CoolSET(R) ICE3ARxx80CJZ is a complete solution for the low power SMPS application. Version 2.0 Power Management Internal Bias Latched Off Mode Reset; V VCC < 8V or AC fast reset is triggered Power-Down Reset Undervoltage Lockout 17V 10.5V Voltage Reference 5.0V Auto Restart Mode Soft Start block Active Burst Mode Latched Off Mode Figure 3 Power Management The Undervoltage Lockout monitors the external supply voltage VVCC. When the SMPS is plugged to the main line the internal Startup Cell is biased and starts to charge the external capacitor CVCC which is connected to the VCC pin. This VCC charge current is controlled to 1.0mA by the Startup Cell. When the VVCC exceeds the on-threshold VCCon=17V the bias circuit are switched on. Then the Startup Cell is switched off by the Undervoltage Lockout and therefore no power losses present due to the connection of the Startup Cell to the Drain voltage. To avoid uncontrolled ringing at switch-on, a hysteresis start up voltage is implemented. The switch-off of the controller can only take place when VVCC falls below 10.5V after normal operation was entered. The maximum current consumption before the controller is activated is about 210A. When VVCC falls below the off-threshold VCCoff=10.5V, the bias circuit is switched off and the soft start counter is reset. Thus it ensures that at every startup cycle the soft start starts at zero. The internal bias circuit is switched off if Latched Off Mode or Auto Restart Mode is entered. The current consumption is then reduced to 420A. Once the malfunction condition is removed, this block will then turn back on. The recovery from Auto Restart Mode does not require re-cycling the AC line. In case Latched Off Mode is entered, VCC needs to be lowered below 8V or having AC fast reset triggered to reset the 8 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Functional Description Latched Off Mode. This is done usually by re-cycling the AC line. When Active Burst Mode is entered, the internal Bias is switched off most of the time but the Voltage Reference is kept alive in order to reduce the current consumption below 620A. 3.3 In case the amplified current sense signal exceeds the FBB signal the on-time ton of the driver is finished by resetting the PWM-Latch (Figure 5). The primary current is sensed by the external series resistor RSense inserted in the source of the integrated CoolMOS(R). By means of Current Mode regulation, the secondary output voltage is insensitive to the line variations. The current waveform slope will change with the line variation, which controls the duty cycle. The external RSense allows an individual adjustment of the maximum source current of the integrated CoolMOS(R). To improve the Current Mode during light load conditions the amplified current ramp of the PWM-OP is superimposed on a voltage ramp, which is built by the switch T2, the voltage source V1 and a resistor R1 (see Figure 6). Every time the oscillator shuts down for maximum duty cycle limitation the switch T2 is closed by VOSC. When the oscillator triggers the Gate Driver, T2 is opened so that the voltage ramp can start. Improved Current Mode Soft-Start Comparator PWM-Latch FBB C8 R Q Driver S Q 0.6V Soft-Start Comparator PWM OP PWM Comparator x3.25 CS FBB C8 Improved Current Mode Figure 4 PWM-Latch Oscillator VOSC Current Mode time delay circuit (156ns) Current Mode means the duty cycle is controlled by the slope of the primary current. This is done by comparing the FBB signal with the amplified current sense signal. Gate Driver 0.6V 10k Amplified Current Signal X3.25 T2 FBB R1 V1 PWM OP 0.6V Driver Voltage Ramp t Figure 6 t on t Figure 5 Pulse Width Modulation Version 2.0 Improved Current Mode In case of light load the amplified current ramp is too small to ensure a stable regulation. In that case the Voltage Ramp is a well defined signal for the comparison with the FBB-signal. The duty cycle is then controlled by the slope of the Voltage Ramp. By means of the time delay circuit which is triggered by the inverted VOSC signal, the Gate Driver is switched-off until it reaches approximately 156ns delay time (Figure 9 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Functional Description 7). It allows the duty cycle to be reduced continuously till 0% by decreasing VFBB below that threshold. 5V RFB VOSC Soft-Start Comparator max. Duty Cycle FBB PWM-Latch C8 Voltage Ramp PWM Comparator t 0.6V 0.6V Optocoupler FBB PWM OP CS Gate Driver X3.25 t 156ns time delay Improved Current Mode t Figure 7 3.3.1 Light Load Conditions PWM Controlling 3.3.3 Slope Compensation Due to the sub harmonic oscillation of CCM operation when duty cycle is larger than 50%, the slope compensation is added. The slope Mc; 50mV/s is added to the current sense pin when gate is on. During burst mode operation, the Mc slope is shut down and no slope added into the current sense signal. This can save the power consumption at burst mode. PWM-OP The input of the PWM-OP is applied over the internal leading edge blanking to the external sense resistor RSense connected to pin CS. RSense converts the source current into a sense voltage. The sense voltage is amplified with a gain of 3.25 by PWM OP. The output of the PWM-OP is connected to the voltage source V1. The voltage ramp with the superimposed amplified current signal is fed into the positive inputs of the PWMComparator C8 and the Soft-Start-Comparator (Figure 8). 3.3.2 Figure 8 C8 PWM comparator PWM-Comparator The PWM-Comparator compares the sensed current signal of the integrated CoolMOS(R) with the feedback signal VFBB (Figure 8). VFBB is created by an external optocoupler or external transistor in combination with the internal pull-up resistor RFB and provides the load information of the feedback circuitry. When the amplified current signal of the integrated CoolMOS(R) exceeds the signal VFBB the PWM-Comparator switches off the Gate Driver. Slope compensation 5.0V Gate Drive signal Mc=50mV/us 0.62V S5 x3.25 PWM OP LEB 180/220ns Rslope 10k CS 1pF D2 Active burst mode Figure 9 Version 2.0 PWM latch FB 10 Slope compesnation 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Functional Description 3.4 Startup Phase The function is realized by an internal Soft Start resistor, an current sink and a counter. And the amplitude of the current sink is controlled by the counter (Figure 12). Soft Start counter 5V Soft Start finish R SoftS SoftS SoftS Soft Start Soft Start Soft-Start Com parator G ate Driver C7 & Soft Start 32I Counter G7 8I 4I 2I I 0.6V x3.25 CS Figure 12 PW M O P Figure 10 Soft Start Circuit After the IC is switched on, the VSoftS voltage is controlled such that the voltage is increased stepwisely (32 steps) with the increase of the counts. The Soft Start counter would send a signal to the current sink control in every 300s such that the current sink decrease gradually and the duty ratio of the gate drive increases gradually. The Soft Start will be finished in 10ms (tSoft-Start) after the IC is switched on. At the end of the Soft Start period, the current sink is switched off. Within the soft start period, the duty cycle is increasing from zero to maximum gradually (see Figure 13). Soft Start In the Startup Phase, the IC provides a Soft Start period to control the primary current by means of a duty cycle limitation. The Soft Start function is a built-in function and it is controlled by an internal counter. . V SoftS tSoft-Start V SOFTS32 V S o ftS Gate Driver V S o ftS 2 V S o ftS 1 t t Figure 11 Soft Start Phase Figure 13 When the VVCC exceeds the on-threshold voltage, the IC starts the Soft Start mode (Figure 11). Version 2.0 11 Gate drive signal under Soft-Start Phase 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Functional Description In addition to Start-Up, Soft-Start is also activated at each restart attempt during normal Auto Restart. 3.5 PWM Section 0.75 V S o ftS PWM Section Oscillator t S o ft-S ta rt Duty Cycle max V S O FT S 3 2 Clock V FB Frequency Jitter t 4.5V Soft Start Block V OUT Soft Start Comparator V OUT PWM Comparator t S ta rt-U p 1 G8 Gate Driver S R Q & G9 Current Limiting t Figure 14 FF1 t CoolMOS(R) Gate Start Up Phase The Start-Up time tStart-Up before the converter output voltage VOUT is settled, must be shorter than the SoftStart Phase tSoft-Start (Figure 14). By means of Soft-Start there is an effective minimization of current and voltage stresses on the integrated CoolMOS(R), the clamp circuit and the output rectifier and it helps to prevent saturation of the transformer during Start-Up. Figure 15 PWM Section Block 3.5.1 Oscillator The oscillator generates a fixed frequency of 100KHz with frequency jittering of 4% (which is 4KHz) at a jittering period of 4ms. A capacitor, a current source and current sink which determine the frequency are integrated. The charging and discharging current of the implemented oscillator capacitor are internally trimmed in order to achieve a very accurate switching frequency. The ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of Dmax=0.75. Once the Soft Start period is over and when the IC goes into normal operating mode, the switching frequency of the clock is varied by the control signal from the Soft Start block. Then the switching frequency is varied in range of 100KHz 4KHz at period of 4ms. 3.5.2 PWM-Latch FF1 The output of the oscillator block provides continuous pulse to the PWM-Latch which turns on/off the integrated CoolMOS(R). After the PWM-Latch is set, it is reset by the PWM comparator, the Soft Start comparator or the Current -Limit comparator. When it is in reset mode, the output of the driver is shut down immediately. Version 2.0 12 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Functional Description 3.5.3 3.6 Gate Driver Current Limiting VCC PWM Latch FF1 PWM-Latch 1 Current Limiting Propagation-Delay Compensation 50 Vcsth LEB 220ns C10 Gate S4 PWM-OP LEB 180ns & CoolMOS(R) C12 G6 VCSth_burst Propagation-Delay Compensation-Burst Gate Driver Figure 16 Active Burst Mode Gate Driver or The driver-stage is optimized to minimize EMI and to provide high circuit efficiency. This is done by reducing the switch on slope when exceeding the integrated CoolMOS(R) threshold. This is achieved by a slope control of the rising edge at the driver's output (Figure 17) and adding a 50 gate turn on resistor (Figure 16). Thus the leading switch on spike is minimized. G8 VFB_burst FBB CS Current Limiting Block There is a cycle by cycle peak current limiting operation realized by the Current-Limit comparator C10. The source current of the integrated CoolMOS(R) is sensed via an external sense resistor RSense. By means of RSense the source current is transformed to a sense voltage VSense which is fed into the pin CS. If the voltage VSense exceeds the internal threshold voltage Vcsth, the comparator C10 immediately turns off the gate drive by resetting the PWM Latch FF1. A Propagation Delay Compensation is added to support the immediate shut down of the integrated CoolMOS(R) with very short propagation delay. Thus the influence of the AC input voltage on the maximum output power can be reduced to minimal. This compensation applies to both the peak load and burst mode. In order to prevent the current limit from distortions caused by leading edge spikes, a Leading Edge Blanking (LEB) is integrated in the current sense path for the comparators C10, C12 and the PWM-OP. The output of comparator C12 is activated by the Gate G6 if Active Burst Mode is entered. When it is activated, the current limiting is reduced to Vcsth_burst. This voltage level determines the maximum power level in Active Burst Mode. (internal) VGate typ. t = 160ns 4.6V t Gate Rising Slope Furthermore the driver circuit is designed to eliminate cross conduction of the output stage. During power up, when VCC is below the undervoltage lockout threshold VVCCoff, the output of the Gate Driver is set to low in order to disable power transfer to the secondary side. Version 2.0 1pF D1 Figure 18 Figure 17 10k C5 13 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Functional Description 3.6.1 Leading Edge Blanking slope is depending on the AC input voltage. Propagation Delay Compensation is integrated to reduce the overshoot due to dI/dt of the rising primary current. Thus the propagation delay time between exceeding the current sense threshold Vcsth and the switching off of the integrated CoolMOS(R) is compensated over temperature within a wide input range. Current Limiting is then very accurate. For the inherit influence of the CCM operation, the final Vcs can not be constant in whole line range as in DCM. This ICE3ARxx80CJZ has implemented with 2 compensation curves for the compensation so that the maximum power can be close. One of the curve is used when the time range is larger than 4s and the other is for lower than 4s. The Propagation Delay Compensation is realized by means of a dynamic threshold voltage Vcsth (Figure 21). In case of a steeper slope the switch off of the driver is earlier to compensate the delay. VSense Vcsth tLEB = 220ns/180ns t Figure 19 Leading Edge Blanking Whenever the integrated CoolMOS(R) is switched on, a leading edge spike is generated due to the primaryside capacitances and reverse recovery time of the secondary-side rectifier. This spike can cause the gate drive to switch off unintentionally. In order to avoid a premature termination of the switching pulse, this spike is blanked out with a time constant of tLEB = 220ns for normal load and tLEB = 180ns for burst mode. 3.6.2 VOSC Combined OPP curve considering Propagation Delay and Slope Compensation off time V Sense The ICE3ARxx80CJZ has combined the propagation delay, CCM inherit reduced power effect and the slope compensation effect for the overcurrent control. It employs the dynamic threshold voltage Vcsth with 2 steps slope compensation to achieve the closed over current for whole input voltage range. In case of overcurrent detection, there is always propagation delay to switch off the integrated CoolMOS(R). An overshoot of the peak current Ipeak is induced to the delay, which depends on the ratio of dI/ dt of the peak current (Figure 20). Signal2 ISense Propagation Delay t Vcsth Signal1 Signal2 t Figure 21 Dynamic Voltage Threshold Vcsth A typical measured Vsense vs dVsense/dt is plotted in Figure 22 for reference. Signal1 tPropagation Delay 0.800 IOvershoot2 0.780 VSense (V) Ipeak2 Ipeak1 ILimit max. Duty Cycle IOvershoot1 0.760 0.740 0.720 0.700 t Figure 20 0.000 Current Limiting 0.200 0.300 0.400 0.500 0.600 0.700 dVsenses The overshoot of Signal2 is larger than of Signal1 due to the steeper rising waveform. This change in the Version 2.0 0.100 Figure 22 14 Overcurrent Shutdown 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Functional Description Similarly, the same concept of propagation delay compensation is also implemented in burst mode with reduced level, Vcsth_burst (Figure 18). With this implementation, the entry and exit burst mode power can be close between low line and high line input voltage. 3.7 CS Vcsth_burst C12 G6 & FF1 Internal Bias Burst detect and adjust Control Unit The Control Unit contains the functions for Active Burst Mode, Auto Restart Mode and Latch Mode. The Active Burst Mode, Latch Mode and the Auto Restart Mode both have internal blanking time. With the blanking time, the IC avoids entering into those two modes accidentally. Those buffer time is very useful for the application which works in short duration of peak power occasionally. 20 ms Blanking Time VFB_burst C5 FBB Active Burst Mode C13 4.0V Rsel 3.5V C6a 3.7.1 Active Burst Mode (patented) To increase the efficiency of the system at light load, the most effective way is to operate at burst mode. Starting from CoolSET(R) F3, the IC has been employing the active burst mode and it can achieve the lowest standby power. ICE3ARxx80CJZ adopts the same concept with some more innovative improvements to the feature. It includes the adjustable entry burst level, close power control between high line and low line and the smaller output ripple during burst mode. Most of the burst mode design in the market will provide a fixed entry burst mode level which is a ratio to the maximum power of the design. ICE3ARxx80CJZ provides a more flexible level which can be selected externally. Propagation delay is the major contributor for the power control variation for DCM flyback converter. It is proved to be effective in the maximum power control. ICE3ARxx80CJZ also apply the same concept in the burst mode. Therefore, the entry and exit burst mode power is also finely controlled during burst mode. The feedback control swing during burst mode will affect the output ripple voltage directly. ICE3ARxx80CJZ reduces the swing to 0.3V (from 0.5V). Therefore, it would have around 40% improvement for the output ripple. & G11 C6b 3.2V Figure 23 Control Unit Active Burst Mode The Active Burst Mode is located in the Control Unit. Figure 23 shows the related components. 3.7.1.1 Selectable burst entry level The burst mode entry level can be selected by changing the different Resistor Rsel at FBB pin. There are 3 levels to be selected with different resistor which are targeted for 15%, 10% and 5% of the maximum input power. At the same time, the exit burst level are targeted to 27%, 20% and 11% of the maximum power accordingly. The below table is the control logic for the entry and exit level with the FBB voltage. Level VFBB Rsel < 405k 1 VFBB< Vref1 (1.8V) 2 Vref1 (1.8V) <VFBB<Vref2 (4.0V) 3 VFBB > Vref2 (4.0V) 15 685k ~ 900k > 1530k Entry level Version 2.0 Current Limiting Exit level Level % of Pin_max VFB_burst % of Pin_max 1 5% 1.29V 11% 0.21V 2 10% 1.61V 20% 0.29V 3 15% 1.84V 27% 0.34V Vcsth_burst 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Functional Description During IC first startup, the Refgood signal is logic low when Vcc<8V. The low Refgood signal will reset the Burst Mode level Detection latch. When the Burst Mode Level Detection latch is low and IC is in OFF state, the FBB resistor is isolated from the FBB pin and a current source Isel (3.5) is turned on instead. From Vcc=8V to Vcc on threshold(17V), the FBB pin will start to charge to a voltage level associated with Rsel resistor. When Vcc reaches Vcc on threshold, the FBB voltage is sensed. The burst mode thresholds are then chosen according to the FBB voltage level. The Burst Mode Level Detection latch is then set to high. Once the detection latch is set high, any change of the FBB level will not change the threshold level. When Vcc reaches Vcc on threshold, a timer of 2s is started. After the 2s ends, the Isel is turned off while the FBB resistor is connected to FBB pin (Figure 24). 3.7.1.3 Working in Active Burst Mode After entering the Active Burst Mode, the FBB voltage rises as VOUT starts to decrease, which is due to the inactive PWM section. The comparator C6a monitors the FBB signal. If the voltage level is larger than 3.5V, the internal circuit will be activated; the Internal Bias circuit resumes and starts to provide switching pulse. In Active Burst Mode the gate G6 is released and the current limit is reduced to Vcsth_burst (Figure 2 and 23). In one hand, it can reduce the conduction loss and the other hand, it can reduce the audible noise. If the load at VOUT is still kept unchanged, the FBB signal will drop to 3.2V. At this level the C6b deactivates the internal circuit again by switching off the Internal Bias. The gate G11 is active again as the burst flag is set after entering Active Burst Mode. In Active Burst Mode, the FBB voltage is changing like a saw tooth between 3.2V and 3.5V (Figure 25). 3.7.1.4 Leaving Active Burst Mode The FBB voltage will increase immediately if there is a high load jump. This is observed by the comparator C13 (Figure 23). Since the current limit is reduced to 0.21V~0.34V during active burst mode, it needs a certain load jump to rise the FBB signal to exceed 4.0V. At that time the comparator C5 resets the Active Burst Mode control which in turn blocks the comparator C12 by the gate G6. The maximum current can then be resumed to stabilize VOUT. Vdd Isel UVLO S2 2s delay Rfb Refgood S1 Burst mode detection latch Vcsth_burst VFB_burst Selection Logic Compare logic FBB Vref1 Rsel S R Vref2 Control unit Figure 24 Burst mode detect and adjust 3.7.1.2 Entering Active Burst Mode The FBB signal is kept monitoring by the comparator C5 (Figure 23). During normal operation, the internal blanking time counter is reset to 0. When FBB signal falls below VFB_burst, it starts to count. When the counter reaches 20ms and FBB signal is still below VFB_burst, the system enters the Active Burst Mode. This time window prevents a sudden entering into the Active Burst Mode due to large load jumps. After entering Active Burst Mode, a burst flag is set and the internal bias is switched off in order to reduce the current consumption of the IC to about 620A. It needs the application to enforce the VCC voltage above the Undervoltage Lockout level of 10.5V such that the Startup Cell will not be switched on accidentally. Or otherwise the power loss will increase drastically. The minimum VCC level during Active Burst Mode depends on the load condition and the application. The lowest VCC level is reached at no load condition. Version 2.0 16 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Functional Description VFBB Entering Active Burst Mode 4.0V 3.5V 3.2V 3.7.2 Protection Modes The IC provides Auto Restart mode as the major protection feature. Auto Restart mode can prevent the SMPS from destructive states. There are 3 kinds of auto restart mode; normal auto restart mode, odd skip auto restart mode and non switch auto restart mode. Odd skip auto restart mode (Figure 26) is that there is no detect of fault and no switching pulse for the odd number restart cycle. At the even number of restart cycle the fault detect and soft start switching pulses are maintained. If the fault persists, it would continue the auto-restart mode. However, if the fault is removed, it can release to normal operation only at the even number auto restart cycle . Leaving Active Burst Mode VFB_burst Blanking Timer t 20ms Blanking Time VCS t VVCC Fault detected No detect Startup and detect No detect 17V Vcsth Current limit level during Active Burst Mode 10.5V Vcsth_burst VCS VVCC t t t Figure 26 10.5V IVCC Non switch auto restart mode is similar to odd skip auto restart mode except the start up switching pulses are also suppressed at the even number of the restart cycle. The detection of fault still remains at the even number of the restart cycle. When the fault is removed, the IC will resume to normal operation at the even number of the restart cycle (Figure 27). t 3.4mA 620uA VOUT Odd skip auto restart waveform t VVCC Fault detected No detect Startup and detect No detect 17V 10.5V VCS t Figure 25 t No switching Signals in Active Burst Mode t Figure 27 non switch auto restart waveform The main purpose of the odd skip auto restart is to extend the restart time such that the power loss during auto restart protection can be reduced. This feature is particularly good for smaller Vcc capacitor where the restart time is shorter. Version 2.0 17 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Functional Description mode after 210s blanking time. The gate drive is stopped and there is no switching pulse before it is recovered . The Vcc undervoltage and short opto-coupler will go into the normal auto restart mode inherently. In case of VCC undervoltage, the Vcc voltage drops indefinitely. When it drops below the Vcc under voltage lock out "OFF" voltage (10.5V), the IC will turn off the IC and the startup cell will turn on again. Then the Vcc voltage will be charged up to UVLO "ON" voltage (17V) and the IC turns on again provided the startup cell charge up current is not drained by the fault. If the fault is not removed, the Vcc will continue to drop until it hits UVLO "OFF" voltage and the restart cycle repeats. Short Optocoupler can lead to Vcc undervoltage because once the opto-coupler (transistor side) is shorted, the feedback voltage will drop to zero and there will be no switching pulse. Then the Vcc voltage will drop same as the Vcc undervoltage. The following table lists the possible system failures and the corresponding protection modes. VCC Over voltage Odd skip Auto Restart Mode Over load Odd skip Auto Restart Mode Open Loop Odd skip Auto Restart Mode VCC Undervoltage Normal Auto Restart Mode Short Optocoupler Normal Auto Restart Mode Over temperature Non switch Auto Restart Mode External protection enable Latch Mode 3.7.2.1 Vcc OVP, OTP, external protection enable and Vcc under voltage 210s blanking time BRL 0.4V 3.7.2.2 Over load, open loop protection Auto Restart Mode Reset VVCC < 10.5V Stop gate drive C9 TLE Latch mode Latch Enable Signal 5.0V Thermal Shutdown Tj >130C 25.5V C2 120s blanking time Spike Blanking 30s Auto Restart mode RFB VCC FBB Control Unit Figure 28 C4 Voltage Reference 4.5V Auto Restart Mode Control Unit Vcc OVP, OTP, external protection enable Figure 29 Vcc OVP condition is when VVCC voltage is > 25.5V, the IC enters into odd skip Auto Restart Mode (Figure 28). The over temperature protection OTP is sensed inside the controller IC. The Thermal Shutdown block keeps on monitoring the junction temperature of the controller. After detecting a junction temperature higher than 130C, the IC will enter into the non switch Auto Restart mode. The ICE3ARxx80CJZ has also implemented with a 50C hysteresis. That means the IC can only be recovered when the controller junction temperature is dropped 50C lower than the over temperature trigger point (Figure 28). The external latch enable feature can provide a flexibility to a customer's self-defined protection feature. This function can be triggered by pulling down the VBRL voltage to < 0.4V. Or it can simply trigger the base pin of an external transistor, TLE at the BRL pin. When this function is enabled, it will enter into latch Version 2.0 40ms Blanking Time Over load and open loop protection In case of Overload or Open Loop, the VFBB voltage exceeds 4.5V which will be observed by comparator C4. Then the built-in blanking time counter starts to count. When it reaches 40ms, the odd skip Auto Restart Mode is activated (Figure 29). 3.7.3 Brownout Mode When the AC input voltage is removed, the voltage at the bulk capacitor will fall. When it reaches a point that the system is greater than the system allowed maximum power, the system may go into over load protection. However, this kind of protection is not expected for some of the applications such as auxiliary power for PC/server system because the output is in hiccup mode due to over load protection (auto restart mode). The brownout mode is to eliminate this phenomenon. The ICE3ARxx80CJZ will sense the 18 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Functional Description input AC voltage to the BRL pin by an AC hold up circuit and 2 potential divider resistors. In some applications, it needs the IC to continue to work for certain time when AC voltage is disconnected. After that, the IC will stop working. If the brownout connection is taping from the bulk capacitor, the delay time is too short. Therefore, it needs the brown out detetction at the AC input (Figure 30). The CBR0 is charged up by AC line voltage through RBO0, which is then fed to BRL pin through a voltage divider. When the AC voltage drops, if the BRL pin voltage is lower than 1V for 270s, the ICE3ARxx80CJZ will go into brownout mode. If, however, the AC line goes up again, the BRL voltage will be larger than 1.25V and the ICE3ARxx80CJZ will leave brown out mode and recover to normal operation. The brownout mode is default "ON" during the system starts up. When the system is powered up, the bulk capacitor and the Vcc capacitor are charged up at the same time. When the Vcc voltage is charged to >8V, the brownout circuit starts to operate (Figure 30). Since the UVLO is still at low level as the Vcc voltage does not reach the 17V UVLO "ON" voltage. The NAND gate G20 will release a low signal to the flip flop FF2 and the negative output of FF2 will release a high signal. Hence it is in brownout mode during the system starts up. 10.5V VCS Figure 31 3.7.4 Fast AC reset During normal operation, the ICE3ARxx80CJZ can be latched by pulling down the BRL voltage below 0.4V for 210s. There are 2 condtions to reset the latch feature. The first one is to pull down the Vcc voltage to below 8V. However, the Vcc drop would take quite a long time if it is by normal AC power down. The second one is to have a slow rise time of the BRL voltage from 0.4V to 1V for at least 450s after the BRL pin is pulled down. This timing can be achieved by the AC recycle. And it is also called the fast AC reset (Figure 32). R BRL 1V Q Vac FF2 C1b RBO2 Q S C1a Brownout mode waveform If the brownout feature is not needed, it needs to tie the BRL pin to the Vcc pin through a current limiting resistor, 5M~10M. The BRL pin cannot be in floating condition. CBR0 RBO1 t t Brownout mode 1.25V Startup and detect BBL voltage 17V Vac RBO0 Brownout detected VVCC RBO0 G21 0.4V Blanking Time 270s RBO1 G20 TLE Figure 30 Blanking time 210us C2a Blanking time 450s 0.4V Control Unit UVLO C3 Latch Mode CBR0 Brownout detection circuit Latch Enable Signal Once the system enters the brownout mode, there will be no switching pulse and the IC enters into another type auto-restart mode which is similar to the protection auto-restart mode but the IC will monitor the BRL signal in each restart cycle (Figure 31). BRL RBO2 C2b 1V G3 Vcc C11 8V Figure 32 & G2 Latch Reset Control Unit Latch and fast AC reset Figure 33 shows different latch and reset cases. Case a : not latched (solid line); the timing below 0.4V is 150s and is less than 210s. Version 2.0 19 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Functional Description Case b : latched (dashed line); the timing below 0.4V is 450s which is larger than 210s. No latch reset as the rise time from 0.4V to 1V is 300s which is less than the 450s. Case c : latched and reset (dotted line); the timing below 0.4V is 710s which is larger than 210s. But the rise time from 0.4V to 1V is 560s which is larger than the latch reset blanking time of 450s. VBRL 150s 710s 560s Latched and reset (c) 450s 300s Latched (b) Not latched (a) 1V 0.4V t Figure 33 Version 2.0 Latch and fast AC reset example 20 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Electrical Characteristics 4 Electrical Characteristics Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are not violated. 4.1 Note: Absolute Maximum Ratings Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is discharged before assembling the application circuit. Ta=25C unless otherwise specified. Parameter Drain Source Voltage Pulse drain current, tp limited by Tjmax Symbol Limit Values min. max. VDS - 800 Unit V ID_Puls - 1.95 A Avalanche energy, repetitive tAR limited by max. Tj=150C1) EAR - 0.024 mJ Avalanche current, repetitive tAR limited by max. Tj=150C IAR - 0.95 A VCC Supply Voltage VVCC -0.3 27 V FBB Voltage VFBB -0.3 5.5 V BRL Voltage VBRL -0.3 5.5 V CS Voltage VCS -0.3 5.5 V Tj -40 150 C Junction Temperature Remarks Controller & CoolMOS(R) TS -55 150 C Thermal Resistance Junction -Ambient RthJA - 96 K/W Soldering temperature, wavesoldering only allowed at leads Tsold - 260 C 1.6mm (0.063in.) from case for 10s ESD Capability (incl. Drain Pin) VESD - 2 kV Human body model2) Storage Temperature 1) Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f 2) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor) Version 2.0 21 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Electrical Characteristics 4.2 Note: Operating Range Within the operating range the IC operates as described in the functional description. Parameter Symbol Limit Values Unit Remarks min. max. VCC Supply Voltage VVCC VVCCoff 24.7 V Max value limited due to Vcc OVP Junction Temperature of Controller TjCon -25 130 C Max value limited due to thermal shut down of controller Junction Temperature of CoolMOS(R) TjCoolMOS -25 150 C 4.3 4.3.1 Note: Characteristics Supply Section The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range TJ from - 25 C to 125 C. Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC = 17 V is assumed. Parameter Symbol Limit Values Unit Test Condition min. typ. max. IVCCstart - 210 300 A VVCC =16V IVCCcharge1 - - 5.0 mA VVCC = 0V IVCCcharge2 0.55 1.0 1.60 mA VVCC = 1V IVCCcharge3 0.38 0.75 - mA VVCC =16V Leakage Current of Start Up Cell and CoolMOS(R) IStartLeak - 0.2 50 A VDrain = 650V at Tj=100C 1) Supply Current with Inactive Gate IVCCsup1 - 1.9 3.2 mA Supply Current with Active Gate IVCCsup2 - 3.4 4.8 mA IFBB = 0A Supply Current in Latched Off Mode with Inactive Gate IVCClatch - 420 - A IFBB = 0A Supply Current in Auto Restart Mode with Inactive Gate IVCCrestart - 420 - A IFBB = 0A Supply Current in Active Burst Mode with Inactive Gate IVCCburst1 - 620 950 A VFBB = 2.5V IVCCburst2 - 620 950 A VVCC = 11.5V, VFBB = 2.5V VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hysteresis VVCCon VVCCoff VVCChys 16.0 9.8 - 17.0 10.5 6.5 18.0 11.2 - V V V Start Up Current VCC Charge Current 1) The parameter is not subjected to production test - verified by design/characterization Version 2.0 22 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Electrical Characteristics 4.3.2 Internal Voltage Reference Parameter Trimmed Reference Voltage 4.3.3 Symbol VREF Limit Values Unit min. typ. max. 4.90 5.00 5.10 V Test Condition measured at pin FBB IFBB = 0A PWM Section Parameter Symbol Limit Values Unit Test Condition min. typ. max. fOSC1 87 100 113 kHz fOSC2 92 100 108 kHz Tj = 25C Frequency Jittering Range fjitter - 4.0 - kHz Tj = 25C Frequency Jittering period Tjitter - 4.0 - ms Tj = 25C Max. Duty Cycle Dmax 0.70 0.75 0.80 Min. Duty Cycle Dmin - - 0 PWM-OP Gain AV 3.17 3.25 3.33 VOffset-Ramp - 0.60 - V VFBB Operating Range Min Level VFBmin - 0.7 - V VFBB Operating Range Max level VFBmax - - 4.4 V FBB Pull-Up Resistor RFB 9.0 15.4 22.0 k Slope Compensation rate MC 45 50 55 mV/s Fixed Oscillator Frequency Voltage Ramp Offset 1) VFBB < 0.3V dVsense / dt = 0.134V/s , limited by Comparator C41) CS=0V The parameter is not subjected to production test - verified by design/characterization 4.3.4 Soft Start time Parameter Soft Start time Version 2.0 Symbol tSS Limit Values Unit min. typ. max. - 10 - 23 Test Condition ms 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Electrical Characteristics 4.3.5 Control Unit Parameter Symbol Limit Values Unit min. typ. max. Test Condition Brownout reference voltage for comparator C1a VBO_L 1.14 1.25 1.36 V Brownout reference voltage for comparator C1b VBO_E 0.91 1 1.09 V Leakage current of BRL pin Ileakage -0.5 - 0.5 Blanking time to enter brownout mode VBKC1b 190 270 310 s Fast AC reset voltage for comparator C2a VC2a 0.3 0.4 0.5 V Fast AC reset voltage for comparator C2b VC2b 0.91 1 1.09 V VBKC2a 315 450 585 s Isel 2.8 3.5 4.2 Burst mode selection reference voltage Vref1 1.69 1.80 1.91 V Vref2 3.78 4.00 4.22 V Over Load Limit for Comparator C4 VFBC4 4.40 4.50 4.72 V 15% Pin_max VFB_burst1 1.77 1.84 1.91 V Vfbb>Vref2 10% Pin_max VFB_burst2 1.50 1.61 1.72 V Vref1<Vfbb<Vref2 5% Pin_max Blanking time for comparator C2a Charging current to select burst mode Active Burst Mode Entry level for Comparator C5 VFB_burst3 1.20 1.29 1.38 V Vfbb<Vref1 Active Burst Mode High Level for Comparator C6a VFBC6a 3.35 3.50 3.65 V In Active Burst Mode Active Burst Mode Low Level for Comparator C6b VFBC6b 3.06 3.20 3.34 V Active Burst Mode Level for Comparator C9 VFBC9 3.85 4.00 4.15 V VVCCOVP 24.7 25.5 26.3 V VLE 0.3 0.4 0.5 V tBK_latch 140 210 295 s TjSD 130 140 150 C Overvoltage Detection Limit for Comparator C2 Latch enable reference voltage for Comparator C3 Built-in Blanking Time to enter Latch Mode Thermal Shutdown1) Hysteresis for thermal Shutdown 1) TjSD_hys - 50 - C Built-in Blanking Time for Overload Protection tBK - 40 - ms Built-in Blanking Time for entering Active Burst Mode tBK_burst - 20 - ms Spike Blanking Time for Vcc OVP tSpike - 150 - s Version 2.0 24 Controller 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Electrical Characteristics 1) The parameter is not subjected to production test - verified by design/characterization. The thermal shutdown temperature refers to the junction temperature of the controller. Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP. 4.3.6 Current Limiting Parameter Peak Current Limitation Symbol Limit Values Unit Test Condition 0.77 V dVsense / dt = 0.41V/s 0.80 V dVsense / dt = 0.134V/s min. typ. max. Vcsth1 0.69 0.73 Vcsth2 0.72 0.76 Peak Current Limitation in Active Burst Mode 27% Pin_max Vcsth_burst1 0.313 0.34 0.368 V Vfbb>Vref2 20% Pin_max Vcsth_burst2 0.264 0.29 0.320 V Vref1<Vfbb<Vref2 11% Pin_max Vcsth_burst3 0.184 0.21 0.238 V Vfbb<Vref1 Leading Edge Blanking Normal mode tLEB_normal - 220 - ns Burst mode tLEB_burst - 180 - ns ICSbias -1.5 -0.2 - A CS Input Bias Current 4.3.7 VCS =0V CoolMOS(R) Section Parameter Symbol Limit Values Unit Test Condition min. typ. max. V(BR)DSS 800 870 - - V V Tj = 25C Tj = 110C1) Drain Source On-Resistance RDSon - 4.70 10.45 12.76 5.18 11.50 14.04 Tj = 25C Tj=125C1) Tj=150C1) at ID = 0.58A Effective output capacitance, energy related Co(er) - 7.2 - pF VDS = 0V to 480V Rise Time trise - 302) - ns Fall Time tfall - 302) - ns Drain Source Breakdown Voltage 1) The parameter is not subjected to production test - verified by design/characterization 2) Measured in a Typical Flyback Converter Application Version 2.0 25 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ CoolMOS(R) Perfromance Characteristic 5 CoolMOS(R) Perfromance Characteristic Safe Operating Area for ICE3AR4780CJZ ID = f ( V DS ) parameter : D = 0, TC = 25deg.C 10 1 ID [A] 0.1 0.01 tp = 0.1ms tp = 1ms tp = 10ms tp = 100ms DC 0.001 0.0001 1 10 100 1000 VDS [V] Figure 34 Safe Operating Area (SOA) curve for ICE3AR4780CJZ SOA temperature derating coefficient curve ( package dissipation ) for F3 & F2 CoolSET SOA temperature derating coefficient [%] 120 100 80 60 40 20 0 0 20 40 60 80 100 120 140 Ambient/Case temperature Ta/Tc [deg.C] Ta : DIP, Tc : TO220 Figure 35 Version 2.0 SOA temperature derating coefficient curve 26 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ CoolMOS(R) Perfromance Characteristic Allowable Power Dissipation for F3 CoolSET in DIP-7 package Allowable Power Dissipation, Ptot [W] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 20 40 60 80 100 120 140 Ambient temperature, T A [deg.C] Figure 36 Power dissipation; Ptot=f(Ta) Figure 37 Drain-source breakdown voltage; VBR(DSS)=f(Tj), ID=0.25mA Version 2.0 27 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Input Power Curve 6 Input Power Curve Two input power curves giving the typical input power versus ambient temperature are showed below; Vin=85Vac~265Vac (Figure 38) and Vin=230Vac+/-15% (Figure 39). The curves are derived based on a typical discontinuous mode flyback model which considers either 60% maximum duty ratio or 150V maximum secondary to primary reflected voltage (higher priority). The calculation is based on no copper area as heatsink for the device. The input power already includes the power loss at input common mode choke, bridge rectifier and the CoolMOS.The device saturation current (ID_Puls @ Tj=125C) is also considered. To estimate the output power of the device, it is simply multiplying the input power at a particular operating ambient temperature with the estimated efficiency for the application. For example, a wide range input voltage (Figure 38), operating temperature is 50C, estimated efficiency is 85%, then the estimated output power is 17W (20W * 85%). Figure 38 Input power curve Vin=85~265Vac; Pin=f(Ta) Figure 39 Input power curve Vin=230Vac+/-15%; Pin=f(Ta) Version 2.0 28 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Outline Dimension 7 Outline Dimension PG-DIP-7 (Plastic Dual In-Line Outline) Figure 40 Version 2.0 PG-DIP-7 (Pb-free lead plating Plastic Dual-in-Line Outline) 29 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Marking 8 Marking Marking Figure 41 Version 2.0 Marking for ICE3AR4780CJZ 30 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Schematic for recommended PCB layout 9 Schematic for recommended PCB layout TR1 BR1 FUSE1 L Spark Gap 3 D21 C11 bulk cap X-CAP Vo L1 C1 Spark Gap 1 C12 R11 D11 C21 GND Spark Gap 2 D11 Spark Gap 4 N C2 Y-CAP Y-CAP Z11 C16 CS C4 Y-CAP BA GND DRAIN F3 CoolSET VCC FB R13 R14 R21 D13 R23 C22 C23 C14 IC12 F3 CoolSET schematic for recommended PCB layout Figure 42 R22 NC C15 C13 * GND IC11 R12 C3 R24 IC21 R25 Schematic for recommended PCB layout General guideline for PCB layout design using F3 CoolSET (refer to Figure 42): 1. "Star Ground "at bulk capacitor ground, C11: "Star Ground "means all primary DC grounds should be connected to the ground of bulk capacitor C11 separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET device effectively. The primary DC grounds include the followings. a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11. b. DC ground of the current sense resistor, R12 c. DC ground of the CoolSET device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector of IC12 should be connected to the GND pin of IC11 and then "star "connect to the bulk capacitor ground. d. DC ground from bridge rectifier, BR1 e. DC ground from the bridging Y-capacitor, C4 2. High voltage traces clearance: High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur. a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm b. 600V traces (drain voltage of CoolSET IC11) to nearby trace: > 2.5mm 3. Filter capacitor close to the controller ground: Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin as possible so as to reduce the switching noise coupled into the controller. Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 42): 1. Add spark gap Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated charge during surge test through the sharp point of the saw-tooth plate. a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1: Gap separation is around 1.5mm (no safety concern) Version 2.0 31 19 Apr 2013 CoolSET(R)-F3R80 ICE3AR4780CJZ Schematic for recommended PCB layout b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND: These 2 Spark Gaps can be used when the lightning surge requirement is >6KV. 230Vac input voltage application, the gap separation is around 5.5mm 115Vac input voltage application, the gap separation is around 3mm 2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input 3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12: The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET and reduce the abnormal behavior of the CoolSET. The diode can be a fast speed diode such as IN4148. The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through the sensitive components such as the primary controller, IC11. Version 2.0 32 19 Apr 2013 Total Quality Management Qualitat hat fur uns eine umfassende Bedeutung. Wir wollen allen Ihren Anspruchen in der bestmoglichen Weise gerecht werden. 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