LTC4267-1
1
42671f
Power over Ethernet
IEEE 802.3af PD Interface with
Integrated Switching Regulator
The LTC®4267-1 combines an IEEE 802.3af compliant
Powered Device (PD) interface with a current mode switch-
ing regulator, providing a complete power solution for PD
applications. The LTC4267-1 integrates the 25k signature
resistor, classifi cation current source, thermal overload
protection, signature disable and power good signal along
with an undervoltage lockout optimized for use with the
IEEE-required diode bridge. The LTC4267-1 provides an
increased operational current limit, maximizing power
available for class 3 applications.
The current mode switching regulator is designed for
driving a 6V rated N-channel MOSFET and features pro-
grammable slope compensation, soft-start, and constant
frequency operation, minimizing noise even with light
loads. The LTC4267-1 includes an onboard error amplifi er
and voltage reference allowing use in both isolated and
nonisolated confi gurations.
The LTC4267-1 is available in a space saving, low profi le
16-pin SSOP package.
■ IP Phone Power Management
■ Wireless Access Points
■ Security Cameras
■ Power over Ethernet
■ Complete Power Interface Port for IEEE 802®.3af
Powered Device (PD)
■ Onboard 100V, UVLO Switch
■ Precision Dual Level Inrush Current Limit
■ Integrated Current Mode Switching Regulator
■ Onboard 25k Signature Resistor with Disable
■ Programmable Classifi cation Current (Class 0-4)
■ Thermal Overload Protection
■ Power Good Signal
■ Integrated Error Amplifi er and Voltage Reference
■ Low Profi le 16-Pin SSOP Package
FEATURES DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
Class 2 PD with 3.3V Isolated Power Supply
17$$
183(%
/("5&
4&/4&
*5)36/
7'#
1(/%
1065
710351
3$-"44
4*(%*4"
71035/
-5$
++
3$-"44
7
M'
.*/
L
7
L
L
17$$
17$$
M'
M'
.*/
O'
•
•
1"
14
#"4
5-7
4#.
4."+"
7
"
$)"44*4
)%
o
o
)%
o7
'30.
%"5"1"*3
o7
'30.
41"3&1"*3
5"
4J
7
L
L
M'
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
LTC4267-1
2
42671f
VPORTN with Respect to VPORTP Voltage ... 0.3V to –100V
POUT, SIGDISA,
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D
Voltage ..................... VPORTN + 100V to VPORTN –0.3V
PVCC to PGND Voltage (Note 2)
Low Impedance Source ........................... –0.3V to 8V
Current Fed .......................................... 5mA into PVCC
RCLASS Voltage .................VPORTN + 7V to VPORTN – 0.3V
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D Current .....................................................10mA
RCLASS Current .....................................................100mA
NGATE to PGND Voltage ...........................–0.3V to PVCC
VFB, ITH/RUN to PGND Voltages ................–0.3V to 3.5V
SENSE to PGND Voltage .............................. –0.3V to 1V
NGATE Peak Output Current (<10s) ..........................1A
Operating Ambient Temperature Range
LTC4267C-1 ............................................. 0°C to 70°C
LTC4267I-1 ..........................................–40°C to 85°C
Junction Temperature ........................................... 150°C
Storage Temperature Range ...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
(Note 1)
The
● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VPORTN Supply Voltage Voltage with Respect to VPORTP Pin
Maximum Operating Voltage (Notes 4, 5, 6) ● –57 V
Signature Range ● –1.5 –9.5 V
Classifi cation Range ● –12.5 –21 V
UVLO Turn-On Voltage ● –34.8 –36.0 –37.2 V
UVLO Turn-Off Voltage ● –29.3 –30.5 –31.5 V
VTURNON P
VCC Turn-On Voltage Voltage with Respect to PGND ● 7.8 8.7 9.2 V
VTURNOFF P
VCC Turn-Off Voltage Voltage with Respect to PGND ● 4.6 5.7 6.8 V
VHYST P
VCC Hysteresis VTURNON – VTURNOFF ● 1.5 3.0 V
ABSOLUTE AXI U RATI GS
W
WW
U
ELECTRICAL CHARACTERISTICS
PIN CONFIGURATION
5017*&8
(/1"$,"(&
-&"%/"33081-"45*$4401
1(/%
*5)36/
/("5&
17$$
3$-"44
/$
71035/
1(/%
1(/%
7'#
4&/4&
710351
4*(%*4"
183(%
1065
1(/%
TJMAX = 150°C, θJA = 90°C/W
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4267CGN-1#PBF
LTC4267IGN-1#PBF
LTC4267CGN-1#TRPBF
LTC4267IGN-1#TRPBF
4267-1
4267I-1
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
0°C to 70°C
–40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4267CGN-1
LTC4267IGN-1
LTC4267CGN-1#TR
LTC4267IGN-1#TR
4267-1
4267I-1
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
*For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
LTC4267-1
3
42671f
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCLAMP1mA P
VCC Shunt Regulator Voltage IPVCC = 1mA, VITH/RUN = 0V, Voltage ● 8.3 9.4 10.3 V
with Respect to PGND
VMARGIN V
CLAMP1mA – VTURNON Margin ● 0.05 0.6 V
IVPORTN_ON V
PORTN Supply Current when ON VPORTN = –48V, POUT,
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D, SIGDISA Floating ● 3 mA
IPVCC_ON P
VCC Supply Current (Note 7)
Normal Operation VITH/RUN – PGND = 1.3V ● 240 350 µA
Start-Up PVCC – PGND = VTURNON – 100mV ● 40 90 µA
IVPORTN_CLASS V
PORTN Supply Current VPORTN = –17.5V, POUT Tied to VPORTP
, RCLASS, ● 0.35 0.5 0.65 mA
During Classifi cation SIGDISA Floating (Note 8)
ΔICLASS Current Accuracy 10mA < ICLASS < 40mA, –12.5V ≤ VPORTN ≤ –21V ● ±3.5 %
During Classifi cation (Note 9)
RSIGNATURE Signature Resistance –1.5V ≤ VPORTN ≤ – 9.5V, POUT Tied to VPORTP, ● 23.25 26.00 kΩ
IEEE 802.3af 2-Point Measurement (Notes 4, 5)
RINVALID Invalid Signature Resistance –1.5V ≤ VPORTN ≤ – 9.5V, SIGDISA and POUT Tied to ● 9 11.8 kΩ
V
PORTP, IEEE 802.3af 2-Point Measurement
(Notes 4, 5)
VIH Signature Disable With Respect to VPORTN ● 3 57 V
High Level Input Voltage High Level Invalidates Signature (Note 10)
VIL Signature Disable With Respect to VPORTN ● 0.45 V
Low Level Input Voltage Low Level Enables Signature
RINPUT Signature Disable, Input Resistance With Respect to VPORTN ● 100 kΩ
VPG_OUT Power Good Output Low Voltage I = 1mA VPORTN = –48V, ● 0.5 V
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D Referenced to VPORTN
Power Good Trip Point VPORTN = –48V, Voltage between VPORTN and POUT
VPG _FALL P
OUT Falling ● 1.3 1.5 1.7 V
VPG_RISE P
OUT Rising ● 2.7 3.0 3.3 V
IPG_LEAK Power Good Leakage Current VPORTN = 0V,
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D FET Off, V
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D = 57V ● 1 µA
RON On-Resistance I = 300mA, VPORTN = –48V, Measured from 1.0 1.6 Ω
V
PORTN to POUT ● 2 Ω
VITHSHDN Shutdown Threshold (at ITH/RUN) PVCC – PGND = VTURNON + 100mV ● 0.15 0.28 0.45 V
ITHSTART Start-Up Current Source at ITH/RUN VITH/RUN – PGND = 0V, PVCC – PGND = 8V 0.2 0.3 0.4 µA
VFB Regulated Feedback Voltage Referenced to PGND, PVCC – PGND = 8V (Note 11) ● 0.780 0.800 0.812 V
IFB V
FB Input Current PVCC – PGND = 8V (Note 11) 10 50 nA
gm Error Amplifi er Transconductance ITH/RUN Pin Load = ±5µA (Note 11) 200 333 500 µA/V
ΔVO(LINE) Output Voltage Line Regulation VTURNOFF < PVCC < VCLAMP (Note 11) 0.05 mV/V
ΔVO(LOAD) Output Voltage Load Regulation ITH/RUN Sinking 5µA, PVCC – PGND = 8V (Note 11) 3 mV/µA
I
TH/RUN Sourcing 5µA, PVCC – PGND = 8V (Note 11) 3 mV/µA
IPOUT_LEAK P
OUT Leakage VPORTN = 0V, Power MOSFET Off, ● 150 µA
P
OUT = 57V (Note 12)
ILIM_HI Input Current Limit, High Level VPORTN = –48V, POUT = – 43V (Note 13, 14) ● 350 450 mA
ILIM_LO Input Current Limit, Low Level VPORTN = –48V, POUT = –43V (Note 13, 14) ● 90 205 mA
fOSC Oscillator Frequency VITH/RUN – PGND = 1.3V, PVCC – PGND = 8V 180 200 240 kHz
DCON(MIN) Minimum Switch On Duty Cycle VITH/RUN – PGND = 1.3V, VFB – PGND = 0.8V, 6 8 %
P
VCC – PGND = 8V
DCON(MAX) Maximum Switch On Duty Cycle VITH/RUN – PGND = 1.3V, VFB – PGND = 0.8V, 70 80 90 %
P
VCC – PGND = 8V
ELECTRICAL CHARACTERISTICS
LTC4267-1
4
42671f
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tRISE NGATE Drive Rise Time CLOAD = 3000pF, PVCC – PGND = 8V 40 ns
tFALL NGATE Drive Fall Time CLOAD = 3000pF, PVCC – PGND = 8V 40 ns
VIMAX Peak Current Sense Voltage RSL = 0, PVCC – PGND = 8V (Note 15) ● 90 100 115 mV
ISLMAX Peak Slope Compensation Output Current PVCC – PGND = 8V (Note 16) 5 µA
tSFST Soft-Start Time PVCC – PGND = 8V 1.4 ms
TSHUTDOWN Thermal Shutdown Trip Temperature (Notes 13, 17) 140 °C
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: PVCC internal clamp circuit self regulates to 9.4V with respect to
PGND.
Note 3: The LTC4267-1 operates with a negative supply voltage in the
range of – 1.5V to – 57V. To avoid confusion, voltages for the PD interface
are always referred to in terms of absolute magnitude. Terms such as
“maximum negative voltage” refer to the largest negative voltage and
a “rising negative voltage” refers to a voltage that is becoming more
negative.
Note 4: The LTC4267-1 is designed to work with two polarity protection
diode drops between the PSE and PD. Parameter ranges specifi ed in the
Electrical Characteristics section are with respect to this product pins and
are designed to meet IEEE 802.3af specifi cations when these diode drops
are included. See the Application Information section.
Note 5: Signature resistance is measured via the two-point ΔV/ΔI method
as defi ned by IEEE 802.3af. The PD signature resistance is offset from
the 25k to account for diode resistance. With two series diodes, the total
PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af
specifi cations. The minimum probe voltages measured at the LTC4267-1
pins are –1.5V and –2.5V. The maximum probe voltages are –8.5V and
–9.5V.
Note 6: The PD interface includes hysteresis in the UVLO voltages to
preclude any start-up oscillation. Per IEEE 802.3af requirements, the PD
will power up from a voltage source with 20Ω series resistance on the fi rst
trial.
Note 7: Dynamic Supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 8: IVPORTN_CLASS does not include classifi cation current
programmed at the RCLASS pin. Total current in classifi cation mode will be
IVPORTN_CLASS + ICLASS (See note 9).
Note 9: ICLASS is the measured current fl owing through RCLASS. ΔICLASS
accuracy is with respect to the ideal current defi ned as ICLASS = 1.237/
RCLASS. The current accuracy does not include variations in RCLASS
resistance. The total classifi cation current for a PD also includes the IC
quiescent current (IVPORTN_CLASS). See Applications Information.
Note 10: To disable the 25k signature, tie SIGDISA to VPORTP or hold
SIGDISA high with respect to VPORTN. See Applications Information.
Note 11: The switching regulator is tested in a feedback loop that servos
VFB to the output of the error amplifi er while maintaining ITH/RUN at the
midpoint of the current limit range.
Note 12: IPOUT_LEAK includes current drawn through POUT by the power
good status circuit. This current is compensated for in the 25k signature
resistance and does not affect PD operation.
Note 13: The LTC4267-1 PD Interface includes thermal protection. In
the event of an overtemperature condition, the PD interface will turn off
the switching regulator until the part cools below the overtemperature
limit. The LTC4267-1 is also protected against thermal damage from
incorrect classifi cation probing by the PSE. If the LTC4267-1 exceeds the
overtemperature threshold, the classifi cation load current is disabled.
Note 14: The PD interface includes dual level input current limit. At turn-
on, before the POUT load capacitor is charged, the PD current level is set
to a low level. After the load capacitor is charged and the POUT – VPORTN
voltage difference is below the power good threshold, the PD switches to
high level current limit. The PD stays in high level current limit until the
input voltage drops below the UVLO turn-off threshold.
Note 15: Peak current sense voltage is reduced dependent on duty cycle
and an optional external resistor in series with the SENSE pin (RSL). For
details, refer to the programmable slope compensation feature in the
Applications Information section.
Note 16: Guaranteed by design.
Note 17: The PD interface includes overtemperature protection that is
intended to protect the device from momentary overload conditions.
Junction temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the specifi ed maximum operating
junction temperature may impair device reliability.
ELECTRICAL CHARACTERISTICS
LTC4267-1
5
42671f
Input Current vs Input Voltage
25k Detection Range Input Current vs Input Voltage Input Current vs Input Voltage
Input Current vs Input Voltage
Signature Resistance vs
Input Voltage
Normalized UVLO Threshold vs
Temperature
Power Good Output Low Voltage
vs Current POUT Leakage Current Current Limit vs Input Voltage
TYPICAL PERFOR
UW
CE CHARACTERISTICSA
71035/70-5"(&7
*/165$633&/5N"
o o o o
(
o
5"¡$
71035/70-5"(&7
o
*/165$633&/5N"
o o
(
o o o
¡$
o¡$
$-"4401&3"5*0/
71035/70-5"(&7
*/165$633&/5N"
o o o o
(
o o
$-"44
$-"44
$-"44
$-"44
$-"44
5"¡$
71035/70-5"(&7
*/165$633&/5N"
o o
(
oo o
&9$-6%&4"/:-0"%$633&/5
5"¡$
71035/70-5"(&7
o
7
7
4*(/"563&3&4*45"/$&L7
o o
(
o o
o o
o o o
3&4*45"/$&
%*0%&44#
5"¡$
$7
$*
7o7
*o*
*&&&611&3-*.*5
*&&&-08&3-*.*5
-5$%*0%&4
-5$0/-:
$633&/5N"
71(@0657
(
5"¡$
10651*/70-5"(&7
7065$633&/5M"
(
7*/7
5"¡$
71035/70-5"(&7
o
$633&/5-*.*5N"
o
(
o o o
¡$
¡$
o ¡$
o ¡$
)*()$633&/5.0%&
-08$633&/5.0%&
5&.1&3"563&¡$
o
o
/03."-*;&%67-05)3&4)0-%
o
o
(
"11-*$"#-&50563/0/
"/%563/''5)3&4)0-%4
LTC4267-1
6
42671f
Reference Voltage vs
Temperature
Reference Voltage vs
Supply Voltage
Oscillator Frequency vs
Temperature
Oscillator Frequency vs
Supply Voltage
PVCC Undervoltage Lockout
Thresholds vs Temperature
PVCC Shunt Regulator Voltage vs
Temperature
IPVCC Supply Current vs
Temperature
TYPICAL PERFOR A CE CHARACTERISTICS
UW
17$$4611-:70-5"(&7
7'#70-5"(&N7
(
5"¡$
17$$õ7$-".1N"
5&.1&3"563&¡$
o
04$*--"503'3&26&/$:L)[
o
(
o
17$$7
8*5)3&41&$5501(/%
17$$4611-:70-5"(&7
04$*--"503'3&26&/$:L)[
(
5"¡$
5&.1&3"563&¡$
o
17$$6/%&370-5"(&-0$,0657
o
(
o
7563/0/
7563/0''
5&.1&3"563&¡$
o
17$$7
o
(
o
*17$$N"
5&.1&3"563&¡$
o
4611-:$633&/5"
o
(
o
17$$7
7*5)36/7
5&.1&3"563&¡$
o
7'#70-5"(&N7
(
o o
17$$7
LTC4267-1
7
42671f
Peak Current Sense Voltage vs
Temperature Soft-Start Time vs Temperature
Start-Up IPVCC Supply Current vs
Temperature
ITH/RUN Shutdown Threshold vs
Temperature
ITH/RUN Start-Up Current Source
vs Temperature
5&.1&3"563&¡$
o
45"35614611-:$633&/5M"
o
(
o
17$$7563/0/o7
5&.1&3"563&¡$
o
4)65%08/5)3&4)0-%N7
(
o o
5&.1&3"563&¡$
o
*5)36/1*/$633&/54063$&O"
o
(
o
17$$7563/0/7
7*5)36/7
5&.1&3"563&¡$
o
4&/4&1*/70-5"(&N7
(
o
o
17$$7
5&.1&3"563&¡$
o
40'545"355*.&NT
o
o
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC4267-1
8
42671f
UU
U
PI FU CTIO S
PGND (Pin 1, 8, 9, 16): Switching Regulator Negative
Supply. This pin is the negative supply rail for the switching
regulator controller and must be tied to POUT.
ITH/RUN (Pin 2): Current Threshold/Run Input. This
pin performs two functions. It serves as the switching
regulator error amplifi er compensation point as well as
the run/shutdown control input. Nominal voltage range is
0.7V to 1.9V. Forcing the pin below 0.28V with respect to
PGND causes the controller to shut down.
NGATE (Pin 3): Gate Driver Output. This pin drives the
regulator’s external N-Channel MOSFET and swings from
PGND to PVCC.
PVCC (Pin 4): Switching Regulator Positive Supply. This
pin is the positive supply rail for the switching regulator
and must be closely decoupled to PGND.
RCLASS (Pin 5): Class Select Input. Used to set the current
value the PD maintains during classifi cation. Connect a
resistor between RCLASS and VPORTN (see Table 2).
NC (Pin 6): No Internal Connection.
VPORTN (Pin 7): Negative Power Input. Tie to the –48V
input port through the input diodes.
POUT (Pin 10): Power Output. Supplies –48V to the switch-
ing regulator PGND pin and any additional PD loads through
an internal power MOSFET that limits input current. POUT
is high impedance until the voltage reaches the turn-on
UVLO threshold. The output is then current limited. See
the Application Information section.
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D (Pin 11): Power Good Output, Open-Drain.
Indicates that the PD MOSFET is on and the switching
regulator can start operation. Low impedance indicates
power is good.
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D is high impedance during detec-
tion, classifi cation and in the event of a thermal overload.
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D is referenced to VPORTN.
SIGDISA (Pin 12): Signature Disable Input. SIGDISA al-
lows the PD to present an invalid signature resistance and
remain inactive. Connecting SIGDISA to VPORTP lowers
the signature resistance to an invalid value and disables
all functions of the LTC4267-1. If unused, tie SIGDISA to
VPORTN.
VPORTP (Pin 13): Positive Power Input. Tie to the input
port power return through the input diodes.
SENSE (Pin 14): Current Sense. This pin performs two
functions. It monitors the regulator switch current by read-
ing the voltage across an external sense resistor. It also
injects a current ramp that develops a slope compensation
voltage across an optional external programming resistor.
See the Applications Information section.
VFB (Pin 15): Feedback Input. Receives the feedback voltage
from the external resistor divider across the output.
LTC4267-1
9
42671f
BLOCK DIAGRAM
#%
71035/
#0-%-*/&*/%*$"5&4)*()$633&/51"5)
1065
o
1(/%
3$-"44
183(%
$0/530-
$*3$6*54
*/165
$633&/5
-*.*5
108&3(00%
$-"44*'*$"5*0/
$633&/5-0"%
7
&/
N"
N"
L
L
o
&/ L
4*(/"563&
3&4*4503
710351 4*(%*4"
o
o
4-01&
$0.1
$633&/5
3".1
17$$
("5&
%3*7&3
/("5&
4&/4&
L)[
04$*--"503
6/%&370-5"(&
-0$,065
2
3
$633&/5
$0.1"3"503
4)65%08/
$0.1"3"503
4)65%08/
4
N7
*5)36/
&3303
".1-*'*&3
7'#
40'5
45"35
$-".1
7$$
4)6/5
3&(6-"503
48*5$)*/(
-0(*$"/%
#-"/,*/(
$*3$6*5
7 17$$
7563/0/
M"
17$$
o
7
N7
3&'&3&/$&
OVERVIEW
The LTC4267-1 is partitioned into two major blocks: a
Powered Device (PD) interface controller and a current
mode fl yback switching regulator. The Powered Device
(PD) interface is intended for use as the front end of a
PD adhering to the IEEE 802.3af standard, and includes
a trimmed 25k signature resistor, classifi cation current
source, and an input current limit circuit. With these
functions integrated into the LTC4267-1, the signature
and power interface for a PD can be built that meets all
the requirements of the IEEE 802.3af specifi cation with a
minimum of external components.
The switching regulator portion of the LTC4267-1 is a
constant frequency current mode controller that is opti-
mized for Power over Ethernet applications. The regulator
is designed to drive a 6V N-channel MOSFET and features
soft-start and programmable slope compensation. The
integrated error amplifi er and precision reference give the
PD designer the option of using a nonisolated topology
without the need for an external amplifi er or reference. The
LTC4267-1 has been specifi cally designed to interface with
both IEEE compliant Power Sourcing Equipment (PSE)
and legacy PSEs which do not meet the inrush current
requirement of the IEEE 802.3af specifi cation. By setting
the initial inrush current limit to a low level, a PD using
the LTC4267-1 minimizes the current drawn from the PSE
during start-up. After powering up, the LTC4267-1 switches
to the high level current limit, thereby allowing the PD to
consume up to 12.95W if an IEEE 802.3af PSE is present.
This low level current limit also allows the LTC4267-1 to
charge arbitrarily large load capacitors without exceeding
the inrush limits of the IEEE 802.3af specifi cation. This
dual level current limit provides the system designer with
fl exibility to design PDs which are compatible with legacy
PSEs while also being able to take advantage of the higher
power available in an IEEE 802.3af system.
Using an LTC4267-1 for the power and signature inter-
face functions of a PD provides several advantages. The
LTC4267-1 current limit circuit includes an onboard 100V
power MOSFET. This low leakage MOSFET is specifi ed to
APPLICATIO S I FOR ATIO
WUUU
LTC4267-1
10
42671f
avoid corrupting the 25k signature resistor while also sav-
ing board space and cost. In addition, the inrush current
limit requirement of the IEEE 802.3af standard can cause
large transient power dissipation in the PD. The LTC4267-1
is designed to allow multiple turn-on sequences without
overheating the miniature 16-lead package. In the event of
excessive power cycling, the LTC4267-1 provides thermal
overload protection to keep the onboard power MOSFET
within its safe operating area.
OPERATION
The LTC4267-1 PD interface has several modes of opera-
tion depending on the applied input voltage as shown in
Figure 1 and summarized in Table 1. These modes satisfy
the requirements defi ned in the IEEE 802.3af specifi cation.
The input voltage is applied to the VPORTN pin and must
be negative relative to the VPORTP pin. Voltages in the data
sheet for the PD interface portion of the LTC4267-1 are
with respect to VPORTP while the voltages for the switch-
ing regulator are referenced to PGND. It is assumed that
PGND is tied to POUT. Note the use of different ground
symbols throughout the data sheet.
Table 1. LTC4267-1 Operational Mode
as a Function of Input Voltage
INPUT VOLTAGE
(VPORTN with RESPECT to VPORTP) LTC4267-1 MODE OF OPERATION
0V to –1.4V Inactive
–1.5V to –9.5V** 25k Signature Resistor Detection
–9.8V to –12.4V Classifi cation Load Current Ramps up
from 0% to 100%
–12.5V to UVLO* Classifi cation Load Current Active
UVLO* to –57V Power Applied to Switching Regulator
*VPORTN UVLO includes hysteresis.
Rising input threshold ≅ –36.0V
Falling input threshold ≅ –30.5V
**Measured at LTC4267-1 pin. The LTC4267-1 meets the IEEE 802.3af 10V
minimum when operating with the required diode bridges.
APPLICATIO S I FOR ATIO
WUUU
Figure 1. Output Voltage,
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D and PD
Current as a Function of Input Voltage
%&5&$5*0/7
$-"44*'*$"5*0/
67-0
563/0/
67-0
0''
108&3
#"%
67-0
0''
67-0
0/
67-0
563/0''
T3-0"%$
183(%53"$,4
71035/
%&5&$5*0/7
o
5*.&
o
o
71035/7
o
o
o
5*.&
o
o
10657
o
o
o
5*.&
o
o
183(%7
o
o
*$-"44
1%$633&/5
*-*.@-0
E7
EU
*-*.@-0
$
108&3
#"%
108&3
(00%
%&5&$5*0/*
$-"44*'*$"5*0/
*$-"44
%&5&$5*0/*
-0"%*-0"%6150*-*.@)*
$633&/5
-*.*5*-*.@-0
'
*$-"44%&1&/%&/50/3$-"444&-&$5*0/
*-*.@-0N"/0.*/"-*-*.@)*N"/0.*/"-
* 7o%*0%&%3014
L7
*-0"%6150*-*.@)*
7065
3-0"%
* 7o%*0%&%3014
L7
710351
14&
**/
-5$
3
3$-"44
3-0"%
7065
$
3$-"44
183(%
1065
1(/%
71035/
7*/
5*.&
70-5"(&48*5)3&41&$550710351
LTC4267-1
11
42671f
Series Diodes
The IEEE 802.3af-defi ned operating modes for a PD refer-
ence the input voltage at the RJ45 connector on the PD.
The PD must be able to accept power of either polarity
at each of its inputs, so it is common to install diode
bridges (Figure 2). The LTC4267-1 takes this into account
by compensating for these diode drops in the threshold
points for each range of operation. A similar adjustment
is made for the UVLO voltages.
Detection
During detection, the PSE will apply a voltage in the
range of –2.8V to –10V on the cable and look for a 25k
signature resistor. This identifi es the device at the end of
the cable as a PD. With the terminal voltage in this range,
the LTC4267-1 connects an internal 25k resistor between
the VPORTP and VPORTN pins. This precision, temperature
compensated resistor presents the proper signature to
alert the PSE that a PD is present and desires power to be
applied. The internal low-leakage UVLO switch prevents
the switching regulator circuitry from affecting the detec-
tion signature.
The LTC4267-1 is designed to compensate for the voltage
and resistance effects of the IEEE required diode bridge.
The signature range extends below the IEEE range to ac-
commodate the voltage drop of the two diodes. The IEEE
specifi cation requires the PSE to use a ΔV/ΔI measurement
technique to keep the DC offset of these diodes from af-
fecting the signature resistance measurement. However,
the diode resistance appears in series with the signature
resistor and must be included in the overall signature
resistance of the PD. The LTC4267-1 compensates for
the two series diodes in the signature path by offsetting
the resistance so that a PD built using the LTC4267-1 will
meet the IEEE specifi cation.
In some applications it is necessary to control whether
or not the PD is detected. In this case, the 25k signature
resistor can be enabled and disabled with the use of the
SIGDISA pin (Figure 3). Disabling the signature via the
SIGDISA pin will change the signature resistor to 9k
(typical) which is an invalid signature per the IEEE 802.3af
specifi cation. This invalid signature is present for PD input
voltages from –2.8V to –10V. If the input rises above –10V,
the signature resistor reverts to 25k to minimize power
dissipation in the LTC4267-1. To disable the signature,
tie SIGDISA to VPORTP
. Alternately, the SIGDISA pin can
be driven high with respect to VPORTN. When SIGDISA is
high, all functions of the PD interface are disabled.
APPLICATIO S I FOR ATIO
WUUU
39o
39
59o
59
3+ 5
108&3&%%&7*$&1%
*/5&3'"$&
"4%&'*/&%
#:*&&&BG
'
41"3&o
41"3&
501):
#3
#3
710351
%
-5$
71035/
Figure 2. LTC4267-1 PD Front End Using
Diode Bridges on Main and Spare Inputs
LTC4267-1
12
42671f
710351
71035/
-5$
'
L4*(/"563&
3&4*4503
4*(/"563&%*4"#-&
4*(%*4"
L
L
50
14&
Classifi cation
Once the PSE has detected a PD, the PSE may option-
ally classify the PD. Classifi cation provides a method for
more effi cient allocation of power by allowing the PSE
to identify lower power PDs and allocate less power for
these devices. The IEEE 802.3af specifi cation defi nes fi ve
classes (Table 2) with varying power levels. The designer
selects the appropriate classifi cation based on the power
consumption of the PD. For each class, there is an as-
sociated load current that the PD asserts onto the line
during classifi cation probing. The PSE measures the PD
load current to determine the proper classifi cation and
PD power requirements.
During classifi cation (Figure 4), the PSE presents a fi xed
voltage between –15.5V and –20.5V to the PD. With the
input voltage in this range, the LTC4267-1 asserts a load
current from the VPORTP pin through the RCLASS resistor.
The magnitude of the load current is set by the RCLASS
resistor. The resistor values associated with each class are
shown in Table 2. Note that the switching regulator will
not interfere with the classifi cation measurement since the
LTC4267-1 has not passed power to the regulator.
Table 2. Summary of IEEE 802.3af Power Classifi cations and
LTC4267-1 RCLASS Resistor Selection
Class Usage
Maximum
Power Levels
at Input of PD
(W)
Nominal
Classifi cation
Load Current
(mA)
LTC4267-1
RCLASS
Resistor
(Ω, 1%)
0 Default 0.44 to 12.95 <5 Open
1 Optional 0.44 to 3.84 10.5 124
2 Optional 3.84 to 6.49 18.5 68.1
3 Optional 6.49 to 12.95 28 45.3
4 Reserved Reserved* 40 30.9
*Class 4 is currently reserved and should not be used.
The IEEE 802.3af specifi cation limits the classifi cation
time to 75ms because a signifi cant amount of power is
dissipated in the PD. The LTC4267-1 is designed to handle
the power dissipation for this time period. If the PSE prob-
ing exceeds 75ms, the LTC4267-1 may overheat. In this
situation, the thermal protection circuit will engage and
disable the classifi cation current source in order to protect
the part. The LTC4267-1 stays in classifi cation mode until
the input voltage rises above the UVLO turn-on voltage.
VPORTN Undervoltage Lockout
The IEEE specifi cation dictates a maximum turn-on voltage
of 42V and a minimum turn-off voltage of 30V for the PD.
In addition, the PD must maintain large on-off hysteresis to
prevent resistive losses in the wiring between the PSE and
the PD from causing start-up oscillation. The LTC4267-1
incorporates an undervoltage lockout (UVLO) circuit that
monitors the line voltage at VPORTN to determine when
to apply power to the integrated switching regulator
(Figure 5). Before the power is applied to the switching
regulator, the POUT pin is high impedance and sitting at
the ground potential since there is no charge on capacitor
C1. When the input voltage rises above the UVLO turn-on
threshold, the LTC4267-1 removes the detection and clas-
sifi cation loads and turns on the internal power MOSFET.
C1 charges up under the LTC4267-1 current limit control
and the POUT pin transitions from 0V to VPORTN. This
sequence is shown in Figure 1. The LTC4267-1 includes
a hysteretic UVLO circuit on VPORTN that keeps power
applied to the load until the input voltage falls below the
UVLO turn-off threshold. Once the input voltage drops
below –30V, the internal power MOSFET is turned off and
Figure 4. IEEE 802.3af Classifi cation Probing
APPLICATIO S I FOR ATIO
WUUU
710351
3$-"44
71035/
-5$
$0/45"/5
-0"%
$633&/5
*/5&3/"-
50-5$
'
3$-"44
$633&/51"5)
7
1%14&
14&$633&/5.0/*503
14&
130#*/(
70-5"(&
4063$&
o750o7
Figure 3. 25k Signature Resistor with Disable
LTC4267-1
13
42671f
Figure 5. LTC4267-1 VPORTN Undervoltage Lockout
the classifi cation current is reenabled. C1 will discharge
through the PD circuitry and the POUT pin will go to a high
impedance state.
limit because the load capacitor is charged with a current
below the IEEE inrush current limit specifi cation.
As the LTC4267-1 switches from the low to high level
current limit, the current will increase momentarily. This
current spike is a result of the LTC4267-1 charging the
last 1.5V at the high level current limit. When charging a
10µF capacitor, the current spike is typically 100µs wide
and 125% of the nominal low level current limit.
The LTC4267-1 stays in the high level current limit mode
until the input voltage drops below the UVLO turn-off
threshold. This dual level current limit provides the sys-
tem designer with the fl exibility to design PDs which are
compatible with legacy PSEs while also being able to take
advantage of the higher power allocation available in an
IEEE 802.3af system.
During the current limited turn on, a large amount of
power is dissipated in the power MOSFET. The LTC4267-1
PD interface is designed to accept this thermal load and
is thermally protected to avoid damage to the onboard
power MOSFET. Note that in order to adhere to the IEEE
802.3af standard, it is necessary for the PD designer to
ensure the PD steady state power consumption falls within
the limits shown in Table 2. In addition, the steady state
current must be less than ILIM_HI.
Power Good
The LTC4267-1 PD Interface includes a power good circuit
(Figure 6) that is used to indicate that load capacitor C1
is fully charged and that the switching regulator can start
operation. The power good circuit monitors the voltage
across the internal UVLO power MOSFET and
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D is
asserted when the voltage falls below 1.5V. The power
good circuit includes hysteresis to allow the LTC4267-1 to
operate near the current limit point without inadvertently
disabling
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D. The MOSFET voltage must increase to
3V before
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D is disabled.
If a sudden increase in voltage appears on the input line,
this voltage step will be transferred through capacitor C1
and appear across the power MOSFET. The response of the
LTC4267-1 will depend on the magnitude of the voltage
step, the rise time of the step, the value of capacitor C1
and the switching regulator load. For fast rising inputs,
APPLICATIO S I FOR ATIO
WUUU
Input Current Limit
IEEE 802.3af specifi es a maximum inrush current and
also specifi es a minimum load capacitor between the
VPORTP and POUT pins. To control turn-on surge current
in the system, the LTC4267-1 integrates a dual level cur-
rent limit circuit with an onboard power MOSFET and
sense resistor to provide a complete inrush control circuit
without additional external components. At turn-on, the
LTC4267-1 will limit the input current to the low level,
allowing the load capacitor to ramp up to the line voltage
in a controlled manner.
The LTC4267-1 has been specifi cally designed to interface
with legacy PSEs which do not meet the inrush current
requirement of the IEEE 802.3af specifi cation. At turn-on
the LTC4267-1 current limit is set to the lower level. After
C1 is charged up and the POUT – VPORTN voltage difference
is below the power good threshold, the LTC4267-1 switches
to the high level current limit. The dual level current limit
allows legacy PSEs with limited current sourcing capability
to power up the PD while also allowing the PD to draw full
power from an IEEE 802.3af PSE. The dual level current
limit also allows use of arbitrarily large load capacitors.
The IEEE 802.3af specifi cation mandates that at turn-on
the PD not exceed the inrush current limit for more than
50ms. The LTC4267-1 is not restricted to the 50ms time
$
M'
.*/
71035/
710351
1065
1(/%
-5$
'
50
14& 6/%&370-5"(&
-0$,065
$*3$6*5
$633&/5-*.*5&%
563/0/
*/165 -5$
70-5"(& 108&3.04'&5
75067-0 0''
67-0 0/
67-0*/$-6%&4):45&3&4*4
3*4*/(*/1655)3&4)0-% o7
'"--*/(*/1655)3&4)0-% o7
LTC4267-1
14
42671f
183(%
$
M'
.*/
71035/ 1065
7
L L
3
L
-5$
5)&3."-4)65%08/
67-0
'
50
14&
o
o
*5)36/
1(/%
1(/%
the LTC4267-1 will attempt to quickly charge capacitor C1
using an internal secondary current limit circuit. In this
scenario, the PSE current limit should provide the overall
limit for the circuit. For slower rising inputs, the 375mA
current limit in the LTC4267-1 will set the charge rate of
the capacitor C1. In either case, the
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D signal may
go inactive briefl y while the capacitor is charged up to the
new line voltage. In the design of a PD, it is necessary
to determine if a step in the input voltage will cause the
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D signal to go inactive and how to respond to this
event. In some designs, it may be desirable to fi lter the
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D signal so that intermittent power bad conditions
are ignored. Figure 7 demonstrates a method to insert a
lowpass fi lter on the power good interface.
For PD designs that use a large load capacitor and also con-
sume a lot of power, it is important to delay activation of the
switching regulator with the
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D signal. If the regulator
is not disabled during the current-limited turn-on sequence,
the PD circuitry will rob current intended for charging up
the load capacitor and create a slow rising input, possibly
causing the LTC4267-1 to go into thermal shutdown.
The
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D pin connects to an internal open drain, 100V
transistor capable of sinking 1mA. Low impedance to
VPORTN indicates power is good.
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D is high imped-
ance during signature and classifi cation probing and in
the event of a thermal overload. During turn-off,
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D
is deactivated when the input voltage drops below 30V.
In addition,
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D may go active briefl y at turn-on for
fast rising input waveforms.
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D is referenced to the
VPORTN pin and when active, will be near the VPORTN po-
tential. Connect the
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D pin to the switching regulator
circuitry as shown in Figure 7.
Figure 6. LTC4267-1 Power Good
APPLICATIO S I FOR ATIO
WUUU
Figure 7. Power Good Interface Examples
PD Interface Thermal Protection
The LTC4267-1 PD Interface includes thermal overload
protection in order to provide full device functionality
in a miniature package while maintaining safe operating
temperatures. Several factors create the possibility of
signifi cant power dissipation within the LTC4267-1. At
turn-on, before the load capacitor has charged up, the
instantaneous power dissipated by the LTC4267-1 can be
as much as 10W. As the load capacitor charges up, the
power dissipation in the LTC4267-1 will decrease until it
reaches a steady-state value dependent on the DC load
current. The size of the load capacitor determines how fast
the power dissipation in the LTC4267-1 will subside. At
room temperature, the LTC4267-1 can typically handle load
capacitors as large as 800µF without going into thermal
shutdown. With large load capacitors, the LTC4267-1 die
temperature will increase by as much as 50°C during a
single turn-on sequence. If for some reason power were
removed from the part and then quickly reapplied so that
the LTC4267-1 had to charge up the load capacitor again,
the temperature rise would be excessive if safety precau-
tions were not implemented.
The LTC4267-1 PD interface protects itself from thermal
damage by monitoring the die temperature. If the die
'
-5$
71035/ 1065
1(/%
710351
*5)36/
*5)36/
50
14&
o7
$
M'
7
"-5&3/"5&"$5*7&)*()&/"#-&'0317$$1*/
$"/%$015*0/"-
4&&"11-*$"5*0/4*/'03."5*0/4&$5*0/
"$5*7&)*()&/"#-&'0336/1*/8*5)*/5&3/"-16--61
3
L
3
L
%
..#%
$
M'
2
'..5
-5$
(/%
015*0/"-
"69*-*"3:
48*5$)*/(
3&(6-"503
183(%
1(/%
-5$
71035/ 1065
1(/%
710351
17$$
50
14&
o7
$
M'
7
3
L
3
L
%
..#%
$
M'
2
'..5
183(%
1(/%
345"35
$17$$
$
LTC4267-1
15
42671f
temperature exceeds the overtemperature trip point, the
current is reduced to zero and very little power is dissi-
pated in the part until it cools below the overtemperature
set point. Once the LTC4267-1 has charged up the load
capacitor and the PD is powered and running, there will
be minor residual heating due to the DC load current of
the PD fl owing through the internal MOSFET.
During classifi cation, excessive heating of the LTC4267-1
can occur if the PSE violates the 75ms probing time limit.
To protect the LTC4267-1, thermal overload circuitry will
disable classifi cation current if the die temperature exceeds
the overtemperature trip point. When the die cools down
below the trip point, classifi cation current is reenabled.
The PD is designed to operate at a high ambient tem-
perature and with the maximum allowable supply (57V).
However, there is a limit to the size of the load capacitor
that can be charged up before the LTC4267-1 reaches the
overtemperature trip point. Hitting the overtemperature trip
point intermittently does not harm the LTC4267-1, but it
will delay the completion of capacitor charging. Capacitors
up to 200µF can be charged without a problem over the
full operating temperature range.
Switching Regulator Main Control Loop
Due to space limitations, the basics of current mode
DC/DC conversion will not be discussed here. The reader
is referred to the detail treatment in Application Note 19
or in texts such as Abraham Pressman’s Switching Power
Supply Design.
In a Power over Ethernet System, the majority of applica-
tions involve an isolated power supply design. This means
that the output power supply does not have any DC elec-
trical path to the PD interface or the switching regulator
primary. The DC isolation is achieved typically through
a transformer in the forward path and an optoisolator in
the feedback path or a third winding in the transformer.
The typical application circuit shown on the front page
of the datasheet represents an isolated design using an
optoisolator. In applications where a nonisolated topology
is desired, the LTC4267-1 features a feedback port and
an internal error amplifi er that can be enabled for this
specifi c application.
In the typical application circuit (Figure 11), the isolated
topology employs an external resistive voltage divider
to present a fraction of the output voltage to an external
error amplifi er. The error amplifi er responds by pulling
an analog current through the input LED on an optoiso-
lator. The collector of the optoisolator output presents a
corresponding current into the ITH/RUN pin via a series
diode. This method generates a feedback voltage on the
ITH/RUN pin while maintaining isolation.
The voltage on the ITH/RUN pin controls the pulse-width
modulator formed by the oscillator, current comparator,
and RS latch. Specifi cally, the voltage at the ITH/RUN pin
sets the current comparator’s trip threshold. The current
comparator monitors the voltage across a sense resistor
in series with the source terminal of the external N-Chan-
nel MOSFET. The LTC4267-1 turns on the external power
MOSFET when the internal free-running 200kHz oscillator
sets the RS latch. It turns off the MOSFET when the cur-
rent comparator resets the latch or when 80% duty cycle
is reached, whichever happens fi rst. In this way, the peak
current levels through the fl yback transformer’s primary
and secondary are controlled by the ITH/RUN voltage.
In applications where a nonisolated topology is desirable
(Figure 11), an external resistive voltage divider can pres-
ent a fraction of the output voltage directly to the VFB pin
of the LTC4267-1. The divider must be designed so when
the output is at its desired voltage, the VFB pin voltage will
equal the 800mV onboard internal reference. The internal
error amplifi er responds by driving the ITH/RUN pin. The
LTC4267-1 switching regulator performs in a similar
manner as described previously.
Regulator Start-Up/Shutdown
The LTC4267-1 switching regulator has two shutdown
mechanisms to enable and disable operation: an un-
dervoltage lockout on the PVCC supply pin and a forced
shutdown whenever external circuitry drives the ITH/RUN
pin low. The LTC4267-1 switcher transitions into and out
of shutdown according to the state diagram (Figure 8).
It is important not to confuse the undervoltage lockout
of the PD interface at VPORTN with that of the switching
regulator at PVCC. They are independent functions.
APPLICATIO S I FOR ATIO
WUUU
LTC4267-1
16
42671f
Adjustable Slope Compensation
The LTC4267-1 switching regulator injects a 5µA peak
current ramp out through its SENSE pin which can be
used for slope compensation in designs that require it.
This current ramp is approximately linear and begins at
zero current at 6% duty cycle, reaching peak current at
80% duty cycle. Programming the slope compensation
via a series resistor is discussed in the External Interface
and Component Selection section.
EXTERNAL INTERFACE AND COMPONENT SELECTION
Input Interface Transformer
Nodes on an Ethernet network commonly interface to the
outside world via an isolation transformer (Figure 9). For
PoE devices, the isolation transformer must include a
center tap on the media (cable) side. Proper termination
is required around the transformer to provide correct
impedance matching and to avoid radiated and conducted
emissions. Transformer vendors such as Bel Fuse, Coil-
craft, Pulse and Tyco (Table 3) can provide assistance with
selection of an appropriate isolation transformer and proper
termination methods. These vendors have transformers
specifi cally designed for use in PD applications.
Table 3. Power over Ethernet Transformer Vendors
VENDOR CONTACT INFORMATION
Bel Fuse Inc. 206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
FAX: 201-432-9542
http://www.belfuse.com
Coilcraft, Inc. 1102 Silver Lake Road
Cary, IL 60013
Tel: 847-639-6400
FAX: 847-639-1469
http://www.coilcraft.com
Pulse Engineering 12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
FAX: 858-674-8262
http://www.pulseeng.com
Tyco Electronics 308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
FAX: 650-361-2508
http://www.circuitprotection.com
APPLICATIO S I FOR ATIO
WUUU
Figure 8. LTC4267-1 Switching Regulator
Start-Up/Shutdown State Diagram
The undervoltage lockout mechanism on PVCC prevents
the LTC4267-1 switching regulator from trying to drive
the external N-Channel MOSFET with insuffi cient gate-to-
source voltage. The voltage at the PVCC pin must exceed
VTURNON (nominally 8.7V with respect to PGND) at least
momentarily to enable operation. The PVCC voltage must
fall to VTURNOFF (nominally 5.7V with respect to PGND)
before the undervoltage lockout disables the switching
regulator. This wide UVLO hysteresis range supports
applications where a bias winding on the fl yback trans-
former is used to increase the effi ciency of the LTC4267-1
switching regulator.
The ITH/RUN can be driven below VITHSHDN (nominally 0.28V
with respect to PGND) to force the LTC4267-1 switching
regulator into shutdown. An internal 0.3µA current source
always tries to pull the ITH/RUN pin towards PVCC. When
the ITH/RUN pin voltage is allowed to exceed VITHSHDN and
PVCC exceeds VTURNON, the LTC4267-1 switching regulator
begins to operate and an internal clamp immediately pulls
the ITH/RUN pin to about 0.7V. In operation, the ITH/RUN
pin voltage will vary from roughly 0.7V to 1.9V to represent
current comparator thresholds from zero to maximum.
Internal Soft-Start
An internal soft-start feature is enabled whenever the
LTC4267-1 switching regulator comes out of shutdown.
Specifi cally, the ITH/RUN voltage is clamped and is
prevented from reaching maximum until 1.4ms have
passed. This allows the input current of the PD to rise in a
smooth and controlled manner on start-up and stay within
the current limit requirement of the LTC4267-1 interface.
,4#
07-
3(54$/7.
,4#
07-
%.!",%$
6)4(25.
6)4(3($.
./-).!,,9
6
6)4(25.6)4(3($.
!.$06##6452./.
./-).!,,96
06##6452./&&
&
!,,6/,4!'%37)4(
2%30%#44/0'.$
LTC4267-1
17
42671f
Diode Bridge
IEEE 802.3af allows power wiring in either of two confi gu-
rations: on the TX/RX wires or via the spare wire pairs in
the RJ45 connector. The PD is required to accept power in
either polarity on either the main or spare inputs; therefore
it is common to install diode bridges on both inputs in
order to accommodate the different wiring confi gurations.
Figure 9 demonstrates an implementation of these diode
bridges. The IEEE 802.3af specifi cation also mandates
that the leakage back through the unused bridge be less
than 28µA when the PD is powered with 57V.
The IEEE standard includes an AC impedance requirement
in order to implement the AC disconnect function. Capaci-
tor C14 in Figure 9 is used to meet this AC impedance
requirement. A 0.1µF capacitor is recommended for this
application.
The LTC4267-1 has several different modes of opera-
tion based on the voltage present between VPORTN and
VPORTP pins. The forward voltage drop of the input diodes
in a PD design subtracts from the input voltage and will
affect the transition point between modes. When using
the LTC4267-1, it is necessary to pay close attention to
this forward voltage drop. Selection of oversized diodes
will help keep the PD thresholds from exceeding IEEE
specifi cations.
The input diode bridge of a PD can consume over 4%
of the available power in some applications. It may be
desirable to use Schottky diodes in order to reduce power
loss. However, if the standard diode bridge is replaced
with a Schottky bridge, the transition points between the
modes will be affected. Figure 10 shows a technique for
using Schottky diodes while maintaining proper threshold
points to meet IEEE 802.3af compliance. D13 is added to
compensate for the change in UVLO turn-on voltage caused
by the Schottky diodes and consumes little power.
Classifi cation Resistor Selection (RCLASS)
The IEEE specifi cation allows classifying PDs into four
distinct classes with class 4 being reserved for future use
(Table 2). An external resistor connected from RCLASS to
VPORTN (Figure 4) sets the value of the load current. The
APPLICATIO S I FOR ATIO
WUUU
Figure 9. PD Front End with Isolation Transformer, Diode Bridges and Capacitor
39o
39
59o
59
3+
5
16-4&)
'
%
4."+"
574
#3
)%
#3
)%
501):
-5$
71035/
41"3&o
41"3&
$
M'
7
710351
LTC4267-1
18
42671f
APPLICATIO S I FOR ATIO
WUUU
39o
41"3&o
39
59o
59
+
*/
'30.
14&
5
3+
59065
065
501):
59065o
41"3&
39065
39065o
/05&46/-&4405)&38*4&41&$*'*&%
"--3&4*45034"3&
4&-&$53$-"44'03$-"4401&3"5*0/3&'&3
50%"5"4)&&5"11-*$"5*0/4*/'03."5*0/4&$5*0/
$"79($."5
%50%%50%%*0%&4*/$#
516-4&)
3$-"44
3$-"44
71035/
%
..4%
$
M'
7
%
4."+"
3
7
$
M'
7
3
7
$
M'
7
3
7
$
M'
7
3
7
$
M'
7
$
Q'
L7
%
#
%
#
%
#
%
#
%
#
%
#
%
#
%
#
710351
-5$
'
Figure 10. PD Front End with Isolation Transformer, 2nd Schottky Diode Bridge
designer should determine which power category the PD
falls into and then select the appropriate value of RCLASS
from Table 2. If a unique load current is required, the value
of RCLASS can be calculated as:
R
CLASS = 1.237V/(IDESIRED – IIN_CLASS)
where IIN_CLASS is the LTC4267-1 IC supply current during
classifi cation and is given in the electrical specifi cations.
The RCLASS resistor must be 1% or better to avoid de-
grading the overall accuracy of the classifi cation circuit.
Resistor power dissipation will be 50mW maximum and
is transient so heating is typically not a concern. In order
to maintain loop stability, the layout should minimize
capacitance at the RCLASS node. The classifi cation circuit
can be disabled by fl oating the RCLASS pin. The RCLASS pin
should not be shorted to VPORTN as this would force the
LTC4267-1 classifi cation circuit to attempt to source very
large currents and quickly go into thermal shutdown.
LTC4267-1
19
42671f
APPLICATIO S I FOR ATIO
WUUU
Power Good Interface
The
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D signal is controlled by a high voltage, open-
drain transistor. The designer has the option of using this
signal to enable the onboard switching regulator through
the ITH/RUN or the PVCC pins. Examples of active-high
interface circuits for controlling the switching regulator
are shown in Figure 7.
In some applications, it is desirable to ignore intermittent
power bad conditions. This can be accomplished by in-
cluding capacitor C15 in Figure 7 to form a lowpass fi lter.
With the components shown, power bad conditions less
than about 200µs will be ignored. Conversely, in other
applications it may be desirable to delay assertion of
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D to the switching regulator using CPVCC or C17
as shown in Figure 7.
It is recommended that the designer use the power
good signal to enable the switching regulator. Using
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D ensures the capacitor C1 has reached within
1.5V of the fi nal value and is ready to accept a load. The
LTC4267-1 is designed with wide power good hysteresis
to handle sudden fl uctuations in the load voltage and
current without prematurely shutting off the switching
regulator. Please refer to the Power-Up Sequencing of the
Application Information section.
Signature Disable Interface
To disable the 25k signature resistor, connect SIGDISA pin
to the VPORTP pin. Alternately, SIGDISA pin can be driven
high with respect to VPORTN. An example of a signature
disable interface is shown in Figure 16, option 2. Note that
the SIGDISA input resistance is relatively large and the
threshold voltage is fairly low. Because of high voltages
present on the printed circuit board, leakage currents from
the VPORTP pin could inadvertently pull SIGDISA high. To
ensure trouble-free operation, use high voltage layout
techniques in the vicinity of SIGDISA. If unused, connect
SIGDISA to VPORTN.
Load Capacitor
The IEEE 802.3af specifi cation requires that the PD maintain
a minimum load capacitance of 5µF (provided by C1 in
Figure 11). It is permissible to have a much larger load
capacitor and the LTC4267-1 can charge very large load
capacitors before thermal issues become a problem. The
load capacitor must be large enough to provide suffi cient
energy for proper operation of the switching regulator.
However, the capacitor must not be too large or the PD
design may violate IEEE 802.3af requirements.
If the load capacitor is too large, there can be a problem
with inadvertent power shutdown by the PSE. Consider
the following scenario. If the PSE is running at –57V
(maximum allowed) and the PD has detected and powered
up, the load capacitor will be charged to nearly –57V. If
for some reason the PSE voltage is suddenly reduced to
–44V (minimum allowed), the input bridge will reverse
bias and the PD power will be supplied by the load capaci-
tor. Depending on the size of the load capacitor and the
DC load of the PD, the PD will not draw any power for
a period of time. If this period of time exceeds the IEEE
802.3af 300ms disconnect delay, the PSE will remove
power from the PD. For this reason, it is necessary to
ensure that inadvertent shutdown cannot occur.
Very small output capacitors (≤10µF) will charge very
quickly in current limit. The rapidly changing voltage at
the output may reduce the current limit temporarily, caus-
ing the capacitor to charge at a somewhat reduced rate.
Conversely, charging a very large capacitor may cause the
current limit to increase slightly. In either case, once the
output voltage reaches its fi nal value, the input current
limit will be restored to its nominal value.
The load capacitor can store signifi cant energy when fully
charged. The design of a PD must ensure that this energy
is not inadvertently dissipated in the LTC4267-1. The po-
larity-protection diode(s) prevent an accidental short on
LTC4267-1
20
42671f
the cable from causing damage. However, if the VPORTN
pin is shorted to VPORTP inside the PD while the capacitor
is charged, current will fl ow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4267-1.
Maintain Power Signature
In an IEEE 802.3af system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically
draw at least 10mA and also have an AC impedance less
than 26.25kΩ in parallel with 0.05µF. If either the DC
current is less than 10mA or the AC impedance is above
26.25kΩ, the PSE may disconnect power. The DC current
must be less than 5mA and the AC impedance must be
above 2MΩ to guarantee power will be removed.
Selecting Feedback Resistor Values
The regulated output voltage of the switching regulator is
determined by the resistor divider across VOUT (R1 and
R2 in Figure 11) and the error amplifi er reference voltage
VREF
. The ratio of R2 to R1 needed to produce the desired
voltage can be calculated as:
R2 = R1 • (VOUT – VREF)/VREF
In an isolated power supply application, VREF is determined
by the designer’s choice of an external error amplifi er.
Commercially available error amplifi ers or programmable
shunt regulators may include an internal reference of
1.25V or 2.5V. Since the LTC4267-1 internal reference
and error amplifi er are not used in an isolated design, tie
the VFB pin to PGND.
In a nonisolated power supply application, the LTC4267-1
onboard internal reference and error amplifi er can be
used. The resistor divider output can be tied directly to
the VFB pin. The internal reference of the LTC4267-1 is
0.8V nominal.
Choose resistance values for R1 and R2 to be as large as
possible to minimize any effi ciency loss due to the static
current drawn from VOUT, but just small enough so that
when VOUT is in regulation, the error caused by the nonzero
input current from the output of the resistor divider to the
error amplifi er pin is less than 1%.
Error Amplifi er and Optoisolator Considerations
In an isolated topology, the selection of the external error
amplifi er depends on the output voltage of the switching
regulator. Typical error amplifi ers include a voltage refer-
ence of either 1.25V or 2.5V. The output of the amplifi er
and the amplifi er upper supply rail are often tied together
internally. The supply rail is usually specifi ed with a wide
upper voltage range, but it is not allowed to fall below the
reference voltage. This can be a problem in an isolated
switcher design if the amplifi er supply voltage is not prop-
erly managed. When the switcher load current decreases
and the output voltage rises, the error amplifi er responds
by pulling more current through the LED. The LED voltage
can be as large as 1.5V, and along with RLIM, reduces the
supply voltage to the error amplifi er. If the error amp does
not have enough headroom, the voltage drop across the
LED and RLIM may shut the amplifi er off momentarily,
causing a lock-up condition in the main loop. The switcher
will undershoot and not recover until the error amplifi er
releases its sink current. Care must be taken to select the
reference voltage and RLIM value so that the error amplifi er
always has enough headroom. An alternate solution that
avoids these problems is to utilize the LT1431 or LT4430
where the output of the error amplifi er and amplifi er supply
rail are brought out to separate pins.
The PD designer must also select an optoisolator such
that its bandwidth is suffi ciently wider than the bandwidth
of the main control loop. If this step is overlooked, the
main control loop may be diffi cult to stabilize. The output
APPLICATIO S I FOR ATIO
WUUU
LTC4267-1
21
42671f
collector resistor of the optoisolator can be selected for
an increase in bandwidth at the cost of a reduction in gain
of this stage.
Output Transformer Design Considerations
Since the external feedback resistor divider sets the
output voltage, the PD designer has relative freedom in
selecting the transformer turns ratio. The PD designer
can use simple ratios of small integers (i.e. 1:1, 2:1, 3:2)
which yields more freedom in setting the total turns and
mutual inductance and may allow the use of an off the
shelf transformer.
Transformer leakage inductance on either the primary or
secondary causes a voltage spike to occur after the output
switch (Q1 in Figure 11) turns off. The input supply volt-
age plus the secondary-to-primary referred voltage of the
fl yback pulse (including leakage spike) must not exceed
the allowed external MOSFET breakdown rating. This spike
is increasingly prominent at higher load currents, where
more stored energy must be dissipated. In some cases,
a “snubber” circuit will be required to avoid overvoltage
breakdown at the MOSFET’s drain node. Application
Note 19 is a good reference for snubber design.
Current Sense Resistor Consideration
The external current sense resistor (RSENSE in Figure 11)
allows the designer to optimize the current limit behavior
for a particular application. As the current sense resistor
is varied from several ohms down to tens of milliohms,
peak swing current goes from a fraction of an ampere to
several amperes. Care must be taken to ensure proper
circuit operation, especially for small current sense resis-
tor values.
Choose RSENSE such that the switching current exercises
the entire range of the ITH/RUN voltage. The nominal voltage
range is 0.7V to 1.9V and RSENSE can be determined by
experiment. The main loop can be temporarily stabilized
by connecting a large capacitor on the power supply. Apply
the maximum load current allowable at the power sup-
ply output based on the class of the PD. Choose RSENSE
such that ITH/RUN approaches 1.9V. Finally, exercise the
output load current over the entire operating range and
ensure that ITH/RUN voltage remains within the 0.7V to
1.9V range. Layout is critical around the RSENSE resistor.
For example, a 0.020Ω sense resistor, with one milliohm
(0.001Ω) of parasitic resistance will cause a 5% reduction
in peak switch current. The resistance of printed circuit
copper traces cannot necessarily be ignored and good
layout techniques are mandatory.
Programmable Slope Compensation
The LTC4267-1 switching regulator injects a ramping
current through its SENSE pin into an external slope
compensation resistor (RSL in Figure 11). This current
ramp starts at zero after the NGATE pin has been high for
the LTC4267-1’s minimum duty cycle of 6%. The current
rises linearly towards a peak of 5µA at the maximum duty
cycle of 80%, shutting off once the NGATE pin goes low.
A series resistor (RSL) connecting the SENSE pin to the
current sense resistor (RSENSE) develops a ramping volt-
age drop. From the perspective of the LTC4267-1 SENSE
pin, this ramping voltage adds to the voltage across the
sense resistor, effectively reducing the current comparator
threshold in proportion to duty cycle. This stabilizes the
control loop against subharmonic oscillation. The amount
of reduction in the current comparator threshold (∆VSENSE)
can be calculated using the following equation:
ΔVSENSE = 5µA • RSL • [(Duty Cycle – 6%)/74%]
Note: The LTC4267-1 enforces 6% < Duty Cycle < 80%.
Designs not needing slope compensation may replace
RSL with a short-circuit.
Applications Employing a Third Transformer Winding
A standard operating topology may employ a third wind-
ing on the transformer’s primary side that provides power
APPLICATIO S I FOR ATIO
WUUU
LTC4267-1
22
42671f
APPLICATIO S I FOR ATIO
WUUU
Figure 11. Typical LTC4267-1 Application Circuits
17$$
17$$
17$$
710351
3$-"44
4*(%*4"
71035/
*5)36/
-5$
/("5&
4&/4&
7'#
3
%
%
t
t
$065
1(/%
1(/%
1(/%
1(/%
1(/%
1(/%
1(/%
1(/%
1(/%
1065
$ -4&$
-13*
-#*"4
$17$$
$$
7065
'
34&/4&
34-
345"35
3
3
2
5
t
3$-"44
17$$
710351
3$-"44
4*(%*4"
71035/
*5)36/
-5$
/("5&
4&/4&
7'#
%
t
t
$065
M'
7
M'
7
1(/%
1(/%
1(/%
1(/%
1065
$ -4&$
-13*
$17$$
7065
34&/4&
34-
345"35
2
3
3
3-*.
o7
'30.
%"5"1"*3
o7
'30.
41"3&1"*3
3$-"44
710351
710351
71035/
5
$*40
0150*40-"503
$$
3$
&3303
".1-*'*&3
*40-"5&%%&4*(/&9".1-&
/0/*40-"5&%%&4*(/&9".1-&
o
o
o7
'30.
%"5"1"*3
o7
'30.
41"3&1"*3
o
o
LTC4267-1
23
42671f
APPLICATIO S I FOR ATIO
WUUU
to the LTC4267-1 switching regulator via its PVCC pin
(Figure 11). However, this arrangement is not inherently
self-starting. Start-up is usually implemented by the use of
an external “trickle-charge” resistor (RSTART) in conjunc-
tion with the internal wide hysteresis undervoltage lockout
circuit that monitors the PVCC pin voltage.
RSTART is connected to VPORTP and supplies a current,
typically 100µA, to charge CPVCC. After some time, the
voltage on CPVCC reaches the PVCC turn-on threshold. The
LTC4267-1 switching regulator then turns on abruptly and
draws its normal supply current. The NGATE pin begins
switching and the external MOSFET (Q1) begins to deliver
power. The voltage on CPVCC begins to decline as the
switching regulator draws its normal supply current, which
exceeds the delivery from RSTART. After some time, typically
tens of milliseconds, the output voltage approaches the
desired value. By this time, the third transformer winding
is providing virtually all the supply current required by the
LTC4267-1 switching regulator.
One potential design pitfall is under-sizing the value of
capacitor CPVCC. In this case, the normal supply current
drawn through PVCC will discharge CPVCC rapidly before the
third winding drive becomes effective. Depending on the
particular situation, this may result in either several off-on
cycles before proper operation is reached or permanent
relaxation oscillation at the PVCC node.
Resistor RSTART should be selected to yield a worst-case
minimum charging current greater that the maximum rated
LTC4267-1 start-up current to ensure there is enough cur-
rent to charge CPVCC to the PVCC turn-on threshold. RSTART
should also be selected large enough to yield a worst-case
maximum charging current less than the minimum-rated
PVCC supply current, so that in operation, most of the
PVCC current is delivered through the third winding. This
results in the highest possible effi ciency.
Capacitor CPVCC should then be made large enough to avoid
the relaxation oscillation behavior described previously.
This is diffi cult to determine theoretically as it depends on
the particulars of the secondary circuit and load behavior.
Empirical testing is recommended.
The third transformer winding should be designed so
that its output voltage, after accounting for the forward
diode voltage drop, exceeds the maximum PVCC turn-off
threshold. Also, the third winding’s nominal output voltage
should be at least 0.5V below the minimum rated PVCC
clamp voltage to avoid running up against the LTC4267-1
shunt regulator, needlessly wasting power.
PVCC Shunt Regulator
In applications including a third transformer winding,
the internal PVCC shunt regulator serves to protect the
LTC4267-1 switching regulator from overvoltage transients
as the third winding is powering up.
If a third transformer winding is undesirable or unavail-
able, the shunt regulator allows the LTC4267-1 switching
regulator to be powered through a single dropping resistor
from VPORTP as shown in Figure 12. This simplicity comes
at the expense of reduced effi ciency due to static power
dissipation in the RSTART dropping resistor.
The shunt regulator can sink up to 5mA through the PVCC
pin to PGND. The values of RSTART and CPVCC must be
selected for the application to withstand the worst-case
load conditions and drop on PVCC, ensuring that the PVCC
turn-off threshold is not reached. CPVCC should be sized
suffi ciently to handle the switching current needed to drive
NGATE while maintaining minimum switching voltage.
External Preregulator
The circuit in Figure 13 shows a third way to power the
LTC4267-1 switching regulator circuit. An external series
LTC4267-1
24
42671f
virtually all the supply current required by the LTC4267-1
switching regulator. CPVCC should be sized suffi ciently to
handle the switching current needed to drive NGATE while
maintaining minimum switching voltage.
The external preregulator has improved effi ciency over
the simple resistor-shunt regulator method mentioned
previously. RB can be selected so that it provides a small
current necessary to maintain the zener diode voltage and
the maximum possible base current Q1 will encounter. The
actual current needed to power the LTC4267-1 switching
regulator goes through Q1 and PVCC sources current on
an “as-needed” basis. The static current is then limited
only to the current through RB and D1.
Compensating the Main Loop
In an isolated topology, the compensation point is typically
chosen by the components confi gured around the external
error amplifi er. Shown in Figure 14, a series RC network
APPLICATIO S I FOR ATIO
WUUU
Figure 12. Powering the LTC4267-1 Switching
Regulator via the Shunt Regulator
Figure 13. Powering the LTC4267-1 Switching
Regulator with an External Preregulator
710351
17$$
1(/%
1065
71035/
-5$
o
'30.
14&
345"35
$17$$
o
1(/%
'
preregulator consists of a series pass transistor Q1, zener
diode D1, and a bias resistor RB. The preregulator holds
PVCC at 7.6V nominal, well above the maximum rated PVCC
turn-off threshold of 6.8V. Resistor RSTART momentarily
charges the PVCC node up to the PVCC turn-on threshold,
enabling the switching regulator. The voltage on CPVCC
begins to decline as the switching regulator draws its
normal supply current, which exceeds the delivery of
RSTART. After some time, the output voltage approaches
the desired value. By this time, the pass transistor Q1
catches the declining voltage on the PVCC pin, and provides
710351
17$$
1(/%
1065
71035/
-5$
o
'30.
14&
345"35
$17$$
o
1(/%
1(/%
1(/%
2
%
7
3#
'
is connected from the compare voltage of the error am-
plifi er to the error amplifi er output. In PD designs where
transient load response is not critical, replace RZ with a
short. The product of R2 and CC should be suffi ciently large
to ensure stability. When fast settling transient response
is critical, introduce a zero set by RZCC. The PD designer
must ensure that the faster settling response of the output
voltage does not compromise loop stability.
Figure 14. Main Loop Compensation for an Isolated Design
3
3
$$
3;
500150
*40-"503
'
7065
LTC4267-1
25
42671f
In a nonisolated design, the LTC4267-1 incorporates an
internal error amplifi er where the ITH/RUN pin serves as
a compensation point. In a similar manner, a series RC
network can be connected from ITH/RUN to PGND as
shown in Figure 15. CC and RZ are chosen for optimum
load and line transient response.
Auxiliary Power Source
In some applications, it may be desirable to power the
PD from an auxiliary power source such as a wall trans-
former. The auxiliary power can be injected into the PD
at several locations and various trade-offs exist. Power
can be injected at the 3.3V or 5V output of the isolated
power supply with the use of a diode ORing circuit. This
method accesses the internal circuits of the PD after the
isolation barrier and therefore meets the 802.3af isola-
tion safety requirements for the wall transformer jack on
the PD. Power can also be injected into the PD interface
portion of the LTC4267-1. In this case, it is necessary to
ensure the user cannot access the terminals of the wall
transformer jack on the PD since this would compromise
the 802.3af isolation safety requirements.
Figure 16 demonstrates three methods of diode ORing
external power into a PD. Option 1 inserts power before
the LTC4267-1 interface controller while options 2 and
3 bypass the LTC4267-1 interface controller section and
power the switching regulator directly.
If power is inserted before the LTC4267-1 interface con-
troller, it is necessary for the wall transformer to exceed
the LTC4267-1 UVLO turn-on requirement and include a
transient voltage suppressor (TVS) to limit the maximum
voltage to 57V. This option provides input current limit
for the transformer, provides a valid power good signal,
and simplifi es power priority issues. As long as the wall
transformer applies power to the PD before the PSE, it
will take priority and the PSE will not power up the PD
because the wall power will corrupt the 25k signature. If
the PSE is already powering the PD, the wall transformer
power will be in parallel with the PSE. In this case, prior-
ity will be given to the higher supply voltage. If the wall
transformer voltage is higher, the PSE should remove the
line voltage since no current will be drawn from the PSE.
On the other hand, if the wall transformer voltage is lower,
the PSE will continue to supply power to the PD and the
wall transformer will not be used. Proper operation should
occur in either scenario.
APPLICATIO S I FOR ATIO
WUUU
Figure 15. Main Loop Compensation for a Nonisolated Design
-5$
$$3;
*5)36/ 1(/%
'
Selecting the Switching Transistor
With the N-channel power MOSFET driving the primary of
the transformer, the inductance will cause the drain of the
MOSFET to traverse twice the voltage across VPORTP and
PGND. The LTC4267-1 operates with a maximum supply
of – 57V; thus the MOSFET must be rated to handle 114V
or more with suffi cient design margin. Typical transis-
tors have 150V ratings while some manufacturers have
developed 120V rated MOSFETs specifi cally for Power-
over-Ethernet applications.
The NGATE pin of the LTC4267-1 drives the gate of the
N-channel MOSFET. NGATE will traverse a rail-to-rail volt-
age from PGND to PVCC. The designer must ensure the
MOSFET provides a low “ON” resistance when switched
to PVCC as well as ensure the gate of the MOSFET can
handle the PVCC supply voltage.
For high effi ciency applications, select an N-channel
MOSFET with low total gate charge. The lower total gate
charge improves the effi ciency of the NGATE drive circuit
and minimizes the switching current needed to charge
and discharge the gate.
LTC4267-1
26
42671f
Figure 16. Auxiliary Power Source for PD
APPLICATIO S I FOR ATIO
WUUU
39o
39
59o
59
3+ 5
41"3&o
o
41"3&
*40-"5&%
8"--
53"/4'03.&3
501):
710351
015*0/"69*-*"3:108&3*/4&35&%#&'03&-5$1%
015*0/"69*-*"3:108&3*/4&35&%"'5&3-5$1%8*5)4*(/"563&%*4"#-&%
71035/ 1065
1(/%
1(/%
7507
%
4#
%
4."+"
574
$
1(/%
1(/%
$
M'
7
39o
39
59o
59
3+ 5
41"3&o
o
41"3&
*40-"5&%
8"--
53"/4'03.&3
501):
710351
4*(%*4"
-5$
-5$
#3
)%
_
_
o
#3
)%
_
_
o
#3
)%
_
_
o
71035/ 1065
'
%
4#
%
4."+"
574
$
L
%
4#
015*0/"69*-*"3:108&3"11-*&%50-5$1%"/%48*5$)*/(3&(6-"503
39o
39
59o
59
3+ 5
41"3&o
o
41"3&
*40-"5&%
8"--
53"/4'03.&3
501):
7507
710351
-5$
71035/ 1065
%
4#
%
4."+"
574
$
$
M'
7
$
M'
7
#3
)%
_
_
o
#3
)%
_
_
o
#3
)%
_
_
o
L
#44
345"35
$17$$
345"35
$17$$
345"35
$17$$
1(/%
17$$
1(/%
17$$
17$$
LTC4267-1
27
42671f
If auxiliary power is applied directly to the LTC4267-1
switching regulator (bypassing the LTC4267-1 PD inter-
face), a different set of tradeoffs arise. In the confi guration
shown in option 2, the wall transformer does not need
to exceed the LTC4267-1 turn-on UVLO requirement;
however, it is necessary to include diode D9 to prevent
the transformer from applying power to the LTC4267-1
interface controller. The transformer voltage requirement
will be governed by the needs of the onboard switching
regulator. However, power priority issues require more
intervention. If the wall transformer voltage is below
the PSE voltage, then priority will be given to the PSE
power. The LTC4267-1 interface controller will draw power
from the PSE while the transformer will sit unused. This
confi guration is not a problem in a PoE system. On the
other hand, if the wall transformer voltage is higher than
the PSE voltage, the LTC4267-1 switching regulator will
draw power from the transformer. In this situation, it is
necessary to address the issue of power cycling that may
occur if a PSE is present. The PSE will detect the PD and
apply power. If the switcher is being powered by the wall
transformer, then the PD will not meet the minimum load
requirement and the PSE will subsequently remove power.
The PSE will again detect the PD and power cycling will
start. With a transformer voltage above the PSE voltage,
it is necessary to either disable the signature, as shown
in option 2, or install a minimum load on the output of the
LTC4267-1 interface to prevent power cycling.
The third option also applies power directly to the
LTC4267-1 switching regulator, bypassing the LTC4267-1
interface controller and omitting diode D9. With the
diode omitted, the transformer voltage is applied to the
LTC4267-1 interface controller in addition to the switching
regulator. For this reason, it is necessary to ensure that the
transformer maintain the voltage between 38V and 57V
to keep the LTC4267-1 interface controller in its normal
operating range. The third option has the advantage of
automatically disabling the 25k signature resistor when
the external voltage exceeds the PSE voltage.
Power-Up Sequencing the LTC4267-1
The LTC4267-1 consists of two functional cells, the PD
interface and the switching regulator, and the power up
sequencing of these two cells must be carefully considered.
The PD designer should ensure that the switching regulator
does not begin operation until the interface has completed
charging up the load capacitor. This will ensure that the
switcher load current does not compete with the load
capacitor charging current provided by the PD interface
current limit circuit. Overlooking this consideration may
result in slow power supply ramp up, power-up oscillation,
and possibly thermal shutdown.
The LTC4267-1 includes a power good signal in the PD
interface that can be used to indicate to the switching
regulator that the load capacitor is fully charged and ready
to handle the switcher load. Figure 7 shows two examples
of ways the
⎯
P
⎯
W
⎯
R
⎯
G
⎯
D signal can be used to control the
switching regulator. The fi rst example employs an N-chan-
nel MOSFET to drive the ITH/RUN port below the shutdown
threshold (typically 0.28V). The second example drives
PVCC below the PVCC turn-off threshold. Employing the
second example has the added advantage of adding delay
to the switching regulator start-up beyond the time the
power good signal becomes active. The second example
ensures additional timing margin at start-up without the
need for added delay components. In applications where it
is not desirable to utilize the power good signal, suffi cient
timing margin can be achieved with RSTART and CPVCC.
RSTART and CPVCC should be set to a delay of two to three
times longer than the duration needed to charge up C1.
Layout Considerations for the LTC4267-1
The most critical layout considerations for the LTC4267-1
are the placement of the supporting external components
associated with the switching regulator. Effi ciency, stability,
and load transient response can deteriorate without good
layout practices around critical components.
APPLICATIO S I FOR ATIO
WUUU
LTC4267-1
28
42671f
For the LTC4267-1 switching regulator, the current loop
through C1, T1 primary, Q1, and RSENSE must be given
careful layout attention. (Refer to Figure 11.) Because of
the high switching current circulating in this loop, these
components should be placed in close proximity to each
other. In addition, wide copper traces or copper planes
should be used between these components. If vias are
necessary to complete the connectivity of this loop,
placing multiple vias lined perpendicular to the fl ow of
current is essential for minimizing parasitic resistance and
reducing current density. Since the switching frequency
and the power levels are substantial, shielding and high
frequency layout techniques should be employed. A low
current, low impedance alternate connection should be
employed between the PGND pins of the LTC4267-1 and
the PGND side of RSENSE, away from the high current loop.
This Kelvin sensing will ensure an accurate representation
of the sense voltage is measured by the LTC4267-1.
The placement of the feedback resistors R1 and R2 as
well as the compensation capacitor CC is very important
in the accuracy of the output voltage, the stability of the
main control loop, and the load transient response. In
an isolated design application, R1, R2, and CC should be
placed as close as possible to the error amplifi er’s input
with minimum trace lengths and minimum capacitance.
In a nonisolated application, R1, and R2 should be placed
APPLICATIO S I FOR ATIO
WUUU
as close as possible to the VFB pin of the LTC4267-1
and CC should be placed close to the ITH/RUN pin of the
LTC4267-1.
In essence, a tight overall layout of the high current loop
and careful attention to current density will ensure suc-
cessful operation of the LTC4267-1 in a PD.
The PD interface section of the LTC4267-1 is relatively im-
mune to layout problems. Excessive parasitic capacitance
on the RCLASS pin should be avoided. The SIGDISA pin is
adjacent to the VPORTP pin and any coupling, whether resis-
tive or capacitive may inadvertently disable the signature
resistance. To ensure consistent behavior, the SIGDISA
pin should be electrically connected and not left fl oating.
Voltages in a PD can be as large as –57V, so high voltage
layout techniques should be employed.
Electro Static Discharge and Surge Protection
The LTC4267-1 is specifi ed to operate with an absolute
maximum voltage of –100V and is designed to tolerate
brief overvoltage events. However, the pins that interface
to the outside world (primarily VPORTN and VPORTP) can
routinely see peak voltages in excess of 10kV. To protect
the LTC4267-1, it is highly recommended that a transient
voltage suppressor be installed between the diode bridge
and the LTC4267-1 (D3 in Figure 2).
LTC4267-1
29
42671f
TYPICAL APPLICATIO S
U
Class 3 PD with 5V Nonisolated Power Supply
17$$
/("5&
183(%
4&/4&
7'#
*5)36/
710351
3$-"44
4*(%*4"
71035/
-5$
7
L
M'
M'
•
•
$0*-530/*$4
$59
#"4
614
4."+"
7
"
)%
)%
o
o
o7
'30.
%"5"1"*3
o7
'30.
41"3&1"*3
5"
'%$
7
L
L
7
L
L
Q'
7
7
O'
M'
M'
.*/
1(/%
1065
..#5"
L
M'$&3".*$M'5"/5"-6.
5)3&&'$&3".*$4
LTC4267-1
30
42671f
TYPICAL APPLICATIO S
U
Synchronous Class 3 PD with Triple Output Isolated Power Supplies
1
7$$
/("5&
183(%
*
5)
36/
7
'#
7
10351
4*(%*4"
7
1035/
-5$
7
+ 4."+"
1
7$$
L
M'
M'
.*/
1
065
1(/%
M'
O'
•
•
•
•
O'
7"$
14
5"
+)"-0)'+31&-*/5&(3"5&%+"$,
5$0*-$3"'5%"-
516-4&1"
580M'$"1"$*5034*/1"3"--&-
M'"/%M'*/1"3"--&-
M'$&3".*$M'5"/5"-6.
#"4
L
M'
1
7$$
L
7
L
#$9
..#5
7
Q
#"4
L
M'
7
M' M'
M'
M'
M'
L
L
7
"5"
7
"5"
7
"5"
$)"44*4
5
5
1)%-
1)%-
1)%-
#"54-5
L
;3-
7
L
4J%7
4J%7
•
•
3
$-"44
4&/4&
50
1):
50
1):
LTC4267-1
31
42671f
PACKAGE DESCRIPTIO
U
GN16 (SSOP) 0204
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC4267-1
32
42671f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
LT 0207 • PRINTED IN USA
High-Effi ciency Class 3 PD with 3.3V Isolated Power Supply
17$$
/("5&
4&/4&
*5)36/
183(%
7'#
710351
3$-"44
4*(%*4"
71035/
-5$
7
L 7L
17$$
M'
4."+"
..4%
16-4&
1"
..4%
#"4
#"4
..5#"
o7
'30.
%"5"1"*3
o7
'30.
41"3&1"*3
4J
/
17$$
L
17$$
L
L
L
M'
M'
.*/
#
1-"$&4
1065 1(/%
7 Q'
7
7
7
L
L
M'
O'
•
•
•
7Q'
Q'
i:w$"1
7"$
14
5-7
4#.
7
"
$)"44*4
5"
M'$&3".*$M'5"/5"-6.
'$&3".*$M'5"/5"-6.
#"4
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LTC1737 High Power Isolated Flyback Controller Sense Output Voltage Directly from Primary-Side Winding
LTC1871 Wide Input Range, No RSENSE™ Current Mode
Flyback, Boost and SEPIC Controller
Adjustable Switching Frequency, Programmable Undervoltage Lockout,
Optional Burst Mode® Operation at Light Load
LTC3803 Current Mode Flyback DC/DC Controller in ThinSOT™ 200kHz Constant Frequency, Adjustable Slope Compensation, Optimized for
High Input Voltage Applications
LTC3825 Isolate No-Opto Synchronous Flyback Controller with
Wide Input Supply Range
Adjustable Switching Frequency, Programmable Undervoltage Lockout,
Accurate Regulation without Trim, Synchronous for High Effi ciency
LTC4257 IEEE 802.3af PD Interface Controller 100V 400mA Internal Switch, Programmable Classifi cation
LTC4257-1 IEEE 802.3af PD Interface Controller 100V 400mA Internal Switch, Programmable Classifi cation Dual Current Limit
LTC4258 Quad IEEE 802.3af Power over Ethernet Controller DC Disconnect Only, IEEE-Compliant PD Detection and Classifi cation,
Autonomous Operation or I2C™ Control
LTC4259A-1 Quad IEEE 802.3af Power over Ethernet Controller AC or DC Disconnect IEEE-Compliant PD Detection and Classifi cation,
Autonomous Operation or I2C Control
LTC4263 Single IEEE 802.3af Power over Ethernet Controller AC or DC Disconnect IEEE-Compliant PD Detection and Classifi cation,
Autonomous Operation or I2C Control
LTC4267 IEEE 802.3af PD Interface with an Integrated
Switching Regulator
100V 400mA Internal Switch, Programmable Classifi cation, 200kHz Constant
Frequency PWM, Interface and Switcher Optimized for IEEE-Compliant PD
System
Burst Mode is a registered trademark of Linear Technology Corporation. No RSENSE and ThinSOT are trademarks of Linear Technology Corporation.
RELATED PARTS
